From c1b22ede302d6984f84e57716780fce461247e4f Mon Sep 17 00:00:00 2001 From: Fan Yang <93824713+helloeagleyang@users.noreply.github.com> Date: Tue, 6 Sep 2022 12:48:16 +0800 Subject: [PATCH] Add BSP for HPM6750EVK and HPM6750EVKMINI (#6374) * Add CANFD support and correct typos - Added CANFD required fields to can.h - Fixed typos in can.h and can.c - Corrected all the projects affected by the typo - Fixed wrong line-ending in some affected can driver files Signed-off-by: Fan YANG * update * bsp: support boards from hpmicro - Supported HPM6750EVKMINI - Supported HPM6750EVK Signed-off-by: Fan YANG Signed-off-by: Fan YANG Co-authored-by: Meco Man <920369182@qq.com> --- bsp/hpmicro/hpm6750evk/.config | 714 + .../blink_led.OpenOCD.Debug.rttlaunch | 58 + ...umcueclipse.managedbuild.cross.riscv.prefs | 2 + .../.settings/language.settings.xml | 25 + .../org.eclipse.core.resources.prefs | 2 + .../.settings/org.eclipse.core.runtime.prefs | 3 + bsp/hpmicro/hpm6750evk/.settings/projcfg.ini | 19 + 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create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h 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bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld create mode 100644 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bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_acmp_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bacc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bkey_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bmon_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bsec_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_butn_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_can_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_conctl_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmamux_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_exip_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gptmr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_hall_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2c_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_jpeg_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keym_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keyman_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mbx_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mchtmr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_otp_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_sw_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctl_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pmon_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_psec_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qei_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rng_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rtc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tamp_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tsns_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_vad_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_wdg_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c create mode 100644 libcpu/risc-v/hpmicro/SConscript create mode 100644 libcpu/risc-v/hpmicro/context_gcc.S create mode 100644 libcpu/risc-v/hpmicro/cpuport.c create mode 100644 libcpu/risc-v/hpmicro/cpuport.h create mode 100644 libcpu/risc-v/hpmicro/riscv-stackframe.h create mode 100644 libcpu/risc-v/hpmicro/trap_entry_gcc.S diff --git a/bsp/hpmicro/hpm6750evk/.config b/bsp/hpmicro/hpm6750evk/.config new file mode 100644 index 0000000000..fc6c479b23 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/.config @@ -0,0 +1,714 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# CONFIG_RT_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +CONFIG_RT_USING_LEGACY=y +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Sensor libraries +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display libraries +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set + +# +# Timing libraries +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Project libraries +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM6000=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART13 is not set +# CONFIG_BSP_USING_UART14 is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_RTC=y +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_SDXC is not set +# CONFIG_BSP_USING_TOUCH is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_LVGL is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +CONFIG_BSP_USING_DRAM=y +CONFIG_INIT_EXT_RAM_FOR_DATA=y +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_DAO is not set +# CONFIG_BSP_USING_PDM is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_CAN is not set diff --git a/bsp/hpmicro/hpm6750evk/.settings/blink_led.OpenOCD.Debug.rttlaunch b/bsp/hpmicro/hpm6750evk/.settings/blink_led.OpenOCD.Debug.rttlaunch new file mode 100644 index 0000000000..b0ccdd0117 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/.settings/blink_led.OpenOCD.Debug.rttlaunch @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/hpm6750evk/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs b/bsp/hpmicro/hpm6750evk/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs new file mode 100644 index 0000000000..131f98bfbb --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +toolchain.path.512258282=${toolchain_install_path}/RISC-V/RISC-V-GCC-RV32/2022-04-12/bin diff --git a/bsp/hpmicro/hpm6750evk/.settings/language.settings.xml b/bsp/hpmicro/hpm6750evk/.settings/language.settings.xml new file mode 100644 index 0000000000..89463fc038 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/hpm6750evk/.settings/org.eclipse.core.resources.prefs b/bsp/hpmicro/hpm6750evk/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000000..99f26c0203 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/bsp/hpmicro/hpm6750evk/.settings/org.eclipse.core.runtime.prefs b/bsp/hpmicro/hpm6750evk/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 0000000000..9f1acfcfba --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/.settings/projcfg.ini b/bsp/hpmicro/hpm6750evk/.settings/projcfg.ini new file mode 100644 index 0000000000..1ae5ab7322 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/.settings/projcfg.ini @@ -0,0 +1,19 @@ +#RT-Thread Studio Project Configuration +#Thu Feb 17 15:17:36 CST 2022 +cfg_version=v3.0 +board_name=HPM6750EVKMINI +example_name=blink_led +hardware_adapter=FT2232 +project_type=rt-thread +board_base_nano_proj=False +chip_name=HPM6750 +selected_rtt_version=4.0.5 +bsp_version=0.3.0 +os_branch=full +output_project_path=C\:/DevTools/RT-ThreadStudio/workspace +is_base_example_project=True +is_use_scons_build=True +project_base_bsp=true +project_name=blink_led +os_version=4.0.5 +bsp_path=repo/Local/Board_Support_Packages/HPMicro/HPM6750EVKMINI/0.3.0(offline)/hpm6750-rtt-bsp diff --git a/bsp/hpmicro/hpm6750evk/Kconfig b/bsp/hpmicro/hpm6750evk/Kconfig new file mode 100644 index 0000000000..79b160b856 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hpmicro/hpm6750evk/SConscript b/bsp/hpmicro/hpm6750evk/SConscript new file mode 100644 index 0000000000..bb673e4f18 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/SConstruct b/bsp/hpmicro/hpm6750evk/SConstruct new file mode 100644 index 0000000000..3dadc575c0 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6750evk/applications/SConscript b/bsp/hpmicro/hpm6750evk/applications/SConscript new file mode 100644 index 0000000000..a65aa4d855 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/applications/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6750evk/applications/main.c b/bsp/hpmicro/hpm6750evk/applications/main.c new file mode 100644 index 0000000000..b766dd547e --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/applications/main.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2021 hpmicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" + +void thread_entry(void *arg); + + + +int main(void) +{ + + app_init_led_pins(); + + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + + +void thread_entry(void *arg) +{ + while(1){ + app_led_write(0, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(0, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm6750evk/board/Kconfig b/bsp/hpmicro/hpm6750evk/board/Kconfig new file mode 100644 index 0000000000..e506401bb3 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/Kconfig @@ -0,0 +1,379 @@ +menu "Hardware Drivers Config" + +config SOC_HPM6000 + bool + select SOC_SERIES_HPM6000 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_DMA_CHANNEL + int "Set UART0 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART0_TX_DMA_CHANNEL + int "Set UART0 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_DMA_CHANNEL + int "Set UART6 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART6_TX_DMA_CHANNEL + int "Set UART6 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART13 + bool "Enable UART13" + default n + if BSP_USING_UART13 + config BSP_UART13_RX_USING_DMA + bool "Enable UART13 RX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default n + + config BSP_UART13_TX_USING_DMA + bool "Enable UART13 TX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default n + + config BSP_UART13_RX_DMA_CHANNEL + int "Set UART13 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART13_TX_DMA_CHANNEL + int "Set UART13 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART13_RX_BUFSIZE + int "Set UART13 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART13_TX_BUFSIZE + int "Set UART13 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART14 + bool "Enable UART14" + default n + if BSP_USING_UART14 + config BSP_UART14_RX_USING_DMA + bool "Enable UART14 RX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default n + + config BSP_UART14_TX_USING_DMA + bool "Enable UART14 TX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default n + + config BSP_UART14_RX_DMA_CHANNEL + int "Set UART14 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART14_TX_DMA_CHANNEL + int "Set UART14 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART14_RX_BUFSIZE + int "Set UART14 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART14_TX_BUFSIZE + int "Set UART14 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default y + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + + select RT_USING_ETH + if BSP_USING_ETH + choice + prompt "ETH" + config BSP_USING_ETH0 + bool "Enable ETH0" + + config BSP_USING_ETH1 + bool "Enable ETH1" + endchoice + endif + + menuconfig BSP_USING_SDXC + bool "Enable SDXC" + default n + select RT_USING_SDIO if BSP_USING_SDXC + if BSP_USING_SDXC + config BSP_USING_SDXC0 + bool "Enable SDXC0" + default n + + config BSP_USING_SDXC1 + bool "Enable SDXC1" + default y + endif + + menuconfig BSP_USING_TOUCH + bool "Enable touch" + default n + if BSP_USING_TOUCH + config BSP_USING_TOUCH_GT911 + bool "Enable GT911" + default y + + config BSP_USING_TOUCH_FT5406 + bool "Enable FT5406" + default n + endif + + menuconfig BSP_USING_LCD + bool "Enable LCD" + default n + + menuconfig BSP_USING_LVGL + bool "Enable LVGL" + default n + select PKG_USING_LVGL if BSP_USING_LVGL + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + config BSP_USING_GPTMR4 + bool "Enable GPTMR4" + default n + config BSP_USING_GPTMR5 + bool "Enable GPTMR5" + default n + config BSP_USING_GPTMR6 + bool "Enable GPTMR6" + default n + config BSP_USING_GPTMR7 + bool "Enable GPTMR7" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + select RT_USING_I2C if BSP_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + endif + + menuconfig BSP_USING_DRAM + bool "Enable DRAM" + default y + menuconfig INIT_EXT_RAM_FOR_DATA + bool "INIT_EXT_RAM_FOR_DATA" + default y + + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select PKG_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + + menuconfig BSP_USING_DAO + bool "Enable Audio DAO play" + default n + select RT_USING_AUDIO if BSP_USING_DAO + + menuconfig BSP_USING_PDM + bool "Enable Audio PDM record" + default n + select RT_USING_AUDIO if BSP_USING_PDM + + menuconfig BSP_USING_I2S + bool "Enable Audio I2S device" + default n + select RT_USING_AUDIO if BSP_USING_I2S + if BSP_USING_I2S + config BSP_USING_I2S0 + bool "Enable I2S0" + default y + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB Host" + default n + endif + + + menuconfig BSP_USING_WDG + bool "Enable Watchdog" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default n + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + config BSP_USING_WDG2 + bool "Enable WDG2" + default n + config BSP_USING_WDG3 + bool "Enable WDG3" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN if BSP_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN0 + bool "Enable CAN0" + default n + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + config BSP_USING_CAN2 + bool "Enable CAN2" + default n + config BSP_USING_CAN3 + bool "Enable CAN3" + default n + endif +endmenu + + + +endmenu diff --git a/bsp/hpmicro/hpm6750evk/board/SConscript b/bsp/hpmicro/hpm6750evk/board/SConscript new file mode 100644 index 0000000000..b0557f0945 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/SConscript @@ -0,0 +1,20 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + eth_phy_port.c + fal_flash_port.c + hpm_sgtl5000.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D45', 'HPM6750'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6750evk/board/board.c b/bsp/hpmicro/hpm6750evk/board/board.c new file mode 100644 index 0000000000..8b0de6ffd8 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/board.c @@ -0,0 +1,1026 @@ +/* + * Copyright (c) 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_lcdc_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_debug_console.h" +#include "hpm_dram_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_sdxc_drv.h" +#include "hpm_pwm_drv.h" +#include "hpm_trgm_drv.h" +#include "hpm_pllctl_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if BOARD_CONSOLE_TYPE == console_type_uart + console_config_t cfg; + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t) BOARD_CONSOLE_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_BAUDRATE; + + init_uart_pins((UART_Type *) cfg.base); + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while(1); +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu1:\t\t %dHz\n", clock_get_frequency(clock_cpu1)); + printf("axi0:\t\t %dHz\n", clock_get_frequency(clock_axi0)); + printf("axi1:\t\t %dHz\n", clock_get_frequency(clock_axi1)); + printf("axi2:\t\t %dHz\n", clock_get_frequency(clock_axi2)); + printf("ahb:\t\t %dHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); + printf("mchtmr1:\t %dHz\n", clock_get_frequency(clock_mchtmr1)); + printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); + printf("xpi1:\t\t %dHz\n", clock_get_frequency(clock_xpi1)); + printf("dram:\t\t %dHz\n", clock_get_frequency(clock_dram)); + printf("display:\t %dHz\n", clock_get_frequency(clock_display)); + printf("cam0:\t\t %dHz\n", clock_get_frequency(clock_camera0)); + printf("cam1:\t\t %dHz\n", clock_get_frequency(clock_camera1)); + printf("jpeg:\t\t %dHz\n", clock_get_frequency(clock_jpeg)); + printf("pdma:\t\t %dHz\n", clock_get_frequency(clock_pdma)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + init_uart_pins(ptr); +} + +void board_init_ahb(void) +{ + clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ +} + +void board_print_banner(void) +{ + const uint8_t banner[] = {"\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n"}; + printf("%s", banner); +} + +static void board_turnoff_rgb_led(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; + + HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +void board_init(void) +{ + board_turnoff_rgb_led(); + board_init_clock(); + board_init_console(); + board_init_pmp(); + board_init_ahb(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_sdram_pins(void) +{ + init_sdram_pins(); +} + +uint32_t board_init_dram_clock(void) +{ + clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ + /* clock_set_source_divider(clock_dram, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ + + return clock_get_frequency(clock_dram); +} + +void board_power_cycle_lcd(void) +{ + /* turn off backlight */ + gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0); + + board_delay_ms(150); + /* power recycle */ + gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0); + board_delay_ms(150); + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1); + board_delay_ms(150); + + /* turn on backlight */ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); + +} + +void board_init_lcd(void) +{ + board_init_lcd_clock(); + init_lcd_pins(BOARD_LCD_BASE); + + board_power_cycle_lcd(); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + init_i2c_pins_as_gpio(ptr); + if (ptr == BOARD_CAP_I2C_BASE) { + gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN); + gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); + if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { + printf("CLK is low, please power cycle the board\n"); + while (1) {} + } + if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); + while (1) { + for (uint32_t i = 0; i < 9; i++) { + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0); + board_delay_ms(10); + } + board_delay_ms(100); + } + printf("I2C bus is cleared\n"); + } +} + +void board_init_i2c(I2C_Type *ptr) +{ + hpm_stat_t stat; + uint32_t freq; + i2c_config_t config; + + board_i2c_bus_clear(ptr); + + init_i2c_pins(ptr); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); + stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE); + while (1) {} + } +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART6) { + clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart6); + } else if (ptr == HPM_UART13) { + clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart13); + } else if (ptr == HPM_UART14) { + clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart14); + } else { + /* Not supported */ + } + return freq; +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + /* SPI2 clock configure */ + clock_add_to_group(clock_spi2, 0); + clock_set_source_divider(clock_spi2, clk_src_osc24m, 1U); + + return clock_get_frequency(clock_spi2); + } + return 0; +} + +void board_init_cap_touch(void) +{ + init_cap_pins(); + gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0); + gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + + board_delay_ms(1); + gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); + + gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); + board_init_i2c(BOARD_CAP_I2C_BASE); +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); +} + +void board_led_toggle(void) +{ +#ifdef BOARD_LED_TOGGLE_RGB + static uint8_t i; + gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_R_GPIO_PIN); + i++; + i = i % 3; +#else + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +#endif +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_init_cam_pins(void) +{ + init_cam_pins(); + /* enable cam RST pin out with high level */ + gpio_set_pin_output_with_initial(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, 1); +} + +void board_write_cam_rst(uint8_t state) +{ + gpio_write_pin(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, state); + +} + +void board_init_usb_pins(void) +{ + /* set pull-up for USBx OC pins and ID pins */ + init_usb_pins(); + + /* configure USBx ID pins as input function */ + gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); + gpio_set_pin_input(BOARD_USB1_ID_PORT, BOARD_USB1_ID_GPIO_INDEX, BOARD_USB1_ID_GPIO_PIN); + + /* configure USBx OC Flag pins as input function */ + gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN); + gpio_set_pin_input(BOARD_USB1_OC_PORT, BOARD_USB1_OC_GPIO_INDEX, BOARD_USB1_OC_GPIO_PIN); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ +} + +void board_init_pmp(void) +{ + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + + uint32_t start_addr = (uint32_t) __noncacheable_start__; + uint32_t end_addr = (uint32_t) __noncacheable_end__; + uint32_t length = end_addr - start_addr; + + if (length == 0) { + return; + } + + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + + pmp_entry_t pmp_entry[1]; + pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + + pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + hpm_core_clock = cpu0_freq; + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1); + } + + /* Add most Clocks to group 0 */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_axi0, 0); + clock_add_to_group(clock_axi1, 0); + clock_add_to_group(clock_axi2, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_xpi1, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_gptmr4, 0); + clock_add_to_group(clock_gptmr5, 0); + clock_add_to_group(clock_gptmr6, 0); + clock_add_to_group(clock_gptmr7, 0); + clock_add_to_group(clock_uart0, 0); + clock_add_to_group(clock_uart1, 0); + clock_add_to_group(clock_uart2, 0); + clock_add_to_group(clock_uart3, 0); + clock_add_to_group(clock_uart13, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_can2, 0); + clock_add_to_group(clock_can3, 0); + clock_add_to_group(clock_display, 0); + clock_add_to_group(clock_sdxc0, 0); + clock_add_to_group(clock_sdxc1, 0); + clock_add_to_group(clock_camera0, 0); + clock_add_to_group(clock_camera1, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_ref0, 0); + clock_add_to_group(clock_ref1, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_eth0, 0); + clock_add_to_group(clock_eth1, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_ram0, 0); + clock_add_to_group(clock_ram1, 0); + clock_add_to_group(clock_usb0, 0); + clock_add_to_group(clock_usb1, 0); + clock_add_to_group(clock_jpeg, 0); + clock_add_to_group(clock_pdma, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_mot1, 0); + clock_add_to_group(clock_mot2, 0); + clock_add_to_group(clock_mot3, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_dao, 0); + clock_add_to_group(clock_msyn, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); + + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_adc2, 0); + clock_add_to_group(clock_adc3, 0); + + clock_add_to_group(clock_i2s0, 0); + clock_add_to_group(clock_i2s1, 0); + clock_add_to_group(clock_i2s2, 0); + clock_add_to_group(clock_i2s3, 0); + + /* Add the CPU1 clock to Group1 */ + clock_add_to_group(clock_mchtmr1, 1); + clock_add_to_group(clock_mbx1, 1); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { + printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); + while(1); + } + + clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); + clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); +} + +uint32_t board_init_cam_clock(CAM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAM0) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_camera0); + } else if (ptr == HPM_CAM1) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_camera1); + } else { + /* Invalid camera instance */ + } + return freq; +} + +uint32_t board_init_lcd_clock(void) +{ + uint32_t freq; + clock_add_to_group(clock_display, 0); + /* Configure LCDC clock to 29.7MHz */ + clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U); + freq = clock_get_frequency(clock_display); + return freq; +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr) +{ + uint32_t freq = 0; + switch ((uint32_t) ptr) { + case HPM_ADC0_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc0); + break; + case HPM_ADC1_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc1); + break; + case HPM_ADC2_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc2); + break; + default: + /* Invalid ADC instance */ + break; + } + + return freq; +} + +uint32_t board_init_dao_clock(void) +{ + clock_add_to_group(clock_dao, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_dao); +} + +uint32_t board_init_pdm_clock(void) +{ + clock_add_to_group(clock_pdm, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_pdm); +} + +uint32_t board_init_i2s_clock(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_i2s0); + } + return 0; +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_ADC3) { + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} + +void board_init_can(CAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(CAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAN0) { + /* Set the CAN0 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_CAN1) { + /* Set the CAN1 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can1); + } else if (ptr == HPM_CAN2) { + /* Set the CAN2 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can2); + } else if (ptr == HPM_CAN3) { + /* Set the CAN3 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can3); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, 0); + clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr0); + } + else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, 0); + clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr1); + } + else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, 0); + clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr2); + } + else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, 0); + clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr3); + } + else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, 0); + clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr4); + } + else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, 0); + clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr5); + } + else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, 0); + clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr6); + } + else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, 0); + clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr7); + } + else { + /* Invalid instance */ + } +} + + +/* + * this function will be called during startup to initialize external memory for data use + */ +void _init_ext_ram(void) +{ + uint32_t dram_clk_in_hz; + board_init_sdram_pins(); + dram_clk_in_hz = board_init_dram_clock(); + + dram_config_t config = {0}; + dram_sdram_config_t sdram_config = {0}; + + dram_default_config(HPM_DRAM, &config); + config.dqs = DRAM_DQS_INTERNAL; + dram_init(HPM_DRAM, &config); + + sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.prescaler = 0x3; + sdram_config.burst_len_in_byte = 8; + sdram_config.auto_refresh_count_in_one_burst = 1; + sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + + sdram_config.precharge_to_act_in_ns = 18; /* Trp */ + sdram_config.act_to_rw_in_ns = 18; /* Trcd */ + sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */ + sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */ + sdram_config.cke_off_in_ns = 42; /* Trcd */ + sdram_config.act_to_precharge_in_ns = 42; /* Tras */ + + sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */ + sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ + sdram_config.act_to_act_in_ns = 12; /* Trrd */ + sdram_config.idle_timeout_in_ns = 6; + sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + + sdram_config.cs = BOARD_SDRAM_CS; + sdram_config.base_address = BOARD_SDRAM_ADDRESS; + sdram_config.size_in_byte = BOARD_SDRAM_SIZE; + sdram_config.port_size = BOARD_SDRAM_PORT_SIZE; + sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; + sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; + sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; + sdram_config.delay_cell_value = 29; + + dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); +} + + +void board_init_sd_pins(SDXC_Type *ptr) +{ + init_sdxc_pins(ptr, false); +} + + +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) +{ + uint32_t actual_freq = 0; + do { + if (ptr != HPM_SDXC1) { + break; + } + clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; + sdxc_enable_sd_clock(ptr, false); + /* Configure the clock below 400KHz for the identification state */ + if (freq <= 400000UL) { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63); + } + /* configure the clock to 24MHz for the SDR12/Default speed */ + else if (freq <= 25000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); + } + /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ + else if (freq <= 50000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8); + } + /* Configure the clock to 100MHz for the SDR50 */ + else if (freq <= 100000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4); + } + /* Configure the clock to 166MHz for SDR104/HS200/HS400 */ + else if (freq <= 208000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2); + } + /* For other unsupported clock ranges, configure the clock to 24MHz */ + else { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); + } + sdxc_enable_sd_clock(ptr, true); + actual_freq = clock_get_frequency(sdxc_clk); + } while (false); + + return actual_freq; +} + +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) +{ + /* This feature is not supported */ +} + +bool board_sd_detect_card(SDXC_Type *ptr) +{ + return ((BOARD_APP_SDCARD_CDN_GPIO_CTRL->DI[GPIO_DI_GPIOD].VALUE & (1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN)) == 0U); +} + +static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index) +{ + pwm_cmp_config_t cmp_config = {0}; + pwm_output_channel_t ch_config = {0}; + + pwm_stop_counter(ptr); + pwm_get_default_cmp_config(ptr, &cmp_config); + pwm_get_default_output_channel_config(ptr, &ch_config); + + pwm_set_reload(ptr, 0, 0xF); + pwm_set_start_count(ptr, 0, 0); + + cmp_config.mode = pwm_cmp_mode_output_compare; + cmp_config.cmp = 0x10; + cmp_config.update_trigger = pwm_shadow_register_update_on_modify; + pwm_config_cmp(ptr, cmp_index, &cmp_config); + + ch_config.cmp_start_index = cmp_index; + ch_config.cmp_end_index = cmp_index; + ch_config.invert_output = false; + + pwm_config_output_channel(ptr, pin, &ch_config); +} + +void board_init_rgb_pwm_pins(void) +{ + trgm_output_t config = {0}; + board_turnoff_rgb_led(); + + set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_OUT, BOARD_RED_PWM_CMP); + set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT, BOARD_GREEN_PWM_CMP); + set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT, BOARD_BLUE_PWM_CMP); + + init_rgb_pwm_pins(); + + config.type = 0; + config.invert = false; + + /* Red: TRGM1 P1 */ + config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH8REF; + trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT1, &config); + + /* Green: TRGM0 P6 */ + config.input = HPM_TRGM0_INPUT_SRC_PWM0_CH8REF; + trgm_output_config(HPM_TRGM0, TRGM_TRGOCFG_TRGM_OUT6, &config); + + /* Blue: TRGM1 P3 */ + config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH9REF; + trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT3, &config); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + trgm_disable_io_output(HPM_TRGM1, 1 << 1); + break; + case BOARD_RGB_GREEN: + trgm_disable_io_output(HPM_TRGM0, 1 << 6); + break; + case BOARD_RGB_BLUE: + trgm_disable_io_output(HPM_TRGM1, 1 << 3); + break; + default: + while (1) { + ; + } + } +} + +void board_enable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + trgm_enable_io_output(HPM_TRGM1, 1 << 1); + break; + case BOARD_RGB_GREEN: + trgm_enable_io_output(HPM_TRGM0, 1 << 6); + break; + case BOARD_RGB_BLUE: + trgm_enable_io_output(HPM_TRGM1, 1 << 3); + break; + default: + while (1) { + ; + } + } +} + +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) +{ + /* set clock source */ + if (ptr == HPM_ENET0) { + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ + clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */ + } else if (ptr == HPM_ENET1) { + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */ + clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */ + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) +{ + if (internal == false) { + return status_success; + } + /* Configure Enet clock to output reference clock */ + if (ptr == HPM_ENET0) { + /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */ + clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); + } else if (ptr == HPM_ENET1) { + /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */ + clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */ + } else { + return status_invalid_argument; + } + return status_success; +} + +void board_init_adc12_pins(void) +{ + init_adc12_pins(); +} + +void board_init_adc16_pins(void) +{ + init_adc16_pins(); +} + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr) +{ + init_enet_pins(ptr); + + if (ptr == HPM_ENET0) { + gpio_set_pin_output_with_initial(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0); + } else if (ptr == HPM_ENET1) { + gpio_set_pin_output_with_initial(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 1); + } else if (ptr == HPM_ENET1) { + gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1); + } else { + return status_invalid_argument; + } + + return status_success; +} diff --git a/bsp/hpmicro/hpm6750evk/board/board.h b/bsp/hpmicro/hpm6750evk/board/board.h new file mode 100644 index 0000000000..fefeb8352f --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/board.h @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" + +#define BOARD_NAME "hpm6750evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +/* uart section */ +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART0 +#define BOARD_APP_UART_IRQ IRQn_UART0 +#else +#ifndef BOARD_APP_UART_IRQ +#warning no IRQ specified for applicaiton uart +#endif +#endif + +/* uart rx idle demo section */ +#define BOARD_UART_IDLE HPM_UART13 +#define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART13_RX + +#define BOARD_UART_IDLE_TRGM HPM_TRGM2 +#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 +#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI + +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart0 + +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE console_type_uart +#endif + +#if BOARD_CONSOLE_TYPE == console_type_uart +#ifndef BOARD_CONSOLE_BASE +#if BOARD_RUNNING_CORE == HPM_CORE0 +#define BOARD_CONSOLE_BASE HPM_UART0 +#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#else +#define BOARD_CONSOLE_BASE HPM_UART13 +#define BOARD_CONSOLE_CLK_NAME clock_uart13 +#endif +#endif +#define BOARD_CONSOLE_BAUDRATE (115200UL) +#endif + + +#define BOARD_FREEMASTER_UART_BASE HPM_UART0 +#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 +#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 + +/* sdram section */ +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32*SIZE_1MB) +#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_32_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) + +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (16 << 20) + +/* lcd section */ +#define BOARD_LCD_BASE HPM_LCDC +#define BOARD_LCD_IRQ IRQn_LCDC_D0 +#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_POWER_GPIO_PIN 16 +#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 +#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 + +#define BOARD_CAM_I2C_BASE HPM_I2C0 +#define BOARD_CAM_I2C_CLK_NAME clock_i2c0 +#define BOARD_SUPPORT_CAM_RESET +#define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 +#define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOY +#define BOARD_CAM_RST_GPIO_PIN 5 + +#define BOARD_CAP_I2C_BASE (HPM_I2C0) +#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 +#define BOARD_CAP_RST_GPIO (HPM_GPIO0) +#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_RST_GPIO_PIN (9) +#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) +#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_INTR_GPIO_PIN (8) +#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOZ) +#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) +#define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOZ) +#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR4 +#define BOARD_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_GPTMR_CHANNEL 1 +#define BOARD_GPTMR_PWM HPM_GPTMR3 +#define BOARD_GPTMR_PWM_CHANNEL 1 + +/* gpio section */ +#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_R_GPIO_PIN 11 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_G_GPIO_PIN 12 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_B_GPIO_PIN 13 + +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 + +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_LED_GPIO_PIN 12 +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +#define BOARD_LED_TOGGLE_RGB 1 + +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ +#define BOARD_APP_GPIO_PIN 2 + +/* pinmux section */ +#define USING_GPIO0_FOR_GPIOZ +#ifndef USING_GPIO0_FOR_GPIOZ +#define BOARD_APP_GPIO_CTRL HPM_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#else +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#endif + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI2 +#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) +#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX +#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX +#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 + + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* lcd section */ +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH (800) +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT (480) +#endif + +/* pdma section */ +#define BOARD_PDMA_BASE HPM_PDMA + +/* i2s section */ +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_DATA_LINE (2U) +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 + +/* enet section */ +#define BOARD_ENET0_RST_GPIO HPM_GPIO0 +#define BOARD_ENET0_RST_GPIO_INDEX GPIO_DO_GPIOF +#define BOARD_ENET0_RST_GPIO_PIN (0U) +#define BOARD_ENET0_INF enet_inf_rgmii +#define BOARD_ENET0 HPM_ENET0 +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (21U) +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) + +#define BOARD_ENET1_RST_GPIO HPM_GPIO0 +#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE +#define BOARD_ENET1_RST_GPIO_PIN (26U) +#define BOARD_ENET1_INF enet_inf_rmii +#define BOARD_ENET1 HPM_ENET1 +#define BOARD_ENET1_INT_REF_CLK (1U) +#define BOARD_ENET1_PTP_CLOCK (clock_ptp1) + +/* ADC section */ +#define BOARD_APP_ADC12_NAME "ADC0" +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC12_CH (11U) + +#define BOARD_APP_ADC16_NAME "ADC3" +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC16_CH (2U) + +#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) +#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES (192U) +#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) +#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 +#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 +#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 +#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 +#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_CAN0 +#define BOARD_APP_CAN_IRQn IRQn_CAN0 + + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR7) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR7) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) + +/* SDXC section */ +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_CDN_GPIO_CTRL (HPM_GPIO0) +#define BOARD_APP_SDCARD_CDN_GPIO_PIN (15UL) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) + +/* USB section */ +#define BOARD_USB0_ID_PORT (HPM_GPIO0) +#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) +#define BOARD_USB0_ID_GPIO_PIN (10) + +#define BOARD_USB0_OC_PORT (HPM_GPIO0) +#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) +#define BOARD_USB0_OC_GPIO_PIN (8) + +#define BOARD_USB1_ID_PORT (HPM_GPIO0) +#define BOARD_USB1_ID_GPIO_INDEX (GPIO_DO_GPIOF) +#define BOARD_USB1_ID_GPIO_PIN (7) + +#define BOARD_USB1_OC_PORT (HPM_GPIO0) +#define BOARD_USB1_OC_GPIO_INDEX (GPIO_DI_GPIOF) +#define BOARD_USB1_OC_GPIO_PIN (5) + +/*BLDC pwm*/ + +/*PWM define*/ +#define BOARD_BLDCPWM HPM_PWM2 +#define BOARD_BLDC_UH_PWM_OUTPIN (0U) +#define BOARD_BLDC_UL_PWM_OUTPIN (1U) +#define BOARD_BLDC_VH_PWM_OUTPIN (2U) +#define BOARD_BLDC_VL_PWM_OUTPIN (3U) +#define BOARD_BLDC_WH_PWM_OUTPIN (4U) +#define BOARD_BLDC_WL_PWM_OUTPIN (5U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM2 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) + +/*HALL define*/ + +#define BOARD_BLDC_HALL_BASE HPM_HALL2 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM2 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL2 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) + + + +/*QEI*/ + +#define BOARD_BLDC_QEI_BASE HPM_QEI2 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI2 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM2 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +/*Timer define*/ + +#define BOARD_TMR_1MS HPM_GPTMR2 +#define BOARD_TMR_1MS_CH 0 +#define BOARD_TMR_1MS_CMP 0 +#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 +#define BOARD_TMR_1MS_RELOAD (100000U) + +#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS +#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH +#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP +#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ +#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD +#define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (7U) +#define BOARD_BLDC_ADC_CH_V (10U) +#define BOARD_BLDC_ADC_CH_W (11U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM2 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot2 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_TRGM HPM_TRGM2 + +/* RGB LED Section */ +#define BOARD_RED_PWM_IRQ IRQn_PWM1 +#define BOARD_RED_PWM HPM_PWM1 +#define BOARD_RED_PWM_OUT 8 +#define BOARD_RED_PWM_CMP 8 +#define BOARD_RED_PWM_CMP_INITIAL_ZERO true +#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_GREEN_PWM_IRQ IRQn_PWM0 +#define BOARD_GREEN_PWM HPM_PWM0 +#define BOARD_GREEN_PWM_OUT 8 +#define BOARD_GREEN_PWM_CMP 8 +#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 + +#define BOARD_BLUE_PWM_IRQ IRQn_PWM1 +#define BOARD_BLUE_PWM HPM_PWM1 +#define BOARD_BLUE_PWM_OUT 9 +#define BOARD_BLUE_PWM_CMP 9 +#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_RGB_RED 0 +#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) +#define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) + +#define BOARD_CPU_FREQ (816000000UL) + +#define BOARD_APP_DISPLAY_CLOCK clock_display + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); + +void board_init_uart(UART_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_lcd(void); + +void board_init_can(CAN_Type *ptr); + +uint32_t board_init_dram_clock(void); + +void board_init_sdram_pins(void); +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_led_pins(void); + +/* cap touch */ +void board_init_cap_touch(void); + +void board_led_write(uint8_t state); +void board_led_toggle(void); + +void board_fpga_power_enable(void); + +void board_init_cam_pins(void); +void board_write_cam_rst(uint8_t state); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); + +/* Initialize the UART clock */ +uint32_t board_init_uart_clock(UART_Type *ptr); + +/* Initialize the CAM(camera) dot clock */ +uint32_t board_init_cam_clock(CAM_Type *ptr); + +/* Initialize the LCD pixel clock */ +uint32_t board_init_lcd_clock(void); + +uint32_t board_init_spi_clock(SPI_Type *ptr); + +uint32_t board_init_adc12_clock(ADC12_Type *ptr); + +uint32_t board_init_adc16_clock(ADC16_Type *ptr); + +uint32_t board_init_can_clock(CAN_Type *ptr); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); +uint32_t board_init_i2s_clock(I2S_Type *ptr); +uint32_t board_init_pdm_clock(void); +uint32_t board_init_dao_clock(void); + +void board_init_sd_pins(SDXC_Type *ptr); +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); +bool board_sd_detect_card(SDXC_Type *ptr); + +void board_init_adc12_pins(void); +void board_init_adc16_pins(void); + +void board_init_usb_pins(void); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); + +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); + +void board_delay_ms(uint32_t ms); + +void board_timer_create(uint32_t ms, board_timer_cb cb); + +void board_init_rgb_pwm_pins(void); +void board_enable_output_rgb_led(uint8_t color); +void board_disable_output_rgb_led(uint8_t color); + +/* + * Keep mchtmr clock on low power mode + */ +void board_ungate_mchtmr_at_lp_mode(void); + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/boards/hpm6750evk.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/boards/hpm6750evk.cfg new file mode 100644 index 0000000000..9f15d4c2ec --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/boards/hpm6750evk.cfg @@ -0,0 +1,345 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3040000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +proc init_sdram { } { +# configure dram frequency +# 133Mhz pll1_clk0: 266Mhz divide by 2 + #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x201 +# 166Mhz pll2_clk0: 333Mhz divide by 2 + $::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x401 + # PC01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040208 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040200 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB31 + $::_TARGET0 riscv dmi_write 0x39 0xF40401F8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB30 + $::_TARGET0 riscv dmi_write 0x39 0xF40401F0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB29 + $::_TARGET0 riscv dmi_write 0x39 0xF40401E8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB28 + $::_TARGET0 riscv dmi_write 0x39 0xF40401E0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB27 + $::_TARGET0 riscv dmi_write 0x39 0xF40401D8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB26 + $::_TARGET0 riscv dmi_write 0x39 0xF40401D0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB25 + $::_TARGET0 riscv dmi_write 0x39 0xF40401C8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB24 + $::_TARGET0 riscv dmi_write 0x39 0xF40401C0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB23 + $::_TARGET0 riscv dmi_write 0x39 0xF40401B8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB22 + $::_TARGET0 riscv dmi_write 0x39 0xF40401B0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB21 + $::_TARGET0 riscv dmi_write 0x39 0xF40401A8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB20 + $::_TARGET0 riscv dmi_write 0x39 0xF40401A0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040198 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040190 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PD13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040368 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040360 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040350 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040348 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040340 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040338 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040330 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040328 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040320 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040318 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040310 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040308 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040300 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC29 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC28 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC27 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC22 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC21 + $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC17 + $::_TARGET0 riscv dmi_write 0x39 0xF4040288 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC15 + $::_TARGET0 riscv dmi_write 0x39 0xF4040278 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040260 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC11 + $::_TARGET0 riscv dmi_write 0x39 0xF4040258 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040250 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040248 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040240 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040238 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040230 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040228 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040220 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC14 + $::_TARGET0 riscv dmi_write 0x39 0xF4040270 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040268 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC16 + # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 + $::_TARGET0 riscv dmi_write 0x3C 0x1000C + # PC26 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC25 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040298 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040290 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC23 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC24 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC30 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC31 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040210 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040218 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # dramc configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + sleep 10 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + $::_TARGET0 riscv dmi_write 0x39 0xF3050008 + $::_TARGET0 riscv dmi_write 0x3C 0x30524 + $::_TARGET0 riscv dmi_write 0x39 0xF305000C + $::_TARGET0 riscv dmi_write 0x3C 0x6030524 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x10000000 + + $::_TARGET0 riscv dmi_write 0x39 0xF3050010 + $::_TARGET0 riscv dmi_write 0x3C 0x4000001b + $::_TARGET0 riscv dmi_write 0x39 0xF3050014 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3050040 + $::_TARGET0 riscv dmi_write 0x3C 0xf32 + + # 133Mhz configuration + #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + # 166Mhz configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e33 + + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020300 + + # config delay cell + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x3b + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x203b + + $::_TARGET0 riscv dmi_write 0x39 0xF3050094 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3050098 + $::_TARGET0 riscv dmi_write 0x3C 0 + + # precharge all + $::_TARGET0 riscv dmi_write 0x39 0xF3050090 + $::_TARGET0 riscv dmi_write 0x3C 0x40000000 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + # auto refresh + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + # set mode + $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 + $::_TARGET0 riscv dmi_write 0x3C 0x33 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020301 + echo "SDRAM has been initialized" +} + +$_TARGET0 configure -event reset-init { + init_clock + init_sdram +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 0000000000..b9ae112104 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 0000000000..580d98ef85 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 0000000000..4fb0fba2e7 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 0000000000..fd8f04428c --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 0000000000..e9d6e6d698 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-csr.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-csr.cfg new file mode 100644 index 0000000000..c053c1d16d --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-csr.cfg @@ -0,0 +1 @@ +riscv expose_csrs 262,774,1984-2005,2015-2017,2048,2057,2059,2060,2500-2505,2509,2511,2513-2516,2528,2531-2534 diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg new file mode 100644 index 0000000000..3a0460204f --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg @@ -0,0 +1,38 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6750 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +set _TARGET1 $_CHIP.cpu1 +target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 + +proc release_core1 {} { + # set start point for core1 + $::_TARGET0 riscv dmi_write 0x39 0xF4002C08 + $::_TARGET0 riscv dmi_write 0x3C 0x20016284 + + # set boot flag for core1 + $::_TARGET0 riscv dmi_write 0x39 0xF4002C0C + $::_TARGET0 riscv dmi_write 0x3C 0xC1BEF1A9 + + # release core1 + $::_TARGET0 riscv dmi_write 0x39 0xF4002C00 + $::_TARGET0 riscv dmi_write 0x3C 0x1000 +} + +$_TARGET1 configure -event reset-deassert-pre release_core1 +$_TARGET1 configure -event examine-start release_core1 +$_TARGET1 configure -event examine-end { + $::_TARGET1 arp_examine +} + +$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x04000 -work-area-backup 0 diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg new file mode 100644 index 0000000000..8e2bbe5f19 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg @@ -0,0 +1,13 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6750 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c new file mode 100644 index 0000000000..e229bf41d8 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.c @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-01-11 hpmicro First version + */ + +#include "rtthread.h" + +#ifdef RT_USING_PHY +#include +#include +#include "hpm_enet_drv.h" +#include "eth_phy_port.h" +#include "hpm_soc.h" +#include "netif/ethernetif.h" +#include "board.h" + +typedef struct +{ + char *mdio_name; + ENET_Type *instance; + struct eth_device *eth_dev; + phy_device_t *phy_dev; + struct rt_mdio_bus *mdio_bus; +} eth_phy_handle_t; + +typedef struct +{ + uint8_t phy_handle_cnt; + eth_phy_handle_t **phy_handle; +} eth_phy_monitor_handle_t; + +#ifdef BSP_USING_ETH0 +extern struct eth_device eth0_dev; +static struct rt_mdio_bus mdio0_bus; +static phy_device_t phy0_dev; +static uint8_t phy0_reg_list[]= {PHY0_REG_LIST}; + +static eth_phy_handle_t eth0_phy_handle = +{ + .instance = HPM_ENET0, + .eth_dev = ð0_dev, + .phy_dev = &phy0_dev, + .mdio_name = "MDIO0", + .mdio_bus = &mdio0_bus, +}; +#endif + +#ifdef BSP_USING_ETH1 +extern struct eth_device eth1_dev; +static struct rt_mdio_bus mdio1_bus; +static phy_device_t phy1_dev; +static uint8_t phy1_reg_list[]= {PHY1_REG_LIST}; + +static eth_phy_handle_t eth1_phy_handle = +{ + .instance = HPM_ENET1, + .eth_dev = ð1_dev, + .phy_dev = &phy1_dev, + .mdio_name = "MDIO1", + .mdio_bus = &mdio1_bus, +}; +#endif + +static eth_phy_handle_t *s_gphys[] = +{ +#ifdef BSP_USING_ETH0 +ð0_phy_handle, +#endif + +#ifdef BSP_USING_ETH1 +ð1_phy_handle +#endif +}; + +static uint8_t *s_gphy_reg_list[] = +{ +#ifdef BSP_USING_ETH0 +phy0_reg_list, +#endif + +#ifdef BSP_USING_ETH1 +phy1_reg_list, +#endif +}; + +eth_phy_monitor_handle_t phy_monitor_handle = +{ + .phy_handle_cnt = ARRAY_SIZE(s_gphys), + .phy_handle = s_gphys +}; + +static struct rt_phy_ops phy_ops; + +static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) +{ + return PHY_STATUS_OK; +} + +static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); + + return size; +} + +static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, *(uint16_t *)data); + + return size; +} + +static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) +{ + uint16_t reg_status; + + reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]); + + #if PHY_AUTO_NEGO + reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK; + *status = reg_status ? RT_TRUE : RT_FALSE; + + #else + reg_status &= PHY_LINKED_STATUS_MASK; + *status = reg_status ? RT_TRUE : RT_FALSE; + #endif + + return PHY_STATUS_OK; +} + +static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) +{ + uint16_t reg_status; + + reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]); +#if RGMII + if (PHY_STATUS_SPEED_1000M(reg_status)) + { + *speed = PHY_SPEED_1000M; + } + else if (PHY_STATUS_SPEED_100M(reg_status)) + { + *speed = PHY_SPEED_100M; + } + else + { + *speed = PHY_SPEED_10M; + } +#else + if (PHY_STATUS_SPEED_10M(reg_status)) + { + *speed = PHY_SPEED_10M; + } + else + { + *speed = PHY_SPEED_100M; + } +#endif + *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX; + + return PHY_STATUS_OK; +} + +static void phy_poll_status(void *parameter) +{ + int ret; + phy_info_t phy_info; + rt_uint32_t status; + rt_device_t dev; + rt_phy_msg_t msg; + rt_uint32_t speed, duplex; + phy_device_t *phy_dev; + struct eth_device* eth_dev; + char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; + + eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) + { + eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; + phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; + + phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); + + if (status) + { + phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); + + ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (ret != 0) + { + memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + } + } + + if (phy_dev->phy_link != status) + { + phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; + eth_device_linkchange(eth_dev, status); + LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); + if (status == PHY_LINK_UP) + { + LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); + LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); + } + } + } +} + +static void phy_detection(void *parameter) +{ + uint8_t detected_count = 0; + struct rt_phy_msg msg = {0, 0}; + phy_device_t *phy_dev = (phy_device_t *)parameter; + rt_uint32_t i; + + msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX]; + phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ); + + while(phy_dev->phy.addr == 0xffff) + { + /* Search a PHY */ + for (i = 0; i <= 0x1f; i++) + { + ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i; + phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1); + + if (msg.value == PHY_ID1) + { + phy_dev->phy.addr = i; + LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr); + return; + } + } + + phy_dev->phy.addr = 0xffff; + detected_count++; + rt_thread_mdelay(1000); + + if (detected_count > 3) + { + LOG_E("No any PHY device is detected! Please check your hardware!\n"); + return; + } + } +} + +static void phy_monitor_thread_entry(void *args) +{ + rt_timer_t phy_status_timer; + + eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) + { + LOG_D("Detect a PHY%d\n", i); + phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev); + } + + phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); + + if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK) + { + LOG_E("Failed to start link change detection timer\n"); + } +} + +int phy_device_register(void) +{ + rt_err_t err = RT_ERROR; + rt_thread_t thread_phy_monitor; + + /* Set ops for PHY */ + phy_ops.init = phy_init; + phy_ops.get_link_status = phy_get_link_status; + phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex; + + for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++) + { + /* Set PHY address */ + s_gphys[i]->phy_dev->phy.addr = 0xffff; + + /* Set MIDO bus */ + s_gphys[i]->mdio_bus->hw_obj = s_gphys[i]->instance; + s_gphys[i]->mdio_bus->name = s_gphys[i]->mdio_name; + s_gphys[i]->mdio_bus->ops->read = phy_read; + s_gphys[i]->mdio_bus->ops->write = phy_write; + s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; + s_gphys[i]->phy_dev->phy.ops = &phy_ops; + + /* Set PHY register list */ + s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i]; + + rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME); + } + + /* Start PHY monitor */ + thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2); + + if (thread_phy_monitor != RT_NULL) + { + rt_thread_startup(thread_phy_monitor); + } + else + { + err = RT_ERROR; + } + + return err; +} +INIT_PREV_EXPORT(phy_device_register); +#endif /* RT_USING_PHY */ diff --git a/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h new file mode 100644 index 0000000000..ae756ff551 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/eth_phy_port.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * +*/ + +#ifndef ETH_PHY_PORT_H +#define ETH_PHY_PORT_H + +#include "hpm_ioc_regs.h" +#include + +#ifndef PHY_AUTO_NEGO +#define PHY_AUTO_NEGO (1U) +#endif + +#ifndef PHY_MDIO_CSR_CLK_FREQ +#define PHY_MDIO_CSR_CLK_FREQ (200000000U) +#endif + +enum phy_link_status +{ + PHY_LINK_DOWN = 0U, + PHY_LINK_UP +}; + +typedef struct { + rt_uint32_t phy_speed; + rt_uint32_t phy_duplex; +} phy_info_t; + +typedef struct { + rt_uint32_t phy_link; + rt_phy_t phy; + phy_info_t phy_info; +} phy_device_t; + +#ifdef BSP_USING_ETH0 + + #define RGMII (1U) + + /* DP83867 name and ID */ + #define PHY_NAME ("DP83867") + #define PHY_ID1 (0x2000U) + #define PHY_ID2 (0x28U) + + /* PHY_DP83867 basic control register */ + #define PHY_BASIC_CONTROL_REG (0x00U) + #define PHY_RESET_MASK (1U << 15) + #define PHY_AUTO_NEGOTIATION_MASK (1U << 12) + + /* PHY_DP83867 basic status register */ + #define PHY_BASIC_STATUS_REG (0x01U) + #define PHY_LINKED_STATUS_MASK (1U << 2) + #define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) + + /* PHY_DP83867 ID one register */ + #define PHY_ID1_REG (0x02U) + + /* PHY_DP83867 ID two register */ + #define PHY_ID2_REG (0x03U) + + /* PHY_DP83867 auto-negotiate advertise register */ + #define PHY_AUTONEG_ADVERTISE_REG (0x04U) + + /* PHY_DP83867 status register */ + #define PHY_STATUS_REG (0x11U) + #define PHY_100M_MASK (1UL << 14) + #define PHY_1000M_MASK (1UL << 15) + #define PHY_FULL_DUPLEX_MASK (1UL << 13) + #define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) + #define PHY_STATUS_SPEED_1000M(SR) ((SR) & PHY_1000M_MASK) + #define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) + #define PHY_SPEED_SEL_SHIFT (14U) + /* PHY_DP83867 interrupt control register */ + #define PHY_INTERTUPT_CTRL_REG (0x12U) + + /* PHY_DP83867 interrupt status register */ + #define PHY_INTERRUPT_STATUS_REG (0x13U) + + /* PHY register index */ + typedef enum { + PHY_BASIC_CONTROL_REG_IDX = 0, + PHY_BASIC_STATUS_REG_IDX, + PHY_ID1_REG_IDX, + PHY_ID2_REG_IDX, + PHY_AUTONEG_ADVERTISE_REG_IDX, + PHY_STATUS_REG_IDX, + PHY_INTERRUPT_FLAG_REG_IDX, + PHY_INTERRUPT_MASK_REG_IDX + } phy_reg_idx_t; + + /* ETH0 PHY register list */ + #define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\ + PHY_BASIC_STATUS_REG,\ + PHY_ID1_REG,\ + PHY_ID2_REG,\ + PHY_AUTONEG_ADVERTISE_REG,\ + PHY_STATUS_REG,\ + PHY_INTERTUPT_CTRL_REG,\ + PHY_INTERRUPT_STATUS_REG + +#else + #define RMII (1U) + + /* DP83848 name and ID */ + #define PHY_NAME ("DP83848") + #define PHY_ID1 (0x2000U) + #define PHY_ID2 (0x17U) + + /* DP83848 basic control register */ + #define PHY_BASIC_CONTROL_REG (0x00U) + #define PHY_RESET_MASK (1U << 15) + #define PHY_AUTO_NEGOTIATION_MASK (1U << 12) + + /* DP83848 basic status register */ + #define PHY_BASIC_STATUS_REG (0x01U) + #define PHY_LINKED_STATUS_MASK (1U << 2) + #define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) + + /* DP83848 ID one register */ + #define PHY_ID1_REG (0x02U) + + /* DP83848 ID two register */ + #define PHY_ID2_REG (0x03U) + + /* DP83848 auto-negotiate advertise register */ + #define PHY_AUTONEG_ADVERTISE_REG (0x04U) + + /* DP83848 status register */ + #define PHY_STATUS_REG (0x10U) + #define PHY_10M_MASK (1UL << 1) + #define PHY_FULL_DUPLEX_MASK (1UL << 2) + #define PHY_STATUS_SPEED_10M(SR) ((SR) & PHY_10M_MASK) + #define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) + + /* PHY register index */ + typedef enum { + PHY_BASIC_CONTROL_REG_IDX = 0, + PHY_BASIC_STATUS_REG_IDX, + PHY_ID1_REG_IDX, + PHY_ID2_REG_IDX, + PHY_AUTONEG_ADVERTISE_REG_IDX, + PHY_STATUS_REG_IDX, + } phy_reg_idx_t; + + /* ETH0 PHY register list */ + #define PHY1_REG_LIST PHY_BASIC_CONTROL_REG,\ + PHY_BASIC_STATUS_REG,\ + PHY_ID1_REG,\ + PHY_ID2_REG,\ + PHY_AUTONEG_ADVERTISE_REG,\ + PHY_STATUS_REG + +#endif +#endif + + + + diff --git a/bsp/hpmicro/hpm6750evk/board/fal_cfg.h b/bsp/hpmicro/hpm6750evk/board/fal_cfg.h new file mode 100644 index 0000000000..80818b24e7 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/fal_cfg.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 9*1024*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c b/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c new file mode 100644 index 0000000000..a664b13fa8 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/fal_flash_port.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + +#if defined(FLASH_XIP) && (FLASH_XIP == 1) + +#define FAL_ENTER_CRITICAL() do {\ + rt_enter_critical();\ + disable_irq_from_intc();\ + fencei();\ + }while(0) + +#define FAL_EXIT_CRITICAL() do {\ + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ + fencei();\ + rt_exit_critical();\ + enable_irq_from_intc();\ + }while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + +#else +#define FAL_ENTER_CRITICAL() + +#define FAL_EXIT_CRITICAL() + +#define FAL_RAMFUNC + +#endif + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.c b/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.c new file mode 100644 index 0000000000..ebe335a235 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.c @@ -0,0 +1,722 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_sgtl5000.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config) +{ + assert(context != NULL); + assert(config != NULL); + + if (sgtl_write_reg(context, CHIP_ANA_POWER, 0x6AFF) != status_success) + { + return status_fail; + } + + /* Set the data route */ + if (sgtl_set_data_route(context, config->route) != status_success) + { + return status_fail; + } + + /* Set sgtl5000 to master or slave */ + sgtl_set_master_mode(context, config->master); + + /* Input Volume Control + Configure ADC left and right analog volume to desired default. + Example shows volume of 0dB. */ + if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0000U) != status_success) + { + return status_fail; + } + + /* Volume and Mute Control + Configure HP_OUT left and right volume to minimum, unmute. + HP_OUT and ramp the volume up to desired volume.*/ + if (sgtl_write_reg(context, CHIP_ANA_HP_CTRL, 0x1818U) != status_success) + { + return status_fail; + } + + if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFEFU, 0x0000U) != status_success) + { + return status_fail; + } + + /* LINEOUT and DAC volume control */ + if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFEFFU, 0x0000U) != status_success) + { + return status_fail; + } + + /* Configure DAC left and right digital volume */ + if (sgtl_write_reg(context, CHIP_DAC_VOL, 0x5C5CU) != status_success) + { + return status_fail; + } + + /* Configure ADC volume, reduce 6db. */ + if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0100U) != status_success) + { + return status_fail; + } + + /* Unmute DAC */ + if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFFBU, 0x0000U) != status_success) + { + return status_fail; + } + + if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFF7U, 0x0000U) != status_success) + { + return status_fail; + } + + /* Unmute ADC */ + if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFFEU, 0x0000U) != status_success) + { + return status_fail; + } + + /* Set the audio format */ + if (sgtl_set_protocol(context, config->bus) != status_success) + { + return status_fail; + } + + if (sgtl_config_data_format(context, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width) != + status_success) + { + return status_fail; + } + + /* sclk valid edge */ + if (config->format.sclk_edge == sgtl_sclk_valid_edge_rising) + { + if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE) != + status_success) + { + return status_fail; + } + } + else + { + if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE) != + status_success) + { + return status_fail; + } + } + + return status_success; +} + +hpm_stat_t sgtl_deinit(sgtl_context_t *context) +{ + hpm_stat_t stat = status_success; + + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_dap)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_lineout)); + + return stat; +} + +void sgtl_set_master_mode(sgtl_context_t *context, bool master) +{ + if (master == true) + { + (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_MASTER); + } + else + { + (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_SLAVE); + } +} + +hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module) +{ + hpm_stat_t stat = status_success; + switch (module) + { + case sgtl_module_adc: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_ADC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_ADC_POWERUP_SHIFT))); + break; + case sgtl_module_dac: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAC_POWERUP_SHIFT))); + break; + case sgtl_module_dap: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAP_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); + break; + case sgtl_module_i2sin: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_I2S_IN_ENABLE_SHIFT))); + break; + case sgtl_module_i2sout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); + break; + case sgtl_module_hp: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); + break; + case sgtl_module_lineout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_LINEOUT_POWERUP_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module) +{ + hpm_stat_t stat = status_success; + switch (module) + { + case sgtl_module_adc: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_ADC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_ADC_POWERUP_SHIFT))); + break; + case sgtl_module_dac: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAC_POWERUP_SHIFT))); + break; + case sgtl_module_dap: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAP_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); + break; + case sgtl_module_i2sin: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_I2S_IN_ENABLE_SHIFT))); + break; + case sgtl_module_i2sout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); + break; + case sgtl_module_hp: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); + break; + case sgtl_module_lineout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_LINEOUT_POWERUP_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route) +{ + hpm_stat_t stat = status_success; + switch (route) + { + case sgtl_route_bypass: + /* Bypass means from line-in to HP*/ + HPM_CHECK_RET(sgtl_write_reg(context, CHIP_DIG_POWER, 0x0000)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_LINEIN)); + break; + case sgtl_route_playback: + /* Data route I2S_IN-> DAC-> HP */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + break; + case sgtl_route_playback_record: + /* I2S IN->DAC->HP LINE_IN->ADC->I2S_OUT */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); + break; + case sgtl_route_playback_with_dap: + /* I2S_IN->DAP->DAC->HP */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + break; + case sgtl_route_playback_with_dap_record: + /* I2S_IN->DAP->DAC->HP, LINE_IN->ADC->I2S_OUT */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); + HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, 0x0001)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); + break; + case sgtl_route_record: + /* LINE_IN->ADC->I2S_OUT */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol) +{ + hpm_stat_t stat = status_success; + switch (protocol) + { + case sgtl_bus_i2s: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); + break; + case sgtl_bus_left_justified: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); + break; + case sgtl_bus_right_justified: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_RJ)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); + break; + case sgtl_bus_pcma: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); + break; + case sgtl_bus_pcmb: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32_t volume) +{ + uint16_t vol = 0; + hpm_stat_t stat = status_success; + switch (module) + { + case sgtl_module_adc: + if (volume > SGTL5000_ADC_MAX_VOLUME_VALUE) + { + return status_invalid_argument; + } + + vol = (uint16_t)(volume | (volume << 4U)); + stat = sgtl_modify_reg(context, CHIP_ANA_ADC_CTRL, + SGTL5000_ADC_VOL_LEFT_CLR_MASK & SGTL5000_ADC_VOL_RIGHT_CLR_MASK, vol); + break; + case sgtl_module_dac: + if ((volume > SGTL5000_DAC_MAX_VOLUME_VALUE) || (volume < SGTL5000_DAC_MIN_VOLUME_VALUE)) + { + return status_invalid_argument; + } + vol = (uint16_t)(volume | (volume << 8U)); + stat = sgtl_write_reg(context, CHIP_DAC_VOL, vol); + break; + case sgtl_module_hp: + if (volume > SGTL5000_HEADPHONE_MAX_VOLUME_VALUE) + { + return status_invalid_argument; + } + vol = (uint16_t)(volume | (volume << 8U)); + stat = sgtl_write_reg(context, CHIP_ANA_HP_CTRL, vol); + break; + case sgtl_module_lineout: + if (volume > SGTL5000_LINE_OUT_MAX_VOLUME_VALUE) + { + return status_invalid_argument; + } + vol = (uint16_t)(volume | (volume << 8U)); + stat = sgtl_write_reg(context, CHIP_LINE_OUT_VOL, vol); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module) +{ + uint16_t vol = 0; + hpm_stat_t stat = status_success; + + switch (module) + { + case sgtl_module_adc: + stat = sgtl_read_reg(context, CHIP_ANA_ADC_CTRL, &vol); + vol = (vol & (uint16_t)SGTL5000_ADC_VOL_LEFT_GET_MASK) >> SGTL5000_ADC_VOL_LEFT_SHIFT; + break; + case sgtl_module_dac: + stat = sgtl_read_reg(context, CHIP_DAC_VOL, &vol); + vol = (vol & (uint16_t)SGTL5000_DAC_VOL_LEFT_GET_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; + break; + case sgtl_module_hp: + stat = sgtl_read_reg(context, CHIP_ANA_HP_CTRL, &vol); + vol = (vol & (uint16_t)SGTL5000_HP_VOL_LEFT_GET_MASK) >> SGTL5000_HP_VOL_LEFT_SHIFT; + break; + case sgtl_module_lineout: + stat = sgtl_read_reg(context, CHIP_LINE_OUT_VOL, &vol); + vol = (vol & (uint16_t)SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK) >> SGTL5000_LINE_OUT_VOL_LEFT_SHIFT; + break; + default: + vol = 0; + break; + } + return stat == status_success ? vol : 0U; +} + +hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute) +{ + hpm_stat_t stat = status_success; + switch (module) + { + case sgtl_module_adc: + stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_ADC_CLR_MASK, mute ? 1U : 0U); + break; + case sgtl_module_dac: + if (mute) + { + stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, + SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x000C); + } + else + { + stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, + SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x0000); + } + break; + case sgtl_module_hp: + stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_HP_CLR_MASK, + ((uint16_t)mute << SGTL5000_MUTE_HP_SHIFT)); + break; + case sgtl_module_lineout: + stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_LO_CLR_MASK, + ((uint16_t)mute << SGTL5000_MUTE_LO_SHIFT)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits) +{ + uint16_t val = 0; + uint16_t regVal = 0; + uint16_t mul_clk = 0U; + uint32_t sysFs = 0U; + hpm_stat_t stat = status_success; + + /* Over sample rate can only up to 512, the least to 8k */ + if ((mclk / (MIN(sample_rate * 6U, 96000U)) > 512U) || (mclk / sample_rate < 256U)) + { + return status_invalid_argument; + } + + /* Configure the sample rate */ + switch (sample_rate) + { + case 8000: + if (mclk > 32000U * 512U) + { + val = 0x0038; + sysFs = 48000; + } + else + { + val = 0x0020; + sysFs = 32000; + } + break; + case 11025: + val = 0x0024; + sysFs = 44100; + break; + case 12000: + val = 0x0028; + sysFs = 48000; + break; + case 16000: + if (mclk > 32000U * 512U) + { + val = 0x003C; + sysFs = 96000; + } + else + { + val = 0x0010; + sysFs = 32000; + } + break; + case 22050: + val = 0x0014; + sysFs = 44100; + break; + case 24000: + if (mclk > 48000U * 512U) + { + val = 0x002C; + sysFs = 96000; + } + else + { + val = 0x0018; + sysFs = 48000; + } + break; + case 32000: + val = 0x0000; + sysFs = 32000; + break; + case 44100: + val = 0x0004; + sysFs = 44100; + break; + case 48000: + if (mclk > 48000U * 512U) + { + val = 0x001C; + sysFs = 96000; + } + else + { + val = 0x0008; + sysFs = 48000; + } + break; + case 96000: + val = 0x000C; + sysFs = 96000; + break; + default: + stat = status_invalid_argument; + break; + } + + if (stat != status_success) + { + return stat; + } + + if (sgtl_read_reg(context, CHIP_I2S_CTRL, ®Val) != status_success) + { + return status_fail; + } + + /* While as slave, Fs is input */ + if ((regVal & SGTL5000_I2S_MS_GET_MASK) == 0U) + { + sysFs = sample_rate; + } + mul_clk = (uint16_t)(mclk / sysFs); + /* Configure the mul_clk. Sgtl-5000 only support 256, 384 and 512 oversample rate */ + if ((mul_clk / 128U - 2U) > 2U) + { + return status_invalid_argument; + } + else + { + val |= (mul_clk / 128U - 2U); + } + + if (sgtl_write_reg(context, CHIP_CLK_CTRL, val) != status_success) + { + return status_fail; + } + + /* Data bits configure,sgtl supports 16bit, 20bit 24bit, 32bit */ + if (sgtl_modify_reg(context, CHIP_I2S_CTRL, 0xFEFF, SGTL5000_I2S_SCLKFREQ_64FS) != status_success) + { + return status_fail; + } + + switch (bits) + { + case 16: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_16); + break; + case 20: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_20); + break; + case 24: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_24); + break; + case 32: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_32); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t sgtl_set_play(sgtl_context_t *context, uint32_t playSource) +{ + uint16_t regValue = 0U, regBitMask = 0x40U; + + /* headphone source form PGA */ + if (playSource == (uint32_t)sgtl_play_source_linein) + { + regValue = 0x40U; + } + /* headphone source from DAC */ + else + { + regValue = 0U; + } + + return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); +} + +hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource) +{ + uint16_t regValue = 0U, regBitMask = 0x4U; + + /* ADC source form LINEIN */ + if (recordSource == (uint32_t)sgtl_record_source_linein) + { + regValue = 0x4U; + } + /* ADC source from MIC */ + else + { + regValue = 0U; + } + + return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); +} + +hpm_stat_t sgtl_write_reg(sgtl_context_t *context, uint16_t reg, uint16_t val) +{ + rt_size_t size; + rt_uint8_t data[4]; + data[0] = reg >> 8; + data[1] = reg & 0xFF; + data[2] = (uint8_t) (val>>8); + data[3] = (uint8_t) (val & 0xFF); + size = rt_i2c_master_send(context->i2c_bus, context->slave_address, RT_I2C_WR, data, 4U); + if (size != 4) { + return status_fail; + } + return status_success; +} + +hpm_stat_t sgtl_read_reg(sgtl_context_t *context, uint16_t reg, uint16_t *val) +{ + rt_size_t size; + rt_uint8_t r[2]; + uint8_t d[2]; + r[0] = reg >> 8; + r[1] = reg & 0xFF; + + size = rt_i2c_master_send(context->i2c_bus, context->slave_address, RT_I2C_WR, r, 2U); + if (size != 2) { + return status_fail; + } + + size = rt_i2c_master_recv(context->i2c_bus, context->slave_address, RT_I2C_RD, d, 2U); + if (size != 2) { + return status_fail; + } + *val = (uint16_t)((d[0] << 8) | d[1]); + return status_success; +} + +hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_mask, uint16_t val) +{ + hpm_stat_t retval = 0; + uint16_t reg_val; + + /* Read the register value out */ + retval = sgtl_read_reg(context, reg, ®_val); + if (retval != status_success) + { + return status_fail; + } + + /* Modify the value */ + reg_val &= clr_mask; + reg_val |= val; + + /* Write the data to register */ + retval = sgtl_write_reg(context, reg, reg_val); + if (retval != status_success) + { + return status_fail; + } + + return status_success; +} diff --git a/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.h b/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.h new file mode 100644 index 0000000000..c0073d1948 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/hpm_sgtl5000.h @@ -0,0 +1,1035 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_SGTL5000_H_ +#define _HPM_SGTL5000_H_ + +#include +#include +#include "rtt_board.h" +#include "drivers/i2c.h" + +/*! + * @addtogroup sgtl5000 + * @ingroup codec + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define the register address of sgtl5000. */ +#define CHIP_ID 0x0000U +#define CHIP_DIG_POWER 0x0002U +#define CHIP_CLK_CTRL 0x0004U +#define CHIP_I2S_CTRL 0x0006U +#define CHIP_SSS_CTRL 0x000AU +#define CHIP_ADCDAC_CTRL 0x000EU +#define CHIP_DAC_VOL 0x0010U +#define CHIP_PAD_STRENGTH 0x0014U +#define CHIP_ANA_ADC_CTRL 0x0020U +#define CHIP_ANA_HP_CTRL 0x0022U +#define CHIP_ANA_CTRL 0x0024U +#define CHIP_LINREG_CTRL 0x0026U +#define CHIP_REF_CTRL 0x0028U +#define CHIP_MIC_CTRL 0x002AU +#define CHIP_LINE_OUT_CTRL 0x002CU +#define CHIP_LINE_OUT_VOL 0x002EU +#define CHIP_ANA_POWER 0x0030U +#define CHIP_PLL_CTRL 0x0032U +#define CHIP_CLK_TOP_CTRL 0x0034U +#define CHIP_ANA_STATUS 0x0036U +#define CHIP_ANA_TEST2 0x003AU +#define CHIP_SHORT_CTRL 0x003CU +#define SGTL5000_DAP_CONTROL 0x0100U +#define SGTL5000_DAP_PEQ 0x0102U +#define SGTL5000_DAP_BASS_ENHANCE 0x0104U +#define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106U +#define SGTL5000_DAP_AUDIO_EQ 0x0108U +#define SGTL5000_DAP_SGTL_SURROUND 0x010AU +#define SGTL5000_DAP_FILTER_COEF_ACCESS 0x010CU +#define SGTL5000_DAP_COEF_WR_B0_MSB 0x010EU +#define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110U +#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0 0x0116U +#define SGTL5000_DAP_AUDIO_EQ_BAND1 0x0118U +#define SGTL5000_DAP_AUDIO_EQ_BAND2 0x011AU +#define SGTL5000_DAP_AUDIO_EQ_BAND3 0x011CU +#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4 0x011EU +#define SGTL5000_DAP_MAIN_CHAN 0x0120U +#define SGTL5000_DAP_MIX_CHAN 0x0122U +#define SGTL5000_DAP_AVC_CTRL 0x0124U +#define SGTL5000_DAP_AVC_THRESHOLD 0x0126U +#define SGTL5000_DAP_AVC_ATTACK 0x0128U +#define SGTL5000_DAP_AVC_DECAY 0x012AU +#define SGTL5000_DAP_COEF_WR_B1_MSB 0x012CU +#define SGTL5000_DAP_COEF_WR_B1_LSB 0x012EU +#define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130U +#define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132U +#define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134U +#define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136U +#define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138U +#define SGTL5000_DAP_COEF_WR_A2_LSB 0x013AU + +/* + * Field Definitions. + */ + +/* + * SGTL5000_CHIP_DIG_POWER + */ +#define SGTL5000_ADC_ENABLE_CLR_MASK 0xFFBFU +#define SGTL5000_ADC_ENABLE_GET_MASK 0x0040U +#define SGTL5000_ADC_ENABLE_SHIFT 0x6U +#define SGTL5000_DAC_ENABLE_CLR_MASK 0xFFDFU +#define SGTL5000_DAC_ENABLE_GET_MASK 0x0020U +#define SGTL5000_DAC_ENABLE_SHIFT 0x5U +#define SGTL5000_DAP_ENABLE_CLR_MASK 0xFFEFU +#define SGTL5000_DAP_ENABLE_GET_MASK 0x0010U +#define SGTL5000_DAP_ENABLE_SHIFT 0x4U +#define SGTL5000_I2S_OUT_ENABLE_CLR_MASK 0xFFFDU +#define SGTL5000_I2S_OUT_ENABLE_GET_MASK 0x0002U +#define SGTL5000_I2S_OUT_ENABLE_SHIFT 0x1U +#define SGTL5000_I2S_IN_ENABLE_CLR_MASK 0xFFFEU +#define SGTL5000_I2S_IN_ENABLE_GET_MASK 0x0001U +#define SGTL5000_I2S_IN_ENABLE_SHIFT 0x0U + +/* + * SGTL5000_CHIP_CLK_CTRL + */ +#define SGTL5000_RATE_MODE_CLR_MASK 0xFFCFU +#define SGTL5000_RATE_MODE_GET_MASK 0x0030U +#define SGTL5000_RATE_MODE_SHIFT 0x4U +#define SGTL5000_RATE_MODE_DIV_1 0x0000U +#define SGTL5000_RATE_MODE_DIV_2 0x0010U +#define SGTL5000_RATE_MODE_DIV_4 0x0020U +#define SGTL5000_RATE_MODE_DIV_6 0x0030U +#define SGTL5000_SYS_FS_CLR_MASK 0xFFF3U +#define SGTL5000_SYS_FS_GET_MASK 0x000CU +#define SGTL5000_SYS_FS_SHIFT 0x2U +#define SGTL5000_SYS_FS_32k 0x0000U +#define SGTL5000_SYS_FS_44_1k 0x0004U +#define SGTL5000_SYS_FS_48k 0x0008U +#define SGTL5000_SYS_FS_96k 0x000CU +#define SGTL5000_MCLK_FREQ_CLR_MASK 0xFFFCU +#define SGTL5000_MCLK_FREQ_GET_MASK 0x0003U +#define SGTL5000_MCLK_FREQ_SHIFT 0x0U +#define SGTL5000_MCLK_FREQ_256FS 0x0000U +#define SGTL5000_MCLK_FREQ_384FS 0x0001U +#define SGTL5000_MCLK_FREQ_512FS 0x0002U +#define SGTL5000_MCLK_FREQ_PLL 0x0003U + +/* + * SGTL5000_CHIP_I2S_CTRL + */ +#define SGTL5000_I2S_SLCKFREQ_CLR_MASK 0xFEFFU +#define SGTL5000_I2S_SCLKFREQ_GET_MASK 0x0100U +#define SGTL5000_I2S_SCLKFREQ_SHIFT 0x8U +#define SGTL5000_I2S_SCLKFREQ_64FS 0x0000U +#define SGTL5000_I2S_SCLKFREQ_32FS 0x0100U /* Not for RJ mode */ +#define SGTL5000_I2S_MS_CLR_MASK 0xFF7FU +#define SGTL5000_I2S_MS_GET_MASK 0x0080U +#define SGTL5000_I2S_MS_SHIFT 0x7U +#define SGTL5000_I2S_MASTER 0x0080U +#define SGTL5000_I2S_SLAVE 0x0000U +#define SGTL5000_I2S_SCLK_INV_CLR_MASK 0xFFBFU +#define SGTL5000_I2S_SCLK_INV_GET_MASK 0x0040U +#define SGTL5000_I2S_SCLK_INV_SHIFT 0x6U +#define SGTL5000_I2S_VAILD_FALLING_EDGE 0x0040U +#define SGTL5000_I2S_VAILD_RISING_EDGE 0x0000U +#define SGTL5000_I2S_DLEN_CLR_MASK 0xFFCFU +#define SGTL5000_I2S_DLEN_GET_MASK 0x0030U +#define SGTL5000_I2S_DLEN_SHIFT 0x4U +#define SGTL5000_I2S_DLEN_32 0x0000U +#define SGTL5000_I2S_DLEN_24 0x0010U +#define SGTL5000_I2S_DLEN_20 0x0020U +#define SGTL5000_I2S_DLEN_16 0x0030U +#define SGTL5000_I2S_MODE_CLR_MASK 0xFFF3U +#define SGTL5000_I2S_MODE_GET_MASK 0x000CU +#define SGTL5000_I2S_MODE_SHIFT 0x2U +#define SGTL5000_I2S_MODE_I2S_LJ 0x0000U +#define SGTL5000_I2S_MODE_RJ 0x0004U +#define SGTL5000_I2S_MODE_PCM 0x0008U +#define SGTL5000_I2S_LRALIGN_CLR_MASK 0xFFFDU +#define SGTL5000_I2S_LRALIGN_GET_MASK 0x0002U +#define SGTL5000_I2S_LRALIGN_SHIFT 0x1U +#define SGTL5000_I2S_ONE_BIT_DELAY 0x0000U +#define SGTL5000_I2S_NO_DELAY 0x0002U +#define SGTL5000_I2S_LRPOL_CLR_MASK 0xFFFEU +#define SGTL5000_I2S_LRPOL_GET_MASK 0x0001U +#define SGTL5000_I2S_LRPOL_SHIFT 0x0U +#define SGTL5000_I2S_LEFT_FIRST 0x0000U +#define SGTL5000_I2S_RIGHT_FIRST 0x0001U + +/* + * SGTL5000_CHIP_SSS_CTRL + */ +#define SGTL5000_DAP_MIX_LRSWAP_CLR_MASK 0xBFFFU +#define SGTL5000_DAP_MIX_LRSWAP_GET_MASK 0x4000U +#define SGTL5000_DAP_MIX_LRSWAP_SHIFT 0xEU +#define SGTL5000_DAP_LRSWAP_CLR_MASK 0xDFFFU +#define SGTL5000_DAP_LRSWAP_GET_MASK 0x2000U +#define SGTL5000_DAP_LRSWAP_SHIFT 0xDU +#define SGTL5000_DAC_LRSWAP_CLR_MASK 0xEFFFU +#define SGTL5000_DAC_LRSWAP_GET_MASK 0x1000U +#define SGTL5000_DAC_LRSWAP_SHIFT 0xCU +#define SGTL5000_I2S_LRSWAP_CLR_MASK 0xFBFFU +#define SGTL5000_I2S_LRSWAP_GET_MASK 0x0400U +#define SGTL5000_I2S_LRSWAP_SHIFT 0xAU +#define SGTL5000_DAP_MIX_SEL_CLR_MASK 0xFCFFU +#define SGTL5000_DAP_MIX_SEL_GET_MASK 0x0300U +#define SGTL5000_DAP_MIX_SEL_SHIFT 0x8U +#define SGTL5000_DAP_MIX_SEL_ADC 0x0000U +#define SGTL5000_DAP_MIX_SEL_I2S_IN 0x0100U +#define SGTL5000_DAP_SEL_CLR_MASK 0xFF3FU +#define SGTL5000_DAP_SEL_GET_MASK 0x00C0U +#define SGTL5000_DAP_SEL_SHIFT 0x6U +#define SGTL5000_DAP_SEL_ADC 0x0000U +#define SGTL5000_DAP_SEL_I2S_IN 0x0040U +#define SGTL5000_DAC_SEL_CLR_MASK 0xFFCFU +#define SGTL5000_DAC_SEL_GET_MASK 0x0030U +#define SGTL5000_DAC_SEL_SHIFT 0x4U +#define SGTL5000_DAC_SEL_ADC 0x0000U +#define SGTL5000_DAC_SEL_I2S_IN 0x0010U +#define SGTL5000_DAC_SEL_DAP 0x0030U +#define SGTL5000_I2S_OUT_SEL_CLR_MASK 0xFFFCU +#define SGTL5000_I2S_OUT_SEL_GET_MASK 0x0003U +#define SGTL5000_I2S_OUT_SEL_SHIFT 0x0U +#define SGTL5000_I2S_OUT_SEL_ADC 0x0000U +#define SGTL5000_I2S_OUT_SEL_I2S_IN 0x0001U +#define SGTL5000_I2S_OUT_SEL_DAP 0x0003U + +/* + * SGTL5000_CHIP_ADCDAC_CTRL + */ +#define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000U +#define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000U +#define SGTL5000_DAC_VOL_RAMP_EN_CLR_MASK 0xFDFFU +#define SGTL5000_DAC_VOL_RAMP_EN_GET_MASK 0x0200U +#define SGTL5000_DAC_VOL_RAMP_EN_SHIFT 0x9U +#define SGTL5000_DAC_VOL_RAMP_EXPO_CLR_MASK 0xFEFFU +#define SGTL5000_DAC_VOL_RAMP_EXPO_GET_MASK 0x0100U +#define SGTL5000_DAC_VOL_RAMP_EXPO_SHIFT 0x8U +#define SGTL5000_DAC_MUTE_RIGHT_CLR_MASK 0xFFF7U +#define SGTL5000_DAC_MUTE_RIGHT_GET_MASK 0x0008U +#define SGTL5000_DAC_MUTE_RIGHT_SHIFT 0x3U +#define SGTL5000_DAC_MUTE_LEFT_CLR_MASK 0xFFFBU +#define SGTL5000_DAC_MUTE_LEFT_GET_MASK 0x0004U +#define SGTL5000_DAC_MUTE_LEFT_SHIFT 0x2U +#define SGTL5000_ADC_HPF_FREEZE_CLR_MASK 0xFFFDU +#define SGTL5000_ADC_HPF_FREEZE_GET_MASK 0x0002U +#define SGTL5000_ADC_HPF_FREEZE_SHIFT 0x1U +#define SGTL5000_ADC_HPF_BYPASS_CLR_MASK 0xFFFEU +#define SGTL5000_ADC_HPF_BYPASS_GET_MASK 0x0001U +#define SGTL5000_ADC_HPF_BYPASS_SHIFT 0x0U + +/* + * SGTL5000_CHIP_DAC_VOL + */ +#define SGTL5000_DAC_VOL_RIGHT_CLR_MASK 0x00FFU +#define SGTL5000_DAC_VOL_RIGHT_GET_MASK 0xFF00U +#define SGTL5000_DAC_VOL_RIGHT_SHIFT 0x8U +#define SGTL5000_DAC_VOL_LEFT_CLR_MASK 0xFF00U +#define SGTL5000_DAC_VOL_LEFT_GET_MASK 0x00FFU +#define SGTL5000_DAC_VOL_LEFT_SHIFT 0x0U + +/* + * SGTL5000_CHIP_PAD_STRENGTH + */ +#define SGTL5000_PAD_I2S_LRCLK_CLR_MASK 0xFCFFU +#define SGTL5000_PAD_I2S_LRCLK_GET_MASK 0x0300U +#define SGTL5000_PAD_I2S_LRCLK_SHIFT 0x8U +#define SGTL5000_PAD_I2S_SCLK_CLR_MASK 0xFF3FU +#define SGTL5000_PAD_I2S_SCLK_GET_MASK 0x00C0U +#define SGTL5000_PAD_I2S_SCLK_SHIFT 0x6U +#define SGTL5000_PAD_I2S_DOUT_CLR_MASK 0xFFCFU +#define SGTL5000_PAD_I2S_DOUT_GET_MASK 0x0030U +#define SGTL5000_PAD_I2S_DOUT_SHIFT 0x4U +#define SGTL5000_PAD_I2C_SDA_CLR_MASK 0xFFF3U +#define SGTL5000_PAD_I2C_SDA_GET_MASK 0x000CU +#define SGTL5000_PAD_I2C_SDA_SHIFT 0x2U +#define SGTL5000_PAD_I2C_SCL_CLR_MASK 0xFFFCU +#define SGTL5000_PAD_I2C_SCL_GET_MASK 0x0003U +#define SGTL5000_PAD_I2C_SCL_SHIFT 0x0U + +/* + * SGTL5000_CHIP_ANA_ADC_CTRL + */ +#define SGTL5000_ADC_VOL_M6DB_CLR_MASK 0xFEFFU +#define SGTL5000_ADC_VOL_M6DB_GET_MASK 0x0100U +#define SGTL5000_ADC_VOL_M6DB_SHIFT 0x8U +#define SGTL5000_ADC_VOL_RIGHT_CLR_MASK 0xFF0FU +#define SGTL5000_ADC_VOL_RIGHT_GET_MASK 0x00F0U +#define SGTL5000_ADC_VOL_RIGHT_SHIFT 0x4U +#define SGTL5000_ADC_VOL_LEFT_CLR_MASK 0xFFF0U +#define SGTL5000_ADC_VOL_LEFT_GET_MASK 0x000FU +#define SGTL5000_ADC_VOL_LEFT_SHIFT 0x0U + +/* + * SGTL5000_CHIP_ANA_HP_CTRL + */ +#define SGTL5000_HP_VOL_RIGHT_CLR_MASK 0x80FFU +#define SGTL5000_HP_VOL_RIGHT_GET_MASK 0x7F00U +#define SGTL5000_HP_VOL_RIGHT_SHIFT 0x8U +#define SGTL5000_HP_VOL_LEFT_CLR_MASK 0xFF80U +#define SGTL5000_HP_VOL_LEFT_GET_MASK 0x007FU +#define SGTL5000_HP_VOL_LEFT_SHIFT 0x0U + +/* + * SGTL5000_CHIP_ANA_CTRL + */ +#define SGTL5000_MUTE_LO_GET_MASK 0x0100U +#define SGTL5000_MUTE_LO_CLR_MASK 0xFEFFU +#define SGTL5000_MUTE_LO_SHIFT 0x8U +#define SGTL5000_SEL_HP_GET_MASK 0x0040U +#define SGTL5000_SEL_HP_CLR_MASK 0xFFBFU +#define SGTL5000_SEL_HP_SHIFT 0x6U +#define SGTL5000_SEL_HP_DAC 0x0000U +#define SGTL5000_SEL_HP_LINEIN 0x0040U +#define SGTL5000_EN_ZCD_HP_GET_MASK 0x0020U +#define SGTL5000_EN_ZCD_HP_CLR_MASK 0xFFDFU +#define SGTL5000_EN_ZCD_HP_SHIFT 0x5U +#define SGTL5000_MUTE_HP_GET_MASK 0x0010U +#define SGTL5000_MUTE_HP_CLR_MASK 0xFFEFU +#define SGTL5000_MUTE_HP_SHIFT 0x4U +#define SGTL5000_SEL_ADC_GET_MASK 0x0004U +#define SGTL5000_SEL_ADC_CLR_MASK 0xFFFBU +#define SGTL5000_SEL_ADC_SHIFT 0x2U +#define SGTL5000_SEL_ADC_MIC 0x0000U +#define SGTL5000_SEL_ADC_LINEIN 0x0004U +#define SGTL5000_EN_ZCD_ADC_GET_MASK 0x0002U +#define SGTL5000_EN_ZCD_ADC_CLR_MASK 0xFFFDU +#define SGTL5000_EN_ZCD_ADC_SHIFT 0x1U +#define SGTL5000_MUTE_ADC_GET_MASK 0x0001U +#define SGTL5000_MUTE_ADC_CLR_MASK 0xFFFEU +#define SGTL5000_MUTE_ADC_SHIFT 0x0U + +/* + * SGTL5000_CHIP_LINREG_CTRL + */ +#define SGTL5000_VDDC_MAN_ASSN_CLR_MASK 0xFFBFU +#define SGTL5000_VDDC_MAN_ASSN_GET_MASK 0x0040U +#define SGTL5000_VDDC_MAN_ASSN_SHIFT 0x6U +#define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0000U +#define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x0040U +#define SGTL5000_VDDC_ASSN_OVRD 0x0020U +#define SGTL5000_LINREG_VDDD_CLR_MASK 0xFFF0U +#define SGTL5000_LINREG_VDDD_GET_MASK 0x000FU +#define SGTL5000_LINREG_VDDD_SHIFT 0x0U + +/* + * SGTL5000_CHIP_REF_CTRL + */ +#define SGTL5000_ANA_GND_MASK 0x01f0U +#define SGTL5000_ANA_GND_SHIFT 0x4U +#define SGTL5000_ANA_GND_WIDTH 0x5U +#define SGTL5000_ANA_GND_BASE 0x320U /* mv */ +#define SGTL5000_ANA_GND_STP 0x19U /*mv */ +#define SGTL5000_BIAS_CTRL_MASK 0x000eU +#define SGTL5000_BIAS_CTRL_SHIFT 0x1U +#define SGTL5000_BIAS_CTRL_WIDTH 0x3U +#define SGTL5000_SMALL_POP 0x0001U + +/* + * SGTL5000_CHIP_MIC_CTRL + */ +#define SGTL5000_BIAS_R__CLR_MASK 0xFCFFU +#define SGTL5000_BIAS_R_GET_MASK 0x0300U +#define SGTL5000_BIAS_R_SHIFT 0x8U +#define SGTL5000_BIAS_R_off 0x0000U +#define SGTL5000_BIAS_R_2K 0x0100U +#define SGTL5000_BIAS_R_4k 0x0200U +#define SGTL5000_BIAS_R_8k 0x0300U +#define SGTL5000_BIAS_VOLT_CLR_MASK 0xFF8FU +#define SGTL5000_BIAS_VOLT_GET_MASK 0x0070U +#define SGTL5000_BIAS_VOLT_SHIFT 0x4U +#define SGTL5000_MIC_GAIN_CLR_MASK 0xFFFCU +#define SGTL5000_MIC_GAIN_GET_MASK 0x0003U +#define SGTL5000_MIC_GAIN_SHIFT 0x0U + +/* + * SGTL5000_CHIP_LINE_OUT_CTRL + */ +#define SGTL5000_LINE_OUT_CURRENT_CLR_MASK 0xF0FFU +#define SGTL5000_LINE_OUT_CURRENT_GET_MASK 0x0F00U +#define SGTL5000_LINE_OUT_CURRENT_SHIFT 0x8U +#define SGTL5000_LINE_OUT_CURRENT_180u 0x0000U +#define SGTL5000_LINE_OUT_CURRENT_270u 0x0100U +#define SGTL5000_LINE_OUT_CURRENT_360u 0x0300U +#define SGTL5000_LINE_OUT_CURRENT_450u 0x0700U +#define SGTL5000_LINE_OUT_CURRENT_540u 0x0F00U +#define SGTL5000_LINE_OUT_GND_CLR_MASK 0xFFC0U +#define SGTL5000_LINE_OUT_GND_GET_MASK 0x003FU +#define SGTL5000_LINE_OUT_GND_SHIFT 0x0U +#define SGTL5000_LINE_OUT_GND_BASE 0x320U /* mv */ +#define SGTL5000_LINE_OUT_GND_STP 0x19U +#define SGTL5000_LINE_OUT_GND_MAX 0x23U + +/* + * SGTL5000_CHIP_LINE_OUT_VOL + */ +#define SGTL5000_LINE_OUT_VOL_RIGHT_CLR_MASK 0xE0FFU +#define SGTL5000_LINE_OUT_VOL_RIGHT_GET_MASK 0x1F00U +#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 0x8U +#define SGTL5000_LINE_OUT_VOL_LEFT_CLR_MASK 0xFFE0U +#define SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK 0x001FU +#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0x0U + +/* + * SGTL5000_CHIP_ANA_POWER + */ +#define SGTL5000_RIGHT_DAC_POWERUP_GET_MASK 0x4000U +#define SGTL5000_RIGHT_DAC_POWERUP_CLR_MASK 0xBFFFU +#define SGTL5000_RIGHT_DAC_POWERUP_SHIFT 0xEU +#define SGTL5000_LINREG_SIMPLE_POWERUP_GET_MASK 0x2000U +#define SGTL5000_LINREG_SIMPLE_POWERUP_CLR_MASK 0xDFFFU +#define SGTL5000_LINREG_SIMPLE_POWERUP_SHIFT 0xDU +#define SGTL5000_STARTUP_POWERUP_GET_MASK 0x1000U +#define SGTL5000_STARTUP_POWERUP_CLR_MASK 0xEFFFU +#define SGTL5000_STARTUP_POWERUP_SHIFT 0xCU +#define SGTL5000_VDDC_CHRGPMP_POWERUP_GET_MASK 0x0800U +#define SGTL5000_VDDC_CHRGPMP_POWERUP_CLR_MASK 0xF7FFU +#define SGTL5000_VDDC_CHRGPMP_POWERUP_SHIFT 0xBU +#define SGTL5000_PLL_POWERUP_GET_MASK 0x0400U +#define SGTL5000_PLL_POWERUP_CLR_MASK 0xFBFFU +#define SGTL5000_PLL_POWERUP_SHIFT 0xAU +#define SGTL5000_LINREG_D_POWERUP_GET_MASK 0x0200U +#define SGTL5000_LINREG_D_POWERUP_CLR_MASK 0xFDFFU +#define SGTL5000_LINREG_D_POWERUP_SHIFT 0x9U +#define SGTL5000_VCOAMP_POWERUP_GET_MASK 0x0100U +#define SGTL5000_VCOAMP_POWERUP_CLR_MASK 0xFEFFU +#define SGTL5000_VCOAMP_POWERUP_SHIFT 0x8U +#define SGTL5000_VAG_POWERUP_GET_MASK 0x0080U +#define SGTL5000_VAG_POWERUP_CLR_MASK 0xFF7FU +#define SGTL5000_VAG_POWERUP_SHIFT 0x7U +#define SGTL5000_RIGHT_ADC_POWERUP_GET_MASK 0x0040U +#define SGTL5000_RIGHT_ADC_POWERUP_CLR_MASK 0xFFBFU +#define SGTL5000_RIGHT_ADC_POWERUP_SHIFT 0x6U +#define SGTL5000_REFTOP_POWERUP_GET_MASK 0x0020U +#define SGTL5000_REFTOP_POWERUP_CLR_MASK 0xFFDFU +#define SGTL5000_REFTOP_POWERUP_SHIFT 0x5U +#define SGTL5000_HEADPHONE_POWERUP_GET_MASK 0x0010U +#define SGTL5000_HEADPHONE_POWERUP_CLR_MASK 0xFFEFU +#define SGTL5000_HEADPHONE_POWERUP_SHIFT 0x4U +#define SGTL5000_DAC_POWERUP_GET_MASK 0x0008U +#define SGTL5000_DAC_POWERUP_CLR_MASK 0xFFF7U +#define SGTL5000_DAC_POWERUP_SHIFT 0x3U +#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_GET_MASK 0x0004U +#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_CLR_MASK 0xFFFBU +#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_SHIFT 0x2U +#define SGTL5000_ADC_POWERUP_GET_MASK 0x0002U +#define SGTL5000_ADC_POWERUP_CLR_MASK 0xFFFDU +#define SGTL5000_ADC_POWERUP_SHIFT 0x1U +#define SGTL5000_LINEOUT_POWERUP_GET_MASK 0x0001U +#define SGTL5000_LINEOUT_POWERUP_CLR_MASK 0xFFFEU +#define SGTL5000_LINEOUT_POWERUP_SHIFT 0x0U + +/* + * SGTL5000_CHIP_PLL_CTRL + */ +#define SGTL5000_PLL_INT_DIV_CLR_MASK 0x07FFU +#define SGTL5000_PLL_INT_DIV_GET_MASK 0xF800U +#define SGTL5000_PLL_INT_DIV_SHIFT 0xBU +#define SGTL5000_PLL_FRAC_DIV_CLR_MASK 0xF8FFU +#define SGTL5000_PLL_FRAC_DIV_GET_MASK 0x0700U +#define SGTL5000_PLL_FRAC_DIV_SHIFT 0x0U + +/* + * SGTL5000_CHIP_CLK_TOP_CTRL + */ +#define SGTL5000_ENABLE_INT_OSC_GET_MASK 0x0800U +#define SGTL5000_ENABLE_INT_OSC_CLR_MASK 0xF7FFU +#define SGTL5000_ENABLE_INT_OSC_SHIFT 0xBU +#define SGTL5000_INPUT_FREQ_DIV2_GET_MASK 0x0008U +#define SGTL5000_INPUT_FREQ_DIV2_CLR_MASK 0xFFF7U +#define SGTL5000_INPUT_FREQ_DIV2_SHIFT 0x3U + +/* + * SGTL5000_CHIP_ANA_STATUS + */ +#define SGTL5000_HP_LRSHORT 0x0200U +#define SGTL5000_CAPLESS_SHORT 0x0100U +#define SGTL5000_PLL_LOCKED 0x0010U + +/* + * SGTL5000_CHIP_SHORT_CTRL + */ +#define SGTL5000_LVLADJR_CLR_MASK 0x8FFFU +#define SGTL5000_LVLADJR_GET_MASK 0x7000U +#define SGTL5000_LVLADJR_SHIFT 0xCU +#define SGTL5000_LVLADJL_CLR_MASK 0xF8FFU +#define SGTL5000_LVLADJL_GET_MASK 0x0700U +#define SGTL5000_LVLADJL_SHIFT 0x8U +#define SGTL5000_LVLADJC_CLR_MASK 0xFF8FU +#define SGTL5000_LVLADJC_GET_MASK 0x0070U +#define SGTL5000_LVLADJC_SHIFT 0x4U +#define SGTL5000_LR_SHORT_MOD_CLR_MASK 0xFFF3U +#define SGTL5000_LR_SHORT_MOD_GET_MASK 0x000CU +#define SGTL5000_LR_SHORT_MOD_SHIFT 0x2U +#define SGTL5000_CM_SHORT_MOD_CLR_MASK 0xFFFCU +#define SGTL5000_CM_SHORT_MOD_GET_MASK 0x0003U +#define SGTL5000_CM_SHORT_MOD_SHIFT 0x0U + +/* DAP control register */ +#define SGTL5000_DAP_CONTROL_MIX_EN_GET_MASK 0x0010U +#define SGTL5000_DAP_CONTROL_MIX_EN_CLR_MASK 0xFFEFU +#define SGTL5000_DAP_CONTROL_MIX_EN_SHIFT 0x4U +#define SGTL5000_DAP_CONTROL_DAP_EN_GET_MASK 0x0001U +#define SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_CONTROL_DAP_EN_SHIFT 0x0U + +/* + * DAP_PEQ_REG + */ +#define SGTL5000_DAP_PEQ_EN_GET_MASK 0x0007U +#define SGTL5000_DAP_PEQ_EN_CLR_MASK 0xFFF8U +#define SGTL5000_DAP_PEQ_EN_SHIFT 0x0U + +/* + * DAP_BASS_ENHANCE_REG + */ +#define SGTL5000_DAP_BASS_ENHANCE_MULT_GET_MASK 0xC000U +#define SGTL5000_DAP_BASS_ENHANCE_MULT_CLR_MASK 0x3FFFU +#define SGTL5000_DAP_BASS_ENHANCE_MULT_SHIFT 0xEU +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_GET_MASK 0x0E00U +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_CLR_MASK 0xF1FFU +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_SHIFT 0x9U +#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_GET_MASK 0x0100U +#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_CLR_MASK 0xFEFFU +#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_SHIFT 0x8U +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_GET_MASK 0x0070U +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_CLR_MASK 0xFF8FU +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_SHIFT 0x4U +#define SGTL5000_DAP_BASS_ENHANCE_EN_GET_MASK 0x0001U +#define SGTL5000_DAP_BASS_ENHANCE_EN_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_BASS_ENHANCE_EN_SHIFT 0x0U + +/* + * DAP_BASS_ENHANCE_CTRL_REG + */ +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_GET_MASK 0x3F00U +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_CLR_MASK 0xC0FFU +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_SHIFT 0x8U +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_GET_MASK 0x007FU +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_CLR_MASK 0xFF80U +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_EN_GET_MASK 0x0003U +#define SGTL5000_DAP_AUDIO_EQ_EN_CLR_MASK 0xFFFCU +#define SGTL5000_DAP_AUDIO_EQ_EN_SHIFT 0x0U + +/* + * DAP_SGTL_SURROUND_REG + */ +#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_GET_MASK 0x0070U +#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_CLR_MASK 0xFF8FU +#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_SHIFT 0x4U +#define SGTL5000_DAP_SGTL_SURROUND_SEL_GET_MASK 0x0003U +#define SGTL5000_DAP_SGTL_SURROUND_SEL_CLR_MASK 0xFFFCU +#define SGTL5000_DAP_SGTL_SURROUND_SEL_SHIFT 0x0U + +/* + * DAP_FILTER_COEF_ACCESS_REG + */ +#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_GET_MASK 0x1000U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_CLR_MASK 0xEFFFU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_SHIFT 0xCU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_GET_MASK 0x0200U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_CLR_MASK 0xFDFFU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_SHIFT 0x9U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_GET_MASK 0x0100U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_CLR_MASK 0xFEFFU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_SHIFT 0x8U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_GET_MASK 0x00FFU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_CLR_MASK 0xFF00U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_SHIFT 0x0U + +/* + * DAP_COEF_WR_B0_MSB_REG + */ +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_GET_MASK 0x8000U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_CLR_MASK 0x7FFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_SHIFT 0xFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_GET_MASK 0x4000U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_CLR_MASK 0xBFFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_SHIFT 0xEU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_GET_MASK 0x2000U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_CLR_MASK 0xDFFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_SHIFT 0xDU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_GET_MASK 0x1000U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_CLR_MASK 0xEFFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_SHIFT 0xCU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_GET_MASK 0x0800U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_CLR_MASK 0xF7FFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_SHIFT 0xBU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_GET_MASK 0x0400U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_CLR_MASK 0xFBFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_SHIFT 0xAU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_GET_MASK 0x0200U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_CLR_MASK 0xFDFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_SHIFT 0x9U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_GET_MASK 0x0100U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_CLR_MASK 0xFEFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_SHIFT 0x8U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_GET_MASK 0x0080U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_CLR_MASK 0xFF7FU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_SHIFT 0x7U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_GET_MASK 0x0040U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_CLR_MASK 0xFFBFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_SHIFT 0x6U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_GET_MASK 0x0020U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_CLR_MASK 0xFFDFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_SHIFT 0x5U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_GET_MASK 0x0010U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_CLR_MASK 0xFFEFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_SHIFT 0x4U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_GET_MASK 0x0008U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_CLR_MASK 0xFFF7U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_SHIFT 0x3U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_GET_MASK 0x0004U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_CLR_MASK 0xFFFBU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_SHIFT 0x2U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_GET_MASK 0x0002U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_CLR_MASK 0xFFFDU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_SHIFT 0x1U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_GET_MASK 0x0001U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_SHIFT 0x0U + +/* + * DAP_COEF_WR_B0_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_GET_MASK 0x0008U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_CLR_MASK 0xFFF7U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_SHIFT 0x3U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_GET_MASK 0x0004U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_CLR_MASK 0xFFFBU +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_SHIFT 0x2U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_GET_MASK 0x0002U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_CLR_MASK 0xFFFDU +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_SHIFT 0x1U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_GET_MASK 0x0001U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_BASS_BAND0_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_BAND1_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_BAND2_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_BAND3_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_TREBLE_BAND4_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_SHIFT 0x0U + +/* + * DAP_MAIN_CHAN_REG + */ +#define SGTL5000_DAP_MAIN_CHAN_VOL_GET_MASK 0xFFFFU +#define SGTL5000_DAP_MAIN_CHAN_VOL_CLR_MASK 0x0000U +#define SGTL5000_DAP_MAIN_CHAN_VOL_SHIFT 0x0U + +/* + * DAP_MIX_CHAN_REG + */ +#define SGTL5000_DAP_MIX_CHAN_VOL_GET_MASK 0xFFFFU +#define SGTL5000_DAP_MIX_CHAN_VOL_CLR_MASK 0x0000U +#define SGTL5000_DAP_MIX_CHAN_VOL_SHIFT 0x0U + +/* + * DAP_AVC_CTRL_REG + */ +#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_GET_MASK 0x4000U +#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_CLR_MASK 0xBFFFU +#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_SHIFT 0xEU +#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_GET_MASK 0x3000U +#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_CLR_MASK 0xCFFFU +#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_SHIFT 0xCU +#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_GET_MASK 0x0300U +#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_CLR_MASK 0xFCFFU +#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_SHIFT 0x8U +#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_GET_MASK 0x0020U +#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_CLR_MASK 0xFFDFU +#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_SHIFT 0x5U +#define SGTL5000_DAP_AVC_CTRL_STOP_GET_MASK 0x0004U +#define SGTL5000_DAP_AVC_CTRL_STOP_SHIFT 0x2U +#define SGTL5000_DAP_AVC_CTRL_RUNNING_GET_MASK 0x0002U +#define SGTL5000_DAP_AVC_CTRL_RUNNING_SHIFT 0x1U +#define SGTL5000_DAP_AVC_CTRL_EN_GET_MASK 0x0001U +#define SGTL5000_DAP_AVC_CTRL_EN_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_AVC_CTRL_EN_SHIFT 0x0U + +/* + * DAP_AVC_ATTACK_REG + */ +#define SGTL5000_DAP_AVC_ATTACK_RATE_GET_MASK 0x0FFFU +#define SGTL5000_DAP_AVC_ATTACK_RATE_CLR_MASK 0xF000U +#define SGTL5000_DAP_AVC_ATTACK_RATE_SHIFT 0x0U + +/* + * DAP_AVC_DECAY_REG + */ +#define SGTL5000_DAP_AVC_DECAY_RATE_GET_MASK 0x0FFFU +#define SGTL5000_DAP_AVC_DECAY_RATE_CLR_MASK 0xF000U +#define SGTL5000_DAP_AVC_DECAY_RATE_SHIFT 0x0U + +/* + * DAP_COEF_WR_B1_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_GET_MASK 0x000FU +#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_CLR_MASK 0xFFF0U +#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_SHIFT 0x0U + +/* + * DAP_COEF_WR_B2_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_GET_MASK 0x000FU +#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_CLR_MASK 0xFFF0U +#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_SHIFT 0x0U + +/* + * DAP_COEF_WR_A1_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_GET_MASK 0x000FU +#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_CLR_MASK 0xFFF0U +#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_SHIFT 0x0U + +/* + * DAP_COEF_WR_A2_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_GET_MASK 0x000FU +#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_CLR_MASK 0xFFF0U +#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_SHIFT 0x0U + +/*! @brief SGTL5000 volume setting range */ +#define SGTL5000_HEADPHONE_MAX_VOLUME_VALUE 0x7FU +#define SGTL5000_HEADPHONE_MIN_VOLUME_VALUE 0U +#define SGTL5000_LINE_OUT_MAX_VOLUME_VALUE 0x1FU +#define SGTL5000_LINE_OUT_MIN_VOLUME_VALUE 0U +#define SGTL5000_ADC_MAX_VOLUME_VALUE 0xFU +#define SGTL5000_ADC_MIN_VOLUME_VALUE 0U +#define SGTL5000_DAC_MAX_VOLUME_VALUE 0xF0U +#define SGTL5000_DAC_MIN_VOLUME_VALUE 0x3CU + +/*! @brief SGTL5000 I2C address. */ +#define SGTL5000_I2C_ADDR 0x0A + +/*! @brief sgtl i2c baudrate */ +#define SGTL_I2C_BITRATE 100000U + +/*! @brief Modules in Sgtl5000 board. */ +typedef enum _sgtl5000_module +{ + sgtl_module_adc = 0x0, /*!< ADC module in SGTL5000 */ + sgtl_module_dac, /*!< DAC module in SGTL5000 */ + sgtl_module_dap, /*!< DAP module in SGTL5000 */ + sgtl_module_hp, /*!< Headphone module in SGTL5000 */ + sgtl_module_i2sin, /*!< I2S-IN module in SGTL5000 */ + sgtl_module_i2sout, /*!< I2S-OUT module in SGTL5000 */ + sgtl_module_linein, /*!< Line-in moudle in SGTL5000 */ + sgtl_module_lineout, /*!< Line-out module in SGTL5000 */ + sgtl_module_micin /*!< Micphone module in SGTL5000 */ +} sgtl_module_t; + +/*! + * @brief Sgtl5000 data route. + * @note Only provide some typical data route, not all route listed. + * Users cannot combine any routes, once a new route is set, the precios one would be replaced. + */ +typedef enum _sgtl_route +{ + sgtl_route_bypass = 0x0, /*!< LINEIN->Headphone. */ + sgtl_route_playback, /*!< I2SIN->DAC->Headphone. */ + sgtl_route_playback_record, /*!< I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT. */ + sgtl_route_playback_with_dap, /*!< I2SIN->DAP->DAC->Headphone. */ + sgtl_route_playback_with_dap_record, /*!< I2SIN->DAP->DAC->HP, LINEIN->ADC->I2SOUT. */ + sgtl_route_record /*!< LINEIN->ADC->I2SOUT. */ +} sgtl_route_t; + +/*! + * @brief The audio data transfer protocol choice. + * Sgtl5000 only supports I2S format and PCM format. + */ +typedef enum _sgtl_protocol +{ + sgtl_bus_i2s = 0x0, /*!< I2S Type */ + sgtl_bus_left_justified, /*!< Left justified */ + sgtl_bus_right_justified, /*!< Right Justified */ + sgtl_bus_pcma, /*!< PCMA */ + sgtl_bus_pcmb /*!< PCMB */ +} sgtl_protocol_t; + +/*! @brief sgtl play channel + * @anchor _sgtl_play_channel + */ +enum +{ + sgtl_headphone_left = 0, /*!< headphone left channel */ + sgtl_headphone_right = 1, /*!< headphone right channel */ + sgtl_lineout_left = 2, /*!< lineout left channel */ + sgtl_lineout_right = 3, /*!< lineout right channel */ +}; + +/*! @brief sgtl record source + * _sgtl_record_source + */ +enum +{ + sgtl_record_source_linein = 0U, /*!< record source line in */ + sgtl_record_source_mic = 1U, /*!< record source single end */ +}; + +/*! @brief sgtl play source + * _stgl_play_source + */ +enum +{ + sgtl_play_source_linein = 0U, /*!< play source line in */ + sgtl_play_source_dac = 1U, /*!< play source line in */ +}; + +/*! @brief SGTL SCLK valid edge */ +typedef enum _sgtl_sclk_edge +{ + sgtl_sclk_valid_edge_rising = 0U, /*!< SCLK valid edge */ + sgtl_sclk_valid_edge_failing = 1U, /*!< SCLK failling edge */ +} sgtl_sclk_edge_t; + +/*! @brief Audio format configuration. */ +typedef struct _sgtl_audio_format +{ + uint32_t mclk_hz; /*!< master clock */ + uint32_t sample_rate; /*!< Sample rate */ + uint32_t bit_width; /*!< Bit width */ + sgtl_sclk_edge_t sclk_edge; /*!< sclk valid edge */ +} sgtl_audio_format_t; + +/*! @brief Initailize structure of sgtl5000 */ +typedef struct _sgtl_config +{ + sgtl_route_t route; /*!< Audio data route.*/ + sgtl_protocol_t bus; /*!< Audio transfer protocol */ + bool master; /*!< Master or slave. True means master, false means slave. */ + sgtl_audio_format_t format; /*!< audio format */ +} sgtl_config_t; + +typedef struct +{ + struct rt_i2c_bus_device *i2c_bus; /* I2C bus device */ + uint8_t slave_address; /*!< code device slave address */ +} sgtl_context_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief sgtl5000 initialize function. + * + * In this function, some configurations are fixed. + * The second parameter can be NULL. If users want to change the SGTL5000 settings, + * a configure structure should be prepared. + * @note If the codec_config is NULL, it would initialize sgtl5000 using default settings. + * The default setting: + * @code + * sgtl_init_t codec_config + * codec_config.route = sgtl_route_playback_record + * codec_config.bus = sgtl_bus_i2s + * codec_config.master = slave + * @endcode + * + * @param context Sgtl5000 context structure. + * @param config sgtl5000 configuration structure. If this pointer equals to NULL, + * it means using the default configuration. + * @return Initialization status + */ +hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config); + +/*! + * @brief Set audio data route in sgtl5000. + * + * This function would set the data route according to route. The route cannot be combined, + * as all route would enable different modules. + * + * @note If a new route is set, the previous route would not work. + * @param context Sgtl5000 context structure. + * @param route Audio data route in sgtl5000. + */ +hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route); + +/*! + * @brief Set the audio transfer protocol. + * + * Sgtl5000 only supports I2S, I2S left, I2S right, PCM A, PCM B format. + * @param context Sgtl5000 context structure. + * @param protocol Audio data transfer protocol. + */ +hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol); + +/*! + * @brief Set sgtl5000 as master or slave. + * + * @param context Sgtl5000 context structure. + * @param master 1 represent master, 0 represent slave. + */ +void sgtl_set_master_mode(sgtl_context_t *context, bool master); + +/*! + * @brief Set the volume of different modules in sgtl5000. + * + * This function would set the volume of sgtl5000 modules. This interface set module volume. + * The function assume that left channel and right channel has the same volume. + * + * sgtl_module_adc volume range: 0 - 0xF, 0dB - 22.5dB + * sgtl_module_dac volume range: 0x3C - 0xF0, 0dB - -90dB + * sgtl_module_hp volume range: 0 - 0x7F, 12dB - -51.5dB + * sgtl_module_lineout volume range: 0 - 0x1F, 0.5dB steps + * + * @param context Sgtl5000 context structure. + * @param module Sgtl5000 module, such as DAC, ADC and etc. + * @param volume Volume value need to be set. The value is the exact value in register. + */ +hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32_t volume); + +/*! + * @brief Get the volume of different modules in sgtl5000. + * + * This function gets the volume of sgtl5000 modules. This interface get DAC module volume. + * The function assume that left channel and right channel has the same volume. + * @param context Sgtl5000 context structure. + * @param module Sgtl5000 module, such as DAC, ADC and etc. + * @return Module value, the value is exact value in register. + */ +uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module); + +/*! + * @brief Mute/unmute modules in sgtl5000. + * + * @param context Sgtl5000 context structure. + * @param module Sgtl5000 module, such as DAC, ADC and etc. + * @param mute True means mute, and false means unmute. + */ +hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute); + +/*! + * @brief Enable expected devices. + * @param context Sgtl5000 context structure. + * @param module Module expected to enable. + */ +hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module); + +/*! + * @brief Disable expected devices. + * @param context Sgtl5000 context structure. + * @param module Module expected to enable. + */ +hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module); + +/*! + * @brief Deinit the sgtl5000 codec. Shut down Sgtl5000 modules. + * @param context Sgtl5000 context structure pointer. + */ +hpm_stat_t sgtl_deint(sgtl_context_t *context); + +/*! + * @brief Configure the data format of audio data. + * + * This function would configure the registers about the sample rate, bit depths. + * @param context Sgtl5000 context structure pointer. + * @param mclk Master clock frequency of I2S. + * @param sample_rate Sample rate of audio file running in sgtl5000. Sgtl5000 now + * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. + * @param bits Bit depth of audio file (Sgtl5000 only supports 16bit, 20bit, 24bit + * and 32 bit in HW). + */ +hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits); + +/*! + * @brief select SGTL codec play source. + * + * @param context Sgtl5000 context structure pointer. + * @param playSource play source value, reference _sgtl_play_source. + * + * @return kStatus_Success, else failed. + */ +hpm_stat_t sgtl_set_play(sgtl_context_t *context, uint32_t playSource); + +/*! + * @brief select SGTL codec record source. + * + * @param context Sgtl5000 context structure pointer. + * @param recordSource record source value, reference _sgtl_record_source. + * + * @return kStatus_Success, else failed. + */ +hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource); + +/*! + * @brief Write register to sgtl using I2C. + * @param context Sgtl5000 context structure. + * @param reg The register address in sgtl. + * @param val Value needs to write into the register. + */ +hpm_stat_t sgtl_write_reg(sgtl_context_t *context, uint16_t reg, uint16_t val); + +/*! + * @brief Read register from sgtl using I2C. + * @param context Sgtl5000 context structure. + * @param reg The register address in sgtl. + * @param val Value written to. + */ +hpm_stat_t sgtl_read_reg(sgtl_context_t *context, uint16_t reg, uint16_t *val); + +/*! + * @brief Modify some bits in the register using I2C. + * @param context Sgtl5000 context structure. + * @param reg The register address in sgtl. + * @param clr_mask The mask code for the bits want to write. The bit you want to write should be 0. + * @param val Value needs to write into the register. + */ +hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_mask, uint16_t val); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _HPM_SGTL5000_H_ */ diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld new file mode 100644 index 0000000000..f728b0414e --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,255 @@ +/* + * Copyright 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*cpuport.o (.text .text* .rodata .rodata*)) + KEEP(*trap_entry.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__; + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld new file mode 100644 index 0000000000..915330acb9 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld @@ -0,0 +1,256 @@ +/* + * Copyright 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 1M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01100000, LENGTH = NONCACHEABLE_SIZE +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*cpuport.o (.text .text* .rodata .rodata*)) + KEEP(*trap_entry.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__; + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld new file mode 100644 index 0000000000..4b63b46ca6 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,214 @@ +/* + * Copyright 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + /* It's alias address of core0 ILM+DLM, but accessing via system bus */ + CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K + /* It's alias address of core1 ILM+DLM, but accessing via system bus */ + CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE +} + +SECTIONS +{ + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_execpt_table)) + KEEP(*(.gcc_execpt_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE + __noncacheable_start__ = ORIGIN(NONCACHEABLE); + __noncacheable_end__ = ORIGIN(NONCACHEABLE) + LENGTH(NONCACHEABLE); + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + } > DLM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > SDRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evk/board/pinmux.c b/bsp/hpmicro/hpm6750evk/board/pinmux.c new file mode 100644 index 0000000000..0ad35b7570 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/pinmux.c @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + } else if (ptr == HPM_UART2) { + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD; + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD; + } else if (ptr == HPM_UART13) { + HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD; + HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD; + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; + } +} + +void init_lcd_pins(LCDC_Type *ptr) +{ + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1; + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_3; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_DIS0_R_4; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_DIS0_R_5; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_DIS0_R_6; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_7; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_G_0; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_1; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_DIS0_G_2; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_DIS0_G_3; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_DIS0_G_4; + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_DIS0_G_5; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_G_6; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_DIS0_G_7; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_B_0; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_1; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_2; + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_B_3; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_B_4; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_B_5; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_B_6; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_B_7; + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_CLK; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_EN; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_DIS0_VSYNC; + + /* PWM */ + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10; + /* RST */ + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_GPIO_B_16; +} + +void init_cap_pins(void) +{ + /* CAP_INT */ + HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPIO_B_08; + /* CAP_RST */ + HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09; +} + +void init_trgmux_pins(uint32_t pin) +{ + /* all trgmux pin ALT_SELECT fixed to 16*/ + HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); +} + +void init_i2c_pins_as_gpio(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + /* I2C0 */ + HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_GPIO_Z_11; + HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; + HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_GPIO_Z_10; + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3; + } else { + while(1); + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2C0_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3; + HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else { + while(1); + } +} + +void init_sdram_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); +} + +void init_gpio_pins(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + +#ifdef USING_GPIO0_FOR_GPIOZ + HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; + HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; +#endif +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_SPI2_CSN; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + +void init_pins(void) +{ + init_uart_pins(BOARD_CONSOLE_BASE); + init_sdram_pins(); +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR3) { + /* TMR3 compare 1 */ + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR3_COMP_1; + } + if (ptr == HPM_GPTMR4) { + /* TMR4 capture 1 */ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1; + } +} + +void init_hall_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_TRGM2_P_06; + HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_TRGM2_P_07; + HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_TRGM2_P_08; +} + +void init_qei_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_TRGM2_P_09; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; +} + +void init_i2s_pins(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PF02_FUNC_CTL_I2S0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_I2S0_MCLK; + HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_I2S0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_I2S0_BCLK; + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2S0_FCLK; + } +} + +void init_dao_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_DAOR_P; + HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08; + HPM_IOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_DAOR_N; + HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_SOC_PY_09; +} + +void init_pdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK; + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; + HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11; +} + +void init_vad_pins(void) +{ + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT; +} + +void init_cam_pins(void) +{ +#ifdef CAMREA_RESET_PWDN_CONFIGURABLE + HPM_IOC->PAD[IOC_PAD_PX08].FUNC_CTL = IOC_PX08_FUNC_CTL_GPIO_X_08; + HPM_IOC->PAD[IOC_PAD_PX09].FUNC_CTL = IOC_PX09_FUNC_CTL_GPIO_X_09; +#endif + + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK; + HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_CAM0_VSYNC; + HPM_IOC->PAD[IOC_PAD_PA05].FUNC_CTL = IOC_PA05_FUNC_CTL_CAM0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_CAM0_D_2; + HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_CAM0_D_3; + HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_CAM0_D_4; + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_CAM0_D_5; + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_CAM0_D_6; + HPM_IOC->PAD[IOC_PAD_PA04].FUNC_CTL = IOC_PA04_FUNC_CTL_CAM0_D_7; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_CAM0_D_8; + HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_CAM0_D_9; +} + +void init_butn_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED; +} + +void init_acmp_pins(void) +{ + /* configure to ACMP_COMP_1(ALT16) function */ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ACMP_COMP_1; + /* configure to CMP1_INP7 function */ + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* configure to CMP1_INN6 function */ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_enet_pins(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_GPIO_F_00; + + HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_ETH0_MDC; + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_ETH0_MDIO; + + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_ETH0_RXD_0; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_ETH0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_ETH0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_ETH0_RXD_3; + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_ETH0_RXCK; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_ETH0_RXDV; + + HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_ETH0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_ETH0_TXD_1; + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_ETH0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_ETH0_TXD_3; + HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_ETH0_TXCK; + HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_ETH0_TXEN; + } else if (ptr == HPM_ENET1) { + HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_GPIO_E_26; + + HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC; + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO; + + HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0; + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1; + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV; + + HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0; + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1; + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN; + + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK | IOC_PE16_FUNC_CTL_ETH1_REFCLK; + } +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM3) { + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_PWM3_P_6; + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_PWM3_P_7; + } else if (ptr == HPM_PWM2) { + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_PWM2_P_5; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_PWM2_P_4; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_PWM2_P_1; + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_PWM2_P_0; + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_PWM2_P_3; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_PWM2_P_2; + } +} + +void init_adc12_pins(void) +{ + /* ADC0/1/2.VIN7 */ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2.VIN10 */ + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2.VIN11 */ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc16_pins(void) +{ + /* ADC3.INA2 */ + HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_usb_pins(void) +{ + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10; + HPM_IOC->PAD[IOC_PAD_PF10].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; + HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + + /* USB1_ID */ + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07; + HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + + /* USB1_OC */ + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_GPIO_F_05; + HPM_IOC->PAD[IOC_PAD_PF05].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); +} + +void init_can_pins(CAN_Type *ptr) +{ + if (ptr == HPM_CAN0) { + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_CAN0_TXD; + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_CAN0_RXD; + } +} + +void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8) +{ + uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);; + uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_SDXC0) { + } else if (ptr == HPM_SDXC1) { + /* CLK */ + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; + + /* CMD */ + HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl; + HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl; + + /* DATA0 */ + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; + /* DATA1 */ + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; + /* DATA2 */ + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; + /* DATA3 */ + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; + + /* CDN */ + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; + HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = pad_ctl; + HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN; + + } +} + +void init_clk_obs_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; +} + +void init_rgb_pwm_pins(void) +{ + /* Red */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_TRGM1_P_01; + /* Green */ + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_TRGM0_P_06; + /* BLUE */ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_TRGM1_P_03; +} + +void init_led_pins_as_gpio(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; + HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; + HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; +} diff --git a/bsp/hpmicro/hpm6750evk/board/pinmux.h b/bsp/hpmicro/hpm6750evk/board/pinmux.h new file mode 100644 index 0000000000..faa0a72c1d --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/pinmux.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_uart_pins(UART_Type *ptr); +void init_lcd_pins(LCDC_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_cap_pins(void); +void init_sdram_pins(void); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_pins(void); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_i2s_pins(I2S_Type *ptr); +void init_dao_pins(void); +void init_pdm_pins(void); +void init_vad_pins(void); +void init_cam_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_enet_pins(ENET_Type *ptr); +void init_pwm_pins(PWM_Type *ptr); +void init_adc12_pins(void); +void init_adc16_pins(void); +void init_usb_pins(void); +void init_can_pins(CAN_Type *ptr); +void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8); +void init_adc_bldc_pins(void); +void init_rgb_pwm_pins(void); +void init_i2c_pins_as_gpio(I2C_Type *ptr); +void init_led_pins_as_gpio(void); +void init_trgmux_pins(uint32_t pin); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm6750evk/board/rtt_board.c b/bsp/hpmicro/hpm6750evk/board/rtt_board.c new file mode 100644 index 0000000000..f16cd34489 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/rtt_board.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_mchtmr_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_manager.h" + +void os_tick_config(void); + +extern int rt_hw_uart_init(void); + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_manager_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); + gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); + gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); + + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, APP_LED_OFF); +} + +void app_led_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state); + break; + case 1: + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, state); + break; + case 2: + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + + enable_mchtmr_irq(); +} + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_interrupt_enter(); + rt_tick_increase(); + rt_interrupt_leave(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_HOT &= ~(1UL << 31); + HPM_PPOR->RESET_COLD |= (1UL << 31); + + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); diff --git a/bsp/hpmicro/hpm6750evk/board/rtt_board.h b/bsp/hpmicro/hpm6750evk/board/rtt_board.h new file mode 100644 index 0000000000..de60e7f9f8 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/rtt_board.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" + +/* gpio section */ +#define APP_LED0_GPIO_CTRL HPM_GPIO0 +#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOB +#define APP_LED0_GPIO_PIN 11 +#define APP_LED1_GPIO_CTRL HPM_GPIO0 +#define APP_LED1_GPIO_INDEX GPIO_DI_GPIOB +#define APP_LED1_GPIO_PIN 12 +#define APP_LED2_GPIO_CTRL HPM_GPIO0 +#define APP_LED2_GPIO_INDEX GPIO_DI_GPIOB +#define APP_LED2_GPIO_PIN 13 +#define APP_LED_ON (0) +#define APP_LED_OFF (1) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* SPI WIFI section */ +#define RW007_RST_PIN (IOC_PAD_PE02) +#define RW007_INT_BUSY_PIN (IOC_PAD_PE01) +#define RW007_CS_PIN (IOC_PAD_PE03) +#define RW007_CS_GPIO (HPM_GPIO0) +#define RW007_SPI_BUS_NAME "spi1" + + +/* CAN section */ +#define BOARD_CAN_NAME "can0" + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); + + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm6750evk/makefile.targets b/bsp/hpmicro/hpm6750evk/makefile.targets new file mode 100644 index 0000000000..502182f4e7 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard ../board/linker_scripts/flash_xip_rtt.ld) diff --git a/bsp/hpmicro/hpm6750evk/rtconfig.h b/bsp/hpmicro/hpm6750evk/rtconfig.h new file mode 100644 index 0000000000..7e7fd18386 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/rtconfig.h @@ -0,0 +1,207 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50000 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_LEGACY +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_RTC + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Sensor libraries */ + + +/* Display libraries */ + + +/* Timing libraries */ + + +/* Project libraries */ + + +/* Hardware Drivers Config */ + +#define SOC_HPM6000 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_RTC +#define BSP_USING_DRAM +#define INIT_EXT_RAM_FOR_DATA + +#endif diff --git a/bsp/hpmicro/hpm6750evk/rtconfig.py b/bsp/hpmicro/hpm6750evk/rtconfig.py new file mode 100644 index 0000000000..63c7cc149d --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/rtconfig.py @@ -0,0 +1,94 @@ +# Copyright 2021-2022 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' + +CHIP_NAME='HPM6750' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compilercute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + + + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -std=gnu11 -DUSE_NONVECTOR_MODE=1' + ARCH_ABI = ' -mcmodel=medlow ' + CFLAGS = DEVICE + ARCH_ABI + ' -ffunction-sections -fdata-sections -fno-common' + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + else: + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' diff --git a/bsp/hpmicro/hpm6750evk/rtconfig_preinc.h b/bsp/hpmicro/hpm6750evk/rtconfig_preinc.h new file mode 100644 index 0000000000..0ad85f00e4 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/rtconfig_preinc.h @@ -0,0 +1,16 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D45 +#define HAVE_CCONFIG_H +#define HPM6750 +#define RT_USING_NEWLIB +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6360/SConscript b/bsp/hpmicro/hpm6750evk/startup/HPM6360/SConscript new file mode 100644 index 0000000000..18c366ba28 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6360/SConscript @@ -0,0 +1,21 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Split(''' + startup.c + trap.c +''') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6360/startup.c b/bsp/hpmicro/hpm6750evk/startup/HPM6360/startup.c new file mode 100644 index 0000000000..5d6123bd09 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6360/startup.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/start.S new file mode 100644 index 0000000000..17f48174db --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/start.S @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_in_dlm + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Disable Vector mode */ + csrci CSR_MMISC_CTL, 2 + + /* Initialize trap_entry base */ + la t0, irq_handler_trap + csrw mtvec, t0 + + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S new file mode 100644 index 0000000000..39fdb20af5 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* ADC0 IRQ handler */ + IRQ_HANDLER 9 /* ADC1 IRQ handler */ + IRQ_HANDLER 10 /* ADC2 IRQ handler */ + IRQ_HANDLER 11 /* DAC IRQ handler */ + IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 14 /* SPI0 IRQ handler */ + IRQ_HANDLER 15 /* SPI1 IRQ handler */ + IRQ_HANDLER 16 /* SPI2 IRQ handler */ + IRQ_HANDLER 17 /* SPI3 IRQ handler */ + IRQ_HANDLER 18 /* UART0 IRQ handler */ + IRQ_HANDLER 19 /* UART1 IRQ handler */ + IRQ_HANDLER 20 /* UART2 IRQ handler */ + IRQ_HANDLER 21 /* UART3 IRQ handler */ + IRQ_HANDLER 22 /* UART4 IRQ handler */ + IRQ_HANDLER 23 /* UART5 IRQ handler */ + IRQ_HANDLER 24 /* UART6 IRQ handler */ + IRQ_HANDLER 25 /* UART7 IRQ handler */ + IRQ_HANDLER 26 /* CAN0 IRQ handler */ + IRQ_HANDLER 27 /* CAN1 IRQ handler */ + IRQ_HANDLER 28 /* PTPC IRQ handler */ + IRQ_HANDLER 29 /* WDG0 IRQ handler */ + IRQ_HANDLER 30 /* WDG1 IRQ handler */ + IRQ_HANDLER 31 /* TSNS IRQ handler */ + IRQ_HANDLER 32 /* MBX0A IRQ handler */ + IRQ_HANDLER 33 /* MBX0B IRQ handler */ + IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 38 /* I2C0 IRQ handler */ + IRQ_HANDLER 39 /* I2C1 IRQ handler */ + IRQ_HANDLER 40 /* I2C2 IRQ handler */ + IRQ_HANDLER 41 /* I2C3 IRQ handler */ + IRQ_HANDLER 42 /* PWM0 IRQ handler */ + IRQ_HANDLER 43 /* HALL0 IRQ handler */ + IRQ_HANDLER 44 /* QEI0 IRQ handler */ + IRQ_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_HANDLER 46 /* HALL1 IRQ handler */ + IRQ_HANDLER 47 /* QEI1 IRQ handler */ + IRQ_HANDLER 48 /* SDP IRQ handler */ + IRQ_HANDLER 49 /* XPI0 IRQ handler */ + IRQ_HANDLER 50 /* XPI1 IRQ handler */ + IRQ_HANDLER 51 /* XDMA IRQ handler */ + IRQ_HANDLER 52 /* HDMA IRQ handler */ + IRQ_HANDLER 53 /* DRAM IRQ handler */ + IRQ_HANDLER 54 /* RNG IRQ handler */ + IRQ_HANDLER 55 /* I2S0 IRQ handler */ + IRQ_HANDLER 56 /* I2S1 IRQ handler */ + IRQ_HANDLER 57 /* DAO IRQ handler */ + IRQ_HANDLER 58 /* PDM IRQ handler */ + IRQ_HANDLER 59 /* FFA IRQ handler */ + IRQ_HANDLER 60 /* NTMR0 IRQ handler */ + IRQ_HANDLER 61 /* USB0 IRQ handler */ + IRQ_HANDLER 62 /* ENET0 IRQ handler */ + IRQ_HANDLER 63 /* SDXC0 IRQ handler */ + IRQ_HANDLER 64 /* PSEC IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PWDG IRQ handler */ + IRQ_HANDLER 67 /* PTMR IRQ handler */ + IRQ_HANDLER 68 /* PUART IRQ handler */ + IRQ_HANDLER 69 /* FUSE IRQ handler */ + IRQ_HANDLER 70 /* SECMON IRQ handler */ + IRQ_HANDLER 71 /* RTC IRQ handler */ + IRQ_HANDLER 72 /* BUTN IRQ handler */ + IRQ_HANDLER 73 /* BGPIO IRQ handler */ + IRQ_HANDLER 74 /* BVIO IRQ handler */ + IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6360/trap.c b/bsp/hpmicro/hpm6750evk/startup/HPM6360/trap.c new file mode 100644 index 0000000000..68ce432bd4 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6360/trap.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "riscv-stackframe.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +static void rt_show_stack_frame(void); + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + rt_kprintf("mdcause: FP disabled exception \r\n"); + break; + case 2: + rt_kprintf("mdcause: ACE disabled exception \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + rt_kprintf("mdcause: PMA NAMO exception \r\n"); + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + default: + rt_kprintf("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_show_stack_frame(); + while (1) + { + } +} + +void trap_entry(rt_hw_stack_frame_t *stack_frame); + +void trap_entry(rt_hw_stack_frame_t *stack_frame) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + + s_stack_frame = stack_frame; + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +static void rt_show_stack_frame(void) +{ + rt_kprintf("Stack frame:\r\n----------------------------------------\r\n"); + rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra); + rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS)); + rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); + rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); + rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2); + rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); + rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1); + rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2); + rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3); + rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4); + rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5); + rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6); + rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7); + rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3); + rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4); + rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5); + rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); +} diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/SConscript b/bsp/hpmicro/hpm6750evk/startup/HPM6750/SConscript new file mode 100644 index 0000000000..18c366ba28 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/SConscript @@ -0,0 +1,21 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Split(''' + startup.c + trap.c +''') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c new file mode 100644 index 0000000000..5d6123bd09 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S new file mode 100644 index 0000000000..2ccc4540ac --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_in_dlm + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Disable Vector mode */ + csrci CSR_MMISC_CTL, 2 + /* Initialize trap_entry base */ + la t0, irq_handler_trap + csrw mtvec, t0 + + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/vectors.S new file mode 100644 index 0000000000..7ac2b728b0 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/vectors.S @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + .section .vector_table, "a" + .global __vector_table + .align 9 +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_E IRQ handler */ + IRQ_HANDLER 15 /* GPIO1_F IRQ handler */ + IRQ_HANDLER 16 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 17 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 18 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 19 /* ADC0 IRQ handler */ + IRQ_HANDLER 20 /* ADC1 IRQ handler */ + IRQ_HANDLER 21 /* ADC2 IRQ handler */ + IRQ_HANDLER 22 /* ADC3 IRQ handler */ + IRQ_HANDLER 23 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 25 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 26 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 27 /* SPI0 IRQ handler */ + IRQ_HANDLER 28 /* SPI1 IRQ handler */ + IRQ_HANDLER 29 /* SPI2 IRQ handler */ + IRQ_HANDLER 30 /* SPI3 IRQ handler */ + IRQ_HANDLER 31 /* UART0 IRQ handler */ + IRQ_HANDLER 32 /* UART1 IRQ handler */ + IRQ_HANDLER 33 /* UART2 IRQ handler */ + IRQ_HANDLER 34 /* UART3 IRQ handler */ + IRQ_HANDLER 35 /* UART4 IRQ handler */ + IRQ_HANDLER 36 /* UART5 IRQ handler */ + IRQ_HANDLER 37 /* UART6 IRQ handler */ + IRQ_HANDLER 38 /* UART7 IRQ handler */ + IRQ_HANDLER 39 /* UART8 IRQ handler */ + IRQ_HANDLER 40 /* UART9 IRQ handler */ + IRQ_HANDLER 41 /* UART10 IRQ handler */ + IRQ_HANDLER 42 /* UART11 IRQ handler */ + IRQ_HANDLER 43 /* UART12 IRQ handler */ + IRQ_HANDLER 44 /* UART13 IRQ handler */ + IRQ_HANDLER 45 /* UART14 IRQ handler */ + IRQ_HANDLER 46 /* UART15 IRQ handler */ + IRQ_HANDLER 47 /* CAN0 IRQ handler */ + IRQ_HANDLER 48 /* CAN1 IRQ handler */ + IRQ_HANDLER 49 /* CAN2 IRQ handler */ + IRQ_HANDLER 50 /* CAN3 IRQ handler */ + IRQ_HANDLER 51 /* PTPC IRQ handler */ + IRQ_HANDLER 52 /* WDG0 IRQ handler */ + IRQ_HANDLER 53 /* WDG1 IRQ handler */ + IRQ_HANDLER 54 /* WDG2 IRQ handler */ + IRQ_HANDLER 55 /* WDG3 IRQ handler */ + IRQ_HANDLER 56 /* MBX0_CA IRQ handler */ + IRQ_HANDLER 57 /* MBX0_CB IRQ handler */ + IRQ_HANDLER 58 /* MBX1_CA IRQ handler */ + IRQ_HANDLER 59 /* MBX1_CB IRQ handler */ + IRQ_HANDLER 60 /* TMR0 IRQ handler */ + IRQ_HANDLER 61 /* TMR1 IRQ handler */ + IRQ_HANDLER 62 /* TMR2 IRQ handler */ + IRQ_HANDLER 63 /* TMR3 IRQ handler */ + IRQ_HANDLER 64 /* TMR4 IRQ handler */ + IRQ_HANDLER 65 /* TMR5 IRQ handler */ + IRQ_HANDLER 66 /* TMR6 IRQ handler */ + IRQ_HANDLER 67 /* TMR7 IRQ handler */ + IRQ_HANDLER 68 /* I2C0 IRQ handler */ + IRQ_HANDLER 69 /* I2C1 IRQ handler */ + IRQ_HANDLER 70 /* I2C2 IRQ handler */ + IRQ_HANDLER 71 /* I2C3 IRQ handler */ + IRQ_HANDLER 72 /* PWM0 IRQ handler */ + IRQ_HANDLER 73 /* HAL0 IRQ handler */ + IRQ_HANDLER 74 /* ENC0 IRQ handler */ + IRQ_HANDLER 75 /* PWM1 IRQ handler */ + IRQ_HANDLER 76 /* HAL1 IRQ handler */ + IRQ_HANDLER 77 /* ENC1 IRQ handler */ + IRQ_HANDLER 78 /* PWM2 IRQ handler */ + IRQ_HANDLER 79 /* HAL2 IRQ handler */ + IRQ_HANDLER 80 /* ENC2 IRQ handler */ + IRQ_HANDLER 81 /* PWM3 IRQ handler */ + IRQ_HANDLER 82 /* HAL3 IRQ handler */ + IRQ_HANDLER 83 /* ENC3 IRQ handler */ + IRQ_HANDLER 84 /* SDP IRQ handler */ + IRQ_HANDLER 85 /* XPI0 IRQ handler */ + IRQ_HANDLER 86 /* XPI1 IRQ handler */ + IRQ_HANDLER 87 /* XDMA IRQ handler */ + IRQ_HANDLER 88 /* HDMA IRQ handler */ + IRQ_HANDLER 89 /* DRAM IRQ handler */ + IRQ_HANDLER 90 /* RNG IRQ handler */ + IRQ_HANDLER 91 /* I2S0 IRQ handler */ + IRQ_HANDLER 92 /* I2S1 IRQ handler */ + IRQ_HANDLER 93 /* I2S2 IRQ handler */ + IRQ_HANDLER 94 /* I2S3 IRQ handler */ + IRQ_HANDLER 95 /* I2SCLASSD IRQ handler */ + IRQ_HANDLER 96 /* I2SPDM IRQ handler */ + IRQ_HANDLER 97 /* CAM0 IRQ handler */ + IRQ_HANDLER 98 /* CAM1 IRQ handler */ + IRQ_HANDLER 99 /* LCD_D0 IRQ handler */ + IRQ_HANDLER 100 /* LCD_D1 IRQ handler */ + IRQ_HANDLER 101 /* PDMA_D0 IRQ handler */ + IRQ_HANDLER 102 /* PDMA_D1 IRQ handler */ + IRQ_HANDLER 103 /* JPEG IRQ handler */ + IRQ_HANDLER 104 /* NTM0 IRQ handler */ + IRQ_HANDLER 105 /* NTM1 IRQ handler */ + IRQ_HANDLER 106 /* USB0 IRQ handler */ + IRQ_HANDLER 107 /* USB1 IRQ handler */ + IRQ_HANDLER 108 /* ENET0 IRQ handler */ + IRQ_HANDLER 109 /* ENET1 IRQ handler */ + IRQ_HANDLER 110 /* SDXC0 IRQ handler */ + IRQ_HANDLER 111 /* SDXC1 IRQ handler */ + IRQ_HANDLER 112 /* SEC_EVENT IRQ handler */ + IRQ_HANDLER 113 /* PMIC_GPIO IRQ handler */ + IRQ_HANDLER 114 /* PMIC_WDG IRQ handler */ + IRQ_HANDLER 115 /* PMIC_TMR IRQ handler */ + IRQ_HANDLER 116 /* PMIC_UART IRQ handler */ + IRQ_HANDLER 117 /* VAD IRQ handler */ + IRQ_HANDLER 118 /* FUSE IRQ handler */ + IRQ_HANDLER 119 /* SECMON IRQ handler */ + IRQ_HANDLER 120 /* BATT_RTC IRQ handler */ + IRQ_HANDLER 121 /* BUTTON IRQ handler */ + IRQ_HANDLER 122 /* BATT_GPIO IRQ handler */ + IRQ_HANDLER 123 /* VIOLATION IRQ handler */ + IRQ_HANDLER 124 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 125 /* CLK_FAIL IRQ handler */ + IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */ diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c b/bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c new file mode 100644 index 0000000000..68ce432bd4 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "riscv-stackframe.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +static void rt_show_stack_frame(void); + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + rt_kprintf("mdcause: FP disabled exception \r\n"); + break; + case 2: + rt_kprintf("mdcause: ACE disabled exception \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + rt_kprintf("mdcause: PMA NAMO exception \r\n"); + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + default: + rt_kprintf("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_show_stack_frame(); + while (1) + { + } +} + +void trap_entry(rt_hw_stack_frame_t *stack_frame); + +void trap_entry(rt_hw_stack_frame_t *stack_frame) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + + s_stack_frame = stack_frame; + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +static void rt_show_stack_frame(void) +{ + rt_kprintf("Stack frame:\r\n----------------------------------------\r\n"); + rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra); + rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS)); + rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); + rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); + rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2); + rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); + rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1); + rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2); + rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3); + rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4); + rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5); + rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6); + rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7); + rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3); + rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4); + rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5); + rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); +} diff --git a/bsp/hpmicro/hpm6750evk/startup/SConscript b/bsp/hpmicro/hpm6750evk/startup/SConscript new file mode 100644 index 0000000000..de51a7c0d6 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/.config b/bsp/hpmicro/hpm6750evkmini/.config new file mode 100644 index 0000000000..270be34aba --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/.config @@ -0,0 +1,717 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# CONFIG_RT_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +CONFIG_RT_USING_LEGACY=y +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Sensor libraries +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display libraries +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set + +# +# Timing libraries +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Project libraries +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM6000=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_RW007_USING_BLE is not set +# CONFIG_RW007_USING_WIFI is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART13 is not set +# CONFIG_BSP_USING_UART14 is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_RTC=y +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_SDXC is not set +# CONFIG_BSP_USING_TOUCH is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_LVGL is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +CONFIG_BSP_USING_DRAM=y +CONFIG_INIT_EXT_RAM_FOR_DATA=y +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_DAO is not set +# CONFIG_BSP_USING_PDM is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_WDG is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_ADC is not set diff --git a/bsp/hpmicro/hpm6750evkmini/.settings/blink_led.OpenOCD.Debug.rttlaunch b/bsp/hpmicro/hpm6750evkmini/.settings/blink_led.OpenOCD.Debug.rttlaunch new file mode 100644 index 0000000000..b0ccdd0117 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/.settings/blink_led.OpenOCD.Debug.rttlaunch @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/hpm6750evkmini/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs b/bsp/hpmicro/hpm6750evkmini/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs new file mode 100644 index 0000000000..131f98bfbb --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +toolchain.path.512258282=${toolchain_install_path}/RISC-V/RISC-V-GCC-RV32/2022-04-12/bin diff --git a/bsp/hpmicro/hpm6750evkmini/.settings/language.settings.xml b/bsp/hpmicro/hpm6750evkmini/.settings/language.settings.xml new file mode 100644 index 0000000000..89463fc038 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/hpm6750evkmini/.settings/org.eclipse.core.resources.prefs b/bsp/hpmicro/hpm6750evkmini/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000000..99f26c0203 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/bsp/hpmicro/hpm6750evkmini/.settings/org.eclipse.core.runtime.prefs b/bsp/hpmicro/hpm6750evkmini/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 0000000000..9f1acfcfba --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/.settings/projcfg.ini b/bsp/hpmicro/hpm6750evkmini/.settings/projcfg.ini new file mode 100644 index 0000000000..1ae5ab7322 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/.settings/projcfg.ini @@ -0,0 +1,19 @@ +#RT-Thread Studio Project Configuration +#Thu Feb 17 15:17:36 CST 2022 +cfg_version=v3.0 +board_name=HPM6750EVKMINI +example_name=blink_led +hardware_adapter=FT2232 +project_type=rt-thread +board_base_nano_proj=False +chip_name=HPM6750 +selected_rtt_version=4.0.5 +bsp_version=0.3.0 +os_branch=full +output_project_path=C\:/DevTools/RT-ThreadStudio/workspace +is_base_example_project=True +is_use_scons_build=True +project_base_bsp=true +project_name=blink_led +os_version=4.0.5 +bsp_path=repo/Local/Board_Support_Packages/HPMicro/HPM6750EVKMINI/0.3.0(offline)/hpm6750-rtt-bsp diff --git a/bsp/hpmicro/hpm6750evkmini/Kconfig b/bsp/hpmicro/hpm6750evkmini/Kconfig new file mode 100644 index 0000000000..79b160b856 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hpmicro/hpm6750evkmini/SConscript b/bsp/hpmicro/hpm6750evkmini/SConscript new file mode 100644 index 0000000000..bb673e4f18 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/SConstruct b/bsp/hpmicro/hpm6750evkmini/SConstruct new file mode 100644 index 0000000000..3dadc575c0 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6750evkmini/applications/SConscript b/bsp/hpmicro/hpm6750evkmini/applications/SConscript new file mode 100644 index 0000000000..a65aa4d855 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/applications/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6750evkmini/applications/main.c b/bsp/hpmicro/hpm6750evkmini/applications/main.c new file mode 100644 index 0000000000..b766dd547e --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/applications/main.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2021 hpmicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" + +void thread_entry(void *arg); + + + +int main(void) +{ + + app_init_led_pins(); + + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + + +void thread_entry(void *arg) +{ + while(1){ + app_led_write(0, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(0, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/Kconfig b/bsp/hpmicro/hpm6750evkmini/board/Kconfig new file mode 100644 index 0000000000..a4ab7880bf --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/Kconfig @@ -0,0 +1,417 @@ +menu "Hardware Drivers Config" + +config SOC_HPM6000 + bool + select SOC_SERIES_HPM6000 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + config RW007_USING_BLE + bool "Enable RW007 BLE" + default n + select RT_USING_SPI if RW007_USING_BLE + select BSP_USING_SPI1 if RW007_USING_BLE + + config RW007_USING_WIFI + bool "Enable RW007 WIFI" + select RT_USING_SPI if RW007_USING_BLE + select BSP_USING_SPI1 if RW007_USING_BLE + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_DMA_CHANNEL + int "Set UART0 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART0_TX_DMA_CHANNEL + int "Set UART0 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_DMA_CHANNEL + int "Set UART6 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART6_TX_DMA_CHANNEL + int "Set UART6 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART13 + bool "Enable UART13" + default n + if BSP_USING_UART13 + config BSP_UART13_RX_USING_DMA + bool "Enable UART13 RX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default n + + config BSP_UART13_TX_USING_DMA + bool "Enable UART13 TX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default n + + config BSP_UART13_RX_DMA_CHANNEL + int "Set UART13 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART13_TX_DMA_CHANNEL + int "Set UART13 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART13_RX_BUFSIZE + int "Set UART13 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART13_TX_BUFSIZE + int "Set UART13 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART14 + bool "Enable UART14" + default n + if BSP_USING_UART14 + config BSP_UART14_RX_USING_DMA + bool "Enable UART14 RX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default n + + config BSP_UART14_TX_USING_DMA + bool "Enable UART14 TX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default n + + config BSP_UART14_RX_DMA_CHANNEL + int "Set UART14 RX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default 0 + + config BSP_UART14_TX_DMA_CHANNEL + int "Set UART14 TX DMA CHANNEL" + range 0 7 + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default 1 + + config BSP_UART14_RX_BUFSIZE + int "Set UART14 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + + config BSP_UART14_TX_BUFSIZE + int "Set UART14 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default y + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_ETH + if BSP_USING_ETH + config BSP_USING_ETH1 + bool "Enable ETH1" + default n + endif + + menuconfig BSP_USING_SDXC + bool "Enable SDXC" + default n + select RT_USING_SDIO if BSP_USING_SDXC + if BSP_USING_SDXC + config BSP_USING_SDXC0 + bool "Enable SDXC0" + default n + + config BSP_USING_SDXC1 + bool "Enable SDXC1" + default y + endif + + menuconfig BSP_USING_TOUCH + bool "Enable touch" + default n + if BSP_USING_TOUCH + config BSP_USING_TOUCH_GT911 + bool "Enable GT911" + default y + + config BSP_USING_TOUCH_FT5406 + bool "Enable FT5406" + default n + endif + + menuconfig BSP_USING_LCD + bool "Enable LCD" + default n + + menuconfig BSP_USING_LVGL + bool "Enable LVGL" + default n + select PKG_USING_LVGL if BSP_USING_LVGL + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + config BSP_USING_GPTMR4 + bool "Enable GPTMR4" + default n + config BSP_USING_GPTMR5 + bool "Enable GPTMR5" + default n + config BSP_USING_GPTMR6 + bool "Enable GPTMR6" + default n + config BSP_USING_GPTMR7 + bool "Enable GPTMR7" + default n + endif + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + endif + + menuconfig BSP_USING_DRAM + bool "Enable DRAM" + default y + menuconfig INIT_EXT_RAM_FOR_DATA + bool "INIT_EXT_RAM_FOR_DATA" + default y + + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select PKG_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + + menuconfig BSP_USING_DAO + bool "Enable Audio DAO play" + default n + select RT_USING_AUDIO if BSP_USING_DAO + + menuconfig BSP_USING_PDM + bool "Enable Audio PDM record" + default n + select RT_USING_AUDIO if BSP_USING_PDM + + menuconfig BSP_USING_I2S + bool "Enable Audio I2S device" + default n + select RT_USING_AUDIO if BSP_USING_I2S + if BSP_USING_I2S + config BSP_USING_I2S0 + bool "Enable I2S0" + default y + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB HOST" + default n + endif + + + menuconfig BSP_USING_WDG + bool "Enable Watchdog" + default n + select RT_USING_WDT if BSP_USING_WDG + if BSP_USING_WDG + config BSP_USING_WDG0 + bool "Enable WDG0" + default n + config BSP_USING_WDG1 + bool "Enable WDG1" + default n + config BSP_USING_WDG2 + bool "Enable WDG2" + default n + config BSP_USING_WDG3 + bool "Enable WDG3" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN if BSP_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN0 + bool "Enable CAN0" + default n + config BSP_USING_CAN1 + bool "Enable CAN1" + default n + config BSP_USING_CAN2 + bool "Enable CAN2" + default n + config BSP_USING_CAN3 + bool "Enable CAN3" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC12 + bool "Enable ADC12" + default n + if BSP_USING_ADC12 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + if !BSP_USING_ADC12 + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default n + if BSP_USING_ADC16 + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + endif + endif +endmenu + + + +endmenu diff --git a/bsp/hpmicro/hpm6750evkmini/board/SConscript b/bsp/hpmicro/hpm6750evkmini/board/SConscript new file mode 100644 index 0000000000..c6470a28bc --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/SConscript @@ -0,0 +1,20 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + rw007_port.c + eth_phy_port.c + fal_flash_port.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D45', 'HPM6750'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6750evkmini/board/board.c b/bsp/hpmicro/hpm6750evkmini/board/board.c new file mode 100644 index 0000000000..e26970e0e7 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/board.c @@ -0,0 +1,969 @@ +/* + * Copyright (c) 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_lcdc_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_debug_console.h" +#include "hpm_dram_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_sdxc_drv.h" +#include "hpm_sdxc_soc_drv.h" +#include "hpm_pllctl_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +#endif + +void board_init_console(void) +{ +#if BOARD_CONSOLE_TYPE == console_type_uart + console_config_t cfg; + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t) BOARD_CONSOLE_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_BAUDRATE; + + init_uart_pins((UART_Type *) cfg.base); + + console_init(&cfg); +#else + while(1); +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1)); + printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0)); + printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1)); + printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); + printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("display:\t %luHz\n", clock_get_frequency(clock_display)); + printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); + printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); + printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg)); + printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + init_uart_pins(ptr); +} + +void board_init_ahb(void) +{ + clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ +} + +void board_print_banner(void) +{ + const uint8_t banner[] = {"\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n"}; + printf("%s", banner); +} + +static void board_turnoff_rgb_led(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; + + HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; +} + +void board_init(void) +{ + board_turnoff_rgb_led(); + board_init_clock(); + board_init_console(); + board_init_pmp(); + board_init_ahb(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_sdram_pins(void) +{ + init_sdram_pins(); +} + +uint32_t board_init_dram_clock(void) +{ + clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ + return clock_get_frequency(clock_dram); +} + +void board_power_cycle_lcd(void) +{ + /* turn off backlight */ + gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0); + + board_delay_ms(150); + /* power recycle */ + gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0); + board_delay_ms(20); + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1); + board_delay_ms(150); + + /* turn on backlight */ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); + +} + +void board_init_lcd(void) +{ + board_init_lcd_clock(); + init_lcd_pins(BOARD_LCD_BASE); + + board_power_cycle_lcd(); + + board_delay_ms(10); + board_power_cycle_lcd(); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, void *cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = (board_timer_cb)cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + init_i2c_pins_as_gpio(ptr); + if (ptr == BOARD_CAP_I2C_BASE) { + gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN); + gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); + if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { + printf("CLK is low, please power cycle the board\n"); + while (1) {} + } + if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); + for (uint8_t i = 0; i < 3; i++) { + for (uint32_t j = 0; j < 9; j++) { + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0); + board_delay_ms(10); + } + board_delay_ms(100); + } + printf("I2C bus is cleared\n"); + } +} + +void board_init_i2c(I2C_Type *ptr) +{ + hpm_stat_t stat; + uint32_t freq; + i2c_config_t config; + + board_i2c_bus_clear(ptr); + + init_i2c_pins(ptr); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); + stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", BOARD_CAP_I2C_BASE); + while (1) {} + } +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart0); + } + else if (ptr == HPM_UART1) { + clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart1); + } + else if (ptr == HPM_UART2) { + clock_set_source_divider(clock_uart2, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart2); + } + else if (ptr == HPM_UART3) { + clock_set_source_divider(clock_uart3, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart3); + } + else if (ptr == HPM_UART4) { + clock_set_source_divider(clock_uart4, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart4); + } + else if (ptr == HPM_UART5) { + clock_set_source_divider(clock_uart5, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart5); + } + else if (ptr == HPM_UART6) { + clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart6); + } + else if (ptr == HPM_UART7) { + clock_set_source_divider(clock_uart7, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart7); + } + else if (ptr == HPM_UART8) { + clock_set_source_divider(clock_uart8, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart8); + } + else if (ptr == HPM_UART9) { + clock_set_source_divider(clock_uart9, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart9); + } + else if (ptr == HPM_UART10) { + clock_set_source_divider(clock_uart10, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart10); + } + else if (ptr == HPM_UART11) { + clock_set_source_divider(clock_uart11, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart11); + } + else if (ptr == HPM_UART12) { + clock_set_source_divider(clock_uart12, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart12); + } + else if (ptr == HPM_UART13) { + clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart13); + } + else if (ptr == HPM_UART14) { + clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart14); + } + else if (ptr == HPM_UART15) { + clock_set_source_divider(clock_uart15, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart15); + } + else { + /* Unsupported instance */ + } + + return freq; +} + + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_SPI0) { + /* SPI0 clock configure */ + clock_add_to_group(clock_spi0, 0); + clock_set_source_divider(clock_spi0, clk_src_pll1_clk1, 5U); + + freq = clock_get_frequency(clock_spi0); + } + else if (ptr == HPM_SPI1) { + /* SPI1 clock configure */ + clock_add_to_group(clock_spi1, 0); + clock_set_source_divider(clock_spi1, clk_src_pll1_clk1, 5U); + + freq = clock_get_frequency(clock_spi1); + } + else if (ptr == HPM_SPI2) { + /* SPI2 clock configure */ + clock_add_to_group(clock_spi2, 0); + clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); + + freq = clock_get_frequency(clock_spi2); + } + else if (ptr == HPM_SPI3) { + /* SPI3 clock configure */ + clock_add_to_group(clock_spi3, 0); + clock_set_source_divider(clock_spi3, clk_src_pll1_clk1, 5U); + + freq = clock_get_frequency(clock_spi3); + } + else { + /* Invalid instance */ + } + return freq; +} + +void board_init_cap_touch(void) +{ + init_cap_pins(); + gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0); + gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + + board_delay_ms(1); + gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); + + gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); + board_init_i2c(BOARD_CAP_I2C_BASE); +} + + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); +} + +void board_led_toggle(void) +{ + static uint8_t i; + gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_G_GPIO_PIN); + i++; + i = i % 3; +} + +void board_led_write(bool state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state ? BOARD_LED_ON_LEVEL : BOARD_LED_OFF_LEVEL); +} + +void board_init_cam_pins(void) +{ + init_cam_pins(HPM_CAM0); +} + +void board_init_usb_pins(void) +{ + /* set pull-up for USBx OC pins */ + init_usb_pins(HPM_USB0); + + /* configure USBx OC Flag pins as input function */ + gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ +} + +void board_init_pmp(void) +{ + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + + uint32_t start_addr = (uint32_t) __noncacheable_start__; + uint32_t end_addr = (uint32_t) __noncacheable_end__; + uint32_t length = end_addr - start_addr; + + if (length == 0) { + return; + } + + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + + pmp_entry_t pmp_entry[1]; + pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + + pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + hpm_core_clock = cpu0_freq; + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + HPM_PLLCTL->XTAL = PLLCTL_XTAL_RAMP_TIME_SET(32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1); + } + + /* Add most Clocks to group 0 */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_axi0, 0); + clock_add_to_group(clock_axi1, 0); + clock_add_to_group(clock_axi2, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_xpi1, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_gptmr4, 0); + clock_add_to_group(clock_gptmr5, 0); + clock_add_to_group(clock_gptmr6, 0); + clock_add_to_group(clock_gptmr7, 0); + clock_add_to_group(clock_uart0, 0); + clock_add_to_group(clock_uart1, 0); + clock_add_to_group(clock_uart2, 0); + clock_add_to_group(clock_uart3, 0); + clock_add_to_group(clock_uart6, 0); + clock_add_to_group(clock_uart13, 0); + clock_add_to_group(clock_uart14, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_can2, 0); + clock_add_to_group(clock_can3, 0); + clock_add_to_group(clock_display, 0); + clock_add_to_group(clock_sdxc0, 0); + clock_add_to_group(clock_sdxc1, 0); + clock_add_to_group(clock_camera0, 0); + clock_add_to_group(clock_camera1, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_ref0, 0); + clock_add_to_group(clock_ref1, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_eth0, 0); + clock_add_to_group(clock_eth1, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_ram0, 0); + clock_add_to_group(clock_ram1, 0); + clock_add_to_group(clock_usb0, 0); + clock_add_to_group(clock_usb1, 0); + clock_add_to_group(clock_jpeg, 0); + clock_add_to_group(clock_pdma, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_mot1, 0); + clock_add_to_group(clock_mot2, 0); + clock_add_to_group(clock_mot3, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_dao, 0); + clock_add_to_group(clock_msyn, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); + + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_adc2, 0); + clock_add_to_group(clock_adc3, 0); + + clock_add_to_group(clock_i2s0, 0); + clock_add_to_group(clock_i2s1, 0); + clock_add_to_group(clock_i2s2, 0); + clock_add_to_group(clock_i2s3, 0); + + /* Add the CPU1 clock to Group1 */ + clock_add_to_group(clock_mchtmr1, 1); + clock_add_to_group(clock_mbx1, 1); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { + printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ); + while(1); + } + + clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); + clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); +} + +uint32_t board_init_cam_clock(CAM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAM0) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_camera0); + } else if (ptr == HPM_CAM1) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_camera1); + } else { + /* Invalid camera instance */ + } + return freq; +} + +uint32_t board_init_lcd_clock(void) +{ + uint32_t freq; + clock_add_to_group(clock_display, 0); + /* Configure LCDC clock to 29.7MHz */ + clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U); + freq = clock_get_frequency(clock_display); + return freq; +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr) +{ + uint32_t freq = 0; + switch ((uint32_t) ptr) { + case HPM_ADC0_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc0); + break; + case HPM_ADC1_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc1); + break; + case HPM_ADC2_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc2); + break; + default: + /* Invalid ADC instance */ + break; + } + + return freq; +} + +uint32_t board_init_dao_clock(void) +{ + clock_add_to_group(clock_dao, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_dao); +} + +uint32_t board_init_pdm_clock(void) +{ + clock_add_to_group(clock_pdm, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_pdm); +} + +uint32_t board_init_i2s_clock(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_i2s0); + } else { + return 0; + } +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_ADC3) { + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} + +void board_init_can(CAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(CAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAN0) { + /* Set the CAN0 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_CAN1) { + /* Set the CAN1 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can1); + } else if (ptr == HPM_CAN2) { + /* Set the CAN2 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can2); + } else if (ptr == HPM_CAN3) { + /* Set the CAN3 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can3); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, 0); + clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr0); + } + else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, 0); + clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr1); + } + else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, 0); + clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr2); + } + else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, 0); + clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr3); + } + else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, 0); + clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr4); + } + else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, 0); + clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr5); + } + else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, 0); + clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr6); + } + else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, 0); + clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(clock_gptmr7); + } + else { + /* Invalid instance */ + } +} + +/* + * this function will be called during startup to initialize external memory for data use + */ +void _init_ext_ram(void) +{ + uint32_t dram_clk_in_hz; + board_init_sdram_pins(); + dram_clk_in_hz = board_init_dram_clock(); + + dram_config_t config = {0}; + dram_sdram_config_t sdram_config = {0}; + + dram_default_config(HPM_DRAM, &config); + config.dqs = DRAM_DQS_INTERNAL; + dram_init(HPM_DRAM, &config); + + sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.prescaler = 0x3; + sdram_config.burst_len_in_byte = 8; + sdram_config.auto_refresh_count_in_one_burst = 1; + sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + + sdram_config.precharge_to_act_in_ns = 18; /* Trp */ + sdram_config.act_to_rw_in_ns = 18; /* Trcd */ + sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */ + sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */ + sdram_config.cke_off_in_ns = 42; /* Trcd */ + sdram_config.act_to_precharge_in_ns = 42; /* Tras */ + + sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */ + sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ + sdram_config.act_to_act_in_ns = 12; /* Trrd */ + sdram_config.idle_timeout_in_ns = 6; + sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + + sdram_config.cs = BOARD_SDRAM_CS; + sdram_config.base_address = BOARD_SDRAM_ADDRESS; + sdram_config.size_in_byte = BOARD_SDRAM_SIZE; + sdram_config.port_size = BOARD_SDRAM_PORT_SIZE; + sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; + sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; + sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; + sdram_config.delay_cell_value = 29; + + dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); +} + +void board_init_sd_pins(SDXC_Type *ptr) +{ + if (ptr == HPM_SDXC1) { + init_sdxc_pins(ptr, false); + } else { + while (1) { + + } + } +} + +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) +{ + uint32_t actual_freq = 0; + do { + if (ptr != HPM_SDXC1) { + break; + } + clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; + sdxc_enable_inverse_clock(ptr, false); + sdxc_enable_sd_clock(ptr, false); + /* Configure the clock below 400KHz for the identification state */ + if (freq <= 400000UL) { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63); + } + /* configure the clock to 24MHz for the SDR12/Default speed */ + else if (freq <= 25000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); + } + /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ + else if (freq <= 50000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8); + } + /* Configure the clock to 100MHz for the SDR50 */ + else if (freq <= 100000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4); + } + /* Configure the clock to 166MHz for SDR104/HS200/HS400 */ + else if (freq <= 208000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2); + } + /* For other unsupported clock ranges, configure the clock to 24MHz */ + else { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); + } + sdxc_enable_inverse_clock(ptr, true); + sdxc_enable_sd_clock(ptr, true); + actual_freq = clock_get_frequency(sdxc_clk); + } while (false); + + return actual_freq; +} + +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) +{ + if (internal == false) { + return status_success; + } + + /* Configure Enet clock to output reference clock */ + if (ptr == HPM_ENET0) { + /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */ + clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); + } else if (ptr == HPM_ENET1) { + /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */ + clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */ + } else { + return status_invalid_argument; + } + return status_success; +} + +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) +{ + sdxc_switch_to_1v8_signal(ptr, true); + init_sdxc_pins(ptr, true); +} + +bool board_sd_detect_card(SDXC_Type *ptr) +{ + return sdxc_is_card_inserted(ptr); +} + +void board_init_rgb_pwm_pins(void) +{ + init_led_pins_as_pwm(); +} + +void board_init_beep_pwm_pins(void) +{ + init_beep_pwm_pins(); +} + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr) +{ + init_enet_pins(ptr); + + if (ptr == HPM_ENET1) { + gpio_set_pin_output_with_initial(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +void board_reset_enet_phy(ENET_Type *ptr) +{ + gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0); + board_delay_ms(BOARD_ENET1_PHY_RST_TIME); + gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1); +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/board.h b/bsp/hpmicro/hpm6750evkmini/board/board.h new file mode 100644 index 0000000000..416bd1925f --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/board.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "hpm_clock_drv.h" +#include "hpm_enet_drv.h" +#include "pinmux.h" + +#define BOARD_NAME "hpm6750evkmini" + +/* uart section */ +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART0 +#define BOARD_APP_UART_IRQ IRQn_UART0 +#else +#ifndef BOARD_APP_UART_IRQ +#warning no IRQ specified for applicaiton uart +#endif +#endif + +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart0 + +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE console_type_uart +#endif + +#if BOARD_CONSOLE_TYPE == console_type_uart +#define BOARD_CONSOLE_BASE HPM_UART0 +#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_BAUDRATE (115200UL) +#endif + +#define BOARD_FREEMASTER_UART_BASE HPM_UART0 +#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 +#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 + +/* sdram section */ +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (16*SIZE_1MB) +#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_REFRESH_COUNT (4096UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (2UL) + +/* lcd section */ +#define BOARD_LCD_BASE HPM_LCDC +#define BOARD_LCD_IRQ IRQn_LCDC_D0 +#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_POWER_GPIO_PIN 12 +#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 23 + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 + +#define BOARD_APP_I2C_SLAVE_BASE HPM_I2C3 +#define BOARD_APP_I2C_SLAVE_IRQ IRQn_I2C3 +#define BOARD_APP_I2C_SLAVE_CLK_NAME clock_i2c3 + +#define BOARD_CAM_I2C_BASE HPM_I2C0 +#define BOARD_CAM_I2C_CLK_NAME clock_i2c0 + +#define BOARD_CAP_I2C_BASE (HPM_I2C0) +#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 +#define BOARD_CAP_RST_GPIO (HPM_GPIO0) +#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_RST_GPIO_PIN (9) +#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) +#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_INTR_GPIO_PIN (8) +#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) +#define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) + +/* dma section */ +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA + +/* gpio section */ +#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_R_GPIO_PIN 19 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_G_GPIO_PIN 18 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_B_GPIO_PIN 20 + +#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL +#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX +#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN + +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ +#define BOARD_APP_GPIO_PIN 2 + +/* pinmux section */ +#define USING_GPIO0_FOR_GPIOZ +#ifndef USING_GPIO0_FOR_GPIOZ +#define BOARD_APP_GPIO_CTRL HPM_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#else +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#endif + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI2 +#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) +#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00000000U) + +/* lcd section */ +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH (800) +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT (480) +#endif + +/* pdma section */ +#define BOARD_PDMA_BASE HPM_PDMA + +/* enet section */ +#define BOARD_ENET1_RST_GPIO HPM_GPIO0 +#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOD +#define BOARD_ENET1_RST_GPIO_PIN (15U) +#define BOARD_ENET1_INF enet_inf_rmii +#define BOARD_ENET1_INT_REF_CLK (0U) +#define BOARD_ENET1_PHY_RST_TIME (30) +#define BOARD_ENET1_PTP_CLOCK (clock_ptp1) +/* adc section */ +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC_CH (0U) +#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES (1024U) +#define BOARD_APP_ADC_PREEMPT_DMA_SIZE_IN_4BYTES (192U) +#define BOARD_APP_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_APP_ADC_SINGLE_CONV_CNT (6) +#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 +#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 +#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 +#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 +#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR0) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr0) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR0) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr0) + +/* SDXC section */ +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) + +/* USB section */ +#define BOARD_USB0_VBUS_PORT (HPM_GPIO0) +#define BOARD_USB0_VBUS_GPIO_INDEX (GPIO_DO_GPIOF) +#define BOARD_USB0_VBUS_GPIO_PIN (9) + +#define BOARD_USB0_OC_PORT (HPM_GPIO0) +#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) +#define BOARD_USB0_OC_GPIO_PIN (8) + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 4 +#define BOARD_APP_PWM_OUT2 5 +#define BOARD_APP_TRGM HPM_TRGM0 + +/* RGB LED Section */ +#define BOARD_RED_PWM_IRQ IRQn_PWM1 +#define BOARD_RED_PWM HPM_PWM1 +#define BOARD_RED_PWM_OUT 0 +#define BOARD_RED_PWM_CMP 0 +#define BOARD_RED_PWM_CMP_INITIAL_ZERO true +#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_GREEN_PWM_IRQ IRQn_PWM1 +#define BOARD_GREEN_PWM HPM_PWM1 +#define BOARD_GREEN_PWM_OUT 1 +#define BOARD_GREEN_PWM_CMP 1 +#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_BLUE_PWM_IRQ IRQn_PWM0 +#define BOARD_BLUE_PWM HPM_PWM0 +#define BOARD_BLUE_PWM_OUT 7 +#define BOARD_BLUE_PWM_CMP 0 +#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 + + +/* Beep Section */ +#define BOARD_BEEP_PWM HPM_PWM3 +#define BOARD_BEEP_PWM_OUT 4 +#define BOARD_BEEP_PWM_CLOCK_NAME clock_mot3 + +#define BOARD_CPU_FREQ (816000000UL) + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE 0 +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); + +void board_init_uart(UART_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_lcd(void); + +void board_init_can(CAN_Type *ptr); + +uint32_t board_init_dram_clock(void); + +void board_init_sdram_pins(void); +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_led_pins(void); + +/* cap touch */ +void board_init_cap_touch(void); + +void board_led_write(bool state); +void board_led_toggle(void); + +void board_fpga_power_enable(void); + +void board_init_cam_pins(void); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); + +/* Initialize the CAM(camera) dot clock */ +uint32_t board_init_cam_clock(CAM_Type *ptr); + +/* Initialize the LCD pixel clock */ +uint32_t board_init_lcd_clock(void); + +uint32_t board_init_uart_clock(UART_Type *ptr); + +uint32_t board_init_spi_clock(SPI_Type *ptr); + +uint32_t board_init_adc12_clock(ADC12_Type *ptr); + +uint32_t board_init_adc16_clock(ADC16_Type *ptr); + +uint32_t board_init_can_clock(CAN_Type *ptr); + +uint32_t board_init_i2s_clock(I2S_Type *ptr); +uint32_t board_init_pdm_clock(void); +uint32_t board_init_dao_clock(void); + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); + +void board_init_sd_pins(SDXC_Type *ptr); +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); +bool board_sd_detect_card(SDXC_Type *ptr); + +void board_init_usb_pins(void); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); + +void board_delay_ms(uint32_t ms); + +void board_init_beep_pwm_pins(void); +void board_init_rgb_pwm_pins(void); + +void board_timer_create(uint32_t ms, void *cb); + +/* Initialize enet pins */ +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); + +/* Initialize enet reference clock in RMII mode */ +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); + +/* Reset an enet PHY */ +void board_reset_enet_phy(ENET_Type *ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg new file mode 100644 index 0000000000..686495c1a9 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/boards/hpm6750evkmini.cfg @@ -0,0 +1,299 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause +# +# openocd flash driver argument: +# - ARG7: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - ARG8: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3040000 +# - base address: 0x80000000 +# - flash size: 0x1000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +proc init_sdram { } { +# configure dram frequency +# 133Mhz pll1_clk0: 266Mhz divide by 2 + #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x201 +# 166Mhz pll2_clk0: 333Mhz divide by 2 + $::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x401 + + # PD13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040368 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040360 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040350 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040348 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040340 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040338 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040330 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040328 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040320 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040318 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040310 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040308 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040300 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC29 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC28 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC27 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC22 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC21 + $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC17 + $::_TARGET0 riscv dmi_write 0x39 0xF4040288 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC15 + $::_TARGET0 riscv dmi_write 0x39 0xF4040278 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040260 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC11 + $::_TARGET0 riscv dmi_write 0x39 0xF4040258 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040250 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040248 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040240 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040238 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040230 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040228 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040220 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC14 + $::_TARGET0 riscv dmi_write 0x39 0xF4040270 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040268 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC16 + # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 + $::_TARGET0 riscv dmi_write 0x3C 0x1000C + # PC26 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC25 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040298 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040290 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC23 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC24 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC30 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC31 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040210 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040218 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # dramc configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + sleep 10 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + $::_TARGET0 riscv dmi_write 0x39 0xF3050008 + $::_TARGET0 riscv dmi_write 0x3C 0x30524 + $::_TARGET0 riscv dmi_write 0x39 0xF305000C + $::_TARGET0 riscv dmi_write 0x3C 0x6030524 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x10000000 + + # 16MB + $::_TARGET0 riscv dmi_write 0x39 0xF3050010 + $::_TARGET0 riscv dmi_write 0x3C 0x40000019 + $::_TARGET0 riscv dmi_write 0x39 0xF3050014 + $::_TARGET0 riscv dmi_write 0x3C 0 + # 16-bit + $::_TARGET0 riscv dmi_write 0x39 0xF3050040 + $::_TARGET0 riscv dmi_write 0x3C 0xf31 + + # 133Mhz configuration + #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + # 166Mhz configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e33 + + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020300 + + # config delay cell + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x3b + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x203b + + $::_TARGET0 riscv dmi_write 0x39 0xF3050094 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3050098 + $::_TARGET0 riscv dmi_write 0x3C 0 + + # precharge all + $::_TARGET0 riscv dmi_write 0x39 0xF3050090 + $::_TARGET0 riscv dmi_write 0x3C 0x40000000 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + # auto refresh + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + # set mode + $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 + $::_TARGET0 riscv dmi_write 0x3C 0x33 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020301 + echo "SDRAM has been initialized" +} + +$_TARGET0 configure -event reset-init { + init_clock + init_sdram +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 0000000000..b9ae112104 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 0000000000..580d98ef85 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 0000000000..4fb0fba2e7 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 0000000000..fd8f04428c --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 0000000000..e9d6e6d698 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-csr.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-csr.cfg new file mode 100644 index 0000000000..c053c1d16d --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-csr.cfg @@ -0,0 +1 @@ +riscv expose_csrs 262,774,1984-2005,2015-2017,2048,2057,2059,2060,2500-2505,2509,2511,2513-2516,2528,2531-2534 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg new file mode 100644 index 0000000000..3a0460204f --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg @@ -0,0 +1,38 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6750 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +set _TARGET1 $_CHIP.cpu1 +target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 + +proc release_core1 {} { + # set start point for core1 + $::_TARGET0 riscv dmi_write 0x39 0xF4002C08 + $::_TARGET0 riscv dmi_write 0x3C 0x20016284 + + # set boot flag for core1 + $::_TARGET0 riscv dmi_write 0x39 0xF4002C0C + $::_TARGET0 riscv dmi_write 0x3C 0xC1BEF1A9 + + # release core1 + $::_TARGET0 riscv dmi_write 0x39 0xF4002C00 + $::_TARGET0 riscv dmi_write 0x3C 0x1000 +} + +$_TARGET1 configure -event reset-deassert-pre release_core1 +$_TARGET1 configure -event examine-start release_core1 +$_TARGET1 configure -event examine-end { + $::_TARGET1 arp_examine +} + +$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x04000 -work-area-backup 0 diff --git a/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg new file mode 100644 index 0000000000..8e2bbe5f19 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg @@ -0,0 +1,13 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6750 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c new file mode 100644 index 0000000000..665541daec --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-01-11 hpmicro First version + */ + +#include "rtthread.h" + +#ifdef RT_USING_PHY +#include +#include +#include "hpm_enet_drv.h" +#include "eth_phy_port.h" +#include "hpm_soc.h" +#include "netif/ethernetif.h" +#include "board.h" + +typedef struct +{ + char *mdio_name; + ENET_Type *instance; + struct eth_device *eth_dev; + phy_device_t *phy_dev; + struct rt_mdio_bus *mdio_bus; +} eth_phy_handle_t; + +typedef struct +{ + uint8_t phy_handle_cnt; + eth_phy_handle_t **phy_handle; +} eth_phy_monitor_handle_t; + +#ifdef BSP_USING_ETH0 +extern struct eth_device eth0_dev; +static struct rt_mdio_bus mdio0_bus; +static phy_device_t phy0_dev; +static uint8_t phy0_reg_list[]= {PHY0_REG_LIST}; + +static eth_phy_handle_t eth0_phy_handle = +{ + .instance = HPM_ENET0, + .eth_dev = ð0_dev, + .phy_dev = &phy0_dev, + .mdio_name = "MDIO0", + .mdio_bus = &mdio0_bus, +}; +#endif + +#ifdef BSP_USING_ETH1 +extern struct eth_device eth1_dev; +static struct rt_mdio_bus mdio1_bus; +static phy_device_t phy1_dev; +static uint8_t phy1_reg_list[]= {PHY1_REG_LIST}; + +static eth_phy_handle_t eth1_phy_handle = +{ + .instance = HPM_ENET1, + .eth_dev = ð1_dev, + .phy_dev = &phy1_dev, + .mdio_name = "MDIO1", + .mdio_bus = &mdio1_bus, +}; +#endif + +static eth_phy_handle_t *s_gphys[] = +{ +#ifdef BSP_USING_ETH0 +ð0_phy_handle, +#endif + +#ifdef BSP_USING_ETH1 +ð1_phy_handle +#endif +}; + +static uint8_t *s_gphy_reg_list[] = +{ +#ifdef BSP_USING_ETH0 +phy0_reg_list, +#endif + +#ifdef BSP_USING_ETH1 +phy1_reg_list, +#endif +}; + +eth_phy_monitor_handle_t phy_monitor_handle = +{ + .phy_handle_cnt = ARRAY_SIZE(s_gphys), + .phy_handle = s_gphys +}; + +static struct rt_phy_ops phy_ops; + +static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) +{ + return PHY_STATUS_OK; +} + +static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg); + + return size; +} + +static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg, *(uint16_t *)data); + + return size; +} + +static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) +{ + uint16_t reg_status; + + reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]); + + #if PHY_AUTO_NEGO + reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK; + *status = reg_status ? RT_TRUE : RT_FALSE; + + #else + reg_status &= PHY_LINKED_STATUS_MASK; + *status = reg_status ? RT_TRUE : RT_FALSE; + #endif + + return PHY_STATUS_OK; +} + +static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) +{ + uint16_t reg_status; + + reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]); + + *speed = PHY_STATUS_SPEED_100M(reg_status) ? PHY_SPEED_100M : PHY_SPEED_10M; + *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX; + + return PHY_STATUS_OK; +} + +static void phy_poll_status(void *parameter) +{ + int ret; + phy_info_t phy_info; + rt_uint32_t status; + rt_device_t dev; + rt_phy_msg_t msg; + rt_uint32_t speed, duplex; + phy_device_t *phy_dev; + struct eth_device* eth_dev; + char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; + + eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) + { + eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; + phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; + + phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); + + if (status) + { + phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); + + ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (ret != 0) + { + memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + } + } + + if (phy_dev->phy_link != status) + { + phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; + eth_device_linkchange(eth_dev, status); + LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); + if (status == PHY_LINK_UP) + { + LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); + LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); + } + } + } +} + +static void phy_detection(void *parameter) +{ + uint8_t detected_count = 0; + struct rt_phy_msg msg = {0, 0}; + phy_device_t *phy_dev = (phy_device_t *)parameter; + rt_uint32_t i; + + msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX]; + phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ); + + while(phy_dev->phy.addr == 0xffff) + { + /* Search a PHY */ + for (i = 0; i <= 0x1f; i++) + { + ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i; + phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1); + + if (msg.value == PHY_ID1) + { + phy_dev->phy.addr = i; + LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr); + return; + } + } + + phy_dev->phy.addr = 0xffff; + detected_count++; + rt_thread_mdelay(1000); + + if (detected_count > 3) + { + LOG_E("No any PHY device is detected! Please check your hardware!\n"); + return; + } + } +} + +static void phy_monitor_thread_entry(void *args) +{ + rt_timer_t phy_status_timer; + + eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) + { + LOG_D("Detect a PHY%d\n", i); + phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev); + } + + phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); + + if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK) + { + LOG_E("Failed to start link change detection timer\n"); + } +} + +int phy_device_register(void) +{ + rt_err_t err = RT_ERROR; + rt_thread_t thread_phy_monitor; + + /* Set ops for PHY */ + phy_ops.init = phy_init; + phy_ops.get_link_status = phy_get_link_status; + phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex; + + for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++) + { + /* Set PHY address */ + s_gphys[i]->phy_dev->phy.addr = 0xffff; + + /* Set MIDO bus */ + s_gphys[i]->mdio_bus->hw_obj = s_gphys[i]->instance; + s_gphys[i]->mdio_bus->name = s_gphys[i]->mdio_name; + s_gphys[i]->mdio_bus->ops->read = phy_read; + s_gphys[i]->mdio_bus->ops->write = phy_write; + s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; + s_gphys[i]->phy_dev->phy.ops = &phy_ops; + + /* Set PHY register list */ + s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i]; + + rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME); + } + + /* Start PHY monitor */ + thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2); + + if (thread_phy_monitor != RT_NULL) + { + rt_thread_startup(thread_phy_monitor); + } + else + { + err = RT_ERROR; + } + + return err; +} +INIT_PREV_EXPORT(phy_device_register); +#endif /* RT_USING_PHY */ diff --git a/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h new file mode 100644 index 0000000000..78b4350edb --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/eth_phy_port.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef ETH_PHY_PORT_H +#define ETH_PHY_PORT_H + +#include "hpm_ioc_regs.h" +#include + +#ifndef PHY_AUTO_NEGO +#define PHY_AUTO_NEGO (1U) +#endif + +#ifndef PHY_MDIO_CSR_CLK_FREQ +#define PHY_MDIO_CSR_CLK_FREQ (200000000U) +#endif + +enum phy_link_status +{ + PHY_LINK_DOWN = 0U, + PHY_LINK_UP +}; + +typedef struct { + rt_uint32_t phy_speed; + rt_uint32_t phy_duplex; +} phy_info_t; + +typedef struct { + rt_uint32_t phy_link; + rt_phy_t phy; + phy_info_t phy_info; +} phy_device_t; + +/** @note PHY: LAN8720A */ + +#define PHY_NAME ("LAN8720A") +#define PHY_ID1 (7U) + +/* The PHY basic control register */ +#define PHY_BASIC_CONTROL_REG (0x00U) +#define PHY_RESET_MASK (1U << 15) +#define PHY_AUTO_NEGOTIATION_MASK (1U << 12) + +/* The PHY basic status register */ +#define PHY_BASIC_STATUS_REG (0x01U) +#define PHY_LINKED_STATUS_MASK (1U << 2) +#define PHY_AUTONEGO_COMPLETE_MASK (1U << 5) + +/* The PHY ID one register */ +#define PHY_ID1_REG (0x02U) + +/* The PHY ID two register */ +#define PHY_ID2_REG (0x03U) + +/* The PHY auto-negotiate advertise register */ +#define PHY_AUTONEG_ADVERTISE_REG (0x04U) + +/* The PHY SPECIAL MODES REGISTER */ +#define PHY_SPECIAL_MODES_REG (0x12U) + +/* The PHY interrupt source flag register. */ +#define PHY_INTERRUPT_FLAG_REG (0x1dU) + +/* The PHY interrupt mask register. */ +#define PHY_INTERRUPT_MASK_REG (0x1eU) +#define PHY_LINK_DOWN_MASK (1 << 4) +#define PHY_AUTO_NEGO_COMPLETE_MASK (1 << 6) + +/* The PHY status register. */ +#define PHY_STATUS_REG (0x1fU) +#define PHY_10M_MASK (1 << 2) +#define PHY_100M_MASK (1 << 3) +#define PHY_FULL_DUPLEX_MASK (1 << 4) +#define PHY_STATUS_SPEED_10M(SR) ((SR) & PHY_10M_MASK) +#define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK) +#define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK) + +/* PHY0 register list */ +#define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\ + PHY_BASIC_STATUS_REG,\ + PHY_ID1_REG,\ + PHY_ID2_REG,\ + PHY_SPECIAL_MODES_REG,\ + PHY_INTERRUPT_FLAG_REG,\ + PHY_INTERRUPT_MASK_REG,\ + PHY_STATUS_REG + +/* PHY0 register index */ +#define PHY0_BASIC_STATUS_REG_IDX (1U) +#define PHY0_ID1_REG_IDX (2U) +#define PHY0_STATUS_REG_IDX (7U) + +/* PHY1 register list */ +#define PHY1_REG_LIST PHY_BASIC_CONTROL_REG,\ + PHY_BASIC_STATUS_REG,\ + PHY_ID1_REG,\ + PHY_ID2_REG,\ + PHY_SPECIAL_MODES_REG,\ + PHY_INTERRUPT_FLAG_REG,\ + PHY_INTERRUPT_MASK_REG,\ + PHY_STATUS_REG + +/* PHY1 register index */ +#define PHY_BASIC_STATUS_REG_IDX (1U) +#define PHY_ID1_REG_IDX (2U) +#define PHY_STATUS_REG_IDX (7U) + +#endif diff --git a/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h b/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h new file mode 100644 index 0000000000..207d026da7 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/fal_cfg.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 1*1024*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* PKG_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm6750evkmini/board/fal_flash_port.c b/bsp/hpmicro/hpm6750evkmini/board/fal_flash_port.c new file mode 100644 index 0000000000..a664b13fa8 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/fal_flash_port.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + +#if defined(FLASH_XIP) && (FLASH_XIP == 1) + +#define FAL_ENTER_CRITICAL() do {\ + rt_enter_critical();\ + disable_irq_from_intc();\ + fencei();\ + }while(0) + +#define FAL_EXIT_CRITICAL() do {\ + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ + fencei();\ + rt_exit_critical();\ + enable_irq_from_intc();\ + }while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + +#else +#define FAL_ENTER_CRITICAL() + +#define FAL_EXIT_CRITICAL() + +#define FAL_RAMFUNC + +#endif + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld new file mode 100644 index 0000000000..c2a16eef0a --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,255 @@ +/* + * Copyright 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*cpuport.o (.text .text* .rodata .rodata*)) + KEEP(*trap_entry.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__; + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld new file mode 100644 index 0000000000..915330acb9 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld @@ -0,0 +1,256 @@ +/* + * Copyright 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 1M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01100000, LENGTH = NONCACHEABLE_SIZE +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*cpuport.o (.text .text* .rodata .rodata*)) + KEEP(*trap_entry.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__; + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld new file mode 100644 index 0000000000..5450273021 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,214 @@ +/* + * Copyright 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + /* It's alias address of core0 ILM+DLM, but accessing via system bus */ + CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K + /* It's alias address of core1 ILM+DLM, but accessing via system bus */ + CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE +} + +SECTIONS +{ + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_execpt_table)) + KEEP(*(.gcc_execpt_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE + __noncacheable_start__ = ORIGIN(NONCACHEABLE); + __noncacheable_end__ = ORIGIN(NONCACHEABLE) + LENGTH(NONCACHEABLE); + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + } > DLM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > SDRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.c b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c new file mode 100644 index 0000000000..d9baae0c41 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + } else if (ptr == HPM_UART6) { + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_UART6_RXD; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_UART6_TXD; + } else if (ptr == HPM_UART13) { + HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD; + HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD; + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; + } else if (ptr == HPM_UART14) { + HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_UART14_RXD; + HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_UART14_TXD; + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_SOC_PZ_10; + HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_SOC_PZ_11; + } +} + +void init_lcd_pins(LCDC_Type *ptr) +{ + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1; + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_3; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_DIS0_R_4; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_DIS0_R_5; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_DIS0_R_6; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_7; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_G_0; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_1; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_DIS0_G_2; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_DIS0_G_3; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_DIS0_G_4; + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_DIS0_G_5; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_G_6; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_DIS0_G_7; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_B_0; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_1; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_2; + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_B_3; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_B_4; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_B_5; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_B_6; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_B_7; + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_CLK; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_EN; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_DIS0_VSYNC; + + /* PWM */ + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23; + /* PWR */ + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; +} + +void init_cap_pins(void) +{ + /* CAP_INT */ + HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPIO_B_08; + /* CAP_RST */ + HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09; +} + +void init_i2c_pins_as_gpio(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + /* I2C0 */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10; + } else { + while(1); + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2C0_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PB10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else if (ptr == HPM_I2C3) { + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_I2C3_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_I2C3_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB14].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else { + while(1); + } +} + +void init_sdram_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_DRAM_DQ_14; + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_DRAM_DQ_15; + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_DRAM_DQ_12; + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_DRAM_DQ_13; + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_DRAM_DQ_00; + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_DRAM_DQ_10; + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_DRAM_DQ_11; + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_DRAM_DQ_01; + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_DRAM_DQ_08; + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_DRAM_DQ_09; + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_DRAM_DQ_04; + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_DRAM_DQ_03; + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_DRAM_DQ_02; + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_DRAM_DQ_07; + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_DRAM_DQ_06; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_DRAM_DQ_05; + + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_DRAM_A_11; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_DRAM_A_09; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_DRAM_A_10; + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_DRAM_A_08; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_DRAM_A_07; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_DRAM_A_06; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_DRAM_A_01; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_DRAM_A_00; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_DRAM_A_05; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_DRAM_A_04; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_DRAM_A_03; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_DRAM_A_02; + + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_DRAM_BA1; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_DRAM_BA0; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_DRAM_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_DRAM_CLK; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_DRAM_CKE; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_DRAM_CS_0; + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_DRAM_RAS; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_DRAM_CAS; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_DRAM_WE; + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_DRAM_DM_0; + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_DRAM_DM_1; +} + +void init_gpio_pins(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + /* Green LED*/ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; + HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; + +#ifdef USING_GPIO0_FOR_GPIOZ + HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; + HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; +#endif +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_GPIO_E_03; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_SPI2_CSN; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI3) { + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_SPI3_CSN; + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + +void init_pins(void) +{ + init_uart_pins(BOARD_CONSOLE_BASE); + init_sdram_pins(); +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR4) { + /* TMR4 capture 1 */ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1; + } else if (ptr == HPM_GPTMR5) { + /* TMR5 compare 0 */ + HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_GPTMR5_COMP_0; + } +} + +void init_i2s_pins(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_I2S0_MCLK; + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2S0_FCLK; + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_I2S0_BCLK; + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_I2S0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_I2S0_TXD_1; + } +} + +void init_dao_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_DAOR_P; + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_DAOR_N; +} + +void init_pdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK; + HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0; + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11; +} + +void init_vad_pins(void) +{ + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK; + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT; +} + +void init_cam_pins(CAM_Type *ptr) +{ + if (ptr == HPM_CAM0) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK; + HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_CAM0_VSYNC; + HPM_IOC->PAD[IOC_PAD_PA05].FUNC_CTL = IOC_PA05_FUNC_CTL_CAM0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_CAM0_D_2; + HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_CAM0_D_3; + HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_CAM0_D_4; + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_CAM0_D_5; + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_CAM0_D_6; + HPM_IOC->PAD[IOC_PAD_PA04].FUNC_CTL = IOC_PA04_FUNC_CTL_CAM0_D_7; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_CAM0_D_8; + HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_CAM0_D_9; + } +} + +void init_butn_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED; +} + +void init_acmp_pins(void) +{ +} + +void init_enet_pins(ENET_Type *ptr) +{ + if (ptr == HPM_ENET1) { + /* RST */ + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; + + HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC; + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO; + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN; + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV; + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_ETH1_REFCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1; + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1; + HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0; + HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0; + } +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM0) { + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_PWM0_P_7; + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_PWM0_P_6; + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_PWM0_P_5; + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_PWM0_P_4; + } else if (ptr == HPM_PWM1) { + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_PWM1_P_1; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM1_P_0; + } else if (ptr == HPM_PWM3) { + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_PWM3_P_4; + } +} + +void init_adc_pins(void) +{ + /* ADC0/1/2/.VINP7 */ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2/.VINP8 */ + HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2/.VINP9 */ + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2/.VINP10 */ + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_usb_pins(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + /* USB0 ID */ + HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10; + /* USB0 OC */ + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; + } +} + +void init_can_pins(CAN_Type *ptr) +{ + if (ptr == HPM_CAN1) { + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_CAN1_TXD; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_CAN1_RXD; + } +} + +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) +{ + uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_SDXC1) { + /* SDXC1.CLK */ + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; + + /* SDXC1.CMD */ + HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl; + HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl; + + /* SDXC1.DATA0 */ + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; + /* SDXC1.DATA1 */ + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; + /* SDXC1.DATA2 */ + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; + /* SDXC1.DATA3 */ + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; + + /* SDXC1.CDN */ + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_SDC1_CDN; + HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = pad_ctl; + + /* SDXC1.VSEL */ + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_SDC1_VSEL; + HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = pad_ctl; + } +} + +void init_clk_obs_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; +} + +void init_wifi_pins(void) +{ + /* WiFi INT */ + HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_GPIO_E_01; + HPM_IOC->PAD[IOC_PAD_PE01].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK | IOC_PAD_PAD_CTL_PS_MASK; + /* WiFi RST */ + HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_GPIO_E_02; + + init_spi_pins(HPM_SPI0); +} + +void init_beep_pwm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_PWM3_P_4; +} + +void init_led_pins_as_pwm(void) +{ + /* Blue */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_PWM0_P_7; + /* Green */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_PWM1_P_1; + /* Red */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM1_P_0; +} + +void init_led_pins_as_gpio(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; + HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; + HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; + HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; +} + + diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.h b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h new file mode 100644 index 0000000000..b785fd3445 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H +#include "hpm_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif +void init_uart_pins(UART_Type *ptr); +void init_lcd_pins(LCDC_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_cap_pins(void); +void init_sdram_pins(void); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_pins(void); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_i2s_pins(I2S_Type *ptr); +void init_dao_pins(void); +void init_pdm_pins(void); +void init_vad_pins(void); +void init_cam_pins(CAM_Type *ptr); +void init_fpga_power_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_enet_pins(ENET_Type *ptr); +void init_pwm_pins(PWM_Type *ptr); +void init_adc_pins(void); +void init_usb_pins(USB_Type *ptr); +void init_can_pins(CAN_Type *ptr); +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); +void init_adc_bldc_pins(void); + +void init_i2c_pins_as_gpio(I2C_Type *ptr); + +void init_beep_pwm_pins(void); +void init_led_pins_as_pwm(void); +void init_led_pins_as_gpio(void); +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c new file mode 100644 index 0000000000..e0c7898a79 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_mchtmr_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_manager.h" + +void os_tick_config(void); + +extern int rt_hw_uart_init(void); + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_manager_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); + gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); + gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); + + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, APP_LED_OFF); + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, APP_LED_OFF); +} + +void app_led_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state); + break; + case 1: + gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, state); + break; + case 2: + gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + + enable_mchtmr_irq(); +} + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_interrupt_enter(); + rt_tick_increase(); + rt_interrupt_leave(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_HOT &= ~(1UL << 31); + HPM_PPOR->RESET_COLD |= (1UL << 31); + + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h new file mode 100644 index 0000000000..e310e58f98 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" + +/* gpio section */ +#define APP_LED0_GPIO_CTRL HPM_GPIO0 +#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOB +#define APP_LED0_GPIO_PIN 19 +#define APP_LED1_GPIO_CTRL HPM_GPIO0 +#define APP_LED1_GPIO_INDEX GPIO_DI_GPIOB +#define APP_LED1_GPIO_PIN 18 +#define APP_LED2_GPIO_CTRL HPM_GPIO0 +#define APP_LED2_GPIO_INDEX GPIO_DI_GPIOB +#define APP_LED2_GPIO_PIN 20 +#define APP_LED_ON (0) +#define APP_LED_OFF (1) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* SPI WIFI section */ +#define RW007_RST_PIN (IOC_PAD_PE02) +#define RW007_INT_BUSY_PIN (IOC_PAD_PE01) +#define RW007_CS_PIN (IOC_PAD_PE03) +#define RW007_CS_GPIO (HPM_GPIO0) +#define RW007_SPI_BUS_NAME "spi1" + + +/* CAN section */ +#define BOARD_CAN_NAME "can1" + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); + + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c b/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c new file mode 100644 index 0000000000..276631285a --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/board/rw007_port.c @@ -0,0 +1,121 @@ + +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include + +#ifdef RT_USING_WIFI +#include +#include +#include +#include + +#define RW007_AT_MODE 3 +#define RW007_SPI_MODE 1 + +extern void spi_wifi_isr(int vector); + + +static void rw007_spi_cs_control(uint32_t value) +{ + uint32_t gpio_index = RW007_CS_PIN / 32U; + uint32_t pin_index = RW007_CS_PIN % 32U; + if (value != 0) + { + RW007_CS_GPIO->DO[gpio_index].SET = (1UL << pin_index); + } + else + { + RW007_CS_GPIO->DO[gpio_index].CLEAR = (1UL << pin_index); + } +} + +static void rw007_spi_cs_init(void) +{ + HPM_IOC->PAD[RW007_CS_PIN].FUNC_CTL = 0; + HPM_IOC->PAD[RW007_CS_PIN].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + uint32_t gpio_index = RW007_CS_PIN / 32U; + uint32_t pin_index = RW007_CS_PIN % 32U; + RW007_CS_GPIO->DO[gpio_index].SET = (1UL << pin_index); + RW007_CS_GPIO->OE[gpio_index].SET = (1UL <user_data; + set_rw007_mode(RW007_AT_MODE); + return 0; +} +MSH_CMD_EXPORT(rw007_update, rw007_update); + +static void int_wifi_irq(void * p) +{ + ((void)p); + spi_wifi_isr(0); +} + +void spi_wifi_hw_init(void) +{ + rt_pin_attach_irq(RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0); + rt_pin_irq_enable(RW007_INT_BUSY_PIN, RT_TRUE); +} + +rt_bool_t spi_wifi_is_busy(void) +{ + return !rt_pin_read(RW007_INT_BUSY_PIN); +} + +void spi_wifi_int_cmd(rt_bool_t cmd) +{ + rt_pin_irq_enable(RW007_INT_BUSY_PIN, cmd); +} + +#endif /* RT_USING_WIFI */ diff --git a/bsp/hpmicro/hpm6750evkmini/makefile.targets b/bsp/hpmicro/hpm6750evkmini/makefile.targets new file mode 100644 index 0000000000..502182f4e7 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard ../board/linker_scripts/flash_xip_rtt.ld) diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.h b/bsp/hpmicro/hpm6750evkmini/rtconfig.h new file mode 100644 index 0000000000..7e7fd18386 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.h @@ -0,0 +1,207 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50000 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_LEGACY +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_RTC + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Sensor libraries */ + + +/* Display libraries */ + + +/* Timing libraries */ + + +/* Project libraries */ + + +/* Hardware Drivers Config */ + +#define SOC_HPM6000 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_RTC +#define BSP_USING_DRAM +#define INIT_EXT_RAM_FOR_DATA + +#endif diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.py b/bsp/hpmicro/hpm6750evkmini/rtconfig.py new file mode 100644 index 0000000000..63c7cc149d --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.py @@ -0,0 +1,94 @@ +# Copyright 2021-2022 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' + +CHIP_NAME='HPM6750' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compilercute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + + + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -std=gnu11 -DUSE_NONVECTOR_MODE=1' + ARCH_ABI = ' -mcmodel=medlow ' + CFLAGS = DEVICE + ARCH_ABI + ' -ffunction-sections -fdata-sections -fno-common' + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + else: + CFLAGS += ' -O2 -Os' + LFLAGS += ' -O2 -Os' + LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig_preinc.h b/bsp/hpmicro/hpm6750evkmini/rtconfig_preinc.h new file mode 100644 index 0000000000..0ad85f00e4 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig_preinc.h @@ -0,0 +1,16 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D45 +#define HAVE_CCONFIG_H +#define HPM6750 +#define RT_USING_NEWLIB +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/SConscript b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/SConscript new file mode 100644 index 0000000000..18c366ba28 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/SConscript @@ -0,0 +1,21 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Split(''' + startup.c + trap.c +''') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/startup.c b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/startup.c new file mode 100644 index 0000000000..5d6123bd09 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/startup.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S new file mode 100644 index 0000000000..17f48174db --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_in_dlm + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Disable Vector mode */ + csrci CSR_MMISC_CTL, 2 + + /* Initialize trap_entry base */ + la t0, irq_handler_trap + csrw mtvec, t0 + + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/vectors.S new file mode 100644 index 0000000000..39fdb20af5 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/vectors.S @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* ADC0 IRQ handler */ + IRQ_HANDLER 9 /* ADC1 IRQ handler */ + IRQ_HANDLER 10 /* ADC2 IRQ handler */ + IRQ_HANDLER 11 /* DAC IRQ handler */ + IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 14 /* SPI0 IRQ handler */ + IRQ_HANDLER 15 /* SPI1 IRQ handler */ + IRQ_HANDLER 16 /* SPI2 IRQ handler */ + IRQ_HANDLER 17 /* SPI3 IRQ handler */ + IRQ_HANDLER 18 /* UART0 IRQ handler */ + IRQ_HANDLER 19 /* UART1 IRQ handler */ + IRQ_HANDLER 20 /* UART2 IRQ handler */ + IRQ_HANDLER 21 /* UART3 IRQ handler */ + IRQ_HANDLER 22 /* UART4 IRQ handler */ + IRQ_HANDLER 23 /* UART5 IRQ handler */ + IRQ_HANDLER 24 /* UART6 IRQ handler */ + IRQ_HANDLER 25 /* UART7 IRQ handler */ + IRQ_HANDLER 26 /* CAN0 IRQ handler */ + IRQ_HANDLER 27 /* CAN1 IRQ handler */ + IRQ_HANDLER 28 /* PTPC IRQ handler */ + IRQ_HANDLER 29 /* WDG0 IRQ handler */ + IRQ_HANDLER 30 /* WDG1 IRQ handler */ + IRQ_HANDLER 31 /* TSNS IRQ handler */ + IRQ_HANDLER 32 /* MBX0A IRQ handler */ + IRQ_HANDLER 33 /* MBX0B IRQ handler */ + IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 38 /* I2C0 IRQ handler */ + IRQ_HANDLER 39 /* I2C1 IRQ handler */ + IRQ_HANDLER 40 /* I2C2 IRQ handler */ + IRQ_HANDLER 41 /* I2C3 IRQ handler */ + IRQ_HANDLER 42 /* PWM0 IRQ handler */ + IRQ_HANDLER 43 /* HALL0 IRQ handler */ + IRQ_HANDLER 44 /* QEI0 IRQ handler */ + IRQ_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_HANDLER 46 /* HALL1 IRQ handler */ + IRQ_HANDLER 47 /* QEI1 IRQ handler */ + IRQ_HANDLER 48 /* SDP IRQ handler */ + IRQ_HANDLER 49 /* XPI0 IRQ handler */ + IRQ_HANDLER 50 /* XPI1 IRQ handler */ + IRQ_HANDLER 51 /* XDMA IRQ handler */ + IRQ_HANDLER 52 /* HDMA IRQ handler */ + IRQ_HANDLER 53 /* DRAM IRQ handler */ + IRQ_HANDLER 54 /* RNG IRQ handler */ + IRQ_HANDLER 55 /* I2S0 IRQ handler */ + IRQ_HANDLER 56 /* I2S1 IRQ handler */ + IRQ_HANDLER 57 /* DAO IRQ handler */ + IRQ_HANDLER 58 /* PDM IRQ handler */ + IRQ_HANDLER 59 /* FFA IRQ handler */ + IRQ_HANDLER 60 /* NTMR0 IRQ handler */ + IRQ_HANDLER 61 /* USB0 IRQ handler */ + IRQ_HANDLER 62 /* ENET0 IRQ handler */ + IRQ_HANDLER 63 /* SDXC0 IRQ handler */ + IRQ_HANDLER 64 /* PSEC IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PWDG IRQ handler */ + IRQ_HANDLER 67 /* PTMR IRQ handler */ + IRQ_HANDLER 68 /* PUART IRQ handler */ + IRQ_HANDLER 69 /* FUSE IRQ handler */ + IRQ_HANDLER 70 /* SECMON IRQ handler */ + IRQ_HANDLER 71 /* RTC IRQ handler */ + IRQ_HANDLER 72 /* BUTN IRQ handler */ + IRQ_HANDLER 73 /* BGPIO IRQ handler */ + IRQ_HANDLER 74 /* BVIO IRQ handler */ + IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c new file mode 100644 index 0000000000..68ce432bd4 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "riscv-stackframe.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +static void rt_show_stack_frame(void); + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + rt_kprintf("mdcause: FP disabled exception \r\n"); + break; + case 2: + rt_kprintf("mdcause: ACE disabled exception \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + rt_kprintf("mdcause: PMA NAMO exception \r\n"); + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + default: + rt_kprintf("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_show_stack_frame(); + while (1) + { + } +} + +void trap_entry(rt_hw_stack_frame_t *stack_frame); + +void trap_entry(rt_hw_stack_frame_t *stack_frame) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + + s_stack_frame = stack_frame; + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +static void rt_show_stack_frame(void) +{ + rt_kprintf("Stack frame:\r\n----------------------------------------\r\n"); + rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra); + rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS)); + rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); + rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); + rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2); + rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); + rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1); + rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2); + rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3); + rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4); + rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5); + rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6); + rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7); + rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3); + rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4); + rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5); + rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); +} diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/SConscript b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/SConscript new file mode 100644 index 0000000000..18c366ba28 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/SConscript @@ -0,0 +1,21 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Split(''' + startup.c + trap.c +''') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c new file mode 100644 index 0000000000..5d6123bd09 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S new file mode 100644 index 0000000000..2ccc4540ac --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_in_dlm + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Disable Vector mode */ + csrci CSR_MMISC_CTL, 2 + /* Initialize trap_entry base */ + la t0, irq_handler_trap + csrw mtvec, t0 + + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/vectors.S new file mode 100644 index 0000000000..7ac2b728b0 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/vectors.S @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + .section .vector_table, "a" + .global __vector_table + .align 9 +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_E IRQ handler */ + IRQ_HANDLER 15 /* GPIO1_F IRQ handler */ + IRQ_HANDLER 16 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 17 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 18 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 19 /* ADC0 IRQ handler */ + IRQ_HANDLER 20 /* ADC1 IRQ handler */ + IRQ_HANDLER 21 /* ADC2 IRQ handler */ + IRQ_HANDLER 22 /* ADC3 IRQ handler */ + IRQ_HANDLER 23 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 25 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 26 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 27 /* SPI0 IRQ handler */ + IRQ_HANDLER 28 /* SPI1 IRQ handler */ + IRQ_HANDLER 29 /* SPI2 IRQ handler */ + IRQ_HANDLER 30 /* SPI3 IRQ handler */ + IRQ_HANDLER 31 /* UART0 IRQ handler */ + IRQ_HANDLER 32 /* UART1 IRQ handler */ + IRQ_HANDLER 33 /* UART2 IRQ handler */ + IRQ_HANDLER 34 /* UART3 IRQ handler */ + IRQ_HANDLER 35 /* UART4 IRQ handler */ + IRQ_HANDLER 36 /* UART5 IRQ handler */ + IRQ_HANDLER 37 /* UART6 IRQ handler */ + IRQ_HANDLER 38 /* UART7 IRQ handler */ + IRQ_HANDLER 39 /* UART8 IRQ handler */ + IRQ_HANDLER 40 /* UART9 IRQ handler */ + IRQ_HANDLER 41 /* UART10 IRQ handler */ + IRQ_HANDLER 42 /* UART11 IRQ handler */ + IRQ_HANDLER 43 /* UART12 IRQ handler */ + IRQ_HANDLER 44 /* UART13 IRQ handler */ + IRQ_HANDLER 45 /* UART14 IRQ handler */ + IRQ_HANDLER 46 /* UART15 IRQ handler */ + IRQ_HANDLER 47 /* CAN0 IRQ handler */ + IRQ_HANDLER 48 /* CAN1 IRQ handler */ + IRQ_HANDLER 49 /* CAN2 IRQ handler */ + IRQ_HANDLER 50 /* CAN3 IRQ handler */ + IRQ_HANDLER 51 /* PTPC IRQ handler */ + IRQ_HANDLER 52 /* WDG0 IRQ handler */ + IRQ_HANDLER 53 /* WDG1 IRQ handler */ + IRQ_HANDLER 54 /* WDG2 IRQ handler */ + IRQ_HANDLER 55 /* WDG3 IRQ handler */ + IRQ_HANDLER 56 /* MBX0_CA IRQ handler */ + IRQ_HANDLER 57 /* MBX0_CB IRQ handler */ + IRQ_HANDLER 58 /* MBX1_CA IRQ handler */ + IRQ_HANDLER 59 /* MBX1_CB IRQ handler */ + IRQ_HANDLER 60 /* TMR0 IRQ handler */ + IRQ_HANDLER 61 /* TMR1 IRQ handler */ + IRQ_HANDLER 62 /* TMR2 IRQ handler */ + IRQ_HANDLER 63 /* TMR3 IRQ handler */ + IRQ_HANDLER 64 /* TMR4 IRQ handler */ + IRQ_HANDLER 65 /* TMR5 IRQ handler */ + IRQ_HANDLER 66 /* TMR6 IRQ handler */ + IRQ_HANDLER 67 /* TMR7 IRQ handler */ + IRQ_HANDLER 68 /* I2C0 IRQ handler */ + IRQ_HANDLER 69 /* I2C1 IRQ handler */ + IRQ_HANDLER 70 /* I2C2 IRQ handler */ + IRQ_HANDLER 71 /* I2C3 IRQ handler */ + IRQ_HANDLER 72 /* PWM0 IRQ handler */ + IRQ_HANDLER 73 /* HAL0 IRQ handler */ + IRQ_HANDLER 74 /* ENC0 IRQ handler */ + IRQ_HANDLER 75 /* PWM1 IRQ handler */ + IRQ_HANDLER 76 /* HAL1 IRQ handler */ + IRQ_HANDLER 77 /* ENC1 IRQ handler */ + IRQ_HANDLER 78 /* PWM2 IRQ handler */ + IRQ_HANDLER 79 /* HAL2 IRQ handler */ + IRQ_HANDLER 80 /* ENC2 IRQ handler */ + IRQ_HANDLER 81 /* PWM3 IRQ handler */ + IRQ_HANDLER 82 /* HAL3 IRQ handler */ + IRQ_HANDLER 83 /* ENC3 IRQ handler */ + IRQ_HANDLER 84 /* SDP IRQ handler */ + IRQ_HANDLER 85 /* XPI0 IRQ handler */ + IRQ_HANDLER 86 /* XPI1 IRQ handler */ + IRQ_HANDLER 87 /* XDMA IRQ handler */ + IRQ_HANDLER 88 /* HDMA IRQ handler */ + IRQ_HANDLER 89 /* DRAM IRQ handler */ + IRQ_HANDLER 90 /* RNG IRQ handler */ + IRQ_HANDLER 91 /* I2S0 IRQ handler */ + IRQ_HANDLER 92 /* I2S1 IRQ handler */ + IRQ_HANDLER 93 /* I2S2 IRQ handler */ + IRQ_HANDLER 94 /* I2S3 IRQ handler */ + IRQ_HANDLER 95 /* I2SCLASSD IRQ handler */ + IRQ_HANDLER 96 /* I2SPDM IRQ handler */ + IRQ_HANDLER 97 /* CAM0 IRQ handler */ + IRQ_HANDLER 98 /* CAM1 IRQ handler */ + IRQ_HANDLER 99 /* LCD_D0 IRQ handler */ + IRQ_HANDLER 100 /* LCD_D1 IRQ handler */ + IRQ_HANDLER 101 /* PDMA_D0 IRQ handler */ + IRQ_HANDLER 102 /* PDMA_D1 IRQ handler */ + IRQ_HANDLER 103 /* JPEG IRQ handler */ + IRQ_HANDLER 104 /* NTM0 IRQ handler */ + IRQ_HANDLER 105 /* NTM1 IRQ handler */ + IRQ_HANDLER 106 /* USB0 IRQ handler */ + IRQ_HANDLER 107 /* USB1 IRQ handler */ + IRQ_HANDLER 108 /* ENET0 IRQ handler */ + IRQ_HANDLER 109 /* ENET1 IRQ handler */ + IRQ_HANDLER 110 /* SDXC0 IRQ handler */ + IRQ_HANDLER 111 /* SDXC1 IRQ handler */ + IRQ_HANDLER 112 /* SEC_EVENT IRQ handler */ + IRQ_HANDLER 113 /* PMIC_GPIO IRQ handler */ + IRQ_HANDLER 114 /* PMIC_WDG IRQ handler */ + IRQ_HANDLER 115 /* PMIC_TMR IRQ handler */ + IRQ_HANDLER 116 /* PMIC_UART IRQ handler */ + IRQ_HANDLER 117 /* VAD IRQ handler */ + IRQ_HANDLER 118 /* FUSE IRQ handler */ + IRQ_HANDLER 119 /* SECMON IRQ handler */ + IRQ_HANDLER 120 /* BATT_RTC IRQ handler */ + IRQ_HANDLER 121 /* BUTTON IRQ handler */ + IRQ_HANDLER 122 /* BATT_GPIO IRQ handler */ + IRQ_HANDLER 123 /* VIOLATION IRQ handler */ + IRQ_HANDLER 124 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 125 /* CLK_FAIL IRQ handler */ + IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */ diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c new file mode 100644 index 0000000000..68ce432bd4 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "riscv-stackframe.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +static void rt_show_stack_frame(void); + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + rt_kprintf("mdcause: FP disabled exception \r\n"); + break; + case 2: + rt_kprintf("mdcause: ACE disabled exception \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + rt_kprintf("mdcause: PMA NAMO exception \r\n"); + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + default: + rt_kprintf("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_show_stack_frame(); + while (1) + { + } +} + +void trap_entry(rt_hw_stack_frame_t *stack_frame); + +void trap_entry(rt_hw_stack_frame_t *stack_frame) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + + s_stack_frame = stack_frame; + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +static void rt_show_stack_frame(void) +{ + rt_kprintf("Stack frame:\r\n----------------------------------------\r\n"); + rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra); + rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS)); + rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); + rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); + rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2); + rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); + rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1); + rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2); + rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3); + rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4); + rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5); + rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6); + rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7); + rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3); + rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4); + rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5); + rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); +} diff --git a/bsp/hpmicro/hpm6750evkmini/startup/SConscript b/bsp/hpmicro/hpm6750evkmini/startup/SConscript new file mode 100644 index 0000000000..de51a7c0d6 --- /dev/null +++ b/bsp/hpmicro/hpm6750evkmini/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/libraries/Kconfig b/bsp/hpmicro/libraries/Kconfig new file mode 100644 index 0000000000..faf5bc5bb4 --- /dev/null +++ b/bsp/hpmicro/libraries/Kconfig @@ -0,0 +1,4 @@ +config SOC_HPM6000_SERIES + bool + select ARCH_RISCV32 + select ARCH_RISCV_DPU diff --git a/bsp/hpmicro/libraries/drivers/SConscript b/bsp/hpmicro/libraries/drivers/SConscript new file mode 100644 index 0000000000..a58760f3ad --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/SConscript @@ -0,0 +1,63 @@ +from building import * + +cwd = GetCurrentDir() + +src = [] + +if GetDepend('BSP_USING_GPIO'): + src += ['drv_gpio.c'] + +if GetDepend('BSP_USING_SPI'): + src += [ 'drv_spi.c'] + +if GetDepend('BSP_USING_I2C'): + src += [ 'drv_i2c.c'] + +if GetDepend('BSP_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('BSP_USING_WDG'): + src += ['drv_wdt.c'] + +if GetDepend('BSP_USING_ETH'): + src += ['drv_enet.c'] + +if GetDepend('BSP_USING_SDXC'): + src += ['drv_sdio.c'] + +if GetDepend('BSP_USING_PWM'): + src += ['drv_pwm.c'] + +if GetDepend('BSP_USING_GPTMR'): + src += ['drv_hwtimer.c'] + +if GetDepend('BSP_USING_CAN'): + src += ['drv_can.c'] + +if GetDepend('BSP_USING_UART'): + if GetDepend(['RT_USING_SERIAL_V2']): + src += ['drv_uart_v2.c'] + else: + src += ['drv_uart.c'] + +if GetDepend('BSP_USING_ADC'): + src += ['drv_adc.c'] + +if GetDepend('BSP_USING_USB_HOST'): + src += ['drv_usb.c'] + +if GetDepend('BSP_USING_DAO'): + src += ['drv_dao.c'] + +if GetDepend('BSP_USING_PDM'): + src += ['drv_pdm.c'] + +if GetDepend('BSP_USING_I2S'): + src += ['drv_i2s.c'] + + +path = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/hpmicro/libraries/drivers/drv_adc.c b/bsp/hpmicro/libraries/drivers/drv_adc.c new file mode 100644 index 0000000000..b9b308e325 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_adc.c @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-05-08 hpmicro the first version + */ +#include + +#ifdef BSP_USING_ADC +#include +#include "board.h" +#include "drv_adc.h" +#ifdef BSP_USING_ADC12 +#include "hpm_adc12_drv.h" +#endif +#ifdef BSP_USING_ADC16 +#include "hpm_adc16_drv.h" +#endif +#include "hpm_sysctl_drv.h" + +typedef struct +{ + char *adc_name; + struct rt_adc_device hpm_adc_device; + uint16_t channel; +#ifdef BSP_USING_ADC12 + ADC12_Type *adc_base; +#endif +#ifdef BSP_USING_ADC16 + ADC16_Type *adc_base; +#endif +}hpm_rtt_adc; + +static hpm_rtt_adc hpm_adc_config_tbl[] = +{ +#ifdef BSP_USING_ADC0 + { + .adc_name = "adc0", +#ifdef BSP_USING_ADC12 + .adc_base = HPM_ADC0, +#endif +#ifdef BSP_USING_ADC16 + .adc_base = HPM_ADC0, +#endif + }, +#endif + +#ifdef BSP_USING_ADC1 + { + .adc_name = "adc1", +#ifdef BSP_USING_ADC12 + .adc_base = HPM_ADC1, +#endif +#ifdef BSP_USING_ADC16 + .adc_base = HPM_ADC1, +#endif + }, +#endif + +#ifdef BSP_USING_ADC2 + { + .adc_name = "adc2", +#ifdef BSP_USING_ADC12 + .adc_base = HPM_ADC2, +#endif +#ifdef BSP_USING_ADC16 + .adc_base = HPM_ADC2, +#endif + }, +#endif + +#ifdef BSP_USING_ADC3 + { + .adc_name = "adc3", +#ifdef BSP_USING_ADC12 + .adc_base = HPM_ADC3, +#endif +#ifdef BSP_USING_ADC16 + .adc_base = HPM_ADC3, +#endif + }, +#endif +}; + +static uint8_t adc_nums = sizeof(hpm_adc_config_tbl) / sizeof(hpm_rtt_adc); + +static rt_err_t init_adc_config(hpm_rtt_adc *adc) +{ +#ifdef BSP_USING_ADC12 + adc12_config_t cfg; + hpm_stat_t ret; + + adc12_get_default_config(&cfg); + cfg.res = adc12_res_12_bits; + cfg.conv_mode = adc12_conv_mode_oneshot; + cfg.adc_clk_div = 1; + ret = adc12_init(adc->adc_base, &cfg); + if (ret != status_success) { + return RT_ERROR; + } +#endif + +#ifdef BSP_USING_ADC16 + adc16_config_t cfg; + hpm_stat_t ret; + + adc16_get_default_config(&cfg); + cfg.conv_mode = adc16_conv_mode_oneshot; + cfg.adc_clk_div = 3; + cfg.sel_sync_ahb = true; + ret = adc16_init(adc->adc_base, &cfg); + if (ret != status_success) { + return RT_ERROR; + } +#endif + return RT_EOK; +} + +static rt_err_t init_channel_config(hpm_rtt_adc *adc) +{ +#ifdef BSP_USING_ADC12 + adc12_channel_config_t ch_cfg;; + hpm_stat_t ret; + + ch_cfg.ch = adc->channel; + ch_cfg.diff_sel = adc12_sample_signal_single_ended; + ch_cfg.sample_cycle = 20; + + ret = adc12_init_channel(adc->adc_base, &ch_cfg); + if (ret != status_success) { + return RT_ERROR; + } +#endif + +#ifdef BSP_USING_ADC16 + + adc16_channel_config_t ch_cfg;; + hpm_stat_t ret; + + ch_cfg.ch = adc->channel; + ch_cfg.sample_cycle = 20; + + ret = adc16_init_channel(adc->adc_base, &ch_cfg); + if (ret != status_success) { + return RT_ERROR; + } +#endif + return RT_EOK; +} + +static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + hpm_rtt_adc *hpm_adc_handler; + rt_err_t ret; + + RT_ASSERT(device != RT_NULL); + hpm_adc_handler = (hpm_rtt_adc *)device->parent.user_data; + ret = init_adc_config(hpm_adc_handler); + if (ret != RT_EOK) { + return RT_ERROR; + } + hpm_adc_handler->channel = channel; + ret = init_channel_config(hpm_adc_handler); + if (ret != RT_EOK) { + return RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + hpm_rtt_adc hpm_adc_handler; + rt_err_t ret; + rt_uint16_t val; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + hpm_adc_handler = *(hpm_rtt_adc *)device->parent.user_data; + hpm_adc_handler.channel = channel; +#ifdef BSP_USING_ADC12 + adc12_get_oneshot_result(hpm_adc_handler.adc_base, hpm_adc_handler.channel, &val); + *value = (val >> 4); +#endif + +#ifdef BSP_USING_ADC16 + adc16_get_oneshot_result(hpm_adc_handler.adc_base, hpm_adc_handler.channel, &val); + *value = val; +#endif + + return RT_EOK; +} + +static const struct rt_adc_ops hpm_adc_ops = +{ + .enabled = hpm_adc_enabled, + .convert = hpm_get_adc_value, +}; + +int rt_hw_adc_init(void) +{ + rt_err_t ret = RT_EOK; + + for (uint32_t i = 0; i < adc_nums; i++) { + ret = rt_hw_adc_register(&hpm_adc_config_tbl[i].hpm_adc_device, hpm_adc_config_tbl[i].adc_name, &hpm_adc_ops, &hpm_adc_config_tbl[i]); + if (ret != RT_EOK) { + ret = RT_ERROR; + break; + } + } + return ret; +} +INIT_BOARD_EXPORT(rt_hw_adc_init); + +#endif diff --git a/bsp/hpmicro/libraries/drivers/drv_adc.h b/bsp/hpmicro/libraries/drivers/drv_adc.h new file mode 100644 index 0000000000..ab524bfdde --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_adc.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-05-08 hpmicro the first version + */ +#ifndef LIBRARIES_DRIVERS_DRV_ADC_H_ +#define LIBRARIES_DRIVERS_DRV_ADC_H_ + +int rt_hw_adc_init(void); + +#endif /* LIBRARIES_DRIVERS_DRV_ADC_H_ */ diff --git a/bsp/hpmicro/libraries/drivers/drv_can.c b/bsp/hpmicro/libraries/drivers/drv_can.c new file mode 100644 index 0000000000..b520ce9010 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_can.c @@ -0,0 +1,703 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-05-08 hpmicro the first version + */ + +#include +#include +#include +#include "board.h" +#include "hpm_can_drv.h" + + +#define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */ +#define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */ +#define CAN_FILTER_NUM_MAX (16U) /* CAN Hardware Filter number */ + + +#ifdef RT_USING_CAN + +typedef struct _hpm_can_struct +{ + CAN_Type *can_base; /**< CAN Base address */ + const char *name; /**< CAN device name */ + int32_t irq_num; /**< CAN IRQ index */ + uint32_t fifo_index; /**< FIFO index, it is a fake value to satisfy the driver framework */ + can_config_t can_config; /**< CAN configuration for IP */ + struct rt_can_device can_dev; /**< CAN device configuration in rt-thread */ + uint32_t filter_num; /**< Filter number */ + can_filter_config_t filter_list[CAN_FILTER_NUM_MAX]; /**< Filter list */ +} hpm_can_t; + +/** + * @brief Configure CAN controller + * @param [in/out] can CAN device pointer + * @param [in] cfg CAN configuration pointer + * @retval RT_EOK for valid configuration + * @retval -RT_ERROR for invalid configuration + */ +static rt_err_t hpm_can_configure(struct rt_can_device *can, struct can_configure *cfg); + +/** + * @brief Control/Get CAN state + * including:interrupt, mode, priority, baudrate, filter, status + * @param [in/out] can CAN device pointer + * @param [in] cmd Control command + * @param [in/out] arg Argument pointer + * @retval RT_EOK for valid control command and arg + * @retval -RT_ERROR for invalid control command or arg + */ +static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg); + +/** + * @brief Send out CAN message + * @param [in] can CAN device pointer + * @param [in] buf CAN message buffer + * @param [in] boxno Mailbox number, it is not used in this porting + * @retval RT_EOK No error + * @retval -RT_ETIMEOUT timeout happened + * @retval -RT_EFULL Transmission buffer is full + */ +static int hpm_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno); + +/** + * @brief Receive message from CAN + * @param [in] can CAN device pointer + * @param [out] buf CAN receive buffer + * @param [in] boxno Mailbox Number, it is not used in this porting + * @retval RT_EOK no error + * @retval -RT_ERROR Error happened during reading receive FIFO + * @retval -RT_EMPTY no data in receive FIFO + */ +static int hpm_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno); + +/** + * @brief Common Interrupt Service routine + * @param [in] hpm_can HPM CAN pointer + */ +static void hpm_can_isr(hpm_can_t *hpm_can); + +/** + * @brief Decode data bytes from DLC + * @param [in] dlc Data Length Code + * @return decoded data bytes + */ +static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc); + +#if defined(HPM_CAN0_BASE) && defined(BSP_USING_CAN0) +static hpm_can_t dev_can0 = +{ + .can_base = HPM_CAN0, + .name = "can0", + .irq_num = IRQn_CAN0, + .fifo_index = 0, +}; + +void can0_isr(void) +{ + hpm_can_isr(&dev_can0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN0, can0_isr); + +#endif + +#if defined(HPM_CAN1_BASE) && defined(BSP_USING_CAN1) +static hpm_can_t dev_can1 = +{ + .can_base = HPM_CAN1, + .name = "can1", + .irq_num = IRQn_CAN1, + .fifo_index = 1, +}; +void can1_isr(void) +{ + hpm_can_isr(&dev_can1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN1, can1_isr); +#endif + +#if defined(HPM_CAN2_BASE) && defined(BSP_USING_CAN2) +static hpm_can_t dev_can2 = +{ + .can_base = HPM_CAN2, + .name = "can2", + .irq_num = IRQn_CAN2, + .fifo_index = 2, +}; +void can2_isr(void) +{ + hpm_can_isr(&dev_can2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN2, can2_isr); +#endif + +#if defined(HPM_CAN3_BASE) && defined(BSP_USING_CAN3) +static hpm_can_t dev_can3 = +{ + .can_base = HPM_CAN3, + .name = "can3", + .irq_num = IRQn_CAN3, + .fifo_index = 3, +}; +void can3_isr(void) +{ + hpm_can_isr(&dev_can3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN3, can3_isr); +#endif + +static hpm_can_t *hpm_cans[] = { +#if defined(HPM_CAN0_BASE) && defined(BSP_USING_CAN0) + &dev_can0, +#endif +#if defined(HPM_CAN1_BASE) && defined(BSP_USING_CAN1) + &dev_can1, +#endif +#if defined(HPM_CAN2_BASE) && defined(BSP_USING_CAN2) + &dev_can2, +#endif +#if defined(HPM_CAN3_BASE) && defined(BSP_USING_CAN3) + &dev_can3, +#endif + }; + + +static const struct rt_can_ops hpm_can_ops = { + .configure = hpm_can_configure, + .control = hpm_can_control, + .sendmsg = hpm_can_sendmsg, + .recvmsg = hpm_can_recvmsg, +}; + + + +static void hpm_can_isr(hpm_can_t *hpm_can) +{ + uint8_t tx_rx_flags = can_get_tx_rx_flags(hpm_can->can_base); + uint8_t error_flags = can_get_error_interrupt_flags(hpm_can->can_base); + + /* High-priority message transmission done */ + if ((tx_rx_flags & CAN_EVENT_TX_PRIMARY_BUF) != 0U) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8)); + } + + /* Normal priority message transmission done */ + if ((tx_rx_flags & CAN_EVENT_TX_SECONDARY_BUF) != 0U) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8)); + } + + /* Data available in FIFO */ + if ((tx_rx_flags & CAN_EVENT_RECEIVE) == CAN_EVENT_RECEIVE) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RX_IND | (hpm_can->fifo_index << 8)); + } + + /* RX FIFO overflow */ + if ((tx_rx_flags & CAN_EVENT_RX_BUF_OVERRUN) != 0U) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8)); + } + + /* Error happened on CAN Bus */ + if (((tx_rx_flags & CAN_EVENT_ERROR) != 0U) || (error_flags != 0U)) + { + uint8_t err_kind = can_get_last_error_kind(hpm_can->can_base); + switch(err_kind) + { + case CAN_KIND_OF_ERROR_ACK_ERROR: + hpm_can->can_dev.status.ackerrcnt++; + break; + case CAN_KIND_OF_ERROR_BIT_ERROR: + hpm_can->can_dev.status.biterrcnt++; + break; + case CAN_KIND_OF_ERROR_CRC_ERROR: + hpm_can->can_dev.status.crcerrcnt++; + break; + case CAN_KIND_OF_ERROR_FORM_ERROR: + hpm_can->can_dev.status.formaterrcnt++; + break; + case CAN_KIND_OF_ERROR_STUFF_ERROR: + hpm_can->can_dev.status.bitpaderrcnt++; + break; + } + + hpm_can->can_dev.status.rcverrcnt = can_get_receive_error_count(hpm_can->can_base); + hpm_can->can_dev.status.snderrcnt = can_get_transmit_error_count(hpm_can->can_base); + hpm_can->can_dev.status.lasterrtype = can_get_last_error_kind(hpm_can->can_base); + hpm_can->can_dev.status.errcode = 0; + if ((error_flags & CAN_ERROR_WARNING_LIMIT_FLAG) != 0U) + { + hpm_can->can_dev.status.errcode |= ERRWARNING; + } + if ((error_flags & CAN_ERROR_PASSIVE_INT_FLAG) != 0U) + { + hpm_can->can_dev.status.errcode |= ERRPASSIVE; + } + if (can_is_in_bus_off_mode(hpm_can->can_base)) + { + hpm_can->can_dev.status.errcode |= BUSOFF; + } + } + + can_clear_tx_rx_flags(hpm_can->can_base, tx_rx_flags); + can_clear_error_interrupt_flags(hpm_can->can_base, error_flags); +} + +static rt_err_t hpm_can_configure(struct rt_can_device *can, struct can_configure *cfg) +{ + RT_ASSERT(can); + RT_ASSERT(cfg); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + +#ifdef RT_CAN_USING_CANFD + drv_can->can_config.enable_canfd = (cfg->enable_canfd != 0) ? true : false; + if (cfg->use_bit_timing != 0U) + { + drv_can->can_config.use_lowlevel_timing_setting = true; + drv_can->can_config.can_timing.prescaler = cfg->can_timing.prescaler; + drv_can->can_config.can_timing.num_seg1 = cfg->can_timing.num_seg1; + drv_can->can_config.can_timing.num_seg2 = cfg->can_timing.num_seg2; + drv_can->can_config.can_timing.num_sjw = cfg->can_timing.num_sjw; + + drv_can->can_config.canfd_timing.prescaler = cfg->canfd_timing.prescaler; + drv_can->can_config.canfd_timing.num_seg1 = cfg->canfd_timing.num_seg1; + drv_can->can_config.canfd_timing.num_seg2 = cfg->canfd_timing.num_seg2; + drv_can->can_config.canfd_timing.num_sjw = cfg->canfd_timing.num_sjw; + } + else +#endif + { + drv_can->can_config.use_lowlevel_timing_setting = false; + drv_can->can_config.baudrate = cfg->baud_rate; +#ifdef RT_CAN_USING_CANFD + drv_can->can_config.baudrate_fd = cfg->baud_rate_fd; +#endif + } + + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + drv_can->can_config.mode = can_mode_normal; + break; + case RT_CAN_MODE_LISTEN: + drv_can->can_config.mode = can_mode_listen_only; + break; + case RT_CAN_MODE_LOOPBACK: + drv_can->can_config.mode = can_mode_loopback_internal; + break; + default: + return -RT_ERROR; + break; + } + + drv_can->can_config.enable_tx_buffer_priority_mode = (cfg->privmode != 0U) ? true : false; + init_can_pins(drv_can->can_base); + uint32_t can_clk = board_init_can_clock(drv_can->can_base); + drv_can->can_config.filter_list_num = drv_can->filter_num; + drv_can->can_config.filter_list = &drv_can->filter_list[0]; + hpm_stat_t status = can_init(drv_can->can_base, &drv_can->can_config, can_clk); + if (status != status_success) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) +{ + RT_ASSERT(can); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + + uint32_t arg_val; + rt_err_t err = RT_EOK; + + uint32_t temp; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + arg_val = (uint32_t) arg; + intc_m_disable_irq(drv_can->irq_num); + if (arg_val == RT_DEVICE_FLAG_INT_RX) + { + uint8_t irq_txrx_mask = CAN_EVENT_RECEIVE | CAN_EVENT_RX_BUF_ALMOST_FULL | CAN_EVENT_RX_BUF_FULL | CAN_EVENT_RX_BUF_OVERRUN; + drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask; + can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + } + else if (arg_val == RT_DEVICE_FLAG_INT_TX) + { + uint8_t irq_txrx_mask = CAN_EVENT_TX_PRIMARY_BUF | CAN_EVENT_TX_SECONDARY_BUF; + drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask; + can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + } + else if (arg_val == RT_DEVICE_CAN_INT_ERR) + { + uint8_t irq_txrx_mask = CAN_EVENT_ERROR; + uint8_t irq_error_mask = CAN_ERROR_ARBITRAITION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE; + drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask; + drv_can->can_config.irq_error_enable_mask &= (uint8_t)~irq_error_mask; + can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + can_disable_error_irq(drv_can->can_base, irq_error_mask); + } + else + { + err = -RT_ERROR; + } + break; + case RT_DEVICE_CTRL_SET_INT: + arg_val = (uint32_t) arg; + if (arg_val == RT_DEVICE_FLAG_INT_RX) + { + uint8_t irq_txrx_mask = CAN_EVENT_RECEIVE | CAN_EVENT_RX_BUF_ALMOST_FULL | CAN_EVENT_RX_BUF_FULL | CAN_EVENT_RX_BUF_OVERRUN; + drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask; + can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + } + else if (arg_val == RT_DEVICE_FLAG_INT_TX) + { + uint8_t irq_txrx_mask = CAN_EVENT_TX_PRIMARY_BUF | CAN_EVENT_TX_SECONDARY_BUF; + drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask; + can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + } + else if (arg_val == RT_DEVICE_CAN_INT_ERR) + { + uint8_t irq_txrx_mask = CAN_EVENT_ERROR; + uint8_t irq_error_mask = CAN_ERROR_ARBITRAITION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE; + drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask; + drv_can->can_config.irq_error_enable_mask |= irq_error_mask; + can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); + can_enable_error_irq(drv_can->can_base, irq_error_mask); + intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + } + else + { + err = -RT_ERROR; + } + break; + case RT_CAN_CMD_SET_FILTER: + { + /* Convert the RT-Thread Filter format to the filter format supported by HPM CAN */ + struct rt_can_filter_config *filter = (struct rt_can_filter_config*)arg; + if (filter != NULL) + { + drv_can->filter_num = filter->count; + RT_ASSERT(filter->count <= CAN_FILTER_NUM_MAX); + for (uint32_t i=0; icount; i++) + { + drv_can->filter_list[i].index = (filter->items[i].hdr == -1) ? i : filter->items[i].hdr; + drv_can->filter_list[i].enable = (filter->actived != 0U) ? true : false; + drv_can->filter_list[i].code = filter->items[i].id; + drv_can->filter_list[i].id_mode = (filter->items[i].ide != 0U) ? can_filter_id_mode_extended_frames : can_filter_id_mode_standard_frames; + drv_can->filter_list[i].mask = (~filter->items[i].mask) & ~(7UL <<29); + } + } + else + { + drv_can->filter_num = 0; + } + err = hpm_can_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_SET_MODE: + arg_val = (uint32_t) arg; + if ((arg_val != RT_CAN_MODE_NORMAL) && (arg_val != RT_CAN_MODE_LISTEN) && (arg_val != RT_CAN_MODE_LOOPBACK)) + { + err = -RT_ERROR; + break; + } + if (arg_val != drv_can->can_dev.config.mode) + { + drv_can->can_dev.config.mode = arg_val; + err = hpm_can_configure(can, &drv_can->can_dev.config); + } + + break; + case RT_CAN_CMD_SET_BAUD: + arg_val = (uint32_t) arg; + if (arg_val != drv_can->can_dev.config.baud_rate) + { + drv_can->can_dev.config.baud_rate = arg_val; + } + err = hpm_can_configure(can, &drv_can->can_dev.config); + break; +#ifdef RT_CAN_USING_CANFD + case RT_CAN_CMD_SET_CANFD: + arg_val = (uint32_t) arg; + if (arg_val != drv_can->can_dev.config.enable_canfd) + { + drv_can->can_dev.config.enable_canfd = arg_val; + err = hpm_can_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_SET_BAUD_FD: + arg_val = (uint32_t) arg; + if (arg_val != drv_can->can_dev.config.baud_rate_fd) + { + drv_can->can_dev.config.baud_rate_fd = arg_val; + err = hpm_can_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_SET_BITTIMING: + { + struct rt_can_bit_timing_config *timing_configs = (struct rt_can_bit_timing_config*)arg; + if ((timing_configs == RT_NULL) || (timing_configs->count < 1) || (timing_configs->count > 2)) + { + return -RT_ERROR; + } + + if (timing_configs->count != 0U) + { + drv_can->can_dev.config.can_timing = timing_configs->items[0]; + } + if (timing_configs->count == 2) + { + drv_can->can_dev.config.canfd_timing = timing_configs->items[1]; + } + err = hpm_can_configure(can, &drv_can->can_dev.config); + } + break; +#endif + case RT_CAN_CMD_SET_PRIV: + arg_val = (uint32_t)arg; + if ((arg_val != RT_CAN_MODE_PRIV) && (arg_val != RT_CAN_MODE_NOPRIV)) + { + return -RT_ERROR; + } + if (arg_val != drv_can->can_dev.config.privmode) + { + drv_can->can_dev.config.privmode = arg_val; + err = hpm_can_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_GET_STATUS: + drv_can->can_dev.status.rcverrcnt = can_get_receive_error_count(drv_can->can_base); + drv_can->can_dev.status.snderrcnt = can_get_transmit_error_count(drv_can->can_base); + drv_can->can_dev.status.lasterrtype = can_get_last_error_kind(drv_can->can_base); + temp = can_get_error_interrupt_flags(drv_can->can_base); + drv_can->can_dev.status.errcode = 0; + if ((temp & CAN_ERROR_WARNING_LIMIT_FLAG) != 0U) + { + drv_can->can_dev.status.errcode |= ERRWARNING; + } + if ((temp & CAN_ERROR_PASSIVE_INT_FLAG) != 0U) + { + drv_can->can_dev.status.errcode |= ERRPASSIVE; + } + if (can_is_in_bus_off_mode(drv_can->can_base)) + { + drv_can->can_dev.status.errcode |= BUSOFF; + } + rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status)); + break; + } +} + +static int hpm_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) +{ + RT_ASSERT(can); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + + struct rt_can_msg *can_msg = (struct rt_can_msg *) buf; + + can_transmit_buf_t tx_buf = { 0 }; + tx_buf.id = can_msg->id; + if (can_msg->ide == RT_CAN_STDID) + { + tx_buf.extend_id = false; + } + else + { + tx_buf.extend_id = true; + } + + if (can_msg->rtr == RT_CAN_DTR) + { + tx_buf.remote_frame = false; + } + else + { + tx_buf.remote_frame = true; + } + +#ifdef RT_CAN_USING_CANFD + if (can_msg->fd_frame != 0) + { + tx_buf.canfd_frame = 1; + tx_buf.bitrate_switch = 1; + + RT_ASSERT(can_msg->len <= 15); + } + else +#endif + { + RT_ASSERT(can_msg->len <= 8); + } + + uint32_t msg_len = can_get_data_bytes_from_dlc(can_msg->len); + for (uint32_t i = 0; i < msg_len; i++) + { + tx_buf.data[i] = can_msg->data[i]; + } + tx_buf.dlc = can_msg->len; + + uint32_t delay_cnt = 0; + + if (can_msg->priv != 0U) + { + while (can_is_primary_transmit_buffer_full(drv_can->can_base)) + { + rt_thread_mdelay(1); + delay_cnt++; + if (delay_cnt >= CAN_SEND_WAIT_MS_MAX) + { + return -RT_ETIMEOUT; + } + } + hpm_stat_t status = can_send_message_nonblocking(drv_can->can_base, &tx_buf); + if (status != status_success) + { + return -RT_EFULL; + } + } + else + { + while (can_is_secondary_transmit_buffer_full(drv_can->can_base)) + { + rt_thread_mdelay(1); + delay_cnt++; + if (delay_cnt >= CAN_SEND_WAIT_MS_MAX) + { + return -RT_ETIMEOUT; + } + } + hpm_stat_t status = can_send_message_nonblocking(drv_can->can_base, &tx_buf); + if (status != status_success) + { + return -RT_EFULL; + } + } + + return RT_EOK; +} + +static int hpm_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) +{ + RT_ASSERT(can); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + + rt_can_msg_t can_msg = (rt_can_msg_t)buf; + + if (can_is_data_available_in_receive_buffer(drv_can->can_base)) { + can_receive_buf_t rx_buf; + hpm_stat_t status = can_read_received_message(drv_can->can_base, &rx_buf); + if (status != status_success) { + return -RT_ERROR; + } + + if (rx_buf.extend_id != 0) { + can_msg->ide = RT_CAN_EXTID; + } + else { + can_msg->ide = RT_CAN_STDID; + } + can_msg->id = rx_buf.id; + + if (rx_buf.remote_frame != 0) { + can_msg->rtr = RT_CAN_RTR; + } + else { + can_msg->rtr = RT_CAN_DTR; + } + + can_msg->len = rx_buf.dlc; + uint32_t msg_len = can_get_data_bytes_from_dlc(can_msg->len); + for(uint32_t i = 0; i < msg_len; i++) { + can_msg->data[i] = rx_buf.data[i]; + } + } + else { + return -RT_EEMPTY; + } + + return RT_EOK; +} + +static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc) +{ + uint32_t data_bytes = 0; + + dlc &= 0xFU; + if (dlc <= 8U) { + data_bytes = dlc; + } else { + switch (dlc) { + case can_payload_size_12: + data_bytes = 12U; + break; + case can_payload_size_16: + data_bytes = 16U; + break; + case can_payload_size_20: + data_bytes = 20U; + break; + case can_payload_size_24: + data_bytes = 24U; + break; + case can_payload_size_32: + data_bytes = 32U; + break; + case can_payload_size_48: + data_bytes = 48U; + break; + case can_payload_size_64: + data_bytes = 64U; + break; + default: + /* Code should never touch here */ + break; + } + } + + return data_bytes; +} + +int rt_hw_can_init(void) +{ + struct can_configure config = CANDEFAULTCONFIG; + config.privmode = RT_CAN_MODE_NOPRIV; + config.sndboxnumber = CAN_SENDBOX_NUM; + config.ticks = 50; + + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) + { + hpm_cans[i]->can_dev.config = config; + hpm_cans[i]->filter_num = 0; + can_get_default_config(&hpm_cans[i]->can_config); + rt_hw_can_register(&hpm_cans[i]->can_dev, hpm_cans[i]->name, &hpm_can_ops, hpm_cans[i]); + } + return RT_EOK; +} + +INIT_BOARD_EXPORT(rt_hw_can_init); + +#endif + + diff --git a/bsp/hpmicro/libraries/drivers/drv_can.h b/bsp/hpmicro/libraries/drivers/drv_can.h new file mode 100644 index 0000000000..320248116d --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_can.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRV_CAN_H +#define DRV_CAN_H + +int rt_hw_can_init(void); + +#endif /* DRV_CAN_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_dao.c b/bsp/hpmicro/libraries/drivers/drv_dao.c new file mode 100644 index 0000000000..01cdf69ffe --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_dao.c @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include + +#define DBG_TAG "dao" +#define DBG_LVL DBG_INFO +#include + +#ifdef BSP_USING_DAO +#include "drivers/audio.h" +#include "hpm_i2s_drv.h" +#include "hpm_dao_drv.h" +#include "board.h" +#include "drv_dao.h" +#include "hpm_dma_drv.h" +#include "hpm_dmamux_drv.h" +#include "hpm_l1c_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_dma_manager.h" + +/* DAO connect to I2S1 TX*/ +#define DAO_DMA_REQ HPM_DMA_SRC_I2S1_TX +#define DAO_I2S_DATA_LINE 0 + +struct hpm_dao +{ + struct rt_audio_device audio; + struct rt_audio_configure play_config; + rt_uint8_t* tx_fifo; +}; + +struct hpm_dao hpm_dao_dev = { 0 }; +static hpm_dma_resource_t dma_resource = { 0 }; + +void dao_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +{ + if (int_stat == DMA_CHANNEL_STATUS_TC) { + rt_audio_tx_complete(&hpm_dao_dev.audio); + } +} + +static rt_err_t hpm_dao_getcaps(struct rt_audio_device* audio, struct rt_audio_caps* caps) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(audio != RT_NULL); + struct hpm_dao* hpm_audio = (struct hpm_dao*)audio->parent.user_data; + + switch(caps->main_type) + { + case AUDIO_TYPE_OUTPUT: + { + switch(caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.samplerate = hpm_audio->play_config.samplerate; + caps->udata.config.channels = hpm_audio->play_config.channels; + caps->udata.config.samplebits = hpm_audio->play_config.samplebits; + break; + + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = hpm_audio->play_config.samplerate; + break; + + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = hpm_audio->play_config.channels; + break; + + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = hpm_audio->play_config.samplebits; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t hpm_dao_set_samplerate(uint32_t samplerate) +{ + uint32_t mclk_hz; + i2s_transfer_config_t transfer; + + mclk_hz = clock_get_frequency(clock_i2s1); + i2s_get_default_transfer_config_for_dao(&transfer); + transfer.sample_rate = samplerate; + if (status_success != i2s_config_tx(DAO_I2S, mclk_hz, &transfer)) + { + LOG_E("dao_i2s configure transfer failed\n"); + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_dao_configure(struct rt_audio_device* audio, struct rt_audio_caps* caps) +{ + + rt_err_t result = RT_EOK; + RT_ASSERT(audio != RT_NULL); + + struct hpm_dao* hpm_audio = (struct hpm_dao*)audio->parent.user_data; + + switch(caps->main_type) + { + case AUDIO_TYPE_OUTPUT: + { + switch(caps->sub_type) + { + case AUDIO_DSP_SAMPLERATE: + { + hpm_audio->play_config.samplerate = caps->udata.config.samplerate; + hpm_dao_set_samplerate(caps->udata.config.samplerate); + break; + } + + default: + result = -RT_ERROR; + break; + } + } + + default: + result = -RT_ERROR; + break; + } + return result; +} + +static rt_err_t hpm_dao_init(struct rt_audio_device* audio) +{ + RT_ASSERT(audio != RT_NULL); + rt_uint32_t mclk_hz; + i2s_config_t i2s_config; + i2s_transfer_config_t transfer; + dao_config_t dao_config; + + init_dao_pins(); + board_init_dao_clock(); + + i2s_get_default_config(DAO_I2S, &i2s_config); + i2s_init(DAO_I2S, &i2s_config); + i2s_enable_tx_dma_request(DAO_I2S); + + mclk_hz = clock_get_frequency(clock_i2s1); + i2s_get_default_transfer_config_for_dao(&transfer); + if (status_success != i2s_config_tx(DAO_I2S, mclk_hz, &transfer)) + { + LOG_E("dao_i2s configure transfer failed\n"); + return -RT_ERROR; + } + + /* init audio configure */ + hpm_dao_dev.play_config.channels = 2U; /* fix to 2 channels*/ + hpm_dao_dev.play_config.samplebits = 32U; /* fix to 32 sample bits */ + hpm_dao_dev.play_config.samplerate = 48000U; /* default 48KHz sample rate */ + + dao_get_default_config(HPM_DAO, &dao_config); + dao_config.enable_mono_output = true; + if (status_success != dao_init(HPM_DAO, &dao_config)) { + LOG_E("dao init failed\n"); + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_dao_start(struct rt_audio_device* audio, int stream) +{ + RT_ASSERT(audio != RT_NULL); + + dao_start(HPM_DAO); + + if (dma_manager_request_resource(&dma_resource) == status_success) { + uint8_t dmamux_ch; + dma_manager_install_interrupt_callback(&dma_resource, dao_dma_callback, NULL); + dma_manager_enable_dma_interrupt(&dma_resource, 1); + dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource.base, dma_resource.channel); + dmamux_config(HPM_DMAMUX, dmamux_ch, DAO_DMA_REQ, true); + } else { + LOG_E("no dma resource available for DAO transfer.\n"); + return -RT_ERROR; + } + + rt_audio_tx_complete(audio); + + return RT_EOK; +} + +static rt_err_t hpm_dao_stop(struct rt_audio_device* audio, int stream) +{ + RT_ASSERT(audio != RT_NULL); + + dao_stop(HPM_DAO); + + dma_manager_release_resource(&dma_resource); + + return RT_EOK; +} + +static rt_size_t hpm_dao_transmit(struct rt_audio_device* audio, const void* writeBuf, void* readBuf, rt_size_t size) +{ + RT_ASSERT(audio != RT_NULL); + + dma_channel_config_t ch_config = {0}; + dma_default_channel_config(dma_resource.base, &ch_config); + ch_config.src_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)writeBuf); + ch_config.dst_addr = (uint32_t)&DAO_I2S->TXD[DAO_I2S_DATA_LINE]; + ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; + ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; + ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + ch_config.size_in_byte = size; + ch_config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + + if (l1c_dc_is_enabled()) { + /* cache writeback for sent buff */ + l1c_dc_writeback((uint32_t)writeBuf, size); + } + + if (status_success != dma_setup_channel(dma_resource.base, dma_resource.channel, &ch_config)) { + return 0; + } + + return size; +} + +static void hpm_dao_buffer_info(struct rt_audio_device* audio, struct rt_audio_buf_info* info) +{ + RT_ASSERT(audio != RT_NULL); + /** + * AUD_FIFO + * +----------------+----------------+ + * | block1 | block2 | + * +----------------+----------------+ + * \ block_size / + */ + info->buffer = hpm_dao_dev.tx_fifo; + info->total_size = DAO_FIFO_SIZE; + info->block_size = DAO_FIFO_SIZE / 2; + info->block_count = 2; +} + +static struct rt_audio_ops hpm_dao_ops = +{ + .getcaps = hpm_dao_getcaps, + .configure = hpm_dao_configure, + .init = hpm_dao_init, + .start = hpm_dao_start, + .stop = hpm_dao_stop, + .transmit = hpm_dao_transmit, + .buffer_info = hpm_dao_buffer_info, +}; + +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t dao_tx_fifo[DAO_FIFO_SIZE]; + +int rt_hw_dao_init(void) +{ + hpm_dao_dev.tx_fifo = dao_tx_fifo; + + hpm_dao_dev.audio.ops = &hpm_dao_ops; + + LOG_I("audio dao registered.\n"); + LOG_I("!!!Note: dao depends on i2s1, they share clock.\n"); + rt_audio_register(&hpm_dao_dev.audio, "dao", RT_DEVICE_FLAG_WRONLY, &hpm_dao_dev); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_dao_init); + + +#endif /* BSP_USING_DAO */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_dao.h b/bsp/hpmicro/libraries/drivers/drv_dao.h new file mode 100644 index 0000000000..3a7915b2c1 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_dao.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRV_DAO_H +#define DRV_DAO_H + +#define DAO_FIFO_SIZE (2048) + +int rt_hw_dao_init(void); + +#endif /* DRV_DAO_H */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_enet.c b/bsp/hpmicro/libraries/drivers/drv_enet.c new file mode 100644 index 0000000000..c9e4819ebb --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_enet.c @@ -0,0 +1,529 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-01-11 hpmicro First version + * 2022-07-10 hpmicro Driver optimization for multiple instances + */ + +#include + +#ifdef BSP_USING_ETH +#include +#include +#include "board.h" +#include "drv_enet.h" +#include "hpm_soc_feature.h" +#include "hpm_enet_soc_drv.h" +#include "hpm_enet_drv.h" + +#define ETH_DEBUG + +#ifdef BSP_USING_ETH0 + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) +__RW enet_rx_desc_t enet0_dma_rx_desc_tab[ENET0_RX_BUFF_COUNT] ; /* Ethernet0 Rx DMA Descriptor */ + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) +__RW enet_tx_desc_t enet0_dma_tx_desc_tab[ENET0_TX_BUFF_COUNT] ; /* Ethernet0 Tx DMA Descriptor */ + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +__RW uint8_t enet0_rx_buff[ENET0_RX_BUFF_COUNT][ENET0_RX_BUFF_SIZE]; /* Ethernet0 Receive Buffer */ + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +__RW uint8_t enet0_tx_buff[ENET0_TX_BUFF_COUNT][ENET0_TX_BUFF_SIZE]; /* Ethernet0 Transmit Buffer */ + +struct eth_device eth0_dev; +static enet_device enet0_dev; +static enet_buff_config_t enet0_rx_buff_cfg = {.buffer = (uint32_t)enet0_rx_buff, + .count = ENET0_RX_BUFF_COUNT, + .size = ENET0_RX_BUFF_SIZE + }; + +static enet_buff_config_t enet0_tx_buff_cfg = {.buffer = (uint32_t)enet0_tx_buff, + .count = ENET0_TX_BUFF_COUNT, + .size = ENET0_TX_BUFF_SIZE + }; + +static enet_ptp_time_t ptp_timestamp0 = {0, 0}; +static enet_ptp_config_t ptp_config0 = {.sub_sec_count_res = enet_ptp_count_res_low, + .update_method = enet_ptp_time_fine_update, + .addend = 0xffffffff, + }; + +static hpm_enet_t enet0 = {.name = "ETH0", + .base = HPM_ENET0, + .irq_num = IRQn_ENET0, + .inf = BOARD_ENET0_INF, + .eth_dev = ð0_dev, + .enet_dev = &enet0_dev, + .rx_buff_cfg = &enet0_rx_buff_cfg, + .tx_buff_cfg = &enet0_tx_buff_cfg, + .dma_rx_desc_tab = enet0_dma_rx_desc_tab, + .dma_tx_desc_tab = enet0_dma_tx_desc_tab, + .tx_delay = BOARD_ENET0_TX_DLY, + .rx_delay = BOARD_ENET0_RX_DLY, + .ptp_enable = true, + .ptp_clk_src = BOARD_ENET0_PTP_CLOCK, + .ptp_config = &ptp_config0, + .ptp_timestamp = &ptp_timestamp0 + }; +#endif + +#ifdef BSP_USING_ETH1 + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) +__RW enet_rx_desc_t enet1_dma_rx_desc_tab[ENET1_RX_BUFF_COUNT]; /* Ethernet1 Rx DMA Descriptor */ + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) +__RW enet_tx_desc_t enet1_dma_tx_desc_tab[ENET1_TX_BUFF_COUNT]; /* Ethernet1 Tx DMA Descriptor */ + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +__RW uint8_t enet1_rx_buff[ENET1_RX_BUFF_COUNT][ENET1_RX_BUFF_SIZE]; /* Ethernet1 Receive Buffer */ + +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +__RW uint8_t enet1_tx_buff[ENET1_TX_BUFF_COUNT][ENET1_TX_BUFF_SIZE]; /* Ethernet1 Transmit Buffer */ + +struct eth_device eth1_dev; +static enet_device enet1_dev; +static enet_buff_config_t enet1_rx_buff_cfg = {.buffer = (uint32_t)enet1_rx_buff, + .count = ENET1_RX_BUFF_COUNT, + .size = ENET1_RX_BUFF_SIZE + }; + +static enet_buff_config_t enet1_tx_buff_cfg = {.buffer = (uint32_t)enet1_tx_buff, + .count = ENET1_TX_BUFF_COUNT, + .size = ENET1_TX_BUFF_SIZE + }; + +static enet_ptp_time_t ptp_timestamp1 = {0, 0}; +static enet_ptp_config_t ptp_config1 = {.sub_sec_count_res = enet_ptp_count_res_low, + .update_method = enet_ptp_time_fine_update, + .addend = 0xffffffff, + }; + +static hpm_enet_t enet1 = {.name = "ETH1", + .base = HPM_ENET1, + .irq_num = IRQn_ENET1, + .inf = BOARD_ENET1_INF, + .eth_dev = ð1_dev, + .enet_dev = &enet1_dev, + .rx_buff_cfg = &enet1_rx_buff_cfg, + .tx_buff_cfg = &enet1_tx_buff_cfg, + .dma_rx_desc_tab = enet1_dma_rx_desc_tab, + .dma_tx_desc_tab = enet1_dma_tx_desc_tab, + .int_refclk = BOARD_ENET1_INT_REF_CLK, + .ptp_enable = true, + .ptp_clk_src = BOARD_ENET1_PTP_CLOCK, + .ptp_config = &ptp_config1, + .ptp_timestamp = &ptp_timestamp1 + }; + +#endif + +static hpm_enet_t *s_geths[] = { +#ifdef BSP_USING_ETH0 + &enet0, +#endif + +#ifdef BSP_USING_ETH1 + &enet1 +#endif +}; + + +static hpm_stat_t hpm_enet_init(enet_device *init) +{ + /* Initialize eth controller */ + enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, init->mask, init->dis_mask); + + if (init->media_interface == enet_inf_rmii) + { + /* Initialize reference clock */ + board_init_enet_rmii_reference_clock(init->instance, init->int_refclk); + enet_rmii_enable_clock(init->instance, init->int_refclk); + } + + /* Set RGMII clock delay */ + if (init->media_interface == enet_inf_rgmii) + { + enet_rgmii_enable_clock(init->instance); + enet_rgmii_set_clock_delay(init->instance, init->tx_delay, init->rx_delay); + } + + if (init->ptp_enable) + { + /* initialize Ethernet PTP Module */ + init->ptp_config.ssinc = ENET_ONE_SEC_IN_NANOSEC / clock_get_frequency(init->ptp_clk_src); + enet_init_ptp(init->instance, &init->ptp_config); + + /* set the initial timestamp */ + enet_set_ptp_timestamp(init->instance, &init->ptp_timestamp); + } + + /* enable irq */ + intc_m_enable_irq(init->irq_number); +} + +static rt_err_t rt_hpm_eth_init(rt_device_t dev) +{ + enet_device *enet_dev = (enet_device *)dev->user_data; + + /* Initialize GPIOs */ + board_init_enet_pins(enet_dev->instance); + + /* Reset an enet PHY */ + board_reset_enet_phy(enet_dev->instance); + + /* Initialize MAC and DMA */ + if (hpm_enet_init(enet_dev) == 0) { + LOG_D("Ethernet control initialize successfully\n"); + } + + return RT_EOK; +} + +static rt_err_t rt_hpm_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_hpm_eth_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_hpm_eth_read(rt_device_t dev, rt_off_t pos, void * buffer, rt_size_t size) +{ + return 0; +} + +static rt_size_t rt_hpm_eth_write(rt_device_t dev, rt_off_t pos, const void * buffer, rt_size_t size) +{ + return 0; +} + +static rt_err_t rt_hpm_eth_control(rt_device_t dev, int cmd, void * args) +{ + uint8_t *mac; + + switch (cmd) + { + case NIOCTL_GADDR: + /* read MAC address */ + if (args != NULL) + { + mac = (uint8_t *)args; + mac[0] = MAC_ADDR0; + mac[1] = MAC_ADDR1; + mac[2] = MAC_ADDR2; + mac[3] = MAC_ADDR3; + mac[4] = MAC_ADDR4; + mac[5] = MAC_ADDR5; + SMEMCPY(args, mac, 6); + } + else + { + return -RT_ERROR; + } + break; + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) +{ + rt_err_t ret = RT_ERROR; + uint32_t status; + enet_device *enet_dev = (enet_device *)dev->user_data; + uint32_t tx_buff_size = enet_dev->desc.tx_buff_cfg.size; + struct pbuf *q; + uint8_t *buffer; + __IO enet_tx_desc_t *dma_tx_desc; + uint32_t frame_length = 0; + uint32_t buffer_offset = 0; + uint32_t bytes_left_to_copy = 0; + uint32_t payload_offset = 0; + enet_tx_desc_t *tx_desc_list_cur = enet_dev->desc.tx_desc_list_cur; + + dma_tx_desc = tx_desc_list_cur; + buffer = (uint8_t *)(dma_tx_desc->tdes2_bm.buffer1); + buffer_offset = 0; + + /* copy frame from pbufs to driver buffers */ + for (q = p; q != NULL; q = q->next) + { + /* Get bytes in current lwIP buffer */ + bytes_left_to_copy = q->len; + payload_offset = 0; + + /* Check if the length of data to copy is bigger than Tx buffer size*/ + while ((bytes_left_to_copy + buffer_offset) > tx_buff_size) + { + /* Copy data to Tx buffer*/ + SMEMCPY((uint8_t *)((uint8_t *)buffer + buffer_offset), + (uint8_t *)((uint8_t *)q->payload + payload_offset), + tx_buff_size - buffer_offset); + + /* Point to next descriptor */ + dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); + + /* Check if the buffer is available */ + if (dma_tx_desc->tdes0_bm.own != 0) + { + LOG_E("DMA tx desc buffer is not valid\n"); + return ERR_USE; + } + + buffer = (uint8_t *)(dma_tx_desc->tdes2_bm.buffer1); + + bytes_left_to_copy = bytes_left_to_copy - (tx_buff_size - buffer_offset); + payload_offset = payload_offset + (tx_buff_size - buffer_offset); + frame_length = frame_length + (tx_buff_size - buffer_offset); + buffer_offset = 0; + } + + /* Copy the remaining bytes */ + SMEMCPY((uint8_t *)((uint8_t *)buffer + buffer_offset), + (uint8_t *)((uint8_t *)q->payload + payload_offset), + bytes_left_to_copy); + + buffer_offset = buffer_offset + bytes_left_to_copy; + frame_length = frame_length + bytes_left_to_copy; + } + + /* Prepare transmit descriptors to give to DMA */ + LOG_D("The length of the transmitted frame: %d\n", frame_length); + + frame_length += 4; + status = enet_prepare_transmission_descriptors(enet_dev->instance, &enet_dev->desc.tx_desc_list_cur, frame_length, enet_dev->desc.tx_buff_cfg.size); + if (status != ENET_SUCCESS) + { + LOG_E("Ethernet controller transmit unsuccessfully: %d\n", status); + } + + return ERR_OK; +} + +static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) +{ + struct pbuf *p = NULL, *q = NULL; + enet_device *enet_dev = (enet_device *)dev->user_data; + uint32_t rx_buff_size = enet_dev->desc.rx_buff_cfg.size; + uint16_t len = 0; + uint8_t *buffer; + enet_frame_t frame = {0, 0, 0}; + enet_rx_desc_t *dma_rx_desc; + uint32_t buffer_offset = 0; + uint32_t payload_offset = 0; + uint32_t bytes_left_to_copy = 0; + uint32_t i = 0; + + /* Get a received frame */ + frame = enet_get_received_frame_interrupt(&enet_dev->desc.rx_desc_list_cur, + &enet_dev->desc.rx_frame_info, + enet_dev->desc.rx_buff_cfg.count); + + /* Obtain the size of the packet and put it into the "len" variable. */ + len = frame.length; + buffer = (uint8_t *)frame.buffer; + + LOG_D("The current received frame length : %d\n", len); + + if (len > 0) + { + /* allocate a pbuf chain of pbufs from the Lwip buffer pool */ + p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + } + + if (p != NULL) + { + dma_rx_desc = frame.rx_desc; + buffer_offset = 0; + for (q = p; q != NULL; q = q->next) + { + bytes_left_to_copy = q->len; + payload_offset = 0; + + /* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/ + while ((bytes_left_to_copy + buffer_offset) > rx_buff_size) + { + /* Copy data to pbuf */ + SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), (rx_buff_size - buffer_offset)); + + /* Point to next descriptor */ + dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc); + buffer = (uint8_t *)(dma_rx_desc->rdes2_bm.buffer1); + + bytes_left_to_copy = bytes_left_to_copy - (rx_buff_size - buffer_offset); + payload_offset = payload_offset + (rx_buff_size - buffer_offset); + buffer_offset = 0; + } + /* Copy remaining data in pbuf */ + SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), bytes_left_to_copy); + buffer_offset = buffer_offset + bytes_left_to_copy; + } + } + else + { + return NULL; + } + + /* Release descriptors to DMA */ + /* Point to first descriptor */ + dma_rx_desc = frame.rx_desc; + + /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ + for (i = 0; i < enet_dev->desc.rx_frame_info.seg_count; i++) + { + dma_rx_desc->rdes0_bm.own = 1; + dma_rx_desc = (enet_rx_desc_t*)(dma_rx_desc->rdes3_bm.next_desc); + } + + /* Clear Segment_Count */ + enet_dev->desc.rx_frame_info.seg_count = 0; + + return p; +} + +static void eth_rx_callback(struct eth_device* dev) +{ + rt_err_t result; + result = eth_device_ready(dev); + if (result != RT_EOK) + { + LOG_I("Receive callback error = %d\n", result); + } +} + +void isr_enet(hpm_enet_t *obj) +{ + uint32_t status; + + status = obj->base->DMA_STATUS; + + if (ENET_DMA_STATUS_GLPII_GET(status)) { + obj->base->DMA_STATUS |= ENET_DMA_STATUS_GLPII_SET(ENET_DMA_STATUS_GLPII_GET(status)); + } + + if (ENET_DMA_STATUS_RI_GET(status)) { + obj->base->DMA_STATUS |= ENET_DMA_STATUS_RI_SET(ENET_DMA_STATUS_RI_GET(status)); + eth_rx_callback(obj->eth_dev); + } +} + +#ifdef BSP_USING_ETH0 +void isr_enet0(void) +{ + isr_enet(&enet0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_ENET0, isr_enet0) +#endif + +#ifdef BSP_USING_ETH1 +void isr_enet1(void) +{ + isr_enet(&enet1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_ENET1, isr_enet1) +#endif + +int rt_hw_eth_init(void) +{ + rt_err_t err = RT_ERROR; + + for (uint32_t i = 0; i < ARRAY_SIZE(s_geths); i++) + { + /* Clear memory */ + memset((uint8_t *)s_geths[i]->dma_rx_desc_tab, 0x00, sizeof(enet_rx_desc_t) * s_geths[i]->rx_buff_cfg->count); + memset((uint8_t *)s_geths[i]->dma_tx_desc_tab, 0x00, sizeof(enet_tx_desc_t) * s_geths[i]->tx_buff_cfg->count); + + memset((uint8_t *)s_geths[i]->rx_buff_cfg->buffer, 0x00, sizeof(s_geths[i]->rx_buff_cfg->size)); + memset((uint8_t *)s_geths[i]->tx_buff_cfg->buffer, 0x00, sizeof(s_geths[i]->tx_buff_cfg->size)); + + /* Set list heads */ + s_geths[i]->enet_dev->desc.tx_desc_list_head = (enet_tx_desc_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)s_geths[i]->dma_tx_desc_tab); + s_geths[i]->enet_dev->desc.rx_desc_list_head = (enet_rx_desc_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)s_geths[i]->dma_rx_desc_tab); + + s_geths[i]->enet_dev->desc.tx_buff_cfg.buffer = core_local_mem_to_sys_address(BOARD_RUNNING_CORE, s_geths[i]->tx_buff_cfg->buffer); + s_geths[i]->enet_dev->desc.tx_buff_cfg.count = s_geths[i]->tx_buff_cfg->count; + s_geths[i]->enet_dev->desc.tx_buff_cfg.size = s_geths[i]->tx_buff_cfg->size; + + s_geths[i]->enet_dev->desc.rx_buff_cfg.buffer = core_local_mem_to_sys_address(BOARD_RUNNING_CORE, s_geths[i]->rx_buff_cfg->buffer); + s_geths[i]->enet_dev->desc.rx_buff_cfg.count = s_geths[i]->rx_buff_cfg->count; + s_geths[i]->enet_dev->desc.rx_buff_cfg.size = s_geths[i]->rx_buff_cfg->size; + + /* Set mac0 address */ + s_geths[i]->enet_dev->mac_config.mac_addr_high[0] = MAC_ADDR5 << 8 | MAC_ADDR4; + s_geths[i]->enet_dev->mac_config.mac_addr_low[0] = MAC_ADDR3 << 24 | MAC_ADDR2 << 16 | MAC_ADDR1 << 8 | MAC_ADDR0; + s_geths[i]->enet_dev->mac_config.valid_max_count = 1; + + /* Set instance */ + s_geths[i]->enet_dev->instance = s_geths[i]->base; + + /* Set media interface */ + s_geths[i]->enet_dev->media_interface = s_geths[i]->inf; + + /* Set refclk */ + s_geths[i]->enet_dev->int_refclk = s_geths[i]->int_refclk; + + /* Set TX delay */ + s_geths[i]->enet_dev->tx_delay = s_geths[i]->tx_delay; + + /* Set RX delay */ + s_geths[i]->enet_dev->rx_delay = s_geths[i]->rx_delay; + + /* Set PTP function */ + s_geths[i]->enet_dev->ptp_enable = s_geths[i]->ptp_enable; + s_geths[i]->enet_dev->ptp_clk_src = s_geths[i]->ptp_clk_src; + s_geths[i]->enet_dev->ptp_config = *s_geths[i]->ptp_config; + s_geths[i]->enet_dev->ptp_timestamp = *s_geths[i]->ptp_timestamp; + + /* Set the interrupt enable mask */ + s_geths[i]->enet_dev->mask = ENET_DMA_INTR_EN_NIE_SET(1) /* Enable normal interrupt summary */ + | ENET_DMA_INTR_EN_RIE_SET(1); /* Enable receive interrupt */ + + /* Set the interrupt disable mask */ + s_geths[i]->enet_dev->dis_mask = ENET_INTR_MASK_RGSMIIIM_SET(1); + + /* Set the irq number */ + s_geths[i]->enet_dev->irq_number = s_geths[i]->irq_num; + + /* Set the parent parameters */ + + s_geths[i]->eth_dev->parent.init = rt_hpm_eth_init; + s_geths[i]->eth_dev->parent.open = rt_hpm_eth_open; + s_geths[i]->eth_dev->parent.close = rt_hpm_eth_close; + s_geths[i]->eth_dev->parent.read = rt_hpm_eth_read; + s_geths[i]->eth_dev->parent.write = rt_hpm_eth_write; + s_geths[i]->eth_dev->parent.control = rt_hpm_eth_control; + + s_geths[i]->eth_dev->parent.user_data = s_geths[i]->enet_dev; + + s_geths[i]->eth_dev->eth_rx = rt_hpm_eth_rx; + s_geths[i]->eth_dev->eth_tx = rt_hpm_eth_tx; + + err = eth_device_init(s_geths[i]->eth_dev, s_geths[i]->name); + + if (RT_EOK == err) + { + LOG_D("Ethernet device initialize successfully!\n"); + } + else + { + LOG_D("Ethernet device initialize unsuccessfully!\n"); + return err; + } + } + + return err; + +} +INIT_DEVICE_EXPORT(rt_hw_eth_init); +#endif /* BSP_USING_ETH */ diff --git a/bsp/hpmicro/libraries/drivers/drv_enet.h b/bsp/hpmicro/libraries/drivers/drv_enet.h new file mode 100644 index 0000000000..4b25be6730 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_enet.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRV_ENET_H +#define DRV_ENET_H + +#include +#include "../../applications/inc/netconf.h" +#include "hpm_enet_drv.h" + +typedef struct { + ENET_Type * instance; + enet_desc_t desc; + enet_mac_config_t mac_config; + uint8_t media_interface; + uint32_t mask; + uint32_t dis_mask; + uint32_t irq_number; + bool int_refclk; + uint8_t tx_delay; + uint8_t rx_delay; + bool ptp_enable; + uint32_t ptp_clk_src; + enet_ptp_config_t ptp_config; + enet_ptp_time_t ptp_timestamp; +} enet_device; + +typedef struct _hpm_enet +{ + const char *name; + ENET_Type *base; + clock_name_t clock_name; + int32_t irq_num; + uint8_t inf; + struct eth_device *eth_dev; + enet_device *enet_dev; + enet_buff_config_t *rx_buff_cfg; + enet_buff_config_t *tx_buff_cfg; + volatile enet_rx_desc_t *dma_rx_desc_tab; + volatile enet_tx_desc_t *dma_tx_desc_tab; + uint8_t tx_delay; + uint8_t rx_delay; + bool int_refclk; + bool ptp_enable; + uint32_t ptp_clk_src; + enet_ptp_config_t *ptp_config; + enet_ptp_time_t *ptp_timestamp; +} hpm_enet_t; + +#ifndef ENET0_TX_BUFF_COUNT +#define ENET0_TX_BUFF_COUNT (10U) +#endif + +#ifndef ENET0_RX_BUFF_COUNT +#define ENET0_RX_BUFF_COUNT (20U) +#endif + +#ifndef ENET0_RX_BUFF_SIZE +#define ENET0_RX_BUFF_SIZE ENET_MAX_FRAME_SIZE +#endif + +#ifndef ENET0_TX_BUFF_SIZE +#define ENET0_TX_BUFF_SIZE ENET_MAX_FRAME_SIZE +#endif + +#ifndef ENET1_TX_BUFF_COUNT +#define ENET1_TX_BUFF_COUNT (10U) +#endif + +#ifndef ENET1_RX_BUFF_COUNT +#define ENET1_RX_BUFF_COUNT (20U) +#endif + +#ifndef ENET1_RX_BUFF_SIZE +#define ENET1_RX_BUFF_SIZE ENET_MAX_FRAME_SIZE +#endif + +#ifndef ENET1_TX_BUFF_SIZE +#define ENET1_TX_BUFF_SIZE ENET_MAX_FRAME_SIZE +#endif + +int rt_hw_eth_init(void); + +#endif /* DRV_ENET_H */ + +/* DRV_GPIO_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_gpio.c b/bsp/hpmicro/libraries/drivers/drv_gpio.c new file mode 100644 index 0000000000..520dfa1824 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_gpio.c @@ -0,0 +1,325 @@ +/* + * Copyright (c) 2021 hpm + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-01-11 hpmicro First version + * 2022-07-28 hpmicro Fixed compiling warnings + */ + +#include + +#ifdef BSP_USING_GPIO +#include +#include +#include "board.h" +#include "drv_gpio.h" +#include "hpm_gpio_drv.h" +#include "hpm_gpiom_drv.h" +#include "hpm_clock_drv.h" + +typedef struct +{ + uint32_t gpio_idx; + uint32_t irq_num; +} gpio_irq_map_t; + +static const gpio_irq_map_t hpm_gpio_irq_map[] = { +#ifdef IRQn_GPIO0_A + { GPIO_IE_GPIOA, IRQn_GPIO0_A }, +#endif +#ifdef IRQn_GPIO0_B + { GPIO_IE_GPIOB, IRQn_GPIO0_B }, +#endif +#ifdef IRQn_GPIO0_C + { GPIO_IE_GPIOC, IRQn_GPIO0_C }, +#endif +#ifdef GPIO_IE_GPIOD + { GPIO_IE_GPIOD, IRQn_GPIO0_D }, +#endif +#ifdef IRQn_GPIO0_E + { GPIO_IE_GPIOE, IRQn_GPIO0_E }, +#endif +#ifdef IRQn_GPIO0_F + { GPIO_IE_GPIOF, IRQn_GPIO0_F }, +#endif +#ifdef IRQn_GPIO0_X + { GPIO_IE_GPIOX, IRQn_GPIO0_X }, +#endif +#ifdef IRQn_GPIO0_Y + { GPIO_IE_GPIOY, IRQn_GPIO0_Y }, +#endif +#ifdef IRQn_GPIO0_Z + { GPIO_IE_GPIOZ, IRQn_GPIO0_Z }, +#endif + }; + +static struct rt_pin_irq_hdr hpm_gpio_pin_hdr_tbl[IOC_PAD_PZ11]; + +static int hpm_get_gpi_irq_num(uint32_t gpio_idx) +{ + int irq_num = -1; + + for (uint32_t i = 0; i < sizeof(hpm_gpio_irq_map) / sizeof(hpm_gpio_irq_map[0]); i++) + { + if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx) + { + irq_num = hpm_gpio_irq_map[i].irq_num; + break; + } + } + return irq_num; +} + +static void hpm_gpio_isr(uint32_t gpio_index, GPIO_Type *base) +{ + uint32_t pin_idx = 0; + for(pin_idx = 0; pin_idx < 32; pin_idx++) + { + if (gpio_check_pin_interrupt_flag(base, gpio_index, pin_idx)) + { + uint32_t pin = gpio_index * 32U + pin_idx; + gpio_clear_pin_interrupt_flag(base, gpio_index, pin_idx); + if (hpm_gpio_pin_hdr_tbl[pin].hdr != RT_NULL) + { + hpm_gpio_pin_hdr_tbl[pin].hdr(hpm_gpio_pin_hdr_tbl[pin].args); + } + } + } +} + +#ifdef GPIO_IF_GPIOA +void gpioa_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOA, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_A, gpioa_isr) +#endif + +#ifdef GPIO_IF_GPIOB +void gpiob_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOB, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_B, gpiob_isr) +#endif + +#ifdef GPIO_IF_GPIOC +void gpioc_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOC, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_C, gpioc_isr) +#endif + +#ifdef GPIO_IF_GPIOD +void gpiod_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOD, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_D, gpiod_isr) +#endif + +#ifdef GPIO_IF_GPIOE +void gpioe_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOE, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_E, gpioe_isr) +#endif + +#ifdef GPIO_IF_GPIOF +void gpiof_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOF, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_F, gpiof_isr) +#endif + +#ifdef GPIO_IF_GPIOX +void gpiox_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOX, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_X, gpiox_isr) +#endif + +#ifdef GPIO_IF_GPIOY +void gpioy_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOY, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Y, gpioy_isr) +#endif + +#ifdef GPIO_IF_GPIOZ +void gpioz_isr(void) +{ + hpm_gpio_isr(GPIO_IF_GPIOZ, HPM_GPIO0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Z, gpioz_isr) +#endif + + +static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + /* TODO: Check the validity of the pin value */ + uint32_t gpio_idx = pin >> 5; + uint32_t pin_idx = pin & 0x1FU; + + gpiom_set_pin_controller(HPM_GPIOM, gpio_idx, pin_idx, gpiom_soc_gpio0); + + HPM_IOC->PAD[pin].FUNC_CTL = 0; + + switch (gpio_idx) + { + case GPIO_DI_GPIOY : + HPM_PIOC->PAD[pin].FUNC_CTL = 3; + break; + case GPIO_DI_GPIOZ : + HPM_BIOC->PAD[pin].FUNC_CTL = 3; + break; + default : + break; + } + + switch (mode) + { + case PIN_MODE_OUTPUT: + gpio_set_pin_output(HPM_GPIO0, gpio_idx, pin_idx); + HPM_IOC->PAD[pin].PAD_CTL &= ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK | IOC_PAD_PAD_CTL_OD_MASK); + break; + case PIN_MODE_INPUT: + gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx); + HPM_IOC->PAD[pin].PAD_CTL &= ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK); + break; + case PIN_MODE_INPUT_PULLDOWN: + gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx); + HPM_IOC->PAD[pin].PAD_CTL = (HPM_IOC->PAD[pin].PAD_CTL & ~IOC_PAD_PAD_CTL_PS_MASK) | IOC_PAD_PAD_CTL_PE_SET(1); + break; + case PIN_MODE_INPUT_PULLUP: + gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx); + HPM_IOC->PAD[pin].PAD_CTL |= IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + break; + case PIN_MODE_OUTPUT_OD: + gpio_set_pin_output(HPM_GPIO0, gpio_idx, pin_idx); + HPM_IOC->PAD[pin].PAD_CTL = (HPM_IOC->PAD[pin].PAD_CTL & ~(IOC_PAD_PAD_CTL_PS_MASK | IOC_PAD_PAD_CTL_PE_MASK)) | IOC_PAD_PAD_CTL_OD_SET(1); + break; + default: + /* Invalid mode */ + break; + } +} + +static int hpm_pin_read(rt_device_t dev, rt_base_t pin) +{ + /* TODO: Check the validity of the pin value */ + uint32_t gpio_idx = pin >> 5; + uint32_t pin_idx = pin & 0x1FU; + + return (int) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx); +} + +static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + /* TODO: Check the validity of the pin value */ + uint32_t gpio_idx = pin >> 5; + uint32_t pin_idx = pin & 0x1FU; + + gpio_write_pin(HPM_GPIO0, gpio_idx, pin_idx, value); +} + +static rt_err_t hpm_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, + void (*hdr)(void *args), void *args) +{ + + rt_base_t level; + level = rt_hw_interrupt_disable(); + hpm_gpio_pin_hdr_tbl[pin].pin = pin; + hpm_gpio_pin_hdr_tbl[pin].hdr = hdr; + hpm_gpio_pin_hdr_tbl[pin].mode = mode; + hpm_gpio_pin_hdr_tbl[pin].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hpm_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + level = rt_hw_interrupt_disable(); + hpm_gpio_pin_hdr_tbl[pin].pin = -1; + hpm_gpio_pin_hdr_tbl[pin].hdr = RT_NULL; + hpm_gpio_pin_hdr_tbl[pin].mode = 0; + hpm_gpio_pin_hdr_tbl[pin].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + /* TODO: Check the validity of the pin value */ + uint32_t gpio_idx = pin >> 5; + uint32_t pin_idx = pin & 0x1FU; + + gpio_interrupt_trigger_t trigger; + if (enabled == PIN_IRQ_ENABLE) + { + switch(hpm_gpio_pin_hdr_tbl[pin].mode) + { + case PIN_IRQ_MODE_RISING: + trigger = gpio_interrupt_trigger_edge_rising; + break; + case PIN_IRQ_MODE_FALLING: + trigger = gpio_interrupt_trigger_edge_falling; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + trigger = gpio_interrupt_trigger_level_high; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + trigger = gpio_interrupt_trigger_level_low; + break; + default: + trigger = gpio_interrupt_trigger_edge_rising; + break; + } + gpio_config_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx, trigger); + uint32_t irq_num = hpm_get_gpi_irq_num(gpio_idx); + gpio_enable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx); + intc_m_enable_irq_with_priority(irq_num, 1); + } + else if (enabled == PIN_IRQ_DISABLE) + { + gpio_disable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx); + } + else + { + return RT_EINVAL; + } + + return RT_EOK; +} + +const static struct rt_pin_ops hpm_pin_ops = { + .pin_mode = hpm_pin_mode, + .pin_write = hpm_pin_write, + .pin_read = hpm_pin_read, + .pin_attach_irq = hpm_pin_attach_irq, + .pin_detach_irq = hpm_pin_detach_irq, + .pin_irq_enable = hpm_pin_irq_enable}; + +int rt_hw_pin_init(void) +{ + int ret = RT_EOK; + + ret = rt_device_pin_register("pin", &hpm_pin_ops, RT_NULL); + + return ret; +} + +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* BSP_USING_GPIO */ diff --git a/bsp/hpmicro/libraries/drivers/drv_gpio.h b/bsp/hpmicro/libraries/drivers/drv_gpio.h new file mode 100644 index 0000000000..87778370b5 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_gpio.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-01-11 HPMICRO First version + * 2022-03-22 zhangjun add GET_PIN + */ +#ifndef DRV_GPIO_H +#define DRV_GPIO_H + +#define __HPM_PORT(port) IOC_PAD_P##port##00 +#define GET_PIN(PORTx,PIN) (__HPM_PORT(PORTx) + PIN) + +int rt_hw_pin_init(void); + + +#endif /* DRV_GPIO_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_hwtimer.c b/bsp/hpmicro/libraries/drivers/drv_hwtimer.c new file mode 100644 index 0000000000..b03abdd557 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_hwtimer.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include +#ifdef RT_USING_HWTIMER + +#include "drv_hwtimer.h" +#include "board.h" +#include "hpm_gptmr_drv.h" + +typedef struct _hpm_gptimer +{ + GPTMR_Type *base; + const char *name; + rt_hwtimer_t timer; + uint32_t channel; + clock_name_t clock_name; + int32_t irq_num; +} hpm_gptimer_t; + +static void hpm_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state); +static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode); +static void hpm_hwtimer_stop(rt_hwtimer_t *timer); +static rt_uint32_t hpm_hwtimer_count_get(rt_hwtimer_t *timer); +static rt_err_t hpm_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); + +static void hpm_hwtmr_isr(hpm_gptimer_t *gptmr); + +static const struct rt_hwtimer_ops hpm_hwtimer_ops = { + .init = hpm_hwtimer_init, + .start = hpm_hwtimer_start, + .stop = hpm_hwtimer_stop, + .count_get = hpm_hwtimer_count_get, + .control = hpm_hwtimer_control +}; + +static const struct rt_hwtimer_info hpm_hwtimer_info = { + .maxfreq = 100000000UL, + .minfreq = 93750UL, + .maxcnt = 0xFFFFFFFFUL, + .cntmode = HWTIMER_CNTMODE_UP +}; + + +#ifdef BSP_USING_GPTMR0 +static hpm_gptimer_t timer0 = {.name = "GPT0", .base = HPM_GPTMR0, .clock_name = clock_gptmr0, .irq_num = IRQn_GPTMR0 }; +#endif +#ifdef BSP_USING_GPTMR1 +static hpm_gptimer_t timer1 = {.name = "GPT1", .base = HPM_GPTMR1, .clock_name = clock_gptmr1, .irq_num = IRQn_GPTMR1 }; +#endif +#ifdef BSP_USING_GPTMR2 +static hpm_gptimer_t timer2 = {.name = "GPT2", .base = HPM_GPTMR2, .clock_name = clock_gptmr2, .irq_num = IRQn_GPTMR2 }; +#endif +#ifdef BSP_USING_GPTMR3 +static hpm_gptimer_t timer3 = {.name = "GPT3", .base = HPM_GPTMR3, .clock_name = clock_gptmr3, .irq_num = IRQn_GPTMR3 }; +#endif +#ifdef BSP_USING_GPTMR4 +static hpm_gptimer_t timer4 = {.name = "GPT4", .base = HPM_GPTMR4, .clock_name = clock_gptmr4, .irq_num = IRQn_GPTMR4 }; +#endif +#ifdef BSP_USING_GPTMR5 +static hpm_gptimer_t timer5 = {.name = "GPT5", .base = HPM_GPTMR5, .clock_name = clock_gptmr5, .irq_num = IRQn_GPTMR5 }; +#endif +#ifdef BSP_USING_GPTMR6 +static hpm_gptimer_t timer6 = {.name = "GPT6", .base = HPM_GPTMR6, .clock_name = clock_gptmr6, .irq_num = IRQn_GPTMR6 }; +#endif +#ifdef BSP_USING_GPTMR7 +static hpm_gptimer_t timer7 = {.name = "GPT7", .base = HPM_GPTMR7, .clock_name = clock_gptmr7, .irq_num = IRQn_GPTMR7 }; +#endif + + +static hpm_gptimer_t *s_gptimers[] = { +#ifdef BSP_USING_GPTMR0 + &timer0, +#endif +#ifdef BSP_USING_GPTMR1 + &timer1, +#endif +#ifdef BSP_USING_GPTMR2 + &timer2, +#endif +#ifdef BSP_USING_GPTMR3 + &timer3, +#endif +#ifdef BSP_USING_GPTMR4 + &timer4, +#endif +#ifdef BSP_USING_GPTMR5 + &timer5, +#endif +#ifdef BSP_USING_GPTMR6 + &timer6, +#endif +#ifdef BSP_USING_GPTMR7 + &timer7, +#endif + }; + +#ifdef BSP_USING_GPTMR0 +void gptmr0_isr(void) +{ + hpm_hwtmr_isr(&timer0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR0, gptmr0_isr); +#endif + +#ifdef BSP_USING_GPTMR1 +void gptmr1_isr(void) +{ + hpm_hwtmr_isr(&timer1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR1, gptmr1_isr); +#endif + +#ifdef BSP_USING_GPTMR2 +void gptmr2_isr(void) +{ + hpm_hwtmr_isr(&timer2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR2, gptmr2_isr); +#endif + +#ifdef BSP_USING_GPTMR3 +void gptmr3_isr(void) +{ + hpm_hwtmr_isr(&timer3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR3, gptmr3_isr); +#endif + +#ifdef BSP_USING_GPTMR4 +void gptmr4_isr(void) +{ + hpm_hwtmr_isr(&timer4); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR4, gptmr4_isr); +#endif + +#ifdef BSP_USING_GPTMR5 +void gptmr5_isr(void) +{ + hpm_hwtmr_isr(&timer5); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR5, gptmr5_isr); +#endif + +#ifdef BSP_USING_GPTMR6 +void gptmr6_isr(void) +{ + hpm_hwtmr_isr(&timer6); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR6, gptmr6_isr); +#endif + +#ifdef BSP_USING_GPTMR7 +void gptmr7_isr(void) +{ + hpm_hwtmr_isr(&timer7); +} +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR7, gptmr7_isr); +#endif + +static void hpm_hwtmr_isr(hpm_gptimer_t *timer) +{ + uint32_t hwtmr_stat = gptmr_get_status(timer->base); + if ((hwtmr_stat & GPTMR_CH_CMP_STAT_MASK(0, 0)) != 0U) + { + rt_device_hwtimer_isr(&timer->timer); + gptmr_clear_status(timer->base, GPTMR_CH_CMP_STAT_MASK(0, 0)); + } +} + +static void hpm_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*)timer->parent.user_data; + GPTMR_Type *base = hpm_gptmr->base; + gptmr_channel_config_t config; + + if (state == 1) + { + hpm_gptmr->timer.freq = board_init_gptmr_clock(base); + gptmr_channel_get_default_config(base, &config); + gptmr_channel_config(base, hpm_gptmr->channel, &config, false); + } +} + +static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +{ + hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*) timer->parent.user_data; + GPTMR_Type *base = hpm_gptmr->base; + + gptmr_channel_config_t config; + gptmr_channel_get_default_config(base, &config); + config.cmp[0] = cnt; + config.reload = cnt; + + timer->mode = mode; + + gptmr_channel_config(base, hpm_gptmr->channel, &config, true); + + gptmr_clear_status(base, 0xFU); + gptmr_enable_irq(base, GPTMR_CH_CMP_IRQ_MASK(0, 0)); + + gptmr_channel_update_count(base, hpm_gptmr->channel, 0); + gptmr_start_counter(base, hpm_gptmr->channel); + + intc_m_enable_irq_with_priority(hpm_gptmr->irq_num, 1); + + return RT_EOK; +} + +static void hpm_hwtimer_stop(rt_hwtimer_t *timer) +{ + hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*)timer->parent.user_data; + GPTMR_Type *base = hpm_gptmr->base; + + gptmr_stop_counter(base, hpm_gptmr->channel); +} + +static rt_uint32_t hpm_hwtimer_count_get(rt_hwtimer_t *timer) +{ + hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*)timer->parent.user_data; + GPTMR_Type *base = hpm_gptmr->base; + + rt_uint32_t current_cnt = gptmr_channel_get_counter(base, hpm_gptmr->channel, gptmr_counter_type_normal); + + return current_cnt; +} + +static rt_err_t hpm_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +{ + rt_err_t err = RT_EOK; + hpm_gptimer_t *hpm_gptmr = (hpm_gptimer_t*) timer->parent.user_data; + GPTMR_Type *base = hpm_gptmr->base; + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + err = -RT_ERROR; + break; + case HWTIMER_CTRL_INFO_GET: + *(rt_hwtimer_t*)args = hpm_gptmr->timer; + break; + case HWTIMER_CTRL_MODE_SET: + hpm_gptmr->timer.mode = *(rt_uint32_t*)args; + break; + case HWTIMER_CTRL_STOP: + gptmr_stop_counter(base, hpm_gptmr->channel); + break; + } + + return err; +} + + +int rt_hw_hwtimer_init(void) +{ + int ret = RT_EOK; + + for (uint32_t i = 0; i < ARRAY_SIZE(s_gptimers); i++) + { + s_gptimers[i]->timer.info = &hpm_hwtimer_info; + s_gptimers[i]->timer.ops = &hpm_hwtimer_ops; + ret = rt_device_hwtimer_register(&s_gptimers[i]->timer, s_gptimers[i]->name, s_gptimers[i]); + if (ret != RT_EOK) + { + LOG_E("%s register failed\n", s_gptimers[i]->name); + } + } + + return ret; +} + +#endif /* BSP_USING_GPTMR */ diff --git a/bsp/hpmicro/libraries/drivers/drv_hwtimer.h b/bsp/hpmicro/libraries/drivers/drv_hwtimer.h new file mode 100644 index 0000000000..e04e22ef88 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_hwtimer.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRV_HWTIMER_H +#define DRV_HWTIMER_H + + +int rt_hw_hwtimer_init(void); + +#endif /* DRV_HWTIMER_H */ diff --git a/bsp/hpmicro/libraries/drivers/drv_i2c.c b/bsp/hpmicro/libraries/drivers/drv_i2c.c new file mode 100644 index 0000000000..4d83707262 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_i2c.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include +#ifdef BSP_USING_I2C +#include "drv_i2c.h" +#include "hpm_i2c_drv.h" +#include "board.h" + +#ifdef RT_USING_I2C + +struct hpm_i2c +{ + struct rt_i2c_bus_device bus; + I2C_Type *base; + clock_name_t clk_name; + char *bus_name; +}; + +static struct hpm_i2c hpm_i2cs[] = +{ +#if defined(BSP_USING_I2C0) + { + .base = HPM_I2C0, + .bus_name = "i2c0", + .clk_name = clock_i2c0, + }, +#endif +#if defined(BSP_USING_I2C1) + { + .base = HPM_I2C1, + .bus_name = "i2c1", + .clk_name = clock_i2c1, + }, +#endif +#if defined(BSP_USING_I2C2) + { + .base = HPM_I2C1, + .bus_name = "i2c1", + .clk_name = clock_i2c1, + }, +#endif +#if defined(BSP_USING_I2C3) + { + .base = HPM_I2C1, + .bus_name = "i2c1", + .clk_name = clock_i2c1, + }, +#endif +}; + +static rt_size_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num); + + +struct rt_i2c_bus_device_ops hpm_i2c_ops = +{ + hpm_i2c_master_transfer, + RT_NULL, + RT_NULL +}; + +static rt_size_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) +{ + RT_ASSERT(bus != RT_NULL); + RT_ASSERT(msgs != RT_NULL); + + struct rt_i2c_msg *msg; + struct hpm_i2c *i2c_info = (struct hpm_i2c *)bus; + + hpm_stat_t i2c_stat = status_success; + rt_err_t ret = RT_ERROR; + rt_uint32_t i; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_ADDR_10BIT) + { + i2c_enable_10bit_address_mode(i2c_info->base, true); + } + else + { + i2c_enable_10bit_address_mode(i2c_info->base, false); + } + + if (msg->flags & RT_I2C_RD) + { + i2c_stat = i2c_master_read(i2c_info->base, msg->addr, msg->buf, msg->len); + } + else + { + i2c_stat = i2c_master_write(i2c_info->base, msg->addr, msg->buf, msg->len); + } + + if (i2c_stat != status_success) + { + break; + } + } + + if (i2c_stat != status_success) + { + return ret; + } + + ret = i; + return ret; +} + + +int rt_hw_i2c_init(void) +{ + rt_err_t ret = RT_EOK; + hpm_stat_t stat; + i2c_config_t config; + rt_uint32_t freq; + + for (uint32_t i = 0; i < sizeof(hpm_i2cs) / sizeof(hpm_i2cs[0]); i++) { + init_i2c_pins(hpm_i2cs[i].base); + clock_add_to_group(hpm_i2cs[i].clk_name, 0); + clock_set_source_divider(hpm_i2cs[i].clk_name, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(hpm_i2cs[i].clk_name); + stat = i2c_init_master(hpm_i2cs[i].base, freq, &config); + if (stat != status_success) { + LOG_E("rt i2c device %s init failed", hpm_i2cs[i].bus_name); + } + + hpm_i2cs[i].bus.ops = &hpm_i2c_ops; + ret = rt_i2c_bus_device_register(&hpm_i2cs[i].bus, hpm_i2cs[i].bus_name); + if (ret != RT_EOK) { + LOG_E("rt i2c device %s register failed, status=%d\n", hpm_i2cs[i].bus_name, ret); + } + } + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif /* RT_USING_I2C */ + +#endif /*BSP_USING_I2C*/ + diff --git a/bsp/hpmicro/libraries/drivers/drv_i2c.h b/bsp/hpmicro/libraries/drivers/drv_i2c.h new file mode 100644 index 0000000000..4072da82c7 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_i2c.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRV_I2C_H +#define DRV_I2C_H + +int rt_hw_i2c_init(void); + +#endif /* DRV_I2C_H */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_i2s.c b/bsp/hpmicro/libraries/drivers/drv_i2s.c new file mode 100644 index 0000000000..5312ee0a10 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_i2s.c @@ -0,0 +1,584 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include + +#define DBG_TAG "i2s" +#define DBG_LVL DBG_INFO +#include + +#ifdef BSP_USING_I2S +#include "hpm_i2s_drv.h" +#include "board.h" +#include "hpm_dma_drv.h" +#include "hpm_dmamux_drv.h" +#include "hpm_l1c_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_dma_manager.h" + +#include "drv_i2s.h" +#include "drivers/audio.h" + +static rt_size_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* writeBuf, void* readBuf, rt_size_t size); + +struct hpm_i2s +{ + struct rt_audio_device audio; + struct rt_audio_configure audio_config; + hpm_dma_resource_t rx_dma_resource; + hpm_dma_resource_t tx_dma_resource; + char *dev_name; + I2S_Type *base; + clock_name_t clk_name; + i2s_transfer_config_t transfer; + uint8_t rx_dma_req; + uint8_t tx_dma_req; + rt_uint8_t* tx_buff; + rt_uint8_t* rx_buff; +}; + +#if defined(BSP_USING_I2S0) +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s0_tx_buff[I2S_FIFO_SIZE]; +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s0_rx_buff[I2S_FIFO_SIZE]; +#endif +#if defined(BSP_USING_I2S1) +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s1_tx_buff[I2S_FIFO_SIZE]; +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s1_rx_buff[I2S_FIFO_SIZE]; +#endif +#if defined(BSP_USING_I2S2) +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s2_tx_buff[I2S_FIFO_SIZE]; +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s2_rx_buff[I2S_FIFO_SIZE]; +#endif +#if defined(BSP_USING_I2S3) +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s3_tx_buff[I2S_FIFO_SIZE]; +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s3_rx_buff[I2S_FIFO_SIZE]; +#endif + +static struct hpm_i2s hpm_i2s_set[] = +{ +#if defined(BSP_USING_I2S0) + { + .dev_name = "i2s0", + .base = HPM_I2S0, + .clk_name = clock_i2s0, + .rx_dma_req = HPM_DMA_SRC_I2S0_RX, + .tx_dma_req = HPM_DMA_SRC_I2S0_TX, + .tx_buff = i2s0_tx_buff, + .rx_buff = i2s0_rx_buff, + }, +#endif +#if defined(BSP_USING_I2S1) + { + .dev_name = "i2s1", + .base = HPM_I2S1; + .clk_name = clock_i2s1, + .rx_dma_req = HPM_DMA_SRC_I2S1_RX, + .tx_dma_req = HPM_DMA_SRC_I2S1_TX, + .tx_buff = i2s1_tx_buff, + .rx_buff = i2s1_rx_buff, + }, +#endif +#if defined(BSP_USING_I2S2) + { + .dev_name = "i2s2", + .base = HPM_I2S2, + .clk_name = clock_i2s2, + .rx_dma_req = HPM_DMA_SRC_I2S2_RX, + .tx_dma_req = HPM_DMA_SRC_I2S2_TX, + .tx_buff = i2s2_tx_buff, + .rx_buff = i2s2_rx_buff, + }, +#endif +#if defined(BSP_USING_I2S3) + { + .dev_name = "i2s3", + .base = HPM_I2S3, + .clk_name = clock_i2s3, + .rx_dma_req = HPM_DMA_SRC_I2S3_RX, + .tx_dma_req = HPM_DMA_SRC_I2S3_TX, + .tx_buff = i2s3_tx_buff, + .rx_buff = i2s3_rx_buff, + }, +#endif +}; + +/* I2S TX DMA callback function: trigger next transfer */ +void i2s_tx_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +{ + if (int_stat == DMA_CHANNEL_STATUS_TC) { + struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; + rt_audio_tx_complete(&hpm_audio->audio); + } +} + +/* I2S RX DMA callback function: write data into record->pipe and trigger next transfer */ +void i2s_rx_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +{ + if (int_stat == DMA_CHANNEL_STATUS_TC) { + struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; + rt_audio_rx_done(&hpm_audio->audio, hpm_audio->rx_buff, I2S_FIFO_SIZE); + hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE); + } +} + + +static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) +{ + RT_ASSERT(audio != RT_NULL); + rt_uint32_t mclk_hz; + i2s_config_t i2s_config; + i2s_transfer_config_t transfer; + + struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; + + init_i2s_pins(hpm_audio->base); + board_init_i2s_clock(hpm_audio->base); + + //使用DMA传输 + i2s_enable_rx_dma_request(hpm_audio->base); + i2s_enable_tx_dma_request(hpm_audio->base); + + i2s_get_default_config(hpm_audio->base, &i2s_config); + i2s_config.enable_mclk_out = true; + i2s_config.frame_start_at_rising_edge = true; //左对齐与右对齐方式， 对应上升沿 + i2s_init(hpm_audio->base, &i2s_config); + + mclk_hz = clock_get_frequency(hpm_audio->clk_name); + i2s_get_default_transfer_config(&transfer); + /* 初始化I2S配置, 应用使用configure ops修改属性 */ + transfer.sample_rate = 24000U; + transfer.protocol = I2S_PROTOCOL_LEFT_JUSTIFIED; + transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); /* 1个通道 */ + transfer.audio_depth = I2S_AUDIO_DEPTH_16_BITS; + transfer.master_mode = true; + hpm_audio->transfer = transfer; + //将初始参数记录到audio_config + hpm_audio->audio_config.samplerate = 24000U; + hpm_audio->audio_config.samplebits = 16; + hpm_audio->audio_config.channels = 1; + if (status_success != i2s_config_transfer(hpm_audio->base, mclk_hz, &transfer)) + { + LOG_E("dao_i2s configure transfer failed\n"); + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_i2s_getcaps(struct rt_audio_device* audio, struct rt_audio_caps* caps) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(audio != RT_NULL); + struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; + + switch(caps->main_type) + { + case AUDIO_TYPE_INPUT: + { + switch(caps->sub_type) + { + case AUDIO_DSP_PARAM: + { + caps->udata.config.channels = hpm_audio->audio_config.channels; + caps->udata.config.samplebits = hpm_audio->audio_config.samplebits; + caps->udata.config.samplerate = hpm_audio->audio_config.samplerate; + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + caps->udata.config.samplerate = hpm_audio->audio_config.samplerate; + break; + } + + case AUDIO_DSP_CHANNELS: + { + caps->udata.config.channels = hpm_audio->audio_config.channels; + break; + } + + case AUDIO_DSP_SAMPLEBITS: + { + caps->udata.config.samplebits = hpm_audio->audio_config.samplebits; + break; + } + + case AUDIO_PARM_I2S_DATA_LINE: + { + caps->udata.value = hpm_audio->transfer.data_line; + break; + } + + default: + { + result = -RT_ERROR; + break; + } + } + break; + } + case AUDIO_TYPE_OUTPUT: + { + switch(caps->sub_type) + { + case AUDIO_DSP_PARAM: + { + caps->udata.config.samplerate = hpm_audio->audio_config.samplerate; + caps->udata.config.channels = hpm_audio->audio_config.channels; + caps->udata.config.samplebits = hpm_audio->audio_config.samplebits; + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + caps->udata.config.samplerate = hpm_audio->audio_config.samplerate; + break; + } + + case AUDIO_DSP_CHANNELS: + { + caps->udata.config.channels = hpm_audio->audio_config.channels; + break; + } + + case AUDIO_DSP_SAMPLEBITS: + { + caps->udata.config.samplebits = hpm_audio->audio_config.samplebits; + break; + } + + case AUDIO_PARM_I2S_DATA_LINE: + { + caps->udata.value = hpm_audio->transfer.data_line; + break; + } + + default: + { + result = -RT_ERROR; + break; + } + } + + break; + } + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio_caps* caps) +{ + + rt_err_t result = RT_EOK; + RT_ASSERT(audio != RT_NULL); + struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; + + switch(caps->main_type) + { + case AUDIO_TYPE_OUTPUT: + { + switch(caps->sub_type) + { + case AUDIO_DSP_PARAM: + { + hpm_audio->audio_config.samplerate = caps->udata.config.samplerate; + hpm_audio->audio_config.samplebits = caps->udata.config.samplebits; + hpm_audio->audio_config.channels = caps->udata.config.channels; + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + hpm_audio->audio_config.samplerate = caps->udata.config.samplerate; + break; + } + + case AUDIO_DSP_CHANNELS: + { + hpm_audio->audio_config.channels = caps->udata.config.channels; + break; + } + + case AUDIO_DSP_SAMPLEBITS: + { + hpm_audio->audio_config.samplebits = caps->udata.config.samplebits; + break; + } + + case AUDIO_PARM_I2S_DATA_LINE: + { + hpm_audio->transfer.data_line = caps->udata.value; + break; + } + + default: + result = -RT_ERROR; + break; + } + break; + } + case AUDIO_TYPE_INPUT: + { + switch(caps->sub_type) + { + + case AUDIO_DSP_PARAM: + { + hpm_audio->audio_config.samplerate = caps->udata.config.samplerate; + hpm_audio->audio_config.channels = caps->udata.config.channels; + hpm_audio->audio_config.samplebits = caps->udata.config.samplebits; + break; + } + + case AUDIO_DSP_SAMPLERATE: + { + hpm_audio->audio_config.samplerate = caps->udata.config.samplerate; + break; + } + case AUDIO_DSP_CHANNELS: + { + hpm_audio->audio_config.channels = caps->udata.config.channels; + break; + } + + case AUDIO_DSP_SAMPLEBITS: + { + hpm_audio->audio_config.samplebits = caps->udata.config.samplebits; + break; + } + + case AUDIO_PARM_I2S_DATA_LINE: + { + hpm_audio->transfer.data_line = caps->udata.value; + break; + } + + default: + result = -RT_ERROR; + break; + } + break; + } + + default: + break; + } + + /* 设置 I2S transfer */ + if (hpm_audio->audio_config.channels == i2s_mono_left) { + hpm_audio->transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); + } else if (hpm_audio->audio_config.channels == i2s_mono_right) { + hpm_audio->transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(1); + } else if(hpm_audio->audio_config.channels == 2) { + hpm_audio->transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0) | I2S_CHANNEL_SLOT_MASK(1); + } else { + LOG_E("I2S not support channels number %d.\n", hpm_audio->audio_config.channels); + return -RT_ERROR; + } + + hpm_audio->transfer.sample_rate = hpm_audio->audio_config.samplerate; + + //i2s dma方式仅支持采样位宽为：16bit, 32bit + assert(hpm_audio->audio_config.samplebits == 16 || hpm_audio->audio_config.samplebits == 32); + hpm_audio->transfer.audio_depth = (hpm_audio->audio_config.samplebits - 16) >> 3; + + if (status_success != i2s_config_transfer(hpm_audio->base, clock_get_frequency(hpm_audio->clk_name), &hpm_audio->transfer)) + { + LOG_E("%s configure transfer failed.\n", hpm_audio->dev_name); + } + return result; +} + +static rt_err_t hpm_i2s_start(struct rt_audio_device* audio, int stream) +{ + RT_ASSERT(audio != RT_NULL); + + struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; + + /* 申请DMA resource用于I2S transfer */ + if (stream == AUDIO_STREAM_REPLAY) { + hpm_dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; + if (dma_manager_request_resource(dma_resource) == status_success) { + uint8_t dmamux_ch; + dma_manager_install_interrupt_callback(dma_resource, i2s_tx_dma_callback, hpm_audio); + dma_manager_enable_dma_interrupt(dma_resource, 1); + dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource->base, dma_resource->channel); + dmamux_config(HPM_DMAMUX, dmamux_ch, hpm_audio->tx_dma_req, true); + } else { + LOG_E("no dma resource available for I2S TX transfer.\n"); + return -RT_ERROR; + } + rt_audio_tx_complete(audio); + } else if (stream == AUDIO_STREAM_RECORD) { + hpm_dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; + if (dma_manager_request_resource(dma_resource) == status_success) { + uint8_t dmamux_ch; + dma_manager_install_interrupt_callback(dma_resource, i2s_rx_dma_callback, hpm_audio); + dma_manager_enable_dma_interrupt(dma_resource, 1); + dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource->base, dma_resource->channel); + dmamux_config(HPM_DMAMUX, dmamux_ch, hpm_audio->rx_dma_req, true); + } else { + LOG_E("no dma resource available for I2S RX transfer.\n"); + return -RT_ERROR; + } + + if (RT_EOK != hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE)) { + return RT_ERROR; + } + } else { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_i2s_stop(struct rt_audio_device* audio, int stream) +{ + RT_ASSERT(audio != RT_NULL); + struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; + + if (stream == AUDIO_STREAM_REPLAY) { + hpm_dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; + dma_manager_release_resource(dma_resource); + } else if (stream == AUDIO_STREAM_RECORD) + { + hpm_dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; + dma_manager_release_resource(dma_resource); + } else { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_size_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* writeBuf, void* readBuf, rt_size_t size) +{ + RT_ASSERT(audio != RT_NULL); + struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; + + //支持采样位宽16bit, 32bit + uint8_t data_width; + uint8_t data_shift_byte; + if (hpm_audio->transfer.audio_depth == I2S_AUDIO_DEPTH_16_BITS) { + data_width = DMA_TRANSFER_WIDTH_HALF_WORD; + data_shift_byte = 2U ; //16位音频数据位于寄存器的高位 + } else { + data_width = DMA_TRANSFER_WIDTH_WORD; + data_shift_byte = 0U; + } + + if(writeBuf != RT_NULL) + { + hpm_dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; + dma_channel_config_t ch_config = {0}; + dma_default_channel_config(dma_resource->base, &ch_config); + ch_config.src_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)writeBuf); + ch_config.dst_addr = (uint32_t)&hpm_audio->base->TXD[hpm_audio->transfer.data_line] + data_shift_byte; + ch_config.src_width = data_width; + ch_config.dst_width = data_width; + ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + ch_config.size_in_byte = size; + ch_config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + + if (l1c_dc_is_enabled()) { + /* cache writeback for sent buff */ + l1c_dc_writeback((uint32_t)writeBuf, size); + } + + if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config)) { + LOG_E("dma setup channel failed\n"); + return -RT_ERROR; + } + } else if (readBuf != RT_NULL){ + hpm_dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; + dma_channel_config_t ch_config = {0}; + dma_default_channel_config(dma_resource->base, &ch_config); + ch_config.src_addr = (uint32_t)&hpm_audio->base->RXD[hpm_audio->transfer.data_line] + data_shift_byte; + ch_config.dst_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)readBuf); + ch_config.src_width = data_width; + ch_config.dst_width = data_width; + ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch_config.size_in_byte = size; + ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + + if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config)) { + LOG_E("dma setup channel failed\n"); + return -RT_ERROR; + } + + if (l1c_dc_is_enabled()) { + /* cache invalidate for receive buff */ + l1c_dc_invalidate((uint32_t)readBuf, size); + } + } + + return size; +} + +static void hpm_i2s_buffer_info(struct rt_audio_device* audio, struct rt_audio_buf_info* info) +{ + RT_ASSERT(audio != RT_NULL); + struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; + /** + * AUD_FIFO + * +----------------+----------------+ + * | block1 | block2 | + * +----------------+----------------+ + * \ block_size / + */ + info->buffer = hpm_audio->tx_buff; + info->total_size = I2S_FIFO_SIZE; + info->block_size = I2S_FIFO_SIZE / 2; + info->block_count = 2; +} + + +static struct rt_audio_ops hpm_i2s_ops = +{ + .getcaps = hpm_i2s_getcaps, + .configure = hpm_i2s_configure, + .init = hpm_i2s_init, + .start = hpm_i2s_start, + .stop = hpm_i2s_stop, + .transmit = hpm_i2s_transmit, + .buffer_info = hpm_i2s_buffer_info, +}; + +int rt_hw_i2s_init(void) +{ + rt_err_t ret = RT_EOK; + + for (uint32_t i = 0; i < sizeof(hpm_i2s_set) / sizeof(hpm_i2s_set[0]); i++) { + hpm_i2s_set[i].audio.ops = &hpm_i2s_ops; + + ret = rt_audio_register(&hpm_i2s_set[i].audio, hpm_i2s_set[i].dev_name, RT_DEVICE_FLAG_RDWR, &hpm_i2s_set[i]); + + if (ret != RT_EOK) + { + LOG_E("rt audio %s register failed, status=%d\n", hpm_i2s_set[i].dev_name, ret); + } + + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2s_init); + + +#endif /* BSP_USING_I2S */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_i2s.h b/bsp/hpmicro/libraries/drivers/drv_i2s.h new file mode 100644 index 0000000000..ff9a369108 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_i2s.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRV_I2S_H +#define DRV_I2S_H + +#define I2S_FIFO_SIZE (2048) + +//AUDIO CONCTRL的参数定义 +#define AUDIO_PARM_I2S_DATA_LINE 4 + +int rt_hw_i2s_init(void); + +#endif /* DRV_I2S_H */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_pdm.c b/bsp/hpmicro/libraries/drivers/drv_pdm.c new file mode 100644 index 0000000000..7984f28cfb --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_pdm.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include + +#define DBG_TAG "pdm" +#define DBG_LVL DBG_INFO +#include + +#ifdef BSP_USING_PDM +#include "board.h" +#include "drivers/audio.h" +#include "hpm_i2s_drv.h" +#include "hpm_pdm_drv.h" +#include "drv_pdm.h" +#include "hpm_dma_drv.h" +#include "hpm_dmamux_drv.h" +#include "hpm_l1c_drv.h" +#include "hpm_dma_manager.h" + + +/* PDM connect to I2S0 RX */ +#define PDM_DMA_REQ HPM_DMA_SRC_I2S0_RX +#define PDM_I2S_DATA_LINE 0 + +struct hpm_pdm +{ + struct rt_audio_device audio; + struct rt_audio_configure record_config; + rt_uint8_t* rx_fifo; +}; + +struct hpm_pdm hpm_pdm_dev = { 0 }; +static hpm_dma_resource_t dma_resource = { 0 }; +static rt_err_t hpm_pdm_dma_transmit(); + + +void pdm_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +{ + if (int_stat == DMA_CHANNEL_STATUS_TC) { + rt_audio_rx_done(&hpm_pdm_dev.audio, hpm_pdm_dev.rx_fifo, PDM_FIFO_SIZE); + hpm_pdm_dma_transmit(); + } +} + +static rt_err_t hpm_pdm_getcaps(struct rt_audio_device* audio, struct rt_audio_caps* caps) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(audio != RT_NULL); + struct hpm_pdm* hpm_audio = (struct hpm_pdm*)audio->parent.user_data; + + switch(caps->main_type) + { + case AUDIO_TYPE_INPUT: + { + switch(caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.samplerate = hpm_audio->record_config.samplerate; + caps->udata.config.channels = hpm_audio->record_config.channels; + caps->udata.config.samplebits = hpm_audio->record_config.samplebits; + break; + + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = hpm_audio->record_config.samplerate; + break; + + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = hpm_audio->record_config.channels; + break; + + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = hpm_audio->record_config.samplebits; + break; + + default: + result = -RT_ERROR; + break; + } + + break; + } + + default: + result = -RT_ERROR; + break; + } + + return result; +} + +static rt_err_t hpm_pdm_set_channels(uint32_t channel) +{ + uint32_t mclk_hz; + i2s_transfer_config_t transfer; + + mclk_hz = clock_get_frequency(clock_i2s0); + i2s_get_default_transfer_config_for_pdm(&transfer); + transfer.data_line = I2S_DATA_LINE_0; + if (channel == i2s_mono_left) { + transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); + } else if (channel == i2s_mono_right) { + transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(1); + } else if(channel == 2) { + transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0) | I2S_CHANNEL_SLOT_MASK(1); + } else { + LOG_E("PDM not support channels number %d.\n", channel); + return -RT_ERROR; + } + + if (status_success != i2s_config_rx(PDM_I2S, mclk_hz, &transfer)) + { + LOG_E("dao_i2s configure transfer failed\n"); + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_pdm_configure(struct rt_audio_device* audio, struct rt_audio_caps* caps) +{ + + rt_err_t result = RT_EOK; + RT_ASSERT(audio != RT_NULL); + + struct hpm_pdm* hpm_audio = (struct hpm_pdm*)audio->parent.user_data; + + switch(caps->main_type) + { + case AUDIO_TYPE_INPUT: + { + switch(caps->sub_type) + { + case AUDIO_DSP_CHANNELS: + { + hpm_audio->record_config.channels = caps->udata.config.channels; + hpm_pdm_set_channels(caps->udata.config.channels); + break; + } + + default: + result = -RT_ERROR; + break; + } + } + + default: + result = -RT_ERROR; + break; + } + return result; +} + + +static rt_err_t hpm_pdm_init(struct rt_audio_device* audio) +{ + RT_ASSERT(audio != RT_NULL); + + i2s_config_t i2s_config; + i2s_transfer_config_t transfer; + pdm_config_t pdm_config; + + init_pdm_pins(); + board_init_pdm_clock(); + + i2s_get_default_config(PDM_I2S, &i2s_config); + i2s_enable_rx_dma_request(PDM_I2S); + i2s_init(PDM_I2S, &i2s_config); + + i2s_get_default_transfer_config_for_pdm(&transfer); + transfer.data_line = I2S_DATA_LINE_0; + transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); + if (status_success != i2s_config_rx(PDM_I2S, clock_get_frequency(clock_i2s0), &transfer)) + { + LOG_E("pdm_i2s configure receive failed\n"); + return -RT_ERROR; + } + + /* init audio configure */ + hpm_pdm_dev.record_config.channels = 1U; + hpm_pdm_dev.record_config.samplebits = 32U; /* 数据为32位，实际有效位24bit，高位为0 */ + hpm_pdm_dev.record_config.samplerate = PDM_SOC_SAMPLE_RATE_IN_HZ; /* fix 16KHz */ + + pdm_get_default_config(HPM_PDM, &pdm_config); + if (status_success != pdm_init(HPM_PDM, &pdm_config)) { + LOG_E("pdm init failed\n"); + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_pdm_start(struct rt_audio_device* audio, int stream) +{ + RT_ASSERT(audio != RT_NULL); + struct hpm_pdm* hpm_audio = (struct hpm_pdm*)audio->parent.user_data; + + if (stream == AUDIO_STREAM_RECORD) + { + pdm_start(HPM_PDM); + + if (dma_manager_request_resource(&dma_resource) == status_success) { + uint8_t dmamux_ch; + dma_manager_install_interrupt_callback(&dma_resource, pdm_dma_callback, NULL); + dma_manager_enable_dma_interrupt(&dma_resource, 1); + dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource.base, dma_resource.channel); + dmamux_config(HPM_DMAMUX, dmamux_ch, PDM_DMA_REQ, true); + } else { + LOG_E("no dma resource available for PDM transfer.\n"); + return -RT_ERROR; + } + + if (RT_EOK != hpm_pdm_dma_transmit()) { + return RT_ERROR; + } + } + + return RT_EOK; +} + +static rt_err_t hpm_pdm_stop(struct rt_audio_device* audio, int stream) +{ + RT_ASSERT(audio != RT_NULL); + + if (stream == AUDIO_STREAM_RECORD) + { + pdm_stop(HPM_PDM); + } + + dma_manager_release_resource(&dma_resource); + + return RT_EOK; +} + +static rt_err_t hpm_pdm_dma_transmit() +{ + dma_channel_config_t ch_config = {0}; + dma_default_channel_config(dma_resource.base, &ch_config); + ch_config.src_addr = (uint32_t)&PDM_I2S->RXD[PDM_I2S_DATA_LINE]; + ch_config.dst_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)hpm_pdm_dev.rx_fifo); + ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; + ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; + ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch_config.size_in_byte = PDM_FIFO_SIZE; + ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + + if (status_success != dma_setup_channel(dma_resource.base, dma_resource.channel, &ch_config)) { + LOG_E("dma setup channel failed\n"); + return RT_ERROR; + } + + if (l1c_dc_is_enabled()) { + /* cache invalidate for receive buff */ + l1c_dc_invalidate((uint32_t)hpm_pdm_dev.rx_fifo, PDM_FIFO_SIZE); + } + + return RT_EOK; +} + + +static struct rt_audio_ops hpm_pdm_ops = +{ + .getcaps = hpm_pdm_getcaps, + .configure = hpm_pdm_configure, + .init = hpm_pdm_init, + .start = hpm_pdm_start, + .stop = hpm_pdm_stop, + .transmit = NULL, + .buffer_info = NULL, +}; + +ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t pdm_rx_fifo[PDM_FIFO_SIZE]; + +int rt_hw_pdm_init(void) +{ + hpm_pdm_dev.rx_fifo = pdm_rx_fifo; + + hpm_pdm_dev.audio.ops = &hpm_pdm_ops; + + LOG_I("audio pdm registered.\n"); + LOG_I("!!!Note: pdm depends on i2s0, they share clock.\n"); + rt_audio_register(&hpm_pdm_dev.audio, "pdm", RT_DEVICE_FLAG_RDONLY, &hpm_pdm_dev); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_pdm_init); + +#endif /* BSP_USING_PDM */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_pdm.h b/bsp/hpmicro/libraries/drivers/drv_pdm.h new file mode 100644 index 0000000000..5f76402b9f --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_pdm.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRV_PDM_H +#define DRV_PDM_H + +#define PDM_FIFO_SIZE (2048) + +int rt_hw_pdm_init(void); + +#endif /* DRV_PDM_H */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_pwm.c b/bsp/hpmicro/libraries/drivers/drv_pwm.c new file mode 100644 index 0000000000..268a917cc5 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_pwm.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2022 hpm + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-01-11 will First version + */ + +#include + +#ifdef BSP_USING_PWM +#include +#include +#include "board.h" +#include "drv_gpio.h" +#include "hpm_pwm_drv.h" +#include "hpm_clock_drv.h" + +static PWM_Type * pwm_base_tbl[4] = {HPM_PWM0, HPM_PWM1, HPM_PWM2, HPM_PWM3}; +static const clock_name_t pwm_clock_tbl[4] = {clock_mot0, clock_mot1, clock_mot2, clock_mot3}; + +rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) +{ + uint8_t cmp_index = 0; + uint32_t duty; + pwm_cmp_config_t cmp_config[4] = {0}; + pwm_config_t pwm_config = {0}; + uint32_t reload = 0; + uint32_t freq; + PWM_Type * pwm_name_index; + clock_name_t pwm_clock; + pwm_clock = pwm_clock_tbl[pwm_index]; + pwm_name_index = pwm_base_tbl[pwm_index]; + + freq = clock_get_frequency(pwm_clock); + if(period != 0) { + reload = (uint64_t)freq * period / 1000000000; + } else { + reload = 0; + } + + pwm_stop_counter(pwm_name_index); + pwm_get_default_pwm_config(pwm_name_index, &pwm_config); + + /* + * reload and start counter + */ + pwm_set_reload(pwm_name_index, 0, reload); + pwm_set_start_count(pwm_name_index, 0, 0); + + /* + * config cmp1 and cmp2 and cmp3 + */ + cmp_config[0].mode = pwm_cmp_mode_output_compare; + cmp_config[0].cmp = reload + 1; + cmp_config[0].update_trigger = pwm_shadow_register_update_on_hw_event; + + cmp_config[1].mode = pwm_cmp_mode_output_compare; + cmp_config[1].cmp = reload + 1; + cmp_config[1].update_trigger = pwm_shadow_register_update_on_hw_event; + + cmp_config[3].mode = pwm_cmp_mode_output_compare; + cmp_config[3].cmp = reload; + cmp_config[3].update_trigger = pwm_shadow_register_update_on_modify; + + pwm_config.enable_output = true; + pwm_config.dead_zone_in_half_cycle = 0; + pwm_config.invert_output = true; + /* + * config pwm + */ + if (status_success != pwm_setup_waveform(pwm_name_index, channel, &pwm_config, channel * 2, cmp_config, 2)) { + return RT_FALSE; + } + pwm_load_cmp_shadow_on_capture(pwm_name_index, cmp_index + 17, 0); + pwm_config_cmp(pwm_name_index, cmp_index + 17, &cmp_config[3]); + pwm_start_counter(pwm_name_index); + pwm_issue_shadow_register_lock_event(pwm_name_index); + duty = (uint64_t)freq * pulse / 1000000000; + + pwm_update_raw_cmp_central_aligned(pwm_name_index, channel * 2, channel * 2 + 1, (reload - duty) >> 1, (reload + duty) >> 1); + + return RT_TRUE; + +} + +rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) +{ + uint8_t cmp_index = 0; + uint32_t duty; + pwm_cmp_config_t cmp_config[4] = {0}; + pwm_config_t pwm_config = {0}; + uint32_t reload = 0; + uint32_t freq; + PWM_Type * pwm_name_index; + clock_name_t pwm_clock; + pwm_clock = pwm_clock_tbl[pwm_index]; + pwm_name_index = pwm_base_tbl[pwm_index]; + + freq = clock_get_frequency(pwm_clock); + if(period != 0) { + reload = (uint64_t)freq * period / 1000000000; + } else { + reload = 0; + } + + pwm_get_default_pwm_config(pwm_name_index, &pwm_config); + + pwm_set_reload(pwm_name_index, 0, reload); + + cmp_config[3].mode = pwm_cmp_mode_output_compare; + cmp_config[3].cmp = reload; + cmp_config[3].update_trigger = pwm_shadow_register_update_on_modify; + +// pwm_load_cmp_shadow_on_capture(pwm_name_index, cmp_index + 4, 0); + pwm_config_cmp(pwm_name_index, cmp_index + 4, &cmp_config[3]); + + pwm_issue_shadow_register_lock_event(pwm_name_index); + duty = (uint64_t)freq * pulse / 1000000000; + + pwm_update_raw_cmp_central_aligned(pwm_name_index, channel * 2, channel * 2 + 1, (reload - duty) >> 1, (reload + duty) >> 1); + + return RT_TRUE; + +} + +rt_err_t hpm_disable_pwm(uint8_t pwm_index, uint8_t channel) +{ + + pwm_disable_output(pwm_base_tbl[pwm_index], channel); + return RT_TRUE; + +} + +rt_err_t hpm_pwm_control(struct rt_device_pwm * device, int cmd, void *arg) +{ + uint8_t channel; + uint32_t period; + uint32_t pulse; + rt_err_t sta = RT_TRUE; + unsigned char pwm_name; + struct rt_pwm_configuration * configuration; + configuration = (struct rt_pwm_configuration * )arg; + channel = configuration->channel; + period = configuration->period; + pulse = configuration->pulse; + if (strcmp("pwm0", device->parent.parent.name) == 0) { + pwm_name = 0; + } else if (strcmp("pwm1", device->parent.parent.name) == 0) { + pwm_name = 1; + } else if (strcmp("pwm2", device->parent.parent.name) == 0) { + pwm_name = 2; + } else if (strcmp("pwm3", device->parent.parent.name) == 0) { + pwm_name = 3; + } else { + return RT_FALSE; + } + + switch(cmd) { + case PWM_CMD_ENABLE: { + sta = hpm_generate_central_aligned_waveform(pwm_name, channel, period, pulse); + break; + } + case PWM_CMD_DISABLE: { + hpm_disable_pwm(pwm_name, channel); + break; + } + case PWM_CMD_SET: { + sta = hpm_set_central_aligned_waveform(pwm_name, channel, period, pulse); + break; + } + case PWM_CMD_GET: { + sta = RT_TRUE; + break; + } + default: { + sta = RT_FALSE; + break; + } + } + return sta; +} + +rt_err_t hpm_pwm_dev_control(rt_device_t device, int cmd, void *arg) +{ + uint8_t channel; + uint32_t period; + uint32_t pulse; + rt_err_t sta = RT_TRUE; + uint8_t pwm_name; + struct rt_pwm_configuration * configuration; + configuration = (struct rt_pwm_configuration * )arg; + channel = configuration->channel; + period = configuration->period; + pulse = configuration->pulse; + if (strcmp("pwm0", device->parent.name) == 0) { + pwm_name = 0; + } else if (strcmp("pwm1", device->parent.name) == 0) { + pwm_name = 1; + } else if (strcmp("pwm2", device->parent.name) == 0) { + pwm_name = 2; + } else if (strcmp("pwm3", device->parent.name) == 0) { + pwm_name = 3; + } else { + return RT_FALSE; + } + + switch(cmd) { + case PWM_CMD_ENABLE: { + sta = hpm_generate_central_aligned_waveform(pwm_name, channel, period, pulse); + break; + } + case PWM_CMD_DISABLE: { + hpm_disable_pwm(pwm_name, channel); + break; + } + case PWM_CMD_SET: { + sta = hpm_set_central_aligned_waveform(pwm_name, channel, period, pulse); + break; + } + case PWM_CMD_GET: { + sta = RT_TRUE; + break; + } + default: { + sta = RT_FALSE; + break; + } + } + return sta; +} + +const static struct rt_pwm_ops hpm_pwm_ops = { + .control = &hpm_pwm_control +}; + +static struct rt_device hpm_pwm_parent = { + .control = hpm_pwm_dev_control +}; + +static struct rt_device_pwm hpm_dev_pwm0 = { + .ops = &hpm_pwm_ops, +}; + +static struct rt_device_pwm hpm_dev_pwm1 = { + .ops = &hpm_pwm_ops, +}; + +static struct rt_device_pwm hpm_dev_pwm2 = { + .ops = &hpm_pwm_ops, +}; + +static struct rt_device_pwm hpm_dev_pwm3 = { + .ops = &hpm_pwm_ops, +}; + + +int rt_hw_pwm_init(void) +{ + int ret = RT_EOK; + hpm_dev_pwm0.parent = hpm_pwm_parent; + hpm_dev_pwm1.parent = hpm_pwm_parent; + hpm_dev_pwm2.parent = hpm_pwm_parent; + hpm_dev_pwm3.parent = hpm_pwm_parent; + ret = rt_device_pwm_register(&hpm_dev_pwm0, "pwm0", &hpm_pwm_ops, RT_NULL); + ret = rt_device_pwm_register(&hpm_dev_pwm1, "pwm1", &hpm_pwm_ops, RT_NULL); + ret = rt_device_pwm_register(&hpm_dev_pwm2, "pwm2", &hpm_pwm_ops, RT_NULL); + ret = rt_device_pwm_register(&hpm_dev_pwm3, "pwm3", &hpm_pwm_ops, RT_NULL); + + return ret; +} + +INIT_BOARD_EXPORT(rt_hw_pwm_init); + +#endif /* BSP_USING_GPIO */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_pwm.h b/bsp/hpmicro/libraries/drivers/drv_pwm.h new file mode 100644 index 0000000000..8a99e11989 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_pwm.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-01-11 HPMICRO First version + */ +#ifndef LIBRARIES_DRIVERS_DRV_PWM_H_ +#define LIBRARIES_DRIVERS_DRV_PWM_H_ + +int rt_hw_pwm_init(void); + +#endif /* LIBRARIES_DRIVERS_DRV_PWM_H_ */ diff --git a/bsp/hpmicro/libraries/drivers/drv_rtc.c b/bsp/hpmicro/libraries/drivers/drv_rtc.c new file mode 100644 index 0000000000..f701d71195 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_rtc.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2021-09-19 HPMICRO First version + */ +#include "board.h" +#include "drv_rtc.h" +#include "hpm_rtc_drv.h" + +#include +#include +#include + +#ifdef RT_USING_RTC + +/******************************************************************************************* + * + * Prototypes + * + ******************************************************************************************/ +static rt_err_t hpm_rtc_init(rt_device_t dev); +static rt_err_t hpm_rtc_open(rt_device_t dev, rt_uint16_t oflag); +static rt_err_t hpm_rtc_close(rt_device_t dev); +static rt_size_t hpm_rtc_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size); +static rt_size_t hpm_rtc_write(rt_device_t dev, rt_off_t pos, const void *buf, rt_size_t size); +static rt_err_t hpm_rtc_control(rt_device_t dev, int cmd, void *args); + +static time_t hpm_rtc_get_timestamp(void); +static int hpm_rtc_set_timestamp(time_t timestamp); + +/******************************************************************************************* + * + * Variables + * + ******************************************************************************************/ +static struct rt_device hpm_rtc= { + .type = RT_Device_Class_RTC, + .init = hpm_rtc_init, + .open = hpm_rtc_open, + .close = hpm_rtc_close, + .read = hpm_rtc_read, + .write = hpm_rtc_write, + .control = hpm_rtc_control, +}; + +/******************************************************************************************* + * + * Codes + * + ******************************************************************************************/ +static rt_err_t hpm_rtc_init(rt_device_t dev) +{ + return RT_EOK; +} +static rt_err_t hpm_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} +static rt_err_t hpm_rtc_close(rt_device_t dev) +{ + return RT_EOK; +} +static rt_size_t hpm_rtc_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size) +{ + return 0; +} +static rt_size_t hpm_rtc_write(rt_device_t dev, rt_off_t pos, const void *buf, rt_size_t size) +{ + return 0; +} +static rt_err_t hpm_rtc_control(rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + rt_err_t err = RT_EOK; + + switch(cmd) { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *(uint32_t *)args = hpm_rtc_get_timestamp(); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME: + hpm_rtc_set_timestamp(*(time_t *)args); + break; + default: + err = RT_EINVAL; + break; + } + + return err; +} + +static time_t hpm_rtc_get_timestamp(void) +{ + time_t time = rtc_get_time(HPM_RTC); + + return time; +} + +static int hpm_rtc_set_timestamp(time_t timestamp) +{ + (void)rtc_config_time(HPM_RTC, timestamp); + + return RT_EOK; +} + + +int rt_hw_rtc_init(void) +{ + rt_err_t err = RT_EOK; + + err = rt_device_register(&hpm_rtc, "rtc", RT_DEVICE_FLAG_RDWR); + if (err != RT_EOK) { + LOG_E("rt device %s failed, status=%d\n", "rtc", err); + return err; + } + + rt_device_open(&hpm_rtc, RT_DEVICE_FLAG_RDWR); + + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* RT_USING_RTC */ diff --git a/bsp/hpmicro/libraries/drivers/drv_rtc.h b/bsp/hpmicro/libraries/drivers/drv_rtc.h new file mode 100644 index 0000000000..b92d446924 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_rtc.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRV_RTC_H +#define DRV_RTC_H + +#include +#include + + +int rt_hw_rtc_init(void); + + +#endif /* DRV_RTC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/drv_sdio.c b/bsp/hpmicro/libraries/drivers/drv_sdio.c new file mode 100644 index 0000000000..e8a2250147 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_sdio.c @@ -0,0 +1,433 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-02-23 hpmicro First version + * 2022-07-19 hpmicro Fixed the multi-block read/write issue + */ +#include + +#ifdef BSP_USING_SDXC +#include +#include +#include + +#include "board.h" +#include "hpm_sdxc_drv.h" +#include "hpm_l1c_drv.h" + + +#define CACHE_LINESIZE HPM_L1C_CACHELINE_SIZE +#define SDXC_ADMA_TABLE_WORDS (2U) +#define SDXC_AMDA2_ADDR_ALIGN (4U) +#define SDXC_DATA_TIMEOUT (0xFU) + +#define SDXC_CACHELINE_ALIGN_DOWN(x) ((uint32_t)(x) & ~((uint32_t)(CACHE_LINESIZE) - 1UL)) +#define SDXC_CACHELINE_ALIGN_UP(x) SDXC_CACHELINE_ALIGN_DOWN((uint32_t)(x) + (uint32_t)(CACHE_LINESIZE) - 1U) +#define SDXC_IS_CACHELINE_ALIGNED(n) ((uint32_t)(n) % (uint32_t)(CACHE_LINESIZE) == 0U) + +struct hpm_mmcsd +{ + struct rt_mmcsd_host *host; + struct rt_mmcsd_req *req; + struct rt_mmcsd_cmd *cmd; + + struct rt_timer *timer; + + rt_uint32_t *buf; + + SDXC_Type *sdxc_base; + int32_t irq_num; + uint32_t *sdxc_adma2_table; +}; + +static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req); +static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); +static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en); +static void hpm_sdmmc_host_recovery(SDXC_Type *base); + +static const struct rt_mmcsd_host_ops hpm_mmcsd_host_ops = +{ + .request = hpm_sdmmc_request, + .set_iocfg = hpm_sdmmc_set_iocfg, + .get_card_status = NULL, + .enable_sdio_irq = NULL, // Do not use the interrupt mode, use DMA instead +}; + +/* Place the ADMA2 table to non-cacheable region */ +ATTR_PLACE_AT_NONCACHEABLE static uint32_t s_sdxc_adma2_table[SDXC_ADMA_TABLE_WORDS]; + +/** + * !@brief SDMMC request implementation based on HPMicro SDXC Host + */ +static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct hpm_mmcsd *mmcsd; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + sdxc_adma_config_t adma_config = { 0 }; + sdxc_xfer_t xfer = { 0 }; + sdxc_command_t sdxc_cmd = { 0 }; + sdxc_data_t sdxc_data = { 0 }; + uint32_t *aligned_buf = NULL; + hpm_stat_t err = status_invalid_argument; + + RT_ASSERT(host != RT_NULL); + RT_ASSERT(host->private_data != RT_NULL); + RT_ASSERT(req != RT_NULL); + RT_ASSERT(req->cmd != RT_NULL); + + mmcsd = (struct hpm_mmcsd *) host->private_data; + + cmd = req->cmd; + + data = cmd->data; + + /*　configure command　*/ + sdxc_cmd.cmd_index = cmd->cmd_code; + sdxc_cmd.cmd_argument = cmd->arg; + if (cmd->cmd_code == STOP_TRANSMISSION) + { + sdxc_cmd.cmd_type = sdxc_cmd_type_abort_cmd; + } + else + { + sdxc_cmd.cmd_type = sdxc_cmd_type_normal_cmd; + } + + switch (cmd->flags & RESP_MASK) + { + case RESP_NONE: + sdxc_cmd.resp_type = sdxc_dev_resp_none; + break; + case RESP_R1: + sdxc_cmd.resp_type = sdxc_dev_resp_r1; + break; + case RESP_R1B: + sdxc_cmd.resp_type = sdxc_dev_resp_r1b; + break; + case RESP_R2: + sdxc_cmd.resp_type = sdxc_dev_resp_r2; + break; + case RESP_R3: + sdxc_cmd.resp_type = sdxc_dev_resp_r3; + break; + case RESP_R4: + sdxc_cmd.resp_type = sdxc_dev_resp_r4; + break; + case RESP_R6: + sdxc_cmd.resp_type = sdxc_dev_resp_r6; + break; + case RESP_R7: + sdxc_cmd.resp_type = sdxc_dev_resp_r7; + break; + case RESP_R5: + sdxc_cmd.resp_type = sdxc_dev_resp_r5; + break; + default: + RT_ASSERT(NULL); + break; + } + sdxc_cmd.cmd_flags = 0UL; + xfer.command = &sdxc_cmd; + if (data != NULL) + { + sdxc_data.enable_auto_cmd12 = false; + sdxc_data.enable_auto_cmd23 = false; + + sdxc_data.enable_ignore_error = false; + sdxc_data.data_type = sdxc_xfer_data_normal; + sdxc_data.block_size = data->blksize; + sdxc_data.block_cnt = data->blks; + + /* configure adma2 */ + adma_config.dma_type = sdxc_dmasel_adma2; + adma_config.adma_table = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, + (uint32_t) mmcsd->sdxc_adma2_table); + adma_config.adma_table_words = SDXC_ADMA_TABLE_WORDS; + + if ((req->data->flags & DATA_DIR_WRITE) != 0U) + { + uint32_t write_size = data->blks * data->blksize; + if (!SDXC_IS_CACHELINE_ALIGNED(data->buf) || !SDXC_IS_CACHELINE_ALIGNED(write_size)) + { + write_size = SDXC_CACHELINE_ALIGN_UP(write_size); + aligned_buf = (uint32_t *) rt_malloc_align(write_size, CACHE_LINESIZE); + memcpy(aligned_buf, data->buf, write_size); + sdxc_data.tx_data = aligned_buf; + rt_enter_critical(); + l1c_dc_flush((uint32_t) sdxc_data.tx_data, write_size); + rt_exit_critical(); + } + else + { + sdxc_data.tx_data = (uint32_t const *) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, + (uint32_t) data->buf); + rt_enter_critical(); + l1c_dc_flush((uint32_t) data->buf, write_size); + rt_exit_critical(); + } + sdxc_data.rx_data = NULL; + } + else + { + uint32_t read_size = data->blks * data->blksize; + if (!SDXC_IS_CACHELINE_ALIGNED(data->buf) || !SDXC_IS_CACHELINE_ALIGNED(read_size)) + { + uint32_t aligned_read_size = SDXC_CACHELINE_ALIGN_UP(read_size); + aligned_buf = (uint32_t *) rt_malloc_align(aligned_read_size, CACHE_LINESIZE); + sdxc_data.rx_data = aligned_buf; + } + else + { + sdxc_data.rx_data = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t) data->buf); + } + sdxc_data.tx_data = NULL; + } + xfer.data = &sdxc_data; + + + } + else + { + xfer.data = NULL; + } + + if ((req->data->blks > 1) && ((cmd->cmd_code == READ_MULTIPLE_BLOCK) || ((cmd->cmd_code == WRITE_MULTIPLE_BLOCK)))) + { + xfer.data->enable_auto_cmd12 = true; + } + + err = sdxc_transfer_blocking(mmcsd->sdxc_base, &adma_config, &xfer); + LOG_I("cmd=%d, arg=%x\n", cmd->cmd_code, cmd->arg); + if (err != status_success) + { + hpm_sdmmc_host_recovery(mmcsd->sdxc_base); + LOG_E(" ***sdxc_transfer_blocking error: %d*** -->\n", err); + cmd->err = -RT_ERROR; + } + else + { + LOG_I(" ***sdxc_transfer_blocking passed: %d*** -->\n", err); + if (sdxc_cmd.resp_type == sdxc_dev_resp_r2) + { + LOG_I("resp:0x%08x 0x%08x 0x%08x 0x%08x\n", sdxc_cmd.response[0], + sdxc_cmd.response[1], sdxc_cmd.response[2], sdxc_cmd.response[3]); + } + else + { + LOG_I("resp:0x%08x\n", sdxc_cmd.response[0]); + } + + } + if ((sdxc_data.rx_data != NULL) && (cmd->err == RT_EOK)) + { + uint32_t read_size = data->blks * data->blksize; + if (aligned_buf != NULL) + { + uint32_t aligned_read_size = SDXC_CACHELINE_ALIGN_UP(read_size); + rt_enter_critical(); + l1c_dc_invalidate((uint32_t) aligned_buf, aligned_read_size); + rt_exit_critical(); + memcpy(data->buf, aligned_buf, read_size); + } + else + { + rt_enter_critical(); + l1c_dc_invalidate((uint32_t) data->buf, read_size); + rt_exit_critical(); + } + } + + if (aligned_buf != NULL) + { + rt_free_align(aligned_buf); + aligned_buf = NULL; + } + + if ((cmd->flags & RESP_MASK) == RESP_R2) + { + cmd->resp[3] = sdxc_cmd.response[0]; + cmd->resp[2] = sdxc_cmd.response[1]; + cmd->resp[1] = sdxc_cmd.response[2]; + cmd->resp[0] = sdxc_cmd.response[3]; + } + else + { + cmd->resp[0] = sdxc_cmd.response[0]; + } + + mmcsd_req_complete(host); +} + +/** + * !@brief Set IO Configuration for HPMicro IO and SDXC Host + */ +static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + struct hpm_mmcsd *mmcsd; + uint32_t sdxc_clk; + uint32_t vdd; + RT_ASSERT(host != RT_NULL);RT_ASSERT(host->private_data != RT_NULL);RT_ASSERT(io_cfg != RT_NULL); + + mmcsd = (struct hpm_mmcsd *) host->private_data; + + vdd = io_cfg->vdd; + + static bool has_init = false; + + init_sdxc_pins(mmcsd->sdxc_base, false); + + uint32_t sdxc_clock = io_cfg->clock; + + if (sdxc_clock != 0U) + { + switch (io_cfg->bus_width) + { + case MMCSD_BUS_WIDTH_4: + sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_4bit); + break; + case MMCSD_BUS_WIDTH_8: + sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_8bit); + break; + default: + sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_1bit); + break; + } + board_sd_configure_clock(mmcsd->sdxc_base, sdxc_clk); + } + rt_thread_mdelay(5); +} + +static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en) +{ + RT_ASSERT(host != RT_NULL);RT_ASSERT(host->private_data != RT_NULL); + + struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; + + if (en != 0) + { + intc_m_enable_irq_with_priority(mmcsd->irq_num, 1); + } + else + { + intc_m_disable_irq(mmcsd->irq_num); + } +} + +static void hpm_sdmmc_host_recovery(SDXC_Type *base) +{ + uint32_t pstate = sdxc_get_present_status(base); + bool need_reset_cmd_line = false; + bool need_reset_data_line = false; + + if ((pstate & SDXC_PSTATE_CMD_INHIBIT_MASK) != 0U) + { + /* Reset command line */ + need_reset_cmd_line = true; + } + + if ((pstate & SDXC_PSTATE_DAT_INHIBIT_MASK) != 0U) + { + /* Reset data line */ + need_reset_data_line = true; + } + + uint32_t int_stat = sdxc_get_interrupt_status(base); + + if ((int_stat & 0xF0000UL) != 0U) + { + need_reset_cmd_line = true; + } + if ((int_stat & 0x700000) != 0U) + { + need_reset_data_line = true; + } + + if (need_reset_cmd_line) + { + sdxc_reset(base, sdxc_reset_cmd_line, 0xFFFFUL); + } + if (need_reset_data_line) + { + sdxc_reset(base, sdxc_reset_data_line, 0xFFFFUL); + } + + if (need_reset_cmd_line || need_reset_data_line) + { + sdxc_clear_interrupt_status(base, ~0UL); + } + + rt_thread_mdelay(10); + LOG_E("%s\n", __func__); +} + +int rt_hw_sdio_init(void) +{ + rt_err_t err = RT_EOK; + + struct rt_mmcsd_host *host = NULL; + struct hpm_mmcsd *mmcsd = NULL; + do + { + host = mmcsd_alloc_host(); + if (host == NULL) + { + err = -RT_ERROR; + break; + } + mmcsd = rt_malloc(sizeof(struct hpm_mmcsd)); + if (mmcsd == NULL) + { + LOG_E("allocate hpm_mmcsd failed\n"); + err = -RT_ERROR; + break; + } + + rt_memset(mmcsd, 0, sizeof(struct hpm_mmcsd)); + mmcsd->sdxc_base = BOARD_APP_SDCARD_SDXC_BASE; + mmcsd->sdxc_adma2_table = s_sdxc_adma2_table; + + host->ops = &hpm_mmcsd_host_ops; + host->freq_min = 375000; + host->freq_max = 50000000; + host->valid_ocr = VDD_30_31 | VDD_31_32 | VDD_32_33 | VDD_33_34; + host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4 | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + + host->max_seg_size = 65535; + host->max_dma_segs = 2; + host->max_blk_size = 512; + host->max_blk_count = 4096; + + mmcsd->host = host; + + /* Perform necessary initialization */ + board_sd_configure_clock(mmcsd->sdxc_base, 375000); + + sdxc_config_t sdxc_config = { 0 }; + sdxc_config.data_timeout = SDXC_DATA_TIMEOUT; + sdxc_init(mmcsd->sdxc_base, &sdxc_config); + + host->private_data = mmcsd; + + mmcsd_change(host); + + } while (false); + + if (err != RT_EOK) + { + if (host != NULL) + { + mmcsd_free_host(host); + host = NULL; + } + } + + return err; +} + +INIT_DEVICE_EXPORT(rt_hw_sdio_init); +#endif diff --git a/bsp/hpmicro/libraries/drivers/drv_sdio.h b/bsp/hpmicro/libraries/drivers/drv_sdio.h new file mode 100644 index 0000000000..12bb738388 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_sdio.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRV_SDIO_H +#define DRV_SDIO_H + +int rt_hw_sdio_init(void); + +#endif /* DRV_SDIO_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/drv_spi.c b/bsp/hpmicro/libraries/drivers/drv_spi.c new file mode 100644 index 0000000000..7dd6def0d7 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_spi.c @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2021 hpm + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include + +#ifdef BSP_USING_SPI +#include +#include "board.h" +#include "drv_spi.h" +#include "hpm_spi_drv.h" +#include "hpm_sysctl_drv.h" + +struct hpm_spi +{ + uint32_t instance; + char *bus_name; + SPI_Type *spi_base; + spi_control_config_t control_config; + struct rt_spi_bus spi_bus; + rt_sem_t xfer_sem; + /* TODO: add DMA support later */ +}; + +static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg); +static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg); + +static struct hpm_spi hpm_spis[] = +{ +#if defined(BSP_USING_SPI0) + { + .bus_name = "spi0", + .spi_base = HPM_SPI0, + }, +#endif +#if defined(BSP_USING_SPI1) + { + .bus_name = "spi1", + .spi_base = HPM_SPI1, + }, +#endif +#if defined(BSP_USING_SPI2) + { + .bus_name = "spi2", + .spi_base = HPM_SPI2, + }, +#endif +#if defined(BSP_USING_SPI3) + { + .bus_name = "spi3", + .spi_base = HPM_SPI3, + }, +#endif +}; + +static struct rt_spi_ops hpm_spi_ops = +{ + .configure = hpm_spi_configure, + .xfer = hpm_spi_xfer, +}; + +static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + spi_timing_config_t timing_config = { 0 }; + spi_format_config_t format_config = { 0 }; + + struct hpm_spi *spi = RT_NULL; + + spi = (struct hpm_spi *) (device->bus->parent.user_data); + RT_ASSERT(spi != RT_NULL); + + if (cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) + { + return RT_EINVAL; + } + + spi_master_get_default_timing_config(&timing_config); + spi_master_get_default_format_config(&format_config); + + init_spi_pins(spi->spi_base); + + timing_config.master_config.clk_src_freq_in_hz = board_init_spi_clock(spi->spi_base); + + format_config.common_config.data_len_in_bits = cfg->data_width; + format_config.common_config.cpha = cfg->mode & RT_SPI_CPHA ? 1 : 0; + format_config.common_config.cpol = cfg->mode & RT_SPI_CPOL ? 1 : 0; + format_config.common_config.lsb = cfg->mode & RT_SPI_MSB ? false : true; + format_config.common_config.mosi_bidir = cfg->mode & RT_SPI_3WIRE ? true : false; + spi_format_init(spi->spi_base, &format_config); + + if (cfg->max_hz > timing_config.master_config.clk_src_freq_in_hz) + { + cfg->max_hz = timing_config.master_config.clk_src_freq_in_hz; + } + timing_config.master_config.sclk_freq_in_hz = cfg->max_hz; + + spi_master_timing_init(spi->spi_base, &timing_config); + + + spi_master_get_default_control_config(&spi->control_config); + spi->control_config.master_config.addr_enable = false; + spi->control_config.master_config.cmd_enable = false; + spi->control_config.master_config.token_enable = false; + spi->control_config.common_config.trans_mode = spi_trans_write_read_together; + + return RT_EOK; +} + +static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(msg != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + + cs_ctrl_callback_t cs_pin_control = (cs_ctrl_callback_t) device->parent.user_data; + + struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); + + hpm_stat_t spi_stat = status_success; + + if ((cs_pin_control != NULL) && msg->cs_take) + { + cs_pin_control(SPI_CS_TAKE); + } + + uint32_t remaining_size = msg->length; + uint32_t transfer_len; + uint8_t *tx_buf = (uint8_t*) msg->send_buf; + uint8_t *rx_buf = (uint8_t*) msg->recv_buf; + while (remaining_size > 0) + { + transfer_len = MIN(512, remaining_size); + if (msg->send_buf != NULL && msg->recv_buf != NULL) + { + spi->control_config.common_config.trans_mode = spi_trans_write_read_together; + spi_stat = spi_transfer(spi->spi_base, + &spi->control_config, + NULL, + NULL, + tx_buf, transfer_len, + rx_buf, transfer_len); + } + else if (msg->send_buf != NULL) + { + spi->control_config.common_config.trans_mode = spi_trans_write_only; + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, + NULL, + NULL, + (uint8_t*) tx_buf, transfer_len, + NULL, 0); + } + else + { + spi->control_config.common_config.trans_mode = spi_trans_read_only; + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, + NULL, + NULL, + NULL, 0, + rx_buf, transfer_len); + } + + if (spi_stat != status_success) + { + break; + } + + if (tx_buf != NULL) + { + tx_buf += transfer_len; + } + if (rx_buf != NULL) + { + rx_buf += transfer_len; + } + remaining_size -= transfer_len; + } + if (spi_stat != status_success) + { + msg->length = 0; + } + + if ((cs_pin_control != NULL) && msg->cs_release) + { + cs_pin_control(SPI_CS_RELEASE); + } + + return msg->length; +} + + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, cs_ctrl_callback_t callback) +{ + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + + /* attach the device to spi bus*/ + spi_device = (struct rt_spi_device *) rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void*)callback); + RT_ASSERT(result == RT_EOK); + + return result; +} + + +int rt_hw_spi_init(void) +{ + + rt_err_t ret = RT_EOK; + + for (uint32_t i = 0; i < sizeof(hpm_spis) / sizeof(hpm_spis[0]); i++) + { + hpm_spis[i].spi_bus.parent.user_data = &hpm_spis[i]; + + ret = rt_spi_bus_register(&hpm_spis[i].spi_bus, hpm_spis[i].bus_name, &hpm_spi_ops); + if (ret != RT_EOK) + { + break; + } + + char sem_name[RT_NAME_MAX]; + rt_sprintf(sem_name, "%s_s", hpm_spis[i].bus_name); + hpm_spis[i].xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); + } + + return ret; +} + +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif /*BSP_USING_SPI*/ + diff --git a/bsp/hpmicro/libraries/drivers/drv_spi.h b/bsp/hpmicro/libraries/drivers/drv_spi.h new file mode 100644 index 0000000000..b03349de86 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_spi.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRV_SPI_H +#define DRV_SPI_H + +#include +#include +#include +#include + + +#define SPI_CS_TAKE (0) +#define SPI_CS_RELEASE (1) + +typedef void (*cs_ctrl_callback_t)(uint32_t value); + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, cs_ctrl_callback_t callback); + +int rt_hw_spi_init(void); + + + +#endif /* DRV_SPI_H */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.c b/bsp/hpmicro/libraries/drivers/drv_uart.c new file mode 100644 index 0000000000..df93fb6cd2 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_uart.c @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2021-09-19 HPMICRO First version + * + */ +#include +#include +#include +#include "board.h" +#include "drv_uart.h" +#include "hpm_uart_drv.h" +#include "hpm_sysctl_drv.h" + +#ifdef RT_USING_SERIAL + +#define UART_ROOT_CLK_FREQ BOARD_APP_UART_SRC_FREQ + +struct hpm_uart { + UART_Type *uart_base; + uint32_t irq_num; + struct rt_serial_device *serial; + char *device_name; +}; + + +extern void init_uart_pins(UART_Type *ptr); +static void hpm_uart_isr(struct rt_serial_device *serial); +static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int hpm_uart_putc(struct rt_serial_device *serial, char ch); +static int hpm_uart_getc(struct rt_serial_device *serial); + + +#if defined(BSP_USING_UART0) +struct rt_serial_device serial0; +void uart0_isr(void) +{ + hpm_uart_isr(&serial0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr) +#endif + + +#if defined(BSP_USING_UART1) +struct rt_serial_device serial1; +void uart1_isr(void) +{ + hpm_uart_isr(&serial1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr) +#endif + + +#if defined(BSP_USING_UART2) +struct rt_serial_device serial2; +void uart2_isr(void) +{ + hpm_uart_isr(&serial2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr) +#endif + + +#if defined(BSP_USING_UART3) +struct rt_serial_device serial3; +void uart3_isr(void) +{ + hpm_uart_isr(&serial3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr) +#endif + + +#if defined(BSP_USING_UART4) +struct rt_serial_device serial4; +void uart4_isr(void) +{ + hpm_uart_isr(&serial4); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr) +#endif + + +#if defined(BSP_USING_UART5) +struct rt_serial_device serial5; +void uart5_isr(void) +{ + hpm_uart_isr(&serial5); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr) +#endif + + +#if defined(BSP_USING_UART6) +struct rt_serial_device serial6; +void uart6_isr(void) +{ + hpm_uart_isr(&serial6); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr) +#endif + + +#if defined(BSP_USING_UART7) +struct rt_serial_device serial7; +void uart7_isr(void) +{ + hpm_uart_isr(&serial7); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr) +#endif + + +#if defined(BSP_USING_UART8) +struct rt_serial_device serial8; +void uart8_isr(void) +{ + hpm_uart_isr(&serial8); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr) +#endif + + +#if defined(BSP_USING_UART9) +struct rt_serial_device serial9; +void uart9_isr(void) +{ + hpm_uart_isr(&serial9); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr) +#endif + + +#if defined(BSP_USING_UART10) +struct rt_serial_device serial10; +void uart10_isr(void) +{ + hpm_uart_isr(&serial10); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr) +#endif + +#if defined(BSP_USING_UART11) +struct rt_serial_device serial11; +void uart11_isr(void) +{ + hpm_uart_isr(&serial11); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr) +#endif + +#if defined(BSP_USING_UART12) +struct rt_serial_device serial12; +void uart12_isr(void) +{ + hpm_uart_isr(&serial12); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr) +#endif + +#if defined(BSP_USING_UART13) +struct rt_serial_device serial13; +void uart13_isr(void) +{ + hpm_uart_isr(&serial13); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr) +#endif + +#if defined(BSP_USING_UART14) +struct rt_serial_device serial14; +void uart14_isr(void) +{ + hpm_uart_isr(&serial14); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr) +#endif + +#if defined(BSP_USING_UART15) +struct rt_serial_device serial15; +void uart15_isr(void) +{ + hpm_uart_isr(&serial15); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr) +#endif + +static const struct hpm_uart uarts[] = { +#if defined(BSP_USING_UART0) +{ + HPM_UART0, + IRQn_UART0, + &serial0, + "uart0", +}, +#endif + +#if defined(BSP_USING_UART1) +{ + HPM_UART1, + IRQn_UART1, + &serial1, + "uart1", +}, +#endif + +#if defined(BSP_USING_UART2) +{ + HPM_UART2, + IRQn_UART2, + &serial2, + "uart2", +}, +#endif + +#if defined(BSP_USING_UART3) +{ + HPM_UART3, + IRQn_UART3, + &serial3, + "uart3", +}, +#endif + +#if defined(BSP_USING_UART4) +{ + HPM_UART4, + IRQn_UART4, + &serial4, + "uart4", +}, +#endif + +#if defined(BSP_USING_UART5) +{ + HPM_UART5, + IRQn_UART5, + &serial5, + "uart5", +}, +#endif + +#if defined(BSP_USING_UART6) +{ + HPM_UART6, + IRQn_UART6, + &serial6, + "uart6", +}, +#endif + +#if defined(BSP_USING_UART7) +{ + HPM_UART7, + IRQn_UART7, + &serial7, + "uart7", +}, +#endif + +#if defined(BSP_USING_UART8) +{ + HPM_UART8, + IRQn_UART8, + &serial8, + "uart8", +}, +#endif + +#if defined(BSP_USING_UART9) +{ + HPM_UART9, + IRQn_UART9, + &serial9, + "uart9", +}, +#endif + +#if defined(BSP_USING_UART10) +{ + HPM_UART10, + IRQn_UART10, + &serial10, + "uart10", +}, +#endif + +#if defined(BSP_USING_UART11) +{ + HPM_UART11, + IRQn_UART11, + &serial11, + "uart11", +}, +#endif + +#if defined(BSP_USING_UART12) +{ + HPM_UART12, + IRQn_UART12, + &serial12, + "uart12", +}, +#endif + +#if defined(BSP_USING_UART13) +{ + HPM_UART13, + IRQn_UART13, + &serial13, + "uart13", +}, +#endif + +#if defined(BSP_USING_UART14) +{ + HPM_UART14, + IRQn_UART14, + &serial14, + "uart14", +}, +#endif + +#if defined(BSP_USING_UART15) +{ + HPM_UART15, + IRQn_UART15, + &serial15, + "uart15", +}, +#endif + +}; + +/** + * @brief UART common interrupt process. This + * + * @param serial Serial device + */ +static void hpm_uart_isr(struct rt_serial_device *serial) +{ + struct hpm_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct hpm_uart *)serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* UART in mode Receiver */ + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + + /* leave interrupt */ + rt_interrupt_leave(); +} + + +static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart_config_t uart_config; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + + init_uart_pins(uart->uart_base); + uart_default_config(uart->uart_base, &uart_config); + + uart_config.src_freq_in_hz = board_init_uart_clock(uart->uart_base); + uart_config.baudrate = cfg->baud_rate; + uart_config.num_of_stop_bits = cfg->stop_bits; + uart_config.parity = cfg->parity; + + uart_config.word_length = cfg->data_bits - DATA_BITS_5; + + board_init_uart(uart->uart_base); + uart_init(uart->uart_base, &uart_config); + + hpm_uart_control(serial, RT_DEVICE_CTRL_SET_INT, NULL); +} + + +static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + RT_ASSERT(serial != RT_NULL); + + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + + switch (cmd) { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + uart_disable_irq(uart->uart_base, uart_intr_rx_data_avail_or_timeout); + intc_m_disable_irq(uart->irq_num); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + uart_enable_irq(uart->uart_base, uart_intr_rx_data_avail_or_timeout); + intc_m_enable_irq_with_priority(uart->irq_num, 1); + break; + } + + return RT_EOK; +} + + +static int hpm_uart_putc(struct rt_serial_device *serial, char ch) +{ + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + uart_send_byte(uart->uart_base, ch); + uart_flush(uart->uart_base); +} + +static int hpm_uart_getc(struct rt_serial_device *serial) +{ + int result = -1; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + + if (uart_check_status(uart->uart_base, uart_stat_data_ready)) { + uart_receive_byte(uart->uart_base, (uint8_t*)&result); + } + + return result; +} + + +static const struct rt_uart_ops hpm_uart_ops = { + hpm_uart_configure, + hpm_uart_control, + hpm_uart_putc, + hpm_uart_getc, +}; + + + +int rt_hw_uart_init(void) +{ + + /* Added bypass logic here since the rt_hw_uart_init function will be initialized twice, the 2nd initialization should be bypassed */ + static bool initialized; + rt_err_t err = RT_EOK; + if (initialized) + { + return err; + } + else + { + initialized = true; + } + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + for (uint32_t i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { + uarts[i].serial->ops = &hpm_uart_ops; + uarts[i].serial->config = config; + + /* register UART deivce */ + err = rt_hw_serial_register(uarts[i].serial, + uarts[i].device_name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + (void*)&uarts[i]); + } + + return err; +} + +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.h b/bsp/hpmicro/libraries/drivers/drv_uart.h new file mode 100644 index 0000000000..6b51451234 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_uart.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRV_UART_H +#define DRV_UART_H + +int rt_hw_uart_init(void); + + + +#endif /* DRV_UART_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/drv_uart_v2.c b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c new file mode 100644 index 0000000000..ce82dfb0cb --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c @@ -0,0 +1,1309 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-08 hpmicro First version + * 2022-07-28 hpmicro Fix compiling warning if RT_SERIAL_USING_DMA was not defined + * 2022-08-08 hpmicro Integrate DMA Manager and support dynamic DMA resource assignment + * + */ +#include +#include +#include "board.h" +#include "drv_uart_v2.h" +#include "hpm_uart_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_l1c_drv.h" +#include "hpm_dma_drv.h" +#include "hpm_dmamux_drv.h" +#include "hpm_dma_manager.h" +#include "hpm_soc.h" + +#ifdef RT_USING_SERIAL_V2 + +#ifdef RT_SERIAL_USING_DMA +#define BOARD_UART_DMAMUX HPM_DMAMUX +#define UART_DMA_TRIGGER_LEVEL (1U) + +typedef struct dma_channel { + struct rt_serial_device *serial; + hpm_dma_resource_t resource; + void (*tranfer_done)(struct rt_serial_device *serial); + void (*tranfer_abort)(struct rt_serial_device *serial); + void (*tranfer_error)(struct rt_serial_device *serial); +} hpm_dma_channel_handle_t; + +//static struct dma_channel dma_channels[DMA_SOC_CHANNEL_NUM]; +static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg); +#endif + +#define UART_ROOT_CLK_FREQ BOARD_APP_UART_SRC_FREQ + +struct hpm_uart { + UART_Type *uart_base; + uint32_t irq_num; + struct rt_serial_device *serial; + char *device_name; +#ifdef RT_SERIAL_USING_DMA + uint32_t tx_dma_mux; + uint32_t rx_dma_mux; + uint32_t dma_flags; + hpm_dma_channel_handle_t tx_chn_ctx; + hpm_dma_channel_handle_t rx_chn_ctx; + bool tx_resource_allocated; + bool rx_resource_allocated; +#endif +}; + + +extern void init_uart_pins(UART_Type *ptr); +static void hpm_uart_isr(struct rt_serial_device *serial); +static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int hpm_uart_putc(struct rt_serial_device *serial, char ch); +static int hpm_uart_getc(struct rt_serial_device *serial); + +#ifdef RT_SERIAL_USING_DMA +int hpm_uart_dma_register_channel(struct rt_serial_device *serial, + bool is_tx, + void (*done)(struct rt_serial_device *serial), + void (*abort)(struct rt_serial_device *serial), + void (*error)(struct rt_serial_device *serial)) +{ + + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + + if (is_tx) { + uart->tx_chn_ctx.serial = serial; + uart->tx_chn_ctx.tranfer_done = done; + uart->tx_chn_ctx.tranfer_abort = abort; + uart->tx_chn_ctx.tranfer_error = error; + } else { + uart->rx_chn_ctx.serial = serial; + uart->rx_chn_ctx.tranfer_done = done; + uart->rx_chn_ctx.tranfer_abort = abort; + uart->rx_chn_ctx.tranfer_error = error; + } + return RT_EOK; +} +#endif /* RT_SERIAL_USING_DMA */ + +#if defined(BSP_USING_UART0) +struct rt_serial_device serial0; +void uart0_isr(void) +{ + hpm_uart_isr(&serial0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr) +#endif + + +#if defined(BSP_USING_UART1) +struct rt_serial_device serial1; +void uart1_isr(void) +{ + hpm_uart_isr(&serial1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr) +#endif + + +#if defined(BSP_USING_UART2) +struct rt_serial_device serial2; +void uart2_isr(void) +{ + hpm_uart_isr(&serial2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr) +#endif + + +#if defined(BSP_USING_UART3) +struct rt_serial_device serial3; +void uart3_isr(void) +{ + hpm_uart_isr(&serial3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr) +#endif + + +#if defined(BSP_USING_UART4) +struct rt_serial_device serial4; +void uart4_isr(void) +{ + hpm_uart_isr(&serial4); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr) +#endif + + +#if defined(BSP_USING_UART5) +struct rt_serial_device serial5; +void uart5_isr(void) +{ + hpm_uart_isr(&serial5); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr) +#endif + + +#if defined(BSP_USING_UART6) +struct rt_serial_device serial6; +void uart6_isr(void) +{ + hpm_uart_isr(&serial6); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr) +#endif + + +#if defined(BSP_USING_UART7) +struct rt_serial_device serial7; +void uart7_isr(void) +{ + hpm_uart_isr(&serial7); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr) +#endif + + +#if defined(BSP_USING_UART8) +struct rt_serial_device serial8; +void uart8_isr(void) +{ + hpm_uart_isr(&serial8); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr) +#endif + + +#if defined(BSP_USING_UART9) +struct rt_serial_device serial9; +void uart9_isr(void) +{ + hpm_uart_isr(&serial9); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr) +#endif + + +#if defined(BSP_USING_UART10) +struct rt_serial_device serial10; +void uart10_isr(void) +{ + hpm_uart_isr(&serial10); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr) +#endif + +#if defined(BSP_USING_UART11) +struct rt_serial_device serial11; +void uart11_isr(void) +{ + hpm_uart_isr(&serial11); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr) +#endif + +#if defined(BSP_USING_UART12) +struct rt_serial_device serial12; +void uart12_isr(void) +{ + hpm_uart_isr(&serial12); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr) +#endif + +#if defined(BSP_USING_UART13) +struct rt_serial_device serial13; +void uart13_isr(void) +{ + hpm_uart_isr(&serial13); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr) +#endif + +#if defined(BSP_USING_UART14) +struct rt_serial_device serial14; +void uart14_isr(void) +{ + hpm_uart_isr(&serial14); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr) +#endif + +#if defined(BSP_USING_UART15) +struct rt_serial_device serial15; +void uart15_isr(void) +{ + hpm_uart_isr(&serial15); +} +SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr) +#endif + +static struct hpm_uart uarts[] = +{ +#if defined(BSP_USING_UART0) +{ + HPM_UART0, + IRQn_UART0, + &serial0, + "uart0", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART0_TX, + HPM_DMA_SRC_UART0_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART1) +{ + HPM_UART1, + IRQn_UART1, + &serial1, + "uart1", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART1_TX, + HPM_DMA_SRC_UART1_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART2) +{ + HPM_UART2, + IRQn_UART2, + &serial2, + "uart2", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART2_TX, + HPM_DMA_SRC_UART2_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART3) +{ + HPM_UART3, + IRQn_UART3, + &serial3, + "uart3", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART3_TX, + HPM_DMA_SRC_UART3_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART4) +{ + HPM_UART4, + IRQn_UART4, + &serial4, + "uart4", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART4_TX, + HPM_DMA_SRC_UART4_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART5) +{ + HPM_UART5, + IRQn_UART5, + &serial5, + "uart5", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART5_TX, + HPM_DMA_SRC_UART5_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART6) +{ + HPM_UART6, + IRQn_UART6, + &serial6, + "uart6", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART6_TX, + HPM_DMA_SRC_UART6_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART7) +{ + HPM_UART7, + IRQn_UART7, + &serial7, + "uart7", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART7_TX, + HPM_DMA_SRC_UART7_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART8) +{ + HPM_UART8, + IRQn_UART8, + &serial8, + "uart8", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART8_TX, + HPM_DMA_SRC_UART8_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART9) +{ + HPM_UART9, + IRQn_UART9, + &serial9, + "uart9", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART9_TX, + HPM_DMA_SRC_UART9_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART10) +{ + HPM_UART10, + IRQn_UART10, + &serial10, + "uart10", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART10_TX, + HPM_DMA_SRC_UART10_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART11) +{ + HPM_UART11, + IRQn_UART11, + &serial11, + "uart11", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART11_TX, + HPM_DMA_SRC_UART11_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART12) +{ + HPM_UART12, + IRQn_UART12, + &serial12, + "uart12", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART12_TX, + HPM_DMA_SRC_UART12_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART13) +{ + HPM_UART13, + IRQn_UART13, + &serial13, + "uart13", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART13_TX, + HPM_DMA_SRC_UART13_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART14) +{ + HPM_UART14, + IRQn_UART14, + &serial14, + "uart14", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART14_TX, + HPM_DMA_SRC_UART14_RX, + 0, +#endif +}, +#endif + +#if defined(BSP_USING_UART15) +{ + HPM_UART15, + IRQn_UART15, + &serial15, + "uart15", +#ifdef RT_SERIAL_USING_DMA + HPM_DMA_SRC_UART15_TX, + HPM_DMA_SRC_UART15_RX, + 0, +#endif +}, +#endif + +}; + +enum +{ +#if defined(BSP_USING_UART0) + HPM_UART0_INDEX, +#endif + +#if defined(BSP_USING_UART1) + HPM_UART1_INDEX, +#endif + +#if defined(BSP_USING_UART2) + HPM_UART2_INDEX, +#endif + +#if defined(BSP_USING_UART3) + HPM_UART3_INDEX, +#endif + +#if defined(BSP_USING_UART4) + HPM_UART4_INDEX, +#endif + +#if defined(BSP_USING_UART5) + HPM_UART15_INDEX, +#endif + +#if defined(BSP_USING_UART6) + HPM_UART6_INDEX, +#endif + +#if defined(BSP_USING_UART7) + HPM_UART7_INDEX, +#endif + +#if defined(BSP_USING_UART8) + HPM_UART8_INDEX, +#endif + +#if defined(BSP_USING_UART9) + HPM_UART10_INDEX, +#endif + +#if defined(BSP_USING_UART10) + HPM_UART10_INDEX, +#endif + +#if defined(BSP_USING_UART11) + HPM_UART11_INDEX, +#endif + +#if defined(BSP_USING_UART12) + HPM_UART12_INDEX, +#endif + +#if defined(BSP_USING_UART13) + HPM_UART13_INDEX, +#endif + +#if defined(BSP_USING_UART14) + HPM_UART14_INDEX, +#endif + +#if defined(BSP_USING_UART15) + HPM_UART15_INDEX, +#endif +}; + +#if defined(RT_SERIAL_USING_DMA) + +static void uart_dma_callback(DMA_Type *base, uint32_t channel, void *user_data, uint32_t int_stat) +{ + hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; + if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) + { + return; + } + + if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_TC) && (dma_handle->tranfer_done != NULL)) + { + dma_handle->tranfer_done(dma_handle->serial); + } + + if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_ABORT) && (dma_handle->tranfer_abort != NULL)) + { + dma_handle->tranfer_abort(dma_handle->serial); + } + + if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_ERROR) && (dma_handle->tranfer_error != NULL)) + { + dma_handle->tranfer_error(dma_handle->serial); + } +} + + + +static void uart_tx_done(struct rt_serial_device *serial) +{ + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); +} + +static void uart_rx_done(struct rt_serial_device *serial) +{ + struct rt_serial_rx_fifo *rx_fifo; + + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + if (l1c_dc_is_enabled()) { + l1c_dc_invalidate((uint32_t)rx_fifo->buffer, serial->config.rx_bufsz); + } + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (serial->config.rx_bufsz << 8)); + /* prepare for next read */ + hpm_uart_dma_config(serial, (void *)RT_DEVICE_FLAG_DMA_RX); +} +#endif /* RT_SERIAL_USING_DMA */ + +/** + * @brief UART common interrupt process. This + * + * @param serial Serial device + */ +static void hpm_uart_isr(struct rt_serial_device *serial) +{ + struct hpm_uart *uart; + rt_uint32_t stat, enabled_irq; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct hpm_uart *)serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + /* enter interrupt */ + rt_interrupt_enter(); + stat = uart_get_status(uart->uart_base); + enabled_irq = uart_get_enabled_irq(uart->uart_base); + if ((enabled_irq & uart_intr_rx_data_avail_or_timeout) && (stat & uart_stat_data_ready)) { + struct rt_serial_rx_fifo *rx_fifo; + rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx; + rt_uint8_t put_char = 0; + uart_receive_byte(uart->uart_base, &put_char); + rt_ringbuffer_putchar(&(rx_fifo->rb), put_char); + /* UART in mode Receiver */ + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + if ((enabled_irq & uart_intr_tx_slot_avail) && (stat & uart_stat_tx_slot_avail)) { + /* UART in mode Transmitter */ + struct rt_serial_tx_fifo *tx_fifo; + tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; + RT_ASSERT(tx_fifo != RT_NULL); + rt_uint8_t put_char = 0; + for (;;) { + if (rt_ringbuffer_getchar(&(tx_fifo->rb), &put_char)) { + uart_send_byte(uart->uart_base, put_char); + } else { + uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + break; + } + } + } + /* leave interrupt */ + rt_interrupt_leave(); +} + + +static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart_config_t uart_config; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + + init_uart_pins(uart->uart_base); + uart_default_config(uart->uart_base, &uart_config); + + uart_config.src_freq_in_hz = board_init_uart_clock(uart->uart_base); + uart_config.baudrate = cfg->baud_rate; + uart_config.num_of_stop_bits = cfg->stop_bits; + uart_config.parity = cfg->parity; +#ifdef RT_SERIAL_USING_DMA + if (uart->dma_flags & (RT_DEVICE_FLAG_DMA_TX | RT_DEVICE_FLAG_DMA_RX)) { + uart_config.fifo_enable = true; + uart_config.dma_enable = true; + if (uart->dma_flags & RT_DEVICE_FLAG_DMA_TX) { + uart_config.tx_fifo_level = uart_tx_fifo_trg_not_full; + } + if (uart->dma_flags & RT_DEVICE_FLAG_DMA_RX) { + uart_config.rx_fifo_level = uart_rx_fifo_trg_not_empty; + } + } +#endif + + uart_config.word_length = cfg->data_bits - DATA_BITS_5; + hpm_stat_t status = uart_init(uart->uart_base, &uart_config); + return (status != status_success) ? -RT_ERROR : RT_EOK; +} + +#ifdef RT_SERIAL_USING_DMA + +hpm_stat_t hpm_uart_dma_rx_init(struct hpm_uart *uart_ctx) +{ + hpm_stat_t status = status_fail; + if (!uart_ctx->rx_resource_allocated) + { + status = dma_manager_request_resource(&uart_ctx->rx_chn_ctx.resource); + if (status == status_success) + { + uart_ctx->dma_flags |= RT_DEVICE_FLAG_DMA_RX; + uart_ctx->rx_resource_allocated = true; + dma_manager_install_interrupt_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_callback, &uart_ctx->rx_chn_ctx); + } + } + return status; +} + +hpm_stat_t hpm_uart_dma_tx_init(struct hpm_uart *uart_ctx) +{ + hpm_stat_t status = status_fail; + if (!uart_ctx->tx_resource_allocated) + { + status = dma_manager_request_resource(&uart_ctx->tx_chn_ctx.resource); + if (status == status_success) + { + uart_ctx->dma_flags |= RT_DEVICE_FLAG_DMA_TX; + uart_ctx->tx_resource_allocated = true; + dma_manager_install_interrupt_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_callback, &uart_ctx->tx_chn_ctx); + } + } + return status; +} + +static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) +{ + rt_ubase_t ctrl_arg = (rt_ubase_t) arg; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + dma_handshake_config_t config; + struct rt_serial_rx_fifo *rx_fifo; + + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + config.ch_index = uart->rx_chn_ctx.resource.channel; + config.dst = (uint32_t) rx_fifo->buffer; + config.dst_fixed = false; + config.src = (uint32_t)&(uart->uart_base->RBR); + config.src_fixed = true; + config.size_in_byte = serial->config.rx_bufsz; + if (status_success != dma_setup_handshake(uart->rx_chn_ctx.resource.base, &config)) { + return RT_ERROR; + } + uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->rx_chn_ctx.resource.base, uart->rx_dma_mux); + dmamux_config(BOARD_UART_DMAMUX, uart->rx_chn_ctx.resource.channel, mux, true); + hpm_uart_dma_register_channel(serial, false, uart_rx_done, RT_NULL, RT_NULL); + intc_m_enable_irq(uart->rx_chn_ctx.resource.irq_num); + } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { + uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->tx_chn_ctx.resource.base, uart->tx_dma_mux); + dmamux_config(BOARD_UART_DMAMUX, uart->tx_chn_ctx.resource.channel, mux, true); + intc_m_enable_irq(uart->tx_chn_ctx.resource.irq_num); + } + return RT_EOK; +} + +static void hpm_uart_transmit_dma(DMA_Type *dma, uint32_t ch_num, UART_Type *uart, uint8_t *src, uint32_t size) +{ + rt_base_t align = 0; + dma_handshake_config_t config; + + config.ch_index = ch_num; + config.dst = (uint32_t)&uart->THR; + config.dst_fixed = true; + config.src = (uint32_t) src; + config.src_fixed = false; + config.size_in_byte = size; + dma_setup_handshake(dma, &config); +} + +#endif /* RT_SERIAL_USING_DMA */ + +static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + RT_ASSERT(serial != RT_NULL); + + rt_ubase_t ctrl_arg = (rt_ubase_t) arg; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + + if(ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING)) + { +#ifdef RT_SERIAL_USING_DMA + if (uart->dma_flags & RT_DEVICE_FLAG_DMA_RX) + { + ctrl_arg = RT_DEVICE_FLAG_DMA_RX; + } + else +#endif + { + ctrl_arg = RT_DEVICE_FLAG_INT_RX; + } + } + else if(ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING)) + { +#ifdef RT_SERIAL_USING_DMA + if (uart->dma_flags & RT_DEVICE_FLAG_DMA_TX) + { + ctrl_arg = RT_DEVICE_FLAG_DMA_TX; + } + else +#endif + { + ctrl_arg = RT_DEVICE_FLAG_INT_TX; + } + } + + switch (cmd) { + case RT_DEVICE_CTRL_CLR_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) { + /* disable rx irq */ + uart_disable_irq(uart->uart_base, uart_intr_rx_data_avail_or_timeout); + intc_m_disable_irq(uart->irq_num); + } + else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) { + /* disable tx irq */ + uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); + intc_m_disable_irq(uart->irq_num); + } +#ifdef RT_SERIAL_USING_DMA + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { + dma_manager_disable_channel_interrupt(&uart->tx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); + dma_abort_channel(uart->tx_chn_ctx.resource.base, uart->tx_chn_ctx.resource.channel); + } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { + dma_manager_disable_channel_interrupt(&uart->rx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); + dma_abort_channel(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); + } +#endif + break; + + case RT_DEVICE_CTRL_SET_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) { + /* enable rx irq */ + uart_enable_irq(uart->uart_base, uart_intr_rx_data_avail_or_timeout); + intc_m_enable_irq_with_priority(uart->irq_num, 1); + } else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) { + /* enable tx irq */ + uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); + intc_m_enable_irq_with_priority(uart->irq_num, 1); + } + break; + + case RT_DEVICE_CTRL_CONFIG: +#ifdef RT_SERIAL_USING_DMA + if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX)) { + hpm_uart_dma_config(serial, (void *)ctrl_arg); + } else +#endif + { + hpm_uart_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg); + } + break; + case RT_DEVICE_CHECK_OPTMODE: +#ifdef RT_SERIAL_USING_DMA + if ((ctrl_arg & RT_DEVICE_FLAG_DMA_TX)) { + return RT_SERIAL_TX_BLOCKING_NO_BUFFER; + } else +#endif + { + return RT_SERIAL_TX_BLOCKING_BUFFER; + } + } + + return RT_EOK; +} + + +static int hpm_uart_putc(struct rt_serial_device *serial, char ch) +{ + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + uart_send_byte(uart->uart_base, ch); + uart_flush(uart->uart_base); + return ch; +} + +static int hpm_uart_getc(struct rt_serial_device *serial) +{ + int result = -1; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + + if (uart_check_status(uart->uart_base, uart_stat_data_ready)) { + uart_receive_byte(uart->uart_base, (uint8_t*)&result); + } + + return result; +} + +static rt_size_t hpm_uart_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + rt_uint32_t tx_flag) +{ + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(buf != RT_NULL); + RT_ASSERT(size); + +#ifdef RT_SERIAL_USING_DMA + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + if (uart->dma_flags & RT_DEVICE_FLAG_DMA_TX) { + hpm_uart_dma_register_channel(serial, true, uart_tx_done, RT_NULL, RT_NULL); + intc_m_enable_irq(uart->tx_chn_ctx.resource.irq_num); + hpm_uart_transmit_dma(uart->tx_chn_ctx.resource.base, uart->tx_chn_ctx.resource.channel, uart->uart_base, buf, size); + return size; + } +#endif + hpm_uart_control(serial, RT_DEVICE_CTRL_CONFIG, (void *)tx_flag); + return size; +} + +static const struct rt_uart_ops hpm_uart_ops = { + hpm_uart_configure, + hpm_uart_control, + hpm_uart_putc, + hpm_uart_getc, + hpm_uart_transmit, +}; + + + +static int hpm_uart_config(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + hpm_stat_t status = status_success; + +#ifdef BSP_USING_UART0 + uarts[HPM_UART0_INDEX].serial->config = config; + uarts[HPM_UART0_INDEX].serial->config.rx_bufsz = BSP_UART0_RX_BUFSIZE; + uarts[HPM_UART0_INDEX].serial->config.tx_bufsz = BSP_UART0_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART0_INDEX].dma_flags = 0; +#ifdef BSP_UART0_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART0_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART0_RX_USING_DMA +#ifdef BSP_UART0_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART0_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART0_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART0 + +#ifdef BSP_USING_UART1 + uarts[HPM_UART1_INDEX].serial->config = config; + uarts[HPM_UART1_INDEX].serial->config.rx_bufsz = BSP_UART1_RX_BUFSIZE; + uarts[HPM_UART1_INDEX].serial->config.tx_bufsz = BSP_UART1_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART1_INDEX].dma_flags = 0; +#ifdef BSP_UART1_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART1_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART1_RX_USING_DMA +#ifdef BSP_UART1_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART1_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART1_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART1 + +#ifdef BSP_USING_UART2 + uarts[HPM_UART2_INDEX].serial->config = config; + uarts[HPM_UART2_INDEX].serial->config.rx_bufsz = BSP_UART2_RX_BUFSIZE; + uarts[HPM_UART2_INDEX].serial->config.tx_bufsz = BSP_UART2_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART2_INDEX].dma_flags = 0; +#ifdef BSP_UART2_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART2_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART2_RX_USING_DMA +#ifdef BSP_UART2_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART2_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART2_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART2 + +#ifdef BSP_USING_UART3 + uarts[HPM_UART3_INDEX].serial->config = config; + uarts[HPM_UART3_INDEX].serial->config.rx_bufsz = BSP_UART3_RX_BUFSIZE; + uarts[HPM_UART3_INDEX].serial->config.tx_bufsz = BSP_UART3_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART3_INDEX].dma_flags = 0; +#ifdef BSP_UART3_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART3_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART3_RX_USING_DMA +#ifdef BSP_UART3_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART3_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART3_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART3 + +#ifdef BSP_USING_UART4 + uarts[HPM_UART4_INDEX].serial->config = config; + uarts[HPM_UART4_INDEX].serial->config.rx_bufsz = BSP_UART4_RX_BUFSIZE; + uarts[HPM_UART4_INDEX].serial->config.tx_bufsz = BSP_UART4_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART4_INDEX].dma_flags = 0; +#ifdef BSP_UART4_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART4_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART4_RX_USING_DMA +#ifdef BSP_UART4_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART4_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART4_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART4 + +#ifdef BSP_USING_UART5 + uarts[HPM_UART5_INDEX].serial->config = config; + uarts[HPM_UART5_INDEX].serial->config.rx_bufsz = BSP_UART5_RX_BUFSIZE; + uarts[HPM_UART5_INDEX].serial->config.tx_bufsz = BSP_UART5_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART5_INDEX].dma_flags = 0; +#ifdef BSP_UART5_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART5_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART5_RX_USING_DMA +#ifdef BSP_UART5_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART5_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART5_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART5 + +#ifdef BSP_USING_UART6 + uarts[HPM_UART6_INDEX].serial->config = config; + uarts[HPM_UART6_INDEX].serial->config.rx_bufsz = BSP_UART6_RX_BUFSIZE; + uarts[HPM_UART6_INDEX].serial->config.tx_bufsz = BSP_UART6_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART6_INDEX].dma_flags = 0; +#ifdef BSP_UART6_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART6_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART6_RX_USING_DMA +#ifdef BSP_UART6_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART6_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART6_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART6 + +#ifdef BSP_USING_UART7 + uarts[HPM_UART7_INDEX].serial->config = config; + uarts[HPM_UART7_INDEX].serial->config.rx_bufsz = BSP_UART7_RX_BUFSIZE; + uarts[HPM_UART7_INDEX].serial->config.tx_bufsz = BSP_UART7_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART7_INDEX].dma_flags = 0; +#ifdef BSP_UART7_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART7_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART7_RX_USING_DMA +#ifdef BSP_UART0_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART7_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART7_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART7 + +#ifdef BSP_USING_UART8 + uarts[HPM_UART8_INDEX].serial->config = config; + uarts[HPM_UART8_INDEX].serial->config.rx_bufsz = BSP_UART8_RX_BUFSIZE; + uarts[HPM_UART8_INDEX].serial->config.tx_bufsz = BSP_UART8_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART8_INDEX].dma_flags = 0; +#ifdef BSP_UART8_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART8_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART8_RX_USING_DMA +#ifdef BSP_UART0_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART8_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART8_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART8 + +#ifdef BSP_USING_UART9 + uarts[HPM_UART9_INDEX].serial->config = config; + uarts[HPM_UART9_INDEX].serial->config.rx_bufsz = BSP_UART9_RX_BUFSIZE; + uarts[HPM_UART9_INDEX].serial->config.tx_bufsz = BSP_UART9_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART9_INDEX].dma_flags = 0; +#ifdef BSP_UART9_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART9_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART9_RX_USING_DMA +#ifdef BSP_UART9_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART9_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART9_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART9 + +#ifdef BSP_USING_UART10 + uarts[HPM_UART10_INDEX].serial->config = config; + uarts[HPM_UART10_INDEX].serial->config.rx_bufsz = BSP_UART10_RX_BUFSIZE; + uarts[HPM_UART10_INDEX].serial->config.tx_bufsz = BSP_UART10_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART10_INDEX].dma_flags = 0; +#ifdef BSP_UART10_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART10_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART10_RX_USING_DMA +#ifdef BSP_UART10_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART10_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART10_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART10 + +#ifdef BSP_USING_UART11 + uarts[HPM_UART11_INDEX].serial->config = config; + uarts[HPM_UART11_INDEX].serial->config.rx_bufsz = BSP_UART11_RX_BUFSIZE; + uarts[HPM_UART11_INDEX].serial->config.tx_bufsz = BSP_UART11_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART11_INDEX].dma_flags = 0; +#ifdef BSP_UART11_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART11_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART11_RX_USING_DMA +#ifdef BSP_UART11_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART11_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART11_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART11 + +#ifdef BSP_USING_UART12 + uarts[HPM_UART12_INDEX].serial->config = config; + uarts[HPM_UART12_INDEX].serial->config.rx_bufsz = BSP_UART12_RX_BUFSIZE; + uarts[HPM_UART12_INDEX].serial->config.tx_bufsz = BSP_UART12_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART12_INDEX].dma_flags = 0; +#ifdef BSP_UART12_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART12_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART12_RX_USING_DMA +#ifdef BSP_UART12_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART12_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART12_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART12 + +#ifdef BSP_USING_UART13 + uarts[HPM_UART13_INDEX].serial->config = config; + uarts[HPM_UART13_INDEX].serial->config.rx_bufsz = BSP_UART13_RX_BUFSIZE; + uarts[HPM_UART13_INDEX].serial->config.tx_bufsz = BSP_UART13_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART13_INDEX].dma_flags = 0; +#ifdef BSP_UART13_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART13_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART13_RX_USING_DMA +#ifdef BSP_UART13_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART13_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART13_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART13 + +#ifdef BSP_USING_UART14 + uarts[HPM_UART14_INDEX].serial->config = config; + uarts[HPM_UART14_INDEX].serial->config.rx_bufsz = BSP_UART14_RX_BUFSIZE; + uarts[HPM_UART14_INDEX].serial->config.tx_bufsz = BSP_UART14_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART14_INDEX].dma_flags = 0; +#ifdef BSP_UART14_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART14_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART14_RX_USING_DMA +#ifdef BSP_UART14_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART14_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART14_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART14 + +#ifdef BSP_USING_UART15 + uarts[HPM_UART15_INDEX].serial->config = config; + uarts[HPM_UART15_INDEX].serial->config.rx_bufsz = BSP_UART15_RX_BUFSIZE; + uarts[HPM_UART15_INDEX].serial->config.tx_bufsz = BSP_UART15_TX_BUFSIZE; +#ifdef RT_SERIAL_USING_DMA + uarts[HPM_UART15_INDEX].dma_flags = 0; +#ifdef BSP_UART15_RX_USING_DMA + status = hpm_uart_dma_rx_init(&uarts[HPM_UART15_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART15_RX_USING_DMA +#ifdef BSP_UART15_TX_USING_DMA + status = hpm_uart_dma_tx_init(&uarts[HPM_UART15_INDEX]); + if (status != status_success) + { + return -RT_ERROR; + } +#endif //BSP_UART15_TX_USING_DMA +#endif // RT_SERIAL_USING_DMA +#endif //BSP_USING_UART15 + + + return RT_EOK; +} + +int rt_hw_uart_init(void) +{ + /* Added bypass logic here since the rt_hw_uart_init function will be initialized twice, the 2nd initialization should be bypassed */ + static bool initialized; + rt_err_t err = RT_EOK; + if (initialized) + { + return err; + } + else + { + initialized = true; + } + + if (RT_EOK != hpm_uart_config()) { + return RT_ERROR; + } + + for (uint32_t i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) { + uarts[i].serial->ops = &hpm_uart_ops; + + /* register UART device */ + err = rt_hw_serial_register(uarts[i].serial, + uarts[i].device_name, + RT_DEVICE_FLAG_RDWR, + (void*)&uarts[i]); + } + + return err; +} + +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/hpmicro/libraries/drivers/drv_uart_v2.h b/bsp/hpmicro/libraries/drivers/drv_uart_v2.h new file mode 100644 index 0000000000..6b51451234 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_uart_v2.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRV_UART_H +#define DRV_UART_H + +int rt_hw_uart_init(void); + + + +#endif /* DRV_UART_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/drv_usb.c b/bsp/hpmicro/libraries/drivers/drv_usb.c new file mode 100644 index 0000000000..946a9f3a1a --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_usb.c @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include +#include "tusb.h" + +/* Definition of logic unit number for each drive */ +#define LUN_USB (0U) /* lun 0 of usb drive */ + +static rt_size_t hpm_usb_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size); +static rt_size_t hpm_usb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); +rt_err_t hpm_usb_control(rt_device_t dev, int cmd, void *args); + +rt_uint8_t usb_dev_addr; + +static struct rt_device hpm_usb = { + .read = hpm_usb_read, + .write = hpm_usb_write, + .control = hpm_usb_control, +}; + +static bool usb_disk_wait_for_complete(uint8_t usb_addr) +{ + #if CFG_TUSB_OS != OPT_OS_NONE + int32_t retry_cnt = 200; + #else + int32_t retry_cnt = 5000000; + #endif + + while (!tuh_msc_idle(usb_addr) && retry_cnt--) + { + #if CFG_TUSB_OS != OPT_OS_NONE + osal_task_delay(5); + #else + tuh_task(); + #endif + } + + return retry_cnt > 0 ? true : false; +} + +void hpm_usb_set_addr(uint8_t dev_addr) +{ + usb_dev_addr = dev_addr; +} + +static rt_size_t hpm_usb_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_bool_t result; + + result = tuh_msc_read10(usb_dev_addr, LUN_USB, buffer, pos, size, NULL); + + if (result) { + result = usb_disk_wait_for_complete(usb_dev_addr); + } + + return result ? size : 0; +} + +static rt_size_t hpm_usb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + bool result; + + result = tuh_msc_write10(usb_dev_addr, LUN_USB, buffer, pos, size, NULL); + + if (result) { + result = usb_disk_wait_for_complete(usb_dev_addr); + } + + return result ? size : 0; +} + +rt_err_t hpm_usb_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t ret = RT_EOK; + + switch (cmd) + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + struct rt_device_blk_geometry *geometry = (struct rt_device_blk_geometry *)args; + geometry->sector_count = tuh_msc_get_block_count(usb_dev_addr, LUN_USB); + geometry->bytes_per_sector = tuh_msc_get_block_size(usb_dev_addr, LUN_USB); + break; + case RT_DEVICE_CTRL_BLK_SYNC: + break; + case RT_DEVICE_CTRL_BLK_ERASE: + break; + + default: + ret = RT_EINVAL; + break; + } + + return RT_EOK; +} + +int rt_hw_usb_init(void) +{ + rt_err_t err = RT_EOK; + + hpm_usb.type = RT_Device_Class_Block; + + err = rt_device_register(&hpm_usb, "usb0", RT_DEVICE_FLAG_RDWR); + + if (err != RT_EOK) { + LOG_E("rt device %s failed, status=%d\n", "usb", err); + return err; + } + + return err; +} + +INIT_BOARD_EXPORT(rt_hw_usb_init); + diff --git a/bsp/hpmicro/libraries/drivers/drv_usb.h b/bsp/hpmicro/libraries/drivers/drv_usb.h new file mode 100644 index 0000000000..dea46136af --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_usb.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRV_USB_H +#define DRV_USB_H + + +int rt_hw_usb_init(void); + +#endif diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.c b/bsp/hpmicro/libraries/drivers/drv_wdt.c new file mode 100644 index 0000000000..5b21102680 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.c @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include +#include "board.h" +#include "drv_wdt.h" +#include "hpm_wdg_drv.h" +#include "hpm_sysctl_drv.h" + + +#ifdef BSP_USING_WDG + + +typedef struct hpm_wdog +{ + WDG_Type *wdog_base; + char *device_name; + clock_name_t clock_name; + uint32_t irq_num; + rt_watchdog_t *wdog; +}hpm_wdog_t; + +static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt); +static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag); +static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt); +static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt); +static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args); + +static void hpm_wdog_isr(rt_watchdog_t *wdt); + +static wdg_control_t wdog_ctrl = { + .reset_interval = reset_interval_clock_period_mult_16k, + .interrupt_interval = interrupt_interval_clock_period_multi_8k, + .reset_enable = true, + .interrupt_enable = false, + .clksrc = wdg_clksrc_extclk, + .wdg_enable = false, +}; + +#if defined(BSP_USING_WDG0) +rt_watchdog_t wdog0; +void wdog0_isr(void) +{ + hpm_wdog_isr(&wdog0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_WDOG0, wdog0_isr) +#endif + +#if defined(BSP_USING_WDG1) +rt_watchdog_t wdog1; +void wdog1_isr(void) +{ + hpm_wdog_isr(&wdog1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_WDOG1, wdog1_isr) +#endif + +#if defined(BSP_USING_WDG2) +rt_watchdog_t wdog2; +void wdog2_isr(void) +{ + hpm_wdog_isr(&wdog2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_WDOG2, wdog2_isr) +#endif + +#if defined(BSP_USING_WDG3) +rt_watchdog_t wdog3; +void wdog3_isr(void) +{ + hpm_wdog_isr(&wdog3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_WDOG3, wdog3_isr) +#endif + +static hpm_wdog_t wdogs[] = { +#ifdef BSP_USING_WDG0 + { + .wdog_base = HPM_WDG0, + .device_name = "wdt0", + .clock_name = clock_watchdog0, + .irq_num = IRQn_WDG0, + .wdog = &wdog0, + }, +#endif + +#ifdef BSP_USING_WDG1 + { + .wdog_base = HPM_WDG1, + .device_name = "wdt1", + .clock_name = clock_watchdog1, + .irq_num = IRQn_WDG1, + .wdog = &wdog1, + }, +#endif + +#ifdef BSP_USING_WDG2 + { + .wdog_base = HPM_WDG2, + .device_name = "wdt2", + .clock_name = clock_watchdog2, + .irq_num = IRQn_WDG2, + .wdog = &wdog2, + }, +#endif + +#ifdef BSP_USING_WDG3 + { + .wdog_name = HPM_WDG3, + .device_name = "wdt3", + .clock_name = clock_watchdog3, + .irq_num = IRQn_WDG3, + .wdog = &wdog3, + }, +#endif +}; + +static struct rt_watchdog_ops hpm_wdog_ops = { + .init = hpm_wdog_init, + .control = hpm_wdog_control, +}; + +static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + WDG_Type *base = hpm_wdog->wdog_base; + + wdg_init(base, &wdog_ctrl); + + return RT_EOK; +} + +static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + WDG_Type *base = hpm_wdog->wdog_base; + + rt_enter_critical(); + wdg_enable(base); + rt_exit_critical(); +} + +static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + WDG_Type *base = hpm_wdog->wdog_base; + + rt_enter_critical(); + wdg_disable(base); + rt_exit_critical(); + + return RT_EOK; +} + +static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + WDG_Type *base = hpm_wdog->wdog_base; + + rt_enter_critical(); + wdg_restart(base); + rt_exit_critical(); + + return RT_EOK; +} + +static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) +{ + rt_err_t ret = RT_EOK; + + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + WDG_Type *base = hpm_wdog->wdog_base; + + uint32_t temp; + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + temp = wdg_get_total_reset_interval_in_us(base, WDG_EXT_CLK_FREQ); + temp /= 1000000UL; /* Convert to seconds */ + *(uint32_t *)args = temp; + break; + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + RT_ASSERT(*(uint32_t *)args != 0); + temp = *(uint32_t *)args; + temp *= 1000000U; /* Convert to microseconds */ + wdog_ctrl.interrupt_interval = wdg_convert_interrupt_interval_from_us(WDG_EXT_CLK_FREQ, temp); + wdog_ctrl.reset_interval = reset_interval_clock_period_mult_128; + wdog_ctrl.reset_enable = true; + wdog_ctrl.interrupt_enable = true; + wdog_ctrl.clksrc = wdg_clksrc_extclk; + wdog_ctrl.wdg_enable = false; + hpm_wdog_init(wdt); + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + hpm_wdog_refresh(wdt); + break; + case RT_DEVICE_CTRL_WDT_START: + hpm_wdog_open(wdt, *(uint16_t*)args); + break; + case RT_DEVICE_CTRL_WDT_STOP: + hpm_wdog_close(wdt); + break; + default: + ret = RT_EINVAL; + break; + } + + return RT_EOK; +} + +void hpm_wdog_isr(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + WDG_Type *base = hpm_wdog->wdog_base; + + uint32_t status = wdg_get_status(base); + + if (IS_HPM_BITMASK_SET(status, WDG_ST_INTEXPIRED_MASK)) { + wdg_clear_status(base, WDG_ST_INTEXPIRED_MASK); + } +} + +int rt_hw_wdt_init(void) +{ + rt_err_t err = RT_EOK; + +#if defined(BSP_USING_WDG) + for (uint32_t i = 0; i < sizeof(wdogs) / sizeof(wdogs[0]); i++) + { + wdogs[i].wdog->ops = &hpm_wdog_ops; + clock_add_to_group(wdogs[i].clock_name, 0); + err = rt_hw_watchdog_register(wdogs[i].wdog, wdogs[i].device_name, RT_DEVICE_FLAG_RDWR, (void *)&wdogs[i]); + if (err != RT_EOK) + { + LOG_E("rt device %s failed, status=%d\n", wdogs[i].device_name, err); + } + } +#endif + return err; +} + +INIT_BOARD_EXPORT(rt_hw_wdt_init); +#endif /* RT_USING_WDT */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.h b/bsp/hpmicro/libraries/drivers/drv_wdt.h new file mode 100644 index 0000000000..4c42938700 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRV_WDT_H +#define DRV_WDT_H + + +int rt_hw_wdt_init(void); + +#endif \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md b/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md new file mode 100644 index 0000000000..0c5e5cdb4c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md @@ -0,0 +1,343 @@ +# Change Log + +## [0.13.1] - 2022-08-23: + +Main changes since 0.13.0 + +### Changed: + - Driver:I2S: update i2s drivers + - middleware: lwip: optimize variable_name definition + - samples: lwip: lwip_iperf: update readme files + - samples: lwip: common: arch: add LWIP_MEM_SECTION declartion + +### Fixed: + - samples: multicore: BOOT_HEADER was missing in multicore core0 example + - samples: jpeg: Fix encoding and decoding problem + - samples: audio codec: wav decoder: fix 32bit wave file playback + - I2S_DMA: fix wav channel not align problem + - i2s_interrupt: fix I2S FIFO overflow + - fix lack of interrupt claim for swi + - driver: watchdog: overflow + - Fix critical section logic issue in dma manager + - Fix the core1 application debugging issue + +## [0.13.0] - 2022-07-31: + +Main changes since 0.12.1 + +### Changed: + - drivers: adc: fix sequence and preemption mode + - drivers: usb: automatically change transceiver type in host mode + - drivers: pwm: modify the interface for setting the pwm shadow register trigger function + - drivers: sdxc: driver improvement + - samples: jpeg demo update + - samples: motor_ctrl: Optimize motor control performance + - samples: motor_ctrl: Modify the pwm update method to be hardware triggered + - samples: audio_codec: wav: Modify the interface + - samples: audio_codec: add dao support + - samples: tinyusb: update all USB project names + - samples: adc: place DMA buffer in noncacheable + - components: usb: update two struct definitions for the hcd_data_t and the dcd_data_t + - middleware: littlevgl: update double buffer refresh approach. + - middleware: fatfs: enable exfat format + - middleware: fatfs: change 'USB' to lowercase + - middleware: hpm_math: remove cache operations from the ffa interface + - scripts: ses: update file path using $(HPM_SDK_BASE) + +### Fixed: + - drivers: gpiom: fix spelling errors in API names + - drivers: enet: fix ptp time offset update + - drivers: cam: fix store mode configuration + - drivers: can: Fix the issue can timestamp cannot be enabled + - drivers: gpio: incorrect return type gpio_get_port_interrupt_flags. + - middleware: audio_codec: decoder_wav: fix wav codec problem + - middleware: tinyusb: fix the alignment of _hcd_data + - soc: driver: clock: i2s get clock error + - soc: hpm_misc.h: fix incorrect system address mapping. + - soc: SVD files: fix SDP peripheral reset value problem + - soc: disable vector mode explicitly. + - boards: correct device name in ses project + - board: correct the printf format for frequency and register base + - python: fix ses project generation on windows + - samples: adc: fix not working in sequence mode and preemption mode + - ses: set obj path for common configuration. + - cmake: ses: put app source into separate category in ses. + +### Added: + - components: enet_phy: add rtl8211 driver + - components: hpm_spi: add initial SPI component + - components: add DMA Manager + - drivers: cam: add new API + - drivers: uart: add uart_set_baudrate API + - drivers: spi: update dma transfer API + - samples: tinyusb: host: add a hid demo + - samples: drivers: spi: add master_trans_large_amount_of_data example + - samples: decoder_wav: Add support for different bit rates and bits + - samples: drivers: audio: automatic acquisition of i2s clock frequency + - middleware: tinyusb: update portable file for USB host + +## [0.12.1] - 2022-07-01: + +Main changes since 0.12.0 + +### Fixed: + - update lwipopt.h for updated enet driver + +## [0.12.0] - 2022-06-30: + +Tested with SES 6.32 + +Main changes since 0.11.0 + +### Changed: + - boards: hpm6360evk has been renamed to hpm6300evk + - boards: Use CSR_CYCLE in the clock_delay function + - soc: hpm_soc.h: include hpm_common.h + - driver: rename hpm_pmu_drv.c to hpm_pcfg_drv.h + - driver: spi: change to non-blocking interfaces + - driver: dma: update driver to adapt to different DMA instance constraints + - components: enet_phy: update dp83867 driver + - components: enet_phy: remove rtl8211 driver + - cmake: enable nano newlib by default + - cmake: move distclean to the beginning + - middleware: littlevgl enable PDMA by default + - middleware: tinyusb: upgrade to 0.13.0 + - samples: tinyusb: device: cdc_msc: adjust buffer size + - samples: drivers: plic: use gpio toggle count as nested irq + +### Fixed: + - drivers: pwm: fix function name inconsistency bug + - drivers: enet: remove "board.h" in enet driver + - drivers: clock: Fix bugs in hpm6360 clock driver + - drivers: clock: returns wrong adc/dac clock in HPM6360 + - drivers: dram: failed to configure 8bit mode. + - freertos: fix issue about running on core1 + - boards: hpm6300evk pmp_entry set initial value + - middleware: littlevgl: fix pdma cache op issue + - middleware: littlevgl: fix doxygen markdown for pdma driver + - middleware: lvgl: ses: update ram linker. + - middleware: hpm_math: fix ffa cache size error + - samples: audio_codec: remove the wrong dependency + - samples: FATFS demo cannot support write/read if FATFS passes unaligned buffer address + +### Added: + - samples: add memstress and flash stress + - drivers: clock: add implement common delay function based on mcycle and mcycleh register + - boards: add hpm6300evk support + - boards: hpm6750evkmini: motor control support + - soc: add svd files + - middleware: lwip: iperf: enable iperf and add udp function + - samples: lwip: add lwip_iperf + +## [0.11.0] - 2022-05-31: +Main changes since 0.10.0-hpm6360-er + +### Changed: + - readme: change the location of the starting document + - components: change hal_adc_xx to hpm_adc_xx + - drivers: update the I2C driver + - cmake: change default rv_arch to rv32imac + - cmake: modified in a zephyr-compatible way + - drivers: uart: redefined struct with zephyr + - cmake: change soc and board name + - cmake: ses: support enable ext_dsp in project file. + - samples/tinyusb/host: optimize the toggle rate of the blinking led + - samples/tinyusb/device: replace mchtimer with board_timer for led_linking_taskk + - samples/tinyusb/device: optimize the implement of led_blinking_task + - soc: update IP header and soc header files + +### Fixed: + - samples: motor_ctrl: bldc_block: fix some error + - middleware: hpm_math: fix andes toolchain compile error + - middleware: hpm_math: fix libdsp.a error + - middleware: hpm_math: add ext-dsp for SES + - samples: openocd_algo: fix func_table placement. + - boards: hpm6360evk: correct cpu frequency + - boards: fix warning caused by code irregularities + - boards: LED status is not the same between hpm6750mini rev-A and rev-B + - boards: update board_led_write. + +## Added: + - driver: add spi_setup_dma_transfer() API + - middleware: hpm_math: add software fft function + - middleware: hpm_math: add ffa to hpm_math + - samples: i2c: update the sample b2b + - samples: hpm_math: add fft_performance demo + - samples: add SPI DMA sample + - samples: multicore coremark using debug console only + - samples: 1588: add ptp v1 master/slave + +## [0.10.0_hpm6300] - 2022-05-16: +Main changes since 0.10.0 + +### Changed: + - ip register header file update + - ses_proj: using generated complete cpu_regs_xml to replace general cpu registers xml + - drivers: gpiom: move gpiom_gpio_t into hpm_gpiom_src.h + - drivers: update the enet driver + - samples: dram: change sdram test address in dma demo + - samples: drivers: mbx: exclude flash targets for core0 as well. + - samples: lwip: update ethernetif.c + +### Fixed: + - drivers: ptpc: update ptpc_init_timer_with_initial. + - drivers: can: bug fix and update + - soc: correct vector table inclusion and swi name + - env.sh: fix HPM_SDK_BASE setting problem with msys. + - samples: sha256_example: failed to run case 13 and 14 with gcc. + +### Added: + - soc: add HPM6360 support + - drivers: add ffa, pllctlv2, dac + - boards: add hpm6360evk support + - components: add adcx module + - components/enet_phy: add the RTL8201 driver + - samples: drivers: dac, ffa + - samples: rgb_red: add evkmini ver B support + +## [0.10.0] - 2022-04-30: +Main changes since 0.9.0 + +### Changed: + - drivers: gptmr: split irq enable/disable interface + - drivers: can: 155 Update SJW setting in CAN driver + - soc: HPM6750: rename safe stack symbol in link script + - components: debug_console: wait uart tx flag on writing. + +### Added: + - drivers: enet: add 1588 support + - drivers: can: Add TDC support + - drivers: mchtmr: add counter init API. + - drivers: dma: add dma_disable_channel() API + - middleware: add wav decoder + - samples: lwip: add ptp demos + - samples: tinyusb: add msc, cdc demo + - samples: audio_codec: add wav player demo + - samples: add tinyuf2 initial support + - samples: add initial uart dma rx idle demo + +### Fixed: + - soc: HPM6750: sysctl: fix cpu lp mode API. + - drivers: uart: correct baudrate calculation. + - drivers: usb: fix: no response in device mode when a USB cable is pluged out + - boards: correct the pin setting related to USB + +## [0.9.0] - 2022-04-01: +Main changes since 0.8.0 + +### Changed: + - drivers: update WDG, UART, DMA, DMAMUX driver + - drivers: enet remove enet_intf_selection + - drivers: can: support configure bit timing via low-level bit timing parameters + - drivers: optimize gpio driver + - samples: exclude flash targets for mbx core1 + - samples: adjust SES project setting for coremark + - samples: jpeg: update and integration jpeg decode samples + - ses: use relpath for linker script in project file + - ses: add HPM device name in generated project file + - soc: HPM6750: add an interface selection api + +### Added: + - soc: HPM6750: add ram linker for core1 + - ses: support to use Andes toolchain + - middleware: add hpm_math (replacing hpm_dsp) + - samples: add lwip httpd + - drivers: add section and alignment general instructions in hpm_common.h + +### Fixed: + - boards: hpm6750evk: fix bldc adc pinmux error + - boards : hpm6750evk : pinmux : fix spi init pins error + - samples: sdp: fix non-cacheable data initialization issue + - samples: littlevgl: fix wrong picture patch in README + +## [0.8.0] - 2022-03-04: +All changes since 0.7.3 + +### Changed: + - rename middleware/sdmmc to middleware/hpm_sdmmc + - place isr into .isr_vector section for irq non-vector mode + - change csr functions to support llvm + +### Fixed: + - ses: fix issue in register xml + - freertor: fix trap handler at non-vector mode + - sdxc: fix software reset issue + +### Added: + - add sdk doc + - add more sample doc + - add multicore demo + - i2c/uart: add dma support + - add tensorflow lite for microcontroller + +## [0.7.3] - 2022-02-23: +All changes since 0.7.2 + +### Changed: + - freertos: change exception handling + +## [0.7.2] - 2022-02-21: +All changes since 0.7.1 + +### Changed: + - freertos: change freertos irq stack definition, passed in CMakeLists.txt, defined in linker + - soc: hpm6750: add DISABLE_IRQ_PREEMPTIVE to check if it needs to enable irq preemption + +### Fixed: + - freertos: disable irq preemption + +## [0.7.1] - 2022-02-13: + +All changes since 0.7.0 + +### Changed: + - drivers: adc12: update adc12_prd_config_t + - samples: can: update case with interrupt and communication between two boards + +### Fixed: + - drivers: can: fix blocking transcation issue + - samples: mbx: support run this example in SES + - SES: startup: add fpu enable if abi is set to enable hw fp + +### Added: + - samples: multicore: add flash based multicore example + - drivers: can: add apis to recvieve message for non-blocking use + +## [0.7.0] - 2022-01-30: + +All changes since 0.6.2 + +### Changed: + - update default CPU frequency to 816MHz from 648MHz + - update the ip headers + - drivers: gpio: replace gpio_XXX_pins with gpio_XXX_port + - drivers: gpio: remove pin level enum definition + - drivers: i2s: driver update to remove mclk_div + - drivers: ptpc: update driver + - drivers: common: update get first set bit API + - drivers: uart: split one enable with parameter into enable and disable interfaces + - drivers: pwm: change name of output_channel config API + - drivers: trgm: split separate API to enable/disable io output + - soc: HPM6750: initialize noncacheable data in startup + - soc: HPM6750: l1c: update fence.i call + - samples: hello_world: add LED flashing + - samples: littlevgl: remove lvgl example + +### Fixed: + - hpm6750evkmini: correct refresh cycle number of sdram + - hpm6750evkmini: Fix the SDRAM memory range issue in flash_sdram_xip linker file + - SES: remove no_relax option for linker, since segger has provide a patch to its ld for ses v6.10. + - drivers: gpio: fix read pin issue: + - drivers: usb: fix usb disconnection under linux environment + - drivers: sdxc: Fixed the compatibility issue on different SD/eMMC cards in the sdcard_fatfs demo + - drivers: gptmr: incorrect DMAEN configuration condition + - drivers: gptmr: clear CNTRST bit after set. + - SDK_DECLARE_EXT_ISR_M cannot work in the c++ file + - FreeRTOS: fix ISR_STACK setting + - components: touch: gt911: fix gpio write pin call + +### Added: + - SEG: add register definition file in generated embedded studio project + - samples: drivers: gpiom: Add example to demonstrate gpiom's function + - drivers: common: add macro to put data into noncacheable sections + - middleware: integrate lwip diff --git a/bsp/hpmicro/libraries/hpm_sdk/LICENSE b/bsp/hpmicro/libraries/hpm_sdk/LICENSE new file mode 100644 index 0000000000..d5c5c0ac62 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/LICENSE @@ -0,0 +1,31 @@ +BSD 3-Clause "New" or "Revised" License +https://spdx.org/licenses/BSD-3-Clause.html + +Copyright (c) 2021-2022, HPMicro. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation +and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + diff --git a/bsp/hpmicro/libraries/hpm_sdk/README.md b/bsp/hpmicro/libraries/hpm_sdk/README.md new file mode 100644 index 0000000000..886e6b489e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/README.md @@ -0,0 +1,250 @@ +# HPM SDK Overview +The HPM SDK Project is a software development kit based on HPMicro's MCUs, which supports a wide range of MCUs, based on the BSD license, including drivers, middleware and RTOS, such as littlevgl/ lwIP/ TinyUSB/ FreeRTOS, etc. It supports a large number of Boards. + +# HPM SDK Quick Start Guide + +## Minium required version of dependencies are: + + | Name | Version | + | -------|---------- | + |CMake | 3.13 | + | Python | 3.8 | + +## Install Dependencies + - Ubuntu + - install tools + + ```shell + sudo apt install build-essential cmake ninja-build libc6-i386 libc6-i386-cross libstdc++6-i386-cross + ``` + - install python3 (3.8.5 minimum) and pip + + ```shell + sudo apt install python3 python3-pip + ``` + + - Windows + - Windows Command Prompt + The following commands assume you are using cmd.exe, it might differ if you are using PowerShell. + - Install Chocolatey (https://chocolatey.org/) + It is a package manager for Windows, with which it's not that difficult to install native Windows dependencies. + 1. Install Chocolatey by the following instructions on the Chocolatey Install (https://chocolatey.org/install) page. + 2. Open "cmd.exe" as "Administrator" + 3. Disable global confirmation to avoid having to confirm installation of individual programs: + + ```Batchfile + choco feature enable -n allowGlobalConfirmation + ``` + + 4. Install CMake + + ```Batchfile + choco install cmake --installargs 'ADD_CMAKE_TO_PATH=System' + ``` + 5. Install other tools: + + ```Batchfile + choco install git python ninja + ``` + 6. Close the Administrator command prompt window. + +- Prepare Toolchain & Environment Variables + - Supported toolchains: + - gnu-gcc <-- default toolchain + - nds-gcc + - Toolchain setup: + - gnu-gcc: + 1. Grab a copy of toolchain zip package and unzip to certain path, take TOOLCHAIN_PATH for example, (riscv32-unknown-elf-gcc is supposed to be found in TOOLCHAIN_PATH/bin) + 2. Declare a system environment variable of "GNURISCV_TOOLCHAIN_PATH" to the path of toolchain: + - Linux, taking zsh for example (replace TOOLCHAIN_PATH with the path of toolchain on your workstation): + ```shell + export GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH + export HPM_SDK_TOOLCHAIN_VARIANT= + ``` + - Windows command prompt: + ```Batchfile + set GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH + set HPM_SDK_TOOLCHAIN_VARIANT= + ``` + - nds-gcc: + 1. Grab a copy of toolchain zip package and unzip to certain path, take TOOLCHAIN_PATH for example, (riscv32-elf-gcc is supposed to be found in TOOLCHAIN_PATH/bin) + 2. Declare two system environment variables: "GNURISCV_TOOLCHAIN_PATH" to the path of toolchain; "HPM_SDK_TOOLCHAIN_VARIANT" to "nds-gcc": + - Linux, taking zsh for example (replace TOOLCHAIN_PATH with the path of toolchain on your workstation): + ```shell + export GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH + export HPM_SDK_TOOLCHAIN_VARIANT=nds-gcc + ``` + - Windows command prompt: + ```Batchfile + set GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH + set HPM_SDK_TOOLCHAIN_VARIANT=nds-gcc + ``` + Note: For windows, Andes compiler needs following libraries: + - cygwin1.dll + - cygncursesw-10.dll + make sure its path is appended to the system environment variable "PATH". + - Environment Variables: + - Using provided scripts to set the environment variable: + - Linux: + ```shell + $ source env.sh + ``` + - Windows command prompt: + ```Batchfile + env.cmd + ``` + - Manually declare a environment variable of "HPM_SDK_BASE" to the path of SDK root: + - Linux, taking zsh for example (assume SDK is located at $HOME/hpm_sdk): + ```shell + export HPM_SDK_BASE=$HOME/hpm_sdk + ``` + - Windows command prompt (assume SDK is located at c:\hpm_sdk): + ```Batchfile + set HPM_SDK_BASE=c:\hpm_sdk + ``` + +- Install python dependencies + - Linux: + ```shell + pip3 install --user -r "$HPM_SDK_BASE/scripts/requirements.txt" + ``` + + - Window (by default, python3/pip3 is not available after Python 3.x installed on Windows, but only python/pip): + + ```Batchfile + pip install --user -r "%HPM_SDK_BASE%/scripts/requirements.txt" + ``` + +- Build An Application with GNU GCC toolchain + On finishing the steps mentioned above, SDK projects can be generated and built. + The following steps describe how a demo can be built: + 1. Go to application directory, taking hello_world for example: + + ```shell + cd samples/hello_world + ``` + + 2. create a directory for build + - Linux: + + ```shell + mkdir build + ``` + + - Windows: + + ```Batchfile + md build + ``` + + 3. Change directory to "build" + + ```Batchfile + cd build + ``` + + 4. Generate build files for Ninja: + ```shell + cmake -GNinja -DBOARD=hpm6750evk .. + ``` + Note: if it complains about "CMAKE_MAKE_PROGRAM is not set", please + append -DCMAKE_MAKE_PROGRAM=YOUR_MAKE_EXECUTABLE_PATH to the previous + command (NINJA_PATH is the folder in which ninja can be found): + + ```shell + cmake -GNinja -DBOARD=hpm6750evk -DCMAKE_MAKE_PROGRAM=NINJA_PATH/ninja .. + ``` + + 5. Building: + + ```shell + ninja + ``` + + When it's done the elf and other application related files can be found in the directory of "output", like map file, assembly source or binary file + +- Quick Guide to Run/Debug An Application (hello_world): + 1. Wire up the board, including debug probe (by default it supports jlink) and serial port + 2. power up the board + 3. open console connecting to the debug console (target serial port) with baudrate of 115200 + 4. get a copy of openocd. it can be installed via package management system or downloaded from sourceforge or github. But please make sure its revision is > 0.11 + 5. Go to SDK root directory, run provided environment variable scripts: + - Linux: + ```shell + $ source env.sh + ``` + + - Windows command prompt: + ```Batchfile + env.cmd + ``` + or setup environment variable OPENOCD_SCRIPTS manually: + + - Linux: + ``` shell + $ export OPENOCD_SCRIPTS=${HPM_SDK_BASE}/boards/openocd + ``` + + - Windows: + ``` + set OPENOCD_SCRIPTS=%HPM_SDK_BASE%\boards\openocd + ``` + + 6. Start openocd with several configuration files in order of type of probe, type of core, type of board. For example, the following command will setup an openocd gdb server with ft2232 to single core on hpm6750evk + + ```shell + openocd -f probes/ft2232.cfg -f soc/hpm6750-single-core.cfg -f boards/hpm6750evk.cfg + ``` + Note: If using FTDI debugger and meet `Error: libusb_open() failed with LIBUSB_ERROR_NOT_FOUND` , please check the FTDI usb driver. If it is not installed correctly, use [zadig](https://github.com/pbatard/libwdi/releases/download/b730/zadig-2.5.exe) to update: + + Open zadig, click Options-> List All Devices. + + ![List All Devices](doc/images/readme/zadig_list_all_devices.png) + + Select Dual RS232-HS (Interface 0). + + ![Select Dual RS232-HS (Interface 0)](doc/images/readme/zadig_select_dual_rs232-hs.png) + + Then click Install Driver or Replace Driver. + + ![Replace Driver](doc/images/readme/zadig_replace_driver.png) + + 7. Go to hello_world directory + + ```shell + cd samples/hello_world + ``` + + 8. open up another terminal to start a gdb client + - gnu-gcc: + + ```shell + TOOLCHAIN_PATH/bin/riscv32-unknown-elf-gdb + ``` + + - nds-gcc: + + ```shell + TOOLCHAIN_PATH/bin/riscv32-elf-gdb + ``` + + 9. connect gdb client to the gdbserver started by openocd, (by default, gdbserver port is 3333) + + ```GDB + gdb> file build/output/hello_world.elf + gdb> target remote localhost:3333 + gdb> load + gdb> b main + gdb> c + ``` + + 10. on the debug console, "hello_world" is printed. + +- Build An Application with Segger Embedded Studio + - Segger Embedded Studio for RISC-V can be downloaded from https://www.segger.com/downloads/embedded-studio/ + - Project file for Segger Embedded Studio will be generated while generating build files for Ninja mentioned in "Build An Application with GNU GCC toolchain"->"4. Generate build files for Ninja" + - The project file (.emProject) can be found at build/segger_embedded_studio/. + + Note: openocd executable needs to be found in the PATH variable of current console, otherwise debug configuration will not be generated to project file and needs to be configured manually in Segger Embedded Studio later. + +# Community Support diff --git a/bsp/hpmicro/libraries/hpm_sdk/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/README_zh.md new file mode 100644 index 0000000000..2390421427 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/README_zh.md @@ -0,0 +1,258 @@ +# HPM SDK 概述 +HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多种MCU。基于BSD许可证，包含了底层驱动，中间件和RTOS，例如littlevgl/ lwIP/ TinyUSB/ FreeRTOS等，支持大量评估板。 + +# HPM SDK使用说明 + +## 依赖软件最低版本要求 + +| 软件名称 | 版本号 | +|--- | --- | +| CMake | 3.13 | +| Python | 3.8 | + +## 安装依赖 + +- Ubuntu: + - 安装工具: + +```shell + sudo apt install build-essential cmake ninja-build libc6-i386 libc6-i386-cross libstdc++6-i386-cross +``` + + - 安装python3 (3.8.5 minimum) 与pip: + +```shell + sudo apt install python3 python3-pip +``` + +- Windows: + - Windows命令行: + 以下所使用的命令都以Windows命令行(cmd.exe)为例: + - 安装 Chocolatey (): + 该工具为Windows下的包管理软件,通过该工具可以方便地在Windows平台上安装依赖软件: + 1. 根据Chocolatey官方步骤进行安装() + 2. 以管理员身份打开"cmd.exe" + 3. 禁用全局安装确认: + + ```Batchfile + choco feature enable -n allowGlobalConfirmation + ``` + + 4. 安装CMake: + + ```Batchfile + choco install cmake --installargs 'ADD_CMAKE_TO_PATH=System' + ``` + + 5. 安装其他工具: + + ```Batchfile + choco install git python ninja + ``` + + 6. 关闭该命令行窗口 + +## 准备工具链与环境变量配置 + +- 支持的工具链: + - gnu-gcc <-- 缺省工具链 + - nds-gcc +- 工具链: + - gnu-gcc: + - 下载工具链压缩包,并解压.假定TOOLCHAIN_PATH作为工具链的解压目录(需要满足在TOOLCHAIN_PATH\bin下可以找到riscv32-unknown-elf-gcc) + - 申明系统环境变量"GNURISCV_TOOLCHAIN_PATH"指向工具链路径: + - Linux, 以zsh为例(确保将TOOLCHAIN_PATH替换成你自己的路径): + ```shell + export GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH + export HPM_SDK_TOOLCHAIN_VARIANT= + ``` + - Windows命令行: + ```Batchfile + set GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH + set HPM_SDK_TOOLCHAIN_VARIANT= + ``` + - nds-gcc: + - 下载工具链压缩包,并解压.假定TOOLCHAIN_PATH作为工具链的解压目录(需要满足在TOOLCHAIN_PATH\bin下可以找到riscv32-elf-gcc) + - 申明系统环境变量"GNURISCV_TOOLCHAIN_PATH"指向工具链路径: + - Linux, 以zsh为例(确保将TOOLCHAIN_PATH替换成你自己的路径): + ```shell + export GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH + export HPM_SDK_TOOLCHAIN_VARIANT=nds-gcc + ``` + - Windows命令行: + ```Batchfile + set GNURISCV_TOOLCHAIN_PATH=TOOLCHAIN_PATH + set HPM_SDK_TOOLCHAIN_VARIANT=nds-gcc + ``` + Note: Windows平台上Andes toolchain需要以下cygwin库文件: + - cygwin1.dll + - cygncursesw-10.dll + 务必确保以上库文件所在目录被包含在系统环境变量PATH中 + +- SDK编译所需环境变量设置: + - 通过运行提供的脚本执行: + - Linux: + + ```shell + source env.sh + ``` + + - Windows 命令行: + + ```Batchfile + env.cmd + ``` + + - 手工设置环境变量"HPM_SDK_BASE"指向SDK根目录: + - Linux, 以zsh为例(假定$HOME/hpm_sdk为SDK根目录): + + ```shell + export HPM_SDK_BASE=$HOME/hpm_sdk + ``` + + - Windows 命令行(假定c:\hpm_sdk为SDK根目录): + ```Batchfile + set HPM_SDK_BASE=c:\hpm_sdk + ``` + +- 安装Python依赖包: + - Linux: + + ```shell + pip3 install --user -r "$HPM_SDK_BASE/scripts/requirements.txt" + ``` + + - Window (Windows平台上Python 3.x 安装之后无法找到 python3/pip3, 只有python/pip): + ```Batchfile + pip install --user -r "%HPM_SDK_BASE%/scripts/requirements.txt" + ``` + +- 使用GNU GCC工具链编译示例应用: + 做完尚书步骤之后, 就可以构建编译SDK示例工程. 以下步骤描述了如何编译hello_world: + 1. 切换到示例应用目录: + + ```shell + cd samples/hello_world + ``` + + 2. 创建build目录: + - Linux: + + ```shell + mkdir build + ``` + + - Windows: + + ```Batchfile + md build + ``` + + 3. 切换目录到"build" + + ```shell + cd build + ``` + + 4. 为Ninja-build产生构建文件: + + ```shell + cmake -GNinja -DBOARD=hpm6750evk .. + ``` + + Note: 如果提示"CMAKE_MAKE_PROGRAM is not set", 可以通过在以上命令中追加"-DCMAKE_MAKE_PROGRAM=YOUR_MAKE_EXECUTABLE_PATH" (NINJA_PATH为ninja-build的目录,在其下可以找到ninja): + # cmake -GNinja -DBOARD=hpm6750evk -DCMAKE_MAKE_PROGRAM=NINJA_PATH/ninja .. + + 5. 编译: + + ```shell + ninja + ``` + + 当编译完成后,生成的elf以及对应的其他文件可以在output目录中找到. + +- 运行/调试示例程序说明(hello_world): + 1. 完成评估板连线,包括调试器,串口线以及电源线 + 2. 打开电源 + 3. 打开串口软件,设置baudrate为115200 + 4. 安装openocd(0.11以上) + 5. 切换至SDK根目录, 运行设置环境变量脚本: + - Linux: + + ```shell + $ source env.sh + ``` + - Windows command prompt: + + ```Batchfile + env.cmd + ``` + 或者手动设置名为OPENOCD_SCRIPTS的环境变量: + - Linux: + ``` shell + $ export OPENOCD_SCRIPTS=${HPM_SDK_BASE}/boards/openocd + + ``` + - Windows: + ``` + set OPENOCD_SCRIPTS=%HPM_SDK_BASE%\boards\openocd + ``` + + 6. 运行openocd, 需要按顺序指定配置文件: 调试器配置, 内核配置, 目标板配置。例如，通过ft2232在hpm6750evk上进行单核调试，可以运行如下命令: + + ```shell + openocd -f probes/ft2232.cfg -f soc/hpm6750-single-core.cfg -f boards/hpm6750evk.cfg + ``` + + Note: 如果使用FTDI调试器并遇到提示`Error: libusb_open() failed with LIBUSB_ERROR_NOT_FOUND` , 请检查FTDI usb驱动。如果驱动未正确安装，使用 [zadig](https://github.com/pbatard/libwdi/releases/download/b730/zadig-2.5.exe) 更新驱动： + + 打开zadig，点击 Options->List All Devices. + + ![List All Devices](doc/images/readme/zadig_list_all_devices.png) + + 选择 Dual RS232-HS (Interface 0). + + ![Select Dual RS232-HS (Interface 0)](doc/images/readme/zadig_select_dual_rs232-hs.png) + + 然后点击 Install Driver 或 Replace Driver. + + ![Replace Driver](doc/images/readme/zadig_replace_driver.png) + + 7. 切换到hello_world目录 + + ```shell + cd samples/hello_world + ``` + + 8. 打开另一个终端,启动GDB client: + - gnu-gcc: + + ```shell + TOOLCHAIN_PATH/bin/riscv32-unknown-elf-gdb + ``` + + - nds-gcc: + + ```shell + TOOLCHAIN_PATH/bin/riscv32-elf-gdb + ``` + + 9. 连接GDB client到openocd GDB server (缺省状态下, openocd gdbserver 端口为 3333) + + ```GDB + gdb> file build/output/hello_world.elf + gdb> target remote localhost:3333 + gdb> load + gdb> b main + gdb> c + ``` + 10. 顺利运行后可以在串口终端上打印"hello_world". + +- 使用Segger Embedded Studio for RISC-V编译应用 + - Segger Embedded Studio for RISC-V 可以从 https://www.segger.com/downloads/embedded-studio/ 下载 + - Segger Embedded Studio for RISC-V 工程文件会在 "使用GNU GCC工具链编译示例应用:" -> "4. 为Ninja-build产生构建文件:" 描述的过程中 + - 产生的工程文件(.emProject)可以在build/segger_embedded_studio目录中找到 + + 注意：openocd可执行文件应该可以通过当前终端的PATH环境变量中可以找到, 否则无法在工程文件中生成相应的调试配置，需要之后在Segger Embedded Studio中手工配置。 + +# 社区支持 \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/SConscript b/bsp/hpmicro/libraries/hpm_sdk/SConscript new file mode 100644 index 0000000000..36e1210ef6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/SConscript @@ -0,0 +1,83 @@ +Import('rtconfig') +from building import * + +#get current directory +cwd = GetCurrentDir() + +# Update include path +path = [ cwd + '/arch', cwd + "/drivers/inc", cwd + '/soc/ip'] + +# The set of source files associated with this SConscript file. +src = [] + +src += ['drivers/src/hpm_pmp_drv.c'] +src += ['drivers/src/hpm_pllctl_drv.c'] +src += ['drivers/src/hpm_pllctlv2_drv.c'] +src += ['drivers/src/hpm_dma_drv.c'] + + +if GetDepend(['BSP_USING_GPIO']): + src += ['drivers/src/hpm_gpio_drv.c'] + +if GetDepend(['BSP_USING_UART']): + src += ['drivers/src/hpm_uart_drv.c'] + +if GetDepend(['BSP_USING_I2C']): + src += ['drivers/src/hpm_i2c_drv.c'] + +if GetDepend(['BSP_USING_SPI']): + src += ['drivers/src/hpm_spi_drv.c'] + +if GetDepend(['BSP_USING_RTC']): + src += ['drivers/src/hpm_rtc_drv.c'] + +if GetDepend(['BSP_USING_WDG']): + src += ['drivers/src/hpm_wdg_drv.c'] + +if GetDepend(['BSP_USING_ADC']): + if GetDepend(['BSP_USING_ADC12']): + src += ['drivers/src/hpm_adc12_drv.c'] + if GetDepend(['BSP_USING_ADC16']): + src += ['drivers/src/hpm_adc16_drv.c'] + +if GetDepend(['BSP_USING_CAN']): + src += ['drivers/src/hpm_can_drv.c'] + +if GetDepend(['BSP_USING_ETH']): + src += ['drivers/src/hpm_enet_drv.c'] + +if GetDepend(['BSP_USING_DMA']): + src += ['drivers/src/hpm_dma_drv.c'] + +if GetDepend(['BSP_USING_SDXC']): + src += ['drivers/src/hpm_sdxc_drv.c'] + +if GetDepend(['BSP_USING_LCD']): + src += ['drivers/src/hpm_lcdc_drv.c'] + +if GetDepend(['BSP_USING_GPTMR']): + src += ['drivers/src/hpm_gptmr_drv.c'] + +if GetDepend(['BSP_USING_DRAM']): + src += ['drivers/src/hpm_dram_drv.c'] + +if GetDepend(['BSP_USING_PWM']): + src += ['drivers/src/hpm_pwm_drv.c'] + +if GetDepend(['BSP_USING_USB']): + src += ['drivers/src/hpm_usb_drv.c'] + +if GetDepend(['BSP_USING_I2S']): + src += ['drivers/src/hpm_i2s_drv.c'] + +if GetDepend(['BSP_USING_PDM']): + src += ['drivers/src/hpm_pdm_drv.c'] + src += ['drivers/src/hpm_i2s_drv.c'] + +if GetDepend(['BSP_USING_DAO']): + src += ['drivers/src/hpm_dao_drv.c'] + src += ['drivers/src/hpm_i2s_drv.c'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/VERSION b/bsp/hpmicro/libraries/hpm_sdk/VERSION new file mode 100644 index 0000000000..7be09ab348 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/VERSION @@ -0,0 +1,5 @@ +VERSION_MAJOR = 0 +VERSION_MINOR = 13 +PATCHLEVEL = 1 +VERSION_TWEAK = 0 +EXTRAVERSION = 0 diff --git a/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h b/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h new file mode 100644 index 0000000000..7455ff38bc --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef RISCV_CORE_H +#define RISCV_CORE_H + +#include "hpm_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief write fp csr + * + * @param v value to be set + */ +#define write_fcsr(v) __asm volatile("fscsr %0" : : "r"(v)) + +/** + * @brief clear bits in csr + * + * @param csr_num specific csr + * @param bit bits to be cleared + */ +#define clear_csr(csr_num, bit) __asm volatile("csrc %0, %1" : : "i"(csr_num), "r"(bit)) + +/** + * @brief set bits in csr + * + * @param csr_num specific csr + * @param bit bits to be set + */ +#define set_csr(csr_num, bit) __asm volatile("csrs %0, %1" : : "i"(csr_num), "r"(bit)) + +/** + * @brief write value to csr + * + * @param csr_num specific csr + * @param v value to be written + */ +#define write_csr(csr_num, v) __asm volatile("csrw %0, %1" : : "i"(csr_num), "r"(v)) + +/** + * @brief read value of specific csr + * + * @param csr_num specific csr + * + * @return csr value + */ +#define read_csr(csr_num) ({ uint32_t v; __asm volatile("csrr %0, %1" : "=r"(v) : "i"(csr_num)); v; }) + +/** + * @brief read fp csr + * + * @return fp csr value + */ +#define read_fcsr() ({ uint32_t v; __asm volatile("frcsr %0" : "=r"(v)); v; }) + +/** + * @brief execute fence.i + * + */ +#define fencei() __asm volatile("fence.i") + +#ifdef __cplusplus +} +#endif + + +#endif /* RISCV_CORE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README.md new file mode 100644 index 0000000000..3f8bb83429 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README.md @@ -0,0 +1,75 @@ +# HPM6300EVK + + +::::{important} +:::{note} +Need to supplement the content of each module +::: +:::: + +## Overview + +version +Board overall +Board overall hpm6300evk + +- Console serial port parameters: + + - Baud rate: 115200 + - Data bits: 8 bits + - Check Digit: None + - Stop bit: 1 + - Flow Control Bits: None + - Data encoding method: ASCII + +## DIP Switch S1 + +- Bit 1 and 2 controls boot mode + +| bit[2:1] | Description | +| -------- | ---------------------------- | +| OFF, OFF | Boot from Quad SPI NOR flash | +| OFF, ON | Serial boot | +| ON, OFF | ISP | + +(lab_hpm6300_evk_board)= +## Button + +(lab_hpm6300_evk_board_buttons)= +| Function | Position | +| ---- | -------- | +|PBUTN (sw3) |Power Button, TinyUF2 Boot Button, GPIO Button | +|WBUTN (sw1) | WAKE UP Button | +|RESET (sw2) | Reset Button | + +## Pin Description + +- SPI Pin： + +| Function | Position | +| ---- | -------- | +| SPI3.CSN | J28[24] | +| SPI3.SCLK | J28[23] | +| SPI3.MISO | J28[21] | +| SPI3.MOSI | J28[19] | + +- I2C Pin： + +| Function | Position | +| ---- | -------- | +| I2C0.SCL | J28[13] | +| I2C0.SDA | J28[15] | + +- ACMP Pin + +| Function | Position | +| ---- | -------- | +| CMP.INN5 | J26[7] | +| CMP.COMP_1 | J26[5] | + +- GPTMR Pin + +| Function | Position | +| ---- | -------- | +| GPTMR2.CAPT_2 | J28[40] | +| GPTMR2.COMP_2 | J28[35] | \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README_zh.md new file mode 100644 index 0000000000..e5d3b3fc2d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/README_zh.md @@ -0,0 +1,73 @@ +# HPM6300EVK开发板 + + +::::{important} +:::{note} +添加内容 +::: +:::: + +## 概述 + + +- 控制台串口参数： + + - 波特率：115200 + - 数据位：8位 + - 校验位：无 + - 停止位：1 + - 流控位：无 + - 数据编码方式：ASCII + +## 拨码开关 S1 + +- Bit 1，2控制启动模式 + +| Bit[2:1] | 功能描述 | +| -------- | ----------------------- | +| OFF, OFF | Quad SPI NOR flash 启动 | +| OFF, ON | 串行启动 | +| ON, OFF | 在系统编程 | + +(lab_hpm6300_evk_board)= +## 按键 + +(lab_hpm6300_evk_board_buttons)= +| 名称 | 功能 | +| ---- | -------- | +|PBUTN (sw3) | 电源按键, TinyUF2 Boot按键, GPIO 按键| +|WBUTN (sw1) | WAKE UP 按键| +|RESET (sw2) | Reset 按键| + + +## 引脚描述 + +- SPI引脚： + +| 功能 | 位置 | +| ---- | -------- | +| SPI3.CSN | J28[24] | +| SPI3.SCLK | J28[23] | +| SPI3.MISO | J28[21] | +| SPI3.MOSI | J28[19] | + +- I2C引脚： + +| 功能 | 位置 | +| ---- | -------- | +| I2C0.SCL | J28[13] | +| I2C0.SDA | J28[15] | + +- ACMP引脚 + +| 功能 | 位置 | +| ---- | -------- | +| CMP.INN5 | J26[7] | +| CMP.COMP_1 | J26[5] | + +- GPTMR引脚 + +| 功能 | 位置 | +| ---- | -------- | +| GPTMR2.CAPT_2 | J28[40] | +| GPTMR2.COMP_2 | J28[35] | diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/SConscript b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/SConscript new file mode 100644 index 0000000000..7c742f69d0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.c b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.c new file mode 100644 index 0000000000..b0ae81048a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.c @@ -0,0 +1,682 @@ +/* + * Copyright (c) 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_lcdc_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_debug_console.h" +#include "hpm_dram_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_sdxc_drv.h" +#include "hpm_pwm_drv.h" +#include "hpm_trgm_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_pcfg_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if console_type_uart == BOARD_CONSOLE_TYPE + console_config_t cfg; + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t) BOARD_CONSOLE_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_BAUDRATE; + + init_uart_pins((UART_Type *) cfg.base); + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) { + } +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("axi:\t\t %luHz\n", clock_get_frequency(clock_axi)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); + printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + init_uart_pins(ptr); +} + +void board_init_ahb(void) +{ + clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2);/*200m hz*/ +} + +void board_print_banner(void) +{ + const uint8_t banner[] = {"\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n"}; + printf("%s", banner); +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +void board_init(void) +{ + pcfg_dcdc_set_voltage(HPM_PCFG, 1100); + board_init_clock(); + board_init_console(); + board_init_pmp(); + board_init_ahb(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_sdram_pins(void) +{ + init_sdram_pins(); +} + +uint32_t board_init_dram_clock(void) +{ + clock_add_to_group(clock_dram, 0); + /* Configure the SDRAM to 133MHz */ + clock_set_source_divider(clock_dram, clk_src_pll0_clk1, 2U); + + return clock_get_frequency(clock_dram); +} + +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + init_i2c_pins_as_gpio(ptr); +} + +void board_init_i2c(I2C_Type *ptr) +{ +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + /* SPI3 clock configure */ + clock_add_to_group(clock_spi3, 0); + clock_set_source_divider(clock_spi3, clk_src_osc24m, 1U); + + return clock_get_frequency(clock_spi3); + } + return 0; +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_led_pins(void) +{ + init_led_pins(); + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_led_toggle(void) +{ + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_init_usb_pins(void) +{ + /* set pull-up for USBx ID pin */ + init_usb_pins(); + + /* configure USBx ID pin as input function */ + gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); +} + +uint8_t board_get_usb_id_status(void) +{ + return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ +} + +void board_init_pmp(void) +{ + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + + uint32_t start_addr = (uint32_t) __noncacheable_start__; + uint32_t end_addr = (uint32_t) __noncacheable_end__; + uint32_t length = end_addr - start_addr; + + if (length == 0) { + return; + } + + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + + pmp_entry_t pmp_entry[3] = {0}; + pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(0x0000000, 0x80000000); + pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + + + pmp_entry[1].pmp_addr = PMP_NAPOT_ADDR(0x80000000, 0x80000000); + pmp_entry[1].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + + pmp_entry[2].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[2].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[2].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[2].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + /* Add most Clocks to group 0 */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_ahbp, 0); + clock_add_to_group(clock_axic, 0); + clock_add_to_group(clock_axis, 0); + + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_xpi1, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_uart0, 0); + clock_add_to_group(clock_uart1, 0); + clock_add_to_group(clock_uart2, 0); + clock_add_to_group(clock_uart3, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_sdxc0, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_ref0, 0); + clock_add_to_group(clock_ref1, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_eth0, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_ram0, 0); + clock_add_to_group(clock_usb0, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_mot1, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_dao, 0); + clock_add_to_group(clock_msyn, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_pdm, 0); + + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_adc2, 0); + + clock_add_to_group(clock_dac0, 0); + + clock_add_to_group(clock_i2s0, 0); + clock_add_to_group(clock_i2s1, 0); + + clock_add_to_group(clock_ffa0, 0); + clock_add_to_group(clock_tsns, 0); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + /* Configure CPU0 to 480MHz */ + clock_set_source_divider(clock_cpu0, clk_src_pll1_clk0, 1); + + clock_update_core_clock(); +} + +uint32_t board_init_adc12_clock(ADC16_Type *ptr) +{ + uint32_t freq = 0; + switch ((uint32_t) ptr) { + case HPM_ADC0_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc0); + break; + case HPM_ADC1_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc1); + break; + case HPM_ADC2_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc2); + break; + default: + /* Invalid ADC instance */ + break; + } + + return freq; +} + +uint32_t board_init_dao_clock(void) +{ + return clock_get_frequency(clock_dao); +} + +uint32_t board_init_pdm_clock(void) +{ + return clock_get_frequency(clock_pdm); +} + +uint32_t board_init_i2s_clock(I2S_Type *ptr) +{ + return 0; +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr) +{ + return 0; +} + +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_DAC) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 133MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ahb); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ana); + clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac0); + } + + return freq; +} + +void board_init_can(CAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(CAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAN0) { + /* Set the CAN0 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_CAN1) { + /* Set the CAN1 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5); + freq = clock_get_frequency(clock_can1); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +#ifdef INIT_EXT_RAM_FOR_DATA +/* + * this function will be called during startup to initialize external memory for data use + */ +void _init_ext_ram(void) +{ + uint32_t dram_clk_in_hz; + board_init_sdram_pins(); + dram_clk_in_hz = board_init_dram_clock(); + + dram_config_t config = {0}; + dram_sdram_config_t sdram_config = {0}; + + dram_default_config(HPM_DRAM, &config); + config.dqs = DRAM_DQS_INTERNAL; + dram_init(HPM_DRAM, &config); + + sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.prescaler = 0x3; + sdram_config.burst_len_in_byte = 8; + sdram_config.auto_refresh_count_in_one_burst = 1; + sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + + sdram_config.precharge_to_act_in_ns = 18; /* Trp */ + sdram_config.act_to_rw_in_ns = 18; /* Trcd */ + sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */ + sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */ + sdram_config.cke_off_in_ns = 42; /* Trcd */ + sdram_config.act_to_precharge_in_ns = 42; /* Tras */ + + sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */ + sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ + sdram_config.act_to_act_in_ns = 12; /* Trrd */ + sdram_config.idle_timeout_in_ns = 6; + sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + + sdram_config.cs = BOARD_SDRAM_CS; + sdram_config.base_address = BOARD_SDRAM_ADDRESS; + sdram_config.size_in_byte = BOARD_SDRAM_SIZE; + sdram_config.port_size = BOARD_SDRAM_PORT_SIZE; + sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; + sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; + sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; + sdram_config.delay_cell_value = 29; + + dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); +} +#endif + +void board_init_sd_pins(SDXC_Type *ptr) +{ + init_sdxc_pins(ptr, false); +} + +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) +{ + uint32_t actual_freq = 0; + do { + if (ptr != HPM_SDXC0) { + break; + } + clock_name_t sdxc_clk = clock_sdxc0; + sdxc_enable_sd_clock(ptr, false); + /* Configure the SDXC Frequency to 200MHz */ + clock_set_source_divider(sdxc_clk, clk_src_pll0_clk0, 2); + sdxc_enable_freq_selection(ptr); + + /* Configure the clock below 400KHz for the identification state */ + if (freq <= 400000UL) { + sdxc_set_clock_divider(ptr, 600); + } + /* configure the clock to 24MHz for the SDR12/Default speed */ + else if (freq <= 25000000UL) { + sdxc_set_clock_divider(ptr, 8); + } + /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ + else if (freq <= 50000000UL) { + sdxc_set_clock_divider(ptr, 4); + } + /* Configure the clock to 100MHz for the SDR50 */ + else if (freq <= 100000000UL) { + sdxc_set_clock_divider(ptr, 2); + } + /* Configure the clock to 166MHz for SDR104/HS200/HS400 */ + else if (freq <= 208000000UL) { + sdxc_set_clock_divider(ptr, 1); + } + /* For other unsupported clock ranges, configure the clock to 24MHz */ + else { + sdxc_set_clock_divider(ptr, 8); + } + sdxc_enable_sd_clock(ptr, true); + actual_freq = clock_get_frequency(sdxc_clk) / sdxc_get_clock_divider(ptr); + } while (false); + + return actual_freq; +} + +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) +{ + /* This feature is not supported */ +} + +bool board_sd_detect_card(SDXC_Type *ptr) +{ + return sdxc_is_card_inserted(ptr); +} + +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) +{ + /* set clock source */ + if (ptr == HPM_ENET0) { + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for ent0 ptp clock */ + clock_set_source_divider(clock_ptp0, clk_src_pll0_clk0, 4); /* 100MHz */ + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) +{ + if (internal == false) { + return status_success; + } + + /* Configure Enet clock to output reference clock */ + if (ptr == HPM_ENET0) { + /* make sure pll0_clk2 output clock at 250MHz then set 50MHz for enet0 */ + clock_set_source_divider(clock_eth0, clk_src_pll0_clk2, 5); + } else { + return status_invalid_argument; + } + return status_success; +} + +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr) +{ + init_enet_pins(ptr); + + return status_success; +} + +void board_init_dac_pins(DAC_Type *ptr) +{ + init_dac_pins(ptr); +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART1) { + clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart1); + } else if (ptr == HPM_UART2) { + clock_set_source_divider(clock_uart2, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart2); + } else { + /* Not supported */ + } + return freq; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.h b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.h new file mode 100644 index 0000000000..72d774d76b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.h @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" + +#define BOARD_NAME "hpm6300evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX + +/* uart section */ +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART0 +#define BOARD_APP_UART_IRQ IRQn_UART0 +#else +#ifndef BOARD_APP_UART_IRQ +#warning no IRQ specified for applicaiton uart +#endif +#endif + +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart0 + +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE console_type_uart +#endif + +#if console_type_uart == BOARD_CONSOLE_TYPE +#ifndef BOARD_CONSOLE_BASE +#if BOARD_RUNNING_CORE == HPM_CORE0 +#define BOARD_CONSOLE_BASE HPM_UART0 +#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#else +#define BOARD_CONSOLE_BASE HPM_UART13 +#define BOARD_CONSOLE_CLK_NAME clock_uart13 +#endif +#endif +#define BOARD_CONSOLE_BAUDRATE (115200UL) +#endif + +#define BOARD_FREEMASTER_UART_BASE HPM_UART0 +#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 +#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 + +/* uart rx idle demo section */ +#define BOARD_UART_IDLE HPM_UART2 +#define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART2_RX + +#define BOARD_UART_IDLE_TRGM HPM_TRGM1 +#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PA24 +#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM1_INPUT_SRC_TRGM1_P4 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI + +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR2 +#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr2 +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR2 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +/* sdram section */ +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32*SIZE_1MB) +#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) + + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (16 * SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 +#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR2 +#define BOARD_GPTMR_IRQ IRQn_GPTMR2 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_PWM HPM_GPTMR2 +#define BOARD_GPTMR_PWM_CHANNEL 0 + +/* gpio section */ +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ +#define BOARD_APP_GPIO_PIN 2 + +/* pinmux section */ +#define USING_GPIO0_FOR_GPIOZ +#ifndef USING_GPIO0_FOR_GPIOZ +#define BOARD_APP_GPIO_CTRL HPM_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#else +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#endif + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI3 +#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) +#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI3_RX +#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX +#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PC18 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* i2s section */ +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_DATA_LINE (2U) +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 + +/* enet section */ +#define BOARD_ENET_RMII HPM_ENET0 +#define BOARD_ENET_RMII_RST_GPIO +#define BOARD_ENET_RMII_RST_GPIO_INDEX +#define BOARD_ENET_RMII_RST_GPIO_PIN +#define BOARD_ENET_RMII HPM_ENET0 +#define BOARD_ENET_RMII_INT_REF_CLK (1U) +#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (13U) +#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 +#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 +#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 +#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 +#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT + +/* DAC section */ +#define BOARD_DAC_BASE HPM_DAC +#define BOARD_DAC_IRQn IRQn_DAC +#define BOARD_DAC_CLOCK_NAME clock_dac0 + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_CAN1 +#define BOARD_APP_CAN_IRQn IRQn_CAN1 + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR3) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) + +/* SDXC section */ +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (0) +#if BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO +#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO NULL +#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX 0 +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 0 +#endif + +/* USB section */ +#define BOARD_USB0_ID_PORT (HPM_GPIO0) +#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOC) +#define BOARD_USB0_ID_GPIO_PIN (23) + +/*BLDC pwm*/ + +/*PWM define*/ +#define BOARD_BLDCPWM HPM_PWM0 +#define BOARD_BLDC_UH_PWM_OUTPIN (0U) +#define BOARD_BLDC_UL_PWM_OUTPIN (1U) +#define BOARD_BLDC_VH_PWM_OUTPIN (2U) +#define BOARD_BLDC_VL_PWM_OUTPIN (3U) +#define BOARD_BLDC_WH_PWM_OUTPIN (4U) +#define BOARD_BLDC_WL_PWM_OUTPIN (5U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) + +/*HALL define*/ + +#define BOARD_BLDC_HALL_BASE HPM_HALL0 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM0 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL0 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN8 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN6 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) + + + +/*QEI*/ + +#define BOARD_BLDC_QEI_BASE HPM_QEI0 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI0 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN9 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN10 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +/*Timer define*/ + +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (14U) +#define BOARD_BLDC_ADC_CH_V (12U) +#define BOARD_BLDC_ADC_CH_W (5U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC1 +#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_TRGM HPM_TRGM0 + +#define BOARD_CPU_FREQ (480000000UL) + +/* LED */ +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LED_GPIO_PIN 7 +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); + +void board_init_uart(UART_Type *ptr); +void board_init_i2c(I2C_Type *ptr); + +void board_init_can(CAN_Type *ptr); + +uint32_t board_init_dram_clock(void); + +void board_init_sdram_pins(void); +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +void board_init_led_pins(void); + +void board_led_write(uint8_t state); +void board_led_toggle(void); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); + +uint32_t board_init_spi_clock(SPI_Type *ptr); + +uint32_t board_init_adc16_clock(ADC16_Type *ptr); + +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); + +void board_init_adc16_pins(void); + +void board_init_dac_pins(DAC_Type *ptr); + +uint32_t board_init_can_clock(CAN_Type *ptr); + +uint32_t board_init_i2s_clock(I2S_Type *ptr); +uint32_t board_init_pdm_clock(void); +uint32_t board_init_dao_clock(void); + +void board_init_sd_pins(SDXC_Type *ptr); +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); +bool board_sd_detect_card(SDXC_Type *ptr); + +void board_init_usb_pins(void); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +uint8_t board_get_usb_id_status(void); + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); + +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); + +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +/* Initialize the UART clock */ +uint32_t board_init_uart_clock(UART_Type *ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c new file mode 100644 index 0000000000..202a477985 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; + /* PY port IO needs to configure PIOC */ + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; + } else if (ptr == HPM_UART1) { + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_UART1_TXD; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_UART1_RXD; + } else if (ptr == HPM_UART2) { + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD; + } +} + +void init_i2c_pins_as_gpio(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + /* I2C0 */ + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_GPIO_C_13; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_GPIO_C_14; + } else { + while (1) { + } + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_I2C0_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_I2C0_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else if (ptr == HPM_I2C3) { + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_I2C3_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_I2C3_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else { + while (1) { + } + } +} + +void init_sdram_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + + /* Button */ +#ifdef USING_GPIO0_FOR_GPIOZ + HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; + HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; +#endif +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_SPI3_CSN; + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI3) { + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_GPIO_C_18; + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + +void init_pins(void) +{ + init_uart_pins(BOARD_CONSOLE_BASE); + init_sdram_pins(); +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR2) { + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0; + } +} + +void init_hall_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_TRGM0_P_06; + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_TRGM0_P_07; + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PB28_FUNC_CTL_TRGM0_P_08; +} + +void init_qei_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_TRGM0_P_09; + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_TRGM0_P_10; +} + +void init_butn_pins(void) +{ + /* HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; */ + /* HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; */ +} + +void init_acmp_pins(void) +{ + /* configure to CMP1_INN5 function */ + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* configure to ACMP_COMP_1 function */ + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_ACMP_COMP_1; +} + +void init_enet_pins(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_ETH0_MDC; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_ETH0_MDIO; + + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_ETH0_RXD_0; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_ETH0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_ETH0_RXDV; + + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_ETH0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_ETH0_TXD_1; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_ETH0_TXEN; + + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK | IOC_PA22_FUNC_CTL_ETH0_REFCLK; + } +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM0) { + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_PWM0_P_5; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_PWM0_P_3; + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_PWM0_P_1; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_PWM0_P_4; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_PWM0_P_2; + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_PWM0_P_0; + } +} + +void init_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_usb_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; + HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); +} + +void init_can_pins(CAN_Type *ptr) +{ + if (ptr == HPM_CAN1) { + HPM_IOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_CAN1_TXD; + HPM_IOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_CAN1_RXD; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_SOC_PZ_04; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_SOC_PZ_05; + } +} + +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) +{ + uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + uint32_t clk_pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + /* SDXC0.CLK */ + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA11].PAD_CTL = clk_pad_ctl; + + /* SDXC0.CMD */ + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl; + + /* SDXC0.CD */ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl; + + /* SDXC0.DATA0 */ + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = pad_ctl; + /* SDXC0.DATA1 */ + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = pad_ctl; + /* SDXC0.DATA2 */ + HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA08].PAD_CTL = pad_ctl; + /* SDXC0.DATA3 */ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; +} + +void init_clk_obs_pins(void) +{ + /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */ +} + +void init_led_pins(void) +{ + /* Pull up */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); + + HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_GPIO_A_07; + HPM_IOC->PAD[IOC_PAD_PA07].PAD_CTL = pad_ctl; +} + +void init_dac_pins(DAC_Type *ptr) +{ + if (ptr == HPM_DAC) { + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + } +} + +void init_trgmux_pins(uint32_t pin) +{ + /* all trgmux pin ALT_SELECT fixed to 16*/ + HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h new file mode 100644 index 0000000000..66b1413d0e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h @@ -0,0 +1,41 @@ +/* + *Copyright (c) 2022 hpmicro + * + *SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_uart_pins(UART_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_sdram_pins(void); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_pins(void); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_enet_pins(ENET_Type *ptr); +void init_pwm_pins(PWM_Type *ptr); +void init_adc_pins(void); +void init_dac_pins(DAC_Type *ptr); +void init_usb_pins(void); +void init_can_pins(CAN_Type *ptr); +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); +void init_adc_bldc_pins(void); +void init_rgb_pwm_pins(void); +void init_i2c_pins_as_gpio(I2C_Type *ptr); +void init_led_pins(void); +void init_trgmux_pins(uint32_t pin); +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README.md new file mode 100644 index 0000000000..97772a5be5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README.md @@ -0,0 +1,104 @@ +# HPM6750EVK + +## Overview + +The HPM6750 is a dual-core flashless MCU running 816Mhz. It has a 2MB continuous on-chip ram. Also, it provides various memory interfaces, including SDRAM, Quad SPI NOR Flash, SD/eMMC. It integrates rich audio and video interfaces, including LCD, pixel DMA, camera， and I2S audio interfaces. + + ![hpm6750evk](../../doc/images/boards/hpm6750evk/hpm6750evk.png "hpm6750evk") + +## Hardware + +- HPM6750IVM MCU (816Mhz, 2MB OCRAM) +- Onboard Memory + - 256Mb SDRAM + - 128Mb Quad SPI NOR Flash +- Display & Camera + - LCD connector + - Camera (DVP) +- Ethernet + - 1000 Mbits PHY + - 100 Mbits PHY +- USB + - USB type C (USB 2.0 OTG) connector x3 +- Audio + - Line in + - Mic + - Speaker + - DAO +- Others + - TF Slot + - FT2232 + - Beeper + - RGB LED + - CAN +- Expansion port + - Motor control + +## DIP Switch S1 + +- Bit 1 and 2 controls boot mode + +| bit[2:1] | Description | +| -------- | ---------------------------- | +| OFF, OFF | Boot from Quad SPI NOR flash | +| OFF, ON | Serial boot | +| ON, OFF | ISP | + +- Change the position of bit 3 to select between PWM and 1000Mbit ethernet + +| Bit3 | Description | +| ---- | -------------- | +| OFF | 1000Mbits ENET | +| ON | PWM | + +(lab_hpm6750_evk_board)= +## Button +(lab_hpm6750_evk_board_buttons)= +| Name | FUNCTIONS | +| ---- | -------- | +|PBUTN (S2) | Power Button, TinyUF2 Boot Button, GPIO Button | +|WBUTN (S3) | WAKE UP Button | +|RESET (S4) | Reset Button | + +## Pin Description + +- PWM Pin: + + ![image-1](../../doc/images/boards/hpm6750evk/hpm6750evk_pwm_output_pin.png "image-1") + +- SPI Pin： + +| Function | Position | +| ---- | -------- | +| SPI2.CSN | J20[6] | +| SPI2.SCLK | J20[7] | +| SPI2.MISO | J20[8] | +| SPI2.MOSI | J20[9] | + +- I2C Pin： + +| Function | Position | +| ---- | -------- | +| I2C0.SCL | J20[3] | +| I2C0.SDA | J20[4] | + +- UART for core1 debug console + +| Function | Position | +| ---- | -------- | +| UART13.TXD | J20[5] | +| UART13.RXD | J20[6] | + +- ACMP Pin + +| Function | Position | +| ---- | -------- | +| CMP.INN6 | J12[8] | +| CMP.COMP_1 | J12[6] | + +- GPTMR Pin + +| Function | Function | +| ---- | -------- | +| GPTMR4.CAPT_1 | J12[6] | +| GPTMR3.COMP_1 | J12[7] | diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README_zh.md new file mode 100644 index 0000000000..80dfcabb93 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/README_zh.md @@ -0,0 +1,107 @@ +# HPM6750EVK开发板 + +## 概述 + +HPM6750是一款主频达816Mhz的双核微控制器。该芯片拥有最大2M字节的连续片上RAM，并集成了丰富的存储接口，如SDRAM，Quad SPI NOR flash， SD/eMMC卡。同时它也提供多种音视频接口包括LCD显示，像素DMA，摄像头以及I2S音频接口。 + + ![hpm6750evk](../../doc/images/boards/hpm6750evk/hpm6750evk.png "hpm6750evk") + +## 板上硬件资源 + +- HPM6750IVM 微控制器 (主频816Mhz, 2MB片上内存) +- 板载存储 + - 256Mb SDRAM + - 128Mb Quad SPI NOR Flash +- 显示/摄像头 + - LCD接口 + - 摄像头(DVP)接口 +- 以太网 + - 1000 Mbits PHY + - 100 Mbits PHY +- USB + - USB type C (USB 2.0 OTG) connector x3 +- 音频 + - Line in + - Mic + - Speaker + - DAO +- 其他 + - TF卡槽 + - FT2232 + - 蜂鸣器 + - RGB LED + - CAN +- 扩展口 + - 电机控制 + +## 拨码开关 S1 + +- Bit 1，2控制启动模式 + +| Bit[2:1] | 功能描述 | +| -------- | ----------------------- | +| OFF, OFF | Quad SPI NOR flash 启动 | +| OFF, ON | 串行启动 | +| ON, OFF | 在系统编程 | + +- Bit 3用于选择PWM或是千兆网口 + +| Bit3 | 功能描述 | +| ---- | -------- | +| OFF | 千兆网口 | +| ON | PWM | + +(lab_hpm6750_evk_board)= +## 按键 + +(lab_hpm6750_evk_board_buttons)= +| 名称 | 功能 | +| ---- | -------- | +|PBUTN (S2) | 电源按键, TinyUF2 Boot按键, GPIO 按键| +|WBUTN (S3) | WAKE UP 按键| +|RESET (S4) | Reset 按键| + +## 引脚描述 + +- J12端子的 `P-UH 、P-UL`引脚为PWM输出引脚，如下图所示 + + ![image-1](../../doc/images/boards/hpm6750evk/hpm6750evk_pwm_output_pin.png "image-1") + +- SPI引脚： + +| 功能 | 位置 | +| ---- | -------- | +| SPI2.CSN | J20[6] | +| SPI2.SCLK | J20[7] | +| SPI2.MISO | J20[8] | +| SPI2.MOSI | J20[9] | + +- I2C引脚： + +| 功能 | 位置 | +| ---- | -------- | +| I2C0.SCL | J20[3] | +| I2C0.SDA | J20[4] | + +- CORE1调试串口引脚： + +| 功能 | 位置 | +| ---- | -------- | +| UART13.TXD | J20[5] | +| UART13.RXD | J20[6] | + +- ACMP引脚 + +| 功能 | 位置 | +| ---- | -------- | +| CMP.INN6 | J12[8] | +| CMP.COMP_1 | J12[6] | + +- GPTMR引脚 + +| 功能 | 位置 | +| ---- | -------- | +| GPTMR4.CAPT_1 | J12[6] | +| GPTMR3.COMP_1 | J12[7] | + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/SConscript b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/SConscript new file mode 100644 index 0000000000..7c742f69d0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.c b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.c new file mode 100644 index 0000000000..ed65ffc382 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.c @@ -0,0 +1,991 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_lcdc_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_debug_console.h" +#include "hpm_dram_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_sdxc_drv.h" +#include "hpm_pwm_drv.h" +#include "hpm_trgm_drv.h" +#include "hpm_pllctl_drv.h" +#include "hpm_enet_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if BOARD_CONSOLE_TYPE == console_type_uart + console_config_t cfg; + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t) BOARD_CONSOLE_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_BAUDRATE; + + init_uart_pins((UART_Type *) cfg.base); + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while(1); +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1)); + printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0)); + printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1)); + printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); + printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("display:\t %luHz\n", clock_get_frequency(clock_display)); + printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); + printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); + printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg)); + printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + init_uart_pins(ptr); +} + +void board_init_ahb(void) +{ + clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ +} + +void board_print_banner(void) +{ + const uint8_t banner[] = {"\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n"}; + printf("%s", banner); +} + +static void board_turnoff_rgb_led(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; + + HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +void board_init(void) +{ + board_turnoff_rgb_led(); + board_init_clock(); + board_init_console(); + board_init_pmp(); + board_init_ahb(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_sdram_pins(void) +{ + init_sdram_pins(); +} + +uint32_t board_init_dram_clock(void) +{ + clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ + /* clock_set_source_divider(clock_dram, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ + + return clock_get_frequency(clock_dram); +} + +void board_power_cycle_lcd(void) +{ + /* turn off backlight */ + gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0); + + board_delay_ms(150); + /* power recycle */ + gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0); + board_delay_ms(150); + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1); + board_delay_ms(150); + + /* turn on backlight */ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); + +} + +void board_init_lcd(void) +{ + board_init_lcd_clock(); + init_lcd_pins(BOARD_LCD_BASE); + + board_power_cycle_lcd(); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + init_i2c_pins_as_gpio(ptr); + if (ptr == BOARD_CAP_I2C_BASE) { + gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN); + gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); + if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { + printf("CLK is low, please power cycle the board\n"); + while (1) {} + } + if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); + while (1) { + for (uint32_t i = 0; i < 9; i++) { + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0); + board_delay_ms(10); + } + board_delay_ms(100); + } + printf("I2C bus is cleared\n"); + } +} + +void board_init_i2c(I2C_Type *ptr) +{ + hpm_stat_t stat; + uint32_t freq; + i2c_config_t config; + + board_i2c_bus_clear(ptr); + + init_i2c_pins(ptr); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); + stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t)BOARD_CAP_I2C_BASE); + while (1) {} + } +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART6) { + clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart6); + } else if (ptr == HPM_UART13) { + clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart13); + } else if (ptr == HPM_UART14) { + clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart14); + } else { + /* Not supported */ + } + return freq; +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + /* SPI2 clock configure */ + clock_add_to_group(clock_spi2, 0); + clock_set_source_divider(clock_spi2, clk_src_osc24m, 1U); + + return clock_get_frequency(clock_spi2); + } + return 0; +} + +void board_init_cap_touch(void) +{ + init_cap_pins(); + gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0); + gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + + board_delay_ms(1); + gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); + + gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); + board_init_i2c(BOARD_CAP_I2C_BASE); +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); +} + +void board_led_toggle(void) +{ +#ifdef BOARD_LED_TOGGLE_RGB + static uint8_t i; + gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_R_GPIO_PIN); + i++; + i = i % 3; +#else + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +#endif +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_init_cam_pins(void) +{ + init_cam_pins(); + /* enable cam RST pin out with high level */ + gpio_set_pin_output_with_initial(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, 1); +} + +void board_write_cam_rst(uint8_t state) +{ + gpio_write_pin(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, state); + +} + +void board_init_usb_pins(void) +{ + /* set pull-up for USBx OC pins and ID pins */ + init_usb_pins(); + + /* configure USBx ID pins as input function */ + gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); + gpio_set_pin_input(BOARD_USB1_ID_PORT, BOARD_USB1_ID_GPIO_INDEX, BOARD_USB1_ID_GPIO_PIN); + + /* configure USBx OC Flag pins as input function */ + gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN); + gpio_set_pin_input(BOARD_USB1_OC_PORT, BOARD_USB1_OC_GPIO_INDEX, BOARD_USB1_OC_GPIO_PIN); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ +} + +void board_init_pmp(void) +{ + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + + uint32_t start_addr = (uint32_t) __noncacheable_start__; + uint32_t end_addr = (uint32_t) __noncacheable_end__; + uint32_t length = end_addr - start_addr; + + if (length == 0) { + return; + } + + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + + pmp_entry_t pmp_entry[1]; + pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + + pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1); + } + + /* Add most Clocks to group 0 */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_axi0, 0); + clock_add_to_group(clock_axi1, 0); + clock_add_to_group(clock_axi2, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_xpi1, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_gptmr4, 0); + clock_add_to_group(clock_gptmr5, 0); + clock_add_to_group(clock_gptmr6, 0); + clock_add_to_group(clock_gptmr7, 0); + clock_add_to_group(clock_uart0, 0); + clock_add_to_group(clock_uart1, 0); + clock_add_to_group(clock_uart2, 0); + clock_add_to_group(clock_uart3, 0); + clock_add_to_group(clock_uart13, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_can2, 0); + clock_add_to_group(clock_can3, 0); + clock_add_to_group(clock_display, 0); + clock_add_to_group(clock_sdxc0, 0); + clock_add_to_group(clock_sdxc1, 0); + clock_add_to_group(clock_camera0, 0); + clock_add_to_group(clock_camera1, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_ref0, 0); + clock_add_to_group(clock_ref1, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_eth0, 0); + clock_add_to_group(clock_eth1, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_ram0, 0); + clock_add_to_group(clock_ram1, 0); + clock_add_to_group(clock_usb0, 0); + clock_add_to_group(clock_usb1, 0); + clock_add_to_group(clock_jpeg, 0); + clock_add_to_group(clock_pdma, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_mot1, 0); + clock_add_to_group(clock_mot2, 0); + clock_add_to_group(clock_mot3, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_dao, 0); + clock_add_to_group(clock_msyn, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); + + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_adc2, 0); + clock_add_to_group(clock_adc3, 0); + + clock_add_to_group(clock_i2s0, 0); + clock_add_to_group(clock_i2s1, 0); + clock_add_to_group(clock_i2s2, 0); + clock_add_to_group(clock_i2s3, 0); + + /* Add the CPU1 clock to Group1 */ + clock_add_to_group(clock_mchtmr1, 1); + clock_add_to_group(clock_mbx1, 1); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { + printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); + while(1); + } + + clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); + clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); + + clock_update_core_clock(); +} + +uint32_t board_init_cam_clock(CAM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAM0) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_camera0); + } else if (ptr == HPM_CAM1) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_camera1); + } else { + /* Invalid camera instance */ + } + return freq; +} + +uint32_t board_init_lcd_clock(void) +{ + uint32_t freq; + clock_add_to_group(clock_display, 0); + /* Configure LCDC clock to 29.7MHz */ + clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U); + freq = clock_get_frequency(clock_display); + return freq; +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr) +{ + uint32_t freq = 0; + switch ((uint32_t) ptr) { + case HPM_ADC0_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc0); + break; + case HPM_ADC1_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc1); + break; + case HPM_ADC2_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc2); + break; + default: + /* Invalid ADC instance */ + break; + } + + return freq; +} + +uint32_t board_init_dao_clock(void) +{ + clock_add_to_group(clock_dao, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_dao); +} + +uint32_t board_init_pdm_clock(void) +{ + clock_add_to_group(clock_pdm, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_pdm); +} + +uint32_t board_init_i2s_clock(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, BOARD_APP_AUDIO_CLK_SRC, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_i2s0); + } + return 0; +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_ADC3) { + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} + +void board_init_can(CAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(CAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAN0) { + /* Set the CAN0 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_CAN1) { + /* Set the CAN1 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can1); + } else if (ptr == HPM_CAN2) { + /* Set the CAN2 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can2); + } else if (ptr == HPM_CAN3) { + /* Set the CAN3 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can3); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +#ifdef INIT_EXT_RAM_FOR_DATA +/* + * this function will be called during startup to initialize external memory for data use + */ +void _init_ext_ram(void) +{ + uint32_t dram_clk_in_hz; + board_init_sdram_pins(); + dram_clk_in_hz = board_init_dram_clock(); + + dram_config_t config = {0}; + dram_sdram_config_t sdram_config = {0}; + + dram_default_config(HPM_DRAM, &config); + config.dqs = DRAM_DQS_INTERNAL; + dram_init(HPM_DRAM, &config); + + sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.prescaler = 0x3; + sdram_config.burst_len_in_byte = 8; + sdram_config.auto_refresh_count_in_one_burst = 1; + sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + + sdram_config.precharge_to_act_in_ns = 18; /* Trp */ + sdram_config.act_to_rw_in_ns = 18; /* Trcd */ + sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */ + sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */ + sdram_config.cke_off_in_ns = 42; /* Trcd */ + sdram_config.act_to_precharge_in_ns = 42; /* Tras */ + + sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */ + sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ + sdram_config.act_to_act_in_ns = 12; /* Trrd */ + sdram_config.idle_timeout_in_ns = 6; + sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + + sdram_config.cs = BOARD_SDRAM_CS; + sdram_config.base_address = BOARD_SDRAM_ADDRESS; + sdram_config.size_in_byte = BOARD_SDRAM_SIZE; + sdram_config.port_size = BOARD_SDRAM_PORT_SIZE; + sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; + sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; + sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; + sdram_config.delay_cell_value = 29; + + dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); +} +#endif + +void board_init_sd_pins(SDXC_Type *ptr) +{ + init_sdxc_pins(ptr, false); +} + + +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) +{ + uint32_t actual_freq = 0; + do { + if (ptr != HPM_SDXC1) { + break; + } + clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; + sdxc_enable_inverse_clock(ptr, false); + sdxc_enable_sd_clock(ptr, false); + /* Configure the clock below 400KHz for the identification state */ + if (freq <= 400000UL) { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63); + } + /* configure the clock to 24MHz for the SDR12/Default speed */ + else if (freq <= 25000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); + } + /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ + else if (freq <= 50000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8); + } + /* Configure the clock to 100MHz for the SDR50 */ + else if (freq <= 100000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4); + } + /* Configure the clock to 166MHz for SDR104/HS200/HS400 */ + else if (freq <= 208000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2); + } + /* For other unsupported clock ranges, configure the clock to 24MHz */ + else { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); + } + sdxc_enable_inverse_clock(ptr, true); + sdxc_enable_sd_clock(ptr, true); + actual_freq = clock_get_frequency(sdxc_clk); + } while (false); + + return actual_freq; +} + +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) +{ + /* This feature is not supported */ +} + +bool board_sd_detect_card(SDXC_Type *ptr) +{ + GPIO_Type *gpio = BOARD_APP_SDCARD_CARD_DETECTION_GPIO; + uint32_t gpio_index = BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX; + uint32_t pin_index = BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX; + return ((gpio->DI[gpio_index].VALUE & (1UL << pin_index)) == 0U); +} + +static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index) +{ + pwm_cmp_config_t cmp_config = {0}; + pwm_output_channel_t ch_config = {0}; + + pwm_stop_counter(ptr); + pwm_get_default_cmp_config(ptr, &cmp_config); + pwm_get_default_output_channel_config(ptr, &ch_config); + + pwm_set_reload(ptr, 0, 0xF); + pwm_set_start_count(ptr, 0, 0); + + cmp_config.mode = pwm_cmp_mode_output_compare; + cmp_config.cmp = 0x10; + cmp_config.update_trigger = pwm_shadow_register_update_on_modify; + pwm_config_cmp(ptr, cmp_index, &cmp_config); + + ch_config.cmp_start_index = cmp_index; + ch_config.cmp_end_index = cmp_index; + ch_config.invert_output = false; + + pwm_config_output_channel(ptr, pin, &ch_config); +} + +void board_init_rgb_pwm_pins(void) +{ + trgm_output_t config = {0}; + board_turnoff_rgb_led(); + + set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_OUT, BOARD_RED_PWM_CMP); + set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT, BOARD_GREEN_PWM_CMP); + set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT, BOARD_BLUE_PWM_CMP); + + init_rgb_pwm_pins(); + + config.type = 0; + config.invert = false; + + /* Red: TRGM1 P1 */ + config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH8REF; + trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT1, &config); + + /* Green: TRGM0 P6 */ + config.input = HPM_TRGM0_INPUT_SRC_PWM0_CH8REF; + trgm_output_config(HPM_TRGM0, TRGM_TRGOCFG_TRGM_OUT6, &config); + + /* Blue: TRGM1 P3 */ + config.input = HPM_TRGM1_INPUT_SRC_PWM1_CH9REF; + trgm_output_config(HPM_TRGM1, TRGM_TRGOCFG_TRGM_OUT3, &config); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + trgm_disable_io_output(HPM_TRGM1, 1 << 1); + break; + case BOARD_RGB_GREEN: + trgm_disable_io_output(HPM_TRGM0, 1 << 6); + break; + case BOARD_RGB_BLUE: + trgm_disable_io_output(HPM_TRGM1, 1 << 3); + break; + default: + while (1) { + ; + } + } +} + +void board_enable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + trgm_enable_io_output(HPM_TRGM1, 1 << 1); + break; + case BOARD_RGB_GREEN: + trgm_enable_io_output(HPM_TRGM0, 1 << 6); + break; + case BOARD_RGB_BLUE: + trgm_enable_io_output(HPM_TRGM1, 1 << 3); + break; + default: + while (1) { + ; + } + } +} + +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) +{ + /* set clock source */ + if (ptr == HPM_ENET0) { + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ + clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */ + } else if (ptr == HPM_ENET1) { + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */ + clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */ + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) +{ + if (internal == false) { + return status_success; + } + /* Configure Enet clock to output reference clock */ + if (ptr == HPM_ENET0) { + /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */ + clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); + } else if (ptr == HPM_ENET1) { + /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */ + clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */ + } else { + return status_invalid_argument; + } + + enet_rmii_enable_clock(ptr, internal); + + return status_success; +} + +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) +{ + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); +} + +void board_init_adc12_pins(void) +{ + init_adc12_pins(); +} + +void board_init_adc16_pins(void) +{ + init_adc16_pins(); +} + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr) +{ + init_enet_pins(ptr); + + if (ptr == HPM_ENET0) { + gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1); + } else if (ptr == HPM_ENET1) { + gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1); + } else { + return status_invalid_argument; + } + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.h b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.h new file mode 100644 index 0000000000..9f7d3250df --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/board.h @@ -0,0 +1,524 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" + +#define BOARD_NAME "hpm6750evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +/* uart section */ +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART0 +#define BOARD_APP_UART_IRQ IRQn_UART0 +#else +#ifndef BOARD_APP_UART_IRQ +#warning no IRQ specified for applicaiton uart +#endif +#endif + +/* uart rx idle demo section */ +#define BOARD_UART_IDLE HPM_UART13 +#define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART13_RX + +#define BOARD_UART_IDLE_TRGM HPM_TRGM2 +#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 +#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI + +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart0 + +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE console_type_uart +#endif + +#if BOARD_CONSOLE_TYPE == console_type_uart +#ifndef BOARD_CONSOLE_BASE +#if BOARD_RUNNING_CORE == HPM_CORE0 +#define BOARD_CONSOLE_BASE HPM_UART0 +#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#else +#define BOARD_CONSOLE_BASE HPM_UART13 +#define BOARD_CONSOLE_CLK_NAME clock_uart13 +#endif +#endif +#define BOARD_CONSOLE_BAUDRATE (115200UL) +#endif + + +#define BOARD_FREEMASTER_UART_BASE HPM_UART0 +#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 +#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 + +/* sdram section */ +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32*SIZE_1MB) +#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_32_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) + +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (16 << 20) + +/* lcd section */ +#define BOARD_LCD_BASE HPM_LCDC +#define BOARD_LCD_IRQ IRQn_LCDC_D0 +#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_POWER_GPIO_PIN 16 +#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 +#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 + +#define BOARD_CAM_I2C_BASE HPM_I2C0 +#define BOARD_CAM_I2C_CLK_NAME clock_i2c0 +#define BOARD_SUPPORT_CAM_RESET +#define BOARD_CAM_RST_GPIO_CTRL HPM_GPIO0 +#define BOARD_CAM_RST_GPIO_INDEX GPIO_DI_GPIOY +#define BOARD_CAM_RST_GPIO_PIN 5 + +#define BOARD_CAP_I2C_BASE (HPM_I2C0) +#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 +#define BOARD_CAP_RST_GPIO (HPM_GPIO0) +#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_RST_GPIO_PIN (9) +#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) +#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_INTR_GPIO_PIN (8) +#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOZ) +#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) +#define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOZ) +#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR4 +#define BOARD_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_GPTMR_CHANNEL 1 +#define BOARD_GPTMR_PWM HPM_GPTMR3 +#define BOARD_GPTMR_PWM_CHANNEL 1 + +/* gpio section */ +#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_R_GPIO_PIN 11 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_G_GPIO_PIN 12 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_B_GPIO_PIN 13 + +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 + +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_LED_GPIO_PIN 12 +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +#define BOARD_LED_TOGGLE_RGB 1 + +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ +#define BOARD_APP_GPIO_PIN 2 + +/* pinmux section */ +#define USING_GPIO0_FOR_GPIOZ +#ifndef USING_GPIO0_FOR_GPIOZ +#define BOARD_APP_GPIO_CTRL HPM_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#else +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#endif + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI2 +#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) +#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX +#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX +#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PE31 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* lcd section */ +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH (800) +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT (480) +#endif + +/* pdma section */ +#define BOARD_PDMA_BASE HPM_PDMA + +/* i2s section */ +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_DATA_LINE (2U) +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 + +/* enet section */ +#define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF +#define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) +#define BOARD_ENET_RGMII HPM_ENET0 +#define BOARD_ENET_RGMII_TX_DLY (22U) +#define BOARD_ENET_RGMII_RX_DLY (19U) + +#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) + + +#define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE +#define BOARD_ENET_RMII_RST_GPIO_PIN (26U) +#define BOARD_ENET_RMII HPM_ENET1 +#define BOARD_ENET_RMII_INT_REF_CLK (1U) + +#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) + +/* ADC section */ +#define BOARD_APP_ADC12_NAME "ADC0" +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC12_CH_1 (11U) +#define BOARD_APP_ADC12_CH_2 (10U) +#define BOARD_APP_ADC12_CH_3 (7U) + +#define BOARD_APP_ADC16_NAME "ADC3" +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC16_CH_1 (2U) + + +#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 +#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 +#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 +#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 +#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_CAN0 +#define BOARD_APP_CAN_IRQn IRQn_CAN0 + + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR7) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR7) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) + +/* SDXC section */ +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (1) +#if BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO +#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO HPM_GPIO0 +#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX GPIO_DI_GPIOD +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 15 +#endif + + +/* USB section */ +#define BOARD_USB0_ID_PORT (HPM_GPIO0) +#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) +#define BOARD_USB0_ID_GPIO_PIN (10) + +#define BOARD_USB0_OC_PORT (HPM_GPIO0) +#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) +#define BOARD_USB0_OC_GPIO_PIN (8) + +#define BOARD_USB1_ID_PORT (HPM_GPIO0) +#define BOARD_USB1_ID_GPIO_INDEX (GPIO_DO_GPIOF) +#define BOARD_USB1_ID_GPIO_PIN (7) + +#define BOARD_USB1_OC_PORT (HPM_GPIO0) +#define BOARD_USB1_OC_GPIO_INDEX (GPIO_DI_GPIOF) +#define BOARD_USB1_OC_GPIO_PIN (5) + +/*BLDC pwm*/ + +/*PWM define*/ +#define BOARD_BLDCPWM HPM_PWM2 +#define BOARD_BLDC_UH_PWM_OUTPIN (0U) +#define BOARD_BLDC_UL_PWM_OUTPIN (1U) +#define BOARD_BLDC_VH_PWM_OUTPIN (2U) +#define BOARD_BLDC_VL_PWM_OUTPIN (3U) +#define BOARD_BLDC_WH_PWM_OUTPIN (4U) +#define BOARD_BLDC_WL_PWM_OUTPIN (5U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM2 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM2 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) + +/*HALL define*/ + +#define BOARD_BLDC_HALL_BASE HPM_HALL2 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM2 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL2 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P8 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) + + + +/*QEI*/ + +#define BOARD_BLDC_QEI_BASE HPM_QEI2 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI2 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM2 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +/*Timer define*/ + +#define BOARD_TMR_1MS HPM_GPTMR2 +#define BOARD_TMR_1MS_CH 0 +#define BOARD_TMR_1MS_CMP 0 +#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 +#define BOARD_TMR_1MS_RELOAD (100000U) + +#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS +#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH +#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP +#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ +#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (7U) +#define BOARD_BLDC_ADC_CH_V (10U) +#define BOARD_BLDC_ADC_CH_W (11U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM2 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot2 +#define BOARD_APP_PWM_OUT1 0 +#define BOARD_APP_PWM_OUT2 1 +#define BOARD_APP_TRGM HPM_TRGM2 + +/* RGB LED Section */ +#define BOARD_RED_PWM_IRQ IRQn_PWM1 +#define BOARD_RED_PWM HPM_PWM1 +#define BOARD_RED_PWM_OUT 8 +#define BOARD_RED_PWM_CMP 8 +#define BOARD_RED_PWM_CMP_INITIAL_ZERO true +#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_GREEN_PWM_IRQ IRQn_PWM0 +#define BOARD_GREEN_PWM HPM_PWM0 +#define BOARD_GREEN_PWM_OUT 8 +#define BOARD_GREEN_PWM_CMP 8 +#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot0 + +#define BOARD_BLUE_PWM_IRQ IRQn_PWM1 +#define BOARD_BLUE_PWM HPM_PWM1 +#define BOARD_BLUE_PWM_OUT 9 +#define BOARD_BLUE_PWM_CMP 9 +#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_RGB_RED 0 +#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) +#define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) + +#define BOARD_CPU_FREQ (816000000UL) + +#define BOARD_APP_DISPLAY_CLOCK clock_display + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); + +void board_init_uart(UART_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_lcd(void); + +void board_init_can(CAN_Type *ptr); + +uint32_t board_init_dram_clock(void); + +void board_init_sdram_pins(void); +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +void board_init_led_pins(void); + +/* cap touch */ +void board_init_cap_touch(void); + +void board_led_write(uint8_t state); +void board_led_toggle(void); + +void board_fpga_power_enable(void); + +void board_init_cam_pins(void); +void board_write_cam_rst(uint8_t state); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); + +/* Initialize the UART clock */ +uint32_t board_init_uart_clock(UART_Type *ptr); + +/* Initialize the CAM(camera) dot clock */ +uint32_t board_init_cam_clock(CAM_Type *ptr); + +/* Initialize the LCD pixel clock */ +uint32_t board_init_lcd_clock(void); + +uint32_t board_init_spi_clock(SPI_Type *ptr); + +uint32_t board_init_adc12_clock(ADC12_Type *ptr); + +uint32_t board_init_adc16_clock(ADC16_Type *ptr); + +uint32_t board_init_can_clock(CAN_Type *ptr); + +uint32_t board_init_i2s_clock(I2S_Type *ptr); +uint32_t board_init_pdm_clock(void); +uint32_t board_init_dao_clock(void); + +void board_init_sd_pins(SDXC_Type *ptr); +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); +bool board_sd_detect_card(SDXC_Type *ptr); + +void board_init_adc12_pins(void); +void board_init_adc16_pins(void); + +void board_init_usb_pins(void); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); + +void board_delay_ms(uint32_t ms); + +void board_timer_create(uint32_t ms, board_timer_cb cb); + +void board_init_rgb_pwm_pins(void); +void board_enable_output_rgb_led(uint8_t color); +void board_disable_output_rgb_led(uint8_t color); + +/* + * Keep mchtmr clock on low power mode + */ +void board_ungate_mchtmr_at_lp_mode(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c new file mode 100644 index 0000000000..44fdc7cce8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c @@ -0,0 +1,492 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ + +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + } else if (ptr == HPM_UART2) { + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD; + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD; + } else if (ptr == HPM_UART13) { + HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD; + HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; + } +} + +void init_lcd_pins(LCDC_Type *ptr) +{ + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1; + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_3; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_DIS0_R_4; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_DIS0_R_5; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_DIS0_R_6; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_7; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_G_0; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_1; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_DIS0_G_2; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_DIS0_G_3; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_DIS0_G_4; + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_DIS0_G_5; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_G_6; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_DIS0_G_7; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_B_0; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_1; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_2; + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_B_3; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_B_4; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_B_5; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_B_6; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_B_7; + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_CLK; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_EN; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_DIS0_VSYNC; + + /* PWM */ + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10; + /* RST */ + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_GPIO_B_16; +} + +void init_cap_pins(void) +{ + /* CAP_INT */ + HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPIO_B_08; + /* CAP_RST */ + HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09; +} + +void init_trgmux_pins(uint32_t pin) +{ + /* all trgmux pin ALT_SELECT fixed to 16*/ + HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); +} + +void init_i2c_pins_as_gpio(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + /* I2C0 */ + HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_GPIO_Z_11; + HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_GPIO_Z_10; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3; + } else { + while(1); + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2C0_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3; + HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else { + while(1); + } +} + +void init_sdram_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); +} + +void init_gpio_pins(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + +#ifdef USING_GPIO0_FOR_GPIOZ + HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; + HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; +#endif +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_SPI2_CSN; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_GPIO_E_31; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + +void init_pins(void) +{ + init_uart_pins(BOARD_CONSOLE_BASE); + init_sdram_pins(); +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR3) { + /* TMR3 compare 1 */ + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR3_COMP_1; + } + if (ptr == HPM_GPTMR4) { + /* TMR4 capture 1 */ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1; + } +} + +void init_hall_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_TRGM2_P_06; + HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_TRGM2_P_07; + HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_TRGM2_P_08; +} + +void init_qei_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_TRGM2_P_09; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; +} + +void init_i2s_pins(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PF02_FUNC_CTL_I2S0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_I2S0_MCLK; + HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_I2S0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_I2S0_BCLK; + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2S0_FCLK; + } +} + +void init_dao_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_DAOR_P; + HPM_IOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_DAOR_N; + /* PY port IO needs to configure PIOC */ + HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08; + HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_SOC_PY_09; +} + +void init_pdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK; + HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0; + /* PY port IO needs to configure PIOC */ + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11; +} + +void init_vad_pins(void) +{ + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT; +} + +void init_cam_pins(void) +{ + /* configure rst pin function */ + HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05; + /* PY port IO needs to configure PIOC */ + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SOC_PY_05; + + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK; + HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_CAM0_VSYNC; + HPM_IOC->PAD[IOC_PAD_PA05].FUNC_CTL = IOC_PA05_FUNC_CTL_CAM0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_CAM0_D_2; + HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_CAM0_D_3; + HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_CAM0_D_4; + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_CAM0_D_5; + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_CAM0_D_6; + HPM_IOC->PAD[IOC_PAD_PA04].FUNC_CTL = IOC_PA04_FUNC_CTL_CAM0_D_7; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_CAM0_D_8; + HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_CAM0_D_9; +} + +void init_butn_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED; +} + +void init_acmp_pins(void) +{ + /* configure to ACMP_COMP_1(ALT16) function */ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ACMP_COMP_1; + /* configure to CMP1_INP7 function */ + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* configure to CMP1_INN6 function */ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_enet_pins(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_GPIO_F_00; + + HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_ETH0_MDC; + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_ETH0_MDIO; + + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_ETH0_RXD_0; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_ETH0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_ETH0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_ETH0_RXD_3; + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_ETH0_RXCK; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_ETH0_RXDV; + + HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_ETH0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_ETH0_TXD_1; + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_ETH0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_ETH0_TXD_3; + HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_ETH0_TXCK; + HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_ETH0_TXEN; + } else if (ptr == HPM_ENET1) { + HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_GPIO_E_26; + + HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC; + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO; + + HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0; + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1; + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV; + + HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0; + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1; + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN; + + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK | IOC_PE16_FUNC_CTL_ETH1_REFCLK; + } +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM3) { + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_PWM3_P_6; + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_PWM3_P_7; + } else if (ptr == HPM_PWM2) { + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_PWM2_P_5; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_PWM2_P_4; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_PWM2_P_1; + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_PWM2_P_0; + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_PWM2_P_3; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_PWM2_P_2; + } +} + +void init_adc12_pins(void) +{ + /* ADC0/1/2.VIN7 */ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2.VIN10 */ + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2.VIN11 */ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc16_pins(void) +{ + /* ADC3.INA2 */ + HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_usb_pins(void) +{ + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10; + HPM_IOC->PAD[IOC_PAD_PF10].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; + HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + + /* USB1_ID */ + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07; + HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + + /* USB1_OC */ + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_GPIO_F_05; + HPM_IOC->PAD[IOC_PAD_PF05].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); +} + +void init_can_pins(CAN_Type *ptr) +{ + if (ptr == HPM_CAN0) { + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_CAN0_TXD; + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_CAN0_RXD; + } +} + +void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8) +{ + uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);; + uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_SDXC0) { + } else if (ptr == HPM_SDXC1) { + /* CLK */ + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; + + /* CMD */ + HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl; + HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl; + + /* DATA0 */ + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; + /* DATA1 */ + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; + /* DATA2 */ + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; + /* DATA3 */ + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; + + /* CDN */ + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; + HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = pad_ctl; + HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX; + + } +} + +void init_clk_obs_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; +} + +void init_rgb_pwm_pins(void) +{ + /* Red */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_TRGM1_P_01; + /* Green */ + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_TRGM0_P_06; + /* BLUE */ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_TRGM1_P_03; +} + +void init_led_pins_as_gpio(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; + HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; + HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h new file mode 100644 index 0000000000..11d6a0df91 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_uart_pins(UART_Type *ptr); +void init_lcd_pins(LCDC_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_cap_pins(void); +void init_sdram_pins(void); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_pins(void); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_i2s_pins(I2S_Type *ptr); +void init_dao_pins(void); +void init_pdm_pins(void); +void init_vad_pins(void); +void init_cam_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_enet_pins(ENET_Type *ptr); +void init_pwm_pins(PWM_Type *ptr); +void init_adc12_pins(void); +void init_adc16_pins(void); +void init_usb_pins(void); +void init_can_pins(CAN_Type *ptr); +void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8); +void init_adc_bldc_pins(void); +void init_rgb_pwm_pins(void); +void init_i2c_pins_as_gpio(I2C_Type *ptr); +void init_led_pins_as_gpio(void); +void init_trgmux_pins(uint32_t pin); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README.md new file mode 100644 index 0000000000..97e3a3e929 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README.md @@ -0,0 +1,86 @@ +# HPM6750EVKMINI + +## Overview + +The HPM6750 is a dual-core flashless MCU running 816Mhz. It has a 2MB continuous on-chip ram. Also, it provides various memory interfaces, including SDRAM, Quad SPI NOR Flash, SD/eMMC. It integrates rich audio and video interfaces, including LCD, pixel DMA, camera， and I2S audio interfaces. + + ![hpm6750evkmini](../../doc/images/boards/hpm6750evkmini/hpm6750evkmini.png "hpm6750evkmini") +## Hardware +- HPM6750IVM MCU (816Mhz, 2MB OCRAM) +- Onboard Memory + - 128Mb SDRAM + - 64Mb Quad SPI NOR Flash +- Display & Camera + - LCD connector + - Camera (DVP) +- WiFi + - RW007 over SPI +- USB + - USB type C (USB 2.0 OTG) connector x2 +- Audio + - Mic + - DAO +- Others + - TF Slot + - FT2232 + - Beeper + - RGB LED +- Expansion port + - ART-PI extension port +## DIP Switch S1 +- Bit 1 and 2 controls boot mode + +| bit[2:1] | Description| +|----------|------------| +|OFF, OFF| Boot from Quad SPI NOR flash | +|OFF, ON| Serial boot | +|ON, OFF| ISP | + +(lab_hpm6750_evkmini_board)= +## Button +(lab_hpm6750_evkmini_board_buttons)= +| Name | FUNCTIONS | +|----------|------------| +|PBUTN (S2) | Power Button, TinyUF2 Boot Button, GPIO Button | +|WBUTN (S3) | WAKE UP Button | +|RESET (S4) | Reset Button | + +## Pin Description + + +- SPI Pin + +| Function | Position | +| ---- | -------- | +| SPI2.CSN | P1[24] | +| SPI2.SCLK | P1[23] | +| SPI2.MISO | P1[21] | +| SPI2.MOSI | P1[19] | + +- I2C Pin： + +| Function | Position | +| ---- | -------- | +| I2C0.SCL | P1[13] | +| I2C0.SDA | P1[15] | + +- UART for core1 debug console： + +| Function | Position | +| ---- | -------- | +| UART13.TXD | P1[8] | +| UART13.RXD | P1[10] | + +- ACMP Pin + +| Function | Position | +| ---- | -------- | +| CMP.INN6 | P2[11] | +| CMP.COMP_1 | P1[7] | + +- GPTMR Pin + +| Function | Position | +| ---- | -------- | +| GPTMR2.CAPT_2 | P2[15] | +| GPTMR2.COMP_2 | P2[19] | \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README_zh.md new file mode 100644 index 0000000000..c17fe961ea --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/README_zh.md @@ -0,0 +1,86 @@ +# HPM6750EVKMINI开发板 + +## 概述 +HPM6750是一款主频达816Mhz的双核微控制器。该芯片拥有最大2M字节的连续片上RAM，并集成了丰富的存储接口，如SDRAM，Quad SPI NOR flash， SD/eMMC卡。同时它也提供多种音视频接口包括LCD显示，像素DMA，摄像头以及I2S音频接口。 + + ![hpm6750evkmini](../../doc/images/boards/hpm6750evkmini/hpm6750evkmini.png "hpm6750evkmini") +## 板上硬件资源 +- HPM6750IVM 微控制器 (主频816Mhz, 2MB片上内存) +- 板载存储 + - 128Mb SDRAM + - 64Mb Quad SPI NOR Flash +- 显示/摄像头 + - LCD接口 + - 摄像头(DVP)接口 +- WiFi + - RW007 +- USB + - USB type C (USB 2.0 OTG) connector x2 +- 音频 + - Mic + - DAO +- 其他 + - TF卡槽 + - FT2232 + - 蜂鸣器 + - RGB LED +- 扩展口 + - ART-PI +## 拨码开关 S1 +- Bit 1，2控制启动模式 + +| Bit[2:1] | 功能描述| +|----------|------------| +|OFF, OFF| Quad SPI NOR flash 启动 | +|OFF, ON| 串行启动 | +|ON, OFF| 在系统编程 | + +(lab_hpm6750_evkmini_board)= +## 按键 +(lab_hpm6750_evkmini_board_buttons)= +| 名称 | 功能 | +|----------|------------| +|PBUTN (S2) | 电源按键, TinyUF2 Boot按键, GPIO 按键| +|WBUTN (S3) | WAKE UP 按键| +|RESET (S4) | Reset 按键| + + +## 引脚描述 + + +- SPI引脚： + +| 功能 | 位置 | +| ---- | -------- | +| SPI2.CSN | P1[24] | +| SPI2.SCLK | P1[23] | +| SPI2.MISO | P1[21] | +| SPI2.MOSI | P1[19] | + +- I2C引脚： + +| 功能 | 位置 | +| ---- | -------- | +| I2C0.SCL | P1[13] | +| I2C0.SDA | P1[15] | + +- CORE1调试串口引脚： + +| 功能 | 位置 | +| ---- | -------- | +| UART13.TXD | P1[8] | +| UART13.RXD | P1[10] | + +- ACMP引脚 + +| 功能 | 位置 | +| ---- | -------- | +| CMP.INN6 | P2[11] | +| CMP.COMP_1 | P1[7] | + +- GPTMR引脚 + +| 功能 | 位置 | +| ---- | -------- | +| GPTMR2.CAPT_2 | P2[15] | +| GPTMR2.COMP_2 | P2[19] | \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript new file mode 100644 index 0000000000..7c742f69d0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.c b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.c new file mode 100644 index 0000000000..29c32bdd85 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.c @@ -0,0 +1,955 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_lcdc_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_debug_console.h" +#include "hpm_dram_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_sdxc_drv.h" +#include "hpm_sdxc_soc_drv.h" +#include "hpm_pllctl_drv.h" +#include "hpm_pwm_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if BOARD_CONSOLE_TYPE == console_type_uart + console_config_t cfg; + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t) BOARD_CONSOLE_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_BAUDRATE; + + init_uart_pins((UART_Type *) cfg.base); + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while(1); +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1)); + printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0)); + printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1)); + printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); + printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("display:\t %luHz\n", clock_get_frequency(clock_display)); + printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); + printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); + printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg)); + printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + init_uart_pins(ptr); +} + +void board_init_ahb(void) +{ + clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ +} + +void board_print_banner(void) +{ + const uint8_t banner[] = {"\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n"}; + printf("%s", banner); +} + +static void board_turnoff_rgb_led(void) +{ + uint8_t port_pin18_status; + uint8_t port_pin19_status; + uint8_t port_pin20_status; + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; + + HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; + + port_pin18_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 18); + port_pin19_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 19); + port_pin20_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 20); +/** + * hpm board evkmini Rev. B led light modification, resulting in two versions of rgb led processing different + * + */ + if ((port_pin18_status & port_pin19_status & port_pin20_status) == 0) { + /*Mini Rev B*/ + pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); + HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = pad_ctl; + } +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +void board_init(void) +{ + board_turnoff_rgb_led(); + board_init_clock(); + board_init_console(); + board_init_pmp(); + board_init_ahb(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_sdram_pins(void) +{ + init_sdram_pins(); +} + +uint32_t board_init_dram_clock(void) +{ + clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ + return clock_get_frequency(clock_dram); +} + +void board_power_cycle_lcd(void) +{ + /* turn off backlight */ + gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 0); + + board_delay_ms(150); + /* power recycle */ + gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 0); + board_delay_ms(20); + gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, 1); + board_delay_ms(150); + + /* turn on backlight */ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); + +} + +void board_init_lcd(void) +{ + board_init_lcd_clock(); + init_lcd_pins(BOARD_LCD_BASE); + board_power_cycle_lcd(); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + init_i2c_pins_as_gpio(ptr); + if (ptr == BOARD_CAP_I2C_BASE) { + gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN); + gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); + if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { + printf("CLK is low, please power cycle the board\n"); + while (1) {} + } + if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); + for (uint8_t i = 0; i < 3; i++) { + for (uint32_t j = 0; j < 9; j++) { + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN, 0); + board_delay_ms(10); + } + board_delay_ms(100); + } + printf("I2C bus is cleared\n"); + } +} + +void board_init_i2c(I2C_Type *ptr) +{ + hpm_stat_t stat; + uint32_t freq; + i2c_config_t config; + + board_i2c_bus_clear(ptr); + + init_i2c_pins(ptr); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); + stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t)BOARD_CAP_I2C_BASE); + while (1) {} + } +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART6) { + clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart6); + } else if (ptr == HPM_UART7) { + clock_set_source_divider(clock_uart7, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart7); + } else if (ptr == HPM_UART13) { + clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart13); + } else if (ptr == HPM_UART14) { + clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); + freq = clock_get_frequency(clock_uart14); + } else { + /* Not supported */ + } + return freq; +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + /* SPI2 clock configure */ + clock_add_to_group(clock_spi2, 0); + clock_set_source_divider(clock_spi2, clk_src_osc24m, 1U); + + return clock_get_frequency(clock_spi2); + } else { + return 0; + } +} + +void board_init_cap_touch(void) +{ + init_cap_pins(); + gpio_set_pin_output_with_initial(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 0); + gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + + board_delay_ms(1); + gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); + + gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); + board_init_i2c(BOARD_CAP_I2C_BASE); +} + + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); +} + +void board_led_toggle(void) +{ + static uint8_t i; + if(BOARD_LED_PULL_STATUS){ + /* hpm6750 Mini Rev A led configure*/ + gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_G_GPIO_PIN); + } + else{ + /* hpm6750 Mini Rev B led configure*/ + gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, ((1 << i)) << BOARD_G_GPIO_PIN); + } + i++; + i = i % 3; +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_init_cam_pins(void) +{ + init_cam_pins(HPM_CAM0); +} + +void board_init_usb_pins(void) +{ + /* set pull-up for USBx OC pin and ID pin */ + init_usb_pins(HPM_USB0); + + /* configure USBx ID pin as input function */ + gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); + + /* configure USBx OC Flag pin as input function */ + gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ +} + +void board_init_pmp(void) +{ + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + + uint32_t start_addr = (uint32_t) __noncacheable_start__; + uint32_t end_addr = (uint32_t) __noncacheable_end__; + uint32_t length = end_addr - start_addr; + + if (length == 0) { + return; + } + + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + + pmp_entry_t pmp_entry[1]; + pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + + pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctl_xtal_set_rampup_time(HPM_PLLCTL, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1); + } + + /* Add most Clocks to group 0 */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_axi0, 0); + clock_add_to_group(clock_axi1, 0); + clock_add_to_group(clock_axi2, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_xpi1, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_gptmr4, 0); + clock_add_to_group(clock_gptmr5, 0); + clock_add_to_group(clock_gptmr6, 0); + clock_add_to_group(clock_gptmr7, 0); + clock_add_to_group(clock_uart0, 0); + clock_add_to_group(clock_uart1, 0); + clock_add_to_group(clock_uart2, 0); + clock_add_to_group(clock_uart3, 0); + clock_add_to_group(clock_uart6, 0); + clock_add_to_group(clock_uart7, 0); + clock_add_to_group(clock_uart13, 0); + clock_add_to_group(clock_uart14, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_can2, 0); + clock_add_to_group(clock_can3, 0); + clock_add_to_group(clock_display, 0); + clock_add_to_group(clock_sdxc0, 0); + clock_add_to_group(clock_sdxc1, 0); + clock_add_to_group(clock_camera0, 0); + clock_add_to_group(clock_camera1, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_ref0, 0); + clock_add_to_group(clock_ref1, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_eth0, 0); + clock_add_to_group(clock_eth1, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_ram0, 0); + clock_add_to_group(clock_ram1, 0); + clock_add_to_group(clock_usb0, 0); + clock_add_to_group(clock_usb1, 0); + clock_add_to_group(clock_jpeg, 0); + clock_add_to_group(clock_pdma, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_mot1, 0); + clock_add_to_group(clock_mot2, 0); + clock_add_to_group(clock_mot3, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_dao, 0); + clock_add_to_group(clock_msyn, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); + + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_adc2, 0); + clock_add_to_group(clock_adc3, 0); + + clock_add_to_group(clock_i2s0, 0); + clock_add_to_group(clock_i2s1, 0); + clock_add_to_group(clock_i2s2, 0); + clock_add_to_group(clock_i2s3, 0); + + /* Add the CPU1 clock to Group1 */ + clock_add_to_group(clock_mchtmr1, 1); + clock_add_to_group(clock_mbx1, 1); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { + printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); + while(1); + } + + clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); + clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); + + clock_update_core_clock(); +} + +uint32_t board_init_cam_clock(CAM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAM0) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_camera0); + } else if (ptr == HPM_CAM1) { + /* Configure camera clock to 24MHz */ + clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U); + freq = clock_get_frequency(clock_camera1); + } else { + /* Invalid camera instance */ + } + return freq; +} + +uint32_t board_init_lcd_clock(void) +{ + uint32_t freq; + clock_add_to_group(clock_display, 0); + /* Configure LCDC clock to 29.7MHz */ + clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U); + freq = clock_get_frequency(clock_display); + return freq; +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr) +{ + uint32_t freq = 0; + switch ((uint32_t) ptr) { + case HPM_ADC0_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc0); + break; + case HPM_ADC1_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc1); + break; + case HPM_ADC2_BASE: + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc2); + break; + default: + /* Invalid ADC instance */ + break; + } + + return freq; +} + +uint32_t board_init_dao_clock(void) +{ + clock_add_to_group(clock_dao, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_dao); +} + +uint32_t board_init_pdm_clock(void) +{ + clock_add_to_group(clock_pdm, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_pdm); +} + +uint32_t board_init_i2s_clock(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + return clock_get_frequency(clock_i2s0); + } else { + return 0; + } +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_ADC3) { + /* Configure the ADC clock to 200MHz */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} + +void board_init_can(CAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(CAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_CAN0) { + /* Set the CAN0 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_CAN1) { + /* Set the CAN1 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can1); + } else if (ptr == HPM_CAN2) { + /* Set the CAN2 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can2); + } else if (ptr == HPM_CAN3) { + /* Set the CAN3 peripheral clock to 80MHz */ + clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5); + freq = clock_get_frequency(clock_can3); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +#ifdef INIT_EXT_RAM_FOR_DATA +/* + * this function will be called during startup to initialize external memory for data use + */ +void _init_ext_ram(void) +{ + uint32_t dram_clk_in_hz; + board_init_sdram_pins(); + dram_clk_in_hz = board_init_dram_clock(); + + dram_config_t config = {0}; + dram_sdram_config_t sdram_config = {0}; + + dram_default_config(HPM_DRAM, &config); + config.dqs = DRAM_DQS_INTERNAL; + dram_init(HPM_DRAM, &config); + + sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.prescaler = 0x3; + sdram_config.burst_len_in_byte = 8; + sdram_config.auto_refresh_count_in_one_burst = 1; + sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + + sdram_config.precharge_to_act_in_ns = 18; /* Trp */ + sdram_config.act_to_rw_in_ns = 18; /* Trcd */ + sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */ + sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */ + sdram_config.cke_off_in_ns = 42; /* Trcd */ + sdram_config.act_to_precharge_in_ns = 42; /* Tras */ + + sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */ + sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ + sdram_config.act_to_act_in_ns = 12; /* Trrd */ + sdram_config.idle_timeout_in_ns = 6; + sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + + sdram_config.cs = BOARD_SDRAM_CS; + sdram_config.base_address = BOARD_SDRAM_ADDRESS; + sdram_config.size_in_byte = BOARD_SDRAM_SIZE; + sdram_config.port_size = BOARD_SDRAM_PORT_SIZE; + sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; + sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; + sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; + sdram_config.delay_cell_value = 29; + + dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); +} +#endif + +void board_init_sd_pins(SDXC_Type *ptr) +{ + if (ptr == HPM_SDXC1) { + init_sdxc_pins(ptr, false); + } else { + while (1) { + + } + } +} + + +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) +{ + uint32_t actual_freq = 0; + do { + if (ptr != HPM_SDXC1) { + break; + } + clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; + sdxc_enable_inverse_clock(ptr, false); + sdxc_enable_sd_clock(ptr, false); + /* Configure the clock below 400KHz for the identification state */ + if (freq <= 400000UL) { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 63); + } + /* configure the clock to 24MHz for the SDR12/Default speed */ + else if (freq <= 25000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); + } + /* Configure the clock to 50MHz for the SDR25/High speed/50MHz DDR/50MHz SDR */ + else if (freq <= 50000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 8); + } + /* Configure the clock to 100MHz for the SDR50 */ + else if (freq <= 100000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4); + } + /* Configure the clock to 166MHz for SDR104/HS200/HS400 */ + else if (freq <= 208000000UL) { + clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2); + } + /* For other unsupported clock ranges, configure the clock to 24MHz */ + else { + clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1); + } + sdxc_enable_inverse_clock(ptr, true); + sdxc_enable_sd_clock(ptr, true); + actual_freq = clock_get_frequency(sdxc_clk); + } while (false); + + return actual_freq; +} + +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) +{ + sdxc_select_voltage(ptr, sdxc_bus_voltage_sd_1v8); + init_sdxc_pins(ptr, true); +} + +bool board_sd_detect_card(SDXC_Type *ptr) +{ + return sdxc_is_card_inserted(ptr); +} + +void board_init_rgb_pwm_pins(void) +{ + init_led_pins_as_pwm(); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + pwm_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); + break; + case BOARD_RGB_GREEN: + pwm_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); + break; + case BOARD_RGB_BLUE: + pwm_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); + break; + default: + while (1) { + ; + } + } +} + +void board_enable_output_rgb_led(uint8_t color) +{ + switch (color) { + case BOARD_RGB_RED: + pwm_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); + break; + case BOARD_RGB_GREEN: + pwm_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); + break; + case BOARD_RGB_BLUE: + pwm_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); + break; + default: + while (1) { + ; + } + } +} + +void board_init_beep_pwm_pins(void) +{ + init_beep_pwm_pins(); +} + +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */ + } else if (ptr == HPM_ENET1) { + clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */ + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) +{ + if (internal == false) { + return status_success; + } + /* Configure Enet clock to output reference clock */ + if (ptr == HPM_ENET0) { + /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet0 */ + clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); + } else if (ptr == HPM_ENET1) { + /* make sure pll2_clk1 output clock at 250MHz then set 50MHz for enet1 */ + clock_set_source_divider(clock_eth1, clk_src_pll2_clk1, 5); /* set 50MHz for enet1 */ + } else { + return status_invalid_argument; + } + return status_success; +} + +void board_init_adc12_pins(void) +{ + init_adc12_pins(); +} + +void board_init_adc16_pins(void) +{ + init_adc16_pins(); +} + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr) +{ + init_enet_pins(ptr); + + if (ptr == HPM_ENET1) { + gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1); + } else { + return status_invalid_argument; + } + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.h b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.h new file mode 100644 index 0000000000..e61ab02a64 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/board.h @@ -0,0 +1,514 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "hpm_clock_drv.h" +#include "pinmux.h" + +#define BOARD_NAME "hpm6750evkmini" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +/* uart section */ +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART0 +#define BOARD_APP_UART_IRQ IRQn_UART0 +#else +#ifndef BOARD_APP_UART_IRQ +#warning no IRQ specified for applicaiton uart +#endif +#endif + +/* uart rx idle demo section */ +#define BOARD_UART_IDLE HPM_UART7 +#define BOARD_UART_IDLE_DMA_SRC HPM_DMA_SRC_UART7_RX + +#define BOARD_UART_IDLE_TRGM HPM_TRGM2 +#define BOARD_UART_IDLE_TRGM_PIN IOC_PAD_PD19 +#define BOARD_UART_IDLE_TRGM_INPUT_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_IN HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 +#define BOARD_UART_IDLE_TRGM_OUTPUT_GPTMR_SYNCI HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI + +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr4 +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR4 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart0 + +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE console_type_uart +#endif + +#if BOARD_CONSOLE_TYPE == console_type_uart +#ifndef BOARD_CONSOLE_BASE +#if BOARD_RUNNING_CORE == HPM_CORE0 +#define BOARD_CONSOLE_BASE HPM_UART0 +#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#else +#define BOARD_CONSOLE_BASE HPM_UART13 +#define BOARD_CONSOLE_CLK_NAME clock_uart13 +#endif +#endif +#define BOARD_CONSOLE_BAUDRATE (115200UL) +#endif + +#define BOARD_FREEMASTER_UART_BASE HPM_UART0 +#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0 +#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0 + +/* sdram section */ +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (16*SIZE_1MB) +#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_REFRESH_COUNT (4096UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (2UL) + +/* lcd section */ +#define BOARD_LCD_BASE HPM_LCDC +#define BOARD_LCD_IRQ IRQn_LCDC_D0 +#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_POWER_GPIO_PIN 12 +#define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 23 + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 +#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 + +#define BOARD_CAM_I2C_BASE HPM_I2C0 +#define BOARD_CAM_I2C_CLK_NAME clock_i2c0 + +#define BOARD_CAP_I2C_BASE (HPM_I2C0) +#define BOARD_CAP_I2C_CLK_NAME clock_i2c0 +#define BOARD_CAP_RST_GPIO (HPM_GPIO0) +#define BOARD_CAP_RST_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_RST_GPIO_PIN (9) +#define BOARD_CAP_RST_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_INTR_GPIO (HPM_GPIO0) +#define BOARD_CAP_INTR_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_INTR_GPIO_PIN (8) +#define BOARD_CAP_INTR_GPIO_IRQ (IRQn_GPIO0_B) +#define BOARD_CAP_I2C_SDA_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_I2C_SDA_GPIO_PIN (10) +#define BOARD_CAP_I2C_CLK_GPIO_INDEX (GPIO_DI_GPIOB) +#define BOARD_CAP_I2C_CLK_GPIO_PIN (11) + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR2 +#define BOARD_GPTMR_IRQ IRQn_GPTMR2 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_PWM HPM_GPTMR2 +#define BOARD_GPTMR_PWM_CHANNEL 0 + +/* gpio section */ +#define BOARD_R_GPIO_CTRL HPM_GPIO0 +#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_R_GPIO_PIN 19 +#define BOARD_G_GPIO_CTRL HPM_GPIO0 +#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_G_GPIO_PIN 18 +#define BOARD_B_GPIO_CTRL HPM_GPIO0 +#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_B_GPIO_PIN 20 + +#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL +#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX +#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN + +/* + *led Internal pull-up and pull-down resistance direction + *The configurations of Rev-A / B boards are different + */ +#define BOARD_LED_PULL_STATUS IOC_PAD_PAD_CTL_PS_GET(HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL) +#define BOARD_LED_OFF_LEVEL BOARD_LED_PULL_STATUS +#define BOARD_LED_ON_LEVEL !BOARD_LED_PULL_STATUS + +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ +#define BOARD_APP_GPIO_PIN 2 + +/* pinmux section */ +#define USING_GPIO0_FOR_GPIOZ +#ifndef USING_GPIO0_FOR_GPIOZ +#define BOARD_APP_GPIO_CTRL HPM_BGPIO +#define BOARD_APP_GPIO_IRQ IRQn_BGPIO +#else +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z +#endif + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI2 +#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) +#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX +#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX +#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PB24 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00000000U) + +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (8 << 20) + +/* lcd section */ +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH (800) +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT (480) +#endif + +/* pdma section */ +#define BOARD_PDMA_BASE HPM_PDMA + +/* i2s section */ +#define BOARD_APP_I2S_CLK_NAME clock_i2s1 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 + + +/* enet section */ +#define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOD +#define BOARD_ENET_RMII_RST_GPIO_PIN (15U) +#define BOARD_ENET_RMII HPM_ENET1 +#define BOARD_ENET_RMII_INT_REF_CLK (0U) +#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) + +/* adc section */ +#define BOARD_APP_ADC12_NAME "ADC0" +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC12_CH_1 (7U) + +#define BOARD_APP_ADC16_NAME "ADC3" +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC16_CH_1 (2U) + +#define BOARD_APP_ADC_TRIG_PWMT0 HPM_PWM0 +#define BOARD_APP_ADC_TRIG_PWMT1 HPM_PWM1 +#define BOARD_APP_ADC_TRIG_TRGM0 HPM_TRGM0 +#define BOARD_APP_ADC_TRIG_TRGM1 HPM_TRGM1 +#define BOARD_APP_ADC_TRIG_PWM_SYNC HPM_SYNT + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_CAN1 +#define BOARD_APP_CAN_IRQn IRQn_CAN1 + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR7) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr7) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR7) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) + +/* timer for 1ms*/ +#define BOARD_TMR_1MS HPM_GPTMR2 +#define BOARD_TMR_1MS_CH 0 +#define BOARD_TMR_1MS_CMP 0 +#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 +#define BOARD_TMR_1MS_RELOAD (100000U) + +/* SDXC section */ +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (1) +#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) +#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO (0) +#if BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO +#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO NULL +#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX 0 +#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 0 +#endif + +/* USB section */ +#define BOARD_USB0_ID_PORT (HPM_GPIO0) +#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) +#define BOARD_USB0_ID_GPIO_PIN (10) + +#define BOARD_USB0_OC_PORT (HPM_GPIO0) +#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) +#define BOARD_USB0_OC_GPIO_PIN (8) + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 4 +#define BOARD_APP_PWM_OUT2 5 +#define BOARD_APP_TRGM HPM_TRGM0 + +/* RGB LED Section */ +#define BOARD_RED_PWM_IRQ IRQn_PWM1 +#define BOARD_RED_PWM HPM_PWM1 +#define BOARD_RED_PWM_OUT 0 +#define BOARD_RED_PWM_CMP 0 +#define BOARD_RED_PWM_CMP_INITIAL_ZERO true +#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_GREEN_PWM_IRQ IRQn_PWM1 +#define BOARD_GREEN_PWM HPM_PWM1 +#define BOARD_GREEN_PWM_OUT 1 +#define BOARD_GREEN_PWM_CMP 1 +#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true +#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 + +#define BOARD_BLUE_PWM_IRQ IRQn_PWM0 +#define BOARD_BLUE_PWM HPM_PWM0 +#define BOARD_BLUE_PWM_OUT 7 +#define BOARD_BLUE_PWM_CMP 0 +#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true +#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 + +#define BOARD_RGB_RED 0 +#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) +#define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) + +/* Beep Section */ +#define BOARD_BEEP_PWM HPM_PWM3 +#define BOARD_BEEP_PWM_OUT 4 +#define BOARD_BEEP_PWM_CLOCK_NAME clock_mot3 + +/*BLDC pwm*/ + +/*PWM define*/ +#define BOARD_BLDCPWM HPM_PWM1 +#define BOARD_BLDC_UH_PWM_OUTPIN (2U) +#define BOARD_BLDC_UL_PWM_OUTPIN (3U) +#define BOARD_BLDC_VH_PWM_OUTPIN (4U) +#define BOARD_BLDC_VL_PWM_OUTPIN (5U) +#define BOARD_BLDC_WH_PWM_OUTPIN (6U) +#define BOARD_BLDC_WL_PWM_OUTPIN (7U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM1 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM1 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) + +/*HALL define*/ + +#define BOARD_BLDC_HALL_BASE HPM_HALL2 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM2 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL2 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P9 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P10 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P11 +#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) + + + +/*QEI*/ + +#define BOARD_BLDC_QEI_BASE HPM_QEI2 +#define BOARD_BLDC_QEI_IRQ IRQn_QEI2 +#define BOARD_BLDC_QEI_TRGM HPM_TRGM2 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P6 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM2_INPUT_SRC_TRGM2_P7 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot2 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +/*Timer define*/ + +#define BOARD_TMR_1MS HPM_GPTMR2 +#define BOARD_TMR_1MS_CH 0 +#define BOARD_TMR_1MS_CMP 0 +#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 +#define BOARD_TMR_1MS_RELOAD (100000U) + +#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS +#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH +#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP +#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ +#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_TRIG_FLAG adc12_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (1U) +#define BOARD_BLDC_ADC_CH_V (2U) +#define BOARD_BLDC_ADC_CH_W (3U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG1A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM1_INPUT_SRC_PWM1_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 + + +#define BOARD_CPU_FREQ (816000000UL) + +#define BOARD_APP_DISPLAY_CLOCK clock_display + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE 0 +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); + +void board_init_uart(UART_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_lcd(void); + +void board_init_can(CAN_Type *ptr); + +uint32_t board_init_dram_clock(void); + +void board_init_sdram_pins(void); +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +void board_init_led_pins(void); + +/* cap touch */ +void board_init_cap_touch(void); + +void board_led_write(uint8_t state); +void board_led_toggle(void); + +void board_fpga_power_enable(void); + +void board_init_cam_pins(void); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); + +/* Initialize the UART clock */ +uint32_t board_init_uart_clock(UART_Type *ptr); + +/* Initialize the CAM(camera) dot clock */ +uint32_t board_init_cam_clock(CAM_Type *ptr); + +/* Initialize the LCD pixel clock */ +uint32_t board_init_lcd_clock(void); + +uint32_t board_init_spi_clock(SPI_Type *ptr); + +uint32_t board_init_adc12_clock(ADC12_Type *ptr); + +uint32_t board_init_adc16_clock(ADC16_Type *ptr); + +uint32_t board_init_can_clock(CAN_Type *ptr); + +uint32_t board_init_i2s_clock(I2S_Type *ptr); +uint32_t board_init_pdm_clock(void); +uint32_t board_init_dao_clock(void); + +void board_init_sd_pins(SDXC_Type *ptr); +uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); +void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); +bool board_sd_detect_card(SDXC_Type *ptr); + +void board_init_adc12_pins(void); +void board_init_adc16_pins(void); + +void board_init_usb_pins(void); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); + +void board_delay_ms(uint32_t ms); + +void board_init_beep_pwm_pins(void); +void board_init_rgb_pwm_pins(void); + +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_enable_output_rgb_led(uint8_t color); +void board_disable_output_rgb_led(uint8_t color); + +/* + * Keep mchtmr clock on low power mode + */ +void board_ungate_mchtmr_at_lp_mode(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c new file mode 100644 index 0000000000..0dc8b5ffde --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ + +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + } else if (ptr == HPM_UART6) { + HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_UART6_RXD; + HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_UART6_TXD; + } else if (ptr == HPM_UART7) { + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_UART7_RXD; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_UART7_TXD; + } else if (ptr == HPM_UART13) { + HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD; + HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; + HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; + } else if (ptr == HPM_UART14) { + HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_UART14_RXD; + HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_UART14_TXD; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_SOC_PZ_10; + HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_SOC_PZ_11; + } +} + +void init_lcd_pins(LCDC_Type *ptr) +{ + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_DIS0_R_0; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_DIS0_R_1; + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_DIS0_R_2; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_DIS0_R_3; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_DIS0_R_4; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_DIS0_R_5; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_DIS0_R_6; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_DIS0_R_7; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_DIS0_G_0; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_DIS0_G_1; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_DIS0_G_2; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_DIS0_G_3; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_DIS0_G_4; + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_DIS0_G_5; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_DIS0_G_6; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_DIS0_G_7; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_DIS0_B_0; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_DIS0_B_1; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_DIS0_B_2; + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_DIS0_B_3; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_DIS0_B_4; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_DIS0_B_5; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_DIS0_B_6; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_DIS0_B_7; + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_DIS0_CLK; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_DIS0_EN; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_DIS0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_DIS0_VSYNC; + + /* PWM */ + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23; + /* PWR */ + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; +} + +void init_cap_pins(void) +{ + /* CAP_INT */ + HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPIO_B_08; + /* CAP_RST */ + HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPIO_B_09; +} + +void init_trgmux_pins(uint32_t pin) +{ + /* all trgmux pin ALT_SELECT fixed to 16*/ + HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); +} + +void init_i2c_pins_as_gpio(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + /* I2C0 */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10; + } else { + while(1); + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2C0_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PB10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else if (ptr == HPM_I2C3) { + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_I2C3_SCL + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_I2C3_SDA + | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB14].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else { + while(1); + } +} + +void init_sdram_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_DRAM_DQ_14; + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_DRAM_DQ_15; + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_DRAM_DQ_12; + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_DRAM_DQ_13; + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_DRAM_DQ_00; + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_DRAM_DQ_10; + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_DRAM_DQ_11; + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_DRAM_DQ_01; + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_DRAM_DQ_08; + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_DRAM_DQ_09; + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_DRAM_DQ_04; + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_DRAM_DQ_03; + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_DRAM_DQ_02; + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_DRAM_DQ_07; + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_DRAM_DQ_06; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_DRAM_DQ_05; + + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_DRAM_A_11; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_DRAM_A_09; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_DRAM_A_10; + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_DRAM_A_08; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_DRAM_A_07; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_DRAM_A_06; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_DRAM_A_01; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_DRAM_A_00; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_DRAM_A_05; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_DRAM_A_04; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_DRAM_A_03; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_DRAM_A_02; + + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_DRAM_BA1; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_DRAM_BA0; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_DRAM_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_DRAM_CLK; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_DRAM_CKE; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_DRAM_CS_0; + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_DRAM_RAS; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_DRAM_CAS; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_DRAM_WE; + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_DRAM_DM_0; + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_DRAM_DM_1; +} + +void init_gpio_pins(void) +{ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + /* Green LED*/ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; + HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; + +#ifdef USING_GPIO0_FOR_GPIOZ + HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; + HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; + /* PZ port IO needs to configure BIOC as well */ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; +#endif +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_SPI1_CSN; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_SPI2_CSN; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI3) { + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_SPI3_CSN; + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_GPIO_E_03; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_SPI2_MOSI; + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } else if (ptr == HPM_SPI3) { + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_GPIO_B_29; + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_SPI3_MOSI; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SPI3_MISO; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + } +} + +void init_pins(void) +{ + init_uart_pins(BOARD_CONSOLE_BASE); + init_sdram_pins(); +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR2) { + /* TMR2 capture 0 */ + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_GPTMR2_CAPT_0; + /* TMR2 compare 0 */ + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_GPTMR2_COMP_0; + } +} + +void init_hall_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_TRGM2_P_09; + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_TRGM2_P_11; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; +} + +void init_qei_trgm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_TRGM2_P_06; + HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_TRGM2_P_07; +} + +void init_i2s_pins(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_I2S0_MCLK; + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_I2S0_FCLK; + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_I2S0_BCLK; + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_I2S0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_I2S0_TXD_1; + } +} + +void init_dao_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_DAOR_P; + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_DAOR_N; +} + +void init_pdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK; + HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11; +} + +void init_vad_pins(void) +{ + HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_VAD_CLK; + HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_VAD_DAT; +} + +void init_cam_pins(CAM_Type *ptr) +{ + if (ptr == HPM_CAM0) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK; + HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_CAM0_VSYNC; + HPM_IOC->PAD[IOC_PAD_PA05].FUNC_CTL = IOC_PA05_FUNC_CTL_CAM0_HSYNC; + HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_CAM0_D_2; + HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_CAM0_D_3; + HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_CAM0_D_4; + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_CAM0_D_5; + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_CAM0_D_6; + HPM_IOC->PAD[IOC_PAD_PA04].FUNC_CTL = IOC_PA04_FUNC_CTL_CAM0_D_7; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_CAM0_D_8; + HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_CAM0_D_9; + } +} + +void init_butn_pins(void) +{ + HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; + HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_PLED; + HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_WLED; +} + +void init_acmp_pins(void) +{ + /* configure to ACMP_COMP_1(ALT16) function */ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ACMP_COMP_1; + /* configure to CMP1_INP7 function */ + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* configure to CMP1_INN6 function */ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_enet_pins(ENET_Type *ptr) +{ + if (ptr == HPM_ENET1) { + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15; + + HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH1_MDC; + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_ETH1_MDIO; + + HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PE18_FUNC_CTL_ETH1_RXD_1; + HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH1_TXD_0; + HPM_IOC->PAD[IOC_PAD_PE20].FUNC_CTL = IOC_PE20_FUNC_CTL_ETH1_RXD_0; + + HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_ETH1_TXEN; + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_ETH1_RXDV; + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH1_TXD_1; + + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK | IOC_PE16_FUNC_CTL_ETH1_REFCLK; + } +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM0) { + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_PWM0_P_7; + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_PWM0_P_6; + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_PWM0_P_5; + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_PWM0_P_4; + } else if (ptr == HPM_PWM1) { + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_PWM1_P_3; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_PWM1_P_2; + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_PWM1_P_5; + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_PWM1_P_4; + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_PWM1_P_7; + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_PWM1_P_6; + } else if (ptr == HPM_PWM3) { + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_PWM3_P_4; + } +} + +void init_adc12_pins(void) +{ + /* ADC0/1/2/.VINP7 */ + HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2/.VINP8 */ + HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2/.VINP9 */ + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0/1/2/.VINP10 */ + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc16_pins(void) +{ + /* ADC3.INA2 */ + HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_usb_pins(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + /* USB0 ID */ + HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10; + HPM_IOC->PAD[IOC_PAD_PF10].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + + /* USB0 OC */ + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; + HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + } +} + +void init_can_pins(CAN_Type *ptr) +{ + if (ptr == HPM_CAN1) { + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_CAN1_TXD; + HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_CAN1_RXD; + } +} + +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) +{ + uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | + IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_SDXC1) { + /* SDXC1.CLK */ + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD22].PAD_CTL = pad_ctl; + + /* SDXC1.CMD */ + HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = cmd_func_ctl; + HPM_IOC->PAD[IOC_PAD_PD21].PAD_CTL = pad_ctl; + + /* SDXC1.DATA0 */ + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; + /* SDXC1.DATA1 */ + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; + /* SDXC1.DATA2 */ + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD27].PAD_CTL = pad_ctl; + /* SDXC1.DATA3 */ + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = func_ctl; + HPM_IOC->PAD[IOC_PAD_PD26].PAD_CTL = pad_ctl; + + /* SDXC1.CDN */ + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_SDC1_CDN; + HPM_IOC->PAD[IOC_PAD_PD28].PAD_CTL = pad_ctl; + } + + /* SDXC1.VSEL */ + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_SDC1_VSEL; + HPM_IOC->PAD[IOC_PAD_PD29].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + +void init_clk_obs_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; +} + +void init_wifi_pins(void) +{ + /* WiFi INT */ + HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_GPIO_E_01; + HPM_IOC->PAD[IOC_PAD_PE01].PAD_CTL = IOC_PAD_PAD_CTL_PE_MASK | IOC_PAD_PAD_CTL_PS_MASK; + /* WiFi RST */ + HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_GPIO_E_02; + + init_spi_pins(HPM_SPI0); +} + +void init_beep_pwm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_PWM3_P_4; +} + +void init_led_pins_as_pwm(void) +{ + /* Blue */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_PWM0_P_7; + /* Green */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_PWM1_P_1; + /* Red */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM1_P_0; +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h new file mode 100644 index 0000000000..f772a0fc31 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H +#include "hpm_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif +void init_uart_pins(UART_Type *ptr); +void init_lcd_pins(LCDC_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_cap_pins(void); +void init_sdram_pins(void); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_pins(void); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_i2s_pins(I2S_Type *ptr); +void init_dao_pins(void); +void init_pdm_pins(void); +void init_vad_pins(void); +void init_cam_pins(CAM_Type *ptr); +void init_fpga_power_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_enet_pins(ENET_Type *ptr); +void init_pwm_pins(PWM_Type *ptr); +void init_adc_pins(void); +void init_usb_pins(USB_Type *ptr); +void init_can_pins(CAN_Type *ptr); +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); +void init_adc12_pins(void); +void init_adc16_pins(void); +void init_adc_bldc_pins(void); + +void init_i2c_pins_as_gpio(I2C_Type *ptr); + +void init_beep_pwm_pins(void); +void init_led_pins_as_pwm(void); +void init_led_pins_as_gpio(void); +void init_trgmux_pins(uint32_t pin); +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/index.md b/bsp/hpmicro/libraries/hpm_sdk/boards/index.md new file mode 100644 index 0000000000..06e9ecf9ca --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/index.md @@ -0,0 +1,41 @@ +# HPM Development Board Introduction + +This chapter describes the board-related configuration + +:::{eval-rst} +.. toctree:: + :maxdepth: 3 + :numbered: + + hpm6750evk/README + hpm6750evkmini/README + hpm6300evk/README + ../doc/boards/README + +::: + +**Board level vocabulary cross-reference table** + +(lab_board_resource)= + +:::{tab} HPM6750EVK +Click [here](lab_hpm6750_evk_board) to view the HPM6750EVK development board +::: +:::{tab} HPM6750EVKMINI +Click [here](lab_hpm6750_evkmini_board) to view the HPM6750EVKMINI development board +::: +:::{tab} HPM6300EVK +Click [here](lab_hpm6300_evk_board) to view the HPM6300EVK development board +::: + +(lab_board_lcd_pin)= +(lab_board_app_i2c_pin)= +(lab_board_cam_i2c_pin)= +(lab_board_cap_i2c_pin)= +(lab_board_rgb_pin)= +(lab_board_app_spi_pin)= +(lab_board_drv_pwm_pin)= +(lab_board_motor_ctrl_pin)= +(lab_board_overiew)= +(lab_board_app_acmp_pin)= +(lab_board_app_gptmr_pin)= diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/index_zh.md b/bsp/hpmicro/libraries/hpm_sdk/boards/index_zh.md new file mode 100644 index 0000000000..138303ea94 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/index_zh.md @@ -0,0 +1,38 @@ +# HPM 开发板介绍 + +:::{eval-rst} +.. toctree:: + :maxdepth: 3 + :numbered: + + hpm6750evk/README_zh + hpm6750evkmini/README_zh + hpm6300evk/README_zh + ../doc/boards/README_zh + +::: + +**开发板引脚对照表** + +:::{tab} HPM6750EVK +点击{ref}`此处 `查看HPM6750EVK开发板 +::: +:::{tab} HPM6750EVKMINI +点击{ref}`此处 `查看HPM6750EVKMINI开发板 +::: +:::{tab} HPM6300EVK +点击{ref}`此处 `查看HPM6300EVK开发板 +::: + +(lab_board_resource)= +(lab_board_lcd_pin)= +(lab_board_app_i2c_pin)= +(lab_board_cam_i2c_pin)= +(lab_board_cap_i2c_pin)= +(lab_board_rgb_pin)= +(lab_board_app_spi_pin)= +(lab_board_drv_pwm_pin)= +(lab_board_motor_ctrl_pin)= +(lab_board_overiew)= +(lab_board_app_acmp_pin)= +(lab_board_app_gptmr_pin)= diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6300evk.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6300evk.cfg new file mode 100644 index 0000000000..bca3b8dc16 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6300evk.cfg @@ -0,0 +1,253 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +proc init_sdram { } { +# configure dram frequency +# 133Mhz pll1_clk0: 266Mhz divide by 2 + #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x201 +# 166Mhz pll2_clk0: 333Mhz divide by 2 + $::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x401 + + # PD13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040368 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040360 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040350 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040348 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040340 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040338 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040330 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040328 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040320 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040318 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040310 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040308 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040300 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC29 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC28 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC27 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC22 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC21 + $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC17 + $::_TARGET0 riscv dmi_write 0x39 0xF4040288 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC15 + $::_TARGET0 riscv dmi_write 0x39 0xF4040278 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040260 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC11 + $::_TARGET0 riscv dmi_write 0x39 0xF4040258 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040250 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040248 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040240 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040238 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040230 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040228 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040220 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC14 + $::_TARGET0 riscv dmi_write 0x39 0xF4040270 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040268 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC16 + # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 + $::_TARGET0 riscv dmi_write 0x3C 0x1000C + # PC26 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC25 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040298 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040290 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC23 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC24 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC30 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC31 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040210 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040218 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # dramc configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + sleep 10 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + $::_TARGET0 riscv dmi_write 0x39 0xF3050008 + $::_TARGET0 riscv dmi_write 0x3C 0x30524 + $::_TARGET0 riscv dmi_write 0x39 0xF305000C + $::_TARGET0 riscv dmi_write 0x3C 0x6030524 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x10000000 + + # 32MB + $::_TARGET0 riscv dmi_write 0x39 0xF3050010 + $::_TARGET0 riscv dmi_write 0x3C 0x4000001b + $::_TARGET0 riscv dmi_write 0x39 0xF3050014 + $::_TARGET0 riscv dmi_write 0x3C 0 + # 16-bit + $::_TARGET0 riscv dmi_write 0x39 0xF3050040 + $::_TARGET0 riscv dmi_write 0x3C 0xf31 + + # 133Mhz configuration + #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + # 166Mhz configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e33 + + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020300 + + # config delay cell + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x3b + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x203b + + $::_TARGET0 riscv dmi_write 0x39 0xF3050094 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3050098 + $::_TARGET0 riscv dmi_write 0x3C 0 + + # precharge all + $::_TARGET0 riscv dmi_write 0x39 0xF3050090 + $::_TARGET0 riscv dmi_write 0x3C 0x40000000 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + # auto refresh + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + # set mode + $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 + $::_TARGET0 riscv dmi_write 0x3C 0x33 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020301 + echo "SDRAM has been initialized" +} + +$_TARGET0 configure -event reset-init { + init_clock + init_sdram +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evk.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evk.cfg new file mode 100644 index 0000000000..9f15d4c2ec --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evk.cfg @@ -0,0 +1,345 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3040000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +proc init_sdram { } { +# configure dram frequency +# 133Mhz pll1_clk0: 266Mhz divide by 2 + #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x201 +# 166Mhz pll2_clk0: 333Mhz divide by 2 + $::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x401 + # PC01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040208 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040200 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB31 + $::_TARGET0 riscv dmi_write 0x39 0xF40401F8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB30 + $::_TARGET0 riscv dmi_write 0x39 0xF40401F0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB29 + $::_TARGET0 riscv dmi_write 0x39 0xF40401E8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB28 + $::_TARGET0 riscv dmi_write 0x39 0xF40401E0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB27 + $::_TARGET0 riscv dmi_write 0x39 0xF40401D8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB26 + $::_TARGET0 riscv dmi_write 0x39 0xF40401D0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB25 + $::_TARGET0 riscv dmi_write 0x39 0xF40401C8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB24 + $::_TARGET0 riscv dmi_write 0x39 0xF40401C0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB23 + $::_TARGET0 riscv dmi_write 0x39 0xF40401B8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB22 + $::_TARGET0 riscv dmi_write 0x39 0xF40401B0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB21 + $::_TARGET0 riscv dmi_write 0x39 0xF40401A8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB20 + $::_TARGET0 riscv dmi_write 0x39 0xF40401A0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040198 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PB18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040190 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PD13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040368 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040360 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040350 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040348 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040340 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040338 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040330 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040328 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040320 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040318 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040310 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040308 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040300 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC29 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC28 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC27 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC22 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC21 + $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC17 + $::_TARGET0 riscv dmi_write 0x39 0xF4040288 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC15 + $::_TARGET0 riscv dmi_write 0x39 0xF4040278 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040260 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC11 + $::_TARGET0 riscv dmi_write 0x39 0xF4040258 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040250 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040248 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040240 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040238 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040230 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040228 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040220 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC14 + $::_TARGET0 riscv dmi_write 0x39 0xF4040270 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040268 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC16 + # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 + $::_TARGET0 riscv dmi_write 0x3C 0x1000C + # PC26 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC25 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040298 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040290 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC23 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC24 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC30 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC31 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040210 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040218 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # dramc configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + sleep 10 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + $::_TARGET0 riscv dmi_write 0x39 0xF3050008 + $::_TARGET0 riscv dmi_write 0x3C 0x30524 + $::_TARGET0 riscv dmi_write 0x39 0xF305000C + $::_TARGET0 riscv dmi_write 0x3C 0x6030524 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x10000000 + + $::_TARGET0 riscv dmi_write 0x39 0xF3050010 + $::_TARGET0 riscv dmi_write 0x3C 0x4000001b + $::_TARGET0 riscv dmi_write 0x39 0xF3050014 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3050040 + $::_TARGET0 riscv dmi_write 0x3C 0xf32 + + # 133Mhz configuration + #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + # 166Mhz configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e33 + + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020300 + + # config delay cell + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x3b + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x203b + + $::_TARGET0 riscv dmi_write 0x39 0xF3050094 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3050098 + $::_TARGET0 riscv dmi_write 0x3C 0 + + # precharge all + $::_TARGET0 riscv dmi_write 0x39 0xF3050090 + $::_TARGET0 riscv dmi_write 0x3C 0x40000000 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + # auto refresh + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + # set mode + $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 + $::_TARGET0 riscv dmi_write 0x3C 0x33 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020301 + echo "SDRAM has been initialized" +} + +$_TARGET0 configure -event reset-init { + init_clock + init_sdram +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg new file mode 100644 index 0000000000..686495c1a9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg @@ -0,0 +1,299 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause +# +# openocd flash driver argument: +# - ARG7: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - ARG8: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3040000 +# - base address: 0x80000000 +# - flash size: 0x1000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +proc init_sdram { } { +# configure dram frequency +# 133Mhz pll1_clk0: 266Mhz divide by 2 + #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x201 +# 166Mhz pll2_clk0: 333Mhz divide by 2 + $::_TARGET0 riscv dmi_write 0x39 0xF4001820 + $::_TARGET0 riscv dmi_write 0x3C 0x401 + + # PD13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040368 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040360 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040350 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040348 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040340 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040338 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040330 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040328 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040320 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040318 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040310 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040308 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PD00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040300 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC29 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC28 + $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC27 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC22 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC21 + $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC17 + $::_TARGET0 riscv dmi_write 0x39 0xF4040288 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC15 + $::_TARGET0 riscv dmi_write 0x39 0xF4040278 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040260 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC11 + $::_TARGET0 riscv dmi_write 0x39 0xF4040258 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040250 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040248 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040240 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040238 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040230 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040228 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040220 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # PC14 + $::_TARGET0 riscv dmi_write 0x39 0xF4040270 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040268 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC16 + # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 + $::_TARGET0 riscv dmi_write 0x3C 0x1000C + # PC26 + $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC25 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040298 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040290 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC23 + $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC24 + $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC30 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC31 + $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040210 + $::_TARGET0 riscv dmi_write 0x3C 0xC + # PC03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040218 + $::_TARGET0 riscv dmi_write 0x3C 0xC + + # dramc configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + sleep 10 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + $::_TARGET0 riscv dmi_write 0x39 0xF3050008 + $::_TARGET0 riscv dmi_write 0x3C 0x30524 + $::_TARGET0 riscv dmi_write 0x39 0xF305000C + $::_TARGET0 riscv dmi_write 0x3C 0x6030524 + $::_TARGET0 riscv dmi_write 0x39 0xF3050000 + $::_TARGET0 riscv dmi_write 0x3C 0x10000000 + + # 16MB + $::_TARGET0 riscv dmi_write 0x39 0xF3050010 + $::_TARGET0 riscv dmi_write 0x3C 0x40000019 + $::_TARGET0 riscv dmi_write 0x39 0xF3050014 + $::_TARGET0 riscv dmi_write 0x3C 0 + # 16-bit + $::_TARGET0 riscv dmi_write 0x39 0xF3050040 + $::_TARGET0 riscv dmi_write 0x3C 0xf31 + + # 133Mhz configuration + #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + # 166Mhz configuration + $::_TARGET0 riscv dmi_write 0x39 0xF3050044 + $::_TARGET0 riscv dmi_write 0x3C 0x884e33 + + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF3050048 + $::_TARGET0 riscv dmi_write 0x3C 0x1020d0d + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020300 + + # config delay cell + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x3b + $::_TARGET0 riscv dmi_write 0x39 0xF3050150 + $::_TARGET0 riscv dmi_write 0x3C 0x203b + + $::_TARGET0 riscv dmi_write 0x39 0xF3050094 + $::_TARGET0 riscv dmi_write 0x3C 0 + $::_TARGET0 riscv dmi_write 0x39 0xF3050098 + $::_TARGET0 riscv dmi_write 0x3C 0 + + # precharge all + $::_TARGET0 riscv dmi_write 0x39 0xF3050090 + $::_TARGET0 riscv dmi_write 0x3C 0x40000000 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000F + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + # auto refresh + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000C + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + # set mode + $::_TARGET0 riscv dmi_write 0x39 0xF30500A0 + $::_TARGET0 riscv dmi_write 0x3C 0x33 + $::_TARGET0 riscv dmi_write 0x39 0xF305009C + $::_TARGET0 riscv dmi_write 0x3C 0xA55A000A + sleep 500 + $::_TARGET0 riscv dmi_write 0x39 0xF305003C + $::_TARGET0 riscv dmi_write 0x3C 0x3 + + $::_TARGET0 riscv dmi_write 0x39 0xF305004C + $::_TARGET0 riscv dmi_write 0x3C 0x2020301 + echo "SDRAM has been initialized" +} + +$_TARGET0 configure -event reset-init { + init_clock + init_sdram +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg new file mode 100644 index 0000000000..f7fff1cb69 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg @@ -0,0 +1,34 @@ +# Copyright 2022 hpmicro +# SPDX-License-Identifier: BSD-3-Clause +# +# assumptions: +# - HPM_SDK_BASE has been defined as environment variable pointing to correct hpm_sdk path +# - current directory is ${HPM_SDK_BASE}/boards/openocd +# +# usage: +# # connect hpm6300evk via ft2232, debugging single core +# $ openocd -c "set HPM_SDK_BASE ${HPM_SDK_BASE}; set BOARD hpm6300evk; set PROBE ft2232;" -f hpm6300_all_in_one.cfg +# +# # supported board to be set to BOARD: +# - hpm6300evk +# - hpm6360evk +# # supported probes to be set to PROBE: +# - ft2232 +# - ft232 +# - jlink +# - cmsis_dap +# - nds_aice_micro + +set HPM_OPENOCD_CONFIG ${HPM_SDK_BASE}/boards/openocd + +if { ![info exists PROBE ] } { + set PROBE ft2232 +} + +if { ![info exists BOARD] } { + set BOARD hpm6300evk +} + +source ${HPM_OPENOCD_CONFIG}/probes/${PROBE}.cfg +source ${HPM_OPENOCD_CONFIG}/soc/hpm6360.cfg +source ${HPM_OPENOCD_CONFIG}/boards/${BOARD}.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg new file mode 100644 index 0000000000..cc78b45354 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg @@ -0,0 +1,44 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause +# +# assumptions: +# - HPM_SDK_BASE has been defined as environment variable pointing to correct hpm_sdk path +# - current directory is ${HPM_SDK_BASE}/boards/openocd +# +# usage: +# # connect hpm6750evkmini via ft2232, debugging single core +# $ openocd -c "set HPM_SDK_BASE ${HPM_SDK_BASE}; set BOARD hpm6750evkmini; set PROBE ft2232;" -f hpm6750_all_in_one.cfg +# # connect hpm6750evkmini via ft2232, debugging dual core +# $ openocd -c "set HPM_SDK_BASE ${HPM_SDK_BASE}; set BOARD hpm6750evkmini; set PROBE ft2232; set ENABLE_DUALCORE 1" -f hpm6750_all_in_one.cfg +# +# # supported board to be set to BOARD: +# - hpm6750evk +# - hpm6750evkmini +# # supported probes to be set to PROBE: +# - ft2232 +# - ft232 +# - jlink +# - cmsis_dap +# - nds_aice_micro +# # supported core debug type to ENABLE_DUALCORE: +# - 1: enable dual core debugging + +set HPM_OPENOCD_CONFIG ${HPM_SDK_BASE}/boards/openocd + +if { ![info exists PROBE ] } { + set PROBE ft2232 +} + +if { ![info exists BOARD] } { + set BOARD hpm6750evkmini +} + +if { [info exists ENABLE_DUALCORE] && $ENABLE_DUALCORE == 1 } { + set CORE hpm6750-dual-core +} else { + set CORE hpm6750-single-core +} + +source ${HPM_OPENOCD_CONFIG}/probes/${PROBE}.cfg +source ${HPM_OPENOCD_CONFIG}/soc/${CORE}.cfg +source ${HPM_OPENOCD_CONFIG}/boards/${BOARD}.cfg diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/cmsis_dap.cfg new file mode 100644 index 0000000000..b9ae112104 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg new file mode 100644 index 0000000000..580d98ef85 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft232.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft232.cfg new file mode 100644 index 0000000000..4fb0fba2e7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/jlink.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/jlink.cfg new file mode 100644 index 0000000000..fd8f04428c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 0000000000..e9d6e6d698 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360-csr.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360-csr.cfg new file mode 100644 index 0000000000..abaeb2f373 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360-csr.cfg @@ -0,0 +1,50 @@ +riscv expose_csrs 262=scounteren +riscv expose_csrs 800=mcountinhibit +riscv expose_csrs 1984=milmb +riscv expose_csrs 1985=mdlmb +riscv expose_csrs 1986=mecc_code +riscv expose_csrs 1987=mnvec +riscv expose_csrs 1988=mxstatus +riscv expose_csrs 1989=mpft_ctl +riscv expose_csrs 1990=mhsp_ctl +riscv expose_csrs 1991=msp_bound +riscv expose_csrs 1992=msp_base +riscv expose_csrs 1993=mdcause +riscv expose_csrs 1994=mcache_ctl +riscv expose_csrs 1995=mcctlbeginaddr +riscv expose_csrs 1996=mcctlcommand +riscv expose_csrs 1997=mcctldata +riscv expose_csrs 1998=mcounterwen +riscv expose_csrs 1999=mcounterinten +riscv expose_csrs 2000=mmisc_ctl +riscv expose_csrs 2001=mcountermask_m +riscv expose_csrs 2002=mcountermask_s +riscv expose_csrs 2003=mcountermask_u +riscv expose_csrs 2004=mcounterovf +riscv expose_csrs 2005=mslideleg +riscv expose_csrs 2015=mclk_ctl +riscv expose_csrs 2016=dexc2dbg +riscv expose_csrs 2017=ddcause +riscv expose_csrs 2048=uitb +riscv expose_csrs 2049=ucode +riscv expose_csrs 2057=udcause +riscv expose_csrs 2059=ucctlbeginaddr +riscv expose_csrs 2060=ucctlcommand +riscv expose_csrs 2500=slie +riscv expose_csrs 2501=slip +riscv expose_csrs 2505=sdcause +riscv expose_csrs 2509=scctldata +riscv expose_csrs 2511=scounterinten +riscv expose_csrs 2513=scountermask_m +riscv expose_csrs 2514=scountermask_s +riscv expose_csrs 2515=scountermask_u +riscv expose_csrs 2516=scounterovf +riscv expose_csrs 2528=scountinhibit +riscv expose_csrs 2531=shpmevent3 +riscv expose_csrs 2532=shpmevent4 +riscv expose_csrs 2533=shpmevent5 +riscv expose_csrs 2534=shpmevent6 +riscv expose_csrs 4032=micm_cfg +riscv expose_csrs 4033=mdcm_cfg +riscv expose_csrs 4034=mmsc_cfg +riscv expose_csrs 4035=mmsc_cfg2 diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360.cfg new file mode 100644 index 0000000000..bfce20c208 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6360.cfg @@ -0,0 +1,13 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6360 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-csr.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-csr.cfg new file mode 100644 index 0000000000..abaeb2f373 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-csr.cfg @@ -0,0 +1,50 @@ +riscv expose_csrs 262=scounteren +riscv expose_csrs 800=mcountinhibit +riscv expose_csrs 1984=milmb +riscv expose_csrs 1985=mdlmb +riscv expose_csrs 1986=mecc_code +riscv expose_csrs 1987=mnvec +riscv expose_csrs 1988=mxstatus +riscv expose_csrs 1989=mpft_ctl +riscv expose_csrs 1990=mhsp_ctl +riscv expose_csrs 1991=msp_bound +riscv expose_csrs 1992=msp_base +riscv expose_csrs 1993=mdcause +riscv expose_csrs 1994=mcache_ctl +riscv expose_csrs 1995=mcctlbeginaddr +riscv expose_csrs 1996=mcctlcommand +riscv expose_csrs 1997=mcctldata +riscv expose_csrs 1998=mcounterwen +riscv expose_csrs 1999=mcounterinten +riscv expose_csrs 2000=mmisc_ctl +riscv expose_csrs 2001=mcountermask_m +riscv expose_csrs 2002=mcountermask_s +riscv expose_csrs 2003=mcountermask_u +riscv expose_csrs 2004=mcounterovf +riscv expose_csrs 2005=mslideleg +riscv expose_csrs 2015=mclk_ctl +riscv expose_csrs 2016=dexc2dbg +riscv expose_csrs 2017=ddcause +riscv expose_csrs 2048=uitb +riscv expose_csrs 2049=ucode +riscv expose_csrs 2057=udcause +riscv expose_csrs 2059=ucctlbeginaddr +riscv expose_csrs 2060=ucctlcommand +riscv expose_csrs 2500=slie +riscv expose_csrs 2501=slip +riscv expose_csrs 2505=sdcause +riscv expose_csrs 2509=scctldata +riscv expose_csrs 2511=scounterinten +riscv expose_csrs 2513=scountermask_m +riscv expose_csrs 2514=scountermask_s +riscv expose_csrs 2515=scountermask_u +riscv expose_csrs 2516=scounterovf +riscv expose_csrs 2528=scountinhibit +riscv expose_csrs 2531=shpmevent3 +riscv expose_csrs 2532=shpmevent4 +riscv expose_csrs 2533=shpmevent5 +riscv expose_csrs 2534=shpmevent6 +riscv expose_csrs 4032=micm_cfg +riscv expose_csrs 4033=mdcm_cfg +riscv expose_csrs 4034=mmsc_cfg +riscv expose_csrs 4035=mmsc_cfg2 diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg new file mode 100644 index 0000000000..601b680951 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg @@ -0,0 +1,61 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause +# + + +set _CHIP hpm6750 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +proc dmi_write {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc dmi_read {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc dmi_write_memory {addr value} { + dmi_write 0x39 ${addr} + dmi_write 0x3C ${value} +} + +proc dmi_read_memory {addr} { + set sbcs [expr 0x100000 | [dmi_read 0x38]] + dmi_write 0x38 ${sbcs} + dmi_write 0x39 ${addr} + set value [dmi_read 0x3C] + return ${value} +} + +proc release_core1 {} { + # set start point for core1 + dmi_write_memory 0xF4002C08 0x20016284 + + # set boot flag for core1 + dmi_write_memory 0xF4002C0C 0xC1BEF1A9 + + # release core1 + dmi_write_memory 0xF4002C00 0x1000 +} + +$_TARGET0 configure -event examine-end { + release_core1 +} + +set _TARGET1 $_CHIP.cpu1 +target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 +$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +$_TARGET1 configure -event reset-deassert-pre { + $::_TARGET1 arp_poll + release_core1 +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg new file mode 100644 index 0000000000..8e2bbe5f19 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg @@ -0,0 +1,13 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6750 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/SConscript b/bsp/hpmicro/libraries/hpm_sdk/components/SConscript new file mode 100644 index 0000000000..112e98c351 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/SConscript @@ -0,0 +1,37 @@ +Import('rtconfig') +import os +from building import * + +#get current directory +cwd = GetCurrentDir() + +CPPDEFINES=[] + +# Update include path +path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_manager') ] + +# The set of source files associated with this SConscript file. +src = [] + +src += [ os.path.join(cwd, 'debug_console', 'hpm_debug_console.c') ] +src += [ os.path.join(cwd, 'dma_manager', 'hpm_dma_manager.c') ] +if GetDepend(['BSP_USING_TOUCH_GT911']): + src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_touch_gt911.c') ] + src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_gt911.c') ] + path += [ os.path.join(cwd, 'touch', 'gt911') ] + CPPDEFINES = ['CONFIG_TOUCH_GT911=1'] +if GetDepend(['BSP_USING_TOUCH_FT5406']): + src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_touch_ft5406.c') ] + src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_ft5406.c') ] + path += [ os.path.join(cwd, 'touch', 'ft5406') ] + CPPDEFINES = ['CONFIG_TOUCH_FT5406=1'] +if GetDepend(['BSP_USING_USB_DEVICE']): + src += [ os.path.join(cwd, 'usb', 'device', 'hpm_usb_device.c') ] + path += [ os.path.join(cwd, 'usb', 'device') ] +if GetDepend(['BSP_USING_USB_HOST']): + src += [ os.path.join(cwd, 'usb', 'host', 'hpm_usb_host.c') ] + path += [ os.path.join(cwd, 'usb', 'host') ] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) + +Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h b/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h new file mode 100644 index 0000000000..d3ffad6a14 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h @@ -0,0 +1,617 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ADC_H +#define HPM_ADC_H + +#include "hpm_common.h" +#ifdef CONFIG_HAS_HPMSDK_ADC12 +#include "hpm_adc12_drv.h" +#endif +#ifdef CONFIG_HAS_HPMSDK_ADC16 +#include "hpm_adc16_drv.h" +#endif +#include "hpm_soc_feature.h" +/** + * @brief ADC HAL driver APIs + * @defgroup hpm_adc_interface HPM ADC driver APIs + * @ingroup hpm_adc_interfaces + * @{ + */ + +/** + * @brief An ADC peripheral base address. + * + */ +typedef union +{ +#ifdef CONFIG_HAS_HPMSDK_ADC12 + ADC12_Type *adc12; +#endif +#ifdef CONFIG_HAS_HPMSDK_ADC16 + ADC16_Type *adc16; +#endif +} adc_base; + +/** + * @brief use adc12 or adc16. + * + */ +#define ADCX_MODULE_ADC12 1 +#define ADCX_MODULE_ADC16 2 + +typedef enum { + adc_module_adc12 = ADCX_MODULE_ADC12, + adc_module_adc16 = ADCX_MODULE_ADC16 +} adc_module; + +/** + * @brief ADC common configuration struct. + * + */ +typedef struct { + adc_module module; + adc_base adc_base; + struct { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_config_t adc12; +#endif +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_config_t adc16; +#endif + } config; +} adc_config_t; + +/** + * @brief ADC channel configuration struct. + * + */ +typedef struct { + adc_module module; + adc_base adc_base; + struct { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_channel_config_t adc12_ch; +#endif +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_channel_config_t adc16_ch; +#endif + } config; +} adc_channel_config_t; + +/** + * @brief ADC DMA configuration struct. + * + * */ +typedef struct { + adc_module module; + adc_base adc_base; + struct { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_dma_config_t adc12; +#endif +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_dma_config_t adc16; +#endif + } config; +} adc_dma_config_t; + +/** + * @brief ADC configuration struct for period mode. + * + * */ +typedef struct { + adc_module module; + adc_base adc_base; + struct { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_prd_config_t adc12; +#endif +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_prd_config_t adc16; +#endif + } config; +} adc_prd_config_t; + +/** + * @brief ADC configuration struct for sequence mode. + * + * */ +typedef struct { + adc_module module; + adc_base adc_base; + struct { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_seq_config_t adc12; +#endif +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_seq_config_t adc16; +#endif + } config; +} adc_seq_config_t; + +/** + * @brief ADC trigger configuration struct for preempt mode. + * + * */ +typedef struct +{ + adc_module module; + adc_base adc_base; + struct { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_pmt_config_t adc12; +#endif +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_pmt_config_t adc16; +#endif + } config; +} adc_pmt_config_t; + + +typedef struct +{ + adc_module module; + adc_base adc_base; +} adc_type; + + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get a default configuration for an ADC instance. + * + * @param[out] config A pointer to the configuration struct of "adc_config_t". + * + */ +static inline void hpm_adc_init_default_config(adc_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_get_default_config(&config->config.adc12); +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_get_default_config(&config->config.adc16); +#endif + } +} + +/** + * @brief Get a default configuration for an ADC channel instance. + * + * @param[out] config A pointer to the configuration struct of "adc_channel_config_t". + * + */ +static inline void hpm_adc_init_channel_default_config(adc_channel_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_get_channel_default_config(&config->config.adc12_ch); +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_get_channel_default_config(&config->config.adc16_ch); +#endif + } +} + +/** + * @brief Initialize an ADC instance. + * + * @param[in] config A pointer to the configuration struct of "adc_config_t". + * @retval status_success Initialize an ADC instance successfully. + * @retval status_invalid_argument Initialize an ADC instance unsuccessfully because of passing one or more invalid arguments. + */ +static inline hpm_stat_t hpm_adc_init(adc_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_init(config->adc_base.adc12, &config->config.adc12); +#else + return status_invalid_argument; +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_init(config->adc_base.adc16, &config->config.adc16); +#else + return status_invalid_argument; +#endif + } else { + return false; + } +} + +/** + * @brief Initialize an ADC channel. + * + * @param[in] config A pointer to the configuration struct of "adc_config_t". + * @retval status_success Initialize an ADC instance successfully. + * @retval status_invalid_argument Initialize an ADC instance unsuccessfully because of passing one or more invalid arguments. + */ +static inline hpm_stat_t hpm_adc_channel_init(adc_channel_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_init_channel(config->adc_base.adc12, &config->config.adc12_ch); +#else + return status_invalid_argument; +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_init_channel(config->adc_base.adc16, &config->config.adc16_ch); +#else + return status_invalid_argument; +#endif + } else { + return false; + } +} + +/** + * @brief Configure the periodic mode for an ADC instance. + * + * @param[in] config A pointer to the configuration struct of "adc_prd_config_t". + * @retval status_success Configure the periodic mode for an ADC instance successfully. + * @retval status_invalid_argument Configure the periodic mode for an ADC instance unsuccessfully because of passing one or more invalid arguments. + * + */ +static inline hpm_stat_t hpm_adc_set_period_config(adc_prd_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_set_prd_config(config->adc_base.adc12, &config->config.adc12); +#else + return status_invalid_argument; +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_set_prd_config(config->adc_base.adc16, &config->config.adc16); +#else + return status_invalid_argument; +#endif + } else { + return false; + } +} + +/** + * @brief Configure the sequence mode for an ADC instance. + * + * @param[in] config A pointer to configuration struct of "adc_seq_config_t". + * @retval status_success Configure the sequence mode for an ADC instance successfully. + * @retval status_invalid_argument Configure the sequence mode for an ADC instance unsuccessfully because of passing one or more invalid arguments. + */ +static inline hpm_stat_t hpm_adc_set_sequence_config(adc_seq_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_set_seq_config(config->adc_base.adc12, &config->config.adc12); +#else + return status_invalid_argument; +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_set_seq_config(config->adc_base.adc16, &config->config.adc16); +#else + return status_invalid_argument; +#endif + } else { + return false; + } +} + +/** + * @brief Configure the preemption mode for an ADC instance. + * + * @param[in] config a pointer to configuration struct of "adc_pmt_config_t". + * @retval status_success Configure the preemption mode for an ADC instance successfully. + * @retval status_invalid_argument Configure the preemption mode for an ADC instance unsuccessfully because of passing one or more invalid arguments. + */ +static inline hpm_stat_t hpm_adc_set_preempt_config(adc_pmt_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_set_pmt_config(config->adc_base.adc12, &config->config.adc12); +#else + return status_invalid_argument; +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_set_pmt_config(config->adc_base.adc16, &config->config.adc16); +#else + return status_invalid_argument; +#endif + } else { + return false; + } +} + +/** + * @brief Configure the stop position offset in the specified memory for DMA write operation for sequence mode. + * + * @param[in] ptr An ADC peripheral base address. + * @param[in] stop_pos The stop position offset. + */ +static inline void hpm_adc_set_seq_stop_pos(adc_type *ptr, uint16_t stop_pos) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_set_seq_stop_pos(ptr->adc_base.adc12, stop_pos); +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_set_seq_stop_pos(ptr->adc_base.adc16, stop_pos); +#endif + } +} + +/** + * @brief Configure the start address of DMA write operation for preemption mode. + * + * @param[in] ptr An ADC peripheral base address. + * @param[in] addr The start address of DMA write operation. + */ +static inline void hpm_adc_init_pmt_dma(adc_type *ptr, uint32_t addr) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_init_pmt_dma(ptr->adc_base.adc12, addr); +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_init_pmt_dma(ptr->adc_base.adc16, addr); +#endif + } +} + +/** + * @brief Configure the start address of DMA write operation for preemption mode. + * + * @param[in] config A pointer to configuration struct of "adc_dma_config_t". + */ +static inline void hpm_adc_init_seq_dma(adc_dma_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_init_seq_dma(config->adc_base.adc12, &config->config.adc12); +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_init_seq_dma(config->adc_base.adc16, &config->config.adc16); +#endif + } +} + + +/** + * @brief Get ADC status flags. + * + * This function gets all ADC status flags. + * @param[in] ptr An ADC peripheral base address. + * @retval Status The ADC interrupt status flags. + */ +static inline uint32_t hpm_adc_get_status_flags(adc_type *ptr) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_get_status_flags(ptr->adc_base.adc12); +#else + return 0; +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_get_status_flags(ptr->adc_base.adc16); +#else + return 0; +#endif + } else { + return false; + } +} + +/** + * @brief Get the setting value of wait disable. + * + * This status flag is only used when wait_dis is set to disable. + * + * @param[in] ptr An ADC peripheral base address. + * @retval Status It means whether the current setting of wait disable is disable. + */ +static inline bool hpm_adc_get_wait_dis_status(adc_type *ptr) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_get_wait_dis_status(ptr->adc_base.adc12); +#else + return 1; +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_get_wait_dis_status(ptr->adc_base.adc16); +#else + return 1; +#endif + } else { + return false; + } +} + +/** + * @brief Get status flag of a conversion. + * + * This status flag is only used when wait_dis is set to disable. + * + * @param[in] ptr An ADC peripheral base address. + * @param[in] ch An ADC peripheral channel. + * @retval Status It means the current conversion is valid. + */ +static inline bool hpm_adc_get_conv_valid_status(adc_type *ptr, uint8_t ch) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_get_conv_valid_status(ptr->adc_base.adc12, ch); +#else + return 0; +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_get_conv_valid_status(ptr->adc_base.adc16, ch); +#else + return 0; +#endif + } else { + return false; + } +} + +/** + * @brief Clear status flags. + * + * Only the specified flags can be cleared by writing INT_STS register. + * + * @param[in] ptr An ADC peripheral base address. + * @param[in] mask Mask value for flags to be cleared. Refer to "adc12_irq_event_t". Refer to "adc16_irq_event_t". + */ +static inline void hpm_adc_clear_status_flags(adc_type *ptr, uint32_t mask) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_clear_status_flags(ptr->adc_base.adc12, mask); +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_clear_status_flags(ptr->adc_base.adc16, mask); +#endif + } +} + +/** + * @brief Enable interrupts. + * + * @param[in] ptr An ADC peripheral base address. + * @param[in] mask Mask value for interrupt events. Refer to "adc12_irq_event_t".Refer to "adc16_irq_event_t". + */ +static inline void hpm_adc_enable_interrupts(adc_type *ptr, uint32_t mask) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_enable_interrupts(ptr->adc_base.adc12, mask); +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_enable_interrupts(ptr->adc_base.adc16, mask); +#endif + } +} + +/** + * @brief Disable interrupts. + * + * @param[in] ptr An ADC peripheral base address. + * @param[in] mask Mask value for interrupt events. Refer to "adc12_irq_event_t".Refer to "adc16_irq_event_t". + */ +static inline void hpm_adc_disable_interrupts(adc_type *ptr, uint32_t mask) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_disable_interrupts(ptr->adc_base.adc12, mask); +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_disable_interrupts(ptr->adc_base.adc16, mask); +#endif + } +} + +/** + * @brief Get the result in oneshot mode. + * + * @param[in] ptr An ADC peripheral base address. + * @param[in] ch An ADC peripheral channel. + * @param[out] result The result of an ADC12 conversion. + * + * @retval status_success Get the result of an ADC12 conversion in oneshot mode successfully. + * @retval status_invalid_argument Get the result of an ADC12 conversion in oneshot mode unsuccessfully because of passing invalid arguments. + */ +static inline hpm_stat_t hpm_adc_get_oneshot_result(adc_type *ptr, uint8_t ch, uint16_t *result) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_get_oneshot_result(ptr->adc_base.adc12, ch, result); +#else + return status_invalid_argument; +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_get_oneshot_result(ptr->adc_base.adc16, ch, result); +#else + return status_invalid_argument; +#endif + } else { + return false; + } +} + +/** + * @brief Get the result in periodic mode. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] ch An ADC12 peripheral channel. + * @param[out] result The result of an ADC12 conversion. + * + * @retval status_success Get the result of an ADC12 conversion in periodic mode successfully. + * @retval status_invalid_argument Get the result of an ADC12 conversion in periodic mode unsuccessfully because of passing invalid arguments. + */ +hpm_stat_t hpm_adc_get_prd_result(adc_type *ptr, uint8_t ch, uint16_t *result) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_get_prd_result(ptr->adc_base.adc12, ch, result); +#else + return status_invalid_argument; +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_get_prd_result(ptr->adc_base.adc16, ch, result); +#else + return status_invalid_argument; +#endif + } else { + return false; + } +} + +/** + * @brief Do a software trigger for sequence mode. + * + * @param[in] ptr An adc peripheral base address. + * + */ +void hpm_adc_trigger_seq_by_sw(adc_type *ptr) +{ + if (ptr->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + return adc12_trigger_seq_by_sw(ptr->adc_base.adc12); +#endif + } else if (ptr->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + return adc16_trigger_seq_by_sw(ptr->adc_base.adc16); +#endif + } +} + + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h new file mode 100644 index 0000000000..89d30fef3e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_CAMERA_H +#define HPM_CAMERA_H + +#if CONFIG_CAMERA_OV7725 +#include "hpm_ov7725.h" +#define CAMERA_MAX_IMAGE_OUTPUT_WIDTH OV7725_ACTIVE_IMAGE_WIDTH +#define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT OV7725_ACTIVE_IMAGE_HEIGHT +#elif CONFIG_CAMERA_OV5640 +#include "hpm_ov5640.h" +#define CAMERA_MAX_IMAGE_OUTPUT_WIDTH OV5640_ACTIVE_IMAGE_WIDTH +#define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT OV5640_ACTIVE_IMAGE_HEIGHT +#else +#error "unknown camera type, either have CONFIG_CAMERA_OV7725 or CONFIG_CAMERA_OV5640 defined" +#endif + + +#endif /* HPM_CAMERA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h new file mode 100644 index 0000000000..bfb8502c8f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_CAMERA_CONFIG_H +#define HPM_CAMERA_CONFIG_H + +#include "hpm_common.h" +#include "hpm_display_common.h" +#include "hpm_i2c_drv.h" + +/* Macro to define video resolution. */ +#define HPM_CAMERA_RESOLUTION(width, height) ((uint32_t)(width) | ((uint32_t)(height) << 16U)) + +typedef struct +{ + I2C_Type *ptr; + void (*delay_ms)(uint32_t ms); + void (*write_rst)(uint8_t state); + void (*write_pwdn)(uint8_t state); +} camera_context_t; + +typedef enum +{ + camera_interface_dvp, + camera_interface_mipi, +} camera_interface_t; + +typedef struct +{ + uint32_t width; + uint32_t height; + display_pixel_format_t pixel_format; + camera_interface_t interface; +} camera_config_t; + +/* Video Resolution definition. */ +typedef enum +{ + video_resolution_5mp = HPM_CAMERA_RESOLUTION(2592, 1944), /* 5MP, 2592 * 1944 */ + video_resolution_sxga = HPM_CAMERA_RESOLUTION(1280, 800), /* SXGA, 1280 * 800 */ + video_resolution_1080p = HPM_CAMERA_RESOLUTION(1920, 1080), /* 1080P, 1920 * 1280*/ + video_resolution_720p = HPM_CAMERA_RESOLUTION(1280, 720), /* 720P, 1280 * 720 */ + video_resolution_800_480 = HPM_CAMERA_RESOLUTION(800, 480), /* 640 * 480 */ + video_resolution_vga = HPM_CAMERA_RESOLUTION(640, 480), /* VGA, 640 * 480 */ + video_resolution_480_272 = HPM_CAMERA_RESOLUTION(480, 272), /* 480 * 272 */ + video_resolution_qvga = HPM_CAMERA_RESOLUTION(320, 240), /* QVGA, 320 * 240 */ +} camera_resolution_t; + +/* Camera light mode type. */ +typedef enum +{ + camera_light_mode_auto = 0, + camera_light_mode_sunny, + camera_light_mode_cloudy, + camera_light_mode_office, + camera_light_mode_home, + camera_light_mode_night, +} camera_light_mode_t; + +/* Camera special effect type. */ +typedef enum +{ + camera_special_effect_normal = 0, /* Normal. */ + camera_special_effect_bw, /* B & W */ + camera_special_effect_sepia, /* Sepia. */ + camera_special_effect_bluish, /* Bluish. */ + camera_special_effect_redish, /* Redish. */ + camera_special_effect_greenish, /* Greenish. */ + camera_special_effect_negtive, /* Negtive. */ + camera_special_effect_over_exposure, /* OverExposure. */ + camera_special_effect_solarize, /* Solarize. */ +} camera_special_effect_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * camera device initialization + */ +hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config); + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_CAMERA_CONFIG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c new file mode 100644 index 0000000000..33e807b0dd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_ov5640.h" + +hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) +{ + assert(camera_context->delay_ms != NULL); + + hpm_stat_t stat = status_success; + +#ifdef HPM_CAM_EXECUTE_POWER_UP_SEQUENCE + /* execute power up sequence */ + ov5640_power_up(camera_context); +#endif + + /* software reset */ + stat = ov5640_software_reset(camera_context); + if (stat != status_success) { + return stat; + } + camera_context->delay_ms(20); + + stat = ov5640_init(camera_context, camera_config); + + return stat; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c new file mode 100644 index 0000000000..672e7055eb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c @@ -0,0 +1,822 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_ov5640.h" + +static const ov5640_reg_val_t ov5640_init_param[] = { + /* system setting */ + {0x3008, 0x42}, /* software power down, bit[6] */ + {0x3103, 0x03}, /* system clock from PLL, bit[1] */ + {0x3037, 0x13}, /* PLL root divider, bit[4], PLL pre-divider, bit[3:0] */ + {0x3108, 0x01}, /* PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2], SCLK root divider, bit[1:0] */ + + {0x3630, 0x36}, + {0x3631, 0x0e}, + {0x3632, 0xe2}, + {0x3633, 0x12}, + {0x3621, 0xe0}, + {0x3704, 0xa0}, + {0x3703, 0x5a}, + + {0x302c, 0xc2}, /* pad control */ + {0x4004, 0x02}, /* BLC 2 lines */ + {0x3002, 0x1c}, /* reset JFIFO, SFIFO, JPEG */ + {0x3006, 0xc3}, /* disable clock of JPEG2x, JPEG */ + {0x4713, 0x03}, /* JPEG mode 3 */ + {0x4407, 0x04}, /* Quantization scale */ + {0x460b, 0x35}, + {0x5001, 0xa3}, /* SDE on, scale on, UV average off, color matrix on, AWB on */ + {0x3503, 0x00}, /* AEC/AGC on */ + {0x3c07, 0x08}, /* light meter 1 threshold [7:0] */ + {0x3820, 0x41}, /* Sensor flip off, ISP flip on */ + {0x3821, 0x07}, /* Sensor mirror on, ISP mirror on, H binning on */ + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3709, 0x52}, + {0x370c, 0x03}, + + {0x3715, 0x78}, + {0x3717, 0x01}, + {0x370b, 0x60}, + {0x3705, 0x1a}, + {0x3905, 0x02}, + {0x3906, 0x10}, + {0x3901, 0x0a}, + {0x3731, 0x12}, + {0x3600, 0x08}, /* VCM control */ + {0x3601, 0x33}, /* VCM control */ + {0x302d, 0x60}, /* system control */ + {0x3620, 0x52}, + {0x371b, 0x20}, + {0x471c, 0x50}, + {0x3a13, 0x43}, /* pre-gain = 1.047x */ + {0x3a18, 0x00}, /* gain ceiling */ + {0x3a19, 0xf8}, /* gain ceiling = 15.5x */ + {0x3635, 0x13}, + {0x3636, 0x03}, + {0x3634, 0x40}, + {0x3622, 0x01}, + /* 50/60Hz detection */ + {0x3a02, 0x0b}, /* 60Hz max exposure, night mode 5fps */ + {0x3a03, 0x88}, /* 60Hz max exposure */ + {0x3a14, 0x0b}, /* 50Hz max exposure, night mode 5fps */ + {0x3a15, 0x88}, /* 50Hz max exposure */ + {0x3c01, 0x34}, /* Band auto, bit[7] */ + {0x3c04, 0x28}, /* threshold low sum */ + {0x3c05, 0x98}, /* threshold high sum */ + {0x3c06, 0x00}, /* light meter 1 threshold[15:8] */ + {0x3c07, 0x08}, /* light meter 1 threshold[7:0] */ + {0x3c08, 0x00}, /* light meter 2 threshold[15:8] */ + {0x3c09, 0x1c}, /* light meter 2 threshold[7:0] */ + {0x3c0a, 0x9c}, /* sample number[15:8] */ + {0x3c0b, 0x40}, /* sample number[7:0] */ + {0x3708, 0x64}, + {0x4001, 0x02}, /* BLC start from line 2 */ + {0x4005, 0x1a}, /* BLC always update */ + {0x3000, 0x00}, /* enable blocks */ + {0x3004, 0xff}, /* enable clocks */ + {0x302e, 0x00}, + {0x440e, 0x00}, + {0x5000, 0xa7}, /* Lenc on, raw gamma on, BPC on, WPC on, CIP on */ + /* AEC target */ + {0x3a0f, 0x30}, /* stable range in high */ + {0x3a10, 0x28}, /* stable range in low */ + {0x3a1b, 0x30}, /* stable range out high */ + {0x3a1e, 0x26}, /* stable range out low */ + {0x3a11, 0x60}, /* fast zone high */ + {0x3a1f, 0x14}, /* fast zone low */ + /* Lens correction */ + {0x5800, 0x23}, + {0x5801, 0x14}, + {0x5802, 0x0f}, + {0x5803, 0x0f}, + {0x5804, 0x12}, + {0x5805, 0x26}, + {0x5806, 0x0c}, + {0x5807, 0x08}, + {0x5808, 0x05}, + {0x5809, 0x05}, + {0x580a, 0x08}, + {0x580b, 0x0d}, + {0x580c, 0x08}, + {0x580d, 0x03}, + {0x580e, 0x00}, + {0x580f, 0x00}, + {0x5810, 0x03}, + {0x5811, 0x09}, + {0x5812, 0x07}, + {0x5813, 0x03}, + {0x5814, 0x00}, + {0x5815, 0x01}, + {0x5816, 0x03}, + {0x5817, 0x08}, + {0x5818, 0x0d}, + {0x5819, 0x08}, + {0x581a, 0x05}, + {0x581b, 0x06}, + {0x581c, 0x08}, + {0x581d, 0x0e}, + {0x581e, 0x29}, + {0x581f, 0x17}, + {0x5820, 0x11}, + {0x5821, 0x11}, + {0x5822, 0x15}, + {0x5823, 0x28}, + {0x5824, 0x46}, + {0x5825, 0x26}, + {0x5826, 0x08}, + {0x5827, 0x26}, + {0x5828, 0x64}, + {0x5829, 0x26}, + {0x582a, 0x24}, + {0x582b, 0x22}, + {0x582c, 0x24}, + {0x582d, 0x24}, + {0x582e, 0x06}, + {0x582f, 0x22}, + {0x5830, 0x40}, + {0x5831, 0x42}, + {0x5832, 0x24}, + {0x5833, 0x26}, + {0x5834, 0x24}, + {0x5835, 0x22}, + {0x5836, 0x22}, + {0x5837, 0x26}, + {0x5838, 0x44}, + {0x5839, 0x24}, + {0x583a, 0x26}, + {0x583b, 0x28}, + {0x583c, 0x42}, + {0x583d, 0xce}, /* lenc BR offset */ + /* AWB */ + {0x5180, 0xff}, /* AWB B block */ + {0x5181, 0xf2}, /* AWB control */ + {0x5182, 0x00}, /* [7:4] max local counter, [3:0] max fast counter */ + {0x5183, 0x14}, /* AWB advanced */ + {0x5184, 0x25}, + {0x5185, 0x24}, + {0x5186, 0x09}, + {0x5187, 0x09}, + {0x5188, 0x09}, + {0x5189, 0x75}, + {0x518a, 0x54}, + {0x518b, 0xe0}, + {0x518c, 0xb2}, + {0x518d, 0x42}, + {0x518e, 0x3d}, + {0x518f, 0x56}, + {0x5190, 0x46}, + {0x5191, 0xf8}, /* AWB top limit */ + {0x5192, 0x04}, /* AWB bottom limit */ + {0x5193, 0x70}, /* red limit */ + {0x5194, 0xf0}, /* green limit */ + {0x5195, 0xf0}, /* blue limit */ + {0x5196, 0x03}, /* AWB control */ + {0x5197, 0x01}, /* local limit */ + {0x5198, 0x04}, + {0x5199, 0x12}, + {0x519a, 0x04}, + {0x519b, 0x00}, + {0x519c, 0x06}, + {0x519d, 0x82}, + {0x519e, 0x38}, /* AWB control */ + + /* Gamma */ + {0x5480, 0x01}, /* Gamma bias plus on, bit[0] */ + {0x5481, 0x08}, + {0x5482, 0x14}, + {0x5483, 0x28}, + {0x5484, 0x51}, + {0x5485, 0x65}, + {0x5486, 0x71}, + {0x5487, 0x7d}, + {0x5488, 0x87}, + {0x5489, 0x91}, + {0x548a, 0x9a}, + {0x548b, 0xaa}, + {0x548c, 0xb8}, + {0x548d, 0xcd}, + {0x548e, 0xdd}, + {0x548f, 0xea}, + {0x5490, 0x1d}, + /* color matrix */ + {0x5381, 0x1e}, /* CMX1 for Y */ + {0x5382, 0x5b}, /* CMX2 for Y */ + {0x5383, 0x08}, /* CMX3 for Y */ + {0x5384, 0x0a}, /* CMX4 for U */ + {0x5385, 0x7e}, /* CMX5 for U */ + {0x5386, 0x88}, /* CMX6 for U */ + {0x5387, 0x7c}, /* CMX7 for V */ + {0x5388, 0x6c}, /* CMX8 for V */ + {0x5389, 0x10}, /* CMX9 for V */ + {0x538a, 0x01}, /* sign[9] */ + {0x538b, 0x98}, /* sign[8:1] */ + /* UV adjust */ + {0x5580, 0x06}, /* saturation on, bit[1] */ + {0x5583, 0x40}, + {0x5584, 0x10}, + {0x5003, 0x08}, + {0x5589, 0x10}, + {0x558a, 0x00}, + {0x558b, 0xf8}, + {0x501d, 0x40}, /* enable manual offset of contrast */ + /* CIP */ + {0x5300, 0x08}, /* CIP sharpen MT threshold 1 */ + {0x5301, 0x30}, /* CIP sharpen MT threshold 2 */ + {0x5302, 0x10}, /* CIP sharpen MT offset 1 */ + {0x5303, 0x00}, /* CIP sharpen MT offset 2 */ + {0x5304, 0x08}, /* CIP DNS threshold 1 */ + {0x5305, 0x30}, /* CIP DNS threshold 2 */ + {0x5306, 0x08}, /* CIP DNS offset 1 */ + {0x5307, 0x16}, /* CIP DNS offset 2 */ + {0x5309, 0x08}, /* CIP sharpen TH threshold 1 */ + {0x530a, 0x30}, /* CIP sharpen TH threshold 2 */ + {0x530b, 0x04}, /* CIP sharpen TH offset 1 */ + {0x530c, 0x06}, /* CIP sharpen TH offset 2 */ + {0x5025, 0x00}, + {0x3008, 0x02}, /* wake up from standby, bit[6] */ +}; + +/* Resolution configuration */ +static const ov5640_reg_val_t ov5640_resolution_800_480_param[] = { + {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0x04}, + {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x07}, {0x3807, 0x9b}, + {0x3808, 0x03}, {0x3809, 0x20}, {0x380A, 0x01}, {0x380B, 0xe0}, + {0x380C, 0x07}, {0x380D, 0x68}, {0x380E, 0x03}, {0x380F, 0xd8}, + {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x06}, {0x3814, 0x31}, {0x3815, 0x31}, +}; + +static const ov5640_reg_val_t ov5640_resolution_vga_param[] = { + {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0x04}, + {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x07}, {0x3807, 0x9b}, + {0x3808, 0x02}, {0x3809, 0x80}, {0x380A, 0x01}, {0x380B, 0xe0}, + {0x380C, 0x07}, {0x380D, 0x68}, {0x380E, 0x03}, {0x380F, 0xd8}, + {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x06}, {0x3814, 0x31}, {0x3815, 0x31}, +}; + +static const ov5640_reg_val_t ov5640_resolution_qvga_param[] = { + {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0x04}, + {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x07}, {0x3807, 0x9b}, + {0x3808, 0x01}, {0x3809, 0x40}, {0x380A, 0x00}, {0x380B, 0xf0}, + {0x380C, 0x07}, {0x380D, 0x68}, {0x380E, 0x03}, {0x380F, 0xd8}, + {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x06}, {0x3814, 0x31}, {0x3815, 0x31}, +}; + +static const ov5640_reg_val_t ov5640_resolution_480_272_param[] = { + {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0xfa}, + {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x06}, {0x3807, 0xa9}, + {0x3808, 0x01}, {0x3809, 0xE0}, {0x380A, 0x01}, {0x380B, 0x10}, + {0x380C, 0x07}, {0x380D, 0x64}, {0x380E, 0x02}, {0x380F, 0xe4}, + {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x04}, {0x3814, 0x31}, {0x3815, 0x31}, +}; + +static const ov5640_reg_val_t ov5640_resolution_720p_param[] = { + {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0xfa}, + {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x06}, {0x3807, 0xa9}, + {0x3808, 0x05}, {0x3809, 0x00}, {0x380A, 0x02}, {0x380B, 0xd0}, + {0x380C, 0x07}, {0x380D, 0x64}, {0x380E, 0x02}, {0x380F, 0xe4}, + {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x04}, {0x3814, 0x31}, {0x3815, 0x31}, +}; + +static const ov5640_reg_val_t ov5640_resolution_1080p_param[] = { + {0x3800, 0x01}, {0x3801, 0x50}, {0x3802, 0x01}, {0x3803, 0xb2}, + {0x3804, 0x08}, {0x3805, 0xef}, {0x3806, 0x05}, {0x3807, 0xf1}, + {0x3808, 0x07}, {0x3809, 0x80}, {0x380A, 0x04}, {0x380B, 0x38}, + {0x380C, 0x09}, {0x380D, 0xc4}, {0x380E, 0x04}, {0x380F, 0x60}, + {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x04}, {0x3814, 0x11}, {0x3815, 0x11}, +}; + +/* DVP clock */ +static const ov5640_clock_config_t ov5640_dvp_clock_configs[] = { + { + .resolution = (uint32_t)video_resolution_800_480, + .pllctrl1 = 0x11, + .pllctrl2 = 0x46, + .vfifoctrl0c = 0x22, + .pclkdiv = 0x02, + .pclkperiod = 0x22, + }, + { + .resolution = (uint32_t)video_resolution_vga, + .pllctrl1 = 0x11, + .pllctrl2 = 0x46, + .vfifoctrl0c = 0x22, + .pclkdiv = 0x02, + .pclkperiod = 0x22, + }, + { + .resolution = (uint32_t)video_resolution_qvga, + .pllctrl1 = 0x11, + .pllctrl2 = 0x46, + .vfifoctrl0c = 0x22, + .pclkdiv = 0x02, + .pclkperiod = 0x22, + }, + { + .resolution = (uint32_t)video_resolution_480_272, + .pllctrl1 = 0x21, + .pllctrl2 = 0x69, + .vfifoctrl0c = 0x20, + .pclkdiv = 0x04, + .pclkperiod = 0x16, + }, + { + .resolution = (uint32_t)video_resolution_720p, + .pllctrl1 = 0x21, + .pllctrl2 = 0x69, + .vfifoctrl0c = 0x20, + .pclkdiv = 0x04, + .pclkperiod = 0x16, + }, + { + .resolution = (uint32_t)video_resolution_1080p, + .pllctrl1 = 0x21, + .pllctrl2 = 0x69, + .vfifoctrl0c = 0x20, + .pclkdiv = 0x04, + .pclkperiod = 0x16, + }, +}; + +static const ov5640_light_mode_config_t ov5640_light_mode_configs[] = { + /* Auto. */ + { + .lightmode = camera_light_mode_auto, + .awbctrl = 0x00, + .awbr_h = 0x04, + .awbr_l = 0x00, + .awbg_h = 0x04, + .awbg_l = 0x00, + .awbb_h = 0x04, + .awbb_l = 0x00, + }, + /* Sunny. */ + { + .lightmode = camera_light_mode_sunny, + .awbctrl = 0x01, + .awbr_h = 0x06, + .awbr_l = 0x1c, + .awbg_h = 0x04, + .awbg_l = 0x00, + .awbb_h = 0x04, + .awbb_l = 0xf3, + }, + /* Office. */ + { + .lightmode = camera_light_mode_office, + .awbctrl = 0x01, + .awbr_h = 0x05, + .awbr_l = 0x48, + .awbg_h = 0x04, + .awbg_l = 0x00, + .awbb_h = 0x07, + .awbb_l = 0xcf, + }, + /* Cloudy. */ + { + .lightmode = camera_light_mode_cloudy, + .awbctrl = 0x01, + .awbr_h = 0x06, + .awbr_l = 0x48, + .awbg_h = 0x04, + .awbg_l = 0x00, + .awbb_h = 0x04, + .awbb_l = 0xd3, + }, + /* Home. */ + { + .lightmode = camera_light_mode_home, + .awbctrl = 0x01, + .awbr_h = 0x04, + .awbr_l = 0x10, + .awbg_h = 0x04, + .awbg_l = 0x00, + .awbb_h = 0x08, + .awbb_l = 0x40, + }, +}; + +static const ov5640_special_effect_config_t ov5640_special_effect_configs[] = { + /* Normal. */ + { + .effect = camera_special_effect_normal, + .sdectrl0 = 0x06, + .sdectrl3 = 0x40, + .sdectrl4 = 0x10, + }, + /* Bluish. */ + { + .effect = camera_special_effect_bluish, + .sdectrl0 = 0x1e, + .sdectrl3 = 0xa0, + .sdectrl4 = 0x40, + }, + /* Redish. */ + { + .effect = camera_special_effect_redish, + .sdectrl0 = 0x1e, + .sdectrl3 = 0x80, + .sdectrl4 = 0xc0, + }, + /* B & W */ + { + .effect = camera_special_effect_bw, + .sdectrl0 = 0x1e, + .sdectrl3 = 0x80, + .sdectrl4 = 0x80, + }, + /* Sepia. */ + { + .effect = camera_special_effect_sepia, + .sdectrl0 = 0x1e, + .sdectrl3 = 0x40, + .sdectrl4 = 0xa0, + }, + /* Negtive. */ + { + .effect = camera_special_effect_negtive, + .sdectrl0 = 0x40, + .sdectrl3 = 0x40, + .sdectrl4 = 0x10, + }, + /* Greenish. */ + { + .effect = camera_special_effect_greenish, + .sdectrl0 = 0x1e, + .sdectrl3 = 0x60, + .sdectrl4 = 0x60, + }, +}; + +static const ov5640_clock_config_t *ov5640_get_clock_config(const camera_config_t *config) +{ + uint32_t i; + + if (camera_interface_dvp == config->interface) + { + for (i = 0; i < ARRAY_SIZE(ov5640_dvp_clock_configs); i++) + { + if (HPM_CAMERA_RESOLUTION(config->width, config->height) == ov5640_dvp_clock_configs[i].resolution) + { + return &ov5640_dvp_clock_configs[i]; + } + } + } + + return NULL; +} + +hpm_stat_t ov5640_read_register(camera_context_t *context, uint16_t reg, uint8_t *buf) +{ + uint8_t r[2]; + r[0] = reg >> 8; + r[1] = reg & 0xFF; + return i2c_master_address_read(context->ptr, OV5640_I2C_ADDR, r, sizeof(r), buf, 1); +} + +hpm_stat_t ov5640_write_register(camera_context_t *context, uint16_t reg, uint8_t val) +{ + uint8_t r[2]; + r[0] = reg >> 8; + r[1] = reg & 0xFF; + return i2c_master_address_write(context->ptr, OV5640_I2C_ADDR, r, sizeof(r), &val, 1); +} + +hpm_stat_t ov5640_write_multi_registers(camera_context_t *context, const ov5640_reg_val_t regval[], uint32_t len) +{ + uint32_t i; + hpm_stat_t stat = status_success; + + for (i = 0; i < len; i++) + { + HPM_CHECK_RET(ov5640_write_register(context, regval[i].regaddr, regval[i].regval)); + } + + return stat; +} + +hpm_stat_t ov5640_software_reset(camera_context_t *context) +{ + hpm_stat_t stat = status_success; + + HPM_CHECK_RET(ov5640_write_register(context, 0x3103, 0x11)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3008, 0x82)); + + return stat; +} + +hpm_stat_t ov5640_set_pixel_format(camera_context_t *context, display_pixel_format_t pixel_format) +{ + hpm_stat_t stat = status_success; + + switch (pixel_format) + { + case display_pixel_format_yuv422: + HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x3F)); + HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x00)); + break; + case display_pixel_format_rgb565: + HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x6F)); + HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x01)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t ov5640_check_chip_id(camera_context_t *context) +{ + hpm_stat_t stat = status_success; + uint8_t val_h = 0; + uint8_t val_l = 0; + + HPM_CHECK_RET(ov5640_read_register(context, OV5640_CHIP_ID_HIGH_BYTE_ADDR, &val_h)); + HPM_CHECK_RET(ov5640_read_register(context, OV5640_CHIP_ID_LOW_BYTE_ADDR, &val_l)); + + if (val_h != OV5640_CHIP_ID_HIGH_BYTE_VALUE) { + return status_fail; + } + + if (val_l != OV5640_CHIP_ID_LOW_BYTE_VALUE) { + return status_fail; + } + + return stat; +} + +hpm_stat_t ov5640_set_image_size(camera_context_t *context, camera_config_t *ov_config) +{ + hpm_stat_t stat = status_success; + + switch(HPM_CAMERA_RESOLUTION(ov_config->width, ov_config->height)) + { + case video_resolution_800_480: + stat = ov5640_write_multi_registers(context, ov5640_resolution_800_480_param, ARRAY_SIZE(ov5640_resolution_800_480_param)); + break; + case video_resolution_vga: + stat = ov5640_write_multi_registers(context, ov5640_resolution_vga_param, ARRAY_SIZE(ov5640_resolution_vga_param)); + break; + case video_resolution_qvga: + stat = ov5640_write_multi_registers(context, ov5640_resolution_qvga_param, ARRAY_SIZE(ov5640_resolution_qvga_param)); + break; + case video_resolution_480_272: + stat = ov5640_write_multi_registers(context, ov5640_resolution_480_272_param, ARRAY_SIZE(ov5640_resolution_480_272_param)); + break; + case video_resolution_720p: + stat = ov5640_write_multi_registers(context, ov5640_resolution_720p_param, ARRAY_SIZE(ov5640_resolution_720p_param)); + break; + case video_resolution_1080p: + stat = ov5640_write_multi_registers(context, ov5640_resolution_1080p_param, ARRAY_SIZE(ov5640_resolution_1080p_param)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t ov5640_set_clock_config(camera_context_t *context, camera_config_t *ov_config) +{ + hpm_stat_t stat = status_success; + const ov5640_clock_config_t *clock_config = ov5640_get_clock_config(ov_config); + + if(NULL == clock_config) + { + return status_invalid_argument; + } + + HPM_CHECK_RET(ov5640_write_register(context, 0x3035, clock_config->pllctrl1)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3036, clock_config->pllctrl2)); + HPM_CHECK_RET(ov5640_write_register(context, 0x460c, clock_config->vfifoctrl0c)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3824, clock_config->pclkdiv)); + HPM_CHECK_RET(ov5640_write_register(context, 0x4837, clock_config->pclkperiod)); + + return stat; +} + +hpm_stat_t ov5640_set_interface(camera_context_t *context, camera_config_t *ov_config) +{ + hpm_stat_t stat = status_success; + + if (camera_interface_dvp == ov_config->interface) + { + HPM_CHECK_RET(ov5640_write_register(context, 0x3034, 0x1a)); + + /* Set Frex, Vsync, Href, PCLK, data, GPIO to output. */ + HPM_CHECK_RET(ov5640_write_register(context, 0x3017, 0xFF)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3018, 0xFF)); + + /* DVP mode */ + HPM_CHECK_RET(ov5640_write_register(context, 0x300e, 0x58)); + } + + return stat; +} + +hpm_stat_t ov5640_start(camera_context_t *context) +{ + return ov5640_write_register(context, 0x3008, 0x02); +} + +hpm_stat_t ov5640_stop(camera_context_t *context) +{ + return ov5640_write_register(context, 0x3008, 0x42); +} + +hpm_stat_t ov5640_flip(camera_context_t *context) +{ + hpm_stat_t stat = status_success; + HPM_CHECK_RET(ov5640_write_register(context, 0x3821, 1)); + return stat; +} + + +hpm_stat_t ov5640_set_brightness(camera_context_t *context, int32_t brightness) +{ + hpm_stat_t stat = status_success; + + if ((brightness < -4) || (brightness > 4)) + { + return status_invalid_argument; + } + + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); + if (brightness >= 0) + { + HPM_CHECK_RET(ov5640_write_register(context, 0x5588, 0x01)); + } + else + { + brightness = -brightness; + HPM_CHECK_RET(ov5640_write_register(context, 0x5588, 0x09)); + } + + HPM_CHECK_RET(ov5640_write_register(context, 0x5587, ((uint8_t)brightness) << 4U)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); + + return stat; +} + +hpm_stat_t ov5640_set_contrast(camera_context_t *context, int32_t contrast) +{ + hpm_stat_t stat = status_success; + uint8_t regval; + + if ((-4 > contrast) || (4 < contrast)) + { + return status_invalid_argument; + } + + contrast = 0x20 + contrast * 0x04; + regval = (uint8_t)contrast; + + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x5580, 0x04)); + HPM_CHECK_RET(ov5640_write_register(context, 0x5585, regval)); + HPM_CHECK_RET(ov5640_write_register(context, 0x5586, regval)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); + + return stat; +} + +hpm_stat_t ov5640_set_saturation(camera_context_t *context, int32_t saturation) +{ + hpm_stat_t stat = status_success; + uint8_t regval; + + if ((-4 > saturation) || (4 < saturation)) + { + return status_invalid_argument; + } + + saturation = 0x40 + saturation * 0x10; + regval = (uint8_t)saturation; + + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x5580, 0x02)); + HPM_CHECK_RET(ov5640_write_register(context, 0x5583, regval)); + HPM_CHECK_RET(ov5640_write_register(context, 0x5584, regval)); + HPM_CHECK_RET(ov5640_write_register(context, 0x5588, 0x41)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); + + return stat; +} + +hpm_stat_t ov5640_set_light_mode(camera_context_t *context, int32_t lightmode) +{ + hpm_stat_t stat = status_success; + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(ov5640_light_mode_configs); i++) + { + if (lightmode == (int32_t)ov5640_light_mode_configs[i].lightmode) + { + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x3406, ov5640_light_mode_configs[i].awbctrl)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3400, ov5640_light_mode_configs[i].awbr_h)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3401, ov5640_light_mode_configs[i].awbr_l)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3402, ov5640_light_mode_configs[i].awbg_h)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3403, ov5640_light_mode_configs[i].awbg_l)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3404, ov5640_light_mode_configs[i].awbb_h)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3405, ov5640_light_mode_configs[i].awbb_l)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); + + return stat; + } + } + + /* No configuration found. */ + return status_invalid_argument; +} + +hpm_stat_t ov5640_set_special_effect(camera_context_t *context, int32_t effect) +{ + hpm_stat_t stat = status_success; + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(ov5640_special_effect_configs); i++) + { + if (effect == (int32_t)ov5640_special_effect_configs[i].effect) + { + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x5580, ov5640_special_effect_configs[i].sdectrl0)); + HPM_CHECK_RET(ov5640_write_register(context, 0x5583, ov5640_special_effect_configs[i].sdectrl3)); + HPM_CHECK_RET(ov5640_write_register(context, 0x5584, ov5640_special_effect_configs[i].sdectrl4)); + + HPM_CHECK_RET(ov5640_write_register(context, 0x5003, 0x08)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); + HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); + + return stat; + } + } + + /* No configuration found. */ + return status_invalid_argument; +} + +hpm_stat_t ov5640_init(camera_context_t *context, camera_config_t *ov_config) +{ + hpm_stat_t stat = status_success; + + /* check the chip id */ + HPM_CHECK_RET(ov5640_check_chip_id(context)); + + /* Initialize: load registers value */ + HPM_CHECK_RET(ov5640_write_multi_registers(context, ov5640_init_param, ARRAY_SIZE(ov5640_init_param))); + + /* configure image windowing */ + HPM_CHECK_RET(ov5640_set_image_size(context, ov_config)); + + HPM_CHECK_RET(ov5640_flip(context)); + + /* configure Pixel format */ + HPM_CHECK_RET(ov5640_set_pixel_format(context, ov_config->pixel_format)); + + /* configure PCLK clock */ + HPM_CHECK_RET(ov5640_set_clock_config(context, ov_config)); + + /* configure interface */ + HPM_CHECK_RET(ov5640_set_interface(context, ov_config)); + + /* configure contrast */ + HPM_CHECK_RET(ov5640_set_contrast(context, 2)); + + /* camera start */ + HPM_CHECK_RET(ov5640_write_register(context, 0x3008, 0x02)); + + return stat; +} + +void ov5640_power_up(camera_context_t *context) +{ + assert((context->delay_ms != NULL) && (context->write_rst != NULL) && (context->write_pwdn != NULL)); + + context->write_rst(OV5640_RST_ACTIVE); + context->write_pwdn(OV5640_PWDN_ACTIVE); + context->delay_ms(5); + context->write_pwdn(OV5640_PWDN_INACTIVE); + context->delay_ms(2); + context->write_rst(OV5640_RST_INACTIVE); + context->delay_ms(20); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h new file mode 100644 index 0000000000..29d8aa311c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_OV5640_H +#define HPM_OV5640_H + +#include "hpm_common.h" +#include "hpm_camera_config.h" + +#define OV5640_ACTIVE_IMAGE_WIDTH (2592U) +#define OV5640_ACTIVE_IMAGE_HEIGHT (1944U) +#define OV5640_I2C_ADDR (0x3CU) +#define OV5640_CHIP_ID_HIGH_BYTE_ADDR (0x300A) +#define OV5640_CHIP_ID_HIGH_BYTE_VALUE (0x56) +#define OV5640_CHIP_ID_LOW_BYTE_ADDR (0x300B) +#define OV5640_CHIP_ID_LOW_BYTE_VALUE (0x40) + +#define OV5640_RST_ACTIVE 0 +#define OV5640_RST_INACTIVE 1 +#define OV5640_PWDN_ACTIVE 1 +#define OV5640_PWDN_INACTIVE 0 + +/* Camera clock configuration elements. */ +typedef struct { + uint32_t resolution; + uint8_t fps; + uint8_t pllctrl1; + uint8_t pllctrl2; + uint8_t vfifoctrl0c; + uint8_t pclkdiv; + uint8_t pclkperiod; +} ov5640_clock_config_t; + +typedef struct { + uint8_t lightmode; + uint8_t awbctrl; + uint8_t awbr_h; + uint8_t awbr_l; + uint8_t awbg_h; + uint8_t awbg_l; + uint8_t awbb_h; + uint8_t awbb_l; +} ov5640_light_mode_config_t; + +typedef struct { + uint8_t effect; + uint8_t sdectrl0; + uint8_t sdectrl3; + uint8_t sdectrl4; +} ov5640_special_effect_config_t; + +typedef struct { + uint16_t regaddr; + uint8_t regval; +} ov5640_reg_val_t; + +typedef struct { + uint32_t resolution; /*!< Resolution. */ + ov5640_reg_val_t param[]; /*!< register value from 0x3800 to 0x3813. */ +} ov5640_resolution_param_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ov5640 initialization + */ +hpm_stat_t ov5640_init(camera_context_t *context, camera_config_t *ov_config); + +/* + * ov5640 read register + */ +hpm_stat_t ov5640_read_register(camera_context_t *context, uint16_t reg, uint8_t *buf); + +/* + * ov5640 write register + */ +hpm_stat_t ov5640_write_register(camera_context_t *context, uint16_t reg, uint8_t val); + +/* + * ov5640 write multi register + */ +hpm_stat_t ov5640_write_multi_registers(camera_context_t *context, const ov5640_reg_val_t regval[], uint32_t len); + +/* + * ov5640 softreset + */ +hpm_stat_t ov5640_software_reset(camera_context_t *context); + +/* + * ov5640 set pixel format + */ +hpm_stat_t ov5640_set_pixel_format(camera_context_t *context, display_pixel_format_t pixel_format); + +/* + * ov5640 check chip id + */ +hpm_stat_t ov5640_check_chip_id(camera_context_t *context); + +/* + * ov5640 set image size + */ +hpm_stat_t ov5640_set_image_size(camera_context_t *context, camera_config_t *ov_config); + +/* + * ov5640 set clock config + */ +hpm_stat_t ov5640_set_clock_config(camera_context_t *context, camera_config_t *ov_config); + +/* + * ov5640 set interface + */ +hpm_stat_t ov5640_set_interface(camera_context_t *context, camera_config_t *ov_config); + +/** + * @brief set ov5640 flip + * + * @param context @ref camera_context_t + * @return hpm_stat_t + */ +hpm_stat_t ov5640_flip(camera_context_t *context); + +/* + * ov5640 start + */ +hpm_stat_t ov5640_start(camera_context_t *context); + +/* + * ov5640 stop + */ +hpm_stat_t ov5640_stop(camera_context_t *context); + +/* + * ov5640 set brightness + */ +hpm_stat_t ov5640_set_brightness(camera_context_t *context, int32_t brightness); + +/* + * ov5640 set contrast + */ +hpm_stat_t ov5640_set_contrast(camera_context_t *context, int32_t contrast); + +/* + * ov5640 set saturation + */ +hpm_stat_t ov5640_set_saturation(camera_context_t *context, int32_t saturation); + +/* + * ov5640 set environment light mode + */ +hpm_stat_t ov5640_set_light_mode(camera_context_t *context, int32_t lightmode); + +/* + * ov5640 set special effect + */ +hpm_stat_t ov5640_set_special_effect(camera_context_t *context, int32_t effect); + +/** + * @brief ov5640 power up + * + * @param [in] context camera_context_t + */ +void ov5640_power_up(camera_context_t *context); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_OV5640_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c new file mode 100644 index 0000000000..55f15d41d5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_ov7725.h" + +hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) +{ + assert(camera_context->delay_ms != NULL); + + hpm_stat_t stat = status_success; + +#ifdef HPM_CAM_EXECUTE_POWER_UP_SEQUENCE + /* execute power up sequence */ + ov7725_power_up(camera_context); +#endif + + /* software reset */ + stat = ov7725_software_reset(camera_context); + if (stat != status_success) { + return stat; + } + camera_context->delay_ms(50); + + stat = ov7725_init(camera_context, camera_config); + + return stat; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c new file mode 100644 index 0000000000..5c9e8c405b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_ov7725.h" + +static const uint8_t ov7725_default_regs[][2] = { + {COM3, COM3_SWAP_YUV}, + {COM7, COM7_RES_VGA | COM7_FMT_RGB565}, + + {COM4, 0x01}, /* bypass PLL */ + {CLKRC, 0xC0}, /* Res/Bypass pre-scalar */ + + /* + * VGA Window Size + */ + {HSTART, 0x23}, + {HSIZE, 0xA0}, + {VSTART, 0x07}, + {VSIZE, 0xF0}, + {HREF, 0x00}, + + /* + * Scale down to VGA Resolution + */ + {HOUTSIZE, 0xA0}, + {VOUTSIZE, 0xF0}, + + {COM12, 0x03}, + {EXHCH, 0x00}, + {TGT_B, 0x7F}, + {FIXGAIN, 0x09}, + {AWB_CTRL0, 0xE0}, + {DSP_CTRL1, 0xFF}, + + {DSP_CTRL2, DSP_CTRL2_VDCW_EN | DSP_CTRL2_HDCW_EN | DSP_CTRL2_HZOOM_EN | DSP_CTRL2_VZOOM_EN}, + + {DSP_CTRL3, 0x00}, + {DSP_CTRL4, 0x00}, + {DSPAUTO, 0xFF}, + + {COM8, 0xF0}, + {COM6, 0xC5}, + {COM9, 0x11}, + {COM10, COM10_VSYNC_NEG | COM10_PCLK_MASK}, /* Invert VSYNC and MASK PCLK */ + {BDBASE, 0x7F}, + {DBSTEP, 0x03}, + {AEW, 0x70}, + {AEB, 0x43}, + {VPT, 0xA1}, + {EXHCL, 0x00}, + {AWB_CTRL3, 0xAA}, + {COM8, 0xFF}, + + /* + * Gamma + */ + {GAM1, 0x0C}, + {GAM2, 0x16}, + {GAM3, 0x2A}, + {GAM4, 0x4E}, + {GAM5, 0x61}, + {GAM6, 0x6F}, + {GAM7, 0x7B}, + {GAM8, 0x86}, + {GAM9, 0x8E}, + {GAM10, 0x97}, + {GAM11, 0xA4}, + {GAM12, 0xAF}, + {GAM13, 0xC5}, + {GAM14, 0xD7}, + {GAM15, 0xE8}, + + {SLOP, 0x20}, + {EDGE1, 0x05}, + {EDGE2, 0x03}, + {EDGE3, 0x00}, + {DNSOFF, 0x01}, + + {MTX1, 0xB0}, + {MTX2, 0x9D}, + {MTX3, 0x13}, + {MTX4, 0x16}, + {MTX5, 0x7B}, + {MTX6, 0x91}, + {MTX_CTRL, 0x1E}, + + {BRIGHTNESS, 0x08}, + {CONTRAST, 0x30}, + {UVADJ0, 0x81}, + {SDE, (SDE_CONT_BRIGHT_EN | SDE_SATURATION_EN)}, + + /* + * For 30 fps/60Hz + */ + {DM_LNL, 0x00}, + {DM_LNH, 0x00}, + {BDBASE, 0x7F}, + {DBSTEP, 0x03}, + + /* + * Lens Correction, should be tuned with real camera module + */ + {LC_RADI, 0x10}, + {LC_COEF, 0x10}, + {LC_COEFB, 0x14}, + {LC_COEFR, 0x17}, + {LC_CTR, 0x05}, + {COM5, 0xF5}, +}; + +hpm_stat_t ov7725_read_register(camera_context_t *context, uint8_t reg, uint8_t *buf) +{ + return i2c_master_address_read(context->ptr, OV7725_I2C_ADDR, ®, 1, buf, 1); +} + +hpm_stat_t ov7725_write_register(camera_context_t *context, uint8_t reg, uint8_t val) +{ + return i2c_master_address_write(context->ptr, OV7725_I2C_ADDR, ®, 1, &val, 1); +} + +void ov7725_restore_default_values(camera_context_t *context) +{ + uint32_t i; + for (i = 0; i < (ARRAY_SIZE(ov7725_default_regs)); i++) + { + ov7725_write_register(context, ov7725_default_regs[i][0], ov7725_default_regs[i][1]); + } +} + +hpm_stat_t ov7725_software_reset(camera_context_t *context) +{ + hpm_stat_t stat = status_success; + + stat = ov7725_write_register(context, COM7, COM7_RESET); + if (stat != status_success) { + return stat; + } + + return stat; +} + +hpm_stat_t ov7725_check_chip_id(camera_context_t *context) +{ + hpm_stat_t stat = status_success; + uint8_t val_h = 0; + uint8_t val_l = 0; + + HPM_CHECK_RET(ov7725_read_register(context, OV7725_CHIP_ID_HIGH_BYTE_ADDR, &val_h)); + HPM_CHECK_RET(ov7725_read_register(context, OV7725_CHIP_ID_LOW_BYTE_ADDR, &val_l)); + + if (val_h != OV7725_CHIP_ID_HIGH_BYTE_VALUE) { + return status_fail; + } + + if (val_l != OV7725_CHIP_ID_LOW_BYTE_VALUE) { + return status_fail; + } + + return stat; +} + +static hpm_stat_t ov7725_set_framesize(camera_context_t *context, uint16_t width, uint16_t height) +{ + hpm_stat_t stat = status_success; + uint32_t hstart = 0x22U << 2; + uint32_t vstart = 0x7U << 1; + uint32_t hsize = width + 16; + + stat |= ov7725_write_register(context, HSTART, hstart >> 2); + stat |= ov7725_write_register(context, HSIZE, hsize >> 2); + stat |= ov7725_write_register(context, VSTART, vstart >> 1); + stat |= ov7725_write_register(context, VSIZE, height >> 1); + + stat |= ov7725_write_register(context, HOUTSIZE, width >> 2); + stat |= ov7725_write_register(context, VOUTSIZE, height >> 1); + + stat |= ov7725_write_register(context, HREF, + ((vstart & 1) << 6) | ((hstart & 3) << 4) | ((height & 1) << 2) | ((hsize & 3) << 0)); + + stat = ov7725_write_register(context, EXHCH, ((height & 0x1) << 2) | (width & 0x3)); + if (stat != status_success) { + return stat; + } + return stat; +} + +hpm_stat_t ov7725_set_pixel_format(camera_context_t *context, display_pixel_format_t pixel_format) +{ + hpm_stat_t stat = status_success; + uint8_t val = 0; + + stat |= ov7725_read_register(context, COM7, &val); + val &= ~0x1F; + switch (pixel_format) { + case display_pixel_format_rgb565: + val |= COM7_FMT_RGB565; + break; + case display_pixel_format_rgb444: + val |= COM7_FMT_RGB444; + break; + default: + stat = status_invalid_argument; + break; + } + if (stat != status_success) { + return stat; + } + + stat |= ov7725_write_register(context, COM7, val); + if (stat != status_success) { + return stat; + } + return stat; +} + +hpm_stat_t ov7725_init(camera_context_t *context, camera_config_t *ov_config) +{ + hpm_stat_t stat = status_success; + + ov7725_restore_default_values(context); + + stat |= ov7725_write_register(context, CLKRC, 0x2); + stat |= ov7725_write_register(context, COM4, 0x41); + stat |= ov7725_write_register(context, EXHCL, 0); + stat |= ov7725_write_register(context, DM_LNL, 0); + stat |= ov7725_write_register(context, DM_LNH, 0); + stat |= ov7725_write_register(context, ADVFL, 0); + stat |= ov7725_write_register(context, ADVFH, 0); + stat |= ov7725_write_register(context, COM5, 0x65); + stat |= ov7725_write_register(context, COM10, 0); + stat |= ov7725_write_register(context, COM3, 0); + stat |= ov7725_write_register(context, COM2, 0x3); + stat |= ov7725_set_framesize(context, ov_config->width, ov_config->height); + stat |= ov7725_set_pixel_format(context, ov_config->pixel_format); + if (stat != status_success) { + return stat; + } + + return stat; +} + +void ov7725_power_up(camera_context_t *context) +{ + assert((context->delay_ms != NULL) && (context->write_rst != NULL) && (context->write_pwdn != NULL)); + + context->write_rst(OV7725_RST_ACTIVE); + context->write_pwdn(OV7725_PWDN_ACTIVE); + context->delay_ms(5); + context->write_pwdn(OV7725_PWDN_INACTIVE); + context->delay_ms(2); + context->write_rst(OV7725_RST_INACTIVE); + context->delay_ms(20); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h new file mode 100644 index 0000000000..550ff3ae39 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_OV7725_H +#define HPM_OV7725_H +#include "hpm_common.h" +#include "hpm_camera_config.h" + +#define OV7725_ACTIVE_IMAGE_WIDTH (480U) +#define OV7725_ACTIVE_IMAGE_HEIGHT (480U) +#define OV7725_I2C_ADDR (0x21U) +#define OV7725_CHIP_ID_HIGH_BYTE_ADDR (0x0A) +#define OV7725_CHIP_ID_HIGH_BYTE_VALUE (0x77) +#define OV7725_CHIP_ID_LOW_BYTE_ADDR (0x0B) +#define OV7725_CHIP_ID_LOW_BYTE_VALUE (0x21) /* need to check */ + +#define OV7725_RST_ACTIVE 0 +#define OV7725_RST_INACTIVE 1 +#define OV7725_PWDN_ACTIVE 1 +#define OV7725_PWDN_INACTIVE 0 + +#define GAIN (0x00U) /* AGC – Gain control gain setting */ +#define BLUE (0x01U) /* AWB – Blue channel gain setting */ +#define RED (0x02U) /* AWB – Red channel gain setting */ +#define GREEN (0x03U) /* AWB – Green channel gain setting */ + +#define BAVG (0x05U) /* U/B Average Level */ +#define GAVG (0x06U) /* Y/Gb Average Level */ +#define RAVG (0x07U) /* V/R Average Level */ +#define AECH (0x08U) /* Exposure Value – AEC MSBs */ + +#define COM2 (0x09U) /* Common Control 2 */ +#define COM2_SOFT_SLEEP (0x10U) /* Soft sleep mode */ +#define COM2_OUT_DRIVE_1x (0x00U) /* Output drive capability 1x */ +#define COM2_OUT_DRIVE_2x (0x01U) /* Output drive capability 2x */ +#define COM2_OUT_DRIVE_3x (0x02U) /* Output drive capability 3x */ +#define COM2_OUT_DRIVE_4x (0x03U) /* Output drive capability 4x */ + +#define PID (0x0AU) /* Product ID Number MSB */ +#define VER (0x0BU) /* Product ID Number LSB */ + +#define COM3 (0x0CU) /* Common Control 3 */ +#define COM3_VFLIP (0x80U) /* Vertical flip image ON/OFF selection */ +#define COM3_MIRROR (0x40U) /* Horizontal mirror image ON/OFF selection */ +#define COM3_SWAP_BR (0x20U) /* Swap B/R output sequence in RGB output mode */ +#define COM3_SWAP_YUV (0x10U) /* Swap Y/UV output sequence in YUV output mode */ +#define COM3_SWAP_MSB (0x08U) /* Swap output MSB/LSB */ +#define COM3_TRI_CLOCK (0x04U) /* Tri-state option for output clock at power-down period */ +#define COM3_TRI_DATA (0x02U) /* Tri-state option for output data at power-down period */ +#define COM3_COLOR_BAR (0x01U) /* Sensor color bar test pattern output enable */ + +#define COM4 (0x0DU) /* Common Control 4 */ +#define COM4_PLL_BYPASS (0x00U) /* Bypass PLL */ +#define COM4_PLL_4x (0x40U) /* PLL frequency 4x */ +#define COM4_PLL_6x (0x80U) /* PLL frequency 6x */ +#define COM4_PLL_8x (0xc0U) /* PLL frequency 8x */ +#define COM4_AEC_FULL (0x00U) /* AEC evaluate full window */ +#define COM4_AEC_1_2 (0x10U) /* AEC evaluate 1/2 window */ +#define COM4_AEC_1_4 (0x20U) /* AEC evaluate 1/4 window */ +#define COM4_AEC_2_3 (0x30U) /* AEC evaluate 2/3 window */ + +#define COM5 (0x0EU) /* Common Control 5 */ +#define COM5_AFR (0x80U) /* Auto frame rate control ON/OFF selection (night mode) */ +#define COM5_AFR_SPEED (0x40U) /* Auto frame rate control speed selection */ +#define COM5_AFR_0 (0x00U) /* No reduction of frame rate */ +#define COM5_AFR_1_2 (0x10U) /* Max reduction to 1/2 frame rate */ +#define COM5_AFR_1_4 (0x20U) /* Max reduction to 1/4 frame rate */ +#define COM5_AFR_1_8 (0x30U) /* Max reduction to 1/8 frame rate */ +#define COM5_AFR_4x (0x04U) /* Add frame when AGC reaches 4x gain */ +#define COM5_AFR_8x (0x08U) /* Add frame when AGC reaches 8x gain */ +#define COM5_AFR_16x (0x0cU) /* Add frame when AGC reaches 16x gain */ +#define COM5_AEC_NO_LIMIT (0x01U) /* No limit to AEC increase step */ + +#define COM6 (0x0FU) /* Common Control 6 */ +#define COM6_AUTO_WINDOW (0x01U) /* Auto window setting ON/OFF selection when format changes */ + +#define AEC (0x10U) /* AEC[7:0] (see register AECH for AEC[15:8]) */ +#define CLKRC (0x11U) /* Internal Clock */ + +#define COM7 (0x12U) /* Common Control 7 */ +#define COM7_RESET (0x80U) /* SCCB Register Reset */ +#define COM7_RES_VGA (0x00U) /* Resolution VGA */ +#define COM7_RES_QVGA (0x40U) /* Resolution QVGA */ +#define COM7_BT656 (0x20U) /* BT.656 protocol ON/OFF */ +#define COM7_SENSOR_RAW (0x10U) /* Sensor RAW */ +#define COM7_FMT_GBR422 (0x02U) /* RGB output format GBR422 */ +#define COM7_FMT_RGB565 (0x06U) /* RGB output format RGB565 */ +#define COM7_FMT_RGB555 (0x0AU) /* RGB output format RGB555 */ +#define COM7_FMT_RGB444 (0x0EU) /* RGB output format RGB444 */ +#define COM7_FMT_YUV (0x00U) /* Output format YUV */ +#define COM7_FMT_P_BAYER (0x01U) /* Output format Processed Bayer RAW */ +#define COM7_FMT_R_BAYER (0x03U) /* Output format Bayer RAW */ + +#define COM8 (0x13U) /* Common Control 8 */ +#define COM8_FAST_AUTO (0x80U) /* Enable fast AGC/AEC algorithm */ +#define COM8_STEP_VSYNC (0x00U) /* AEC - Step size limited to vertical blank */ +#define COM8_STEP_UNLIMIT (0x40U) /* AEC - Step size unlimited step size */ +#define COM8_BANDF_EN (0x20U) /* Banding filter ON/OFF */ +#define COM8_AEC_BANDF (0x10U) /* Enable AEC below banding value */ +#define COM8_AEC_FINE_EN (0x08U) /* Fine AEC ON/OFF control */ +#define COM8_AGC_EN (0x04U) /* AGC Enable */ +#define COM8_AWB_EN (0x02U) /* AWB Enable */ +#define COM8_AEC_EN (0x01U) /* AEC Enable */ + +#define COM9 (0x14U) /* Common Control 9 */ +#define COM9_HISTO_AVG (0x80U) /* Histogram or average based AEC/AGC selection */ +#define COM9_AGC_GAIN_2x (0x00U) /* Automatic Gain Ceiling 2x */ +#define COM9_AGC_GAIN_4x (0x10U) /* Automatic Gain Ceiling 4x */ +#define COM9_AGC_GAIN_8x (0x20U) /* Automatic Gain Ceiling 8x */ +#define COM9_AGC_GAIN_16x (0x30U) /* Automatic Gain Ceiling 16x */ +#define COM9_AGC_GAIN_32x (0x40U) /* Automatic Gain Ceiling 32x */ +#define COM9_DROP_VSYNC (0x04U) /* Drop VSYNC output of corrupt frame */ +#define COM9_DROP_HREF (0x02U) /* Drop HREF output of corrupt frame */ + +#define COM10 (0x15U) /* Common Control 10 */ +#define COM10_NEGATIVE (0x80U) /* Output negative data */ +#define COM10_HSYNC_EN (0x40U) /* HREF changes to HSYNC */ +#define COM10_PCLK_FREE (0x00U) /* PCLK output option: free running PCLK */ +#define COM10_PCLK_MASK (0x20U) /* PCLK output option: masked during horizontal blank */ +#define COM10_PCLK_REV (0x10U) /* PCLK reverse */ +#define COM10_HREF_REV (0x08U) /* HREF reverse */ +#define COM10_VSYNC_FALLING (0x00U) /* VSYNC changes on falling edge of PCLK */ +#define COM10_VSYNC_RISING (0x04U) /* VSYNC changes on rising edge of PCLK */ +#define COM10_VSYNC_NEG (0x02U) /* VSYNC negative */ +#define COM10_OUT_RANGE_8 (0x01U) /* Output data range: Full range */ +#define COM10_OUT_RANGE_10 (0x00U) /* Output data range: Data from [10] to [F0] (8 MSBs) */ + +#define REG16 (0x16U) /* Register 16 */ +#define REG16_BIT_SHIFT (0x80U) /* Bit shift test pattern options */ +#define HSTART (0x17U) /* Horizontal Frame (HREF column) Start 8 MSBs (2 LSBs are at HREF[5:4]) */ +#define HSIZE (0x18U) /* Horizontal Sensor Size (2 LSBs are at HREF[1:0]) */ +#define VSTART (0x19U) /* Vertical Frame (row) Start 8 MSBs (1 LSB is at HREF[6]) */ +#define VSIZE (0x1AU) /* Vertical Sensor Size (1 LSB is at HREF[2]) */ +#define PSHFT (0x1BU) /* Data Format - Pixel Delay Select */ +#define REG_MIDH (0x1CU) /* Manufacturer ID Byte – High */ +#define REG_MIDL (0x1DU) /* Manufacturer ID Byte – Low */ +#define LAEC (0x1FU) /* Fine AEC Value - defines exposure value less than one row period */ + +#define COM11 (0x20U) /* Common Control 11 */ +#define COM11_SNGL_FRAME_EN (0x02U) /* Single frame ON/OFF selection */ +#define COM11_SNGL_XFR_TRIG (0x01U) /* Single frame transfer trigger */ + +#define BDBASE (0x22U) /* Banding Filter Minimum AEC Value */ +#define DBSTEP (0x23U) /* Banding Filter Maximum Step */ +#define AEW (0x24U) /* AGC/AEC - Stable Operating Region (Upper Limit) */ +#define AEB (0x25U) /* AGC/AEC - Stable Operating Region (Lower Limit) */ +#define VPT (0x26U) /* AGC/AEC Fast Mode Operating Region */ +#define REG28 (0x28U) /* Selection on the number of dummy rows, N */ +#define HOUTSIZE (0x29U) /* Horizontal Data Output Size MSBs (2 LSBs at register EXHCH[1:0]) */ +#define EXHCH (0x2AU) /* Dummy Pixel Insert MSB */ +#define EXHCL (0x2BU) /* Dummy Pixel Insert LSB */ +#define VOUTSIZE (0x2CU) /* Vertical Data Output Size MSBs (LSB at register EXHCH[2]) */ +#define ADVFL (0x2DU) /* LSB of Insert Dummy Rows in Vertical Sync (1 bit equals 1 row) */ +#define ADVFH (0x2EU) /* MSB of Insert Dummy Rows in Vertical Sync */ +#define YAVE (0x2FU) /* Y/G Channel Average Value */ +#define LUMHTH (0x30U) /* Histogram AEC/AGC Luminance High Level Threshold */ +#define LUMLTH (0x31U) /* Histogram AEC/AGC Luminance Low Level Threshold */ +#define HREF (0x32U) /* Image Start and Size Control */ +#define DM_LNL (0x33U) /* Dummy Row Low 8 Bits */ +#define DM_LNH (0x34U) /* Dummy Row High 8 Bits */ +#define ADOFF_B (0x35U) /* AD Offset Compensation Value for B Channel */ +#define ADOFF_R (0x36U) /* AD Offset Compensation Value for R Channel */ +#define ADOFF_GB (0x37U) /* AD Offset Compensation Value for GB Channel */ +#define ADOFF_GR (0x38U) /* AD Offset Compensation Value for GR Channel */ +#define OFF_B (0x39U) /* AD Offset Compensation Value for B Channel */ +#define OFF_R (0x3AU) /* AD Offset Compensation Value for R Channel */ +#define OFF_GB (0x3BU) /* AD Offset Compensation Value for GB Channel */ +#define OFF_GR (0x3CU) /* AD Offset Compensation Value for GR Channel */ +#define COM12 (0x3DU) /* DC offset compensation for analog process */ + +#define COM13 (0x3EU) /* Common Control 13 */ +#define COM13_BLC_EN (0x80U) /* BLC enable */ +#define COM13_ADC_EN (0x40U) /* ADC channel BLC ON/OFF control */ +#define COM13_ANALOG_BLC (0x20U) /* Analog processing channel BLC ON/OFF control */ +#define COM13_ABLC_GAIN_EN (0x04U) /* ABLC gain trigger enable */ + +#define COM14 (0x3FU) /* Common Control 14 */ +#define COM15 (0x40U) /* Common Control 15 */ +#define COM16 (0x41U) /* Common Control 16 */ +#define TGT_B (0x42U) /* BLC Blue Channel Target Value */ +#define TGT_R (0x43U) /* BLC Red Channel Target Value */ +#define TGT_GB (0x44U) /* BLC Gb Channel Target Value */ +#define TGT_GR (0x45U) /* BLC Gr Channel Target Value */ + +#define LC_CTR (0x46U) /* Lens Correction Control */ +#define LC_CTR_RGB_COMP_1 (0x00U) /* R, G, and B channel compensation coefficient is set by LC_COEF ((0x49U)) */ +/* R, G, and B channel compensation coefficient is set by registers LC_COEFB ((0x4BU)), LC_COEF ((0x49U)), and LC_COEFR ((0x4CU)), respectively */ +#define LC_CTR_RGB_COMP_3 (0x04U) +#define LC_CTR_EN (0x01U) /* Lens correction enable */ +#define LC_XC (0x47U) /* X Coordinate of Lens Correction Center Relative to Array Center */ +#define LC_YC (0x48U) /* Y Coordinate of Lens Correction Center Relative to Array Center */ +#define LC_COEF (0x49U) /* Lens Correction Coefficient */ +#define LC_RADI (0x4AU) /* Lens Correction Radius */ +#define LC_COEFB (0x4BU) /* Lens Correction B Channel Compensation Coefficient */ +#define LC_COEFR (0x4CU) /* Lens Correction R Channel Compensation Coefficient */ + +#define FIXGAIN (0x4DU) /* Analog Fix Gain Amplifier */ +#define AREF0 (0x4EU) /* Sensor Reference Control */ +#define AREF1 (0x4FU) /* Sensor Reference Current Control */ +#define AREF2 (0x50U) /* Analog Reference Control */ +#define AREF3 (0x51U) /* ADC Reference Control */ +#define AREF4 (0x52U) /* ADC Reference Control */ +#define AREF5 (0x53U) /* ADC Reference Control */ +#define AREF6 (0x54U) /* Analog Reference Control */ +#define AREF7 (0x55U) /* Analog Reference Control */ +#define UFIX (0x60U) /* U Channel Fixed Value Output */ +#define VFIX (0x61U) /* V Channel Fixed Value Output */ +#define AWBB_BLK (0x62U) /* AWB Option for Advanced AWB */ + +#define AWB_CTRL0 (0x63U) /* AWB Control Byte 0 */ +#define AWB_CTRL0_GAIN_EN (0x80U) /* AWB gain enable */ +#define AWB_CTRL0_CALC_EN (0x40U) /* AWB calculate enable */ +#define AWB_CTRL0_WBC_MASK (0x0FU) /* WBC threshold 2 */ + +#define DSP_CTRL1 (0x64U) /* DSP Control Byte 1 */ +#define DSP_CTRL1_FIFO_EN (0x80U) /* FIFO enable/disable selection */ +#define DSP_CTRL1_UV_EN (0x40U) /* UV adjust function ON/OFF selection */ +#define DSP_CTRL1_SDE_EN (0x20U) /* SDE enable */ +#define DSP_CTRL1_MTRX_EN (0x10U) /* Color matrix ON/OFF selection */ +#define DSP_CTRL1_INTRP_EN (0x08U) /* Interpolation ON/OFF selection */ +#define DSP_CTRL1_GAMMA_EN (0x04U) /* Gamma function ON/OFF selection */ +#define DSP_CTRL1_BLACK_EN (0x02U) /* Black defect auto correction ON/OFF */ +#define DSP_CTRL1_WHITE_EN (0x01U) /* White defect auto correction ON/OFF */ + +#define DSP_CTRL2 (0x65U) /* DSP Control Byte 2 */ +#define DSP_CTRL2_VDCW_EN (0x08U) /* Vertical DCW enable */ +#define DSP_CTRL2_HDCW_EN (0x04U) /* Horizontal DCW enable */ +#define DSP_CTRL2_VZOOM_EN (0x02U) /* Vertical zoom out enable */ +#define DSP_CTRL2_HZOOM_EN (0x01U) /* Horizontal zoom out enable */ + +#define DSP_CTRL3 (0x66U) /* DSP Control Byte 3 */ +#define DSP_CTRL3_UV_EN (0x80U) /* UV output sequence option */ +#define DSP_CTRL3_CBAR_EN (0x20U) /* DSP color bar ON/OFF selection */ +#define DSP_CTRL3_FIFO_EN (0x08U) /* FIFO power down ON/OFF selection */ +#define DSP_CTRL3_SCAL1_PWDN (0x04U) /* Scaling module power down control 1 */ +#define DSP_CTRL3_SCAL2_PWDN (0x02U) /* Scaling module power down control 2 */ +#define DSP_CTRL3_INTRP_PWDN (0x01U) /* Interpolation module power down control */ + +#define DSP_CTRL4 (0x67U) /* DSP Control Byte 4 */ +#define DSP_CTRL4_YUV_RGB (0x00U) /* Output selection YUV or RGB */ +#define DSP_CTRL4_RAW8 (0x02U) /* Output selection RAW8 */ +#define DSP_CTRL4_RAW10 (0x03U) /* Output selection RAW10 */ + +#define AWB_BIAS (0x68U) /* AWB BLC Level Clip */ +#define AWB_CTRL1 (0x69U) /* AWB Control 1 */ +#define AWB_CTRL2 (0x6AU) /* AWB Control 2 */ + +#define AWB_CTRL3 (0x6BU) /* AWB Control 3 */ +#define AWB_CTRL3_ADVANCED (0x80U) /* AWB mode select - Advanced AWB */ +#define AWB_CTRL3_SIMPLE (0x00U) /* AWB mode select - Simple AWB */ + +#define AWB_CTRL4 (0x6CU) /* AWB Control 4 */ +#define AWB_CTRL5 (0x6DU) /* AWB Control 5 */ +#define AWB_CTRL6 (0x6EU) /* AWB Control 6 */ +#define AWB_CTRL7 (0x6FU) /* AWB Control 7 */ +#define AWB_CTRL8 (0x70U) /* AWB Control 8 */ +#define AWB_CTRL9 (0x71U) /* AWB Control 9 */ +#define AWB_CTRL10 (0x72U) /* AWB Control 10 */ +#define AWB_CTRL11 (0x73U) /* AWB Control 11 */ +#define AWB_CTRL12 (0x74U) /* AWB Control 12 */ +#define AWB_CTRL13 (0x75U) /* AWB Control 13 */ +#define AWB_CTRL14 (0x76U) /* AWB Control 14 */ +#define AWB_CTRL15 (0x77U) /* AWB Control 15 */ +#define AWB_CTRL16 (0x78U) /* AWB Control 16 */ +#define AWB_CTRL17 (0x79U) /* AWB Control 17 */ +#define AWB_CTRL18 (0x7AU) /* AWB Control 18 */ +#define AWB_CTRL19 (0x7BU) /* AWB Control 19 */ +#define AWB_CTRL20 (0x7CU) /* AWB Control 20 */ +#define AWB_CTRL21 (0x7DU) /* AWB Control 21 */ +#define GAM1 (0x7EU) /* Gamma Curve 1st Segment Input End Point (0x04U) Output Value */ +#define GAM2 (0x7FU) /* Gamma Curve 2nd Segment Input End Point (0x08U) Output Value */ +#define GAM3 (0x80U) /* Gamma Curve 3rd Segment Input End Point (0x10U) Output Value */ +#define GAM4 (0x81U) /* Gamma Curve 4th Segment Input End Point (0x20U) Output Value */ +#define GAM5 (0x82U) /* Gamma Curve 5th Segment Input End Point (0x28U) Output Value */ +#define GAM6 (0x83U) /* Gamma Curve 6th Segment Input End Point (0x30U) Output Value */ +#define GAM7 (0x84U) /* Gamma Curve 7th Segment Input End Point (0x38U) Output Value */ +#define GAM8 (0x85U) /* Gamma Curve 8th Segment Input End Point (0x40U) Output Value */ +#define GAM9 (0x86U) /* Gamma Curve 9th Segment Input End Point (0x48U) Output Value */ +#define GAM10 (0x87U) /* Gamma Curve 10th Segment Input End Point (0x50U) Output Value */ +#define GAM11 (0x88U) /* Gamma Curve 11th Segment Input End Point (0x60U) Output Value */ +#define GAM12 (0x89U) /* Gamma Curve 12th Segment Input End Point (0x70U) Output Value */ +#define GAM13 (0x8AU) /* Gamma Curve 13th Segment Input End Point (0x90U) Output Value */ +#define GAM14 (0x8BU) /* Gamma Curve 14th Segment Input End Point (0xB0U) Output Value */ +#define GAM15 (0x8CU) /* Gamma Curve 15th Segment Input End Point (0xD0U) Output Value */ +#define SLOP (0x8DU) /* Gamma Curve Highest Segment Slope */ +#define DNSTH (0x8EU) /* De-noise Threshold */ +#define EDGE0 (0x8FU) /* Edge Enhancement Strength Control */ +#define EDGE1 (0x90U) /* Edge Enhancement Threshold Control */ +#define DNSOFF (0x91U) /* Auto De-noise Threshold Control */ +#define EDGE2 (0x92U) /* Edge Enhancement Strength Upper Limit */ +#define EDGE3 (0x93U) /* Edge Enhancement Strength Upper Limit */ +#define MTX1 (0x94U) /* Matrix Coefficient 1 */ +#define MTX2 (0x95U) /* Matrix Coefficient 2 */ +#define MTX3 (0x96U) /* Matrix Coefficient 3 */ +#define MTX4 (0x97U) /* Matrix Coefficient 4 */ +#define MTX5 (0x98U) /* Matrix Coefficient 5 */ +#define MTX6 (0x99U) /* Matrix Coefficient 6 */ + +#define MTX_CTRL (0x9AU) /* Matrix Control */ +#define MTX_CTRL_DBL_EN (0x80U) /* Matrix double ON/OFF selection */ + +#define BRIGHTNESS (0x9BU) /* Brightness Control */ +#define CONTRAST (0x9CU) /* Contrast Gain */ +#define UVADJ0 (0x9EU) /* Auto UV Adjust Control 0 */ +#define UVADJ1 (0x9FU) /* Auto UV Adjust Control 1 */ +#define SCAL0 (0xA0U) /* DCW Ratio Control */ +#define SCAL1 (0xA1U) /* Horizontal Zoom Out Control */ +#define SCAL2 (0xA2U) /* Vertical Zoom Out Control */ +#define FIFODLYM (0xA3U) /* FIFO Manual Mode Delay Control */ +#define FIFODLYA (0xA4U) /* FIFO Auto Mode Delay Control */ + +#define SDE (0xA6U) /* Special Digital Effect Control */ +#define SDE_NEGATIVE_EN (0x40U) /* Negative image enable */ +#define SDE_GRAYSCALE_EN (0x20U) /* Gray scale image enable */ +#define SDE_V_FIXED_EN (0x10U) /* V fixed value enable */ +#define SDE_U_FIXED_EN (0x08U) /* U fixed value enable */ +#define SDE_CONT_BRIGHT_EN (0x04U) /* Contrast/Brightness enable */ +#define SDE_SATURATION_EN (0x02U) /* Saturation enable */ +#define SDE_HUE_EN (0x01U) /* Hue enable */ + +#define USAT (0xA7U) /* U Component Saturation Gain */ +#define VSAT (0xA8U) /* V Component Saturation Gain */ +#define HUECOS (0xA9U) /* Cosine value × (0x80U) */ +#define HUESIN (0xAAU) /* Sine value × (0x80U) */ +#define SIGN_BIT (0xABU) /* Sign Bit for Hue and Brightness */ + +#define DSPAUTO (0xACU) /* DSP Auto Function ON/OFF Control */ +#define DSPAUTO_AWB_EN (0x80U) /* AWB auto threshold control */ +#define DSPAUTO_DENOISE_EN (0x40U) /* De-noise auto threshold control */ +#define DSPAUTO_EDGE_EN (0x20U) /* Sharpness (edge enhancement) auto strength control */ +#define DSPAUTO_UV_EN (0x10U) /* UV adjust auto slope control */ +#define DSPAUTO_SCAL0_EN (0x08U) /* Auto scaling factor control (register SCAL0 ((0xA0U))) */ +#define DSPAUTO_SCAL1_EN (0x04U) /* Auto scaling factor control (registers SCAL1 ((0xA1U) and SCAL2 ((0xA2U)))*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ov7725 initialization routine + */ +hpm_stat_t ov7725_init(camera_context_t *context, camera_config_t *ov_config); + +/* + * ov7725 read register + */ +hpm_stat_t ov7725_read_register(camera_context_t *context, uint8_t reg, uint8_t *buf); + +/* + * ov7725 write register + */ +hpm_stat_t ov7725_write_register(camera_context_t *context, uint8_t reg, uint8_t val); + +/* + * ov7725 reset + */ +hpm_stat_t ov7725_software_reset(camera_context_t *context); + +/* + * ov7725 check chip id + */ +hpm_stat_t ov7725_check_chip_id(camera_context_t *context); + +/** + * @brief ov7725 power up + * + * @param [in] context camera_context_t + */ +void ov7725_power_up(camera_context_t *context); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_OV7725_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c new file mode 100644 index 0000000000..1899b3f5ec --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c @@ -0,0 +1,713 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_sgtl5000.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config) +{ + assert(context != NULL); + assert(config != NULL); + + if (sgtl_write_reg(context, CHIP_ANA_POWER, 0x6AFF) != status_success) + { + return status_fail; + } + + /* Set the data route */ + if (sgtl_set_data_route(context, config->route) != status_success) + { + return status_fail; + } + + /* Set sgtl5000 to master or slave */ + sgtl_set_master_mode(context, config->master); + + /* Input Volume Control + Configure ADC left and right analog volume to desired default. + Example shows volume of 0dB. */ + if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0000U) != status_success) + { + return status_fail; + } + + /* Volume and Mute Control + Configure HP_OUT left and right volume to minimum, unmute. + HP_OUT and ramp the volume up to desired volume.*/ + if (sgtl_write_reg(context, CHIP_ANA_HP_CTRL, 0x1818U) != status_success) + { + return status_fail; + } + + if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFEFU, 0x0000U) != status_success) + { + return status_fail; + } + + /* LINEOUT and DAC volume control */ + if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFEFFU, 0x0000U) != status_success) + { + return status_fail; + } + + /* Configure DAC left and right digital volume */ + if (sgtl_write_reg(context, CHIP_DAC_VOL, 0x5C5CU) != status_success) + { + return status_fail; + } + + /* Configure ADC volume, reduce 6db. */ + if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0100U) != status_success) + { + return status_fail; + } + + /* Unmute DAC */ + if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFFBU, 0x0000U) != status_success) + { + return status_fail; + } + + if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFF7U, 0x0000U) != status_success) + { + return status_fail; + } + + /* Unmute ADC */ + if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFFEU, 0x0000U) != status_success) + { + return status_fail; + } + + /* Set the audio format */ + if (sgtl_set_protocol(context, config->bus) != status_success) + { + return status_fail; + } + + if (sgtl_config_data_format(context, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width) != + status_success) + { + return status_fail; + } + + /* sclk valid edge */ + if (config->format.sclk_edge == sgtl_sclk_valid_edge_rising) + { + if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE) != + status_success) + { + return status_fail; + } + } + else + { + if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE) != + status_success) + { + return status_fail; + } + } + + return status_success; +} + +hpm_stat_t sgtl_deinit(sgtl_context_t *context) +{ + hpm_stat_t stat = status_success; + + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_dap)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_lineout)); + + return stat; +} + +void sgtl_set_master_mode(sgtl_context_t *context, bool master) +{ + if (master == true) + { + (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_MASTER); + } + else + { + (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_SLAVE); + } +} + +hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module) +{ + hpm_stat_t stat = status_success; + switch (module) + { + case sgtl_module_adc: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_ADC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_ADC_POWERUP_SHIFT))); + break; + case sgtl_module_dac: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAC_POWERUP_SHIFT))); + break; + case sgtl_module_dap: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAP_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, + ((uint16_t)1U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); + break; + case sgtl_module_i2sin: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_I2S_IN_ENABLE_SHIFT))); + break; + case sgtl_module_i2sout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, + ((uint16_t)1U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); + break; + case sgtl_module_hp: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); + break; + case sgtl_module_lineout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, + ((uint16_t)1U << SGTL5000_LINEOUT_POWERUP_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module) +{ + hpm_stat_t stat = status_success; + switch (module) + { + case sgtl_module_adc: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_ADC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_ADC_POWERUP_SHIFT))); + break; + case sgtl_module_dac: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAC_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAC_POWERUP_SHIFT))); + break; + case sgtl_module_dap: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAP_ENABLE_SHIFT))); + HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, + ((uint16_t)0U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); + break; + case sgtl_module_i2sin: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_I2S_IN_ENABLE_SHIFT))); + break; + case sgtl_module_i2sout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, + ((uint16_t)0U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); + break; + case sgtl_module_hp: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); + break; + case sgtl_module_lineout: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, + ((uint16_t)0U << SGTL5000_LINEOUT_POWERUP_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route) +{ + hpm_stat_t stat = status_success; + switch (route) + { + case sgtl_route_bypass: + /* Bypass means from line-in to HP*/ + HPM_CHECK_RET(sgtl_write_reg(context, CHIP_DIG_POWER, 0x0000)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_LINEIN)); + break; + case sgtl_route_playback: + /* Data route I2S_IN-> DAC-> HP */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + break; + case sgtl_route_playback_record: + /* I2S IN->DAC->HP LINE_IN->ADC->I2S_OUT */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); + break; + case sgtl_route_playback_with_dap: + /* I2S_IN->DAP->DAC->HP */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + break; + case sgtl_route_playback_with_dap_record: + /* I2S_IN->DAP->DAC->HP, LINE_IN->ADC->I2S_OUT */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); + HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, 0x0001)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); + break; + case sgtl_route_record: + /* LINE_IN->ADC->I2S_OUT */ + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); + HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol) +{ + hpm_stat_t stat = status_success; + switch (protocol) + { + case sgtl_bus_i2s: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); + break; + case sgtl_bus_left_justified: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); + break; + case sgtl_bus_right_justified: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_RJ)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); + break; + case sgtl_bus_pcma: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); + break; + case sgtl_bus_pcmb: + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); + HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32_t volume) +{ + uint16_t vol = 0; + hpm_stat_t stat = status_success; + switch (module) + { + case sgtl_module_adc: + if (volume > SGTL5000_ADC_MAX_VOLUME_VALUE) + { + return status_invalid_argument; + } + + vol = (uint16_t)(volume | (volume << 4U)); + stat = sgtl_modify_reg(context, CHIP_ANA_ADC_CTRL, + SGTL5000_ADC_VOL_LEFT_CLR_MASK & SGTL5000_ADC_VOL_RIGHT_CLR_MASK, vol); + break; + case sgtl_module_dac: + if ((volume > SGTL5000_DAC_MAX_VOLUME_VALUE) || (volume < SGTL5000_DAC_MIN_VOLUME_VALUE)) + { + return status_invalid_argument; + } + vol = (uint16_t)(volume | (volume << 8U)); + stat = sgtl_write_reg(context, CHIP_DAC_VOL, vol); + break; + case sgtl_module_hp: + if (volume > SGTL5000_HEADPHONE_MAX_VOLUME_VALUE) + { + return status_invalid_argument; + } + vol = (uint16_t)(volume | (volume << 8U)); + stat = sgtl_write_reg(context, CHIP_ANA_HP_CTRL, vol); + break; + case sgtl_module_lineout: + if (volume > SGTL5000_LINE_OUT_MAX_VOLUME_VALUE) + { + return status_invalid_argument; + } + vol = (uint16_t)(volume | (volume << 8U)); + stat = sgtl_write_reg(context, CHIP_LINE_OUT_VOL, vol); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module) +{ + uint16_t vol = 0; + hpm_stat_t stat = status_success; + + switch (module) + { + case sgtl_module_adc: + stat = sgtl_read_reg(context, CHIP_ANA_ADC_CTRL, &vol); + vol = (vol & (uint16_t)SGTL5000_ADC_VOL_LEFT_GET_MASK) >> SGTL5000_ADC_VOL_LEFT_SHIFT; + break; + case sgtl_module_dac: + stat = sgtl_read_reg(context, CHIP_DAC_VOL, &vol); + vol = (vol & (uint16_t)SGTL5000_DAC_VOL_LEFT_GET_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; + break; + case sgtl_module_hp: + stat = sgtl_read_reg(context, CHIP_ANA_HP_CTRL, &vol); + vol = (vol & (uint16_t)SGTL5000_HP_VOL_LEFT_GET_MASK) >> SGTL5000_HP_VOL_LEFT_SHIFT; + break; + case sgtl_module_lineout: + stat = sgtl_read_reg(context, CHIP_LINE_OUT_VOL, &vol); + vol = (vol & (uint16_t)SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK) >> SGTL5000_LINE_OUT_VOL_LEFT_SHIFT; + break; + default: + vol = 0; + break; + } + return stat == status_success ? vol : 0U; +} + +hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute) +{ + hpm_stat_t stat = status_success; + switch (module) + { + case sgtl_module_adc: + stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_ADC_CLR_MASK, mute ? 1U : 0U); + break; + case sgtl_module_dac: + if (mute) + { + stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, + SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x000C); + } + else + { + stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, + SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x0000); + } + break; + case sgtl_module_hp: + stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_HP_CLR_MASK, + ((uint16_t)mute << SGTL5000_MUTE_HP_SHIFT)); + break; + case sgtl_module_lineout: + stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_LO_CLR_MASK, + ((uint16_t)mute << SGTL5000_MUTE_LO_SHIFT)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits) +{ + uint16_t val = 0; + uint16_t regVal = 0; + uint16_t mul_clk = 0U; + uint32_t sysFs = 0U; + hpm_stat_t stat = status_success; + + /* Over sample rate can only up to 512, the least to 8k */ + if ((mclk / (MIN(sample_rate * 6U, 96000U)) > 512U) || (mclk / sample_rate < 256U)) + { + return status_invalid_argument; + } + + /* Configure the sample rate */ + switch (sample_rate) + { + case 8000: + if (mclk > 32000U * 512U) + { + val = 0x0038; + sysFs = 48000; + } + else + { + val = 0x0020; + sysFs = 32000; + } + break; + case 11025: + val = 0x0024; + sysFs = 44100; + break; + case 12000: + val = 0x0028; + sysFs = 48000; + break; + case 16000: + if (mclk > 32000U * 512U) + { + val = 0x003C; + sysFs = 96000; + } + else + { + val = 0x0010; + sysFs = 32000; + } + break; + case 22050: + val = 0x0014; + sysFs = 44100; + break; + case 24000: + if (mclk > 48000U * 512U) + { + val = 0x002C; + sysFs = 96000; + } + else + { + val = 0x0018; + sysFs = 48000; + } + break; + case 32000: + val = 0x0000; + sysFs = 32000; + break; + case 44100: + val = 0x0004; + sysFs = 44100; + break; + case 48000: + if (mclk > 48000U * 512U) + { + val = 0x001C; + sysFs = 96000; + } + else + { + val = 0x0008; + sysFs = 48000; + } + break; + case 96000: + val = 0x000C; + sysFs = 96000; + break; + default: + stat = status_invalid_argument; + break; + } + + if (stat != status_success) + { + return stat; + } + + if (sgtl_read_reg(context, CHIP_I2S_CTRL, ®Val) != status_success) + { + return status_fail; + } + + /* While as slave, Fs is input */ + if ((regVal & SGTL5000_I2S_MS_GET_MASK) == 0U) + { + sysFs = sample_rate; + } + mul_clk = (uint16_t)(mclk / sysFs); + /* Configure the mul_clk. Sgtl-5000 only support 256, 384 and 512 oversample rate */ + if ((mul_clk / 128U - 2U) > 2U) + { + return status_invalid_argument; + } + else + { + val |= (mul_clk / 128U - 2U); + } + + if (sgtl_write_reg(context, CHIP_CLK_CTRL, val) != status_success) + { + return status_fail; + } + + /* Data bits configure,sgtl supports 16bit, 20bit 24bit, 32bit */ + if (sgtl_modify_reg(context, CHIP_I2S_CTRL, 0xFEFF, SGTL5000_I2S_SCLKFREQ_64FS) != status_success) + { + return status_fail; + } + + switch (bits) + { + case 16: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_16); + break; + case 20: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_20); + break; + case 24: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_24); + break; + case 32: + stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_32); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t sgtl_set_pay(sgtl_context_t *context, uint32_t playSource) +{ + uint16_t regValue = 0U, regBitMask = 0x40U; + + /* headphone source form PGA */ + if (playSource == (uint32_t)sgtl_play_source_linein) + { + regValue = 0x40U; + } + /* headphone source from DAC */ + else + { + regValue = 0U; + } + + return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); +} + +hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource) +{ + uint16_t regValue = 0U, regBitMask = 0x4U; + + /* ADC source form LINEIN */ + if (recordSource == (uint32_t)sgtl_record_source_linein) + { + regValue = 0x4U; + } + /* ADC source from MIC */ + else + { + regValue = 0U; + } + + return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); +} + +hpm_stat_t sgtl_write_reg(sgtl_context_t *context, uint16_t reg, uint16_t val) +{ + uint8_t r[2]; + uint8_t d[2]; + r[0] = reg >> 8; + r[1] = reg & 0xFF; + d[0] = (uint8_t) (val>>8); + d[1] = (uint8_t) (val & 0xFF); + + return i2c_master_address_write(context->ptr, context->slave_address, r, 2U, d, 2U); +} + +hpm_stat_t sgtl_read_reg(sgtl_context_t *context, uint16_t reg, uint16_t *val) +{ + hpm_stat_t stat = status_success; + uint8_t r[2]; + uint8_t d[2]; + r[0] = reg >> 8; + r[1] = reg & 0xFF; + + stat = i2c_master_address_read(context->ptr, context->slave_address, r, 2U, d, 2U); + + *val = (uint16_t)((d[0] << 8) | d[1]); + + return stat; +} + +hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_mask, uint16_t val) +{ + hpm_stat_t retval = 0; + uint16_t reg_val; + + /* Read the register value out */ + retval = sgtl_read_reg(context, reg, ®_val); + if (retval != status_success) + { + return status_fail; + } + + /* Modify the value */ + reg_val &= clr_mask; + reg_val |= val; + + /* Write the data to register */ + retval = sgtl_write_reg(context, reg, reg_val); + if (retval != status_success) + { + return status_fail; + } + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h new file mode 100644 index 0000000000..0d222efbe3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h @@ -0,0 +1,1032 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_SGTL5000_H_ +#define _HPM_SGTL5000_H_ + +#include "hpm_i2c_drv.h" + +/*! + * @addtogroup sgtl5000 + * @ingroup codec + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define the register address of sgtl5000. */ +#define CHIP_ID 0x0000U +#define CHIP_DIG_POWER 0x0002U +#define CHIP_CLK_CTRL 0x0004U +#define CHIP_I2S_CTRL 0x0006U +#define CHIP_SSS_CTRL 0x000AU +#define CHIP_ADCDAC_CTRL 0x000EU +#define CHIP_DAC_VOL 0x0010U +#define CHIP_PAD_STRENGTH 0x0014U +#define CHIP_ANA_ADC_CTRL 0x0020U +#define CHIP_ANA_HP_CTRL 0x0022U +#define CHIP_ANA_CTRL 0x0024U +#define CHIP_LINREG_CTRL 0x0026U +#define CHIP_REF_CTRL 0x0028U +#define CHIP_MIC_CTRL 0x002AU +#define CHIP_LINE_OUT_CTRL 0x002CU +#define CHIP_LINE_OUT_VOL 0x002EU +#define CHIP_ANA_POWER 0x0030U +#define CHIP_PLL_CTRL 0x0032U +#define CHIP_CLK_TOP_CTRL 0x0034U +#define CHIP_ANA_STATUS 0x0036U +#define CHIP_ANA_TEST2 0x003AU +#define CHIP_SHORT_CTRL 0x003CU +#define SGTL5000_DAP_CONTROL 0x0100U +#define SGTL5000_DAP_PEQ 0x0102U +#define SGTL5000_DAP_BASS_ENHANCE 0x0104U +#define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106U +#define SGTL5000_DAP_AUDIO_EQ 0x0108U +#define SGTL5000_DAP_SGTL_SURROUND 0x010AU +#define SGTL5000_DAP_FILTER_COEF_ACCESS 0x010CU +#define SGTL5000_DAP_COEF_WR_B0_MSB 0x010EU +#define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110U +#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0 0x0116U +#define SGTL5000_DAP_AUDIO_EQ_BAND1 0x0118U +#define SGTL5000_DAP_AUDIO_EQ_BAND2 0x011AU +#define SGTL5000_DAP_AUDIO_EQ_BAND3 0x011CU +#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4 0x011EU +#define SGTL5000_DAP_MAIN_CHAN 0x0120U +#define SGTL5000_DAP_MIX_CHAN 0x0122U +#define SGTL5000_DAP_AVC_CTRL 0x0124U +#define SGTL5000_DAP_AVC_THRESHOLD 0x0126U +#define SGTL5000_DAP_AVC_ATTACK 0x0128U +#define SGTL5000_DAP_AVC_DECAY 0x012AU +#define SGTL5000_DAP_COEF_WR_B1_MSB 0x012CU +#define SGTL5000_DAP_COEF_WR_B1_LSB 0x012EU +#define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130U +#define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132U +#define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134U +#define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136U +#define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138U +#define SGTL5000_DAP_COEF_WR_A2_LSB 0x013AU + +/* + * Field Definitions. + */ + +/* + * SGTL5000_CHIP_DIG_POWER + */ +#define SGTL5000_ADC_ENABLE_CLR_MASK 0xFFBFU +#define SGTL5000_ADC_ENABLE_GET_MASK 0x0040U +#define SGTL5000_ADC_ENABLE_SHIFT 0x6U +#define SGTL5000_DAC_ENABLE_CLR_MASK 0xFFDFU +#define SGTL5000_DAC_ENABLE_GET_MASK 0x0020U +#define SGTL5000_DAC_ENABLE_SHIFT 0x5U +#define SGTL5000_DAP_ENABLE_CLR_MASK 0xFFEFU +#define SGTL5000_DAP_ENABLE_GET_MASK 0x0010U +#define SGTL5000_DAP_ENABLE_SHIFT 0x4U +#define SGTL5000_I2S_OUT_ENABLE_CLR_MASK 0xFFFDU +#define SGTL5000_I2S_OUT_ENABLE_GET_MASK 0x0002U +#define SGTL5000_I2S_OUT_ENABLE_SHIFT 0x1U +#define SGTL5000_I2S_IN_ENABLE_CLR_MASK 0xFFFEU +#define SGTL5000_I2S_IN_ENABLE_GET_MASK 0x0001U +#define SGTL5000_I2S_IN_ENABLE_SHIFT 0x0U + +/* + * SGTL5000_CHIP_CLK_CTRL + */ +#define SGTL5000_RATE_MODE_CLR_MASK 0xFFCFU +#define SGTL5000_RATE_MODE_GET_MASK 0x0030U +#define SGTL5000_RATE_MODE_SHIFT 0x4U +#define SGTL5000_RATE_MODE_DIV_1 0x0000U +#define SGTL5000_RATE_MODE_DIV_2 0x0010U +#define SGTL5000_RATE_MODE_DIV_4 0x0020U +#define SGTL5000_RATE_MODE_DIV_6 0x0030U +#define SGTL5000_SYS_FS_CLR_MASK 0xFFF3U +#define SGTL5000_SYS_FS_GET_MASK 0x000CU +#define SGTL5000_SYS_FS_SHIFT 0x2U +#define SGTL5000_SYS_FS_32k 0x0000U +#define SGTL5000_SYS_FS_44_1k 0x0004U +#define SGTL5000_SYS_FS_48k 0x0008U +#define SGTL5000_SYS_FS_96k 0x000CU +#define SGTL5000_MCLK_FREQ_CLR_MASK 0xFFFCU +#define SGTL5000_MCLK_FREQ_GET_MASK 0x0003U +#define SGTL5000_MCLK_FREQ_SHIFT 0x0U +#define SGTL5000_MCLK_FREQ_256FS 0x0000U +#define SGTL5000_MCLK_FREQ_384FS 0x0001U +#define SGTL5000_MCLK_FREQ_512FS 0x0002U +#define SGTL5000_MCLK_FREQ_PLL 0x0003U + +/* + * SGTL5000_CHIP_I2S_CTRL + */ +#define SGTL5000_I2S_SLCKFREQ_CLR_MASK 0xFEFFU +#define SGTL5000_I2S_SCLKFREQ_GET_MASK 0x0100U +#define SGTL5000_I2S_SCLKFREQ_SHIFT 0x8U +#define SGTL5000_I2S_SCLKFREQ_64FS 0x0000U +#define SGTL5000_I2S_SCLKFREQ_32FS 0x0100U /* Not for RJ mode */ +#define SGTL5000_I2S_MS_CLR_MASK 0xFF7FU +#define SGTL5000_I2S_MS_GET_MASK 0x0080U +#define SGTL5000_I2S_MS_SHIFT 0x7U +#define SGTL5000_I2S_MASTER 0x0080U +#define SGTL5000_I2S_SLAVE 0x0000U +#define SGTL5000_I2S_SCLK_INV_CLR_MASK 0xFFBFU +#define SGTL5000_I2S_SCLK_INV_GET_MASK 0x0040U +#define SGTL5000_I2S_SCLK_INV_SHIFT 0x6U +#define SGTL5000_I2S_VAILD_FALLING_EDGE 0x0040U +#define SGTL5000_I2S_VAILD_RISING_EDGE 0x0000U +#define SGTL5000_I2S_DLEN_CLR_MASK 0xFFCFU +#define SGTL5000_I2S_DLEN_GET_MASK 0x0030U +#define SGTL5000_I2S_DLEN_SHIFT 0x4U +#define SGTL5000_I2S_DLEN_32 0x0000U +#define SGTL5000_I2S_DLEN_24 0x0010U +#define SGTL5000_I2S_DLEN_20 0x0020U +#define SGTL5000_I2S_DLEN_16 0x0030U +#define SGTL5000_I2S_MODE_CLR_MASK 0xFFF3U +#define SGTL5000_I2S_MODE_GET_MASK 0x000CU +#define SGTL5000_I2S_MODE_SHIFT 0x2U +#define SGTL5000_I2S_MODE_I2S_LJ 0x0000U +#define SGTL5000_I2S_MODE_RJ 0x0004U +#define SGTL5000_I2S_MODE_PCM 0x0008U +#define SGTL5000_I2S_LRALIGN_CLR_MASK 0xFFFDU +#define SGTL5000_I2S_LRALIGN_GET_MASK 0x0002U +#define SGTL5000_I2S_LRALIGN_SHIFT 0x1U +#define SGTL5000_I2S_ONE_BIT_DELAY 0x0000U +#define SGTL5000_I2S_NO_DELAY 0x0002U +#define SGTL5000_I2S_LRPOL_CLR_MASK 0xFFFEU +#define SGTL5000_I2S_LRPOL_GET_MASK 0x0001U +#define SGTL5000_I2S_LRPOL_SHIFT 0x0U +#define SGTL5000_I2S_LEFT_FIRST 0x0000U +#define SGTL5000_I2S_RIGHT_FIRST 0x0001U + +/* + * SGTL5000_CHIP_SSS_CTRL + */ +#define SGTL5000_DAP_MIX_LRSWAP_CLR_MASK 0xBFFFU +#define SGTL5000_DAP_MIX_LRSWAP_GET_MASK 0x4000U +#define SGTL5000_DAP_MIX_LRSWAP_SHIFT 0xEU +#define SGTL5000_DAP_LRSWAP_CLR_MASK 0xDFFFU +#define SGTL5000_DAP_LRSWAP_GET_MASK 0x2000U +#define SGTL5000_DAP_LRSWAP_SHIFT 0xDU +#define SGTL5000_DAC_LRSWAP_CLR_MASK 0xEFFFU +#define SGTL5000_DAC_LRSWAP_GET_MASK 0x1000U +#define SGTL5000_DAC_LRSWAP_SHIFT 0xCU +#define SGTL5000_I2S_LRSWAP_CLR_MASK 0xFBFFU +#define SGTL5000_I2S_LRSWAP_GET_MASK 0x0400U +#define SGTL5000_I2S_LRSWAP_SHIFT 0xAU +#define SGTL5000_DAP_MIX_SEL_CLR_MASK 0xFCFFU +#define SGTL5000_DAP_MIX_SEL_GET_MASK 0x0300U +#define SGTL5000_DAP_MIX_SEL_SHIFT 0x8U +#define SGTL5000_DAP_MIX_SEL_ADC 0x0000U +#define SGTL5000_DAP_MIX_SEL_I2S_IN 0x0100U +#define SGTL5000_DAP_SEL_CLR_MASK 0xFF3FU +#define SGTL5000_DAP_SEL_GET_MASK 0x00C0U +#define SGTL5000_DAP_SEL_SHIFT 0x6U +#define SGTL5000_DAP_SEL_ADC 0x0000U +#define SGTL5000_DAP_SEL_I2S_IN 0x0040U +#define SGTL5000_DAC_SEL_CLR_MASK 0xFFCFU +#define SGTL5000_DAC_SEL_GET_MASK 0x0030U +#define SGTL5000_DAC_SEL_SHIFT 0x4U +#define SGTL5000_DAC_SEL_ADC 0x0000U +#define SGTL5000_DAC_SEL_I2S_IN 0x0010U +#define SGTL5000_DAC_SEL_DAP 0x0030U +#define SGTL5000_I2S_OUT_SEL_CLR_MASK 0xFFFCU +#define SGTL5000_I2S_OUT_SEL_GET_MASK 0x0003U +#define SGTL5000_I2S_OUT_SEL_SHIFT 0x0U +#define SGTL5000_I2S_OUT_SEL_ADC 0x0000U +#define SGTL5000_I2S_OUT_SEL_I2S_IN 0x0001U +#define SGTL5000_I2S_OUT_SEL_DAP 0x0003U + +/* + * SGTL5000_CHIP_ADCDAC_CTRL + */ +#define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000U +#define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000U +#define SGTL5000_DAC_VOL_RAMP_EN_CLR_MASK 0xFDFFU +#define SGTL5000_DAC_VOL_RAMP_EN_GET_MASK 0x0200U +#define SGTL5000_DAC_VOL_RAMP_EN_SHIFT 0x9U +#define SGTL5000_DAC_VOL_RAMP_EXPO_CLR_MASK 0xFEFFU +#define SGTL5000_DAC_VOL_RAMP_EXPO_GET_MASK 0x0100U +#define SGTL5000_DAC_VOL_RAMP_EXPO_SHIFT 0x8U +#define SGTL5000_DAC_MUTE_RIGHT_CLR_MASK 0xFFF7U +#define SGTL5000_DAC_MUTE_RIGHT_GET_MASK 0x0008U +#define SGTL5000_DAC_MUTE_RIGHT_SHIFT 0x3U +#define SGTL5000_DAC_MUTE_LEFT_CLR_MASK 0xFFFBU +#define SGTL5000_DAC_MUTE_LEFT_GET_MASK 0x0004U +#define SGTL5000_DAC_MUTE_LEFT_SHIFT 0x2U +#define SGTL5000_ADC_HPF_FREEZE_CLR_MASK 0xFFFDU +#define SGTL5000_ADC_HPF_FREEZE_GET_MASK 0x0002U +#define SGTL5000_ADC_HPF_FREEZE_SHIFT 0x1U +#define SGTL5000_ADC_HPF_BYPASS_CLR_MASK 0xFFFEU +#define SGTL5000_ADC_HPF_BYPASS_GET_MASK 0x0001U +#define SGTL5000_ADC_HPF_BYPASS_SHIFT 0x0U + +/* + * SGTL5000_CHIP_DAC_VOL + */ +#define SGTL5000_DAC_VOL_RIGHT_CLR_MASK 0x00FFU +#define SGTL5000_DAC_VOL_RIGHT_GET_MASK 0xFF00U +#define SGTL5000_DAC_VOL_RIGHT_SHIFT 0x8U +#define SGTL5000_DAC_VOL_LEFT_CLR_MASK 0xFF00U +#define SGTL5000_DAC_VOL_LEFT_GET_MASK 0x00FFU +#define SGTL5000_DAC_VOL_LEFT_SHIFT 0x0U + +/* + * SGTL5000_CHIP_PAD_STRENGTH + */ +#define SGTL5000_PAD_I2S_LRCLK_CLR_MASK 0xFCFFU +#define SGTL5000_PAD_I2S_LRCLK_GET_MASK 0x0300U +#define SGTL5000_PAD_I2S_LRCLK_SHIFT 0x8U +#define SGTL5000_PAD_I2S_SCLK_CLR_MASK 0xFF3FU +#define SGTL5000_PAD_I2S_SCLK_GET_MASK 0x00C0U +#define SGTL5000_PAD_I2S_SCLK_SHIFT 0x6U +#define SGTL5000_PAD_I2S_DOUT_CLR_MASK 0xFFCFU +#define SGTL5000_PAD_I2S_DOUT_GET_MASK 0x0030U +#define SGTL5000_PAD_I2S_DOUT_SHIFT 0x4U +#define SGTL5000_PAD_I2C_SDA_CLR_MASK 0xFFF3U +#define SGTL5000_PAD_I2C_SDA_GET_MASK 0x000CU +#define SGTL5000_PAD_I2C_SDA_SHIFT 0x2U +#define SGTL5000_PAD_I2C_SCL_CLR_MASK 0xFFFCU +#define SGTL5000_PAD_I2C_SCL_GET_MASK 0x0003U +#define SGTL5000_PAD_I2C_SCL_SHIFT 0x0U + +/* + * SGTL5000_CHIP_ANA_ADC_CTRL + */ +#define SGTL5000_ADC_VOL_M6DB_CLR_MASK 0xFEFFU +#define SGTL5000_ADC_VOL_M6DB_GET_MASK 0x0100U +#define SGTL5000_ADC_VOL_M6DB_SHIFT 0x8U +#define SGTL5000_ADC_VOL_RIGHT_CLR_MASK 0xFF0FU +#define SGTL5000_ADC_VOL_RIGHT_GET_MASK 0x00F0U +#define SGTL5000_ADC_VOL_RIGHT_SHIFT 0x4U +#define SGTL5000_ADC_VOL_LEFT_CLR_MASK 0xFFF0U +#define SGTL5000_ADC_VOL_LEFT_GET_MASK 0x000FU +#define SGTL5000_ADC_VOL_LEFT_SHIFT 0x0U + +/* + * SGTL5000_CHIP_ANA_HP_CTRL + */ +#define SGTL5000_HP_VOL_RIGHT_CLR_MASK 0x80FFU +#define SGTL5000_HP_VOL_RIGHT_GET_MASK 0x7F00U +#define SGTL5000_HP_VOL_RIGHT_SHIFT 0x8U +#define SGTL5000_HP_VOL_LEFT_CLR_MASK 0xFF80U +#define SGTL5000_HP_VOL_LEFT_GET_MASK 0x007FU +#define SGTL5000_HP_VOL_LEFT_SHIFT 0x0U + +/* + * SGTL5000_CHIP_ANA_CTRL + */ +#define SGTL5000_MUTE_LO_GET_MASK 0x0100U +#define SGTL5000_MUTE_LO_CLR_MASK 0xFEFFU +#define SGTL5000_MUTE_LO_SHIFT 0x8U +#define SGTL5000_SEL_HP_GET_MASK 0x0040U +#define SGTL5000_SEL_HP_CLR_MASK 0xFFBFU +#define SGTL5000_SEL_HP_SHIFT 0x6U +#define SGTL5000_SEL_HP_DAC 0x0000U +#define SGTL5000_SEL_HP_LINEIN 0x0040U +#define SGTL5000_EN_ZCD_HP_GET_MASK 0x0020U +#define SGTL5000_EN_ZCD_HP_CLR_MASK 0xFFDFU +#define SGTL5000_EN_ZCD_HP_SHIFT 0x5U +#define SGTL5000_MUTE_HP_GET_MASK 0x0010U +#define SGTL5000_MUTE_HP_CLR_MASK 0xFFEFU +#define SGTL5000_MUTE_HP_SHIFT 0x4U +#define SGTL5000_SEL_ADC_GET_MASK 0x0004U +#define SGTL5000_SEL_ADC_CLR_MASK 0xFFFBU +#define SGTL5000_SEL_ADC_SHIFT 0x2U +#define SGTL5000_SEL_ADC_MIC 0x0000U +#define SGTL5000_SEL_ADC_LINEIN 0x0004U +#define SGTL5000_EN_ZCD_ADC_GET_MASK 0x0002U +#define SGTL5000_EN_ZCD_ADC_CLR_MASK 0xFFFDU +#define SGTL5000_EN_ZCD_ADC_SHIFT 0x1U +#define SGTL5000_MUTE_ADC_GET_MASK 0x0001U +#define SGTL5000_MUTE_ADC_CLR_MASK 0xFFFEU +#define SGTL5000_MUTE_ADC_SHIFT 0x0U + +/* + * SGTL5000_CHIP_LINREG_CTRL + */ +#define SGTL5000_VDDC_MAN_ASSN_CLR_MASK 0xFFBFU +#define SGTL5000_VDDC_MAN_ASSN_GET_MASK 0x0040U +#define SGTL5000_VDDC_MAN_ASSN_SHIFT 0x6U +#define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0000U +#define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x0040U +#define SGTL5000_VDDC_ASSN_OVRD 0x0020U +#define SGTL5000_LINREG_VDDD_CLR_MASK 0xFFF0U +#define SGTL5000_LINREG_VDDD_GET_MASK 0x000FU +#define SGTL5000_LINREG_VDDD_SHIFT 0x0U + +/* + * SGTL5000_CHIP_REF_CTRL + */ +#define SGTL5000_ANA_GND_MASK 0x01f0U +#define SGTL5000_ANA_GND_SHIFT 0x4U +#define SGTL5000_ANA_GND_WIDTH 0x5U +#define SGTL5000_ANA_GND_BASE 0x320U /* mv */ +#define SGTL5000_ANA_GND_STP 0x19U /*mv */ +#define SGTL5000_BIAS_CTRL_MASK 0x000eU +#define SGTL5000_BIAS_CTRL_SHIFT 0x1U +#define SGTL5000_BIAS_CTRL_WIDTH 0x3U +#define SGTL5000_SMALL_POP 0x0001U + +/* + * SGTL5000_CHIP_MIC_CTRL + */ +#define SGTL5000_BIAS_R__CLR_MASK 0xFCFFU +#define SGTL5000_BIAS_R_GET_MASK 0x0300U +#define SGTL5000_BIAS_R_SHIFT 0x8U +#define SGTL5000_BIAS_R_off 0x0000U +#define SGTL5000_BIAS_R_2K 0x0100U +#define SGTL5000_BIAS_R_4k 0x0200U +#define SGTL5000_BIAS_R_8k 0x0300U +#define SGTL5000_BIAS_VOLT_CLR_MASK 0xFF8FU +#define SGTL5000_BIAS_VOLT_GET_MASK 0x0070U +#define SGTL5000_BIAS_VOLT_SHIFT 0x4U +#define SGTL5000_MIC_GAIN_CLR_MASK 0xFFFCU +#define SGTL5000_MIC_GAIN_GET_MASK 0x0003U +#define SGTL5000_MIC_GAIN_SHIFT 0x0U + +/* + * SGTL5000_CHIP_LINE_OUT_CTRL + */ +#define SGTL5000_LINE_OUT_CURRENT_CLR_MASK 0xF0FFU +#define SGTL5000_LINE_OUT_CURRENT_GET_MASK 0x0F00U +#define SGTL5000_LINE_OUT_CURRENT_SHIFT 0x8U +#define SGTL5000_LINE_OUT_CURRENT_180u 0x0000U +#define SGTL5000_LINE_OUT_CURRENT_270u 0x0100U +#define SGTL5000_LINE_OUT_CURRENT_360u 0x0300U +#define SGTL5000_LINE_OUT_CURRENT_450u 0x0700U +#define SGTL5000_LINE_OUT_CURRENT_540u 0x0F00U +#define SGTL5000_LINE_OUT_GND_CLR_MASK 0xFFC0U +#define SGTL5000_LINE_OUT_GND_GET_MASK 0x003FU +#define SGTL5000_LINE_OUT_GND_SHIFT 0x0U +#define SGTL5000_LINE_OUT_GND_BASE 0x320U /* mv */ +#define SGTL5000_LINE_OUT_GND_STP 0x19U +#define SGTL5000_LINE_OUT_GND_MAX 0x23U + +/* + * SGTL5000_CHIP_LINE_OUT_VOL + */ +#define SGTL5000_LINE_OUT_VOL_RIGHT_CLR_MASK 0xE0FFU +#define SGTL5000_LINE_OUT_VOL_RIGHT_GET_MASK 0x1F00U +#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 0x8U +#define SGTL5000_LINE_OUT_VOL_LEFT_CLR_MASK 0xFFE0U +#define SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK 0x001FU +#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0x0U + +/* + * SGTL5000_CHIP_ANA_POWER + */ +#define SGTL5000_RIGHT_DAC_POWERUP_GET_MASK 0x4000U +#define SGTL5000_RIGHT_DAC_POWERUP_CLR_MASK 0xBFFFU +#define SGTL5000_RIGHT_DAC_POWERUP_SHIFT 0xEU +#define SGTL5000_LINREG_SIMPLE_POWERUP_GET_MASK 0x2000U +#define SGTL5000_LINREG_SIMPLE_POWERUP_CLR_MASK 0xDFFFU +#define SGTL5000_LINREG_SIMPLE_POWERUP_SHIFT 0xDU +#define SGTL5000_STARTUP_POWERUP_GET_MASK 0x1000U +#define SGTL5000_STARTUP_POWERUP_CLR_MASK 0xEFFFU +#define SGTL5000_STARTUP_POWERUP_SHIFT 0xCU +#define SGTL5000_VDDC_CHRGPMP_POWERUP_GET_MASK 0x0800U +#define SGTL5000_VDDC_CHRGPMP_POWERUP_CLR_MASK 0xF7FFU +#define SGTL5000_VDDC_CHRGPMP_POWERUP_SHIFT 0xBU +#define SGTL5000_PLL_POWERUP_GET_MASK 0x0400U +#define SGTL5000_PLL_POWERUP_CLR_MASK 0xFBFFU +#define SGTL5000_PLL_POWERUP_SHIFT 0xAU +#define SGTL5000_LINREG_D_POWERUP_GET_MASK 0x0200U +#define SGTL5000_LINREG_D_POWERUP_CLR_MASK 0xFDFFU +#define SGTL5000_LINREG_D_POWERUP_SHIFT 0x9U +#define SGTL5000_VCOAMP_POWERUP_GET_MASK 0x0100U +#define SGTL5000_VCOAMP_POWERUP_CLR_MASK 0xFEFFU +#define SGTL5000_VCOAMP_POWERUP_SHIFT 0x8U +#define SGTL5000_VAG_POWERUP_GET_MASK 0x0080U +#define SGTL5000_VAG_POWERUP_CLR_MASK 0xFF7FU +#define SGTL5000_VAG_POWERUP_SHIFT 0x7U +#define SGTL5000_RIGHT_ADC_POWERUP_GET_MASK 0x0040U +#define SGTL5000_RIGHT_ADC_POWERUP_CLR_MASK 0xFFBFU +#define SGTL5000_RIGHT_ADC_POWERUP_SHIFT 0x6U +#define SGTL5000_REFTOP_POWERUP_GET_MASK 0x0020U +#define SGTL5000_REFTOP_POWERUP_CLR_MASK 0xFFDFU +#define SGTL5000_REFTOP_POWERUP_SHIFT 0x5U +#define SGTL5000_HEADPHONE_POWERUP_GET_MASK 0x0010U +#define SGTL5000_HEADPHONE_POWERUP_CLR_MASK 0xFFEFU +#define SGTL5000_HEADPHONE_POWERUP_SHIFT 0x4U +#define SGTL5000_DAC_POWERUP_GET_MASK 0x0008U +#define SGTL5000_DAC_POWERUP_CLR_MASK 0xFFF7U +#define SGTL5000_DAC_POWERUP_SHIFT 0x3U +#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_GET_MASK 0x0004U +#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_CLR_MASK 0xFFFBU +#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_SHIFT 0x2U +#define SGTL5000_ADC_POWERUP_GET_MASK 0x0002U +#define SGTL5000_ADC_POWERUP_CLR_MASK 0xFFFDU +#define SGTL5000_ADC_POWERUP_SHIFT 0x1U +#define SGTL5000_LINEOUT_POWERUP_GET_MASK 0x0001U +#define SGTL5000_LINEOUT_POWERUP_CLR_MASK 0xFFFEU +#define SGTL5000_LINEOUT_POWERUP_SHIFT 0x0U + +/* + * SGTL5000_CHIP_PLL_CTRL + */ +#define SGTL5000_PLL_INT_DIV_CLR_MASK 0x07FFU +#define SGTL5000_PLL_INT_DIV_GET_MASK 0xF800U +#define SGTL5000_PLL_INT_DIV_SHIFT 0xBU +#define SGTL5000_PLL_FRAC_DIV_CLR_MASK 0xF8FFU +#define SGTL5000_PLL_FRAC_DIV_GET_MASK 0x0700U +#define SGTL5000_PLL_FRAC_DIV_SHIFT 0x0U + +/* + * SGTL5000_CHIP_CLK_TOP_CTRL + */ +#define SGTL5000_ENABLE_INT_OSC_GET_MASK 0x0800U +#define SGTL5000_ENABLE_INT_OSC_CLR_MASK 0xF7FFU +#define SGTL5000_ENABLE_INT_OSC_SHIFT 0xBU +#define SGTL5000_INPUT_FREQ_DIV2_GET_MASK 0x0008U +#define SGTL5000_INPUT_FREQ_DIV2_CLR_MASK 0xFFF7U +#define SGTL5000_INPUT_FREQ_DIV2_SHIFT 0x3U + +/* + * SGTL5000_CHIP_ANA_STATUS + */ +#define SGTL5000_HP_LRSHORT 0x0200U +#define SGTL5000_CAPLESS_SHORT 0x0100U +#define SGTL5000_PLL_LOCKED 0x0010U + +/* + * SGTL5000_CHIP_SHORT_CTRL + */ +#define SGTL5000_LVLADJR_CLR_MASK 0x8FFFU +#define SGTL5000_LVLADJR_GET_MASK 0x7000U +#define SGTL5000_LVLADJR_SHIFT 0xCU +#define SGTL5000_LVLADJL_CLR_MASK 0xF8FFU +#define SGTL5000_LVLADJL_GET_MASK 0x0700U +#define SGTL5000_LVLADJL_SHIFT 0x8U +#define SGTL5000_LVLADJC_CLR_MASK 0xFF8FU +#define SGTL5000_LVLADJC_GET_MASK 0x0070U +#define SGTL5000_LVLADJC_SHIFT 0x4U +#define SGTL5000_LR_SHORT_MOD_CLR_MASK 0xFFF3U +#define SGTL5000_LR_SHORT_MOD_GET_MASK 0x000CU +#define SGTL5000_LR_SHORT_MOD_SHIFT 0x2U +#define SGTL5000_CM_SHORT_MOD_CLR_MASK 0xFFFCU +#define SGTL5000_CM_SHORT_MOD_GET_MASK 0x0003U +#define SGTL5000_CM_SHORT_MOD_SHIFT 0x0U + +/* DAP control register */ +#define SGTL5000_DAP_CONTROL_MIX_EN_GET_MASK 0x0010U +#define SGTL5000_DAP_CONTROL_MIX_EN_CLR_MASK 0xFFEFU +#define SGTL5000_DAP_CONTROL_MIX_EN_SHIFT 0x4U +#define SGTL5000_DAP_CONTROL_DAP_EN_GET_MASK 0x0001U +#define SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_CONTROL_DAP_EN_SHIFT 0x0U + +/* + * DAP_PEQ_REG + */ +#define SGTL5000_DAP_PEQ_EN_GET_MASK 0x0007U +#define SGTL5000_DAP_PEQ_EN_CLR_MASK 0xFFF8U +#define SGTL5000_DAP_PEQ_EN_SHIFT 0x0U + +/* + * DAP_BASS_ENHANCE_REG + */ +#define SGTL5000_DAP_BASS_ENHANCE_MULT_GET_MASK 0xC000U +#define SGTL5000_DAP_BASS_ENHANCE_MULT_CLR_MASK 0x3FFFU +#define SGTL5000_DAP_BASS_ENHANCE_MULT_SHIFT 0xEU +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_GET_MASK 0x0E00U +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_CLR_MASK 0xF1FFU +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_SHIFT 0x9U +#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_GET_MASK 0x0100U +#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_CLR_MASK 0xFEFFU +#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_SHIFT 0x8U +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_GET_MASK 0x0070U +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_CLR_MASK 0xFF8FU +#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_SHIFT 0x4U +#define SGTL5000_DAP_BASS_ENHANCE_EN_GET_MASK 0x0001U +#define SGTL5000_DAP_BASS_ENHANCE_EN_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_BASS_ENHANCE_EN_SHIFT 0x0U + +/* + * DAP_BASS_ENHANCE_CTRL_REG + */ +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_GET_MASK 0x3F00U +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_CLR_MASK 0xC0FFU +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_SHIFT 0x8U +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_GET_MASK 0x007FU +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_CLR_MASK 0xFF80U +#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_EN_GET_MASK 0x0003U +#define SGTL5000_DAP_AUDIO_EQ_EN_CLR_MASK 0xFFFCU +#define SGTL5000_DAP_AUDIO_EQ_EN_SHIFT 0x0U + +/* + * DAP_SGTL_SURROUND_REG + */ +#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_GET_MASK 0x0070U +#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_CLR_MASK 0xFF8FU +#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_SHIFT 0x4U +#define SGTL5000_DAP_SGTL_SURROUND_SEL_GET_MASK 0x0003U +#define SGTL5000_DAP_SGTL_SURROUND_SEL_CLR_MASK 0xFFFCU +#define SGTL5000_DAP_SGTL_SURROUND_SEL_SHIFT 0x0U + +/* + * DAP_FILTER_COEF_ACCESS_REG + */ +#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_GET_MASK 0x1000U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_CLR_MASK 0xEFFFU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_SHIFT 0xCU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_GET_MASK 0x0200U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_CLR_MASK 0xFDFFU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_SHIFT 0x9U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_GET_MASK 0x0100U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_CLR_MASK 0xFEFFU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_SHIFT 0x8U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_GET_MASK 0x00FFU +#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_CLR_MASK 0xFF00U +#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_SHIFT 0x0U + +/* + * DAP_COEF_WR_B0_MSB_REG + */ +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_GET_MASK 0x8000U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_CLR_MASK 0x7FFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_SHIFT 0xFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_GET_MASK 0x4000U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_CLR_MASK 0xBFFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_SHIFT 0xEU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_GET_MASK 0x2000U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_CLR_MASK 0xDFFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_SHIFT 0xDU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_GET_MASK 0x1000U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_CLR_MASK 0xEFFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_SHIFT 0xCU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_GET_MASK 0x0800U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_CLR_MASK 0xF7FFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_SHIFT 0xBU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_GET_MASK 0x0400U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_CLR_MASK 0xFBFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_SHIFT 0xAU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_GET_MASK 0x0200U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_CLR_MASK 0xFDFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_SHIFT 0x9U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_GET_MASK 0x0100U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_CLR_MASK 0xFEFFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_SHIFT 0x8U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_GET_MASK 0x0080U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_CLR_MASK 0xFF7FU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_SHIFT 0x7U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_GET_MASK 0x0040U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_CLR_MASK 0xFFBFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_SHIFT 0x6U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_GET_MASK 0x0020U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_CLR_MASK 0xFFDFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_SHIFT 0x5U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_GET_MASK 0x0010U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_CLR_MASK 0xFFEFU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_SHIFT 0x4U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_GET_MASK 0x0008U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_CLR_MASK 0xFFF7U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_SHIFT 0x3U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_GET_MASK 0x0004U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_CLR_MASK 0xFFFBU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_SHIFT 0x2U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_GET_MASK 0x0002U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_CLR_MASK 0xFFFDU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_SHIFT 0x1U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_GET_MASK 0x0001U +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_SHIFT 0x0U + +/* + * DAP_COEF_WR_B0_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_GET_MASK 0x0008U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_CLR_MASK 0xFFF7U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_SHIFT 0x3U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_GET_MASK 0x0004U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_CLR_MASK 0xFFFBU +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_SHIFT 0x2U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_GET_MASK 0x0002U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_CLR_MASK 0xFFFDU +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_SHIFT 0x1U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_GET_MASK 0x0001U +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_BASS_BAND0_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_BAND1_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_BAND2_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_BAND3_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_SHIFT 0x0U + +/* + * DAP_AUDIO_EQ_TREBLE_BAND4_REG + */ +#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_GET_MASK 0x007FU +#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_CLR_MASK 0xFF80U +#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_SHIFT 0x0U + +/* + * DAP_MAIN_CHAN_REG + */ +#define SGTL5000_DAP_MAIN_CHAN_VOL_GET_MASK 0xFFFFU +#define SGTL5000_DAP_MAIN_CHAN_VOL_CLR_MASK 0x0000U +#define SGTL5000_DAP_MAIN_CHAN_VOL_SHIFT 0x0U + +/* + * DAP_MIX_CHAN_REG + */ +#define SGTL5000_DAP_MIX_CHAN_VOL_GET_MASK 0xFFFFU +#define SGTL5000_DAP_MIX_CHAN_VOL_CLR_MASK 0x0000U +#define SGTL5000_DAP_MIX_CHAN_VOL_SHIFT 0x0U + +/* + * DAP_AVC_CTRL_REG + */ +#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_GET_MASK 0x4000U +#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_CLR_MASK 0xBFFFU +#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_SHIFT 0xEU +#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_GET_MASK 0x3000U +#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_CLR_MASK 0xCFFFU +#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_SHIFT 0xCU +#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_GET_MASK 0x0300U +#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_CLR_MASK 0xFCFFU +#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_SHIFT 0x8U +#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_GET_MASK 0x0020U +#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_CLR_MASK 0xFFDFU +#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_SHIFT 0x5U +#define SGTL5000_DAP_AVC_CTRL_STOP_GET_MASK 0x0004U +#define SGTL5000_DAP_AVC_CTRL_STOP_SHIFT 0x2U +#define SGTL5000_DAP_AVC_CTRL_RUNNING_GET_MASK 0x0002U +#define SGTL5000_DAP_AVC_CTRL_RUNNING_SHIFT 0x1U +#define SGTL5000_DAP_AVC_CTRL_EN_GET_MASK 0x0001U +#define SGTL5000_DAP_AVC_CTRL_EN_CLR_MASK 0xFFFEU +#define SGTL5000_DAP_AVC_CTRL_EN_SHIFT 0x0U + +/* + * DAP_AVC_ATTACK_REG + */ +#define SGTL5000_DAP_AVC_ATTACK_RATE_GET_MASK 0x0FFFU +#define SGTL5000_DAP_AVC_ATTACK_RATE_CLR_MASK 0xF000U +#define SGTL5000_DAP_AVC_ATTACK_RATE_SHIFT 0x0U + +/* + * DAP_AVC_DECAY_REG + */ +#define SGTL5000_DAP_AVC_DECAY_RATE_GET_MASK 0x0FFFU +#define SGTL5000_DAP_AVC_DECAY_RATE_CLR_MASK 0xF000U +#define SGTL5000_DAP_AVC_DECAY_RATE_SHIFT 0x0U + +/* + * DAP_COEF_WR_B1_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_GET_MASK 0x000FU +#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_CLR_MASK 0xFFF0U +#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_SHIFT 0x0U + +/* + * DAP_COEF_WR_B2_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_GET_MASK 0x000FU +#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_CLR_MASK 0xFFF0U +#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_SHIFT 0x0U + +/* + * DAP_COEF_WR_A1_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_GET_MASK 0x000FU +#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_CLR_MASK 0xFFF0U +#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_SHIFT 0x0U + +/* + * DAP_COEF_WR_A2_LSB_REG + */ +#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_GET_MASK 0x000FU +#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_CLR_MASK 0xFFF0U +#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_SHIFT 0x0U + +/*! @brief SGTL5000 volume setting range */ +#define SGTL5000_HEADPHONE_MAX_VOLUME_VALUE 0x7FU +#define SGTL5000_HEADPHONE_MIN_VOLUME_VALUE 0U +#define SGTL5000_LINE_OUT_MAX_VOLUME_VALUE 0x1FU +#define SGTL5000_LINE_OUT_MIN_VOLUME_VALUE 0U +#define SGTL5000_ADC_MAX_VOLUME_VALUE 0xFU +#define SGTL5000_ADC_MIN_VOLUME_VALUE 0U +#define SGTL5000_DAC_MAX_VOLUME_VALUE 0xF0U +#define SGTL5000_DAC_MIN_VOLUME_VALUE 0x3CU + +/*! @brief SGTL5000 I2C address. */ +#define SGTL5000_I2C_ADDR 0x0A + +/*! @brief sgtl i2c baudrate */ +#define SGTL_I2C_BITRATE 100000U + +/*! @brief Modules in Sgtl5000 board. */ +typedef enum _sgtl5000_module +{ + sgtl_module_adc = 0x0, /*!< ADC module in SGTL5000 */ + sgtl_module_dac, /*!< DAC module in SGTL5000 */ + sgtl_module_dap, /*!< DAP module in SGTL5000 */ + sgtl_module_hp, /*!< Headphone module in SGTL5000 */ + sgtl_module_i2sin, /*!< I2S-IN module in SGTL5000 */ + sgtl_module_i2sout, /*!< I2S-OUT module in SGTL5000 */ + sgtl_module_linein, /*!< Line-in moudle in SGTL5000 */ + sgtl_module_lineout, /*!< Line-out module in SGTL5000 */ + sgtl_module_micin /*!< Micphone module in SGTL5000 */ +} sgtl_module_t; + +/*! + * @brief Sgtl5000 data route. + * @note Only provide some typical data route, not all route listed. + * Users cannot combine any routes, once a new route is set, the precios one would be replaced. + */ +typedef enum _sgtl_route +{ + sgtl_route_bypass = 0x0, /*!< LINEIN->Headphone. */ + sgtl_route_playback, /*!< I2SIN->DAC->Headphone. */ + sgtl_route_playback_record, /*!< I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT. */ + sgtl_route_playback_with_dap, /*!< I2SIN->DAP->DAC->Headphone. */ + sgtl_route_playback_with_dap_record, /*!< I2SIN->DAP->DAC->HP, LINEIN->ADC->I2SOUT. */ + sgtl_route_record /*!< LINEIN->ADC->I2SOUT. */ +} sgtl_route_t; + +/*! + * @brief The audio data transfer protocol choice. + * Sgtl5000 only supports I2S format and PCM format. + */ +typedef enum _sgtl_protocol +{ + sgtl_bus_i2s = 0x0, /*!< I2S Type */ + sgtl_bus_left_justified, /*!< Left justified */ + sgtl_bus_right_justified, /*!< Right Justified */ + sgtl_bus_pcma, /*!< PCMA */ + sgtl_bus_pcmb /*!< PCMB */ +} sgtl_protocol_t; + +/*! @brief sgtl play channel + * @anchor _sgtl_play_channel + */ +enum +{ + sgtl_headphone_left = 0, /*!< headphone left channel */ + sgtl_headphone_right = 1, /*!< headphone right channel */ + sgtl_lineout_left = 2, /*!< lineout left channel */ + sgtl_lineout_right = 3, /*!< lineout right channel */ +}; + +/*! @brief sgtl record source + * _sgtl_record_source + */ +enum +{ + sgtl_record_source_linein = 0U, /*!< record source line in */ + sgtl_record_source_mic = 1U, /*!< record source single end */ +}; + +/*! @brief sgtl play source + * _stgl_play_source + */ +enum +{ + sgtl_play_source_linein = 0U, /*!< play source line in */ + sgtl_play_source_dac = 1U, /*!< play source line in */ +}; + +/*! @brief SGTL SCLK valid edge */ +typedef enum _sgtl_sclk_edge +{ + sgtl_sclk_valid_edge_rising = 0U, /*!< SCLK valid edge */ + sgtl_sclk_valid_edge_failing = 1U, /*!< SCLK failling edge */ +} sgtl_sclk_edge_t; + +/*! @brief Audio format configuration. */ +typedef struct _sgtl_audio_format +{ + uint32_t mclk_hz; /*!< master clock */ + uint32_t sample_rate; /*!< Sample rate */ + uint32_t bit_width; /*!< Bit width */ + sgtl_sclk_edge_t sclk_edge; /*!< sclk valid edge */ +} sgtl_audio_format_t; + +/*! @brief Initailize structure of sgtl5000 */ +typedef struct _sgtl_config +{ + sgtl_route_t route; /*!< Audio data route.*/ + sgtl_protocol_t bus; /*!< Audio transfer protocol */ + bool master; /*!< Master or slave. True means master, false means slave. */ + sgtl_audio_format_t format; /*!< audio format */ +} sgtl_config_t; + +typedef struct +{ + I2C_Type *ptr;; /*!< sgtl I2C pointer */ + uint8_t slave_address; /*!< code device slave address */ +} sgtl_context_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief sgtl5000 initialize function. + * + * In this function, some configurations are fixed. + * The second parameter can be NULL. If users want to change the SGTL5000 settings, + * a configure structure should be prepared. + * @note If the codec_config is NULL, it would initialize sgtl5000 using default settings. + * The default setting: + * @code + * sgtl_init_t codec_config + * codec_config.route = sgtl_route_playback_record + * codec_config.bus = sgtl_bus_i2s + * codec_config.master = slave + * @endcode + * + * @param context Sgtl5000 context structure. + * @param config sgtl5000 configuration structure. If this pointer equals to NULL, + * it means using the default configuration. + * @return Initialization status + */ +hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config); + +/*! + * @brief Set audio data route in sgtl5000. + * + * This function would set the data route according to route. The route cannot be combined, + * as all route would enable different modules. + * + * @note If a new route is set, the previous route would not work. + * @param context Sgtl5000 context structure. + * @param route Audio data route in sgtl5000. + */ +hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route); + +/*! + * @brief Set the audio transfer protocol. + * + * Sgtl5000 only supports I2S, I2S left, I2S right, PCM A, PCM B format. + * @param context Sgtl5000 context structure. + * @param protocol Audio data transfer protocol. + */ +hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol); + +/*! + * @brief Set sgtl5000 as master or slave. + * + * @param context Sgtl5000 context structure. + * @param master 1 represent master, 0 represent slave. + */ +void sgtl_set_master_mode(sgtl_context_t *context, bool master); + +/*! + * @brief Set the volume of different modules in sgtl5000. + * + * This function would set the volume of sgtl5000 modules. This interface set module volume. + * The function assume that left channel and right channel has the same volume. + * + * sgtl_module_adc volume range: 0 - 0xF, 0dB - 22.5dB + * sgtl_module_dac volume range: 0x3C - 0xF0, 0dB - -90dB + * sgtl_module_hp volume range: 0 - 0x7F, 12dB - -51.5dB + * sgtl_module_lineout volume range: 0 - 0x1F, 0.5dB steps + * + * @param context Sgtl5000 context structure. + * @param module Sgtl5000 module, such as DAC, ADC and etc. + * @param volume Volume value need to be set. The value is the exact value in register. + */ +hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32_t volume); + +/*! + * @brief Get the volume of different modules in sgtl5000. + * + * This function gets the volume of sgtl5000 modules. This interface get DAC module volume. + * The function assume that left channel and right channel has the same volume. + * @param context Sgtl5000 context structure. + * @param module Sgtl5000 module, such as DAC, ADC and etc. + * @return Module value, the value is exact value in register. + */ +uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module); + +/*! + * @brief Mute/unmute modules in sgtl5000. + * + * @param context Sgtl5000 context structure. + * @param module Sgtl5000 module, such as DAC, ADC and etc. + * @param mute True means mute, and false means unmute. + */ +hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute); + +/*! + * @brief Enable expected devices. + * @param context Sgtl5000 context structure. + * @param module Module expected to enable. + */ +hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module); + +/*! + * @brief Disable expected devices. + * @param context Sgtl5000 context structure. + * @param module Module expected to enable. + */ +hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module); + +/*! + * @brief Deinit the sgtl5000 codec. Shut down Sgtl5000 modules. + * @param context Sgtl5000 context structure pointer. + */ +hpm_stat_t sgtl_deint(sgtl_context_t *context); + +/*! + * @brief Configure the data format of audio data. + * + * This function would configure the registers about the sample rate, bit depths. + * @param context Sgtl5000 context structure pointer. + * @param mclk Master clock frequency of I2S. + * @param sample_rate Sample rate of audio file running in sgtl5000. Sgtl5000 now + * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. + * @param bits Bit depth of audio file (Sgtl5000 only supports 16bit, 20bit, 24bit + * and 32 bit in HW). + */ +hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits); + +/*! + * @brief select SGTL codec play source. + * + * @param context Sgtl5000 context structure pointer. + * @param playSource play source value, reference _sgtl_play_source. + * + * @return kStatus_Success, else failed. + */ +hpm_stat_t sgtl_set_play(sgtl_context_t *context, uint32_t playSource); + +/*! + * @brief select SGTL codec record source. + * + * @param context Sgtl5000 context structure pointer. + * @param recordSource record source value, reference _sgtl_record_source. + * + * @return kStatus_Success, else failed. + */ +hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource); + +/*! + * @brief Write register to sgtl using I2C. + * @param context Sgtl5000 context structure. + * @param reg The register address in sgtl. + * @param val Value needs to write into the register. + */ +hpm_stat_t sgtl_write_reg(sgtl_context_t *context, uint16_t reg, uint16_t val); + +/*! + * @brief Read register from sgtl using I2C. + * @param context Sgtl5000 context structure. + * @param reg The register address in sgtl. + * @param val Value written to. + */ +hpm_stat_t sgtl_read_reg(sgtl_context_t *context, uint16_t reg, uint16_t *val); + +/*! + * @brief Modify some bits in the register using I2C. + * @param context Sgtl5000 context structure. + * @param reg The register address in sgtl. + * @param clr_mask The mask code for the bits want to write. The bit you want to write should be 0. + * @param val Value needs to write into the register. + */ +hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_mask, uint16_t val); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _HPM_SGTL5000_H_ */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c new file mode 100644 index 0000000000..f330883e74 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_debug_console.h" +#include "hpm_uart_drv.h" + +static UART_Type* g_console_uart = NULL; + +hpm_stat_t console_init(console_config_t *cfg) +{ + hpm_stat_t stat = status_fail; + + if (cfg->type == console_type_uart) + { + uart_config_t config = {0}; + uart_default_config((UART_Type *)cfg->base, &config); + config.src_freq_in_hz = cfg->src_freq_in_hz; + config.baudrate = cfg->baudrate; + stat = uart_init((UART_Type *)cfg->base, &config); + if (status_success == stat) { + g_console_uart = (UART_Type *)cfg->base; + } + } + + return stat; +} + +uint8_t console_receive_byte() +{ + uint8_t c; + while (status_success != uart_receive_byte(g_console_uart, &c)) { + }; + return c; +} + +void console_send_byte(uint8_t c) +{ + while (status_success != uart_send_byte(g_console_uart, c)) { + } +} + +#ifdef __SEGGER_RTL_VERSION +#include "__SEGGER_RTL_Int.h" +static int _stdin_ungot = EOF; +struct __SEGGER_RTL_FILE_impl { /* NOTE: Provides implementation for FILE */ + int stub; /* only needed so impl has size != 0. */ +}; + +static FILE __SEGGER_RTL_stdin_file = { 0 }; /* stdin reads from UART */ +static FILE __SEGGER_RTL_stdout_file = { 0 }; /* stdout writes to UART */ +static FILE __SEGGER_RTL_stderr_file = { 0 }; /* stderr writes to UART */ + +FILE *stdin = &__SEGGER_RTL_stdin_file; /* NOTE: Provide implementation of stdin for RTL. */ +FILE *stdout = &__SEGGER_RTL_stdout_file; /* NOTE: Provide implementation of stdout for RTL. */ +FILE *stderr = &__SEGGER_RTL_stderr_file; /* NOTE: Provide implementation of stderr for RTL. */ + +int __SEGGER_RTL_X_file_write(__SEGGER_RTL_FILE *file, const char *data, unsigned size) +{ + int count; + (void)file; + for(count = 0; count < size; count++) + { + if (data[count] == '\n') + { + while (status_success != uart_send_byte(g_console_uart, '\r')) { + } + } + while (status_success != uart_send_byte(g_console_uart, data[count])) { + } + } + while (status_success != uart_flush(g_console_uart)) { + } + return count; + +} + +int __SEGGER_RTL_X_file_read(__SEGGER_RTL_FILE *file, char *s, unsigned size) +{ + (void)file; + while (status_success != uart_receive_byte(g_console_uart, (uint8_t *)s)) { + } + return 1; +} + +int __SEGGER_RTL_X_file_stat(__SEGGER_RTL_FILE *stream) +{ + return 0; +} + +int __SEGGER_RTL_X_file_bufsize(__SEGGER_RTL_FILE *stream) +{ + return 1; +} + +int __SEGGER_RTL_X_file_unget(__SEGGER_RTL_FILE *stream, int c) +{ + if (stream == stdin) { + if (c != EOF && _stdin_ungot == EOF) { + _stdin_ungot = c; + } else { + c = EOF; + } + } else { + c = EOF; + } + return c; +} + +int __SEGGER_RTL_X_file_flush(__SEGGER_RTL_FILE *__stream) +{ + return 1; +} + +#endif + +int _write(int file, char *data, int size) +{ + int count; + (void)file; + for(count = 0; count < size; count++) + { + if (data[count] == '\n') + { + while (status_success != uart_send_byte(g_console_uart, '\r')) { + } + } + while (status_success != uart_send_byte(g_console_uart, data[count])) { + } + } + while (status_success != uart_flush(g_console_uart)) { + } + return count; +} + +int _read(int file, char *s, int size) +{ + (void)file; + while (status_success != uart_receive_byte(g_console_uart, (uint8_t *)s)) { + } + return 1; +} + +int _fstat(int file, struct stat *s) +{ + s->st_mode = S_IFCHR; + return 0; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h new file mode 100644 index 0000000000..08ab66503b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_DEBUG_CONSOLE_H +#define _HPM_DEBUG_CONSOLE_H +#include +#include "hpm_common.h" + +typedef enum console_type { + console_type_uart = 0, +} console_type_t; + +typedef struct { + console_type_t type; + uint32_t base; + uint32_t src_freq_in_hz; + uint32_t baudrate; +} console_config_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +hpm_stat_t console_init(console_config_t *cfg); + +uint8_t console_receive_byte(void); + +void console_send_byte(uint8_t c); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _HPM_CONSOLE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c new file mode 100644 index 0000000000..1174bd6391 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_dma_manager.h" +#include "hpm_soc.h" +#include + +/***************************************************************************************************************** + * + * Definitions + * + *****************************************************************************************************************/ + +typedef struct _dma_instance_info { + DMA_Type *base; + int32_t irq_num; +} dma_channel_info_t; + +/** + * @brief DMA Manager Context Structure + * + */ +typedef struct _dma_manager_context { + dma_channel_info_t dma_instance[DMA_SOC_MAX_COUNT]; /**< DMA instances */ + hpm_dma_channel_context_t channels[DMA_SOC_MAX_COUNT][DMA_SOC_CHANNEL_NUM]; /**< Array of DMA channels */ +} hpm_dma_manager_context_t; + +#define DMA_DISABLE_ALL_CHN_INT (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT) + + +/***************************************************************************************************************** + * + * Prototypes + * + *****************************************************************************************************************/ + +/** + * @brief Search DMA channel context for specified DMA channel resource + * + * @param [in] resource DMA Channel resource + * @return The request DMA channel context if resource is valid or NULL if resource in invalid + */ +static hpm_dma_channel_context_t *dma_manager_search_channel_context(const hpm_dma_resource_t *resource); + +static uint32_t dma_manager_enter_critical(void); +static void dma_manager_exit_critical(uint32_t level); + +static void dma0_isr(void); +SDK_DECLARE_EXT_ISR_M(IRQn_HDMA, dma0_isr); + +#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) +static void dma1_isr(void); +SDK_DECLARE_EXT_ISR_M(IRQn_XDMA, dma1_isr); +#endif + +/***************************************************************************************************************** + * + * Variables + * + *****************************************************************************************************************/ +static hpm_dma_manager_context_t s_dma_mngr_ctx; +#define HPM_DMA_MGR (&s_dma_mngr_ctx) + + + +/***************************************************************************************************************** + * + * Codes + * + *****************************************************************************************************************/ +static inline void handle_dma_isr(DMA_Type *ptr, uint32_t instance) +{ + for (uint8_t channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { + uint32_t int_disable_mask = dma_check_channel_interrupt_mask(ptr, channel); + /* If Channel interrupt is enabled */ + if (int_disable_mask != DMA_DISABLE_ALL_CHN_INT) { + uint32_t chn_int_stat = dma_check_transfer_status(ptr, channel); + if (chn_int_stat != DMA_CHANNEL_STATUS_ONGOING) { + hpm_dma_channel_context_t *chn_ctx = &HPM_DMA_MGR->channels[instance][channel]; + if (chn_ctx->callback != NULL) { + chn_ctx->callback(ptr, channel, chn_ctx->user_data, chn_int_stat); + } + } /* end if (chn_int_stat != DMA_CHANNEL_STATUS_ONGOING) */ + } /* end if (int_disable_mask != DMA_DISABLE_ALL_CHN_INT) */ + } /* end for (uint8_t channel = 0; channel < DMA_SOC_MAX_COUNT; channel++) */ +} + +void dma0_isr(void) +{ + handle_dma_isr(HPM_HDMA, 0); +} + +#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) +void dma1_isr(void) +{ + handle_dma_isr(HPM_XDMA, 1); +} +#endif + +static uint32_t dma_manager_enter_critical(void) +{ + uint32_t level = read_csr(CSR_MSTATUS); + disable_global_irq(CSR_MSTATUS_MIE_MASK); + return level; +} + +static void dma_manager_exit_critical(uint32_t level) +{ + write_csr(CSR_MSTATUS, level); +} + +/* See hpm_dma_manager.h for more details */ +void dma_manager_init(void) +{ + (void) memset(HPM_DMA_MGR, 0, sizeof(*HPM_DMA_MGR)); + HPM_DMA_MGR->dma_instance[0].base = HPM_HDMA, + HPM_DMA_MGR->dma_instance[0].irq_num = IRQn_HDMA; + #if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) + HPM_DMA_MGR->dma_instance[1].base = HPM_XDMA; + HPM_DMA_MGR->dma_instance[1].irq_num = IRQn_XDMA; + #endif +} + +/* See hpm_dma_manager.h for more details */ +hpm_stat_t dma_manager_request_resource(hpm_dma_resource_t *resource) +{ + hpm_stat_t status; + + if (resource == NULL) { + status = status_invalid_argument; + } else { + uint32_t instance; + uint32_t channel; + bool has_found = false; + uint32_t level = dma_manager_enter_critical(); + for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { + for (channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { + if (!HPM_DMA_MGR->channels[instance][channel].is_allocated) { + has_found = true; + break; + } + } + if (has_found) { + break; + } + } + + if (has_found) { + HPM_DMA_MGR->channels[instance][channel].is_allocated = true; + resource->base = HPM_DMA_MGR->dma_instance[instance].base; + resource->channel = channel; + resource->irq_num = HPM_DMA_MGR->dma_instance[instance].irq_num; + status = status_success; + } else { + status = status_dma_manager_no_resource; + } + + dma_manager_exit_critical(level); + } + + return status; +} + +static hpm_dma_channel_context_t *dma_manager_search_channel_context(const hpm_dma_resource_t *resource) +{ + hpm_dma_channel_context_t *channel_ctx = NULL; + + if ((resource != NULL) && (resource->channel < DMA_SOC_CHANNEL_NUM)) { + uint32_t instance; + uint32_t channel; + bool has_found = false; + for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { + if (resource->base == HPM_DMA_MGR->dma_instance[instance].base) { + has_found = true; + break; + } + } + + channel = resource->channel; + if (has_found) { + channel_ctx = &HPM_DMA_MGR->channels[instance][channel]; + } + } + + return channel_ctx; +} + +/* See hpm_dma_manager.h for more details */ +hpm_stat_t dma_manager_release_resource(const hpm_dma_resource_t *resource) +{ + hpm_stat_t status; + + hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); + + if (channel_ctx == NULL) { + status = status_invalid_argument; + } else { + + uint32_t level = dma_manager_enter_critical(); + channel_ctx->is_allocated = false; + channel_ctx->user_data = NULL; + channel_ctx->callback = NULL; + status = status_success; + dma_manager_exit_critical(level); + } + return status; +} + +/* See hpm_dma_manager.h for more details */ +hpm_stat_t dma_manager_enable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask) +{ + hpm_stat_t status; + + hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); + + if (channel_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_enable_channel_interrupt(resource->base, resource->channel, irq_mask); + status = status_success; + } + return status; +} + +/* See hpm_dma_manager.h for more details */ +hpm_stat_t dma_manager_disable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask) +{ + hpm_stat_t status; + + hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); + + if (channel_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_disable_channel_interrupt(resource->base, resource->channel, irq_mask); + status = status_success; + } + return status; +} + + +/* See hpm_dma_manager.h for more details */ +hpm_stat_t dma_manager_enable_dma_interrupt(const hpm_dma_resource_t *resource, uint32_t priority) +{ + hpm_stat_t status; + + hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); + + if (channel_ctx == NULL) { + status = status_invalid_argument; + } else { + intc_m_enable_irq_with_priority(resource->irq_num, priority); + status = status_success; + } + return status; +} + +/* See hpm_dma_manager.h for more details */ +hpm_stat_t dma_manager_disable_dma_interrupt(const hpm_dma_resource_t *resource) +{ + hpm_stat_t status; + + hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); + + if (channel_ctx == NULL) { + status = status_invalid_argument; + } else { + intc_m_disable_irq(resource->irq_num); + status = status_success; + } + return status; +} + + +/* See hpm_dma_manager.h for more details */ +hpm_stat_t dma_manager_install_interrupt_callback(const hpm_dma_resource_t *resource, hpm_dma_channel_callback_t callback, void *user_data) +{ + hpm_stat_t status; + + hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); + + if (channel_ctx == NULL) { + status = status_invalid_argument; + } else { + channel_ctx->user_data = user_data; + channel_ctx->callback = callback; + status = status_success; + } + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h new file mode 100644 index 0000000000..6d5ada4548 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_DMA_MANAGER_H +#define HPM_DMA_MANAGER_H + +#include "hpm_common.h" +#include "hpm_dma_drv.h" +#include "hpm_soc_feature.h" + + +#ifdef __cplusplus + +extern "C" { +#endif + + +/** + * @brief DMA Manager status codes + */ +enum { + status_dma_manager_no_resource = MAKE_STATUS(status_group_dma_manager, 0), /**< No DMA resource available */ +}; + +/** + * @brief DMA Channel Interrupt callback + * + * @param [in] DMA base address + * @param [in] channel DMA channel index + * @param [in/out] user_data User Data context + * @param [in] int_stat DMA interrupt status + * bit0 - DMA_CHANNEL_STATUS_ONGOING + * bit1 - DMA_CHANNEL_STATUS_ERROR + * bit2 - DMA_CHANNEL_STATUS_ABORT + * bit3 - DMA_CHANNEL_STATUS_TC + */ +typedef void (*hpm_dma_channel_callback_t)(DMA_Type *base, uint32_t channel, void *user_data, uint32_t int_stat); + +/** + * @brief DMA Resource Structure + */ +typedef struct _dma_resource { + DMA_Type *base; /**< The DMA intance that the allocated channel belongs to */ + uint32_t channel; /**< Channel index */ + int32_t irq_num; /**< DMA IRQ number */ +} hpm_dma_resource_t; + +/** + * @brief DMA Channel Context Structure + */ +typedef struct _dma_channel_context { + bool is_allocated; /**< Whether DMA channel was allocated */ + void *user_data; /**< User data required by DMA channel callback */ + hpm_dma_channel_callback_t callback;/**< DMA channel callback */ +} hpm_dma_channel_context_t; + + +/** + * @brief Initialize DMA Manager Context + */ +void dma_manager_init(void); + +/** + * @brief Request DMA resource from DMA Manager + * + * @param [out] resource DMA resource + * @retval status_success if no error occurred + * @retval status_invalid_argument if the parameter is invalid + * @retval status_dma_manager_no_resource if all DMA channels are occupied; + */ +hpm_stat_t dma_manager_request_resource(hpm_dma_resource_t *resource); + +/** + * @brief Release DMA resource + * + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if the parameter is invalid + */ +hpm_stat_t dma_manager_release_resource(const hpm_dma_resource_t *resource); + + +/** + * @brief Enable Resource interrupt + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_manager_enable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask); + + +/** + * @brief Disable Resource interrupt + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_manager_disable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask); + + +/** + * @brief Enable DMa interrupt + * @param [in] resource DMA resource + * @param [in] priority Interrupt Priority + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_manager_enable_dma_interrupt(const hpm_dma_resource_t *resource, uint32_t priority); + +/** + * @brief Disable DMA interrupt + * NOTE: Each DMA instance consists of several DMA channels, disabling the DMA interrupt + * will disable the global DMA interrupt for all DMA channels. Please be aware of the + * impact + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_manager_disable_dma_interrupt(const hpm_dma_resource_t *resource); + + +/** + * @brief Install Interrupt Callback for the DMA resource + * + * @param [in] resource DMA resource + * @param [in] callback Interrupt callback for DMA resource + * @param [in] user_data User data used in the callback + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_manager_install_interrupt_callback(const hpm_dma_resource_t *resource, hpm_dma_channel_callback_t callback, void *user_data); + + + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_DMA_MANAGER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c new file mode 100644 index 0000000000..5805e3d516 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_enet_drv.h" +#include "hpm_dp83848_regs.h" +#include "hpm_dp83848.h" +#include "board.h" + +/*---------------------------------------------------------------------* + * Internal API + *---------------------------------------------------------------------*/ +static bool dp83848_id_check(ENET_Type *ptr) +{ + uint16_t id1, id2; + + id1 = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_PHYID1); + id2 = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_PHYID2); + + if (DP83848_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && DP83848_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + return true; + } else { + return false; + } +} + +/*---------------------------------------------------------------------* + * API + *---------------------------------------------------------------------*/ +uint16_t dp83848_register_check(ENET_Type *ptr, uint32_t addr) +{ + return enet_read_phy(ptr, PHY_ADDR, addr); +} + +void dp83848_reset(ENET_Type *ptr) +{ + uint16_t data; + + /* PHY reset */ + enet_write_phy(ptr, PHY_ADDR, DP83848_REG_BMCR, DP83848_BMCR_RESET_SET(1)); + + /* wait until the reset is completed */ + do { + data = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_BMCR); + } while (DP83848_BMCR_RESET_GET(data)); +} + +void dp83848_basic_mode_default_config(ENET_Type *ptr, dp83848_config_t *config) +{ + config->loopback = 1; /* Enable PCS loopback mode */ + config->speed = 2; /* reserved:3/2; 100mbps: 1; 10mbps: 0 */ + config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + config->duplex_mode = 1; /* Full duplex mode */ +} + +bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config) +{ + uint16_t para = 0; + + para |= DP83848_BMCR_RESET_SET(0) /* Normal operation */ + | DP83848_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ + | DP83848_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ + | DP83848_BMCR_PWD_SET(0) /* Normal operation */ + | DP83848_BMCR_ISOLATE_SET(0) /* Normal operation */ + | DP83848_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ + | DP83848_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ + + if (config->auto_negotiation == 0) { + para |= DP83848_BMCR_SPEED0_SET(config->speed) | DP83848_BMCR_SPEED1_SET(config->speed >> 1); + } + + /* check the id of dp83848 */ + if (dp83848_id_check(ptr) == false) { + return false; + } + + para = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_BMCR) & ~ DP83848_BMCR_SPEED0_MASK; + enet_write_phy(ptr, PHY_ADDR, DP83848_REG_BMCR, para); + + return true; +} + + +void dp83848_init_auto_negotiation(void) +{ +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h new file mode 100644 index 0000000000..e19f70b12a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_DP83848_H +#define HPM_DP83848_H + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "stdint.h" + +/*---------------------------------------------------------------------* + * Macro Const Definitions + *---------------------------------------------------------------------*/ +#define PHY_ADDR (1U) +#define PHY_ID1 (0x2000U) +#define PHY_ID2 (0x17U) + +/*---------------------------------------------------------------------* + * Typedef Struct Declarations + *---------------------------------------------------------------------*/ +typedef struct { + bool loopback; + uint8_t speed; + bool auto_negotiation; + uint8_t duplex_mode; +} dp83848_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ +/*---------------------------------------------------------------------* + * Exported Functions + *---------------------------------------------------------------------*/ +uint16_t dp83848_check(ENET_Type *ptr, uint32_t addr); +void dp83848_reset(ENET_Type *ptr); +void dp83848_basic_mode_default_config(ENET_Type *ptr, dp83848_config_t *config); +bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config); +void dp83848_read_status(ENET_Type *ptr); +void dp83848_control_config(ENET_Type *ptr); +void dp83867_ctl_config(ENET_Type *ptr); +void dp83867_bist_config(ENET_Type *ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* HPM_DP83848_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h new file mode 100644 index 0000000000..b8483f6374 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_RTL83848_REGS_H +#define HPM_RTL83848_REGS_H + + /* RTL Register Definitions */ +#define DP83848_REG_BMCR (0U) /* Basic Mode Control Register */ +#define DP83848_REG_BMSR (1U) /* Basic Mode Status Register */ +#define DP83848_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ +#define DP83848_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ +#define DP83848_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ +#define DP83848_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ +#define DP83848_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ +#define DP83848_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ +#define DP83848_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ +#define DP83848_REG_GBCR (9U) /* 1000Base-T Control Register */ +#define DP83848_REG_GBSR (10U) /* 1000Base-T Status Register */ + +#define DP83848_REG_MACR (13U) /* MMD Access Control Register */ +#define DP83848_REG_MAADR (14U) /* MMD Access Address Data Register */ +#define DP83848_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ +#define DP83848_REG_PHYCR (16U) /* PHY Specific Control Register */ +#define DP83848_REG_PHYSR (17U) /* PHY Specific Status Register */ +#define DP83848_REG_INER (18U) /* Interrupt Enable Register */ +#define DP83848_REG_INSR (19U) /* Interrupt Status Register */ +#define DP83848_REG_RXERC (24U) /* Receive Error Counter */ +#define DP83848_REG_PAGSEL (31U) /* Page Select Register */ + +/* RTL MMD Register Definitions */ +#define DP83848_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ +#define DP83848_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ +#define DP83848_MMD_REG_EEECR (20U) /* EEE Capability Register */ +#define DP83848_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ +#define DP83848_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ +#define DP83848_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ + +#define DP83867_REGCR_FUNCTION_ADDR (0 << 14) +#define DP83867_REGCR_FUNCTION_DATA (1 << 14) +#define DP83867_REGCR_DEVAD (0x1f) + +/* Bitfield definition for register: BMCR */ +/* + * Reset (RW) + * + * 1: PHY reset + * 0: Normal operation + * Register 0 (BMCR) and register 1 (BMSR) will return to default + * values after a software reset (set Bit15 to 1). + * This action may change the internal PHY state and the state of the + * physical link associated with the PHY. + */ +#define DP83848_BMCR_RESET_MASK (0x8000U) +#define DP83848_BMCR_RESET_SHIFT (15U) +#define DP83848_BMCR_RESET_SET(x) (((uint32_t)(x) << DP83848_BMCR_RESET_SHIFT) & DP83848_BMCR_RESET_MASK) +#define DP83848_BMCR_RESET_GET(x) (((uint32_t)(x) & DP83848_BMCR_RESET_MASK) >> DP83848_BMCR_RESET_SHIFT) + +/* + * Loopback (RW) + * + * Loopback Mode. + * 1: Enable PCS loopback mode + * 0: Disable PCS loopback mode + */ +#define DP83848_BMCR_LOOPBACK_MASK (0x4000U) +#define DP83848_BMCR_LOOPBACK_SHIFT (14U) +#define DP83848_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << DP83848_BMCR_LOOPBACK_SHIFT) & DP83848_BMCR_LOOPBACK_MASK) +#define DP83848_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & DP83848_BMCR_LOOPBACK_MASK) >> DP83848_BMCR_LOOPBACK_SHIFT) + +/* + * Speed[0] (RW) + * + * Speed Select Bit 0. + * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 + * determine device speed selection. + */ +#define DP83848_BMCR_SPEED0_MASK (0x2000U) +#define DP83848_BMCR_SPEED0_SHIFT (13U) +#define DP83848_BMCR_SPEED0_SET(x) (((uint32_t)(x) << DP83848_BMCR_SPEED0_SHIFT) & DP83848_BMCR_SPEED0_MASK) +#define DP83848_BMCR_SPEED0_GET(x) (((uint32_t)(x) & DP83848_BMCR_SPEED0_MASK) >> DP83848_BMCR_SPEED0_SHIFT) + +/* + * ANE (RW) + * + * Auto-Negotiation Enable. + * 1: Enable Auto-Negotiation + * 0: Disable Auto-Negotiation + */ +#define DP83848_BMCR_ANE_MASK (0x1000U) +#define DP83848_BMCR_ANE_SHIFT (12U) +#define DP83848_BMCR_ANE_SET(x) (((uint32_t)(x) << DP83848_BMCR_ANE_SHIFT) & DP83848_BMCR_ANE_MASK) +#define DP83848_BMCR_ANE_GET(x) (((uint32_t)(x) & DP83848_BMCR_ANE_MASK) >> DP83848_BMCR_ANE_SHIFT) + +/* + * PWD (RW) + * + * Power Down. + * 1: Power down (only Management Interface and logic are active; link + * is down) + * 0: Normal operation + */ +#define DP83848_BMCR_PWD_MASK (0x0800U) +#define DP83848_BMCR_PWD_SHIFT (11U) +#define DP83848_BMCR_PWD_SET(x) (((uint32_t)(x) << DP83848_BMCR_PWD_SHIFT) & DP83848_BMCR_PWD_MASK) +#define DP83848_BMCR_PWD_GET(x) (((uint32_t)(x) & DP83848_BMCR_PWD_MASK) >> DP83848_BMCR_PWD_SHIFT) + +/* + * Isolate (RW) + * + * Isolate. + * 1: RGMII/GMII interface is isolated; the serial management interface + * (MDC, MDIO) is still active. When this bit is asserted, the + * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and + * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. + * 0: Normal operation + */ +#define DP83848_BMCR_ISOLATE_MASK (0x0400U) +#define DP83848_BMCR_ISOLATE_SHIFT (10U) +#define DP83848_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << DP83848_BMCR_ISOLATE_SHIFT) & DP83848_BMCR_ISOLATE_MASK) +#define DP83848_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & DP83848_BMCR_ISOLATE_MASK) >> DP83848_BMCR_ISOLATE_SHIFT) + +/* + * Restart_AN (RW) + * + * Restart Auto-Negotiation. + * 1: Restart Auto-Negotiation + * 0: Normal operation + */ +#define DP83848_BMCR_RESTART_AN_MASK (0x0200U) +#define DP83848_BMCR_RESTART_AN_SHIFT (9U) +#define DP83848_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << DP83848_BMCR_RESTART_AN_SHIFT) & DP83848_BMCR_RESTART_AN_MASK) +#define DP83848_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & DP83848_BMCR_RESTART_AN_MASK) >> DP83848_BMCR_RESTART_AN_SHIFT) + +/* + * Duplex (RW) + * + * Duplex Mode. + * 1: Full Duplex operation + * 0: Half Duplex operation + * This bit is valid only in force mode, i.e., NWay is disabled. + */ +#define DP83848_BMCR_DUPLEX_MASK (0x0100U) +#define DP83848_BMCR_DUPLEX_SHIFT (8U) +#define DP83848_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << DP83848_BMCR_DUPLEX_SHIFT) & DP83848_BMCR_DUPLEX_MASK) +#define DP83848_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & DP83848_BMCR_DUPLEX_MASK) >> DP83848_BMCR_DUPLEX_SHIFT) + +/* + * Collision Test (RW) + * + * Collision Test. + * 1: Collision test enabled + * 0: Normal operation + * When set, this bit will cause the COL signal to be asserted in response + * to the assertion of TXEN within 512-bit times. The COL signal will be + * de-asserted within 4-bit times in response to the de-assertion of + * TXEN. + */ +#define DP83848_BMCR_COLLISION_TEST_MASK (0x0080U) +#define DP83848_BMCR_COLLISION_TEST_SHIFT (7U) +#define DP83848_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << DP83848_BMCR_COLLISION_TEST_SHIFT) & DP83848_BMCR_COLLISION_TEST_MASK) +#define DP83848_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & DP83848_BMCR_COLLISION_TEST_MASK) >> DP83848_BMCR_COLLISION_TEST_SHIFT) + +/* + * Speed[1] (RW) + * + * Speed Select Bit 1. + * Refer to bit 0.13. + */ +#define DP83848_BMCR_SPEED1_MASK (0x0040U) +#define DP83848_BMCR_SPEED1_SHIFT (6U) +#define DP83848_BMCR_SPEED1_SET(x) (((uint32_t)(x) << DP83848_BMCR_SPEED1_SHIFT) & DP83848_BMCR_SPEED1_MASK) +#define DP83848_BMCR_SPEED1_GET(x) (((uint32_t)(x) & DP83848_BMCR_SPEED1_MASK) >> DP83848_BMCR_SPEED1_SHIFT) + +/* Bitfield definition for register: PHYID1 */ +/* + * OUI_MSB (RO) + * + * Organizationally Unique Identifier Bit 3:18. + * Always 0000000000011100. + */ +#define DP83848_PHYID1_OUI_MSB_MASK (0xFFFFU) +#define DP83848_PHYID1_OUI_MSB_SHIFT (0U) +#define DP83848_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & DP83848_PHYID1_OUI_MSB_MASK) >> DP83848_PHYID1_OUI_MSB_SHIFT) + +/* Bitfield definition for register: PHYID2 */ +/* + * OUI_LSB (RO) + * + * Organizationally Unique Identifier Bit 19:24. + * Always 110010. + */ +#define DP83848_PHYID2_OUI_MSB_MASK (0xFC00U) +#define DP83848_PHYID2_OUI_MSB_SHIFT (10U) +#define DP83848_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & DP83848_PHYID2_OUI_MSB_MASK) >> DP83848_PHYID2_OUI_MSB_SHIFT) + +/* Bitfield definition for register: RGMIICTL */ +/* + * RGMII_EN (RW) + * + * RGMII Enable: + * 1 = Enable RGMII interface. + * 0 = Disable RGMII interface + */ +#define DP83867_RGMIICTL_RGMII_EN_MASK (0x80) +#define DP83867_RGMIICTL_RGMII_EN_SHIFT (7U) +#define DP83867_RGMIICTL_RGMII_EN_SET(x) (((uint32_t)(x) << DP83867_RGMIICTL_RGMII_EN_SHIFT) & DP83867_RGMIICTL_RGMII_EN_MASK) +#define DP83867_RGMIICTL_RGMII_EN_GET(x) (((uint32_t)(x) & DP83867_RGMIICTL_RGMII_EN_SHIFT) >> DP83867_RGMIICTL_RGMII_EN_MASK) +#endif /* HPM_DP83848_REGS_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c new file mode 100644 index 0000000000..dddf00eaac --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_enet_drv.h" +#include "hpm_dp83867_regs.h" +#include "hpm_dp83867.h" +#include "board.h" + +/*---------------------------------------------------------------------* + * Interal API + *---------------------------------------------------------------------*/ +bool dp83867_id_check(ENET_Type *ptr) +{ + uint16_t id1, id2; + + id1 = enet_read_phy(ptr, PHY_ADDR, DP83867_REG_PHYID1); + id2 = enet_read_phy(ptr, PHY_ADDR, DP83867_REG_PHYID2); + + if (DP83867_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && DP83867_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + return true; + } else { + return false; + } +} + +static void dp83867_phy_write_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data) +{ + /* set the control register for register address */ + enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_ADDR | DP83867_REGCR_DEVAD); + + /* write the specified register address */ + enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR, addr); + + /* set the control register for register data */ + enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_DATA | DP83867_REGCR_DEVAD); + + /* write the specified register data */ + enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR, data); +} + +static uint16_t dp83867_phy_read_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) +{ + /* set the control register for register address */ + enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_ADDR | DP83867_REGCR_DEVAD); + + /* write the specified register address */ + enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR, addr); + + /* set the control register for register data */ + enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_DATA | DP83867_REGCR_DEVAD); + + /* read the specified register data */ + return enet_read_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR); +} +/*---------------------------------------------------------------------* + * API + *---------------------------------------------------------------------*/ +uint16_t DP83867_REGister_check(ENET_Type *ptr, uint32_t addr) +{ + return enet_read_phy(ptr, PHY_ADDR, addr); +} + +void dp83867_reset(ENET_Type *ptr) +{ + uint16_t data; + + /* PHY reset */ + enet_write_phy(ptr, PHY_ADDR, DP83867_REG_BMCR, DP83867_BMCR_RESET_SET(1)); + + /* wait until the reset is completed */ + do { + data = enet_read_phy(ptr, PHY_ADDR, DP83867_REG_BMCR); + } while (DP83867_BMCR_RESET_GET(data)); +} + +void dp83867_basic_mode_default_config(ENET_Type *ptr, dp83867_config_t *config) +{ + config->loopback = 0; /* Enable PCS loopback mode */ + config->speed = 2; /* 3: reserved; 2: 1000mbps; 1: 100mbps; 0: 10mbps */ + config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + config->duplex_mode = 1; /* Full duplex mode */ +} + +bool dp83867_basic_mode_init(ENET_Type *ptr, dp83867_config_t *config) +{ + uint16_t para = 0; + + para |= DP83867_BMCR_RESET_SET(0) /* Normal operation */ + | DP83867_BMCR_LOOPBACK_SET(config->loopback) /* Configure PCS loopback mode */ + | DP83867_BMCR_ANE_SET(config->auto_negotiation) /* Configure Auto-Negotiation */ + | DP83867_BMCR_PWD_SET(0) /* Normal operation */ + | DP83867_BMCR_ISOLATE_SET(0) /* Normal operation */ + | DP83867_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ + | DP83867_BMCR_DUPLEX_SET(config->duplex_mode) /* Config duplex mode */ + | DP83867_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ + + if (config->auto_negotiation == false) { + para |= DP83867_BMCR_SPEED0_SET(config->speed) | DP83867_BMCR_SPEED1_SET(config->speed >> 1); + } + + /* check the id of dp83867 */ + if (dp83867_id_check(ptr) == false) { + return false; + } + + while (dp83867_get_phy_link_status(ptr) == 0) { + + } + + return true; +} + +void dp83867_init_auto_negotiation(void) +{ + +} + +uint16_t dp83867_get_phy_link_status(ENET_Type *ptr) +{ + return DP83867_BMSR_LINK_STATUS_GET(enet_read_phy(ptr, PHY_ADDR, DP83867_REG_BMSR)); +} + +void dp83867_set_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr, uint8_t delay) +{ + dp83867_phy_write_ext(ptr, phy_addr, DP83867_EXT_REG_RGMIIDCTL, delay); +} + +uint16_t dp83867_get_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr) +{ + uint16_t temp = 0; + + temp = dp83867_phy_read_ext(ptr, phy_addr, DP83867_EXT_REG_RGMIIDCTL); + + return temp; +} + +void dp83867_set_rx_clk_delay(ENET_Type *ptr) +{ + uint16_t para = 0; + + para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL); + dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL, para | 1); +} + +void dp83867_enable_crc_check(ENET_Type *ptr) +{ + uint16_t para = 0; + + para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RXFCFG); + dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RXFCFG, para | (1 << 7)); +} + +void dp83867_enable_rmii_inf(ENET_Type *ptr) +{ + uint16_t para = 0; + + para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL); + dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL, para | (1 << 7)); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h new file mode 100644 index 0000000000..5e6365951d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_DP83867_H +#define HPM_DP83867_H + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "stdint.h" + +/*---------------------------------------------------------------------* + * Macro Const Definitions + *---------------------------------------------------------------------*/ +#define PHY_ADDR (0U) +#define PHY_ID1 (0x2000U) +#define PHY_ID2 (0x28U) + +/*---------------------------------------------------------------------* + * Typedef Struct Declarations + *---------------------------------------------------------------------*/ +typedef struct { + bool loopback; + uint8_t speed; + bool auto_negotiation; + uint8_t duplex_mode; +} dp83867_config_t; + +typedef enum { + DP83867_RX_DELAY_0P25_NS = 0, + DP83867_RX_DELAY_0P50_NS, + DP83867_RX_DELAY_0P75_NS, + DP83867_RX_DELAY_1P00_NS, + DP83867_RX_DELAY_1P25_NS, + DP83867_RX_DELAY_1P50_NS, + DP83867_RX_DELAY_1P75_NS, + DP83867_RX_DELAY_2P00_NS, + DP83867_RX_DELAY_2P25_NS, + DP83867_RX_DELAY_2P50_NS, + DP83867_RX_DELAY_2P75_NS, + DP83867_RX_DELAY_3P00_NS, + DP83867_RX_DELAY_3P25_NS, + DP83867_RX_DELAY_3P50_NS, + DP83867_RX_DELAY_3P75_NS, + DP83867_RX_DELAY_4P00_NS +} dp83867_rgmii_rx_delay_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ +/*---------------------------------------------------------------------* + * Exported Functions + *---------------------------------------------------------------------*/ +uint16_t dp83867_check(ENET_Type *ptr, uint32_t addr); +void dp83867_reset(ENET_Type *ptr); +void dp83867_basic_mode_default_config(ENET_Type *ptr, dp83867_config_t *config); +bool dp83867_basic_mode_init(ENET_Type *ptr, dp83867_config_t *config); +void dp83867_read_status(ENET_Type *ptr); +void dp83867_control_config(ENET_Type *ptr); +void dp83867_ctl_config(ENET_Type *ptr); +void dp83867_bist_config(ENET_Type *ptr); +uint16_t dp83867_get_phy_link_status(ENET_Type *ptr); +void dp83867_set_rx_clk_delay(ENET_Type *ptr); +void dp83867_enable_crc_check(ENET_Type *ptr); +void dp83867_set_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr, uint8_t delay); +uint16_t dp83867_get_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr); +void dp83867_enable_rmii_inf(ENET_Type *ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* HPM_DP83867_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h new file mode 100644 index 0000000000..1c228f3a70 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_DP83867_REGS_H +#define HPM_DP83867_REGS_H + + /* Register Definitions */ +#define DP83867_REG_BMCR (0U) /* Basic Mode Control Register */ +#define DP83867_REG_BMSR (1U) /* Basic Mode Status Register */ +#define DP83867_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ +#define DP83867_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ +#define DP83867_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ +#define DP83867_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ +#define DP83867_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ +#define DP83867_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ +#define DP83867_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ +#define DP83867_REG_GBCR (9U) /* 1000Base-T Control Register */ +#define DP83867_REG_STATUS (10U) /* Status Register */ + +#define DP83867_REG_MACR (13U) /* MMD Access Control Register */ +#define DP83867_REG_MAADR (14U) /* MMD Access Address Data Register */ +#define DP83867_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ +#define DP83867_REG_PHYCR (16U) /* PHY Specific Control Register */ +#define DP83867_REG_PHYSR (17U) /* PHY Specific Status Register */ +#define DP83867_REG_INER (18U) /* Interrupt Enable Register */ +#define DP83867_REG_INSR (19U) /* Interrupt Status Register */ +#define DP83867_REG_RXERC (24U) /* Receive Error Counter */ +#define DP83867_REG_PAGSEL (31U) /* Page Select Register */ + +/* RTL MMD Register Definitions */ +#define DP83867_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ +#define DP83867_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ +#define DP83867_MMD_REG_EEECR (20U) /* EEE Capability Register */ +#define DP83867_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ +#define DP83867_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ +#define DP83867_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ + +/* DP83867 */ + +/* DP83867 Extended Registers */ +#define DP83867_EXT_REG_REGCR (0x000DU) /* Register Control Register */ +#define DP83867_EXT_REG_ADDAR (0x000EU) /* Address or Data Register */ +#define DP83867_EXT_REG_BISCR (0x0016U) /* BIST Control Register */ +#define DP83867_EXT_REG_CTRL (0x001fU) /* Control Register */ +#define DP83867_EXT_REG_RGMIICTL (0x0032U) /* RGMII Control Register */ +#define DP83867_EXT_REG_LOOPCR (0x00FEU) /* Loopback Configuration Register */ +#define DP83867_EXT_REG_RXFCFG (0x0134U) /* Recevie Configuration Register */ + +/* DP83867 extended registers */ +#define DP83867_EXT_REG_RGMIIDCTL (0x0086U) /* RGMII Delay Control */ + + +#define DP83867_REGCR_FUNCTION_ADDR (0 << 14) +#define DP83867_REGCR_FUNCTION_DATA (1 << 14) +#define DP83867_REGCR_DEVAD (0x1f) + +/* Bitfield definition for register: BMCR */ +/* + * Reset (RW) + * + * 1: PHY reset + * 0: Normal operation + * Register 0 (BMCR) and register 1 (BMSR) will return to default + * values after a software reset (set Bit15 to 1). + * This action may change the internal PHY state and the state of the + * physical link associated with the PHY. + */ +#define DP83867_BMCR_RESET_MASK (0x8000U) +#define DP83867_BMCR_RESET_SHIFT (15U) +#define DP83867_BMCR_RESET_SET(x) (((uint32_t)(x) << DP83867_BMCR_RESET_SHIFT) & DP83867_BMCR_RESET_MASK) +#define DP83867_BMCR_RESET_GET(x) (((uint32_t)(x) & DP83867_BMCR_RESET_MASK) >> DP83867_BMCR_RESET_SHIFT) + +/* + * Loopback (RW) + * + * Loopback Mode. + * 1: Enable PCS loopback mode + * 0: Disable PCS loopback mode + */ +#define DP83867_BMCR_LOOPBACK_MASK (0x4000U) +#define DP83867_BMCR_LOOPBACK_SHIFT (14U) +#define DP83867_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << DP83867_BMCR_LOOPBACK_SHIFT) & DP83867_BMCR_LOOPBACK_MASK) +#define DP83867_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & DP83867_BMCR_LOOPBACK_MASK) >> DP83867_BMCR_LOOPBACK_SHIFT) + +/* + * Speed[0] (RW) + * + * Speed Select Bit 0. + * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 + * determine device speed selection. + */ +#define DP83867_BMCR_SPEED0_MASK (0x2000U) +#define DP83867_BMCR_SPEED0_SHIFT (13U) +#define DP83867_BMCR_SPEED0_SET(x) (((uint32_t)(x) << DP83867_BMCR_SPEED0_SHIFT) & DP83867_BMCR_SPEED0_MASK) +#define DP83867_BMCR_SPEED0_GET(x) (((uint32_t)(x) & DP83867_BMCR_SPEED0_MASK) >> DP83867_BMCR_SPEED0_SHIFT) + +/* + * ANE (RW) + * + * Auto-Negotiation Enable. + * 1: Enable Auto-Negotiation + * 0: Disable Auto-Negotiation + */ +#define DP83867_BMCR_ANE_MASK (0x1000U) +#define DP83867_BMCR_ANE_SHIFT (12U) +#define DP83867_BMCR_ANE_SET(x) (((uint32_t)(x) << DP83867_BMCR_ANE_SHIFT) & DP83867_BMCR_ANE_MASK) +#define DP83867_BMCR_ANE_GET(x) (((uint32_t)(x) & DP83867_BMCR_ANE_MASK) >> DP83867_BMCR_ANE_SHIFT) + +/* + * PWD (RW) + * + * Power Down. + * 1: Power down (only Management Interface and logic are active; link + * is down) + * 0: Normal operation + */ +#define DP83867_BMCR_PWD_MASK (0x0800U) +#define DP83867_BMCR_PWD_SHIFT (11U) +#define DP83867_BMCR_PWD_SET(x) (((uint32_t)(x) << DP83867_BMCR_PWD_SHIFT) & DP83867_BMCR_PWD_MASK) +#define DP83867_BMCR_PWD_GET(x) (((uint32_t)(x) & DP83867_BMCR_PWD_MASK) >> DP83867_BMCR_PWD_SHIFT) + +/* + * Isolate (RW) + * + * Isolate. + * 1: RGMII/GMII interface is isolated; the serial management interface + * (MDC, MDIO) is still active. When this bit is asserted, the + * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and + * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. + * 0: Normal operation + */ +#define DP83867_BMCR_ISOLATE_MASK (0x0400U) +#define DP83867_BMCR_ISOLATE_SHIFT (10U) +#define DP83867_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << DP83867_BMCR_ISOLATE_SHIFT) & DP83867_BMCR_ISOLATE_MASK) +#define DP83867_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & DP83867_BMCR_ISOLATE_MASK) >> DP83867_BMCR_ISOLATE_SHIFT) + +/* + * Restart_AN (RW) + * + * Restart Auto-Negotiation. + * 1: Restart Auto-Negotiation + * 0: Normal operation + */ +#define DP83867_BMCR_RESTART_AN_MASK (0x0200U) +#define DP83867_BMCR_RESTART_AN_SHIFT (9U) +#define DP83867_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << DP83867_BMCR_RESTART_AN_SHIFT) & DP83867_BMCR_RESTART_AN_MASK) +#define DP83867_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & DP83867_BMCR_RESTART_AN_MASK) >> DP83867_BMCR_RESTART_AN_SHIFT) + +/* + * Duplex (RW) + * + * Duplex Mode. + * 1: Full Duplex operation + * 0: Half Duplex operation + * This bit is valid only in force mode, i.e., NWay is disabled. + */ +#define DP83867_BMCR_DUPLEX_MASK (0x0100U) +#define DP83867_BMCR_DUPLEX_SHIFT (8U) +#define DP83867_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << DP83867_BMCR_DUPLEX_SHIFT) & DP83867_BMCR_DUPLEX_MASK) +#define DP83867_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & DP83867_BMCR_DUPLEX_MASK) >> DP83867_BMCR_DUPLEX_SHIFT) + +/* + * Collision Test (RW) + * + * Collision Test. + * 1: Collision test enabled + * 0: Normal operation + * When set, this bit will cause the COL signal to be asserted in response + * to the assertion of TXEN within 512-bit times. The COL signal will be + * de-asserted within 4-bit times in response to the de-assertion of + * TXEN. + */ +#define DP83867_BMCR_COLLISION_TEST_MASK (0x0080U) +#define DP83867_BMCR_COLLISION_TEST_SHIFT (7U) +#define DP83867_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << DP83867_BMCR_COLLISION_TEST_SHIFT) & DP83867_BMCR_COLLISION_TEST_MASK) +#define DP83867_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & DP83867_BMCR_COLLISION_TEST_MASK) >> DP83867_BMCR_COLLISION_TEST_SHIFT) + +/* + * Speed[1] (RW) + * + * Speed Select Bit 1. + * Refer to bit 0.13. + */ +#define DP83867_BMCR_SPEED1_MASK (0x0040U) +#define DP83867_BMCR_SPEED1_SHIFT (6U) +#define DP83867_BMCR_SPEED1_SET(x) (((uint32_t)(x) << DP83867_BMCR_SPEED1_SHIFT) & DP83867_BMCR_SPEED1_MASK) +#define DP83867_BMCR_SPEED1_GET(x) (((uint32_t)(x) & DP83867_BMCR_SPEED1_MASK) >> DP83867_BMCR_SPEED1_SHIFT) + +/* Bitfield definition for register: BMSR */ + +/* + * Link Status: + * 1 = Valid link established. + * 0 = Link not established. + * The criteria for link validity is implementation specific. The + * occurrence of a link failure condition will causes the Link Status bit + * to clear. Once cleared, this bit may only be set by establishing a + * good link condition and a read through the management interface. +*/ +#define DP83867_BMSR_LINK_STATUS_MASK (0x0004U) +#define DP83867_BMSR_LINK_STATUS_SHIFT (2U) +#define DP83867_BMSR_LINK_STATUS_GET(x) (((uint32_t)(x) & DP83867_BMSR_LINK_STATUS_MASK) >> DP83867_BMSR_LINK_STATUS_SHIFT) + + + +/* Bitfield definition for register: PHYID1 */ +/* + * OUI_MSB (RO) + * + * Organizationally Unique Identifier Bit 3:18. + * Always 0000000000011100. + */ +#define DP83867_PHYID1_OUI_MSB_MASK (0xFFFFU) +#define DP83867_PHYID1_OUI_MSB_SHIFT (0U) +#define DP83867_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & DP83867_PHYID1_OUI_MSB_MASK) >> DP83867_PHYID1_OUI_MSB_SHIFT) + +/* Bitfield definition for register: PHYID2 */ +/* + * OUI_LSB (RO) + * + * Organizationally Unique Identifier Bit 19:24. + * Always 110010. + */ +#define DP83867_PHYID2_OUI_MSB_MASK (0xFC00U) +#define DP83867_PHYID2_OUI_MSB_SHIFT (10U) +#define DP83867_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & DP83867_PHYID2_OUI_MSB_MASK) >> DP83867_PHYID2_OUI_MSB_SHIFT) + +/* Bitfield definition for register: RGMIICTL */ +/* + * RGMII_EN (RW) + * + * RGMII Enable: + * 1 = Enable RGMII interface. + * 0 = Disable RGMII interface + */ +#define DP83867_RGMIICTL_RGMII_EN_MASK (0x80) +#define DP83867_RGMIICTL_RGMII_EN_SHIFT (7U) +#define DP83867_RGMIICTL_RGMII_EN_SET(x) (((uint32_t)(x) << DP83867_RGMIICTL_RGMII_EN_SHIFT) & DP83867_RGMIICTL_RGMII_EN_MASK) +#define DP83867_RGMIICTL_RGMII_EN_GET(x) (((uint32_t)(x) & DP83867_RGMIICTL_RGMII_EN_SHIFT) >> DP83867_RGMIICTL_RGMII_EN_MASK) +#endif /* HPM_DP83867_REGS_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h new file mode 100644 index 0000000000..a35bb20547 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ENET_PHY_COMMON_H +#define HPM_ENET_PHY_COMMON_H + +typedef enum { + enet_port_speed_10mbps = 0, + enet_port_speed_100msbs, + enet_port_speed_1000mbps +} enet_port_speed_t; + + +#endif \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c new file mode 100644 index 0000000000..0293637792 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_enet_drv.h" +#include "hpm_rtl8201_regs.h" +#include "hpm_rtl8201.h" +#include "board.h" + +/*---------------------------------------------------------------------* + * Internal API + *---------------------------------------------------------------------*/ +static bool rtl8201_id_check(ENET_Type *ptr) +{ + uint16_t id1, id2; + + id1 = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_PHYID1); + id2 = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_PHYID2); + + if (RTL8201_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && RTL8201_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + return true; + } else { + return false; + } +} + +/*---------------------------------------------------------------------* + * API + *---------------------------------------------------------------------*/ +uint16_t rtl8201_register_check(ENET_Type *ptr, uint32_t addr) +{ + return enet_read_phy(ptr, PHY_ADDR, addr); +} + +void rtl8201_reset(ENET_Type *ptr) +{ + uint16_t data; + + /* PHY reset */ + enet_write_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR, RTL8201_BMCR_RESET_SET(1)); + + /* wait until the reset is completed */ + do { + data = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR); + } while (RTL8201_BMCR_RESET_GET(data)); +} + +void rtl8201_basic_mode_default_config(ENET_Type *ptr, rtl8201_config_t *config) +{ + config->loopback = 1; /* Enable PCS loopback mode */ + config->speed = 2; /* reserved:3/2; 100mbps: 1; 10mbps: 0 */ + config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + config->duplex_mode = 1; /* Full duplex mode */ +} + +bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config) +{ + uint16_t para = 0; + + para |= RTL8201_BMCR_RESET_SET(0) /* Normal operation */ + | RTL8201_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ + | RTL8201_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ + | RTL8201_BMCR_PWD_SET(0) /* Normal operation */ + | RTL8201_BMCR_ISOLATE_SET(0) /* Normal operation */ + | RTL8201_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ + | RTL8201_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ + + if (config->auto_negotiation == 0) { + para |= RTL8201_BMCR_SPEED0_SET(config->speed) | RTL8201_BMCR_SPEED1_SET(config->speed >> 1); + } + + /* check the id of rtl8201 */ + if (rtl8201_id_check(ptr) == false) { + return false; + } + + para = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR) & ~RTL8201_BMCR_SPEED0_MASK; + enet_write_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR, para); + + /* select page 7 */ + enet_write_phy(ptr, PHY_ADDR, 31, 7); + para = enet_read_phy(ptr, PHY_ADDR, 16); + para |= 1 << 12; /* set txc as input mode */ + enet_write_phy(ptr, PHY_ADDR, 16, para); + + return true; +} + + +void rtl8201_init_auto_negotiation(void) +{ +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h new file mode 100644 index 0000000000..3359412ffe --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_rtl8201_H +#define HPM_rtl8201_H + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "stdint.h" + +/*---------------------------------------------------------------------* + * Macro Const Definitions + *---------------------------------------------------------------------*/ +#define PHY_ADDR (2U) +#define PHY_ID1 (0x001CU) +#define PHY_ID2 (0x32U) + +/*---------------------------------------------------------------------* + * Typedef Struct Declarations + *---------------------------------------------------------------------*/ +typedef struct { + bool loopback; + uint8_t speed; + bool auto_negotiation; + uint8_t duplex_mode; +} rtl8201_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ +/*---------------------------------------------------------------------* + * Exported Functions + *---------------------------------------------------------------------*/ +uint16_t rtl8201_check(ENET_Type *ptr, uint32_t addr); +void rtl8201_reset(ENET_Type *ptr); +void rtl8201_basic_mode_default_config(ENET_Type *ptr, rtl8201_config_t *config); +bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config); +void rtl8201_read_status(ENET_Type *ptr); +void rtl8201_control_config(ENET_Type *ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* HPM_rtl8201_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h new file mode 100644 index 0000000000..436ac80404 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_RTL8201_REGS_H +#define HPM_RTL8201_REGS_H + + /* RTL Register Definitions */ +#define RTL8201_REG_BMCR (0U) /* Basic Mode Control Register */ +#define RTL8201_REG_BMSR (1U) /* Basic Mode Status Register */ +#define RTL8201_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ +#define RTL8201_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ +#define RTL8201_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ +#define RTL8201_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ +#define RTL8201_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ + +#define RTL8201_REG_RXERC (24U) /* Receive Error Counter */ +#define RTL8201_REG_FB_LP (28U) /* Fiber Mode and Loopback Register */ +#define RTL8201_REG_PAGSEL (31U) /* Page Select Register */ + +/* RTL MMD Register Definitions */ +#define RTL8201_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ +#define RTL8201_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ +#define RTL8201_MMD_REG_EEECR (20U) /* EEE Capability Register */ +#define RTL8201_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ +#define RTL8201_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ +#define RTL8201_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ + +/* Page 0 Registers */ +#define RTL8201_REG_MACR (13U) /* MMD Access Control Register */ +#define RTL8201_REG_MAADR (14U) /* MMD Access Address Data Register */ + +/* Bitfiled definitions of Register: MACR */ +#define RTL8201_REGCR_FUNCTION_ADDR (0 << 14) +#define RTL8201_REGCR_FUNCTION_DATA (1 << 14) +#define RTL8201_REGCR_DEVAD (0x1f) + +/* Bitfield definition for register: BMCR */ +/* + * Reset (RW) + * + * 1: PHY reset + * 0: Normal operation + * Register 0 (BMCR) and register 1 (BMSR) will return to default + * values after a software reset (set Bit15 to 1). + * This action may change the internal PHY state and the state of the + * physical link associated with the PHY. + */ +#define RTL8201_BMCR_RESET_MASK (0x8000U) +#define RTL8201_BMCR_RESET_SHIFT (15U) +#define RTL8201_BMCR_RESET_SET(x) (((uint32_t)(x) << RTL8201_BMCR_RESET_SHIFT) & RTL8201_BMCR_RESET_MASK) +#define RTL8201_BMCR_RESET_GET(x) (((uint32_t)(x) & RTL8201_BMCR_RESET_MASK) >> RTL8201_BMCR_RESET_SHIFT) + +/* + * Loopback (RW) + * + * Loopback Mode. + * 1: Enable PCS loopback mode + * 0: Disable PCS loopback mode + */ +#define RTL8201_BMCR_LOOPBACK_MASK (0x4000U) +#define RTL8201_BMCR_LOOPBACK_SHIFT (14U) +#define RTL8201_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << RTL8201_BMCR_LOOPBACK_SHIFT) & RTL8201_BMCR_LOOPBACK_MASK) +#define RTL8201_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & RTL8201_BMCR_LOOPBACK_MASK) >> RTL8201_BMCR_LOOPBACK_SHIFT) + +/* + * Speed[0] (RW) + * + * Speed Select Bit 0. + * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 + * determine device speed selection. + */ +#define RTL8201_BMCR_SPEED0_MASK (0x2000U) +#define RTL8201_BMCR_SPEED0_SHIFT (13U) +#define RTL8201_BMCR_SPEED0_SET(x) (((uint32_t)(x) << RTL8201_BMCR_SPEED0_SHIFT) & RTL8201_BMCR_SPEED0_MASK) +#define RTL8201_BMCR_SPEED0_GET(x) (((uint32_t)(x) & RTL8201_BMCR_SPEED0_MASK) >> RTL8201_BMCR_SPEED0_SHIFT) + +/* + * ANE (RW) + * + * Auto-Negotiation Enable. + * 1: Enable Auto-Negotiation + * 0: Disable Auto-Negotiation + */ +#define RTL8201_BMCR_ANE_MASK (0x1000U) +#define RTL8201_BMCR_ANE_SHIFT (12U) +#define RTL8201_BMCR_ANE_SET(x) (((uint32_t)(x) << RTL8201_BMCR_ANE_SHIFT) & RTL8201_BMCR_ANE_MASK) +#define RTL8201_BMCR_ANE_GET(x) (((uint32_t)(x) & RTL8201_BMCR_ANE_MASK) >> RTL8201_BMCR_ANE_SHIFT) + +/* + * PWD (RW) + * + * Power Down. + * 1: Power down (only Management Interface and logic are active; link + * is down) + * 0: Normal operation + */ +#define RTL8201_BMCR_PWD_MASK (0x0800U) +#define RTL8201_BMCR_PWD_SHIFT (11U) +#define RTL8201_BMCR_PWD_SET(x) (((uint32_t)(x) << RTL8201_BMCR_PWD_SHIFT) & RTL8201_BMCR_PWD_MASK) +#define RTL8201_BMCR_PWD_GET(x) (((uint32_t)(x) & RTL8201_BMCR_PWD_MASK) >> RTL8201_BMCR_PWD_SHIFT) + +/* + * Isolate (RW) + * + * Isolate. + * 1: RGMII/GMII interface is isolated; the serial management interface + * (MDC, MDIO) is still active. When this bit is asserted, the + * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and + * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. + * 0: Normal operation + */ +#define RTL8201_BMCR_ISOLATE_MASK (0x0400U) +#define RTL8201_BMCR_ISOLATE_SHIFT (10U) +#define RTL8201_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << RTL8201_BMCR_ISOLATE_SHIFT) & RTL8201_BMCR_ISOLATE_MASK) +#define RTL8201_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & RTL8201_BMCR_ISOLATE_MASK) >> RTL8201_BMCR_ISOLATE_SHIFT) + +/* + * Restart_AN (RW) + * + * Restart Auto-Negotiation. + * 1: Restart Auto-Negotiation + * 0: Normal operation + */ +#define RTL8201_BMCR_RESTART_AN_MASK (0x0200U) +#define RTL8201_BMCR_RESTART_AN_SHIFT (9U) +#define RTL8201_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << RTL8201_BMCR_RESTART_AN_SHIFT) & RTL8201_BMCR_RESTART_AN_MASK) +#define RTL8201_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & RTL8201_BMCR_RESTART_AN_MASK) >> RTL8201_BMCR_RESTART_AN_SHIFT) + +/* + * Duplex (RW) + * + * Duplex Mode. + * 1: Full Duplex operation + * 0: Half Duplex operation + * This bit is valid only in force mode, i.e., NWay is disabled. + */ +#define RTL8201_BMCR_DUPLEX_MASK (0x0100U) +#define RTL8201_BMCR_DUPLEX_SHIFT (8U) +#define RTL8201_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << RTL8201_BMCR_DUPLEX_SHIFT) & RTL8201_BMCR_DUPLEX_MASK) +#define RTL8201_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & RTL8201_BMCR_DUPLEX_MASK) >> RTL8201_BMCR_DUPLEX_SHIFT) + +/* + * Collision Test (RW) + * + * Collision Test. + * 1: Collision test enabled + * 0: Normal operation + * When set, this bit will cause the COL signal to be asserted in response + * to the assertion of TXEN within 512-bit times. The COL signal will be + * de-asserted within 4-bit times in response to the de-assertion of + * TXEN. + */ +#define RTL8201_BMCR_COLLISION_TEST_MASK (0x0080U) +#define RTL8201_BMCR_COLLISION_TEST_SHIFT (7U) +#define RTL8201_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << RTL8201_BMCR_COLLISION_TEST_SHIFT) & RTL8201_BMCR_COLLISION_TEST_MASK) +#define RTL8201_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & RTL8201_BMCR_COLLISION_TEST_MASK) >> RTL8201_BMCR_COLLISION_TEST_SHIFT) + +/* + * Speed[1] (RW) + * + * Speed Select Bit 1. + * Refer to bit 0.13. + */ +#define RTL8201_BMCR_SPEED1_MASK (0x0040U) +#define RTL8201_BMCR_SPEED1_SHIFT (6U) +#define RTL8201_BMCR_SPEED1_SET(x) (((uint32_t)(x) << RTL8201_BMCR_SPEED1_SHIFT) & RTL8201_BMCR_SPEED1_MASK) +#define RTL8201_BMCR_SPEED1_GET(x) (((uint32_t)(x) & RTL8201_BMCR_SPEED1_MASK) >> RTL8201_BMCR_SPEED1_SHIFT) + +/* Bitfield definition for register: PHYID1 */ +/* + * OUI_MSB (RO) + * + * Organizationally Unique Identifier Bit 3:18. + * Always 0000000000011100. + */ +#define RTL8201_PHYID1_OUI_MSB_MASK (0xFFFFU) +#define RTL8201_PHYID1_OUI_MSB_SHIFT (0U) +#define RTL8201_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8201_PHYID1_OUI_MSB_MASK) >> RTL8201_PHYID1_OUI_MSB_SHIFT) + +/* Bitfield definition for register: PHYID2 */ +/* + * OUI_LSB (RO) + * + * Organizationally Unique Identifier Bit 19:24. + * Always 110010. + */ +#define RTL8201_PHYID2_OUI_MSB_MASK (0xFC00U) +#define RTL8201_PHYID2_OUI_MSB_SHIFT (10U) +#define RTL8201_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8201_PHYID2_OUI_MSB_MASK) >> RTL8201_PHYID2_OUI_MSB_SHIFT) + +#endif /* HPM_RTL8201_REGS_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c new file mode 100644 index 0000000000..09094ca2bf --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_enet_drv.h" +#include "hpm_rtl8211_regs.h" +#include "hpm_rtl8211.h" +#include "board.h" + +/*---------------------------------------------------------------------* + * Interal API + *---------------------------------------------------------------------*/ +static bool rtl8211_id_check(ENET_Type *ptr) +{ + uint16_t id1, id2; + + id1 = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYID1); + id2 = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYID2); + + if (RTL8211_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && RTL8211_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + return true; + } else { + return false; + } +} + +/*---------------------------------------------------------------------* + * API + *---------------------------------------------------------------------*/ +uint16_t rtl8211_register_check(ENET_Type *ptr, uint32_t addr) +{ + return enet_read_phy(ptr, PHY_ADDR, addr); +} + +void rtl8211_reset(ENET_Type *ptr) +{ + uint16_t data; + + /* PHY reset */ + enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR, RTL8211_BMCR_RESET_SET(1)); + + /* wait until the reset is completed */ + do { + data = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR); + } while (RTL8211_BMCR_RESET_GET(data)); +} + +void rtl8211_basic_mode_default_config(ENET_Type *ptr, rtl8211_config_t *config) +{ + config->loopback = 0; /* Enable PCS loopback mode */ + config->speed = 1; /* reserved:3/2; 100mbps: 1; 10mbps: 0 */ + config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + config->duplex_mode = 1; /* Full duplex mode */ +} + +bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config) +{ + uint16_t para = 0; + + para |= RTL8211_BMCR_RESET_SET(0) /* Normal operation */ + | RTL8211_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ + | RTL8211_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ + | RTL8211_BMCR_PWD_SET(0) /* Normal operation */ + | RTL8211_BMCR_ISOLATE_SET(0) /* Normal operation */ + | RTL8211_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ + | RTL8211_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ + + if (config->auto_negotiation == 0) { + para |= RTL8211_BMCR_SPEED0_SET(config->speed) | RTL8211_BMCR_SPEED1_SET(config->speed >> 1); + } + + enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR, para); + + /* check the id of rtl8211 */ + if (rtl8211_id_check(ptr) == false) { + return false; + } + + return true; +} + +void rtl8211_auto_negotiation_init(void) +{ + /* TODO */ +} + + +void rtl8211_read_status(ENET_Type *ptr) +{ + uint16_t status; + + status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_BMSR); + printf("BMSR: %08x\n", status); + status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_GBSR); + printf("GBSR: %08x\n", status); + status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_GBESR); + printf("GBESR: %08x\n", status); + status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYSR); + printf("PHYSR: %08x\n", status); + status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_RXERC); + printf("RXERC: %08x\n", status); + + status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR); + printf("PHYCR, %x\n", status); +} + +void rtl8211_control_config(ENET_Type *ptr) +{ + uint16_t para = 0; + + para = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR) | (1 << 10); + + enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR, para); + +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h new file mode 100644 index 0000000000..5b20857335 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_RTL8211_H +#define HPM_RTL8211_H + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "stdint.h" + +/*---------------------------------------------------------------------* + * Macro Const Definitions + *---------------------------------------------------------------------*/ +#define PHY_ADDR (2U) +#define PHY_ID1 (0x001CU) +#define PHY_ID2 (0x32U) + +/*---------------------------------------------------------------------* + * Typedef Struct Declarations + *---------------------------------------------------------------------*/ +typedef struct { + bool loopback; + uint8_t speed; + bool auto_negotiation; + uint8_t duplex_mode; +} rtl8211_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ +/*---------------------------------------------------------------------* + * Exported Functions + *---------------------------------------------------------------------*/ +uint16_t rtl8211_check(ENET_Type *ptr, uint32_t addr); +void rtl8211_reset(ENET_Type *ptr); +void rtl8211_basic_mode_default_config(ENET_Type *ptr, rtl8211_config_t *config); +bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config); +void rtl8211_read_status(ENET_Type *ptr); +void rtl8211_control_config(ENET_Type *ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* HPM_RTL8211_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h new file mode 100644 index 0000000000..567c76e798 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_RTL8211_REGS_H +#define HPM_RTL8211_REGS_H + + /* RTL Register Definitions */ +#define RTL8211_REG_BMCR (0U) /* Basic Mode Control Register */ +#define RTL8211_REG_BMSR (1U) /* Basic Mode Status Register */ +#define RTL8211_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ +#define RTL8211_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ +#define RTL8211_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ +#define RTL8211_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ +#define RTL8211_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ +#define RTL8211_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ +#define RTL8211_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ +#define RTL8211_REG_GBCR (9U) /* 1000Base-T Control Register */ +#define RTL8211_REG_GBSR (10U) /* 1000Base-T Status Register */ + +#define RTL8211_REG_MACR (13U) /* MMD Access Control Register */ +#define RTL8211_REG_MAADR (14U) /* MMD Access Address Data Register */ +#define RTL8211_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ +#define RTL8211_REG_PHYCR (16U) /* PHY Specific Control Register */ +#define RTL8211_REG_PHYSR (17U) /* PHY Specific Status Register */ +#define RTL8211_REG_INER (18U) /* Interrupt Enable Register */ +#define RTL8211_REG_INSR (19U) /* Interrupt Status Register */ +#define RTL8211_REG_RXERC (24U) /* Receive Error Counter */ +#define RTL8211_REG_PAGSEL (31U) /* Page Select Register */ + +/* RTL MMD Register Definitions */ +#define RTL8211_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ +#define RTL8211_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ +#define RTL8211_MMD_REG_EEECR (20U) /* EEE Capability Register */ +#define RTL8211_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ +#define RTL8211_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ +#define RTL8211_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ + +/* Bitfield definition for register: BMCR */ +/* + * Reset (RW) + * + * 1: PHY reset + * 0: Normal operation + * Register 0 (BMCR) and register 1 (BMSR) will return to default + * values after a software reset (set Bit15 to 1). + * This action may change the internal PHY state and the state of the + * physical link associated with the PHY. + */ +#define RTL8211_BMCR_RESET_MASK (0x8000U) +#define RTL8211_BMCR_RESET_SHIFT (15U) +#define RTL8211_BMCR_RESET_SET(x) (((uint32_t)(x) << RTL8211_BMCR_RESET_SHIFT) & RTL8211_BMCR_RESET_MASK) +#define RTL8211_BMCR_RESET_GET(x) (((uint32_t)(x) & RTL8211_BMCR_RESET_MASK) >> RTL8211_BMCR_RESET_SHIFT) + +/* + * Loopback (RW) + * + * Loopback Mode. + * 1: Enable PCS loopback mode + * 0: Disable PCS loopback mode + */ +#define RTL8211_BMCR_LOOPBACK_MASK (0x4000U) +#define RTL8211_BMCR_LOOPBACK_SHIFT (14U) +#define RTL8211_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << RTL8211_BMCR_LOOPBACK_SHIFT) & RTL8211_BMCR_LOOPBACK_MASK) +#define RTL8211_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & RTL8211_BMCR_LOOPBACK_MASK) >> RTL8211_BMCR_LOOPBACK_SHIFT) + +/* + * Speed[0] (RW) + * + * Speed Select Bit 0. + * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 + * determine device speed selection. + */ +#define RTL8211_BMCR_SPEED0_MASK (0x2000U) +#define RTL8211_BMCR_SPEED0_SHIFT (13U) +#define RTL8211_BMCR_SPEED0_SET(x) (((uint32_t)(x) << RTL8211_BMCR_SPEED0_SHIFT) & RTL8211_BMCR_SPEED0_MASK) +#define RTL8211_BMCR_SPEED0_GET(x) (((uint32_t)(x) & RTL8211_BMCR_SPEED0_MASK) >> RTL8211_BMCR_SPEED0_SHIFT) + +/* + * ANE (RW) + * + * Auto-Negotiation Enable. + * 1: Enable Auto-Negotiation + * 0: Disable Auto-Negotiation + */ +#define RTL8211_BMCR_ANE_MASK (0x1000U) +#define RTL8211_BMCR_ANE_SHIFT (12U) +#define RTL8211_BMCR_ANE_SET(x) (((uint32_t)(x) << RTL8211_BMCR_ANE_SHIFT) & RTL8211_BMCR_ANE_MASK) +#define RTL8211_BMCR_ANE_GET(x) (((uint32_t)(x) & RTL8211_BMCR_ANE_MASK) >> RTL8211_BMCR_ANE_SHIFT) + +/* + * PWD (RW) + * + * Power Down. + * 1: Power down (only Management Interface and logic are active; link + * is down) + * 0: Normal operation + */ +#define RTL8211_BMCR_PWD_MASK (0x0800U) +#define RTL8211_BMCR_PWD_SHIFT (11U) +#define RTL8211_BMCR_PWD_SET(x) (((uint32_t)(x) << RTL8211_BMCR_PWD_SHIFT) & RTL8211_BMCR_PWD_MASK) +#define RTL8211_BMCR_PWD_GET(x) (((uint32_t)(x) & RTL8211_BMCR_PWD_MASK) >> RTL8211_BMCR_PWD_SHIFT) + +/* + * Isolate (RW) + * + * Isolate. + * 1: RGMII/GMII interface is isolated; the serial management interface + * (MDC, MDIO) is still active. When this bit is asserted, the + * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and + * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. + * 0: Normal operation + */ +#define RTL8211_BMCR_ISOLATE_MASK (0x0400U) +#define RTL8211_BMCR_ISOLATE_SHIFT (10U) +#define RTL8211_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << RTL8211_BMCR_ISOLATE_SHIFT) & RTL8211_BMCR_ISOLATE_MASK) +#define RTL8211_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & RTL8211_BMCR_ISOLATE_MASK) >> RTL8211_BMCR_ISOLATE_SHIFT) + +/* + * Restart_AN (RW) + * + * Restart Auto-Negotiation. + * 1: Restart Auto-Negotiation + * 0: Normal operation + */ +#define RTL8211_BMCR_RESTART_AN_MASK (0x0200U) +#define RTL8211_BMCR_RESTART_AN_SHIFT (9U) +#define RTL8211_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << RTL8211_BMCR_RESTART_AN_SHIFT) & RTL8211_BMCR_RESTART_AN_MASK) +#define RTL8211_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & RTL8211_BMCR_RESTART_AN_MASK) >> RTL8211_BMCR_RESTART_AN_SHIFT) + +/* + * Duplex (RW) + * + * Duplex Mode. + * 1: Full Duplex operation + * 0: Half Duplex operation + * This bit is valid only in force mode, i.e., NWay is disabled. + */ +#define RTL8211_BMCR_DUPLEX_MASK (0x0100U) +#define RTL8211_BMCR_DUPLEX_SHIFT (8U) +#define RTL8211_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << RTL8211_BMCR_DUPLEX_SHIFT) & RTL8211_BMCR_DUPLEX_MASK) +#define RTL8211_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & RTL8211_BMCR_DUPLEX_MASK) >> RTL8211_BMCR_DUPLEX_SHIFT) + +/* + * Collision Test (RW) + * + * Collision Test. + * 1: Collision test enabled + * 0: Normal operation + * When set, this bit will cause the COL signal to be asserted in response + * to the assertion of TXEN within 512-bit times. The COL signal will be + * de-asserted within 4-bit times in response to the de-assertion of + * TXEN. + */ +#define RTL8211_BMCR_COLLISION_TEST_MASK (0x0080U) +#define RTL8211_BMCR_COLLISION_TEST_SHIFT (7U) +#define RTL8211_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << RTL8211_BMCR_COLLISION_TEST_SHIFT) & RTL8211_BMCR_COLLISION_TEST_MASK) +#define RTL8211_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & RTL8211_BMCR_COLLISION_TEST_MASK) >> RTL8211_BMCR_COLLISION_TEST_SHIFT) + +/* + * Speed[1] (RW) + * + * Speed Select Bit 1. + * Refer to bit 0.13. + */ +#define RTL8211_BMCR_SPEED1_MASK (0x0040U) +#define RTL8211_BMCR_SPEED1_SHIFT (6U) +#define RTL8211_BMCR_SPEED1_SET(x) (((uint32_t)(x) << RTL8211_BMCR_SPEED1_SHIFT) & RTL8211_BMCR_SPEED1_MASK) +#define RTL8211_BMCR_SPEED1_GET(x) (((uint32_t)(x) & RTL8211_BMCR_SPEED1_MASK) >> RTL8211_BMCR_SPEED1_SHIFT) + +/* Bitfield definition for register: PHYID1 */ +/* + * OUI_MSB (RO) + * + * Organizationally Unique Identifier Bit 3:18. + * Always 0000000000011100. + */ +#define RTL8211_PHYID1_OUI_MSB_MASK (0xFFFFU) +#define RTL8211_PHYID1_OUI_MSB_SHIFT (0U) +#define RTL8211_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8211_PHYID1_OUI_MSB_MASK) >> RTL8211_PHYID1_OUI_MSB_SHIFT) + +/* Bitfield definition for register: PHYID2 */ +/* + * OUI_LSB (RO) + * + * Organizationally Unique Identifier Bit 19:24. + * Always 110010. + */ +#define RTL8211_PHYID2_OUI_MSB_MASK (0xFC00U) +#define RTL8211_PHYID2_OUI_MSB_SHIFT (10U) +#define RTL8211_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8211_PHYID2_OUI_MSB_MASK) >> RTL8211_PHYID2_OUI_MSB_SHIFT) + +#endif /* HPM_RTL8211_REGS_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h new file mode 100644 index 0000000000..f50cf48ec0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h @@ -0,0 +1,446 @@ +// +// Created by hpm15 on 3/11/21. +// + +#ifndef SFDP_DEF_H +#define SFDP_DEF_H + +#include +#include "hpm_common.h" + +//! @brief Commands for probing the FLASH device +#define kSerialFlash_ReadSFDP (0x5AU) +#define kSerialFlash_ReadManufacturerId (0x9FU) + +//!@brief SFDP related definitions +#define SFDP_SIGNATURE (0x50444653UL) /* ASCII: SFDP */ +#define kSfdp_Version_Major_1_0 (1U) +#define kSfdp_Version_Minor_0 (0U) // JESD216 +#define kSfdp_Version_Minor_A (5U) // JESD216A +#define kSfdp_Version_Minor_B (6U) // JESD216B +#define kSfdp_Version_Minor_C (7U) // JESD216C +#define kSfdp_Version_Minor_D (8U) // JESD216D +#define kSfdp_BasicProtocolTableSize_Rev0 (36U) +#define kSfdp_BasicProtocolTableSize_RevA (64U) +#define kSfdp_BasicProtocolTableSize_RevB kSfdp_BasicProtocolTableSize_RevA +#define kSfdp_BasicProtocolTableSize_RevC (80U) +#define kSfdp_BasicProtocolTableSize_RevD kSfdp_BasicProtocolTableSize_RevC + +typedef union _sfdp_header +{ + uint32_t words[2]; + struct + { + uint32_t signature; + uint8_t minor_rev; + uint8_t major_rev; + uint8_t param_hdr_num; + uint8_t sfdp_access_protocol; // Defined in JESD216C, reserved for older version + }; + +} sfdp_header_t; + +//!@brief SFDP parameter Type ID definitions +#define kParameterID_BasicSpiProtocol (0xFF00U) +// New Table added in JESD216B +#define kParameterID_SectorMap (0xFF81U) +#define kParameterID_4ByteAddressInstructionTable (0xFF84U) +// New Table added in JESD216C +#define kParameterID_xSpiProfile1_0 (0xFF05U) +#define kParameterID_xSpiOrofile2_0 (0xFF06U) +#define kParameterID_StaCtrlCfgRegMap (0xFF87U) +#define kParameterID_OpiEnableSeq (0xFF09U) +#define kParameterID_CmdSeqChangeToOctalDdr (0xFF0AU) + +#define kNorFlash_AddressBits_3B (0U) +#define kNorFlash_AddressBits_3B_4B (1U) +#define kNorFlash_AddressBits_4B (2U) + +#define kCommandExtensionSameAsCommand (0U) +#define kCommandExtensionInverseOfCommand (1U) +#define kCommandAndCommandExtension16BitWord (2U) + +//!@brief Supported methods to enter 8-8-8 mode from 1-1-1 mode, More details please refer to JESD216C/D +#define kEnterOctalMode_Option0 HPM_BITSMASK(1U, 1) +#define kEnterOctalMode_Option1 HPM_BITSMASK(1U, 2) + +//!@brief SFDP Parameter Header, see JESD216D doc for more details +typedef union _sfdp_parameter_header +{ + uint32_t words[2]; + struct + { + uint8_t parameter_id_lsb; + uint8_t minor_rev; + uint8_t major_rev; + uint8_t table_length_in_32bit; + uint8_t parameter_table_pointer[3]; + uint8_t parameter_id_msb; + }; + +} sfdp_parameter_header_t; + +//!@brief Basic Flash Parameter Table, see JESD216D doc for more details +typedef union _jedec_flash_param_table +{ + uint32_t words[20]; + struct + { + struct + { + uint32_t erase_size : 2; + uint32_t write_granularity : 1; + uint32_t reserved0 : 2; + uint32_t unused0 : 3; + uint32_t erase4k_inst : 8; + uint32_t support_1_1_2_fast_read : 1; + uint32_t address_bits : 2; + uint32_t support_ddr_clocking : 1; + uint32_t support_1_2_2_fast_read : 1; + uint32_t supports_1_4_4_fast_read : 1; + uint32_t support_1_1_4_fast_read : 1; + uint32_t unused1 : 9; + } misc; // 1st word + uint32_t flash_density; // 2nd word + struct + { + uint32_t dummy_clocks_1_4_4_read : 5; + uint32_t mode_clocks_1_4_4_read : 3; + uint32_t inst_1_4_4_read : 8; + uint32_t dummy_clocks_1_1_4_read : 5; + uint32_t mode_clocks_1_1_4_read : 3; + uint32_t inst_1_1_4_read : 8; + } read_1_4_info; // 3rd word + struct + { + uint32_t dummy_clocks_1_2_2_read : 5; + uint32_t mode_clocks_1_2_2_read : 3; + uint32_t inst_1_2_2_read : 8; + uint32_t dummy_clocks_1_1_2_read : 5; + uint32_t mode_clocks_1_1_2_read : 3; + uint32_t inst_1_1_2_read : 8; + } read_1_2_info; // 4th word + + struct + { + uint32_t support_2_2_2_fast_read : 1; + uint32_t reserved0 : 3; + uint32_t support_4_4_4_fast_read : 1; + uint32_t reserved1 : 27; + } read_22_44_check; // 5th word + + struct + { + uint32_t reserved0 : 16; + uint32_t dummy_clocks_2_2_2_read : 5; + uint32_t mode_clocks_2_2_2_read : 3; + uint32_t inst_2_2_2_read : 8; + } read_2_2_info; // 6th word + struct + { + uint32_t reserved0 : 16; + uint32_t dummy_clocks_4_4_4_read : 5; + uint32_t mode_clocks_4_4_4_read : 3; + uint32_t inst_4_4_4_read : 8; + } read_4_4_info; // 7th word + + struct + { + uint8_t size; + uint8_t inst; + } erase_info[4]; // 8th,9th word + + uint32_t erase_timing; // 10th word + struct + { + uint32_t reserved0 : 4; + uint32_t page_size : 4; + uint32_t reserved1 : 24; + } chip_erase_progrm_info; // 11th word + + struct + { + uint32_t suspend_resume_spec; + uint32_t suspend_resume_inst; + } suspend_resume_info; // 12th, 13th word + + struct + { + uint32_t reserved0 : 2; + uint32_t busy_status_polling : 6; + uint32_t reserved1 : 24; + } busy_status_info; // 14th word + + struct + { + uint32_t mode_4_4_4_disable_seq : 4; + uint32_t mode_4_4_4_enable_seq : 5; + uint32_t support_mode_0_4_4 : 1; + uint32_t mode_0_4_4_exit_method : 6; + uint32_t mode_0_4_4_entry_method : 4; + uint32_t quad_enable_requirement : 3; + uint32_t hold_reset_disable : 1; + uint32_t reserved0 : 8; + } mode_4_4_info; // 15th word + + struct + { + uint32_t status_reg_write_enable : 7; + uint32_t reserved0 : 1; + uint32_t soft_reset_rescue_support : 6; + uint32_t exit_4_byte_addressing : 10; + uint32_t enter_4_byte_addrssing : 8; + } mode_config_info; // 16th word + + struct + { + uint32_t dummy_clocks_1_8_8_read : 5; + uint32_t mode_clocks_1_8_8_read : 3; + uint32_t inst_1_8_8_read : 8; + uint32_t dummy_clocks_1_1_8_read : 5; + uint32_t mode_clocks_1_1_8_read : 3; + uint32_t inst_1_1_8_read : 8; + } read_1_8_info; // 17th word + + struct + { + uint32_t reserved : 18; + uint32_t output_driver_strength : 5; + uint32_t jedec_spi_protocol_reset : 1; + uint32_t dqs_waveform_type_sdr : 2; + uint32_t dqs_support_in_qpi_sdr : 1; + uint32_t dqs_support_in_qpi_ddr : 1; + uint32_t dqs_support_in_opi_str : 1; + uint32_t cmd_and_extension_in_opi_ddr : 2; + uint32_t byte_order_in_opi_ddr : 1; + } xpi_misc_info; // 18th word + + struct + { + uint32_t opi_sdr_disable_seq : 4; + uint32_t opi_sdr_enable_seq : 5; + uint32_t support_mode_0_8_8 : 1; + uint32_t mode_0_8_8_exit_method : 6; + uint32_t mode_0_8_8_entry_method : 4; + uint32_t octal_enable_requirement : 3; + uint32_t reserved : 9; + } mode_octal_info; // 19th word + + struct + { + uint32_t qpi_sdr_no_dqs : 4; + uint32_t qpi_sdr_with_dqs : 4; + uint32_t qpi_ddr_no_dqs : 4; + uint32_t qpi_ddr_with_dqs : 4; + uint32_t opi_sdr_no_dqs : 4; + uint32_t opi_sdr_with_dqs : 4; + uint32_t opi_ddr_no_dqs : 4; + uint32_t opi_ddr_with_dqs : 4; + } max_speed_info_xpi; // 20th word + }; + +} jedec_flash_param_table_t; + +//!@brief 4Byte Addressing Instruction Table, see JESD216D doc for more details +typedef union _jedec_4byte_addressing_inst_table +{ + uint32_t words[2]; + struct + { + struct + { + uint32_t support_1_1_1_read : 1; + uint32_t support_1_1_1_fast_read : 1; + uint32_t support_1_1_2_fast_read : 1; + uint32_t support_1_2_2_fast_read : 1; + uint32_t support_1_1_4_fast_read : 1; + uint32_t support_1_4_4_fast_read : 1; + uint32_t support_1_1_1_page_program : 1; + uint32_t support_1_1_4_page_program : 1; + uint32_t support_1_4_4_page_program : 1; + uint32_t support_erase_type1_size : 1; + uint32_t support_erase_type2_size : 1; + uint32_t support_erase_type3_size : 1; + uint32_t support_erase_type4_size : 1; + uint32_t support_1_1_1_dtr_read : 1; + uint32_t support_1_2_2_dtr_read : 1; + uint32_t support_1_4_4_dtr_read : 1; + uint32_t support_volatile_sector_lock_read_cmd : 1; + uint32_t support_volatile_sector_lock_write_cmd : 1; + uint32_t support_nonvolatile_sector_lock_read_cmd : 1; + uint32_t support_nonvolatile_sector_lock_write_cmd : 1; + uint32_t reserved : 12; + } cmd_4byte_support_info; + + struct + { + uint8_t erase_inst[4]; + } erase_inst_info; + }; +} jedec_4byte_addressing_inst_table_t; + +typedef union _jedec_cmd_sequence_change_to_octal_mode +{ + uint32_t words[8]; + + struct + { + struct + { + uint32_t byte3_of_1st_command_seq : 8; + uint32_t byte2_of_1st_command_seq : 8; + uint32_t byte1_of_1st_command_seq : 8; + uint32_t length_of_1st_command_seq : 8; + } first_command_sequence_low; // 1st command sequence + + struct + { + uint32_t byte7_of_first_command_seq : 8; + uint32_t byte6_of_first_command_seq : 8; + uint32_t byte5_of_first_command_seq : 8; + uint32_t byte4_of_first_command_seq : 8; + } first_command_sequence_high; // 1st command sequence + + struct + { + uint32_t byte3_of_2nd_command_seq : 8; + uint32_t byte2_of_2nd_command_seq : 8; + uint32_t byte1_of_2nd_command_seq : 8; + uint32_t length_of_2nd_command_seq : 8; + } second_command_sequence_low; // 2nd command sequence + + struct + { + uint32_t byte7_of_2nd_command_seq : 8; + uint32_t byte6_of_2nd_command_seq : 8; + uint32_t byte5_of_2nd_command_seq : 8; + uint32_t byte4_of_2md_command_seq : 8; + } second_command_sequence_high; // 2nd command sequence + + struct + { + uint32_t byte3_of_3rd_command_seq : 8; + uint32_t byte2_of_3rd_command_seq : 8; + uint32_t byte1_of_3rd_command_seq : 8; + uint32_t length_of_3rd_command_seq : 8; + } third_command_sequence_low; // 3rd command sequence + + struct + { + uint32_t byte7_of_3rd_command_seq : 8; + uint32_t byte6_of_3rd_command_seq : 8; + uint32_t byte5_of_3rd_command_seq : 8; + uint32_t byte4_of_3rd_command_seq : 8; + } third_command_sequence_high; // 3rd command sequence + + struct + { + uint32_t byte3_of_4th_command_seq : 8; + uint32_t byte2_of_4th_command_seq : 8; + uint32_t byte1_of_4th_command_seq : 8; + uint32_t length_of_4th_command_seq : 8; + } fourth_command_sequence_low; // 4th command sequence + + struct + { + uint32_t byte7_of_4th_command_seq : 8; + uint32_t byte6_of_4th_command_seq : 8; + uint32_t byte5_of_4th_command_seq : 8; + uint32_t byte4_of_4th_command_seq : 8; + } fourth_command_sequence_high; // 4th command sequence + }; + +} jedec_cmd_sequence_change_to_octal_mode_t; + +typedef union _jedec_x_spi_profile1_0_table_t +{ + uint32_t words[5]; + + struct + { + struct + { + uint32_t fast_read_wrapped_cmd : 8; + uint32_t fast_read_cmd : 8; + uint32_t reserved : 16; + } table1; + + struct + { + uint32_t write_nv_register_cmd : 8; + uint32_t write_v_register_cmd : 8; + uint32_t reserved : 16; + } table2; + + uint32_t unused_tables[3]; + }; + +} jedec_x_spi_profile1_0_table_t; + +typedef union _jedec_status_control_configuration_reg_map +{ + uint32_t words[28]; + struct + { + uint32_t unused_table[2]; + struct + { + uint32_t dummy_cycles_1s_1s_1s : 4; + uint32_t reserved0 : 2; + uint32_t dummy_cycles_8d_8d_8d : 4; + uint32_t dummy_cycles_8s_8s_8s : 4; + uint32_t dummy_cycles_4s_4d_4d : 4; + uint32_t dummy_cycles_4s_4s_4s : 4; + uint32_t dummy_cycles_2s_2s_2s : 4; + uint32_t dummy_cycles_1s_1s_1s_select : 2; + uint32_t addr_bytes_address_status_register : 2; + uint32_t unused0 : 2; + }; + uint32_t unused_table1[25]; + }; +} jedec_status_control_configuration_reg_map_t; + +typedef struct _jdec_query_table +{ + uint32_t standard_version; // JESD216 version + uint32_t flash_param_tbl_size; + jedec_flash_param_table_t flash_param_tbl; + bool has_4b_addressing_inst_table; + jedec_4byte_addressing_inst_table_t flash_4b_inst_tbl; + bool has_otcal_ddr_mode_enable_sequence_table; + jedec_cmd_sequence_change_to_octal_mode_t otcal_ddr_mode_enable_sequence; // JESD216C/D + jedec_x_spi_profile1_0_table_t profile1_0_table; + bool has_spi_profile1_0_table; + jedec_status_control_configuration_reg_map_t sccr_map; + bool has_sccr_map; +} jedec_info_table_t; + + +//!@brief Typical Serial NOR commands supported by most Serial NOR devices +#define kSerialNorCmd_BasicRead_3B (0x03U) +#define kSerialNorCmd_BasicRead_4B (0x13U) +#define kSerialNorCmd_PageProgram_1_1_1_3B (0x02U) +#define kSerialNorCmd_PageProgram_1_1_1_4B (0x12U) +#define kSerialNorCmd_PageProgram_1_4_4_4B (0x3EU) +#define kSerialNorCmd_PageProgram_1_1_4_4B (0x34U) +#define kSerialNorCmd_Read_SDR_1_4_4_3B (0xEBU) +#define kSerialNorCmd_Read_DDR_1_4_4_3B (0xEDU) +#define kSerialNorCmd_Read_SDR_1_4_4_4B (0xECU) +#define kSerialNorCmd_Read_SDR_1_1_4_4B (0x6CU) +#define kSerialNorCmd_Read_DDR_1_4_4_4B (0xEEU) +#define kSerialNorCmd_ChipErase (0x60U) +#define kSerialNorCmd_WriteEnable (0x06U) +#define kSerialNorCmd_WriteStatusReg1 (0x01U) +#define kSerialNorCmd_ReadStatusReg1 (0x05U) +#define kSerialNorCmd_WriteStatusReg2 (0x3EU) +#define kSerialNorCmd_ReadStatusReg2 (0x3FU) +#define kSerialNorCmd_ReadFlagReg (0x70U) +#define kSerialNorCmd_ReadId (0x9FU) +#define kSerialNorCmd_Read_DDR_4B (0x0CU) +#define kSerialNorCmd_Read_DDR_3B (0x0BU) +#define kSerialNorCmd_SE4K_3B (0x20U) +#define kSerialNorCmd_SE4K_4B (0x21U) +#define kSerialNorCmd_SE64K_3B (0xD8U) +#define kSerialNorCmd_SE64K_4B (0xDCU) + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c new file mode 100644 index 0000000000..039132f114 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_spi.h" + +static hpm_stat_t hpm_spi_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t src, uint32_t size) +{ + dma_handshake_config_t config; + config.ch_index = ch_num; + config.dst = (uint32_t)&spi_ptr->DATA; + config.dst_fixed = true; + config.src = src; + config.src_fixed = false; + config.size_in_byte = size; + + return dma_setup_handshake(dma_ptr, &config); +} + +static hpm_stat_t hpm_spi_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, uint32_t size) +{ + dma_handshake_config_t config; + config.ch_index = ch_num; + config.dst = dst; + config.dst_fixed = false; + config.src = (uint32_t)&spi_ptr->DATA; + config.src_fixed = true; + config.size_in_byte = size; + + return dma_setup_handshake(dma_ptr, &config); +} + + +void hpm_spi_prepare_dma_tx_descriptors(spi_context_t *context, spi_control_config_t *config, uint32_t trans_count, + uint32_t *spi_transctrl, dma_linked_descriptor_t *tx_dma_descriptors) +{ + SPI_Type *ptr = context->ptr; + uint32_t dma_transfer_size[trans_count]; + uint32_t tx_size = context->tx_size; + uint32_t per_trans_size = context->per_trans_max; + uint32_t dmamux_ch = context->dma_context.tx_dmamux_ch; + uint8_t *tx_buff = context->tx_buff; + + static uint8_t dummy_cmd = 0xff; + + uint32_t temp32; + uint32_t tx_buff_index = 0; + for (uint32_t i = 0; i < trans_count; i++) { + if (tx_size > per_trans_size) { + temp32 = per_trans_size; + tx_size -= per_trans_size; + } else { + temp32 = tx_size; + } + + *(spi_transctrl + i) = SPI_TRANSCTRL_TRANSMODE_SET(config->common_config.trans_mode == spi_trans_write_read_together ? + spi_trans_write_read_together : spi_trans_write_only) + | SPI_TRANSCTRL_DUALQUAD_SET(config->common_config.data_phase_fmt) + | SPI_TRANSCTRL_WRTRANCNT_SET(temp32 - 1) + | SPI_TRANSCTRL_RDTRANCNT_SET(temp32 - 1); + + if (i == 0) { + temp32 = temp32 + 1; /* DMA transmits one byte more than SPI at the first transmission */ + } + if (i == trans_count - 1) { + temp32 = temp32 - 1; + } + dma_transfer_size[i] = temp32; + + /* SPI CTRL */ + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->trans_size = 1; + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(spi_transctrl + i)); + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->TRANSCTRL); + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_WORD) + | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_WORD) + | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) + | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) + | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->linked_ptr = + core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)); + + /* SPI CMD */ + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->trans_size = 1; + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_cmd); + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->CMD); + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) + | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) + | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) + | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) + | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->linked_ptr = + core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)); + + /* SPI DATA */ + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->trans_size = dma_transfer_size[i]; + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->src_addr = + core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_buff + tx_buff_index)); + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->DATA); + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) + | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) + | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) + | DMA_CHCTRL_CTRL_DSTMODE_SET(DMA_HANDSHAKE_MODE_HANDSHAKE) + | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(DMA_ADDRESS_CONTROL_FIXED) + | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) + | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); + if (i == trans_count - 1) { + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->linked_ptr = 0; + } else { + (tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->linked_ptr = + core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + (i + 1) * SPI_DMA_DESC_COUNT_PER_TRANS)); + } + + tx_buff_index += temp32; + } +} + +void hpm_prepare_dma_rx_descriptors(spi_context_t *context, spi_control_config_t *config, uint32_t trans_count, + uint32_t *spi_transctrl, dma_linked_descriptor_t *rx_dma_descriptors) +{ + SPI_Type *ptr = context->ptr; + uint32_t dma_transfer_size[trans_count]; + uint32_t rx_size = context->rx_size; + uint32_t per_trans_size = context->per_trans_max; + uint32_t dmamux_ch = context->dma_context.rx_dmamux_ch; + uint8_t *rx_buff = context->rx_buff; + + static uint8_t dummy_cmd = 0xff; + + uint32_t temp32; + uint32_t rx_buff_index = 0; + for (uint32_t i = 0; i < trans_count; i++) { + if (rx_size > per_trans_size) { + temp32 = per_trans_size; + rx_size -= per_trans_size; + } else { + temp32 = rx_size; + } + + *(spi_transctrl + i) = SPI_TRANSCTRL_TRANSMODE_SET(spi_trans_read_only) | + SPI_TRANSCTRL_DUALQUAD_SET(config->common_config.data_phase_fmt) | + SPI_TRANSCTRL_WRTRANCNT_SET(temp32 - 1) | + SPI_TRANSCTRL_RDTRANCNT_SET(temp32 - 1); + dma_transfer_size[i] = temp32; + + /* SPI CTRL */ + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->trans_size = 1; + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(spi_transctrl + i)); + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->TRANSCTRL); + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_WORD) + | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_WORD) + | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) + | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) + | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS)->linked_ptr = + core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)); + + /* SPI CMD */ + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->trans_size = 1; + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_cmd); + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->CMD); + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) + | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) + | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) + | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) + | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)->linked_ptr = + core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)); + + /* SPI DATA */ + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->trans_size = dma_transfer_size[i]; + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->DATA); + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->dst_addr = + core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_buff + rx_buff_index)); + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->ctrl = DMA_CHCTRL_CTRL_SRCWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) + | DMA_CHCTRL_CTRL_DSTWIDTH_SET(DMA_TRANSFER_WIDTH_BYTE) + | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(DMA_NUM_TRANSFER_PER_BURST_1T) + | DMA_CHCTRL_CTRL_SRCMODE_SET(DMA_HANDSHAKE_MODE_HANDSHAKE) + | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(DMA_ADDRESS_CONTROL_FIXED) + | DMA_CHCTRL_CTRL_SRCREQSEL_SET(dmamux_ch) + | DMA_CHCTRL_CTRL_DSTREQSEL_SET(dmamux_ch); + if (i == trans_count - 1) { + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->linked_ptr = 0; + } else { + (rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)->linked_ptr = + core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + (i + 1) * SPI_DMA_DESC_COUNT_PER_TRANS)); + } + rx_buff_index += temp32; + } +} + +static uint32_t hpm_spi_get_trans_count(spi_context_t *context, spi_control_config_t *config) +{ + uint32_t total_trans_size, per_trans_size, trans_count; + + per_trans_size = context->per_trans_max; + if (config->common_config.trans_mode == spi_trans_write_only || config->common_config.trans_mode == spi_trans_dummy_write) { + total_trans_size = context->tx_size; + } else if (config->common_config.trans_mode == spi_trans_read_only || config->common_config.trans_mode == spi_trans_dummy_read) { + total_trans_size = context->rx_size; + } else { + /* write read together */ + assert(context->tx_size == context->rx_size); + total_trans_size = context->tx_size; + } + trans_count = (total_trans_size + per_trans_size - 1) / per_trans_size; + + return trans_count; +} + +static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_control_config_t *config) +{ + hpm_stat_t stat = status_success; + SPI_Type *spi_ptr = context->ptr; + DMA_Type *dma_ptr = context->dma_context.dma_ptr; + DMAMUX_Type *dmamux_ptr = context->dma_context.dmamux_ptr; + dma_linked_descriptor_t *dma_linked_descriptor = context->dma_linked_descriptor; + uint32_t *spi_transctrl = context->spi_transctrl; + uint32_t dma_channel; + uint32_t trans_count; + dma_channel_config_t dma_ch_config = {0}; + + trans_count = hpm_spi_get_trans_count(context, config); + + /* active spi cs pin */ + context->write_cs(context->cs_pin, SPI_CS_ACTIVE); + + stat = spi_setup_dma_transfer(spi_ptr, + config, + &context->cmd, + &context->addr, + MIN(context->tx_size, context->per_trans_max), + MIN(context->rx_size, context->per_trans_max)); + if (stat != status_success) { + return stat; + } + + if (config->common_config.trans_mode == spi_trans_write_only || config->common_config.trans_mode == spi_trans_dummy_write) { + /* write only */ + hpm_spi_prepare_dma_tx_descriptors(context, config, trans_count, spi_transctrl, dma_linked_descriptor); + dma_channel = context->dma_context.tx_dma_ch; + dmamux_config(dmamux_ptr, context->dma_context.tx_dmamux_ch, context->dma_context.tx_req, true); + } else if (config->common_config.trans_mode == spi_trans_read_only || config->common_config.trans_mode == spi_trans_dummy_read) { + /* read only */ + hpm_prepare_dma_rx_descriptors(context, config, trans_count, spi_transctrl, dma_linked_descriptor); + dma_channel = context->dma_context.rx_dma_ch; + dmamux_config(dmamux_ptr, context->dma_context.rx_dmamux_ch, context->dma_context.rx_req, true); + } else if (config->common_config.trans_mode == spi_trans_write_read_together) { + /* write and read together */ + hpm_spi_prepare_dma_tx_descriptors(context, config, trans_count, spi_transctrl, dma_linked_descriptor); + dma_channel = context->dma_context.tx_dma_ch; + dmamux_config(dmamux_ptr, context->dma_context.tx_dmamux_ch, context->dma_context.tx_req, true); + dmamux_config(dmamux_ptr, context->dma_context.rx_dmamux_ch, context->dma_context.rx_req, true); + /* spi tx use chained dma descriptor, spi rx use unchained dma */ + stat = hpm_spi_rx_trigger_dma(dma_ptr, + context->dma_context.rx_dmamux_ch, + spi_ptr, + core_local_mem_to_sys_address(context->running_core, (uint32_t)context->rx_buff), + context->rx_size); + if (stat != status_success) { + return stat; + } + } + + /* use a dummy dma transfer to start SPI trans dma chain */ + static uint32_t dummy_data1 = 0xff, dummy_data2 = 0xff; + dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_data1); + dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_data2); + dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + dma_ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; + dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; + dma_ch_config.size_in_byte = 4; + dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(dma_linked_descriptor + SPI_DMA_DESC_COUNT_PER_TRANS - 1)); + + stat = dma_setup_channel(dma_ptr, dma_channel, &dma_ch_config); + if (stat != status_success) { + return stat; + } + + return stat; +} + +static hpm_stat_t spi_setup_trans_with_dma(spi_context_t *context, spi_control_config_t *config) +{ + hpm_stat_t stat = status_success; + SPI_Type *spi_ptr = context->ptr; + DMA_Type *dma_ptr = context->dma_context.dma_ptr; + DMAMUX_Type *dmamux_ptr = context->dma_context.dmamux_ptr; + uint32_t trans_mode = config->common_config.trans_mode; + + if (context->write_cs != NULL) { + context->write_cs(context->cs_pin, SPI_CS_ACTIVE); + } + stat = spi_setup_dma_transfer(spi_ptr, config, + &context->cmd, &context->addr, + context->tx_size, context->rx_size); + if (stat != status_success) { + return stat; + } + + if (trans_mode != spi_trans_write_only && trans_mode != spi_trans_dummy_write && trans_mode != spi_trans_no_data) { + dmamux_config(dmamux_ptr, context->dma_context.rx_dmamux_ch, context->dma_context.rx_req, true); + stat = hpm_spi_rx_trigger_dma(dma_ptr, + context->dma_context.rx_dmamux_ch, + spi_ptr, + core_local_mem_to_sys_address(context->running_core, (uint32_t)context->rx_buff), + context->rx_size); + if (stat != status_success) { + return stat; + } + /* cache invalidate for receive buff */ + if (l1c_dc_is_enabled()) { + l1c_dc_invalidate((uint32_t)context->rx_buff, context->rx_size); + } + } + if (trans_mode != spi_trans_read_only && trans_mode != spi_trans_dummy_read && trans_mode != spi_trans_no_data) { + dmamux_config(dmamux_ptr, context->dma_context.tx_dmamux_ch, context->dma_context.tx_req, true); + /* cache writeback for tx buff */ + if (l1c_dc_is_enabled()) { + l1c_dc_writeback((uint32_t)context->tx_buff, context->tx_size); + } + + stat = hpm_spi_tx_trigger_dma(dma_ptr, + context->dma_context.tx_dmamux_ch, + spi_ptr, + core_local_mem_to_sys_address(context->running_core, (uint32_t)context->tx_buff), + context->tx_size); + if (stat != status_success) { + return stat; + } + } + + return stat; +} + +hpm_stat_t hpm_spi_setup_dma_transfer(spi_context_t *context, spi_control_config_t *config) +{ + assert(context != NULL || config != NULL); + /* use dma */ + assert(&context->dma_context != NULL); + /* spi per trans data size not zero */ + assert(context->per_trans_max); + + hpm_stat_t stat = status_success; + uint32_t trans_mode = config->common_config.trans_mode; + + if ((context->rx_size > context->per_trans_max) || (context->tx_size > context->per_trans_max)) { + /* multiple SPI transmissions with chained DMA */ + assert(trans_mode == spi_trans_read_only || trans_mode == spi_trans_dummy_read + || trans_mode == spi_trans_write_only || trans_mode == spi_trans_dummy_write + || trans_mode == spi_trans_write_read_together); + /* master mode */ + assert((context->ptr->TRANSFMT & SPI_TRANSFMT_SLVMODE_MASK) != SPI_TRANSFMT_SLVMODE_MASK); + /* GPIO should be used to replace SPI CS pin for SPI chained DMA transmissions */ + assert(context->write_cs != NULL); + + stat = spi_setup_trans_with_dma_chain(context, config); + } else { + /* one SPI transmissions with chained DMA */ + stat = spi_setup_trans_with_dma(context, config); + } + + return stat; +} + +/* Using GPIO as SPI CS pin */ +/* When SPI trans completed, GPIO cs pin should be released manually */ +hpm_stat_t hpm_spi_release_gpio_cs(spi_context_t *context) +{ + hpm_stat_t stat; + SPI_Type *ptr = context->ptr; + assert(context->write_cs != NULL); + + stat = spi_wait_for_idle_status(ptr); + if (stat != status_success) { + return stat; + } + + context->write_cs(context->cs_pin, !SPI_CS_ACTIVE); + return status_success; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h new file mode 100644 index 0000000000..91d60e2f42 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_COMPONENT_SPI_H +#define HPM_COMPONENT_SPI_H + +#include "hpm_common.h" +#include "hpm_spi_drv.h" +#include "hpm_dma_drv.h" +#include "hpm_dmamux_drv.h" +#include "hpm_misc.h" +#include "hpm_l1c_drv.h" + +#ifndef SPI_CS_ACTIVE +#define SPI_CS_ACTIVE 0 +#endif + +/* Every transaction can be delineated by 3 dma descriptions: SPI control, SPI cmd, SPI data */ +#define SPI_DMA_DESC_COUNT_PER_TRANS (3U) + +typedef struct { + DMA_Type *dma_ptr; + DMAMUX_Type *dmamux_ptr; + uint8_t rx_dma_ch; + uint8_t tx_dma_ch; + uint8_t rx_dmamux_ch; + uint8_t tx_dmamux_ch; + uint8_t rx_req; + uint8_t tx_req; +} spi_dma_context_t; + +typedef struct { + SPI_Type *ptr; + uint32_t cs_pin; + uint8_t cmd; + uint8_t *rx_buff; + uint8_t *tx_buff; + uint8_t running_core; + uint32_t addr; + uint32_t rx_size; + uint32_t tx_size; + uint32_t per_trans_max; + uint32_t *spi_transctrl; + void (*write_cs)(uint32_t cs_pin, uint8_t state); + spi_dma_context_t dma_context; + dma_linked_descriptor_t *dma_linked_descriptor; +} spi_context_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief hpm_spi setup dma transfer + * + * @param[in] spi_context A pointer to the struct of "spi_context_t" + * @param[in] spi_config A pointer to the struct of "spi_control_config_t" + * @retval status_success if SPI transfers data successfully. + */ +hpm_stat_t hpm_spi_setup_dma_transfer(spi_context_t *context, spi_control_config_t *config); + +/* + * SPI release gpio pin if gpio use for SPI CS function + */ +/** + * @brief hpm_spi releases gpio cs pin after SPI transfer completed + * + * @param[in] spi_context A pointer to the struct of "spi_context_t" + * @retval status_success if SPI releases gpio cs pin successfully. + */ +hpm_stat_t hpm_spi_release_gpio_cs(spi_context_t *context); + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_COMPONENT_SPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c new file mode 100644 index 0000000000..323546a857 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_ft5406.h" + +hpm_stat_t ft5406_read_register(ft5406_context_t *context, uint8_t reg, uint8_t *buf) +{ + return i2c_master_address_read(context->ptr, FT5406_I2C_ADDR, ®, 1, buf, 1); +} + +hpm_stat_t ft5406_write_register(ft5406_context_t *context, uint8_t reg, uint8_t val) +{ + return i2c_master_address_write(context->ptr, FT5406_I2C_ADDR, ®, 1, &val, 1); +} + +hpm_stat_t ft5406_set_mode(ft5406_context_t *context, uint8_t mode) +{ + return ft5406_write_register(context, FT5406_DEVICE_MODE, 1); +} + +hpm_stat_t ft5406_init(ft5406_context_t *context) +{ + return ft5406_set_mode(context, FT5406_DEVICE_MODE_NORMAL); +} + +hpm_stat_t ft5406_get_sys_info(ft5406_context_t *context, ft5406_sys_info_t *info) +{ + hpm_stat_t stat = status_success; + uint8_t reg_addr = FT5406_DEVICE_MODE; + + stat = ft5406_set_mode(context, FT5406_DEVICE_MODE_SYS_INFO); + if (stat != status_success) { + return stat; + } + return i2c_master_address_read(context->ptr, FT5406_I2C_ADDR, ®_addr, 1, (uint8_t *)info, sizeof(ft5406_sys_info_t)); +} + +hpm_stat_t ft5406_read_data(ft5406_context_t *context, uint8_t addr, uint8_t *buf, uint32_t size) +{ + return i2c_master_address_read(context->ptr, FT5406_I2C_ADDR, &addr, 1, buf, size); +} + +hpm_stat_t ft5406_read_touch_data(ft5406_context_t *context, ft5406_touch_data_t *touch_data) +{ + return ft5406_read_data(context, FT5406_GEST_ID, (uint8_t *)touch_data, sizeof(ft5406_touch_data_t)); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h new file mode 100644 index 0000000000..b4c01b48fb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_FT5406_H +#define HPM_FT5406_H +#include "hpm_common.h" +#include "hpm_i2c_drv.h" + +#define FT5406_I2C_ADDR (0x38U) + +/* + * FT5406 registers at operation mode + */ +#define FT5406_DEVICE_MODE (0U) +#define FT5406_GEST_ID (0x1U) +#define FT5406_TD_STATUS (0x2U) +#define FT5406_TOUCH1_XH (0x3U) +#define FT5406_TOUCH1_XL (0x4U) +#define FT5406_TOUCH1_YH (0x5U) +#define FT5406_TOUCH1_YL (0x6U) + +#define FT5406_TOUCH2_XH (0x9U) +#define FT5406_TOUCH2_XL (0xAU) +#define FT5406_TOUCH2_YH (0xBU) +#define FT5406_TOUCH2_YL (0xCU) + +#define FT5406_TOUCH3_XH (0xFU) +#define FT5406_TOUCH3_XL (0x10U) +#define FT5406_TOUCH3_YH (0x11U) +#define FT5406_TOUCH3_YL (0x12U) + +#define FT5406_TOUCH4_XH (0x15U) +#define FT5406_TOUCH4_XL (0x16U) +#define FT5406_TOUCH4_YH (0x17U) +#define FT5406_TOUCH4_YL (0x18U) + +#define FT5406_TOUCH5_XH (0x1BU) +#define FT5406_TOUCH5_XL (0x1CU) +#define FT5406_TOUCH5_YH (0x1DU) +#define FT5406_TOUCH5_YL (0x1EU) + +#define FT5406_ID_G_THGROUP (0x80U) +#define FT5406_ID_G_THPEAK (0x81U) +#define FT5406_ID_G_THCAL (0x82U) +#define FT5406_ID_G_THWARTER (0x83U) +#define FT5406_ID_G_THTEMP (0x84U) + +#define FT5406_ID_G_CTRL (0x86U) +#define FT5406_ID_G_TIME_ENTER_MONITOR (0x87U) +#define FT5406_ID_G_PERIODACTIVE (0x88U) +#define FT5406_ID_G_PERIODMONITOR (0x89U) + +#define FT5406_ID_G_AUTO_CLB_MODE (0xA0U) +#define FT5406_ID_G_LIB_VERSION_H (0xA1U) +#define FT5406_ID_G_LIB_VERSION_L (0xA2U) +#define FT5406_ID_G_CIPHER (0xA3U) +#define FT5406_ID_G_MODE (0xA4U) +#define FT5406_ID_G_PMODE (0xA5U) +#define FT5406_ID_G_FIRM_ID (0xA6U) +#define FT5406_ID_G_STATE (0xA7U) +#define FT5406_ID_G_FT5201ID (0xA8U) +#define FT5406_ID_G_ERR (0xA9U) +#define FT5406_ID_G_CLB (0xAAU) +#define FT5406_ID_G_B_AREA_TH (0xAEU) + +#define FT5406_DEVICE_MODE_NORMAL (0) +#define FT5406_DEVICE_MODE_SYS_INFO (1U) +#define FT5406_DEVICE_MODE_TEST (2U) + +#define FT5406_STATUS_CONFIGURE (0) +#define FT5406_STATUS_WORK (1U) +#define FT5406_STATUS_CALIBRATION (2U) +#define FT5406_STATUS_FACTORY (3U) +#define FT5406_STATUS_AUTO_CALIBRATION (4U) + +#define FT5406_GESTURE_NO_GESTURE (0) +#define FT5406_GESTURE_MOVE_UP (0x10U) +#define FT5406_GESTURE_MOVE_LEFT (0x14U) +#define FT5406_GESTURE_MOVE_DOWN (0x18U) +#define FT5406_GESTURE_MOVE_RIGHT (0x1CU) +#define FT5406_GESTURE_ZOOM_IN (0x48U) +#define FT5406_GESTURE_ZOOM_OUT (0x49U) + +#define FT5406_MAX_TOUCH_POINTS (5U) + +typedef struct { + uint8_t x_h; + uint8_t x_l; + uint8_t y_h; + uint8_t y_l; + uint16_t reserved; +} ft5406_touch_point_t; + +typedef struct { + uint8_t gesture; + uint8_t status; + ft5406_touch_point_t points[FT5406_MAX_TOUCH_POINTS]; +} ft5406_touch_data_t; + +typedef struct { + I2C_Type *ptr; +} ft5406_context_t; + +typedef struct { + uint8_t mode; + uint8_t bist_comm; + uint8_t bist_stat; + uint8_t reserved0[4]; + uint8_t uid[8]; + uint8_t bl_verh; + uint8_t bl_verl; + uint8_t fts_ic_verh; + uint8_t fts_ic_verl; + uint8_t app_idh; + uint8_t app_idl; + uint8_t app_verh; + uint8_t app_verl; + uint8_t reserved1[4]; + uint8_t cid[5]; +} ft5406_sys_info_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * ft5406 initialization routine + */ +hpm_stat_t ft5406_init(ft5406_context_t *context); + +/* + * ft5406 set working mode + */ +hpm_stat_t ft5406_set_mode(ft5406_context_t *context, uint8_t mode); + +/* + * ft5406 get system information + */ +hpm_stat_t ft5406_get_sys_info(ft5406_context_t *context, + ft5406_sys_info_t *info); + +/* + * ft5406 read touch data + */ +hpm_stat_t ft5406_read_touch_data(ft5406_context_t *context, + ft5406_touch_data_t *touch_data); + +/* + * ft5406 read data + */ +hpm_stat_t ft5406_read_data(ft5406_context_t *context, uint8_t addr, + uint8_t *buf, uint32_t size); + +/* + * ft5406 write value to given register + */ +hpm_stat_t ft5406_write_register(ft5406_context_t *context, + uint8_t reg, uint8_t val); + +/* + * ft5406 read value of given register + */ +hpm_stat_t ft5406_read_register(ft5406_context_t *context, uint8_t reg, uint8_t *buf); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_FT5406_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c new file mode 100644 index 0000000000..65378eb3bb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_touch.h" +ft5406_context_t ft5406 = {0}; + +hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points) +{ + hpm_stat_t stat = status_success; + uint8_t i = 0; + ft5406_touch_data_t touch_data = {0}; + + stat = ft5406_read_touch_data(&ft5406, &touch_data); + if (stat != status_success) { + return stat; + } + + if ((touch_data.status < FT5406_MAX_TOUCH_POINTS) && (touch_data.status)) { + for (i = 0; touch_data.points[i].x_h > 0 && touch_data.points[i].x_h < 0xFF; i++) { + points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l; + points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l; + } + } + + *num_of_points = i; + return stat; +} + +hpm_stat_t touch_init(I2C_Type *i2c_ptr) +{ + hpm_stat_t stat; + + ft5406.ptr = i2c_ptr; + stat = ft5406_init(&ft5406); + if (stat != status_success) { + return stat; + } + +#ifdef USE_CAP_INT + stat = ft5406_write_register(&ft5406, FT5406_ID_G_MODE, 0); + if (stat != status_success) { + return stat; + } + cap_int_setup(); +#endif + return stat; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c new file mode 100644 index 0000000000..b4278ae3ee --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_gt911.h" +static uint8_t g_i2c_addr; + +hpm_stat_t gt911_read_data(gt911_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size) +{ + uint8_t r[2]; + r[0] = addr >> 8; + r[1] = addr & 0xFF; + return i2c_master_address_read(context->ptr, g_i2c_addr, r, sizeof(r), buf, size); +} + +hpm_stat_t gt911_write_data(gt911_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size) +{ + uint8_t r[2]; + r[0] = addr >> 8; + r[1] = addr & 0xFF; + + return i2c_master_address_write(context->ptr, g_i2c_addr, r, sizeof(r), buf, size); +} + +hpm_stat_t gt911_read_register(gt911_context_t *context, uint16_t reg, uint8_t *buf) +{ + return gt911_read_data(context, reg, buf, 1); +} + +hpm_stat_t gt911_write_register(gt911_context_t *context, uint16_t reg, uint8_t val) +{ + return gt911_write_data(context, reg, &val, 1); +} + +hpm_stat_t gt911_soft_reset(gt911_context_t *context) +{ + return gt911_write_register(context, GT911_CMD, 0); +} + +static uint8_t gt911_calcualte_config_data_checksum(uint8_t *config) +{ + uint8_t checksum = 0; + for (uint32_t i = 0; i < GT911_CONFIG_DATA_SIZE - 2; i++) { + checksum += config[i]; + } + return (~checksum + 1); +} + +hpm_stat_t gt911_read_config(gt911_context_t *context, uint8_t *buf, uint8_t size) +{ + return gt911_read_data(context, GT911_CONFIG, buf, size); +} + +hpm_stat_t gt911_init(gt911_context_t *context, uint16_t width, uint16_t height) +{ + hpm_stat_t stat = status_success; + uint8_t config[GT911_CONFIG_DATA_SIZE] = {0}; + +#ifdef GT911_I2C_ADDR + g_i2c_addr = GT911_I2C_ADDR; + stat = gt911_read_data(context, GT911_CONFIG, config, sizeof(config)); + if (stat != status_success) { + return stat; + } +#elif !GT911_NO_AUTO_PROBE + g_i2c_addr = GT911_I2C_ADDR0; + stat = gt911_read_data(context, GT911_CONFIG, config, sizeof(config)); + if (stat != status_success) { + printf("0x%x failed to init GT911", g_i2c_addr); + g_i2c_addr = GT911_I2C_ADDR1; + printf(", try 0x%x\n", g_i2c_addr); + stat = gt911_read_data(context, GT911_CONFIG, config, sizeof(config)); + } + if (stat != status_success) { + return stat; + } +#else + g_i2c_addr = GT911_I2C_ADDR0; + stat = gt911_read_data(context, GT911_CONFIG, config, sizeof(config)); + if (stat != status_success) { + return stat; + } +#endif + + if (config[GT911_CONFIG_DATA_SIZE - 2] != gt911_calcualte_config_data_checksum(config)) { + return status_fail; + } + + /* stat = gt911_read_data(context, GT911_ID_B0, (uint8_t*)&val, sizeof(val)); */ + /* if (stat != status_success) { */ + /* return stat; */ + /* } */ + + /* if (val != GT911_PRODUCT_ID) { */ + /* return status_fail; */ + /* } */ + + config[GT911_CONFIG_DATA_RESOLUTION_XL] = width & 0xFF; + config[GT911_CONFIG_DATA_RESOLUTION_XH] = width >> 8; + config[GT911_CONFIG_DATA_RESOLUTION_YL] = height & 0xFF; + config[GT911_CONFIG_DATA_RESOLUTION_YH] = height >> 8; + config[GT911_CONFIG_DATA_TOUCH_NUMBER] = 5; + config[GT911_CONFIG_DATA_MODULE_SWITCH1] = (config[GT911_CONFIG_DATA_MODULE_SWITCH1] & ~0x3); + + config[GT911_CONFIG_DATA_SIZE - 2] = gt911_calcualte_config_data_checksum(config); + config[GT911_CONFIG_DATA_SIZE - 1] = 1; + /* + * for (uint8_t i = 0; i < 5; i++) { + * gt911_write_data(context, GT911_CONFIG, config, GT911_CONFIG_DATA_SIZE); + * } + */ + gt911_write_register(context, GT911_CMD, GT911_CMD_SOFT_RESET); + return status_success; +} + +hpm_stat_t gt911_read_touch_data(gt911_context_t *context, + gt911_touch_data_t *touch_data) +{ + hpm_stat_t stat = status_success; + + stat = gt911_read_data(context, GT911_STATUS, + (uint8_t *)touch_data, sizeof(gt911_touch_data_t)); + if (stat != status_success) { + return stat; + } + + gt911_write_register(context, GT911_STATUS, 0); + + return stat; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h new file mode 100644 index 0000000000..89b02c4e43 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GT911_H +#define HPM_GT911_H +#include "board.h" +#include "hpm_common.h" +#include "hpm_i2c_drv.h" + +#ifdef BOARD_GT911_ADDR +/* if i2c addres is specified by board, use it */ +#define GT911_I2C_ADDR BOARD_GT911_ADDR +/* no auto probe in this case */ +#define GT911_NO_AUTO_PROBE 1 +#else +#undef GT911_I2C_ADDR + +/* enable auto probe */ +#ifndef GT911_NO_AUTO_PROBE +#define GT911_NO_AUTO_PROBE 0 +#endif + +/* i2c device address candidates */ +#define GT911_I2C_ADDR0 (0x14U) +#define GT911_I2C_ADDR1 (0x5DU) +#endif + +#define GT911_PRODUCT_ID (0x313139U) +/* + * GT911 registers at operation mode + */ + +#define GT911_CMD (0x8040U) +#define GT911_CMD_READ_COORD_STAT (0U) +#define GT911_CMD_READ_RAW_DATA (1U) +#define GT911_CMD_SOFT_RESET (2U) +#define GT911_CMD_READ_SCREEN_OFF (5U) + +#define GT911_CONFIG (0x8047U) + +#define GT911_ID_B0 (0x8140U) +#define GT911_ID_B1 (0x8141U) +#define GT911_ID_B2 (0x8142U) +#define GT911_ID_B4 (0x8143U) +#define GT911_FW_VERSION_L (0x8144U) +#define GT911_FW_VERSION_H (0x8145U) +#define GT911_TOUCH_XL (0x8146U) +#define GT911_TOUCH_XH (0x8147U) +#define GT911_TOUCH_YL (0x8148U) +#define GT911_TOUCH_YH (0x8149U) +#define GT911_VENDOR_ID (0x814AU) +#define GT911_STATUS (0x814EU) +#define GT911_GET_STATUS_NUM_OF_POINTS(x) ((x) & 0xFU) +#define GT911_GET_STATUS_LARGE_DETECT(x) (((x) & 0x40U) >> 6) +#define GT911_GET_STATUS_BUFFER_STAT(x) (((x) & 0x80U) >> 7) +#define GT911_FIRST_POINT (0x814FU) + +#define GT911_MAX_TOUCH_POINTS (5U) +#define GT911_CONFIG_DATA_SIZE (186U) +#define GT911_CONFIG_DATA_RESOLUTION_XL (1U) +#define GT911_CONFIG_DATA_RESOLUTION_XH (2U) +#define GT911_CONFIG_DATA_RESOLUTION_YL (3U) +#define GT911_CONFIG_DATA_RESOLUTION_YH (4U) +#define GT911_CONFIG_DATA_TOUCH_NUMBER (5U) +#define GT911_CONFIG_DATA_MODULE_SWITCH1 (6U) + +typedef struct { + uint8_t track_id; + uint8_t x_l; + uint8_t x_h; + uint8_t y_l; + uint8_t y_h; + uint8_t size_l; + uint8_t size_h; + uint8_t reserved; +} gt911_touch_point_t; + +typedef struct { + uint8_t status; + gt911_touch_point_t points[GT911_MAX_TOUCH_POINTS]; +} gt911_touch_data_t; + +typedef struct { + I2C_Type *ptr; +} gt911_context_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * gt911 initialization routine + */ +hpm_stat_t gt911_init(gt911_context_t *context, uint16_t width, uint16_t height); + +/* + * gt911 read touch data + */ +hpm_stat_t gt911_read_touch_data(gt911_context_t *context, + gt911_touch_data_t *touch_data); + +/* + * gt911 read data + */ +hpm_stat_t gt911_read_data(gt911_context_t *context, uint16_t addr, + uint8_t *buf, uint32_t size); + +/* + * gt911 write value to given register + */ +hpm_stat_t gt911_write_register(gt911_context_t *context, + uint16_t reg, uint8_t val); + +/* + * gt911 read value of given register + */ +hpm_stat_t gt911_read_register(gt911_context_t *context, uint16_t reg, uint8_t *buf); + +/* + * gt911 read config data + */ +hpm_stat_t gt911_read_config(gt911_context_t *context, uint8_t *buf, uint8_t size); +#ifdef __cplusplus +} +#endif +#endif /* HPM_GT911_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c new file mode 100644 index 0000000000..afb9a2c08e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_touch.h" +#include "hpm_gpio_drv.h" +#include "hpm_gt911.h" + +gt911_context_t gt911 = {0}; + +hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points) +{ + hpm_stat_t stat = status_success; + gt911_touch_data_t touch_data = {0}; + uint8_t num, i; + + stat = gt911_read_touch_data(>911, &touch_data); + if (stat != status_success) { + printf("gt911 read data failed\n"); + return stat; + } + + num = GT911_GET_STATUS_NUM_OF_POINTS(touch_data.status); + *num_of_points = num; + if (num > 0 && num < GT911_MAX_TOUCH_POINTS) { + for (i = 0; i < num; i++) { + points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l; + points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l; + } + } + + gt911_write_register(>911, GT911_STATUS, 0); + return stat; +} + +void pull_int_pin(bool high) +{ + gpio_set_pin_output(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); + gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1); +} + +void float_int_pin(void) +{ + gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); +} + +hpm_stat_t touch_init(I2C_Type *i2c_ptr) +{ + hpm_stat_t stat = status_success; + + gt911.ptr = i2c_ptr; + + stat = gt911_init(>911, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT); + if (stat != status_success) { + return stat; + } + gt911_write_register(>911, GT911_CMD, GT911_CMD_READ_COORD_STAT); + + return stat; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h new file mode 100644 index 0000000000..9af46c35f0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_TOUCH_H +#define HPM_TOUCH_H + +#include "hpm_common.h" + +#if CONFIG_TOUCH_FT5406 +#include "hpm_ft5406.h" +#define HPM_TOUCH_MAX_POINTS (FT5406_MAX_TOUCH_POINTS) +#elif CONFIG_TOUCH_GT911 +#include "hpm_gt911.h" +#define HPM_TOUCH_MAX_POINTS (GT911_MAX_TOUCH_POINTS) +#else +#error "unknown touch type, either have CONFIG_FT5406 or CONFIG_GT911 defined" +#endif + +typedef struct { + uint16_t x; + uint16_t y; +} touch_point_t; + +#ifdef __cplusplus +extern "C" { +#endif + +hpm_stat_t touch_init(I2C_Type *i2c_ptr); + +hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points); + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_TOUCH_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.c b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.c new file mode 100644 index 0000000000..53a079b761 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*---------------------------------------------------------------------* + * Include + *---------------------------------------------------------------------*/ +#include "hpm_usb_device.h" +#include "hpm_misc.h" +#include "hpm_common.h" + +/* Initialize qtd */ +static void usb_qtd_init(dcd_qtd_t* p_qtd, void *data_ptr, uint16_t total_bytes) +{ + memset(p_qtd, 0, sizeof(dcd_qtd_t)); + + p_qtd->next = USB_SOC_DCD_QTD_NEXT_INVALID; + p_qtd->active = 1; + p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; + + if (data_ptr != NULL) + { + p_qtd->buffer[0] = (uint32_t)data_ptr; + for(uint8_t i = 1; i < USB_SOC_DCD_QHD_BUFFER_COUNT; i++) + { + p_qtd->buffer[i] |= ((p_qtd->buffer[i-1]) & 0xFFFFF000UL) + 4096U; + } + } +} + +/*---------------------------------------------------------------------* + * Device API + *---------------------------------------------------------------------*/ +dcd_qhd_t* usb_device_qhd_get(usb_device_handle_t *handle, uint8_t ep_idx) +{ + return &handle->dcd_data->qhd[ep_idx]; +} + +dcd_qtd_t* usb_device_qtd_get(usb_device_handle_t *handle, uint8_t ep_idx) +{ + return &handle->dcd_data->qtd[ep_idx]; +} + +void usb_device_bus_reset(usb_device_handle_t *handle, uint16_t ep0_max_packet_size) +{ + dcd_data_t *dcd_data = handle->dcd_data; + + usb_dcd_bus_reset(handle->regs, ep0_max_packet_size); + + /* Queue Head & Queue TD */ + memset(dcd_data, 0, sizeof(dcd_data_t)); + + /* Set up Control Endpoints (0 OUT, 1 IN) */ + dcd_data->qhd[0].zero_length_termination = dcd_data->qhd[1].zero_length_termination = 1; + dcd_data->qhd[0].max_packet_size = dcd_data->qhd[1].max_packet_size = ep0_max_packet_size; + dcd_data->qhd[0].qtd_overlay.next = dcd_data->qhd[1].qtd_overlay.next = USB_SOC_DCD_QTD_NEXT_INVALID; + + /* OUT only */ + dcd_data->qhd[0].int_on_setup = 1; +} + +bool usb_device_init(usb_device_handle_t *handle, uint32_t int_mask) +{ + /* Clear memroy */ + if (handle->dcd_data == NULL) { + return false; + } + + memset(handle->dcd_data, 0, sizeof(dcd_data_t)); + + /* Initialize controller in device mode */ + usb_dcd_init(handle->regs); + + /* Set endpoint list address */ + usb_dcd_set_edpt_list_addr(handle->regs, core_local_mem_to_sys_address(0, (uint32_t)handle->dcd_data->qhd)); + + /* Clear status */ + usb_clear_status_flags(handle->regs, usb_get_status_flags(handle->regs)); + + /* Enable interrupt mask */ + usb_enable_interrupts(handle->regs, int_mask); + + /* Connect */ + usb_dcd_connect(handle->regs); + + return true; +} + +void usb_device_deinit(usb_device_handle_t *handle) +{ + /* Clear memroy */ + memset(handle->dcd_data, 0, sizeof(dcd_data_t)); + + usb_dcd_deinit(handle->regs); + + for (int i = 0; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { + usb_dcd_edpt_close(handle->regs, (i | (usb_dir_in << 0x07))); + usb_dcd_edpt_close(handle->regs, (i | (usb_dir_out << 0x07))); + } +} + +uint32_t usb_device_status_flags(usb_device_handle_t *handle) +{ + return usb_get_status_flags(handle->regs); +} + +void usb_device_clear_status_flags(usb_device_handle_t *handle, uint32_t mask) +{ + usb_clear_status_flags(handle->regs, mask); +} + +uint32_t usb_device_interrupts(usb_device_handle_t *handle) +{ + return usb_get_interrupts(handle->regs); +} + +uint8_t usb_device_get_port_speed(usb_device_handle_t *handle) +{ + return usb_get_port_speed(handle->regs); +} + +uint8_t usb_device_get_suspend_status(usb_device_handle_t *handle) +{ + return usb_get_suspend_status(handle->regs); +} + +void usb_device_set_address(usb_device_handle_t *handle, uint8_t dev_addr) +{ + /* Response with status first before changing device address */ + usb_device_edpt_xfer(handle, 0 | usb_dir_in_mask, NULL, 0); + + usb_dcd_set_address(handle->regs, dev_addr); +} + +uint8_t usb_device_get_address(usb_device_handle_t *handle) +{ + return usb_dcd_get_device_addr(handle->regs); +} + +void usb_device_remote_wakeup(usb_device_handle_t *handle) +{ + usb_dcd_remote_wakeup(handle->regs); +} + +void usb_device_connect(usb_device_handle_t *handle) +{ + usb_dcd_connect(handle->regs); +} + +void usb_device_disconnect(usb_device_handle_t *handle) +{ + usb_dcd_disconnect(handle->regs); +} + +bool usb_device_get_port_ccs(usb_device_handle_t *handle) +{ + return usb_get_port_ccs(handle->regs); +} + +bool usb_device_get_port_reset_status(usb_device_handle_t *handle) +{ + return usb_get_port_reset_status(handle->regs); +} + +uint32_t usb_device_get_edpt_complete_status(usb_device_handle_t *handle) +{ + return usb_dcd_get_edpt_complete_status(handle->regs); +} + +void usb_device_clear_edpt_complete_status(usb_device_handle_t *handle, uint32_t mask) +{ + usb_dcd_clear_edpt_complete_status(handle->regs, mask); +} + +uint32_t usb_device_get_setup_status(usb_device_handle_t *handle) +{ + return usb_dcd_get_edpt_setup_status(handle->regs); +} + +void usb_device_clear_setup_status(usb_device_handle_t *handle, uint32_t mask) +{ + usb_dcd_clear_edpt_setup_status(handle->regs, mask); +} + +/*---------------------------------------------------------------------* + * Endpoint API + *---------------------------------------------------------------------*/ +bool usb_device_edpt_open(usb_device_handle_t *handle, usb_endpoint_config_t *config) +{ + uint8_t const epnum = config->ep_addr & 0x0f; + uint8_t const dir = (config->ep_addr & 0x80) >> 7; + uint8_t const ep_idx = 2 * epnum + dir; + + dcd_qhd_t *p_qhd; + + if (config->xfer == usb_xfer_isochronous) { + return false; + } + + /* Must not exceed max endpoint number */ + if (epnum >= USB_SOC_DCD_MAX_ENDPOINT_COUNT) { + return false; + } + + /* Prepare Queue Head */ + p_qhd = &handle->dcd_data->qhd[ep_idx]; + memset(p_qhd, 0, sizeof(dcd_qhd_t)); + + p_qhd->zero_length_termination = 1; + p_qhd->max_packet_size = config->max_packet_size; + p_qhd->qtd_overlay.next = USB_SOC_DCD_QTD_NEXT_INVALID; + + usb_dcd_edpt_open(handle->regs, config); + + return true; +} + +bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + uint8_t const ep_idx = 2 * epnum + dir; + dcd_qhd_t * p_qhd; + dcd_qtd_t * p_qtd; + + if (epnum == 0) + { + /* follows UM Setup packet handling using setup lockout mechanism + * wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out + */ + while(usb_dcd_get_edpt_setup_status(handle->regs) & HPM_BITSMASK(1, 0)) {} + } + + p_qhd = &handle->dcd_data->qhd[ep_idx]; + p_qtd = &handle->dcd_data->qtd[ep_idx]; + + /* Prepare qtd */ + if (buffer != NULL) { + buffer = (uint8_t *)core_local_mem_to_sys_address(0, (uint32_t)buffer); + } + + usb_qtd_init(p_qtd, (void *)buffer, total_bytes); + p_qtd->int_on_complete = true; + p_qhd->qtd_overlay.next = core_local_mem_to_sys_address(0, (uint32_t) p_qtd); /* link qtd to qhd */ + + usb_dcd_edpt_xfer(handle->regs, ep_idx); + + return true; +} + +void usb_device_edpt_stall(usb_device_handle_t *handle, uint8_t ep_addr) +{ + usb_dcd_edpt_stall(handle->regs, ep_addr); +} + +void usb_device_edpt_clear_stall(usb_device_handle_t *handle, uint8_t ep_addr) +{ + usb_dcd_edpt_clear_stall(handle->regs, ep_addr); +} + +void usb_device_edpt_close(usb_device_handle_t *handle, uint8_t ep_addr) +{ + usb_dcd_edpt_close(handle->regs, ep_addr); +} + +void usb_device_edpt_close_all(usb_device_handle_t *handle) +{ + int i; + + for (i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { + usb_device_edpt_close(handle, i); + } +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h new file mode 100644 index 0000000000..0bb9bc568f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_USB_DEVICE_H +#define HPM_USB_DEVICE_H + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_usb_drv.h" +#include "hpm_soc_feature.h" +/*---------------------------------------------------------------------* + * Macro Constant Declarations + *---------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------* + * Macro Typedef Declaration + *---------------------------------------------------------------------*/ + +/* Queue Transfer Descriptor */ +typedef struct { + /* Word 0: Next QTD Pointer */ + volatile uint32_t next; /* Next link pointer This field contains the physical memory address of the next dTD to be processed */ + + /* Word 1: qTQ Token */ + volatile uint32_t : 3 ; + volatile uint32_t xact_err : 1 ; + volatile uint32_t : 1 ; + volatile uint32_t buffer_err : 1 ; + volatile uint32_t halted : 1 ; + volatile uint32_t active : 1 ; + volatile uint32_t : 2 ; + volatile uint32_t iso_mult_override : 2 ; /* This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO. */ + volatile uint32_t : 3 ; + volatile uint32_t int_on_complete : 1 ; + volatile uint32_t total_bytes : 15 ; + volatile uint32_t : 0 ; + + /* Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page */ + volatile uint32_t buffer[USB_SOC_DCD_QHD_BUFFER_COUNT]; + + /*------------- DCD Area -------------*/ + volatile uint16_t expected_bytes; + volatile uint8_t reserved[2]; +} dcd_qtd_t; + +/* Queue Head */ +typedef struct { + /* Word 0: Capabilities and Characteristics */ + + volatile uint32_t : 15 ; /* Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed. */ + volatile uint32_t int_on_setup : 1 ; /* Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. */ + volatile uint32_t max_packet_size : 11 ; /* This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize) */ + volatile uint32_t : 2 ; + volatile uint32_t zero_length_termination : 1 ; /* This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length. */ + volatile uint32_t iso_mult : 2 ; + volatile uint32_t : 0 ; + + /* Word 1: Current qTD Pointer */ + volatile uint32_t qtd_addr; + + /* Word 2-9: Transfer Overlay */ + volatile dcd_qtd_t qtd_overlay; + + /* Word 10-11: Setup request (control OUT only) */ + volatile usb_control_request_t setup_request; + + /*--------------------------------------------------------------------* + * Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes + * thus there are 16 bytes padding free that we can make use of. + *--------------------------------------------------------------------*/ + volatile uint8_t reserved[16]; +} dcd_qhd_t; + +typedef struct { + dcd_qhd_t qhd[USB_SOS_DCD_MAX_QHD_COUNT]; + dcd_qtd_t qtd[USB_SOC_DCD_MAX_QTD_COUNT]; +} dcd_data_t; + +typedef struct { + USB_Type *regs; + dcd_data_t *dcd_data; +} usb_device_handle_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*---------------------------------------------------------------------* + * Exported Function Declarations + *---------------------------------------------------------------------*/ +/* Get a qhd of the specifed endpoint */ +dcd_qhd_t* usb_device_qhd_get(usb_device_handle_t *handle, uint8_t ep_idx); + +/* Get a qtd of the specifed endpoint */ +dcd_qtd_t* usb_device_qtd_get(usb_device_handle_t *handle, uint8_t ep_idx); + +/* USB bus reset */ +void usb_device_bus_reset(usb_device_handle_t *handle, uint16_t ep0_max_packet_size); + +/* Initialize controller to device mode */ +bool usb_device_init(usb_device_handle_t *handle, uint32_t int_mask); + +/* De-initialize controller */ +void usb_device_deinit(usb_device_handle_t *handle); + +/* Set Address request */ +void usb_device_set_address(usb_device_handle_t *handle, uint8_t dev_addr); + +/* Get device address */ +uint8_t usb_device_get_address(usb_device_handle_t *handle); + +/* Wake up host */ +void usb_device_remote_wakeup(usb_device_handle_t *handle); + +/* Connect by enabling internal pull-up resistor on D+/D- */ +void usb_device_connect(usb_device_handle_t *handle); + +/* Disconnect by disabling internal pull-up resistor on D+/D- */ +void usb_device_disconnect(usb_device_handle_t *handle); + +/* Configure an endpoint */ +bool usb_device_edpt_open(usb_device_handle_t *handle, usb_endpoint_config_t *config); + +/* Submit a transfe */ +bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes); + +/* Stall endpoint */ +void usb_device_edpt_stall(usb_device_handle_t *handle, uint8_t ep_addr); + +/* clear stall */ +void usb_device_edpt_clear_stall(usb_device_handle_t *handle, uint8_t ep_addr); + +/* close a specified endpoint */ +void usb_device_edpt_close(usb_device_handle_t *handle, uint8_t ep_addr); + +void usb_device_edpt_close_all(usb_device_handle_t *handle); + +uint32_t usb_device_status_flags(usb_device_handle_t *handle); + +void usb_device_clear_status_flags(usb_device_handle_t *handle, uint32_t mask); + +uint32_t usb_device_interrupts(usb_device_handle_t *handle); + +uint8_t usb_device_get_port_speed(usb_device_handle_t *handle); + +uint8_t usb_device_get_suspend_status(usb_device_handle_t *handle); + +bool usb_device_get_port_ccs(usb_device_handle_t *handle); + +bool usb_device_get_port_reset_status(usb_device_handle_t *handle); + +uint32_t usb_device_get_edpt_complete_status(usb_device_handle_t *handle); + +void usb_device_clear_edpt_complete_status(usb_device_handle_t *handle, uint32_t mask); + +uint32_t usb_device_get_setup_status(usb_device_handle_t *handle); + +void usb_device_clear_setup_status(usb_device_handle_t *handle, uint32_t mask); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* HPM_USB_DEVICE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c new file mode 100644 index 0000000000..7a4637558a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c @@ -0,0 +1,590 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_usb_host.h" +#include "hpm_misc.h" +#include "hpm_common.h" +#include "board.h" + +/*---------------------------------------------------------------------* + * Macros + *---------------------------------------------------------------------*/ +#define USB_QHD_TYP_SHIFT (1U) +#define USB_PERIOD_1MS (1U) +#define USB_PERIOD_2MS (2U) +#define USB_PERIOD_4MS (4U) +#define USB_PERIOD_8MS (8U) +#define USB_DEFAULT_ADDR (0U) +#define USB_HIGH_SPPED_INTERVAL_MAX (16) + +/* log2 of a value */ +static uint8_t usb_log2(uint32_t value) +{ + uint8_t result = 0; + + while (value >>= 1) { + result++; + } + + return result; +} + +/*****************************************************************************/ +/* list functions */ +/*****************************************************************************/ +static void usb_host_list_insert(hcd_link_t *current, hcd_link_t *new, uint8_t new_type) +{ + new->address = current->address; + current->address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)new) | (new_type << USB_QHD_TYP_SHIFT); +} + +static void usb_host_list_remove_qhd_by_addr(hcd_link_t* list_head, uint8_t dev_addr) +{ + hcd_qhd_t *qhd; + + for(hcd_link_t* prev = list_head; + !prev->terminate && (sys_address_to_core_local_mem(USB_HOST_MCU_CORE, usb_host_align32(prev->address)) != (uint32_t)list_head); + prev = (hcd_link_t *)sys_address_to_core_local_mem(USB_HOST_MCU_CORE, (uint32_t)usb_host_list_next(prev))) { + + /* TODO check type for ISO iTD and siTD */ + qhd = (hcd_qhd_t *)sys_address_to_core_local_mem(USB_HOST_MCU_CORE, (uint32_t)usb_host_list_next(prev)); + + if (qhd->dev_addr == dev_addr) { + /* TODO deactive all TD, wait for QHD to inactive before removal */ + prev->address = qhd->next.address; + + /* EHCI link the removed qhd to async head (which always reachable by Host Controller) */ + qhd->next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)list_head) | (usb_qtype_qhd << USB_QHD_TYP_SHIFT); + + if (qhd->int_smask) { + /* period list queue element is guarantee to be free in the next frame (1 ms) */ + qhd->used = 0; + } else { + /* async list use async advance handshake */ + /* mark as removing, will completely re-usable when async advance isr occurs */ + qhd->removing = 1; + } + } + } +} + +hcd_link_t* usb_host_list_next(hcd_link_t *p_link_pointer) +{ + return (hcd_link_t*)usb_host_align32(p_link_pointer->address); +} + +/*************************************************************/ +/* qhd functions */ +/*************************************************************/ +static hcd_qhd_t* usb_host_qhd_control(usb_host_handle_t *handle, uint8_t dev_addr) +{ + return &handle->hcd_data->control[dev_addr].qhd; +} + +hcd_qhd_t* usb_host_qhd_next(hcd_qhd_t const * p_qhd) +{ + return (hcd_qhd_t*)usb_host_align32(p_qhd->next.address); +} + +static hcd_qhd_t* usb_host_qhd_find_free(usb_host_handle_t *handle) +{ + for (uint32_t i = 0; i < USB_SOC_HCD_MAX_ENDPOINT_COUNT; i++) { + if (!handle->hcd_data->qhd_pool[i].used) { + return &handle->hcd_data->qhd_pool[i]; + } + } + + return NULL; +} + +static hcd_qhd_t* usb_host_qhd_get_from_addr(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) +{ + hcd_qhd_t* qhd_pool = handle->hcd_data->qhd_pool; + + for(uint32_t i = 0; i < USB_SOC_HCD_MAX_ENDPOINT_COUNT; i++) { + if ((qhd_pool[i].dev_addr == dev_addr) && + ep_addr == usb_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid)) { + return &qhd_pool[i]; + } + } + + return NULL; +} + +static bool usb_host_qhd_init(usb_host_handle_t *handle, hcd_qhd_t *p_qhd, uint8_t dev_addr, usb_desc_endpoint_t const * ep_desc) +{ + uint8_t const xfer_type = ep_desc->bmAttributes.xfer; + uint8_t const interval = ep_desc->bInterval; + + /* address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise) */ + if (dev_addr != 0) { + memset(p_qhd, 0, sizeof(hcd_qhd_t)); + } + + p_qhd->dev_addr = dev_addr; + p_qhd->fl_inactive_next_xact = 0; + p_qhd->ep_number = usb_edpt_number(ep_desc->bEndpointAddress); + p_qhd->ep_speed = handle->ep_speed; + p_qhd->data_toggle_control = (xfer_type == usb_xfer_control) ? 1 : 0; + p_qhd->head_list_flag = (dev_addr == USB_DEFAULT_ADDR) ? 1 : 0; /* addr0's endpoint is the static async list head */ + p_qhd->max_packet_size = ep_desc->wMaxPacketSize.size; + p_qhd->fl_ctrl_ep_flag = ((xfer_type == usb_xfer_control) && (p_qhd->ep_speed != usb_speed_high)) ? 1 : 0; + p_qhd->nak_reload = 0; + + if (usb_xfer_interrupt == xfer_type) { + if (usb_speed_high == p_qhd->ep_speed) { + if (interval > USB_HIGH_SPPED_INTERVAL_MAX) { + return false; + } + + if (interval < 4) { /* sub millisecond interval */ + p_qhd->interval_ms = 0; + p_qhd->int_smask = (interval == 1) ? USB_HOST_BIN8(11111111) : + (interval == 2) ? USB_HOST_BIN8(10101010) : USB_HOST_BIN8(01000100); + } else { + p_qhd->interval_ms = (uint8_t)MIN(1 << (interval - 4), 255); + p_qhd->int_smask = HPM_BITSMASK(1, interval % 8); + } + } else { + if (interval == 0) { + return false; + } + + /* Full/Low:(EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes */ + p_qhd->int_smask = 0x01; + p_qhd->fl_int_cmask = USB_HOST_BIN8(11100); + p_qhd->interval_ms = interval; + } + } else { + /* Bulk/Control -> smask = cmask = 0 */ + p_qhd->int_smask = p_qhd->fl_int_cmask = 0; + } + + p_qhd->fl_hub_addr = handle->hub_addr; + p_qhd->fl_hub_port = handle->hub_port; + p_qhd->mult = 1; + + /* HCD Management Data */ + p_qhd->used = 1; + p_qhd->removing = 0; + p_qhd->p_qtd_list_head = NULL; + p_qhd->p_qtd_list_tail = NULL; + p_qhd->pid = usb_edpt_dir(ep_desc->bEndpointAddress) ? usb_pid_in : usb_pid_out; /* PID for TD under this endpoint */ + + /* Active, but no TD list */ + p_qhd->qtd_overlay.halted = 0; + p_qhd->qtd_overlay.next.terminate = 1; + p_qhd->qtd_overlay.alternate.terminate = 1; + + if (usb_xfer_bulk == xfer_type && p_qhd->ep_speed == usb_speed_high && p_qhd->pid == usb_pid_out) { + p_qhd->qtd_overlay.ping_err = 1; /* Do PING for Highspeed Bulk OUT, EHCI */ + } + + return true; +} + +hcd_qhd_t* usb_host_qhd_async_head(usb_host_handle_t *handle) +{ + /* control qhd of dev0 is used as async head */ + return usb_host_qhd_control(handle, 0); +} + +bool usb_host_qhd_has_xact_error(hcd_qhd_t * p_qhd) +{ + return (p_qhd->qtd_overlay.buffer_err || p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err); +} + +hcd_link_t* usb_host_get_period_head(usb_host_handle_t *handle, uint8_t interval_ms) +{ + return (hcd_link_t*)&handle->hcd_data->period_head_arr[usb_log2(MIN(USB_HOST_FRAMELIST_SIZE, interval_ms))]; +} + +/*************************************************************/ +/* qtd functions */ +/*************************************************************/ +static hcd_qtd_t* usb_host_qtd_find_free(usb_host_handle_t *handle) +{ + for (uint32_t i = 0; i < USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT; i++) { + if (!handle->hcd_data->qtd_pool[i].used) { + return &handle->hcd_data->qtd_pool[i]; + } + } + + return NULL; +} + +static hcd_qtd_t* usb_host_qtd_next(hcd_qtd_t const * p_qtd) +{ + return (hcd_qtd_t*)usb_host_align32(p_qtd->next.address); +} + +static void usb_host_qtd_insert_to_qhd(hcd_qhd_t *p_qhd, hcd_qtd_t *p_qtd_new) +{ + if (p_qhd->p_qtd_list_head == NULL) { /* empty list */ + p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = p_qtd_new; + } else { + p_qhd->p_qtd_list_tail->next.address = (uint32_t)p_qtd_new; + p_qhd->p_qtd_list_tail = p_qtd_new; + } +} + +static void usb_host_qtd_init(hcd_qtd_t* p_qtd, void* buffer, uint16_t total_bytes) +{ + memset(p_qtd, 0, sizeof(hcd_qtd_t)); + + p_qtd->used = 1; + p_qtd->next.terminate = 1; /* init to null */ + p_qtd->alternate.terminate = 1; /* not used, always set to terminated */ + p_qtd->active = 1; + p_qtd->err_count = 3; + p_qtd->data_toggle = 0; + p_qtd->total_bytes = total_bytes; + p_qtd->expected_bytes = total_bytes; + + if (buffer != NULL) { + p_qtd->buffer[0] = (uint32_t)buffer; + + for(uint8_t i = 1; i < USB_SOC_HCD_QTD_BUFFER_COUNT; i++) { + p_qtd->buffer[i] |= usb_host_align4k(p_qtd->buffer[i-1]) + 4096UL; + } + } +} + +void usb_host_qtd_remove_1st_from_qhd(hcd_qhd_t *p_qhd) +{ + if (p_qhd->p_qtd_list_head == p_qhd->p_qtd_list_tail) { /* last TD --> make it NULL */ + p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = NULL; + } else { + p_qhd->p_qtd_list_head = usb_host_qtd_next(p_qhd->p_qtd_list_head); + } +} + +hcd_qtd_t* usb_host_qtd_control(usb_host_handle_t *handle, uint8_t dev_addr) +{ + return &handle->hcd_data->control[dev_addr].qtd; +} + +static void usb_host_init_async_list(usb_host_handle_t *handle) +{ + hcd_qhd_t *async_head = usb_host_qhd_async_head(handle); + + memset(async_head, 0, sizeof(hcd_qhd_t)); + + async_head->next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)async_head); /* circular list, next is itself */ + async_head->next.type = usb_qtype_qhd; + async_head->head_list_flag = 1; + async_head->qtd_overlay.halted = 1; + async_head->qtd_overlay.next.terminate = 1; + + usb_hcd_set_async_list_addr(handle->regs, core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)async_head)); +} + +static void usb_host_init_periodic_list(usb_host_handle_t *handle) +{ + hcd_link_t *framelist; + hcd_link_t *period_1ms; + + /* Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only */ + for(uint32_t i = 0; i < 4; i++) { + handle->hcd_data->period_head_arr[i].int_smask = 1; /* queue head in period list must have non-zero smask */ + handle->hcd_data->period_head_arr[i].qtd_overlay.halted = 1; /* dummy node, always inactive */ + } + + framelist = handle->hcd_data->period_framelist; + period_1ms = usb_host_get_period_head(handle, USB_PERIOD_1MS); + + /* all links --> period_head_arr[0] (1ms) + * 0, 2, 4, 6 etc --> period_head_arr[1] (2ms) + * 1, 5 --> period_head_arr[2] (4ms) + * 3 --> period_head_arr[3] (8ms) + */ + for(uint32_t i = 0; i < USB_HOST_FRAMELIST_SIZE; i++) { + framelist[i].address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)period_1ms); + framelist[i].type = usb_qtype_qhd; + } + + for(uint32_t i = 0; i < USB_HOST_FRAMELIST_SIZE; i+=2) { + usb_host_list_insert(framelist + i, usb_host_get_period_head(handle, USB_PERIOD_2MS), usb_qtype_qhd); + } + + for(uint32_t i = 1; i < USB_HOST_FRAMELIST_SIZE; i+=4) { + usb_host_list_insert(framelist + i, usb_host_get_period_head(handle, USB_PERIOD_4MS), usb_qtype_qhd); + } + + for(uint32_t i = 3; i < USB_HOST_FRAMELIST_SIZE; i+=8) { + usb_host_list_insert(framelist + i, usb_host_get_period_head(handle, USB_PERIOD_8MS), usb_qtype_qhd); + } + + period_1ms->terminate = 1; + + usb_hcd_set_periodic_list_addr(handle->regs, core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)framelist)); +} + +/* enable vbus output */ +static void usb_host_vbus_ctrl(usb_host_handle_t *handle) +{ + handle->hcd_vbus_ctrl_cb(handle->rhport, 1); +} + +bool usb_host_init(usb_host_handle_t *handle, uint32_t int_mask, uint16_t framelist_size) +{ + usb_hcd_init(handle->regs, int_mask, framelist_size); + memset(handle->hcd_data, 0, sizeof(hcd_data_t)); + usb_host_init_async_list(handle); + usb_host_init_periodic_list(handle); + usb_host_vbus_ctrl(handle); + return true; +} + +void usb_host_port_reset(usb_host_handle_t *handle) +{ + usb_hcd_port_reset(handle->regs); +} + +uint32_t usb_host_uframe_number(usb_host_handle_t *handle) +{ + return handle->hcd_data->uframe_number + usb_hcd_get_frame_index(handle->regs); +} + +bool usb_host_get_port_ccs(usb_host_handle_t *handle) +{ + return usb_get_port_ccs(handle->regs); +} + +bool usb_host_port_csc(usb_host_handle_t *handle) +{ + return usb_hcd_get_port_csc(handle->regs); +} + +uint32_t usb_host_status_flags(usb_host_handle_t *handle) +{ + return usb_get_status_flags(handle->regs); +} + +uint32_t usb_host_interrupts(usb_host_handle_t *handle) +{ + return usb_get_interrupts(handle->regs); +} + +void usb_host_clear_status_flags(usb_host_handle_t *handle, uint32_t status) +{ + usb_clear_status_flags(handle->regs, status); +} + +uint8_t usb_host_get_port_speed(usb_host_handle_t *handle) +{ + return usb_get_port_speed(handle->regs); +} + +/* Close all opened endpoint belong to this device */ +void usb_host_device_close(usb_host_handle_t *handle, uint8_t dev_addr) +{ + /* skip dev0 */ + if (dev_addr == USB_DEFAULT_ADDR) { + return; + } + + /* Remove from async list */ + usb_host_list_remove_qhd_by_addr((hcd_link_t*) usb_host_qhd_async_head(handle), dev_addr); + + /* Remove from all interval period list */ + for(uint8_t i = 0; i < ARRAY_SIZE(handle->hcd_data->period_head_arr); i++) { + usb_host_list_remove_qhd_by_addr((hcd_link_t*)&handle->hcd_data->period_head_arr[i], dev_addr); + } + + /* Async doorbell (EHCI for operational details) */ + usb_hcd_set_command(handle->regs, USB_USBCMD_IAA_MASK); +} + +/*---------------------------------------------------------------------* + * Control Pipe API + *---------------------------------------------------------------------*/ +bool usb_host_edpt_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) +{ + uint8_t const epnum = usb_edpt_number(ep_addr); + uint8_t const dir = usb_edpt_dir(ep_addr); + hcd_qhd_t* qhd; + hcd_qtd_t* qtd; + hcd_qhd_t *p_qhd; + hcd_qtd_t *p_qtd; + + if (buffer != NULL) { + buffer = (uint8_t *)core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)buffer); + } + + if (epnum == 0) { + qhd = usb_host_qhd_control(handle, dev_addr); + qtd = usb_host_qtd_control(handle, dev_addr); + + usb_host_qtd_init(qtd, buffer, buflen); + + /* first first data toggle is always 1 (data & setup stage) */ + qtd->data_toggle = 1; + qtd->pid = dir ? usb_pid_in : usb_pid_out; + + qtd->int_on_complete = 1; + qtd->next.terminate = 1; + + /* sw region */ + qhd->p_qtd_list_head = qtd; + qhd->p_qtd_list_tail = qtd; + + /* attach TD */ + qhd->qtd_overlay.next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)qtd); + } else { + p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); + p_qtd = usb_host_qtd_find_free(handle); + + if (p_qhd == NULL || p_qtd == NULL) { + return false; + } + + usb_host_qtd_init(p_qtd, buffer, buflen); + p_qtd->pid = p_qhd->pid; + + /* Insert TD to QH */ + usb_host_qtd_insert_to_qhd(p_qhd, p_qtd); + p_qhd->p_qtd_list_tail->int_on_complete = 1; + + /* attach head QTD to QHD start transferring */ + p_qhd->qtd_overlay.next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)p_qhd->p_qtd_list_head); + } + + return true; +} + +bool usb_host_setup_send(usb_host_handle_t *handle, uint8_t dev_addr, const uint8_t *setup_packet) +{ + uint32_t *p = NULL; + + hcd_qhd_t* qhd = &handle->hcd_data->control[dev_addr].qhd; + hcd_qtd_t* td = &handle->hcd_data->control[dev_addr].qtd; + + if (setup_packet != NULL) { + p = (uint32_t *)core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)setup_packet); + } + + usb_host_qtd_init(td, (void *)p, USB_SETUP_PACKET_LEN); + td->pid = usb_pid_setup; + td->int_on_complete = 1; + td->next.terminate = 1; + + /* sw region */ + qhd->p_qtd_list_head = td; + qhd->p_qtd_list_tail = td; + + /* attach TD */ + qhd->qtd_overlay.next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)td); + + return true; +} + +bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_endpoint_t const * ep_desc) +{ + hcd_qhd_t *p_qhd = NULL; + hcd_link_t *list_head = NULL; + + if (ep_desc->bmAttributes.xfer == usb_xfer_isochronous) { + return false; + } + + /* Prepare Queue Head */ + if ( ep_desc->bEndpointAddress == 0 ) { + p_qhd = usb_host_qhd_control(handle, dev_addr); + } else { + p_qhd = usb_host_qhd_find_free(handle); + } + + /* Initialize Qhd */ + usb_host_qhd_init(handle, p_qhd, dev_addr, ep_desc); + + switch (ep_desc->bmAttributes.xfer) { + case usb_xfer_control: + case usb_xfer_bulk: + list_head = (hcd_link_t*)usb_host_qhd_async_head(handle); /* control of dev0 is always present as async head */ + break; + + case usb_xfer_interrupt: + list_head = usb_host_get_period_head(handle, p_qhd->interval_ms); + break; + + case usb_xfer_isochronous: + break; + + default: + break; + } + + /* Insert to list */ + usb_host_list_insert(list_head, (hcd_link_t*)p_qhd, usb_qtype_qhd); + + return true; +} + +bool usb_host_pipe_queue_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes) +{ + hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); + hcd_qtd_t *p_qtd = usb_host_qtd_find_free(handle); + + if (p_qhd == NULL || p_qtd == NULL) { + return false; + } + + /* Initialize QTD */ + usb_host_qtd_init(p_qtd, buffer, total_bytes); + p_qtd->pid = p_qhd->pid; + + /* Insert TD to TD list */ + usb_host_qtd_insert_to_qhd(p_qhd, p_qtd); + + return true; +} + +bool usb_host_pipe_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete) +{ + hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); + + if (usb_host_pipe_queue_xfer(handle, dev_addr, ep_addr, buffer, total_bytes) == false) { + return false; + } + + if (int_on_complete) { + /* the just added qtd is pointed by list_tail */ + p_qhd->p_qtd_list_tail->int_on_complete = 1; + } + + /* attach head QTD to QHD start transferring */ + p_qhd->qtd_overlay.next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)p_qhd->p_qtd_list_head); + + return true; +} + +bool usb_host_edpt_busy(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) +{ + hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); + + return ((!p_qhd->qtd_overlay.halted) && (p_qhd->p_qtd_list_head != NULL)); +} + +bool usb_host_edpt_stalled(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) +{ + hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); + + return p_qhd->qtd_overlay.halted && !usb_host_qhd_has_xact_error(p_qhd); +} + +bool usb_host_edpt_clear_stall(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) +{ + hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); + + p_qhd->qtd_overlay.halted = 0; + + return true; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h new file mode 100644 index 0000000000..db6b81329f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_USB_HOST_H +#define HPM_USB_HOST_H + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_usb_drv.h" +#include "hpm_common.h" +#include "hpm_soc_feature.h" + +/*---------------------------------------------------------------------* + * Macros + *---------------------------------------------------------------------*/ +#define USB_HOST_BIN8(x) ((uint8_t) (0b##x)) +#define USB_BIN16(b1, b2) ((uint16_t) (0b##b1##b2)) +#define USB_BIN32(b1, b2, b3, b4) ((uint32_t) (0b##b1##b2##b3##b4)) + +#define USB_HCD_PERIODIC_ARR_COUNT (4U) +#define USB_HCD_MAX_CONNECTED_DEVICES (5U) +#define USB_SETUP_PACKET_LEN (8U) +/*---------------------------------------------------------------------* + * Enum Declarations + *---------------------------------------------------------------------*/ +typedef enum { + usb_max_itd = 4, + usb_max_sitd = 16 +} usb_max_xtd_t; + +typedef enum { + usb_qtype_itd = 0 , + usb_qtype_qhd, + usb_qtype_sitd, + usb_qtype_fstn +} usb_qtype_t; + +typedef enum { + usb_pid_out = 0 , + usb_pid_in , + usb_pid_setup +} usb_pid_t; + +typedef enum { + usb_speed_full = 0, + usb_speed_low , + usb_speed_high, + usb_speed_invalid = 0xff, +} usb_speed_t; + +typedef enum { + usb_cmd_pos_run_stop = 0, + usb_cmd_pos_framelist_szie = 2, + usb_cmd_pos_period_enable = 4, + usb_cmd_pos_async_enable = 5, + usb_cmd_pos_framelist_size_msb = 15, + usb_cmd_pos_interrupt_threshold = 16 +} usb_cmd_pos_t; + +typedef enum { + usb_portsc_mask_current_connect_status = HPM_BITSMASK(1, 0), + usb_portsc_mask_connect_status_change = HPM_BITSMASK(1, 1), + usb_portsc_mask_port_eanbled = HPM_BITSMASK(1, 2), + usb_portsc_mask_port_enable_chagne = HPM_BITSMASK(1, 3), + usb_portsc_mask_over_current_change = HPM_BITSMASK(1, 5), + usb_portsc_mask_port_reset = HPM_BITSMASK(1, 8), + + usb_portsc_mask_all = usb_portsc_mask_connect_status_change + | usb_portsc_mask_port_enable_chagne + | usb_portsc_mask_over_current_change +} usb_portsc_change_mask_t; + +/* Link pointer */ +typedef union { + volatile uint32_t address; + struct { + volatile uint32_t terminate : 1; + volatile uint32_t type : 2; + }; +} hcd_link_t; + +/* Queue Element Transfer Descriptor */ +/* Qtd is used to declare overlay in hcd_qhd_t */ +typedef struct +{ + /* Word 0: Next QTD Pointer */ + volatile hcd_link_t next; + + /* Word 1: Alternate Next QTD Pointer (not used) */ + union{ + volatile hcd_link_t alternate; + struct { + volatile uint32_t : 5; + volatile uint32_t used : 1; + volatile uint32_t : 10; + volatile uint32_t expected_bytes : 16; + }; + }; + + /* Word 2: qTQ Token */ + volatile uint32_t ping_err : 1 ; /* For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator */ + volatile uint32_t non_hs_split_state : 1 ; /* Used by HC to track the state of slipt transaction */ + volatile uint32_t non_hs_missed_uframe : 1 ; /* HC misses a complete slip transaction */ + volatile uint32_t xact_err : 1 ; /* Error (Timeout, CRC, Bad PID ... ) */ + volatile uint32_t babble_err : 1 ; /* Babble detected, also set Halted bit to 1 */ + volatile uint32_t buffer_err : 1 ; /* Data overrun/underrun error */ + volatile uint32_t halted : 1 ; /* Serious error or STALL received */ + volatile uint32_t active : 1 ; /* Start transfer, clear by HC when complete */ + volatile uint32_t pid : 2 ; /* 0: OUT, 1: IN, 2 Setup */ + volatile uint32_t err_count : 2 ; /* Error Counter of consecutive errors */ + volatile uint32_t current_page : 3 ; /* Index into the qTD buffer pointer list */ + volatile uint32_t int_on_complete : 1 ; /* Interrupt on complete */ + volatile uint32_t total_bytes : 15 ; /* Transfer bytes, decreased during transaction */ + volatile uint32_t data_toggle : 1 ; /* Data Toggle bit */ + + /* Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page */ + volatile uint32_t buffer[USB_SOC_HCD_QTD_BUFFER_COUNT]; +} hcd_qtd_t; + +/* Queue Head */ +typedef struct +{ + /* Word 0: Next QHD */ + hcd_link_t next; + + /* Word 1: Endpoint Characteristics */ + volatile uint32_t dev_addr : 7 ; /* device address */ + volatile uint32_t fl_inactive_next_xact : 1 ; /* Only valid for Periodic with Full/Slow speed */ + volatile uint32_t ep_number : 4 ; /* EP number */ + volatile uint32_t ep_speed : 2 ; /* 0: Full, 1: Low, 2: High */ + volatile uint32_t data_toggle_control : 1 ; /* 0: use DT in qHD, 1: use DT in qTD */ + volatile uint32_t head_list_flag : 1 ; /* Head of the queue */ + volatile uint32_t max_packet_size : 11 ; /* Max packet size */ + volatile uint32_t fl_ctrl_ep_flag : 1 ; /* 1 if is Full/Low speed control endpoint */ + volatile uint32_t nak_reload : 4 ; /* Used by HC */ + + /* Word 2: Endpoint Capabilities */ + volatile uint32_t int_smask : 8 ; /* Interrupt Schedule Mask */ + volatile uint32_t fl_int_cmask : 8 ; /* Split Completion Mask for Full/Slow speed */ + volatile uint32_t fl_hub_addr : 7 ; /* Hub Address for Full/Slow speed */ + volatile uint32_t fl_hub_port : 7 ; /* Hub Port for Full/Slow speed */ + volatile uint32_t mult : 2 ; /* Transaction per micro frame */ + + /* Word 3: Current qTD Pointer */ + volatile uint32_t qtd_addr; + + /* Word 4-11: Transfer Overlay */ + volatile hcd_qtd_t qtd_overlay; + + /*-------------------------------------------------------------------- + * Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes + * thus there are 16 bytes padding free that we can make use of. + *--------------------------------------------------------------------*/ + uint8_t used; + uint8_t removing; /* removed from async list, waiting for async advance */ + uint8_t pid; + uint8_t interval_ms; /* polling interval in frames (or millisecond) */ + + uint16_t total_xferred_bytes; /* number of bytes xferred until a qtd with ioc bit set */ + uint8_t reserved2[2]; + + hcd_qtd_t * volatile p_qtd_list_head; /* head of the scheduled TD list */ + hcd_qtd_t * volatile p_qtd_list_tail; /* tail of the scheduled TD list */ +} hcd_qhd_t; + +typedef struct +{ + hcd_link_t period_framelist[USB_HOST_FRAMELIST_SIZE]; + + /* for ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist) + * [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms + */ + hcd_qhd_t period_head_arr[USB_HCD_PERIODIC_ARR_COUNT]; + + /* Note control qhd of dev0 is used as head of async list */ + struct { + hcd_qhd_t qhd; + hcd_qtd_t qtd; + } control[USB_HCD_MAX_CONNECTED_DEVICES + 1]; + + hcd_qhd_t qhd_pool[USB_SOC_HCD_MAX_ENDPOINT_COUNT]; + hcd_qtd_t qtd_pool[USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT]; + + uint32_t uframe_number; +} hcd_data_t; + +typedef struct { + uint8_t rhport; + uint8_t ep_speed; + uint8_t hub_addr; + uint8_t hub_port; + USB_Type *regs; + hcd_data_t *hcd_data; + void (*hcd_vbus_ctrl_cb)(uint8_t rhport, uint8_t level); +} usb_host_handle_t; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__ ((packed)) +{ + uint8_t bLength ; + uint8_t bDescriptorType ; + uint8_t bEndpointAddress ; + + struct __attribute__ ((packed)) { + uint8_t xfer : 2; + uint8_t sync : 2; + uint8_t usage : 2; + uint8_t : 2; + } bmAttributes; + + struct __attribute__ ((packed)) { + uint16_t size : 11; + uint16_t hs_period_mult : 2; + uint16_t : 3; + } wMaxPacketSize; + + uint8_t bInterval; +} usb_desc_endpoint_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/* Get direction from Endpoint address */ +static inline usb_dir_t usb_edpt_dir(uint8_t addr) +{ + return (addr & usb_dir_in_mask) ? usb_dir_in : usb_dir_out; +} + +/* Get Endpoint number from address */ +static inline uint8_t usb_edpt_number(uint8_t addr) +{ + return (uint8_t)(addr & (~usb_dir_in_mask)); +} + +/* Get Endpoint address */ +static inline uint8_t usb_edpt_addr(uint8_t num, uint8_t dir) +{ + return (uint8_t)(num | (dir ? usb_dir_in_mask : 0)); +} + +static inline uint32_t usb_host_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); } +static inline uint32_t usb_host_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); } +static inline uint32_t usb_host_align4k (uint32_t value) { return (value & 0xFFFFF000UL); } +static inline uint32_t usb_host_offset4k(uint32_t value) { return (value & 0xFFFUL); } + +bool usb_host_qhd_has_xact_error (hcd_qhd_t * p_qhd); +bool usb_host_qhd_has_xact_error(hcd_qhd_t * p_qhd); +void usb_host_qtd_remove_1st_from_qhd(hcd_qhd_t *p_qhd); +hcd_link_t* usb_host_list_next(hcd_link_t *p_link_pointer); +hcd_link_t* usb_host_get_period_head(usb_host_handle_t *handle, uint8_t interval_ms); +hcd_qhd_t* usb_host_qhd_async_head(usb_host_handle_t *handle); +hcd_qhd_t* usb_host_qhd_next(hcd_qhd_t const * p_qhd); +hcd_qtd_t* usb_host_qtd_control(usb_host_handle_t *handle, uint8_t dev_addr); +uint32_t usb_host_uframe_number(usb_host_handle_t *handle); +uint32_t usb_host_status_flags(usb_host_handle_t *handle); +uint32_t usb_host_interrupts(usb_host_handle_t *handle); +void usb_host_clear_status_flags(usb_host_handle_t *handle, uint32_t status); +uint8_t usb_host_get_port_speed(usb_host_handle_t *handle); +void usb_host_port_reset(usb_host_handle_t *handle); +bool usb_host_init(usb_host_handle_t *handle, uint32_t int_mask, uint16_t framelist_size); +bool usb_host_get_port_ccs(usb_host_handle_t *handle); +bool usb_host_port_csc(usb_host_handle_t *handle); +void usb_host_device_close(usb_host_handle_t *handle, uint8_t dev_addr); +bool usb_host_edpt_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); +bool usb_host_setup_send(usb_host_handle_t *handle, uint8_t dev_addr, const uint8_t *setup_packet); +bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_endpoint_t const * ep_desc); +bool usb_host_pipe_queue_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes); +bool usb_host_pipe_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete); +bool usb_host_edpt_busy(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr); +bool usb_host_edpt_stalled(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr); +bool usb_host_edpt_clear_stall(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* HPM_USB_HOST_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h new file mode 100644 index 0000000000..c8df2f8399 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ACMP_DRV_H +#define HPM_ACMP_DRV_H + +#include "hpm_common.h" +#include "hpm_acmp_regs.h" + +/** + * @brief ACMP driver APIs + * @defgroup acmp_interface ACMP driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ + +/** + * @brief ACMP hysteresis level + */ +#define ACMP_HYST_LEVEL_0 (0U) +#define ACMP_HYST_LEVEL_1 (1U) +#define ACMP_HYST_LEVEL_2 (2U) +#define ACMP_HYST_LEVEL_3 (3U) + +/** + * @brief ACMP input channel number + */ +#define ACMP_INPUT_DAC_OUT (0U) +#define ACMP_INPUT_ANALOG_1 (1U) +#define ACMP_INPUT_ANALOG_2 (2U) +#define ACMP_INPUT_ANALOG_3 (3U) +#define ACMP_INPUT_ANALOG_4 (4U) +#define ACMP_INPUT_ANALOG_5 (5U) +#define ACMP_INPUT_ANALOG_6 (6U) +#define ACMP_INPUT_ANALOG_7 (7U) + +/** + * @brief ACMP output digital filter mode + */ +#define ACMP_FILTER_MODE_BYPASS (0U) +#define ACMP_FILTER_MODE_CHANGE_IMMEDIATELY (4U) +#define ACMP_FILTER_MODE_CHANGE_AFTER_FILTER (5U) +#define ACMP_FILTER_MODE_STABLE_LOW (6U) +#define ACMP_FILTER_MODE_STABLE_HIGH (7U) + +/** + * @brief ACMP rising/falling flage mask + */ +#define ACMP_EVENT_RISING_EDGE (1U) +#define ACMP_EVENT_FALLING_EDGE (2U) + +/** + * @brief ACMP channel config + */ + +typedef struct acmp_channel_config { + uint8_t plus_input; + uint8_t minus_input; + uint8_t filter_mode; + uint8_t hyst_level; + bool enable_cmp_output; + bool enable_window_mode; + bool invert_output; + bool enable_clock_sync; + bool bypass_filter; + bool enable_dac; + bool enable_hpmode; + uint16_t filter_length; /* ACMP output digital filter length in ACMP clock cycle */ +} acmp_channel_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ACMP channel config DAC output value + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] value DAC output value + */ +static inline void acmp_channel_config_dac(ACMP_Type *ptr, uint8_t ch, uint32_t value) +{ + ptr->CHANNEL[ch].DACCFG = ACMP_CHANNEL_DACCFG_DACCFG_SET(value); +} + +/** + * @brief ACMP channel clear status + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] mask : + * @arg ACMP_EVENT_RISING_EDGE: ACMP output rising flag + * @arg ACMP_EVENT_FALLING_EDGE: ACMP output fall flag + */ +static inline void acmp_channel_clear_status(ACMP_Type *ptr, uint8_t ch, uint32_t mask) +{ + ptr->CHANNEL[ch].SR = mask; +} + +/** + * @brief ACMP channel get status + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @retval ACMP channel's status + */ +static inline uint32_t acmp_channel_get_status(ACMP_Type *ptr, uint8_t ch) +{ + return ptr->CHANNEL[ch].SR; +} + +/** + * @brief ACMP channel enable DMA request + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] mask : + * @arg ACMP_EVENT_RISING_EDGE: ACMP output rising flag + * @arg ACMP_EVENT_FALLING_EDGE: ACMP output fall flag + * @param [in] enable: + * @arg true: enable + * @arg false: disable + */ +static inline void acmp_channel_dma_request_enable(ACMP_Type *ptr, uint8_t ch, + uint32_t mask, bool enable) +{ + ptr->CHANNEL[ch].DMAEN = (ptr->CHANNEL[ch].DMAEN & ~mask) + | (enable ? mask : 0); +} + +/** + * @brief ACMP channel enable IRQ + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] mask : + * @arg ACMP_EVENT_RISING_EDGE: ACMP output rising flag + * @arg ACMP_EVENT_FALLING_EDGE: ACMP output fall flag + * @param [in] enable: + * @arg true: enable + * @arg false: disable + */ +static inline void acmp_channel_enable_irq(ACMP_Type *ptr, uint8_t ch, + uint32_t mask, bool enable) +{ + ptr->CHANNEL[ch].IRQEN = (ptr->CHANNEL[ch].IRQEN & ~mask) + | (enable ? mask : 0); +} + +/** + * @brief ACMP channel enable DAC + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] enable: + * @arg true: enable + * @arg false: disable + */ +static inline void acmp_channel_enable_dac(ACMP_Type *ptr, uint8_t ch, bool enable) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_DACEN_MASK) + | ACMP_CHANNEL_CFG_DACEN_SET(enable); +} + +/** + * @brief ACMP channel enable high performance mode + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] enable: + * @arg true: enable + * @arg false: disable + */ +static inline void acmp_channel_enable_hpmode(ACMP_Type *ptr, uint8_t ch, bool enable) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HPMODE_MASK) + | ACMP_CHANNEL_CFG_HPMODE_SET(enable); +} + +/** + * @brief ACMP channel enable hysteresis level + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] level: ACMP hysteresis level + */ +static inline void acmp_channel_set_hyst(ACMP_Type *ptr, uint8_t ch, uint8_t level) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HYST_MASK) + | ACMP_CHANNEL_CFG_HYST_SET(level); +} + +/** + * @brief ACMP channel enable comparator + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] enable: + * @arg true: enable + * @arg false: disable + */ +static inline void acmp_channel_enable_cmp(ACMP_Type *ptr, uint8_t ch, bool enable) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPEN_MASK) + | ACMP_CHANNEL_CFG_CMPEN_SET(enable); +} + +/** + * @brief ACMP channel enable comparator output + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] enable: + * @arg true: enable + * @arg false: disable + */ +static inline void acmp_channel_enable_cmp_output(ACMP_Type *ptr, uint8_t ch, bool enable) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPOEN_MASK) + | ACMP_CHANNEL_CFG_CMPOEN_SET(enable); +} + +/** + * @brief ACMP channel bypass comparator output filter + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] enable: + * @arg true: bypass + * @arg false: not bypass + */ +static inline void acmp_channel_cmp_output_bypass_filter(ACMP_Type *ptr, uint8_t ch, bool enable) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_FLTBYPS_MASK) + | ACMP_CHANNEL_CFG_FLTBYPS_SET(!enable); +} + +/** + * @brief ACMP channel enable comparator window mode + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] enable: + * @arg true: enable + * @arg false: disable + */ +static inline void acmp_channel_enable_cmp_window_mode(ACMP_Type *ptr, uint8_t ch, bool enable) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_WINEN_MASK) + | ACMP_CHANNEL_CFG_WINEN_SET(enable); +} + +/** + * @brief ACMP channel invert comparator output + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] enable: + * @arg true: invert + * @arg false: not invert + */ +static inline void acmp_channel_invert_output(ACMP_Type *ptr, uint8_t ch, bool enable) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_OPOL_MASK) + | ACMP_CHANNEL_CFG_OPOL_SET(enable); +} + +/** + * @brief ACMP channel set comparator output filter mode + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] filter: ACMP output digital filter mode definition + */ +static inline void acmp_channel_set_filter_mode(ACMP_Type *ptr, uint8_t ch, uint8_t filter) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_FLTMODE_MASK) + | ACMP_CHANNEL_CFG_FLTMODE_SET(filter); +} + +/** + * @brief ACMP channel enable comparator output sync with clock + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] enable: + * @arg true: enable + * @arg false: disable + */ +static inline void acmp_channel_enable_sync(ACMP_Type *ptr, uint8_t ch, bool enable) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_SYNCEN_MASK) + | ACMP_CHANNEL_CFG_SYNCEN_SET(enable); +} + +/** + * @brief ACMP channel set comparator output filter length + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] filter_length: filter length in clock cycles + */ +static inline void acmp_channel_set_filter_length(ACMP_Type *ptr, uint8_t ch, uint16_t filter_length) +{ + ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_FLTLEN_MASK) + | ACMP_CHANNEL_CFG_FLTLEN_SET(filter_length); +} + +/** + * @brief ADC channel config + * + * @param [in] ptr ACMP base address + * @param [in] ch ACMP channel number + * @param [in] config: acmp_channel_config_t + * @param [in] enable: + * @arg true: enable comparator + * @arg false: disable comparator + * + * @retval hpm_stat_t + */ +hpm_stat_t acmp_channel_config(ACMP_Type *ptr, uint8_t ch, acmp_channel_config_t *config, bool enable); + +/** + * @brief ADC channel get default config setting + * + * @param [in] ptr ACMP base address + * @param [out] config: acmp_channel_config_t + */ +void acmp_channel_get_default_config(ACMP_Type *ptr, acmp_channel_config_t *config); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_ACMP_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h new file mode 100644 index 0000000000..a9a7c5e22d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ADC12_DRV_H +#define HPM_ADC12_DRV_H + +#include "hpm_common.h" +#include "hpm_adc12_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief ADC12 driver APIs + * @defgroup adc12_interface ADC12 driver APIs + * @ingroup adc_interfaces + * @{ + */ + +/** @brief Define ADC12 validity check for the signal type */ +#define ADC12_IS_SIGNAL_TYPE_INVALID(TYPE) (TYPE > (uint32_t)adc12_sample_signal_count) + +/** @brief Define ADC12 validity check for the channel number */ +#define ADC12_IS_CHANNEL_INVALID(PTR, CH) ((CH > ADC12_SOC_MAX_CH_NUM && CH != ADC12_SOC_TEMP_CH_NUM) || \ + ((uint32_t)PTR == ADC12_SOC_INVALID_TEMP_BASE && CH == ADC12_SOC_TEMP_CH_NUM)) + +/** @brief Define ADC12 validity check for the trigger number */ +#define ADC12_IS_TRIG_CH_INVLAID(CH) (CH > ADC12_SOC_MAX_TRIG_CH_NUM) + +/** @brief Define ADC12 validity check for the trigger length */ +#define ADC12_IS_TRIG_LEN_INVLAID(TRIG_LEN) (TRIG_LEN > ADC_SOC_MAX_TRIG_CH_LEN) + +/** @brief Define ADC12 validity check for the sequence length */ +#define ADC12_IS_SEQ_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_LEN)) + +/** @brief Define ADC12 validity check for the DMA buffer length in the sequence mode */ +#define ADC12_IS_SEQ_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES)) + +/** @brief Define ADC12 validity check for the DMA buffer length in the preemption mode */ +#define ADC12_IS_PMT_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)) + +/** @brief Define ADC12 sample signal types. */ +typedef enum { + adc12_sample_signal_single_ended = 0, + adc12_sample_signal_differential = 1, + adc12_sample_signal_count = 2 +} adc12_sample_signal_t; + +/** @brief Define ADC12 resolutions. */ +typedef enum { + adc12_res_6_bits = 0, + adc12_res_8_bits, + adc12_res_10_bits, + adc12_res_12_bits +} adc12_resolution_t; + +/** @brief Define ADC12 conversion modes. */ +typedef enum { + adc12_conv_mode_oneshot = 0, + adc12_conv_mode_period, + adc12_conv_mode_sequence, + adc12_conv_mode_preemption +} adc12_conversion_mode_t; + +/** @brief Define ADC12 irq events. */ +typedef enum { + /** This mask indicates that a trigger conversion is complete. */ + adc12_event_trig_complete = ADC12_INT_STS_TRIG_CMPT_MASK, + + /** This mask indicates that a conflict caused by software-triggered conversions. */ + adc12_event_trig_sw_conflict = ADC12_INT_STS_TRIG_SW_CFLCT_MASK, + + /** This mask indicates that a conflict caused by hardware-triggered conversions. */ + adc12_event_trig_hw_conflict = ADC12_INT_STS_TRIG_HW_CFLCT_MASK, + + /** This mask indicates that a conflict caused when bus reading from different channels. */ + adc12_event_read_conflict = ADC12_INT_STS_READ_CFLCT_MASK, + + /** This mask indicates that a conflict caused by sequence-triggered conversions. */ + adc12_event_seq_sw_conflict = ADC12_INT_STS_SEQ_SW_CFLCT_MASK, + + /** This mask indicates that a conflict caused by hardware-triggered conversions. */ + adc12_event_seq_hw_conflict = ADC12_INT_STS_SEQ_HW_CFLCT_MASK, + + /** This mask indicates that DMA is stopped currently. */ + adc12_event_seq_dma_abort = ADC12_INT_STS_SEQ_DMAABT_MASK, + + /** This mask indicates that all of the configured conversion(s) in a queue is(are) complete. */ + adc12_event_seq_full_complete = ADC12_INT_STS_SEQ_CMPT_MASK, + + /** This mask indicates that one of the configured conversion(s) in a queue is complete. */ + adc12_event_seq_single_complete = ADC12_INT_STS_SEQ_CVC_MASK, + + /** This mask indicates that DMA FIFO is full currently. */ + adc12_event_dma_fifo_full = ADC12_INT_STS_DMA_FIFO_FULL_MASK +} adc12_irq_event_t; + +/** @brief ADC12 common configuration struct. */ +typedef struct { + uint8_t res; + uint8_t conv_mode; + uint8_t wait_dis; + uint32_t adc_clk_div; + bool sel_sync_ahb; + bool adc_ahb_en; +} adc12_config_t; + +/** @brief ADC12 channel configuration struct. */ +typedef struct { + uint8_t ch; + uint8_t diff_sel; + uint16_t thshdh; + uint16_t thshdl; + uint8_t sample_cycle_shift; + uint32_t sample_cycle; +} adc12_channel_config_t; + +/** @brief ADC12 DMA configuration struct. */ +typedef struct { + uint32_t *start_addr; + uint32_t buff_len_in_4bytes; + uint32_t stop_pos; + bool stop_en; +} adc12_dma_config_t; + +/** @brief ADC12 DMA configuration struct for the sequence mode. */ +typedef struct { + uint32_t :4; + uint32_t result :12; + uint32_t seq_num :4; + uint32_t :4; + uint32_t adc_ch :5; + uint32_t :2; + uint32_t cycle_bit :1; +} adc12_seq_dma_data_t; + +/** @brief ADC12 DMA configuration struct for the preemption mode. */ +typedef struct { + uint32_t :4; + uint32_t result :12; + uint32_t trig_ch :2; + uint32_t :2; + uint32_t trig_index :4; + uint32_t adc_ch :5; + uint32_t :2; + uint32_t cycle_bit :1; +} adc12_pmt_dma_data_t; + +/** @brief ADC12 configuration struct for the period mode. */ +typedef struct { + uint32_t clk_src_freq_in_hz; + uint8_t ch; + uint8_t prescale; + uint8_t period_count; +} adc12_prd_config_t; + +/** @brief ADC12 queue configuration struct for the sequence mode. */ +typedef struct { + bool seq_int_en; + uint8_t ch; +} adc12_seq_queue_config_t; + +/** @brief ADC12 configuration struct for the sequence mode. */ +typedef struct { + adc12_seq_queue_config_t queue[ADC_SOC_SEQ_MAX_LEN]; + bool restart_en; + bool cont_en; + bool sw_trig_en; + bool hw_trig_en; + uint8_t seq_len; +} adc12_seq_config_t; + +/** @brief ADC12 trigger configuration struct for the preemption mode. */ +typedef struct { + bool inten[ADC_SOC_MAX_TRIG_CH_LEN]; + uint8_t adc_ch[ADC_SOC_MAX_TRIG_CH_LEN]; + uint8_t trig_ch; + uint8_t trig_len; +} adc12_pmt_config_t; + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @name Initialization and Deinitialization + * @{ + */ + +/** + * @brief Get a default configuration for an ADC12 instance. + * + * @param[out] config A pointer to the configuration struct of @ref adc12_config_t. + */ +void adc12_get_default_config(adc12_config_t *config); + +/** + * @brief Get a default configuration for an ADC12 channel. + * + * @param[out] config A pointer to the configuration struct of @ref adc12_channel_config_t. + */ +void adc12_get_channel_default_config(adc12_channel_config_t *config); + +/** + * @brief Initialize an ADC12 instance. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] config A pointer to the configuration struct of @ref adc12_config_t. + * @return A result of initializing an ADC12 instance. + * @retval status_success Initialize an ADC12 instance successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC12 instance unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config); + +/** + * @brief Initialize an ADC12 channel. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] config A pointer to the configuration struct of @ref adc12_channel_config_t. + * @return A result of initializing an ADC12 channel. + * @retval status_success Initialize an ADC12 channel successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC12 channel unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config); + +/** + * @brief Configure the the period mode for an ADC12 instance. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] config A pointer to the configuration struct of @ref adc12_prd_config_t. + * @return A result of configuring the the period mode for an ADC12 instance. + * @retval status_success Configure the the period mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the the period mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config); + +/** + * @brief Configure the the sequence mode for an ADC12 instance. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] config A pointer to configuration struct of @ref adc12_seq_config_t. + * @return A result of configuring the the sequence mode for an ADC12 instance. + * @retval status_success Configure the the sequence mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the the sequence mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config); + +/** + * @brief Configure the preemption mode for an ADC12 instance. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] config A pointer to configuration struct of @ref adc12_pmt_config_t. + * @return A result of configuring the preemption mode for an ADC12 instance. + * @retval status_success Configure the preemption mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the preemption mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config); + +/** @} */ + +/** + * @name DMA Control + * @{ + */ + +/** + * @brief Configure the stop position offset in the specified memory of DMA write operation for the the sequence mode. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] stop_pos A stop position offset. + */ +static inline void adc12_set_seq_stop_pos(ADC12_Type *ptr, uint16_t stop_pos) +{ + ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC12_SEQ_DMA_CFG_STOP_POS_MASK) + | ADC12_SEQ_DMA_CFG_STOP_POS_SET(stop_pos); +} + +/** + * @brief Configure the start address of DMA write operation for the preemption mode. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] addr A start address of DMA write operation. + */ +static inline void adc12_init_pmt_dma(ADC12_Type *ptr, uint32_t addr) +{ + ptr->TRG_DMA_ADDR = addr & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK; +} + +/** + * @brief Configure the start address of DMA write operation for the preemption mode. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] config A pointer to configuration struct of @ref adc12_dma_config_t. + * @return An implementation result of DMA initializing for the sequence mode + * @retval status_success Get the result of an ADC12 conversion in oneshot mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Get the result of an ADC12 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *config); + +/** @} */ + +/** + * @name Status + * @{ + */ + +/** + * @brief Get all ADC12 status flags. + * + * @param[in] ptr An ADC12 peripheral base address. + * @return A mask indicating all corresponding interrupt statuses. + * @retval A mask. Please refer to @ref adc12_irq_event_t. + */ +static inline uint32_t adc12_get_status_flags(ADC12_Type *ptr) +{ + return ptr->INT_STS; +} + +/** + * @brief Get the setting value of the WAIT_DIS bit. + * + * @param[in] ptr An ADC12 peripheral base address. + * @return Status that indicats whether the current setting of the WAIT_DIS bit in the BUF_RESULT register is disabled. + * @retval true It means that the WAIT_DIS bit is 1. + * @retval false It means that the WAIT_DIS bit is 0. + */ +static inline bool adc12_get_wait_dis_status(ADC12_Type *ptr) +{ + return ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0); +} + +/** + * @brief Get the status of a conversion validity. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] ch An ADC12 peripheral channel. + * @retval Status indicating the validity of the current conversion result. + * + * @note This function is only used when the WAIT_DIS bit in the BUF_RESULT register is 1. + */ +static inline bool adc12_get_conv_valid_status(ADC12_Type *ptr, uint8_t ch) +{ + return ADC12_BUS_RESULT_VALID_GET(ptr->BUS_RESULT[ch]); +} + +/** + * @brief Clear the status flags. + * + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] mask A mask that means the specified flags to be cleared. Please refer to @ref adc12_irq_event_t. + * + * @note Only the specified flags can be cleared by writing the INT_STS register. + */ +static inline void adc12_clear_status_flags(ADC12_Type *ptr, uint32_t mask) +{ + ptr->INT_STS |= mask; +} + +/** @} */ + +/** + * @name Interrupts + * @{ + */ + +/** + * @brief Enable interrupts. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] mask A mask indicating the specified ADC interrupt events. Please refer to @ref adc12_irq_event_t. + */ +static inline void adc12_enable_interrupts(ADC12_Type *ptr, uint32_t mask) +{ + ptr->INT_EN |= mask; +} + +/** + * @brief Disable interrupts. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] mask A mask indicating the specified interrupt events. Please refer to @ref adc12_irq_event_t. + */ +static inline void adc12_disable_interrupts(ADC12_Type *ptr, uint32_t mask) +{ + ptr->INT_EN &= ~mask; +} + +/** @} */ + +/** + * @name Trigger and Conversion + * @{ + */ + +/** + * @brief Trigger ADC coversions by software + * + * @param[in] ptr An ADC12 peripheral base address. + */ +void adc12_trigger_seq_by_sw(ADC12_Type *ptr); + +/** + * @brief Get the result in oneshot mode. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] ch An ADC12 peripheral channel. + * @param[out] result A pointer to an ADC12 conversion result. + * @return An implementation result of getting an ADC12 conversion result in oneshot mode. + * @retval status_success Get the result of an ADC12 conversion in oneshot mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Get the result of an ADC12 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result); + +/** + * @brief Get the result in the period mode. + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] ch An ADC12 peripheral channel. + * @param[out] result A pointer to a specified ADC12 conversion result + * @return An implementation of getting an ADC12 conversion result in the period mode. + * @retval status_success Get the result of an ADC12 conversion in the period mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Get the result of an ADC12 conversion in the period mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc12_get_prd_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +/** @} */ +#endif /* HPM_ADC12_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h new file mode 100644 index 0000000000..bb6f12e508 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ADC16_DRV_H +#define HPM_ADC16_DRV_H + +#include "hpm_common.h" +#include "hpm_adc16_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief ADC16 driver APIs + * @defgroup adc16_interface ADC16 driver APIs + * @ingroup adc_interfaces + * @{ + */ + +/** @brief Define ADC16 validity check for the channel number */ +#define ADC16_IS_CHANNEL_INVALID(CH) (CH > ADC16_SOC_MAX_CH_NUM && CH != ADC16_SOC_TEMP_CH_NUM) + +/** @brief Define ADC16 validity check for the trigger number */ +#define ADC16_IS_TRIG_CH_INVLAID(CH) (CH > ADC16_SOC_MAX_TRIG_CH_NUM) + +/** @brief Define ADC16 validity check for the trigger length */ +#define ADC16_IS_TRIG_LEN_INVLAID(TRIG_LEN) (TRIG_LEN > ADC_SOC_MAX_TRIG_CH_LEN) + +/** @brief Define ADC16 validity check for the sequence length */ +#define ADC16_IS_SEQ_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_LEN)) + +/** @brief Define ADC16 validity check for the DMA buffer length in the sequence mode */ +#define ADC16_IS_SEQ_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES)) + +/** @brief Define ADC16 validity check for the DMA buffer length in the preemption mode */ +#define ADC16_IS_PMT_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)) + +/** @brief Define ADC16 conversion modes. */ +typedef enum { + adc16_conv_mode_oneshot = 0, + adc16_conv_mode_period, + adc16_conv_mode_sequence, + adc16_conv_mode_preemption +} adc16_conversion_mode_t; + +/** @brief Define ADC16 irq events. */ +typedef enum { + /** This mask indicates that a trigger conversion is complete. */ + adc16_event_trig_complete = ADC16_INT_STS_TRIG_CMPT_MASK, + + /** This mask indicates that a conflict caused by software-triggered conversions. */ + adc16_event_trig_sw_conflict = ADC16_INT_STS_TRIG_SW_CFLCT_MASK, + + /** This mask indicates that a conflict caused by hardware-triggered conversions. */ + adc16_event_trig_hw_conflict = ADC16_INT_STS_TRIG_HW_CFLCT_MASK, + + /** This mask indicates that a conflict caused when bus reading from different channels. */ + adc16_event_read_conflict = ADC16_INT_STS_READ_CFLCT_MASK, + + /** This mask indicates that a conflict caused by sequence-triggered conversions. */ + adc16_event_seq_sw_conflict = ADC16_INT_STS_SEQ_SW_CFLCT_MASK, + + /** This mask indicates that a conflict caused by hardware-triggered conversions. */ + adc16_event_seq_hw_conflict = ADC16_INT_STS_SEQ_HW_CFLCT_MASK, + + /** This mask indicates that DMA is stopped currently. */ + adc16_event_seq_dma_abort = ADC16_INT_STS_SEQ_DMAABT_MASK, + + /** This mask indicates that all of the configured conversion(s) in a queue is(are) complete. */ + adc16_event_seq_full_complete = ADC16_INT_STS_SEQ_CMPT_MASK, + + /** This mask indicates that one of the configured conversion(s) in a queue is complete. */ + adc16_event_seq_single_complete = ADC16_INT_STS_SEQ_CVC_MASK, + + /** This mask indicates that DMA FIFO is full currently. */ + adc16_event_dma_fifo_full = ADC16_INT_STS_DMA_FIFO_FULL_MASK +} adc16_irq_event_t; + +/** @brief ADC16 common configuration struct. */ +typedef struct { + uint8_t conv_mode; + uint8_t wait_dis; + uint32_t adc_clk_div; + uint16_t conv_duration; + bool port3_rela_time; + bool sel_sync_ahb; + bool adc_ahb_en; +} adc16_config_t; + +/** @brief ADC16 channel configuration struct. */ +typedef struct { + uint8_t ch; + uint16_t thshdh; + uint16_t thshdl; + uint8_t sample_cycle_shift; + uint32_t sample_cycle; +} adc16_channel_config_t; + +/** @brief ADC16 DMA configuration struct. */ +typedef struct { + uint32_t *start_addr; + uint32_t buff_len_in_4bytes; + uint32_t stop_pos; + bool stop_en; +} adc16_dma_config_t; + +/** @brief ADC16 DMA configuration struct for the sequence mode. */ +typedef struct { + uint32_t result :16; + uint32_t seq_num :4; + uint32_t :4; + uint32_t adc_ch :5; + uint32_t :2; + uint32_t cycle_bit :1; +} adc16_seq_dma_data_t; + +/** @brief ADC16 DMA configuration struct for the preemption mode. */ +typedef struct { + uint32_t result :16; + uint32_t trig_ch :2; + uint32_t :2; + uint32_t trig_index :4; + uint32_t adc_ch :5; + uint32_t :2; + uint32_t cycle_bit :1; +} adc16_pmt_dma_data_t; + +/** @brief ADC16 configuration struct for the the period mode. */ +typedef struct { + uint32_t clk_src_freq_in_hz; + uint8_t ch; + uint8_t prescale; + uint8_t period_count; +} adc16_prd_config_t; + +/** @brief ADC16 queue configuration struct for the sequence mode. */ +typedef struct { + bool seq_int_en; + uint8_t ch; +} adc16_seq_queue_config_t; + +/** @brief ADC16 configuration struct for the sequence mode. */ +typedef struct { + adc16_seq_queue_config_t queue[ADC_SOC_SEQ_MAX_LEN]; + bool restart_en; + bool cont_en; + bool sw_trig_en; + bool hw_trig_en; + uint8_t seq_len; +} adc16_seq_config_t; + +/** @brief ADC16 trigger configuration struct for the preemption mode. */ +typedef struct { + bool inten[ADC_SOC_MAX_TRIG_CH_LEN]; + uint8_t adc_ch[ADC_SOC_MAX_TRIG_CH_LEN]; + uint8_t trig_ch; + uint8_t trig_len; +} adc16_pmt_config_t; + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @name Initialization and Deinitialization + * @{ + */ + +/** + * @brief Get a default configuration for an ADC16 instance. + * + * @param[out] config A pointer to the configuration struct of @ref adc16_config_t. + * + */ +void adc16_get_default_config(adc16_config_t *config); + +/** + * @brief Get a default configuration for an ADC16 Channel. + * + * @param[out] config A pointer to the configuration struct of @ref adc16_channel_config_t. + */ +void adc16_get_channel_default_config(adc16_channel_config_t *config); + +/** + * @brief Initialize an ADC16 instance. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] config A pointer to the configuration struct of @ref adc16_config_t. + * @return A result of initializing an ADC16 instance. + * @retval status_success Initialize an ADC16 instance successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC16 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config); + +/** + * @brief Initialize an ADC16 channel + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] config A pointer to the configuration struct of @ref adc16_channel_config_t. + * @return A result of initializing an ADC16 channel. + * @retval status_success Initialize an ADC16 channel successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC16 channel unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config); + +/** + * @brief Configure the the period mode for an ADC16 instance. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] config A pointer to the configuration struct of @ref adc16_prd_config_t. + * @return A result of configuring the the period mode for an ADC16 instance. + * @retval status_success Configure the the period mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the the period mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config); + +/** + * @brief Configure the sequence mode for an ADC16 instance. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] config A pointer to configuration struct of @ref adc16_seq_config_t. + * @return A result of configuring the sequence mode for an ADC16 instance. + * @retval status_success Configure the sequence mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the sequence mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc16_set_seq_config(ADC16_Type *ptr, adc16_seq_config_t *config); + +/** + * @brief Configure the preemption mode for an ADC16 instance. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] config A pointer to configuration struct of @ref adc16_pmt_config_t. + * @return A result of configuring the preemption mode for an ADC16 instance. + * @retval status_success Configure the preemption mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Configure the preemption mode unsuccessfully due to passing one or more invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config); + +/** + * @brief Set the queue enable control. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] trig_ch An ADC16 peripheral trigger channel. + * @param[in] enable A enable control + * @retval status_success Get the result of an ADC16 conversion in oneshot mode successfully. + * @retval status_invalid_argument Get the result of an ADC16 conversion in oneshot mode unsuccessfully due to passing invalid arguments. + */ +hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool enable); + +/** @} */ + +/** + * @name DMA Control + * @{ + */ + +/** + * @brief Configure the stop position offset in the specified memory of DMA write operation for the sequence mode. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] stop_pos A stop position offset. + */ +static inline void adc16_set_seq_stop_pos(ADC16_Type *ptr, uint16_t stop_pos) +{ + ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_STOP_POS_MASK) + | ADC16_SEQ_DMA_CFG_STOP_POS_SET(stop_pos); +} + +/** + * @brief Configure the start address of DMA write operation for the preemption mode. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] addr A start address of DMA write operation. + */ +static inline void adc16_init_pmt_dma(ADC16_Type *ptr, uint32_t addr) +{ + ptr->TRG_DMA_ADDR = addr & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK; +} + +/** + * @brief Configure the start address of DMA write operation for the preemption mode. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] config A pointer to configuration struct of @ref adc16_dma_config_t. + */ +void adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *config); + +/** @} */ + +/** + * @name Status + * @{ + */ + +/** + * @brief Get all ADC16 status flags. + * + * @param[in] ptr An ADC16 peripheral base address. + * @return A mask indicating all corresponding interrupt statuses. + * @retval A mask. Please refer to @ref adc16_irq_event_t. + */ +static inline uint32_t adc16_get_status_flags(ADC16_Type *ptr) +{ + return ptr->INT_STS; +} + +/** + * @brief Get the setting value of the WAIT_DIS bit. + * + * @param[in] ptr An ADC16 peripheral base address. + * @return Status that indicats whether the current setting of the WAIT_DIS bit in the BUF_RESULT register is disabled. + * @retval true It means that the WAIT_DIS bit is 1. + * @retval false It means that the WAIT_DIS bit is 0. + */ +static inline bool adc16_get_wait_dis_status(ADC16_Type *ptr) +{ + return ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0); +} + +/** + * @brief Get the status of a conversion validity. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] ch An ADC16 peripheral channel. + * @retval Status indicating the validity of the current conversion result. + * + * @note This function is only used when the WAIT_DIS bit in the BUF_RESULT register is 1. + */ +static inline bool adc16_get_conv_valid_status(ADC16_Type *ptr, uint8_t ch) +{ + return ADC16_BUS_RESULT_VALID_GET(ptr->BUS_RESULT[ch]); +} + +/** + * @brief Clear the status flags. + * + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] mask A mask that means the specified flags to be cleared. Please refer to @ref adc16_irq_event_t. + * + * @note Only the specified flags can be cleared by writing the INT_STS register. + */ +static inline void adc16_clear_status_flags(ADC16_Type *ptr, uint32_t mask) +{ + ptr->INT_STS |= mask; +} + +/** @} */ + +/** + * @name Interrupts + * @{ + */ + +/** + * @brief Enable interrupts. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] mask A mask indicating the specified ADC interrupt events. Please refer to @ref adc16_irq_event_t. + */ +static inline void adc16_enable_interrupts(ADC16_Type *ptr, uint32_t mask) +{ + ptr->INT_EN |= mask; +} + +/** + * @brief Disable interrupts. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] mask A mask indicating the specified interrupt events. Please refer to @ref adc16_irq_event_t. + */ +static inline void adc16_disable_interrupts(ADC16_Type *ptr, uint32_t mask) +{ + ptr->INT_EN &= ~mask; +} + +/** @} */ + +/** + * @name Trigger and Conversion + * @{ + */ + +/** + * @brief Trigger ADC coversions by software + * + * @param[in] ptr An ADC16 peripheral base address. + */ +void adc16_trigger_seq_by_sw(ADC16_Type *ptr); + +/** + * @brief Get the result in oneshot mode. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] ch An ADC16 peripheral channel. + * @param[out] result A pointer to an ADC16 conversion result. + * @return An implementation result of getting an ADC16 conversion result in oneshot mode. + * @retval status_success Get the result of an ADC16 conversion in oneshot mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Get the result of an ADC16 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc16_get_oneshot_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result); + +/** + * @brief Get the result in the period mode. + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] ch An ADC16 peripheral channel. + * @param[out] result A pointer to a specified ADC16 conversion result + * @return An implementation of getting an ADC16 conversion result in the period mode. + * @retval status_success Get the result of an ADC16 conversion in the period mode successfully. Please refert to @ref hpm_stat_t. + * @retval status_invalid_argument Get the result of an ADC16 conversion in the period mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. + */ +hpm_stat_t adc16_get_prd_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +/** @} */ +#endif /* HPM_ADC16_DRV_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h new file mode 100644 index 0000000000..0bc21c3eca --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BACC_DRV_H +#define HPM_BACC_DRV_H + +#include "hpm_common.h" +#include "hpm_bacc_regs.h" + +/** + * + * @brief BACC driver APIs + * @defgroup bacc_interface BACC driver APIs + * @ingroup io_interfaces + * @{ + */ + +/* @brief Timing gap ratios */ +typedef enum { + bacc_ratio_0 = 0, + bacc_ratio_1_32768 = 1, + bacc_ratio_1_16384 = 2, + bacc_ratio_1_8192 = 3, + bacc_ratio_1_4096 = 4, + bacc_ratio_1_2048 = 5, + bacc_ratio_1_1024 = 6, + bacc_ratio_1_512 = 7, + bacc_ratio_1_256 = 8, + bacc_ratio_1_128 = 9, + bacc_ratio_1_64 = 10, + bacc_ratio_1_32 = 11, + bacc_ratio_1_16 = 12, + bacc_ratio_1_8 = 13, + bacc_ratio_1_4 = 14, + bacc_ratio_1_2 = 15, +} bacc_ratio_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * brief set timing gap after rising edge + * + * @param[in] ptr BACC base address + * @param[in] ratio Ratio of guard band after rising edge + * @param[in] offset Guard band after rising edge (16 bits) + */ +static inline void bacc_timing_gap_post(BACC_Type *ptr, bacc_ratio_t ratio, uint16_t offset) +{ + ptr->PRE_TIME = BACC_PRE_TIME_POST_RATIO_SET(ratio) + | BACC_PRE_TIME_POST_OFFSET_SET(offset); +} + +/* + * brief set timing gap before rising edge + * + * @param[in] ptr BACC base address + * @param[in] ratio Ratio of guard band before rising edge + * @param[in] offset Guard band before rising edge (16 bits) + */ +static inline void bacc_timing_gap_pre(BACC_Type *ptr, bacc_ratio_t ratio, uint16_t offset) +{ + ptr->PRE_TIME = BACC_PRE_TIME_PRE_RATIO_SET(ratio) + | BACC_PRE_TIME_PRE_OFFSET_SET(offset); +} + +/* + * brief disable fast read + * + * @param[in] ptr BACC base address + */ +static inline void bacc_disable_fast_read(BACC_Type *ptr) +{ + ptr->CONFIG &= ~BACC_CONFIG_FAST_READ_MASK; +} + +/* + * brief enable fast read + * + * @param[in] ptr BACC base address + */ +static inline void bacc_enable_fast_read(BACC_Type *ptr) +{ + ptr->CONFIG |= BACC_CONFIG_FAST_READ_MASK; +} + +/* + * brief disable fast wirte + * + * @param[in] ptr BACC base address + */ +static inline void bacc_disable_fast_write(BACC_Type *ptr) +{ + ptr->CONFIG &= ~BACC_CONFIG_FAST_WRITE_MASK; +} + +/* + * brief enable fast wirte + * + * @param[in] ptr BACC base address + */ +static inline void bacc_enable_fast_write(BACC_Type *ptr) +{ + ptr->CONFIG |= BACC_CONFIG_FAST_WRITE_MASK; +} + +/* + * brief set timing of access + * + * @param[in] ptr BACC base address + * @param[in] timing Time in APB clock cycles (16 bits) + */ +static inline void bacc_set_timing(BACC_Type *ptr, uint16_t timing) +{ + ptr->CONFIG = (ptr->CONFIG & ~(BACC_CONFIG_TIMING_MASK)) + | BACC_CONFIG_TIMING_SET(timing); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_BACC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h new file mode 100644 index 0000000000..3ce4af2461 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BKEY_DRV_H +#define HPM_BKEY_DRV_H + +#include "hpm_common.h" +#include "hpm_bkey_regs.h" + +/** + * + * @brief BKEY driver APIs + * @defgroup bkey_interface BKEY driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Lock type + */ +typedef enum bkey_lock_type { + bkey_lock_write = BKEY_ECC_WLOCK_MASK, + bkey_lock_read = BKEY_ECC_RLOCK_MASK, + bkey_lock_both = BKEY_ECC_RLOCK_MASK | BKEY_ECC_WLOCK_MASK, +} bkey_lock_type_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief bkey set key content + * + * Program key content + * + * @param[in] ptr BKEY base address + * @param[in] key Key index + * @param[in] start Key content data start index + * @param[in] data pointer of actual data to be programmed + * @param[in] size data total size in 32-bit + */ +static inline void bkey_set_key_data(BKEY_Type *ptr, uint8_t key, uint8_t start, uint32_t *data, uint8_t size) +{ + for (uint8_t i = 0; i < size; i++) { + ptr->KEY[key].DATA[start + i] = *(data + i); + } +} + +/** + * @brief bkey fetch key content + * + * Fetch key content + * + * @param[in] ptr BKEY base address + * @param[in] key key index + * @param[in] start key content data start index + * @param[in] data pointer of buffer to received key content + * @param[in] size data total size in 32-bit + */ +static inline void bkey_get_key_data(BKEY_Type *ptr, uint8_t key, uint8_t start, uint32_t *data, uint8_t size) +{ + for (uint8_t i = 0; i < size; i++) { + *(data + i) = ptr->KEY[key].DATA[start + i]; + } +} + +/** + * @brief bkey lock key + * + * Feed correct ecc data of current key content and lock it + * + * @param[in] ptr BKEY base address + * @param[in] key key index + * @param[in] lock lock type + * @param[in] ecc ecc value of current key content + */ +static inline void bkey_lock(BKEY_Type *ptr, uint8_t key, bkey_lock_type_t lock, uint16_t ecc) +{ + ptr->ECC[key] = BKEY_ECC_ECC_SET(ecc) | lock; +} + +/** + * @brief bkey select key + * + * Select which key to use + * + * @param[in] ptr BKEY base address + * @param[in] key key index + * @arg 0 select key0 in secure mode, key1 in non-secure mode + * @arg 1 select key1 in secure or non-secure mode + */ +static inline void bkey_select_key(BKEY_Type *ptr, uint8_t key) +{ + ptr->SELECT = BKEY_SELECT_SELECT_SET(key); +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BKEY_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bpor_drv.h new file mode 100644 index 0000000000..88d014f13b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bpor_drv.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BPOR_DRV_H +#define HPM_BPOR_DRV_H + +#include "hpm_common.h" +#include "hpm_bpor_regs.h" + +/** + * + * @brief BPOR driver APIs + * @defgroup bpor_interface BPOR driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +/** @brief Define BPOR power on cause */ +typedef enum { + bpor_power_on_cause_wbutn = 0, + bpor_power_on_cause_safety_violation = 1, + bpor_power_on_cause_rtc_0 = 2, + bpor_power_on_cause_rtc_1 = 3, + bpor_power_on_cause_gpio = 4 +} bpor_power_on_cause_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get power on cause + * + * @param[in] ptr BPOR base address + * @retval POR_CAUSE register value + */ +static inline uint32_t bpor_get_power_on_cause(BPOR_Type *ptr) +{ + return ptr->POR_CAUSE; +} + +/** + * @brief Select power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause bpor_power_on_cause_t + */ +static inline void bpor_select_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT |= 1 << cause; +} + +/** + * @brief Enable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Disable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Set power down counter + * + * @param[in] ptr BPOR base address + * @param[in] counter counter value + */ +static inline void bpor_set_power_down_counter(BPOR_Type *ptr, uint16_t counter) +{ + ptr->POR_CONTROL = BPOR_POR_CONTROL_COUNTER_SET(counter); +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BPOR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h new file mode 100644 index 0000000000..66145706b4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BUTN_DRV_H +#define HPM_BUTN_DRV_H + +#include "hpm_common.h" +#include "hpm_butn_regs.h" + +/** + * + * @brief BUTN driver APIs + * @defgroup butn_interface BUTN driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +#define BUTN_EVENT_POWER_PRESSED (BUTN_BTN_STATUS_PBTN_SET(1)) +#define BUTN_EVENT_POWER_PRESSED_HOLD_0_5_S (BUTN_BTN_STATUS_PBTN_SET(2)) +#define BUTN_EVENT_POWER_PRESSED_HOLD_8_S (BUTN_BTN_STATUS_PBTN_SET(4)) +#define BUTN_EVENT_POWER_PRESSED_HOLD_16_S (BUTN_BTN_STATUS_PBTN_SET(8)) + +#define BUTN_EVENT_WAKE_PRESSED (BUTN_BTN_STATUS_WBTN_SET(1)) +#define BUTN_EVENT_WAKE_PRESSED_HOLD_0_5_S (BUTN_BTN_STATUS_WBTN_SET(2)) +#define BUTN_EVENT_WAKE_PRESSED_HOLD_8_S (BUTN_BTN_STATUS_WBTN_SET(4)) +#define BUTN_EVENT_WAKE_PRESSED_HOLD_16_S (BUTN_BTN_STATUS_WBTN_SET(8)) + +#define BUTN_EVENT_WAKE_POWER_PRESSED (BUTN_BTN_STATUS_DBTN_SET(1)) +#define BUTN_EVENT_WAKE_POWER_PRESSED_HOLD_0_5_S (BUTN_BTN_STATUS_DBTN_SET(2)) +#define BUTN_EVENT_WAKE_POWER_PRESSED_HOLD_8_S (BUTN_BTN_STATUS_DBTN_SET(4)) +#define BUTN_EVENT_WAKE_POWER_PRESSED_HOLD_16_S (BUTN_BTN_STATUS_DBTN_SET(8)) + +#define BUTN_EVENT_POWER_CLICKED (BUTN_BTN_STATUS_PCLICK_SET(1)) +#define BUTN_EVENT_POWER_CLICKED_X2 (BUTN_BTN_STATUS_PCLICK_SET(2)) +#define BUTN_EVENT_POWER_CLICKED_X3 (BUTN_BTN_STATUS_PCLICK_SET(4)) + +#define BUTN_EVENT_POWER_CLICKED_WAKE_HELD (BUTN_BTN_STATUS_XPCLICK_SET(1)) +#define BUTN_EVENT_POWER_CLICKED_X2_WAKE_HELD (BUTN_BTN_STATUS_XPCLICK_SET(2)) +#define BUTN_EVENT_POWER_CLICKED_X3_WAKE_HELD (BUTN_BTN_STATUS_XPCLICK_SET(4)) + +#define BUTN_EVENT_WAKE_CLICKED (BUTN_BTN_STATUS_WCLICK_SET(1)) +#define BUTN_EVENT_WAKE_CLICKED_X2 (BUTN_BTN_STATUS_WCLICK_SET(2)) +#define BUTN_EVENT_WAKE_CLICKED_X3 (BUTN_BTN_STATUS_WCLICK_SET(4)) + +#define BUTN_EVENT_WAKE_CLICKED_POWER_HELD (BUTN_BTN_STATUS_XWCLICK_SET(1)) +#define BUTN_EVENT_WAKE_CLICKED_X2_POWER_HELD (BUTN_BTN_STATUS_XWCLICK_SET(2)) +#define BUTN_EVENT_WAKE_CLICKED_X3_POWER_HELD (BUTN_BTN_STATUS_XWCLICK_SET(4)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get status + * + * @param[in] ptr BUTN base address + * @retval status mask in 32 bits, please refer to BUTN_EVENT_* macros + */ +static inline uint32_t butn_get_status(BUTN_Type *ptr) +{ + return ptr->BTN_STATUS; +} + +/** + * @brief Enable interrupt with mask + * + * @param[in] ptr BUTN base address + * @param[in] mask Mask of interrupts to be enabled, please refer to BUTN_EVENT_* macros + */ +static inline void butn_enable_irq(BUTN_Type *ptr, uint32_t mask) +{ + ptr->BTN_IRQ_MASK |= mask; +} + +/** + * @brief Disable interrupt with mask + * + * @param[in] ptr BUTN base address + * @param[in] mask Mask of interrupts to be disabled, please refer to BUTN_EVENT_* macros + */ +static inline void butn_disable_irq(BUTN_Type *ptr, uint32_t mask) +{ + ptr->BTN_IRQ_MASK &= ~mask; +} + +/** + * @brief Set intense of PLED and RLED/WLED + * + * @param[in] ptr BUTN base address + * @param[in] intense Intense value (0~15) + */ +static inline void butn_set_intense(BUTN_Type *ptr, uint8_t intense) +{ + ptr->LED_INTENSE = BUTN_LED_INTENSE_PLED_SET(intense) + | BUTN_LED_INTENSE_RLED_SET(intense); +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BUTN_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h new file mode 100644 index 0000000000..9e4899bcaf --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_CAM_DRV_H +#define HPM_CAM_DRV_H + +#include "hpm_common.h" +#include "hpm_display_common.h" +#include "hpm_cam_regs.h" + +/** + * @brief CAM driver APIs + * @defgroup cam_interface CAM driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief CAM data store mode + */ +#define CAM_DATA_STORE_MODE_NORMAL (0U) +#define CAM_DATA_STORE_MODE_Y_UV_PLANES (CAM_CR1_STORAGE_MODE_SET(1)) +#define CAM_DATA_STORE_MODE_Y_ONLY (CAM_CR1_STORAGE_MODE_SET(2)) +#define CAM_DATA_STORE_MODE_BINARY (CAM_CR1_STORAGE_MODE_SET(3)) + +/** + * @brief CAM sensor bitwidth + */ +#define CAM_SENSOR_BITWIDTH_8BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(0)) +#define CAM_SENSOR_BITWIDTH_10BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(1)) + +/** + * @brief CAM IRQ flag + */ +#define CAM_IRQ_UNSUPPORTED_CONFIGURATION (CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) +#define CAM_IRQ_HIST_CALCULATION_DONE (CAM_INT_EN_HIST_DONE_INT_EN_MASK) +#define CAM_IRQ_HRESPONSE_ERROR (CAM_INT_EN_HRESP_ERR_EN_MASK) +#define CAM_IRQ_END_OF_FRAME (CAM_INT_EN_EOF_INT_EN_MASK) +#define CAM_IRQ_STAT_FIFO_OVERRUN (CAM_INT_EN_SF_OR_INT_EN_MASK) +#define CAM_IRQ_RX_FIFO_OVERRUN (CAM_INT_EN_RF_OR_INT_EN_MASK) +#define CAM_IRQ_STAT_FIFO_DMA_TRANSFER_DONE (CAM_INT_EN_SFF_DMA_DONE_INT_EN_MASK) +#define CAM_IRQ_FB2_DMA_TRANSFER_DONE (CAM_INT_EN_FB2_DMA_DONE_INT_EN_MASK) +#define CAM_IRQ_FB1_DMA_TRANSFER_DONE (CAM_INT_EN_FB1_DMA_DONE_INT_EN_MASK) +#define CAM_IRQ_START_OF_FRAME (CAM_INT_EN_SOF_INT_EN_MASK) + +/** + * @brief CAM status flag + */ +#define CAM_STATUS_UNSUPPORTED_CONFIGURATION (CAM_STA_ERR_CL_BWID_CFG_MASK) +#define CAM_STATUS_HIST_CALCULATION_DONE (CAM_STA_HIST_DONE_MASK) +#define CAM_STATUS_STAT_FIFO_OVERRUN (CAM_STA_SF_OR_INT_MASK) +#define CAM_STATUS_RX_FIFO_OVERRUN (CAM_STA_RF_OR_INT_MASK) +#define CAM_STATUS_STAT_FIFO_DMA_TRANSFER_DONE (CAM_STA_DMA_TSF_DONE_SFF_MASK) +#define CAM_STATUS_STAT_FIFO_FULL (CAM_STA_STATFF_INT_MASK) +#define CAM_STATUS_FB2_DMA_TRANSFER_DONE (CAM_STA_DMA_TSF_DONE_FB2_MASK) +#define CAM_STATUS_FB1_DMA_TRANSFER_DONE (CAM_STA_DMA_TSF_DONE_FB1_MASK) +#define CAM_STATUS_RX_FIFO_FULL (CAM_STA_RXFF_INT_MASK) +#define CAM_STATUS_END_OF_FRAME (CAM_STA_EOF_INT_MASK) +#define CAM_STATUS_START_OF_FRAME (CAM_STA_SOF_INT_MASK) +#define CAM_STATUS_HRESPONSE_ERROR (CAM_STA_HRESP_ERR_INT_MASK) +#define CAM_STATUS_DATA_READY (CAM_STA_DRDY_MASK) + +/** + * @brief CAM input color format + */ +#define CAM_COLOR_FORMAT_RGB888 (CAM_CR1_COLOR_FORMATS_SET(2)) +#define CAM_COLOR_FORMAT_RGB565 (CAM_CR1_COLOR_FORMATS_SET(4)) +#define CAM_COLOR_FORMAT_RGB555 (CAM_CR1_COLOR_FORMATS_SET(6)) +#define CAM_COLOR_FORMAT_YCBCR422 (CAM_CR1_COLOR_FORMATS_SET(7)) +#define CAM_COLOR_FORMAT_YUV444 (CAM_CR1_COLOR_FORMATS_SET(8)) + +/** + * @brief CAM config + */ +typedef struct { + uint32_t width; + uint32_t height; + bool pixclk_sampling_falling; + bool hsync_active_low; + bool vsync_active_low; + bool color_ext; + bool data_pack_msb; + bool enable_buffer2; + uint8_t data_store_mode; + uint8_t color_format; + uint8_t sensor_bitwidth; + uint32_t buffer1; + uint32_t buffer2; + display_yuv2rgb_config_t csc_config; +} cam_config_t; + +/** + * @brief cam input pixel byte order + */ +typedef enum { + cam_input_pixel_yuv444 = 0, /* Y[23:16] U[15:8] V[7:0] */ + cam_input_pixel_yvu444 = 1, /* Y[23:16] V[15:8] U[7:0] */ + cam_input_pixel_uyv444 = 2, /* U[23:16] Y[15:8] V[7:0] */ + cam_input_pixel_vyu444 = 3, /* V[23:16] Y[15:8] U[7:0] */ + cam_input_pixel_uvy444 = 4, /* U[23:16] V[15:8] Y[7:0] */ + cam_input_pixel_vuy444 = 5, /* V[23:16] U[15:8] Y[7:0] */ + cam_input_pixel_yuyv422 = 0, /* Y0[31:24] U0[23:16] Y1[15:8] V0[7:0] */ + cam_input_pixel_yvyu422 = 1, /* Y0[31:24] V0[23:16] Y1[15:8] U0[7:0] */ + cam_input_pixel_uyvy422 = 2, /* U0[31:24] Y0[23:16] V0[15:8] Y1[7:0] */ + cam_input_pixel_vyuy422 = 3, /* V0[31:24] Y0[23:16] U0[15:8] Y1[7:0] */ + cam_input_pixel_rgb565 = 0, /* R[15:11] G[10:8] G[7:5] B[4:0] */ + cam_input_pixel_bgr565 = 1, /* B[15:11] G[10:8] G[7:5] R[4:0] */ + cam_input_pixel_gbr888 = 0, /* G[23:16] B[15:8] R[7:0] */ + cam_input_pixel_grb888 = 1, /* G[23:16] R[15:8] B[7:0] */ + cam_input_pixel_bgr888 = 2, /* B[23:16] G[15:8] R[7:0] */ + cam_input_pixel_rgb888 = 3, /* R[23:16] G[15:8] B[7:0] */ + cam_input_pixel_brg888 = 4, /* B[23:16] R[15:8] G[7:0] */ + cam_input_pixel_rbg888 = 5, /* R[23:16] B[15:8] G[7:0] */ +} cam_input_pixel_byte_order_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief CAM set high and low limits of color key + * + * @param [in] ptr CAM base address + * @param [in] high color key high limits + * @param [in] low color key low limits + */ +static inline void cam_set_color_key(CAM_Type *ptr, uint32_t high, uint32_t low) +{ + ptr->CLRKEY_LOW = CAM_CLRKEY_LOW_LIMIT_SET(low); + ptr->CLRKEY_HIGH = CAM_CLRKEY_HIGH_LIMIT_SET(high); +} + +/** + * @brief CAM get default config + * + * @param [in] ptr CAM base address + * @param [out] config cam_config_t + * @param [in] pixel_format display_pixel_format_t + */ +void cam_get_default_config(CAM_Type *ptr, cam_config_t *config, display_pixel_format_t pixel_format); + +/** + * @brief CAM init + * + * @param [in] ptr CAM base address + * @param [in] config cam_config_t + * + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config); + +/** + * @brief CAM start + * + * @param [in] ptr CAM base address + */ +void cam_start(CAM_Type *ptr); + +/** + * @brief CAM stop + * + * @param [in] ptr CAM base address + */ +void cam_stop(CAM_Type *ptr); + +/** + * @brief CAM enable binary output + * + * This function is used to enable CAM binary output after + * the CAM is initialized by the cam_init. + * + * @param [in] ptr CAM base address + */ +static inline void cam_enable_binary_output(CAM_Type *ptr) +{ + ptr->CR20 |= CAM_CR20_BINARY_EN_MASK; +} + +/** + * @brief CAM disable binary output + * + * @param [in] ptr CAM base address + */ +static inline void cam_disable_binary_output(CAM_Type *ptr) +{ + ptr->CR20 &= ~CAM_CR20_BINARY_EN_MASK; +} + +/** + * @brief CAM set binary threshold + * + * @param [in] ptr CAM base address + * @param [in] threshold threshold value of binary output + */ +static inline void cam_set_binary_threshold(CAM_Type *ptr, uint8_t threshold) +{ + ptr->CR20 = (ptr->CR20 & (~CAM_CR20_THRESHOLD_MASK)) | CAM_CR20_THRESHOLD_SET(threshold); +} + +/** + * @brief CAM enable argb8888 output + * + * This function is used to enable CAM argb8888 pixel output after the CAM is initialized by + * the cam_init and input pixel byte order is configured by the cam_set_input_pixel_byte_order. + * + * @param [in] ptr CAM base address + */ +static inline void cam_enable_argb8888_output(CAM_Type *ptr) +{ + ptr->CR1 |= CAM_CR1_COLOR_EXT_MASK; +} + +/** + * @brief CAM disable argb8888 output + * + * @param [in] ptr CAM base address + */ +static inline void cam_disable_argb8888_output(CAM_Type *ptr) +{ + ptr->CR1 &= ~CAM_CR1_COLOR_EXT_MASK; +} + +/** + * @brief CAM set input pixel byte order + * + * @param [in] ptr CAM base address + * @param [in] order cam_input_pixel_byte_order_t + */ +static inline void cam_set_input_pixel_byte_order(CAM_Type *ptr, cam_input_pixel_byte_order_t order) +{ + ptr->CR2 = (ptr->CR2 & (~CAM_CR2_CLRBITFORMAT_MASK)) | CAM_CR2_CLRBITFORMAT_SET(order); +} + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_CAM_DRV_H */ + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h new file mode 100644 index 0000000000..d0fe79b6a8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h @@ -0,0 +1,882 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_CAN_DRV_H +#define HPM_CAN_DRV_H + +#include "hpm_common.h" +#include "hpm_can_regs.h" + + +/** + * @brief CAN driver APIs + * @defgroup can_interface CAN driver APIs + * @ingroup can_interfaces + * @{ + * + */ + +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ + +/** + * @brief CAN error codes + */ +enum { + status_can_bit_error = MAKE_STATUS(status_group_can, 0), /**< CAN bit error */ + status_can_form_error = MAKE_STATUS(status_group_can, 1), /**< CAN Form error */ + status_can_stuff_error = MAKE_STATUS(status_group_can, 2), /**< CAN stuff error */ + status_can_ack_error = MAKE_STATUS(status_group_can, 3), /**< CAN ACK error */ + status_can_crc_error = MAKE_STATUS(status_group_can, 4), /**< CAN CRC error */ + status_can_other_error = MAKE_STATUS(status_group_can, 5), /**< CAN other error */ + status_can_tx_fifo_full = MAKE_STATUS(status_group_can, 6), /**< CAN TX fifo full */ + status_can_filter_index_invalid = MAKE_STATUS(status_group_can, 7), /**< CAN filter index is invalid */ + status_can_filter_num_invalid = MAKE_STATUS(status_group_can, 8), /**< CAN filter number is invalid */ +}; + +/** + * @brief CAN Event definitions + */ +#define CAN_EVENT_RECEIVE (CAN_RTIF_RIF_MASK) /**< CAN Receive event */ +#define CAN_EVENT_RX_BUF_OVERRUN (CAN_RTIF_ROIF_MASK) /**< CAN RX buffer overrun event */ +#define CAN_EVENT_RX_BUF_FULL (CAN_RTIF_RFIF_MASK) /**< CAN RX buffer full event */ +#define CAN_EVENT_RX_BUF_ALMOST_FULL (CAN_RTIF_RAFIF_MASK) /**< CAN RX buffer almost full event */ +#define CAN_EVENT_TX_PRIMARY_BUF (CAN_RTIF_TPIF_MASK) /**< CAN TX primary buffer event */ +#define CAN_EVENT_TX_SECONDARY_BUF (CAN_RTIF_TSIF_MASK) /**< CAN TX secondary buffer event */ +#define CAN_EVENT_ERROR (CAN_RTIF_EIF_MASK) /**< CAN error event */ +#define CAN_EVENT_ABORT (CAN_RTIF_AIF_MASK) /**< CAN abort event */ + +/** + * @brief CAN Secondary Transmit buffer Status + */ +#define CAN_STB_IS_EMPTY (0U) /**< CAN Sencondary Transmit buffer is empty */ +#define CAN_STB_LESS_EQUAL_HALF_FULL (1U) /**< CAN Sencondary Transmit buffer <= 1/2 * FULL */ +#define CAN_STB_MORE_THAN_HALF_FULL (2U) /**< CAN Sencondary Transmit buffer > 1/2 * FULL */ +#define CAN_STB_IS_FULL (3U) /**< CAN Sencondary Transmit buffer is full */ + +/** + * @brief CAN Receive Buffer States + */ +#define CAN_RXBUF_IS_EMPTY (0U) /**< CAN Receive buffer is empty */ +#define CAN_RXBUF_HAS_DATA (1U) /**< CAN Receive buffer has data */ +#define CAN_RXBUF_ALMOST_FULL (2U) /**< CAN Receive buffer is almost full */ +#define CAN_RXBUF_IS_FULL (3U) /**< CAN Receive buffer is full */ + +/** + * @brief CAN Error interrupts/flags + * + */ +#define CAN_ERROR_WARNING_LIMIT_FLAG (CAN_ERRINT_EWARN_MASK) /**< CAN Error Limit reached */ +#define CAN_ERROR_PASSIVE_MODE_ACTIVE_FLAG (CAN_ERRINT_EPASS_MASK) /**< CAN Passive mode active */ +#define CAN_ERROR_PASSIVE_INT_ENABLE (CAN_ERRINT_EPIE_MASK) /**< CAN Passive Interrupt Enable */ +#define CAN_ERROR_PASSIVE_INT_FLAG (CAN_ERRINT_EPIF_MASK) /**< CAN Passive Interrupt Flag */ +#define CAN_ERROR_ARBITRAITION_LOST_INT_ENABLE (CAN_ERRINT_ALIE_MASK) /**< CAN Abitration Lost Interrupt Enable */ +#define CAN_ERROR_ARBITRAITION_LOST_INT_FLAG (CAN_ERRINT_ALIE_MASK) /**< CAN arbitration Lost Interrupt Flag */ +#define CAN_ERROR_BUS_ERROR_INT_ENABLE (CAN_ERRINT_BEIE_MASK) /**< CAN BUS error Interrupt Enable */ +#define CAN_ERROR_BUS_ERROR_INT_FLAG (CAN_ERRINT_BEIF_MASK) /**< CAN BUS error Interrupt flag */ + +/** + * @brief CAN Error Kinds + * + */ +#define CAN_KIND_OF_ERROR_NO_ERROR (0U) /**< No error */ +#define CAN_KIND_OF_ERROR_BIT_ERROR (1U) /**< Bit error */ +#define CAN_KIND_OF_ERROR_FORM_ERROR (2U) /**< Form error */ +#define CAN_KIND_OF_ERROR_STUFF_ERROR (3U) /**< Stuff error */ +#define CAN_KIND_OF_ERROR_ACK_ERROR (4U) /**< Acknowledgment error */ +#define CAN_KIND_OF_ERROR_CRC_ERROR (5U) /**< CRC error */ +#define CAN_KIND_OF_ERROR_OTHER_ERROR (6U) /**< Other errors */ +#define CAN_KIND_OF_ERROR_BUS_OFF (7U) /**< BUS off error */ + +/** + * @brief CAN loopback types + */ +typedef enum _can_mode { + can_mode_normal, /**< Non-loopback mode */ + can_mode_loopback_internal, /**< Internal loopback mode */ + can_mode_loopback_external, /**< External loopback mode */ + can_mode_listen_only, /**< CAN listen mode */ +} can_mode_t; + +/** + * @brief CAN bit timing options + */ +typedef enum _can_bit_timing_option { + can_bit_timing_can2_0, /**< CAN 2.0 bit timing option */ + can_bit_timing_canfd_norminal, /**< CANFD norminal timing option */ + can_bit_timing_canfd_data, /**< CANFD data timing option */ +} can_bit_timing_option_t; + +/** + * @brief CAN DLC definitions + */ +enum { + can_payload_size_0 = 0, /**< Payload size is 0 */ + can_payload_size_1, /**< Payload size is 1 */ + can_payload_size_2, /**< Payload size is 2 */ + can_payload_size_3, /**< Payload size is 3 */ + can_payload_size_4, /**< Payload size is 4 */ + can_payload_size_5, /**< Payload size is 5 */ + can_payload_size_6, /**< Payload size is 6 */ + can_payload_size_7, /**< Payload size is 7 */ + can_payload_size_8, /**< Payload size is 8 */ + can_payload_size_12, /**< Payload size is 12 */ + can_payload_size_16, /**< Payload size is 16 */ + can_payload_size_20, /**< Payload size is 20 */ + can_payload_size_24, /**< Payload size is 24 */ + can_payload_size_32, /**< Payload size is 32 */ + can_payload_size_48, /**< Payload size is 48 */ + can_payload_size_64, /**< Payload size is 64 */ + can_payload_size_max = can_payload_size_64, +}; + +/** + * @brief CAN Bit timing parameters + */ +typedef struct { + uint16_t prescaler; /**< Prescaler value */ + uint16_t num_seg1; /**< Seg1 value */ + uint16_t num_seg2; /**< Seg2 value */ + uint16_t num_sjw; /**< SJW value */ +} can_bit_timing_param_t; + +/** + * @brief CAN receive buffer data structure + */ +typedef union _can_rx_buf { + uint32_t buffer[20]; /**< CAN buffer size */ + struct { + struct { + uint32_t id: 29; /**< CAN ID */ + uint32_t : 1; + uint32_t error_state_indicator: 1; /**< Error state indicator */ + }; + struct { + uint32_t dlc: 4; /**< Data length option */ + uint32_t bitrate_switch: 1; /**< bitrate switch flag */ + uint32_t canfd_frame: 1; /**< CANFD frame flag */ + uint32_t remote_frame: 1; /**< Remote frame flag */ + uint32_t extend_id: 1; /**< Extended ID flag */ + uint32_t : 4; + uint32_t loopback_message: 1; /**< Loopback message flag */ + uint32_t error_type: 3; /**< Error type */ + uint32_t cycle_time: 16; /**< Cycle time */ + }; + uint8_t data[]; /**< Data pointer */ + }; +} can_receive_buf_t; + +/** + * @brief CAN transmit buffer data structure + */ +typedef union _can_tx_buf { + uint32_t buffer[18]; /**< CAN transmit buffer */ + struct { + struct { + uint32_t id: 29; /**< CAN ID */ + uint32_t : 2; + uint32_t transmit_timestamp_enable: 1; /**< Timestamp enable flag */ + }; + struct { + uint32_t dlc: 4; /**< Data length option */ + uint32_t bitrate_switch: 1; /**< bitrate switch flag */ + uint32_t canfd_frame: 1; /**< CANFD frame flag */ + uint32_t remote_frame: 1; /**< remote_frame flag */ + uint32_t extend_id: 1; /**< Extended ID flag */ + uint32_t : 24; + }; + uint8_t data[]; /**< Data pointer */ + }; +} can_transmit_buf_t; + +/** + * @brief CAN acceptance filter modes + */ +typedef enum _can_filter_id_mode { + can_filter_id_mode_both_frames, /**< Accept both standard frame and extended frame */ + can_filter_id_mode_standard_frames, /**< Accept standard frame only */ + can_filter_id_mode_extended_frames, /**< Accept extended frame only */ +} can_filter_id_mode_t; + +/** + * @brief CAN acceptance filter configuration + */ +typedef struct { + uint16_t index; /**< CAN filter index */ + can_filter_id_mode_t id_mode; /**< CAN filter id mode */ + bool enable; /**< CAN filter enable flag */ + uint32_t code; /**< CAN filter code */ + uint32_t mask; /**< CAN filter mask */ +} can_filter_config_t; + +/** + * @brief CAN configuration + */ +typedef struct { + union { + struct { + uint32_t baudrate; /**< CAN2.0 baudrate / CANFD nominal baudrate */ + uint32_t baudrate_fd; /**< CANFD data baudrate */ + /**< minimum sampling point, value range (0-1000), samplepoint_min/1000 will be used in driver */ + uint16_t can20_samplepoint_min; + /**< maximum sampling point, value range (0-1000), samplepoint_max/1000 will be used in driver */ + uint16_t can20_samplepoint_max; + /**< minimum sampling point, value range (0-1000), samplepoint_min/1000 will be used in driver */ + uint16_t canfd_samplepoint_min; + /**< maximum sampling point, value range (0-1000), samplepoint_max/1000 will be used in driver */ + uint16_t canfd_samplepoint_max; + }; + struct { + can_bit_timing_param_t can_timing; /**< CAN2.0 /CANFD nominal low-level bit timing parameters */ + can_bit_timing_param_t canfd_timing;/**< CANFD low-level bit timing parameters */ + }; + }; + + can_mode_t mode; /**< CAN work mode */ + bool use_lowlevel_timing_setting; /**< Use low-level timing setting */ + bool enable_canfd; /**< Enable CAN FD */ + bool enable_self_ack; /**< CAN self-ack flag */ + bool disable_re_transmission_for_ptb; /**< disable re-transmission for primary transmit buffer */ + bool disable_re_transmission_for_stb; /**< disable re-transmission for secondary transmit buffer */ + bool enable_tdc; /**< Enable transmittor delay compensation */ + + uint8_t filter_list_num; /**< element number of CAN filters in filter list */ + can_filter_config_t *filter_list; /**< CAN filter list pointer */ + + uint8_t irq_txrx_enable_mask; /**< CAN TX and RX IRQ Enable Mask */ + uint8_t irq_error_enable_mask; /**< CAN Error IRQ Enable Mask */ + bool enable_tx_buffer_priority_mode; /**< Enable Priority-based priority */ + bool enable_can_fd_iso_mode; /**< Enable CAN-FD ISO mode */ +} can_config_t; + + +#ifdef __cpluspuls +extern "C" { +#endif + + +/** + * @brief Reset CAN controller + * + * @param [in] base CAN base address + * @param [in] enable reset flag for CAN controller + * @arg true reset the CAN controller + * @arg false clear the CAN controller reset flag + */ +static inline void can_reset(CAN_Type *base, bool enable) +{ + if (enable) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RESET_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_RESET_MASK; + } +} + +/** + * @brief Set CAN mode + * + * @param [in] base CAN base address + * @param [in] mode CAN loopback mode + * @arg can_mode_normal Normal work mode + * @arg can_mode_loopback_internal internal loopback mode + * @arg can_mode_loopback_external external loopback mode + * @arg can_mode_listen_only CAN listen-only mode + */ +static inline void can_set_mode(CAN_Type *base, can_mode_t mode) +{ + uint32_t cfg_stat = base->CMD_STA_CMD_CTRL & ~(CAN_CMD_STA_CMD_CTRL_LBME_MASK | CAN_CMD_STA_CMD_CTRL_LBMI_MASK | CAN_CMD_STA_CMD_CTRL_LOM_MASK); + if (mode == can_mode_loopback_internal) { + cfg_stat |= CAN_CMD_STA_CMD_CTRL_LBMI_MASK; + } else if (mode == can_mode_loopback_external) { + cfg_stat |= CAN_CMD_STA_CMD_CTRL_LBME_MASK; + } else if (mode == can_mode_listen_only) { + cfg_stat |= CAN_CMD_STA_CMD_CTRL_LOM_MASK; + } else { + /* CAN normal work mode, no change needed here */ + } + base->CMD_STA_CMD_CTRL = cfg_stat; +} + +/** + * @brief Enable CAN listen-only mode + * @param [in] base CAN base address + * @param [in] enable CAN listen-only mode enable flag + * @arg true enable listen-only mode + * @arg false disable listen-only mode + */ +static inline void can_enable_listen_only_mode(CAN_Type *base, bool enable) +{ + if (enable) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_LOM_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_LOM_MASK; + } +} + +/** + * @brief Enter CAN standby mode + * @param [in] base CAN base address + * @param [in] enable Can standby mode enable flag + * @arg true enable standby mode + * @arg false disable standby mode + */ +static inline void can_enter_standby_mode(CAN_Type *base, bool enable) +{ + if (enable) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_STBY_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_STBY_MASK; + } +} + +/** + * @brief Select CAN TX buffer + * @param [in] base CAN base address + * @param [in] select_secondary_buffer CAN secondary transmit buffer selection flag + * @arg true Select the secondary transmit buffer + * @arg false Select the primary transmit buffer + */ +static inline void can_select_tx_buffer(CAN_Type *base, bool select_secondary_buffer) +{ + if (select_secondary_buffer) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; + } +} + +/** + * @brief Start CAN high priority message transmit + * @param [in] base CAN base address + * + */ +static inline void can_start_high_priority_message_transmit(CAN_Type *base) +{ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPE_MASK; +} + +/** + * @brief Abort CAN high priority message transmit + * @param [in] base CAN base address + */ +static inline void can_abort_high_priority_message_transmit(CAN_Type *base) +{ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPA_MASK; +} + +/** + * @brief Start CAN message transmit + * @param [in] base CAN base address + */ +static inline void can_start_message_transmit(CAN_Type *base) +{ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSONE_MASK; +} + +/** + * @brief Start CAN all messages transmit + * @param [in] base CAN base address + */ +static inline void can_start_all_message_transmit(CAN_Type *base) +{ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSALL_MASK; +} + +/** + * @brief Abort CAN message transmit + * @param [in] base CAN base address + */ +static inline void can_abort_message_transmit(CAN_Type *base) +{ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSA_MASK; +} + +/** + * @brief Switch to next CAN tx buffer + * @param [in] base CAN base address + */ +static inline void can_switch_to_next_tx_buffer(CAN_Type *base) +{ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK; +} + +/** + * @brief Select CAN tx buffer priority mode + * @param [in] base CAN base address + * @param [in] enable_priority_decision CAN tx buffer priority mode selection flag + * @arg true priority decision mode + * @arg false FIFO mode + */ +static inline void can_select_tx_buffer_priority_mode(CAN_Type *base, bool enable_priority_decision) +{ + if (enable_priority_decision) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSMODE_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TSMODE_MASK; + } +} + +/** + * @brief Get CAN secondary transmit buffer status + * @param [in] base CAN base address + * @retval secondary transmit buffer status, 0: empty, 1: <= 1/2 full, 2: > 1/2 full, 3: full + * + */ +static inline uint8_t can_get_secondary_transmit_buffer_status(CAN_Type *base) +{ + return CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL); +} + +/** + * @brief Check whether the primary transmit buffer is full + * @param [in] base CAN base address + * @return true for full + */ +static inline bool can_is_primary_transmit_buffer_full(CAN_Type *base) +{ + return ((base->CMD_STA_CMD_CTRL & CAN_CMD_STA_CMD_CTRL_TPE_MASK) != 0U); +} + +/** + * @brief Check whether the secondary transmit buffer is full + * @param [in] base CAN base address + * @return true for full + */ +static inline bool can_is_secondary_transmit_buffer_full(CAN_Type *base) +{ + return (CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL) == CAN_STB_IS_FULL); +} + +/** + * @brief Check whether the CAN is in BUS off mode + * + * @param [in] base CAN base address + * @return true for bus off mode + * @return false for non-bus off mode + */ +static inline bool can_is_in_bus_off_mode(CAN_Type *base) +{ + return ((base->CMD_STA_CMD_CTRL & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) != 0U); +} + +/** + * @brief Enable can self ack + * @param [in] base CAN base address + * @param [in] enable Self-ack enable flag, true or false + * + */ +static inline void can_enable_self_ack(CAN_Type *base, bool enable) +{ + if (enable) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_SACK_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_SACK_MASK; + } +} + +/** + * @brief Set CAN receive buffer overflow mode + * @param [in] base CAN base address + * @param [in] override_enable receive buffer overflow mode option + * @arg true the oldest message will be overwritten + * @arg false the new message will not be stored + */ +static inline void can_set_receive_buffer_overflow_mode(CAN_Type *base, bool override_enable) +{ + if (override_enable) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_ROM_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_ROM_MASK; + } +} + +/** + * @brief Check whether CAN receive buffer is overflow + * @param [in] base CAN base address + * @retval true or false + */ +static inline bool can_is_receive_buffer_overflow(CAN_Type *base) +{ + return IS_HPM_BITMASK_SET(base->CMD_STA_CMD_CTRL, CAN_CMD_STA_CMD_CTRL_ROV_MASK); +} + +/** + * @brief Release CAN receive buffer + * + * @param [in] base CAN base address + */ +static inline void can_release_receive_buffer(CAN_Type *base) +{ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RREL_MASK; +} + +/** + * @brief Allow can store all date in receive buffer + * @param [in] base CAN base address + * @param [in] allow flag to determine whether to store error data frame + */ +static inline void can_allow_store_all_data_in_receive_buffer(CAN_Type *base, bool allow) +{ + if (allow) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RBALL_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_RBALL_MASK; + } +} + +/** + * @brief Get CAN receive buffer status + * @param [in] base CAN base address + * @retval Receive buffer status, 0: empty, 1: > empty, < almost full, 2: >= almost full, 3: full + */ +static inline uint8_t can_get_receive_buffer_status(CAN_Type *base) +{ + return CAN_CMD_STA_CMD_CTRL_RSTAT_GET(base->CMD_STA_CMD_CTRL); +} + +/** + * @brief Check whether there are data available in receive buffer + * @param [in] base CAN base address + * @return true if the receive buffer is not empty + */ +static inline bool can_is_data_available_in_receive_buffer(CAN_Type *base) +{ + return (CAN_CMD_STA_CMD_CTRL_RSTAT_GET(base->CMD_STA_CMD_CTRL) != CAN_RXBUF_IS_EMPTY); +} + + +/** + * @brief Enable CAN FD ISO mode + * @param [in] base CAN base address + * @param enable CAN-FD ISO mode enable flag + */ +static inline void can_enable_can_fd_iso_mode(CAN_Type *base, bool enable) +{ + if (enable) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK; + } +} + +/** + * @brief Enable CAN TX/RX interrupt + * @param [in] base CAN base address + * @param [in] mask CAN interrupt mask + */ +static inline void can_enable_tx_rx_irq(CAN_Type *base, uint8_t mask) +{ + base->RTIE |= mask; +} + +/** + * @brief Disable CAN TX/RX interrupt + * @param [in] base CAN base address + * @param [in] mask CAN interrupt mask + */ +static inline void can_disable_tx_rx_irq(CAN_Type *base, uint8_t mask) +{ + base->RTIE &= ~mask; +} + +/** + * @brief Clear CAN TX/RX flags + * @param [in] base CAN base address + * @param [in] flags CAN TX/RX interrupt flags + */ +static inline void can_clear_tx_rx_flags(CAN_Type *base, uint8_t flags) +{ + base->RTIF = flags; +} + +/** + * @brief Get CAN TX/RX flags + * + * @param [in] base CAN base address + * @retval CAN Tx/RX interrupt flags + */ +static inline uint8_t can_get_tx_rx_flags(CAN_Type *base) +{ + return base->RTIF; +} + +/** + * @brief Enable CAN error interrupt + * @param [in] base CAN base address + * @param [in] mask CAN error interrupt mask + */ +static inline void can_enable_error_irq(CAN_Type *base, uint8_t mask) +{ + base->ERRINT |= mask; +} + +/** + * @brief Disable CAN error interrupt + * + * @param [in] base CAN base address + * @param [in] mask CAN error interrupt mask + */ +static inline void can_disable_error_irq(CAN_Type *base, uint8_t mask) +{ + base->ERRINT &= ~mask; +} + +/** + * @brief Get CAN error interrupt flags + * @param [in] base CAN base address + * @retval CAN error interrupt flags + */ +static inline uint8_t can_get_error_interrupt_flags(CAN_Type *base) +{ + return (base->ERRINT & (uint8_t) ~(CAN_ERRINT_EPIE_MASK | CAN_ERRINT_ALIE_MASK | CAN_ERRINT_BEIE_MASK)); +} + +/** + * @brief Get CAN clear interrupt flags + * @param [in] base CAN base address + * @param [in] flags CAN error interrupt flags + */ +static inline void can_clear_error_interrupt_flags(CAN_Type *base, uint8_t flags) +{ + flags &= (uint8_t)~(CAN_ERRINT_EPIE_MASK | CAN_ERRINT_ALIE_MASK | CAN_ERRINT_BEIE_MASK); + base->ERRINT |= flags; +} + +/** + * @brief Get last CAN error kind + * @param [in] base CAN base address + * @retval CAN last error kind + */ +static inline uint8_t can_get_last_error_kind(CAN_Type *base) +{ + return CAN_EALCAP_KOER_GET(base->EALCAP); +} + +/** + * @brief Get CAN last arbitrary lost position + * @param [in] base CAN base address + * @retval CAN last arbitrary lost position + */ +static inline uint8_t can_get_last_arbitration_lost_position(CAN_Type *base) +{ + return CAN_EALCAP_ALC_GET(base->EALCAP); +} + +/** + * @brief Set CAN transmitter delay compensation + * + * @param [in] base CAN base address + * @param [in] sample_point delay compensation sample point + * @param [in] enable delay compensation enable flag + */ +static inline void can_set_transmitter_delay_compensation(CAN_Type *base, uint8_t sample_point, bool enable) +{ + base->TDC = CAN_TDC_SSPOFF_SET(sample_point) | CAN_TDC_TDCEN_SET((uint8_t) enable); +} + +/** + * @brief Set CAN warning limits + * @param [in] base CAN base address + * @param [in] almost_full_limit + * @param [in] error_warning_limit + */ +static inline void can_set_warning_limits(CAN_Type *base, uint8_t almost_full_limit, uint8_t error_warning_limit) +{ + base->LIMIT = CAN_LIMIT_AFWL_SET(almost_full_limit) | CAN_LIMIT_EWL_SET(error_warning_limit); +} + +/** + * @brief Get CAN receive error count + * @param [in] base CAN base address + * @retval CAN receive error count + */ +static inline uint8_t can_get_receive_error_count(CAN_Type *base) +{ + return base->RECNT; +} + +/** + * @brief Get CAN transmit error count + * @param [in] base CAN base address + * @retval CAN transmit error count + */ +static inline uint8_t can_get_transmit_error_count(CAN_Type *base) +{ + return base->TECNT; +} + +/** + * @brief Disable CAN filter + * + * @param [in] base CAN base address + * @param index CAN filter index + */ +static inline void can_disable_filter(CAN_Type *base, uint32_t index) +{ + base->ACF_EN &= (uint16_t) ~(1U << index); +} + +/** + * @brief Get default CAN configuration parameters + * @param [out] config CAN configuration structure + * @retval API execution status, status_success or status_invalid_argument + */ +hpm_stat_t can_get_default_config(can_config_t *config); + +/** + * @brief Initialize the CAN controller + * @param [in] base CAN base address + * @param [in] config CAN configuration + * @param [in] src_clk_freq CAN IP source clock frequency + * @retval API execution status, status_success or status_invalid_argument + */ +hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq); + + +/** + * @brief Configure the Slow Speed Bit timing using low-level interface + * @param [in] base CAN base address + * @param [in] param CAN bit timing parameter + */ +static inline void can_set_slow_speed_timing(CAN_Type *base, const can_bit_timing_param_t *param) +{ + base->S_PRESC = CAN_S_PRESC_S_PRESC_SET(param->prescaler - 1U) | CAN_S_PRESC_S_SEG_1_SET(param->num_seg1 - 2U) | + CAN_S_PRESC_S_SEG_2_SET(param->num_seg2 - 1U) | CAN_S_PRESC_S_SJW_SET(param->num_sjw - 1U); +} + +/** + * @brief Configure the Fast Speed Bit timing using low-level interface + * @param [in] base CAN base address + * @param [in] param CAN bit timing parameter + */ +static inline void can_set_fast_speed_timing(CAN_Type *base, const can_bit_timing_param_t *param) +{ + base->F_PRESC = CAN_F_PRESC_F_PRESC_SET(param->prescaler - 1U) | CAN_F_PRESC_F_SEG_1_SET(param->num_seg1 - 2U) | + CAN_F_PRESC_F_SEG_2_SET(param->num_seg2 - 1U) | CAN_F_PRESC_F_SJW_SET(param->num_sjw - 1U); +} + +/** + * @brief Configure the CAN bit timing for CAN BUS + * @param [in] base CAN base address + * @param [in] option CAN bit timing option + * @param [in] src_clk_freq CAN IP source clock frequency + * @param [in] baudrate CAN baudrate in MHz + * @param [in] samplepoint_min Minimum Sample point, range(0-1000), samplepoint_min / 1000 will be used in calculation + * @param [in] samplepoint_max Maximum Sample point, range(0-1000), samplepoint_max / 1000 will be used in calculation + * @retval API execution status, status_success or status_invalid_argument + */ +hpm_stat_t can_set_bit_timing(CAN_Type *base, can_bit_timing_option_t option, + uint32_t src_clk_freq, uint32_t baudrate, + uint16_t samplepoint_min, uint16_t samplepoint_max); + + +/** + * @brief Calculate the CAN bit timing for CAN BUS + * @param [in] src_clk_freq CAN IP source clock frequency + * @param [in] option CAN bit timing option + * @param [in] baudrate CAN baudrate in MHz + * @param [in] samplepoint_min Minimum Sample point, range(0-1000), samplepoint_min / 1000 will be used in calculation + * @param [in] samplepoint_max Maximum Sample point, range(0-1000), samplepoint_max / 1000 will be used in calculation + * @param [out] timing_param Calculated CAN bit timing parameter + * @retval API execution status, status_success or status_invalid_argument + */ +hpm_stat_t can_calculate_bit_timing(uint32_t src_clk_freq, can_bit_timing_option_t option, uint32_t baudrate, + uint16_t samplepoint_min, uint16_t samplepoint_max, + can_bit_timing_param_t *timing_param); + + + +/** + * @brief Configure the acceptable filter + * @param [in] base CAN base address + * @param [in] config CAN filter configuration + * @retval API execution status, status_success or status_invalid_argument + */ +hpm_stat_t can_set_filter(CAN_Type *base, const can_filter_config_t *config); + +/** + * @brief Send CAN message using blocking transfer + * @param [in] base CAN base address + * @param [in] message CAN message to be sent out + * @retval API execution status, status_success or status_invalid_argument + */ +hpm_stat_t can_send_message_blocking(CAN_Type *base, const can_transmit_buf_t *message); + +/** + * @brief Send high-priority message using blocking transfer + * @param [in] base CAN base address + * @param [in] message CAN message to be sent out + * @retval API execution status, status_success or status_invalid_argument + */ +hpm_stat_t can_send_high_priority_message_blocking(CAN_Type *base, const can_transmit_buf_t *message); + + +/** + * @brief Send CAN message using non-blocking transfer + * @param [in] base CAN base address + * @param [in] message CAN message to be sent out + * @retval API execution status, status_success or status_invalid_argument + */ +hpm_stat_t can_send_message_nonblocking(CAN_Type *base, const can_transmit_buf_t *message); + +/** + * @brief Send high-priority message using non-blocking transfer + * @param [in] base CAN base address + * @param [in] message CAN message to be sent out + * @retval API execution status, status_success or status_invalid_argument + */ +hpm_stat_t can_send_high_priority_message_nonblocking(CAN_Type *base, const can_transmit_buf_t *message); + +/** + * @brief Receive CAN message using blocking transfer + * @param [in] base CAN base address + * @param [out] message CAN message buffer + * @retval API execution status + * @arg status_success API exection is successful + * @arg status_invalid_argument Invalid parameters + * @arg status_can_bit_error CAN bit error happened during receiving message + * @arg status_can_form_error CAN form error happened during receiving message + * @arg status_can_stuff_error CAN stuff error happened during receiving message + * @arg status_can_ack_error CAN ack error happened during receiving message + * @arg status_can_crc_error CAN crc error happened during receiving message + * @arg status_can_other_error Other error happened during receiving message + */ +hpm_stat_t can_receive_message_blocking(CAN_Type *base, can_receive_buf_t *message); + + +/** + * @brief Read Received CAN message + * @note This API assumes that the received CAN message is available. + * It can be used in the interrupt handler + * @param [in] base CAN base address + * @param [out] message CAN message buffer + * @retval status_success API exection is successful + * @retval status_invalid_argument Invalid parameters + * @retval status_can_bit_error CAN bit error happened during receiving message + * @retval status_can_form_error CAN form error happened during receiving message + * @retval status_can_stuff_error CAN stuff error happened during receiving message + * @retval status_can_ack_error CAN ack error happened during receiving message + * @retval status_can_crc_error CAN crc error happened during receiving message + * @retval status_can_other_error Other error happened during receiving message + */ +hpm_stat_t can_read_received_message(CAN_Type *base, can_receive_buf_t *message); + +/** + * @} + * + */ + + +#ifdef __cpluspuls +} +#endif + + +#endif /* HPM_CAN_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h new file mode 100644 index 0000000000..218f9af87c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_COMMON_H +#define _HPM_COMMON_H + +#include +#include +#include +#include +#include + +/** + * + * @brief COMMON driver APIs + * @defgroup common_interface COMMON driver APIs + * @{ + * + */ + +#define __R volatile const /* Define "read-only" permission */ +#define __RW volatile /* Define "read-write" permission */ +#define __W volatile /* Define "write-only" permission */ + +#ifndef __I +#define __I __R +#endif + +#ifndef __IO +#define __IO __RW +#endif + +#ifndef __O +#define __O __W +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#endif + +#ifndef MAX +#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif +#ifndef MIN +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +#define HPM_BITSMASK(val,offset) ((uint32_t)(val) << (offset)) +#define IS_HPM_BITMASK_SET(val,mask) (((uint32_t)(val) & (uint32_t)(mask)) != 0U) +#define IS_HPM_BIT_SET(val,offset) (((uint32_t)(val) & (1UL << (offset))) != 0U) +#define IS_HPM_BITMASK_CLR(val,mask) (((uint32_t)(val) & (uint32_t)(mask)) == 0U) +#define IS_HPM_BIT_CLR(val,offset) (((uint32_t)(val) & (1UL << (offset))) == 0U) + +#define HPM_BREAK_IF(cond) if(cond) {break;} +#define HPM_CONTINUE_IF(cond) if(cond) {continue;} + +#define HPM_CHECK_RET(x) \ + do \ + { \ + stat = (x); \ + if (status_success != stat) \ + { \ + return stat; \ + } \ + } while (false) + +#define SIZE_1KB (1024UL) +#define SIZE_1MB (1048576UL) + +typedef uint32_t hpm_stat_t; + +/* @brief Enum definition for the Status group + * Rule: + * [Group] 0-999 for the SoC driver and the corresponding components + * 1000 or above for the application status group + * [Code] Valid value: 0-999 + * + * */ +#define MAKE_STATUS(group,code) ((uint32_t)(group)*1000U + (uint32_t)(code)) +/* @brief System status group definitions */ +enum +{ + status_group_common = 0, + status_group_uart = 1, + status_group_i2c = 2, + status_group_spi = 3, + status_group_usb = 4, + status_group_i2s = 5, + status_group_xpi = 6, + status_group_l1c, + status_group_dma, + status_group_dram, + status_group_sdp, + status_group_xpi_nor, + status_group_otp, + status_group_lcdc, + status_group_mbx, + status_group_rng, + status_group_pdma, + status_group_wdg, + status_group_pmic_sec, + status_group_can, + status_group_sdxc, + status_group_pcfg, + status_group_clk, + status_group_pllctl, + status_group_pllctlv2, + status_group_ffa, + + status_group_middleware_start = 500, + status_group_sdmmc = status_group_middleware_start, + status_group_audio_codec, + status_group_dma_manager, +}; + +/* @brief Common status code definitions */ +enum +{ + status_success = MAKE_STATUS(status_group_common, 0), + status_fail = MAKE_STATUS(status_group_common, 1), + status_invalid_argument = MAKE_STATUS(status_group_common, 2), + status_timeout = MAKE_STATUS(status_group_common, 3), +}; + +#if defined(__GNUC__) + +/* alway_inline */ +#define ATTR_ALWAYS_INLINE __attribute__((always_inline)) + +/* weak */ +#define ATTR_WEAK __attribute__((weak)) + +/* alignment */ +#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment))) + +/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */ +#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name))) + +#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \ +ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment) + +#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable") +#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \ + ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment) + +#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss") +#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \ + ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment) + +/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */ +#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init") +#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \ + ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment) + +#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast") +#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \ + ATTR_RAMFUNC ATTR_ALIGN(alignment) + +#else +#error Unknown toolchain +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Count bits set to 1 + * + * @param value Data to be counted + * + * @return number of bits set to 1 + */ +static inline uint32_t count_set_bits(uint32_t value) +{ + if (value == 0) { + return 0; + } + return 1 + count_set_bits(value & (value - 1)); +} + +/** + * @brief Count bits set to 1 from least significant bit + * + * @param value Data to be counted + * + * @return number of bits set to 1 + * @return 0xFFFFFFFF if no bit was set to 1 + */ +static inline uint32_t get_first_set_bit_from_lsb(uint32_t value) +{ + uint32_t i = 0; + if (!value) { + return 0xFFFFFFFFUL; + } + while (value && !(value & 0x1)) { + value >>= 1; + i++; + } + return i; +} + +/** + * @brief Count bits set to 1 from most significant bit + * + * @param value Data to be counted + * + * @return number of bits set to 1 + * @return 0xFFFFFFFF if no bit was set to 1 + */ +static inline uint32_t get_first_set_bit_from_msb(uint32_t value) +{ + uint32_t i = 31; + if (!value) { + return 0xFFFFFFFFUL; + } + while (value && !(value & 0x80000000)) { + value <<= 1; + value &= ~1; + i--; + } + return i; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* _HPM_COMMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h new file mode 100644 index 0000000000..cc6d1163fc --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_DAC_DRV_H +#define HPM_DAC_DRV_H + +#include "hpm_common.h" +#include "hpm_dac_regs.h" +#include "hpm_soc_feature.h" + +#define DAC_AHB_ERROR_EVENT DAC_IRQ_EN_AHB_ERROR_MASK +#define DAC_FIFO_EMPTY_EVENT DAC_IRQ_EN_FIFO_EMPTY_MASK +#define DAC_BUF1_COMPLETE_EVENT DAC_IRQ_EN_BUF1_CMPT_MASK +#define DAC_BUF0_COMPLETE_EVENT DAC_IRQ_EN_BUF0_CMPT_MASK + + +typedef enum { + dac_mode_direct = 0, + dac_mode_step, + dac_mode_buffer +} dac_mode_t; + +typedef enum { + dac_ana_div_2 = 0, + dac_ana_div_4, + dac_ana_div_6, + dac_ana_div_8 +} dac_ana_div_t; + +typedef struct { + bool sync_mode; + uint8_t dac_mode; + uint8_t clk_dac_div; + uint16_t div_cfg; +} dac_config_t; + +typedef enum { + dac_step_up = 0, + dac_step_down +} dac_step_direction_t; + +typedef enum { + dac_round_mode_oneshot = 0, + dac_round_mode_loop +} dac_round_mode_t; + +typedef struct { + uint16_t start_point; + uint16_t end_point; + uint8_t round_mode; + uint8_t up_down; + uint8_t step_num; +} dac_step_config_t; + +typedef enum { + dac_data_stru_2_point = 0, + dac_data_stru_1_point +} dac_data_structure_t; + +typedef enum { + dac_burst_single = 0, + dac_burst_incr4 = 3, + dac_burst_incr8 = 5 +} dac_burst_type_t; + +typedef struct { + uint32_t start_addr; + uint8_t stop; + uint16_t len; +} dac_buffer_t; + +typedef struct { + uint8_t buf_data_mode; + uint8_t burst; + dac_buffer_t buf0; + dac_buffer_t buf1; +} dac_buffer_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +void dac_get_default_config(dac_config_t *config); +hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config); +hpm_stat_t dac_set_direct_config(DAC_Type *ptr, uint16_t data); +hpm_stat_t dac_set_step_config(DAC_Type *ptr, uint8_t step_cfg_idx, dac_step_config_t *config); +hpm_stat_t dac_set_buffer_config(DAC_Type *ptr, dac_buffer_config_t *config); +hpm_stat_t dac_set_output_frequency(DAC_Type *ptr, uint32_t dac_input_freq, uint32_t dac_output_freq); +hpm_stat_t dac_set_step_sw_trigger(DAC_Type *ptr, uint8_t step_sw_trig_idx); +void dac_set_buffer_sw_trigger(DAC_Type *ptr); +void dac_set_hw_trigger_enable(DAC_Type *ptr, bool enable); +hpm_stat_t dac_external_dma_request_enable(DAC_Type *ptr, uint8_t buf_idx, bool enable); +void dac_set_buffer_dma_reset(DAC_Type *ptr); +void dac_enable_conversion(DAC_Type *ptr, bool enable); +void dac_enable_interrupts(DAC_Type *ptr, uint32_t mask); +uint32_t dac_get_status_flags(DAC_Type *ptr); +void dac_set_status_flags(DAC_Type *ptr, uint32_t mask); +uint8_t dac_get_current_buffer_index(DAC_Type *ptr); +uint16_t dac_get_current_buffer_offset(DAC_Type *ptr); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h new file mode 100644 index 0000000000..19bce00e17 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DAO_DRV_H +#define HPM_DAO_DRV_H + +#include "hpm_common.h" +#include "hpm_dao_regs.h" +#include "hpm_i2s_common.h" + +/** + * @brief DAO driver APIs + * @defgroup dao_interface DAO driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief DAO channel selection + */ +#define DAO_CHANNEL_LEFT_ONLY DAO_CTRL_LEFT_EN_MASK +#define DAO_CHANNEL_RIGHT_ONLY DAO_CTRL_RIGHT_EN_MASK +#define DAO_CHANNEL_BOTH \ + (DAO_CTRL_RIGHT_EN_MASK | DAO_CTRL_LEFT_EN_MASK) + +/** + * @brief DAO default output + */ +#define DAO_DEFAULT_OUTPUT_ALL_LOW (0U) +#define DAO_DEFAULT_OUTPUT_ALL_HIGH (1U) +#define DAO_DEFAULT_OUTPUT_P_HIGH_N_LOW (2U) +#define DAO_DEFAULT_OUTPUT_DISABLED (3U) + +/** + * @brief DAO config + */ +typedef struct dao_config { + bool enable_mono_output; + uint8_t default_output_level; + uint8_t channel_count; +} dao_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief config high pass filter + * + * @param [in] ptr DAO base address + * @param [in] hpf_coef_ma high pass filter a coefficient's complement + * @param [in] hpf_coef_b high pass filter b coefficient + * @param [in] enable + * @arg true: enable + * @arg false: disable + */ +static inline void dao_config_hpf(DAO_Type *ptr, + uint32_t hpf_coef_ma, + uint32_t hpf_coef_b, + bool enable) +{ + ptr->HPF_MA = DAO_HPF_MA_COEF_SET(hpf_coef_ma); + ptr->HPF_B = DAO_HPF_B_COEF_SET(hpf_coef_b); + ptr->CTRL = (ptr->CTRL & ~DAO_CTRL_HPF_EN_MASK) + | (enable ? DAO_CTRL_HPF_EN_MASK : 0); +} + +/** + * @brief enable high pass filter + * + * @param [in] ptr DAO base address + */ +static inline void dao_enable_hpf(DAO_Type *ptr) +{ + ptr->CTRL |= DAO_CTRL_HPF_EN_MASK; +} + +/** + * @brief disable high pass filter + * + * @param [in] ptr DAO base address + */ +static inline void dao_disable_hpf(DAO_Type *ptr) +{ + ptr->CTRL &= ~DAO_CTRL_HPF_EN_MASK; +} + +/** + * @brief enable error irq + * + * @param [in] ptr DAO base address + */ +static inline void dao_enable_error_irq(DAO_Type *ptr) +{ + ptr->CTRL |= DAO_CTRL_SAT_ERR_IE_MASK; +} + +/** + * @brief disable error irq + * + * @param [in] ptr DAO base address + */ +static inline void dao_disable_error_irq(DAO_Type *ptr) +{ + ptr->CTRL &= ~DAO_CTRL_SAT_ERR_IE_MASK; +} + +/** + * @brief enable channel + * + * @param [in] ptr DAO base address + * @param [in] ch channel number + */ +static inline void dao_enable_channel(DAO_Type *ptr, uint32_t ch) +{ + ptr->CTRL |= ch; +} + +/** + * @brief disable channel + * + * @param [in] ptr DAO base address + * @param [in] ch channel number + */ +static inline void dao_disable_channel(DAO_Type *ptr, uint32_t ch) +{ + ptr->CTRL &= ~ch; +} + +/** + * @brief enable mono output + * + * @param [in] ptr DAO base address + */ +static inline void dao_enable_mono_output(DAO_Type *ptr) +{ + ptr->CTRL |= DAO_CTRL_MONO_MASK; +} + +/** + * @brief disable mono output + * + * @param [in] ptr DAO base address + */ +static inline void dao_disable_mono_output(DAO_Type *ptr) +{ + ptr->CTRL &= ~DAO_CTRL_MONO_MASK; +} + +/** + * @brief enable remap + * + * @param [in] ptr DAO base address + */ +static inline void dao_enable_remap(DAO_Type *ptr) +{ + ptr->CTRL |= DAO_CTRL_REMAP_MASK; +} + +/** + * @brief disable remap + * + * @param [in] ptr DAO base address + */ +static inline void dao_disable_remap(DAO_Type *ptr) +{ + ptr->CTRL &= ~DAO_CTRL_REMAP_MASK; +} + +/** + * @brief invert output + * + * @param [in] ptr DAO base address + * @param [in] invert + * @arg true: invert output + * @arg false: not invert output + */ +static inline void dao_invert_output(DAO_Type *ptr, bool invert) +{ + ptr->CTRL = (ptr->CTRL & DAO_CTRL_INVERT_MASK) + | DAO_CTRL_INVERT_SET(invert); +} + +/** + * @brief force pads output with certain level + * + * @param [in] ptr DAO base address + * @param [in] output output level + */ +static inline void dao_force_output(DAO_Type *ptr, uint8_t output) +{ + ptr->CTRL = (ptr->CTRL & DAO_CTRL_FALSE_LEVEL_MASK) + | DAO_CTRL_FALSE_LEVEL_SET(output); +} + +/** + * @brief enable false run + * when false run mode is enabled, the module continues to consume data, no actual output on pads. + * @param [in] ptr DAO base address + * @param [in] enable + * @arg true: enable + * @arg false: disable + */ +static inline void dao_enable_false_run(DAO_Type *ptr, bool enable) +{ + ptr->CTRL = (ptr->CTRL & DAO_CTRL_FALSE_RUN_MASK) + | DAO_CTRL_FALSE_RUN_SET(enable); +} + +/** + * @brief software reset + * + * @param [in] ptr DAO base address + */ +static inline void dao_software_reset(DAO_Type *ptr) +{ + ptr->CMD |= DAO_CMD_SFTRST_MASK; + ptr->CMD &= ~DAO_CMD_SFTRST_MASK; +} + +/** + * @brief check whether DAO is running + * + * @param [in] ptr DAO base address + * @retval true if dao is running + */ +static inline bool dao_is_running(DAO_Type *ptr) +{ + return ptr->CMD & DAO_CMD_RUN_MASK; +} + +/** + * @brief start + * + * @param [in] ptr DAO base address + */ +static inline void dao_start(DAO_Type *ptr) +{ + ptr->CMD |= DAO_CMD_RUN_MASK; +} + +/** + * @brief stop + * + * @param [in] ptr DAO base address + */ +static inline void dao_stop(DAO_Type *ptr) +{ + ptr->CMD &= ~DAO_CMD_RUN_MASK; +} + +/** + * @brief initlization + * + * @param [in] ptr DAO base address + * @param [in] config dao_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t dao_init(DAO_Type *ptr, dao_config_t *config); + +/** + * @brief get default config + * + * @param [in] ptr DAO base address + * @param [out] config dao_config_t + */ +void dao_get_default_config(DAO_Type *ptr, dao_config_t *config); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_DAO_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h new file mode 100644 index 0000000000..3cd4e51765 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_DISPLAY_COMMON_H +#define HPM_DISPLAY_COMMON_H + +#include "hpm_common.h" + +/** + * @brief Display_common driver APIs + * @defgroup Display_common_interface Display_common driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief display alphablend mode + */ +typedef enum display_alphablend_mode { + display_alphablend_mode_clear = 0, + display_alphablend_mode_src = 1, + display_alphablend_mode_dst = 2, + display_alphablend_mode_src_over = 3, + display_alphablend_mode_dst_over = 4, + display_alphablend_mode_src_in = 5, + display_alphablend_mode_dst_in = 6, + display_alphablend_mode_src_out = 7, + display_alphablend_mode_dst_out = 8, + display_alphablend_mode_src_at_top = 9, + display_alphablend_mode_dst_at_top = 10, + display_alphablend_mode_xor = 11, + display_alphablend_mode_plus = 12, + display_alphablend_mode_modulate = 13, + display_alphablend_mode_src_org = 14, + display_alphablend_mode_dst_org = 15, +} display_alphablend_mode_t; + +/** + * @brief display pixel format + */ +typedef enum display_pixel_format { + display_pixel_format_argb8888, + display_pixel_format_rgb565, + display_pixel_format_rgb555, + display_pixel_format_rgb444, + display_pixel_format_gbr422, + display_pixel_format_yuv422, + display_pixel_format_ycbcr422, +} display_pixel_format_t; + +/** + * @brief display data byte order + */ +typedef enum display_byteorder { + display_byteorder_a3a2a1a0 = 0, + display_byteorder_a2a3a0a1 = 1, + display_byteorder_a1a0a3a2 = 2, + display_byteorder_a0a1a2a3 = 3, +} display_byteorder_t; + +/** + * @brief display yuv format + */ +typedef enum display_yuv_format { + display_yuv_mode_422_u1y1v1y2 = 0, + display_yuv_mode_422_v1y1u1y2, + display_yuv_mode_422_y1u1y2v1, + display_yuv_mode_422_y1v1y2u1, +} display_yuv_format_t; + +/** + * @brief display data 32 bits argb + */ +typedef union display_color_32b { + uint32_t u; + struct { + uint8_t b; + uint8_t g; + uint8_t r; + uint8_t alpha; + }; +} display_color_32b_t; + +/** + * @brief display data alpha value usage option + */ +typedef enum display_alpha_op { + display_alpha_op_invalid = 0, + display_alpha_op_override = 1, + display_alpha_op_scale = 2, +} display_alpha_op_t; + +/** + * @brief display data alphablend option + */ +typedef struct dispaly_alphablend_option { + uint8_t dst_alpha; + uint8_t src_alpha; + display_alpha_op_t dst_alpha_op; + display_alpha_op_t src_alpha_op; + display_alphablend_mode_t mode; +} display_alphablend_option_t; + +/** + * @brief display yuv to rgb format conversion coefficient + */ +typedef struct dispaly_yuv2rgb_coef { + uint16_t c0; + uint16_t c1; + uint16_t c2; + uint16_t c3; + uint16_t c4; + uint16_t uv_offset; + uint16_t y_offset; +} display_yuv2rgb_coef_t; + +/** + * @brief display yuv to rgb format conversion config + */ +typedef struct display_yuv2rgb_config { + bool enable; + bool ycbcr_mode; + display_yuv2rgb_coef_t yuv2rgb_coef; +} display_yuv2rgb_config_t; + +/** + * @brief display rgb to yuv format conversion config + */ +typedef struct display_rgb2yuv_config { + bool enable; + bool ycbcr_mode; + uint16_t c0; + uint16_t c1; + uint16_t c2; + uint16_t c3; + uint16_t c4; + uint16_t c5; + uint16_t c6; + uint16_t c7; + uint16_t c8; + uint16_t uv_offset; + uint16_t y_offset; +} display_rgb2yuv_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Display get pixel size in bit + * + * @param [in] format display_pixel_format_t + * + * @retval pixel size in bit + */ +static inline + uint8_t display_get_pixel_size_in_bit(display_pixel_format_t format) +{ + switch(format) { + case display_pixel_format_argb8888: + return 32; + case display_pixel_format_rgb565: + return 16; + case display_pixel_format_yuv422: + return 16; + case display_pixel_format_ycbcr422: + return 16; + default: + return 0; + } +} + +/** + * @brief Check whether the pixel data is yuv format + * + * @param [in] format display_pixel_format_t + * + * @retval bool: true or false + */ +static inline bool display_pixel_format_is_yuv_format(display_pixel_format_t format) +{ + switch(format) { + case display_pixel_format_yuv422: + return true; + case display_pixel_format_ycbcr422: + return true; + default: + return false; + } +} + +/** + * @brief Display get pixel size in byte + * + * @param [in] format display_pixel_format_t + * + * @retval pixel size in byte + */ +static inline + uint8_t display_get_pixel_size_in_byte(display_pixel_format_t format) +{ + return display_get_pixel_size_in_bit(format) >> 3; +} + +/** + * @brief Display get pitch length in byte + * + * @param [in] format display_pixel_format_t + * @param [in] width_in_pixel pixel width + * + * @retval pitch length in byte + */ +static inline + uint32_t display_get_pitch_length_in_byte(display_pixel_format_t format, + uint32_t width_in_pixel) +{ + return width_in_pixel * (display_get_pixel_size_in_bit(format) >> 3); +} + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif +#endif /* HPM_DISPLAY_COMMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h new file mode 100644 index 0000000000..78bcbe6655 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMA_DRV_H +#define HPM_DMA_DRV_H +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_dma_regs.h" + +/** + * + * @brief DMA driver APIs + * @defgroup dma_interface DMA driver APIs + * @ingroup io_interfaces + * @{ + */ + +#define DMA_NUM_TRANSFER_PER_BURST_1T (0U) +#define DMA_NUM_TRANSFER_PER_BURST_2T (1U) +#define DMA_NUM_TRANSFER_PER_BURST_4T (2U) +#define DMA_NUM_TRANSFER_PER_BURST_8T (3U) +#define DMA_NUM_TRANSFER_PER_BURST_16T (4U) +#define DMA_NUM_TRANSFER_PER_BURST_32T (5U) +#define DMA_NUM_TRANSFER_PER_BURST_64T (6U) +#define DMA_NUM_TRANSFER_PER_BURST_128T (7U) +#define DMA_NUM_TRANSFER_PER_BURST_256T (8U) +#define DMA_NUM_TRANSFER_PER_BURST_512T (9U) +#define DMA_NUM_TRANSFER_PER_BURST_1024T (10U) + +#define DMA_TRANSFER_WIDTH_BYTE (0U) +#define DMA_TRANSFER_WIDTH_HALF_WORD (1U) +#define DMA_TRANSFER_WIDTH_WORD (2U) +#define DMA_TRANSFER_WIDTH_DOUBLE_WORD (3U) +#define DMA_TRANSFER_WIDTH_QUAD_WORD (4U) +#define DMA_TRANSFER_WIDTH_EIGHT_WORD (5U) + +#define DMA_STATUS_ERROR_SHIFT (0U) +#define DMA_STATUS_ABORT_SHIFT (8U) +#define DMA_STATUS_TC_SHIFT (16U) + +#define DMA_CHANNEL_STATUS_ONGOING (1U) +#define DMA_CHANNEL_STATUS_ERROR (2U) +#define DMA_CHANNEL_STATUS_ABORT (4U) +#define DMA_CHANNEL_STATUS_TC (8U) + +#define DMA_CHANNEL_IRQ_STATUS_ERROR(x) (uint32_t)(1 << (DMA_STATUS_ERROR_SHIFT + x)) +#define DMA_CHANNEL_IRQ_STATUS_ABORT(x) (uint32_t)(1 << (DMA_STATUS_ABORT_SHIFT + x)) +#define DMA_CHANNEL_IRQ_STATUS_TC(x) (uint32_t)(1 << (DMA_STATUS_TC_SHIFT + x)) +#define DMA_CHANNEL_IRQ_STATUS(x) (uint32_t)(DMA_CHANNEL_IRQ_STATUS_TC(x) | \ + DMA_CHANNEL_IRQ_STATUS_ABORT(x) | \ + DMA_CHANNEL_IRQ_STATUS_ERROR(x)) + +#define DMA_CHANNEL_IRQ_STATUS_GET_ALL_TC(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_TC_SHIFT)) +#define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ABORT(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ABORT_SHIFT)) +#define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ERROR(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ERROR_SHIFT)) + +#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U) +#define DMA_HANDSHAKE_MODE_NORMAL (0U) + +#define DMA_ADDRESS_CONTROL_INCREMENT (0U) +#define DMA_ADDRESS_CONTROL_DECREMENT (1U) +#define DMA_ADDRESS_CONTROL_FIXED (2U) + +#define DMA_INTERRUPT_MASK_NONE (0U) +#define DMA_INTERRUPT_MASK_ERROR DMA_CHCTRL_CTRL_INTERRMASK_MASK +#define DMA_INTERRUPT_MASK_ABORT DMA_CHCTRL_CTRL_INTABTMASK_MASK +#define DMA_INTERRUPT_MASK_TERMINAL_COUNT DMA_CHCTRL_CTRL_INTTCMASK_MASK +#define DMA_INTERRUPT_MASK_ALL \ + (uint8_t)(DMA_INTERRUPT_MASK_TERMINAL_COUNT \ + | DMA_INTERRUPT_MASK_ABORT \ + | DMA_INTERRUPT_MASK_ERROR) + +#ifndef DMA_SUPPORT_64BIT_ADDR +#define DMA_SUPPORT_64BIT_ADDR (0) +#endif + +/** + * @brief Linked descriptor + * + * It is consumed by DMA controlled directly + */ +typedef struct dma_linked_descriptor { + uint32_t ctrl; /**< Control */ + uint32_t trans_size; /**< Transfer size in source width */ + uint32_t src_addr; /**< Source address */ + uint32_t src_addr_high; /**< Source address high 32-bit, only valid when bus width > 32bits */ + uint32_t dst_addr; /**< Destination address */ + uint32_t dst_addr_high; /**< Destination address high 32-bit, only valid when bus width > 32bits */ + uint32_t linked_ptr; /**< Linked descriptor address */ + uint32_t linked_ptr_high; /**< Linked descriptor address high 32-bit, , only valid when bus width > 32bits */ +} dma_linked_descriptor_t; + +/* @brief Channel config */ +typedef struct dma_channel_config { + uint8_t priority; /**< Channel priority */ + uint8_t src_burst_size; /**< Source burst size */ + uint8_t src_mode; /**< Source work mode */ + uint8_t dst_mode; /**< Destination work mode */ + uint8_t src_width; /**< Source width */ + uint8_t dst_width; /**< Destination width */ + uint8_t src_addr_ctrl; /**< Source address control */ + uint8_t dst_addr_ctrl; /**< Destination address control */ + uint16_t interrupt_mask; /**< Interrupt mask */ + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + uint32_t linked_ptr; /**< Next linked descriptor */ + uint32_t size_in_byte; /**< Total size to be transferred in byte */ +#if DMA_SUPPORT_64BIT_ADDR + uint32_t src_addr_high; /**< Source address high 32bits */ + uint32_t dst_addr_high; /**< Destination address high 32bits */ + uint32_t linked_ptr_high; /**< Linked descriptor high 32bits */ +#endif +} dma_channel_config_t; + + +/* @brief Channel config */ +typedef struct dma_handshake_config { + uint32_t dst; + uint32_t src; + uint32_t size_in_byte; + uint8_t ch_index; + bool dst_fixed; + bool src_fixed; +} dma_handshake_config_t; + + +/* @brief DMA specific status */ +enum { + status_dma_transfer_done = MAKE_STATUS(status_group_dma, 0), + status_dma_transfer_error = MAKE_STATUS(status_group_dma, 1), + status_dma_transfer_abort = MAKE_STATUS(status_group_dma, 2), + status_dma_transfer_ongoing = MAKE_STATUS(status_group_dma, 3), + status_dma_alignment_error = MAKE_STATUS(status_group_dma, 4), +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reset DMA + * + * @param[in] ptr DMA base address + */ +static inline void dma_reset(DMA_Type *ptr) +{ + ptr->DMACTRL |= DMA_DMACTRL_RESET_MASK; +} + +/** + * @brief Enable DMA channel + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel to be enabled + * + * @return status_success if everything's okay + */ +static inline hpm_stat_t dma_enable_channel(DMA_Type *ptr, uint32_t ch_index) +{ + ptr->CHCTRL[ch_index].CTRL |= DMA_CHCTRL_CTRL_ENABLE_MASK; + + if ((ptr->CHEN == 0) || !(ptr->CHEN & 1 << ch_index)) { + return status_fail; + } + return status_success; +} + +/** + * @brief Disable DMA channel + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel to be disabled + * + */ +static inline void dma_disable_channel(DMA_Type *ptr, uint32_t ch_index) +{ + ptr->CHCTRL[ch_index].CTRL &= ~DMA_CHCTRL_CTRL_ENABLE_MASK; +} + +/** + * @brief Abort channel transfer with mask + * + * @param[in] ptr DMA base address + * @param[in] ch_index_mask Mask of channels to be aborted + */ +static inline void dma_abort_channel(DMA_Type *ptr, uint32_t ch_index_mask) +{ + ptr->CHABORT |= DMA_CHABORT_CHABORT_SET(ch_index_mask); +} + +/** + * @brief Check if channels are enabled with mask + * + * @param[in] ptr DMA base address + * @param[in] ch_index_mask Mask of channels to be checked + * + * @return Enabled channel mask + */ +static inline uint32_t dma_check_enabled_channel(DMA_Type *ptr, + uint32_t ch_index_mask) +{ + return (ch_index_mask & ptr->CHEN); +} + +/** + * @brief Check if linked pointer has been configured + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be checked + * + * @return true if linked pointer has been configured + */ +static inline bool dma_has_linked_pointer_configured(DMA_Type *ptr, uint32_t ch_index) +{ + return ptr->CHCTRL[ch_index].LLPOINTER != 0; +} + +/** + * @brief Check transfer status + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be checked + * + * @retval 1 if transfer is still ongoing + * @retval 2 if any error occurred during transferring + * @retval 4 if transfer is aborted + * @retval 8 if transfer is finished without error + */ +static inline uint32_t dma_check_transfer_status(DMA_Type *ptr, uint8_t ch_index) +{ + volatile uint32_t tmp = ptr->INTSTATUS; + volatile uint32_t tmp_channel; + uint32_t dma_status; + + dma_status = 0; + tmp_channel = tmp & (1 << (DMA_STATUS_TC_SHIFT + ch_index)); + if (tmp_channel) { + dma_status |= DMA_CHANNEL_STATUS_TC; + ptr->INTSTATUS = tmp_channel; + } + tmp_channel = tmp & (1 << (DMA_STATUS_ERROR_SHIFT + ch_index)); + if (tmp_channel) { + dma_status |= DMA_CHANNEL_STATUS_ERROR; + ptr->INTSTATUS = tmp_channel; + } + tmp_channel = tmp & (1 << (DMA_STATUS_ABORT_SHIFT + ch_index)); + if (tmp_channel) { + dma_status |= DMA_CHANNEL_STATUS_ABORT; + ptr->INTSTATUS = tmp_channel; + } + if (dma_status == 0) { + dma_status = DMA_CHANNEL_STATUS_ONGOING; + } + return dma_status; +} + +/** + * @brief Enable DMA Channel interrupt + * + * @param [in] ptr DMA base address + * @param [in] ch_index Target channel index + * @param [in] interrupt_mask Interrupt mask + */ +static inline void dma_enable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) +{ + ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT)); +} + +/** + * @brief Disable DMA Channel interrupt + * + * @param [in] ptr DMA base address + * @param [in] ch_index Target channel index + * @param [in] interrupt_mask Interrupt mask + */ +static inline void dma_disable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) +{ + ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT)); +} + + +/** + * @brief Check Channel interrupt master + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be checked + * @return uint32_t Interrupt mask + */ +static inline uint32_t dma_check_channel_interrupt_mask(DMA_Type *ptr, uint8_t ch_index) +{ + return ptr->CHCTRL[ch_index].CTRL & (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT); +} + +/** + * @brief Get clear IRQ status + * + * @param[in] ptr DMA base address + * @param[in] mask irq mask to be cleared + */ +static inline void dma_clear_irq_status(DMA_Type *ptr, uint32_t mask) +{ + ptr->INTSTATUS = mask; /* Write-1-Clear */ +} + +/** + * @brief Get IRQ status + * + * @param[in] ptr DMA base address + */ +static inline uint32_t dma_get_irq_status(DMA_Type *ptr) +{ + return ptr->INTSTATUS; +} + +/** + * @brief Get default channel config + * + * @param[in] ptr DMA base address + * @param[in] ch Channel config + */ +void dma_default_channel_config(DMA_Type *ptr, dma_channel_config_t *ch); + +/** + * @brief Setup DMA channel + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be configured + * @param[in] ch Channel config + * + * @return status_success if everything is okay + */ +hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint32_t ch_index, + dma_channel_config_t *ch); +/** + * @brief Start DMA copy + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index + * @param[in] dst Destination address + * @param[in] src Source Address + * @param[in] size_in_byte Size in byte + * @param[in] burst_len_in_byte Burst length in byte + * + * @return status_success if everthing is okay + * @note: dst, src, size should be aligned with burst_len_in_byte + */ +hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_index, + uint32_t dst, uint32_t src, + uint32_t size_in_byte, uint32_t burst_len_in_byte); + +/** + * @brief config dma handshake function + * + * @param[in] ptr DMA base address + * @param[in] pconfig dma handshake config pointer + * + * @return status_success if everthing is okay + */ +hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_DMA_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h new file mode 100644 index 0000000000..8e0f71f1ef --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_DMAMUX_DRV_H +#define HPM_DMAMUX_DRV_H +#include "hpm_common.h" +#include "hpm_dmamux_regs.h" + +/** + * + * @brief DMAMUX driver APIs + * @defgroup dmamux_interface DMAMUX driver APIs + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Enable dmamux channel + * + * @param ptr DMAMUX base address + * @param ch_index channel to be enabled + */ +static inline void dmamux_enable_channel(DMAMUX_Type *ptr, uint8_t ch_index) +{ + ptr->MUXCFG[ch_index] |= DMAMUX_MUXCFG_ENABLE_MASK; +} + +/** + * @brief Disable dmamux channel + * + * @param ptr DMAMUX base address + * @param ch_index channel to be disabled + */ +static inline void dmamux_disable_channel(DMAMUX_Type *ptr, uint8_t ch_index) +{ + ptr->MUXCFG[ch_index] &= ~DMAMUX_MUXCFG_ENABLE_MASK; +} + +/** + * @brief Config DMAMUX + * + * @param[in] ptr DMAMUX base address + * @param[in] ch_index channel to be configured + * @param[in] src DMAMUX source + * @param[in] enable Set true to enable the channel + */ +static inline void dmamux_config(DMAMUX_Type *ptr, uint8_t ch_index, uint8_t src, bool enable) +{ + ptr->MUXCFG[ch_index] = DMAMUX_MUXCFG_SOURCE_SET(src) + | DMAMUX_MUXCFG_ENABLE_SET(enable); +} + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_DMAMUX_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dram_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dram_drv.h new file mode 100644 index 0000000000..8e96d41ccb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dram_drv.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_DRAM_DRV_H +#define _HPM_DRAM_DRV_H +#include "hpm_dram_regs.h" + +/** + * @brief DRAM driver APIs + * @defgroup dram_interface DRAM driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +#define DRAM_SDRAM_MAX_BURST_LENGTH_IN_BYTE (8UL) +/* @brief dram sdram column address bit width */ +#define DRAM_SDRAM_COLUMN_ADDR_12_BITS (0U) +#define DRAM_SDRAM_COLUMN_ADDR_11_BITS (1U) +#define DRAM_SDRAM_COLUMN_ADDR_10_BITS (2U) +#define DRAM_SDRAM_COLUMN_ADDR_9_BITS (3U) +#define DRAM_SDRAM_COLUMN_ADDR_8_BITS (4U) +/* @brief cas latency */ +#define DRAM_SDRAM_CAS_LATENCY_1 (1U) +#define DRAM_SDRAM_CAS_LATENCY_2 (2U) +#define DRAM_SDRAM_CAS_LATENCY_3 (3U) +/* @brief iomux options */ +#define DRAM_IO_MUX_NOT_USED (0U) +#define DRAM_IO_MUX_CSX0 (1U) +#define DRAM_IO_MUX_CSX1 (2U) +#define DRAM_IO_MUX_CSX2 (3U) +#define DRAM_IO_MUX_CSX3 (4U) +#define DRAM_IO_MUX_RDY (5U) +/* @brief sdram bank number */ +#define DRAM_SDRAM_BANK_NUM_4 (0U) +#define DRAM_SDRAM_BANK_NUM_2 (1U) +/* @brief chip select */ +#define DRAM_SDRAM_CS0 (0U) +#define DRAM_SDRAM_CS1 (1U) +/* @brief sdram port size */ +#define DRAM_SDRAM_PORT_SIZE_8_BITS (0U) +#define DRAM_SDRAM_PORT_SIZE_16_BITS (1U) +#define DRAM_SDRAM_PORT_SIZE_32_BITS (2U) + +#define DRAM_AXI_Q_COUNT (2U) +#define DRAM_AXI_Q_A (0U) +#define DRAM_AXI_Q_B (1U) +/* @brief DQS option */ +#define DRAM_DQS_INTERNAL (0U) +#define DRAM_DQS_FROM_PAD (1U) + +#define DRAM_BR_COUNT (2U) + +#define DRAM_CMD_KEY DRAM_IPCMD_KEY_SET(0xA55A) +#define DRAM_CMD_WRITE_FLAG (1UL << 31) +#define DRAM_CMD_SDRAM_READ (0x8U) +#define DRAM_CMD_SDRAM_WRITE (DRAM_CMD_WRITE_FLAG | 0x9U) +#define DRAM_CMD_SDRAM_MODE_SET (DRAM_CMD_WRITE_FLAG | 0xAU) +#define DRAM_CMD_SDRAM_ACTIVE (0xBU) +#define DRAM_CMD_SDRAM_AUTO_REFRESH (0xCU) +#define DRAM_CMD_SDRAM_SELF_REFRESH (0xDU) +#define DRAM_CMD_SDRAM_PRECHARGE (0xEU) +#define DRAM_CMD_SDRAM_PRECHARGE_ALL (0xFU) + +/** + * @brief Structure for specifying the configuration of AXI queue weight + */ +typedef struct { + bool enable; /**< Enable AXI weight setting flag */ + uint8_t qos; + uint8_t age; + uint8_t slave_hit_wo_rw; + uint8_t slave_hit; /**< only available for queue A */ + uint8_t page_hit; /**< only available for queue B */ + uint8_t bank_rotation; /**< only available for queue B */ +} dram_axi_q_weight_t; + +/** + * @brief Structure for specifying the configuration of SDRAM + */ +typedef struct { + uint32_t base_address; /**< external SDRAM base address */ + uint32_t size_in_byte; /**< external SDRAM size in byte */ + uint32_t refresh_count; /**< referesh count */ + uint8_t col_addr_bits; /**< column address bit count */ + uint8_t cas_latency; /**< CAS latency */ + uint8_t cs; /**< chip select */ + uint8_t cs_mux_pin; /**< chip select mux */ + uint8_t bank_num; /**< bank number */ + uint8_t prescaler; /**< presecaler */ + uint8_t port_size; /**< SDRAM port size */ + uint8_t burst_len_in_byte; /**< 1/2/4/8 bytes */ + uint8_t cke_off_in_ns; /**< Tcks */ + uint8_t act_to_precharge_in_ns; /**< Tras */ + uint8_t precharge_to_act_in_ns; /**< Trp */ + uint8_t act_to_rw_in_ns; /**< Trcd */ + uint8_t act_to_act_in_ns; /**< Trrd */ + uint8_t refresh_to_refresh_in_ns; /**< Trc */ + uint8_t write_recover_in_ns; /**< Tdpl */ + uint8_t self_refresh_recover_in_ns; /**< Txsr */ + uint8_t refresh_recover_in_ns; /**< Txsr */ + uint8_t refresh_in_ms; /**< Tref */ + uint8_t idle_timeout_in_ns; + uint8_t data_width_in_byte; + uint8_t auto_refresh_count_in_one_burst; + uint8_t delay_cell_value; /**< Delay cell value */ +} dram_sdram_config_t; + +/** + * @brief Structure for specifying the configuration of DRAM + */ +typedef struct { + uint8_t dqs; /**< DQS setting */ + uint8_t cmd_timeout; /**< command timeout */ + uint8_t bus_timeout; /**< bus timeout */ + dram_axi_q_weight_t axi_q_weight[DRAM_AXI_Q_COUNT]; +} dram_config_t; + +/** + * @brief Structure for DRAM command + */ +typedef struct { + uint32_t opcode; + uint32_t data; +} dram_cmd_t; + +/* + * @brief DRAM specific status + */ +enum { + status_dram_cmd_err = MAKE_STATUS(status_group_dram, 1), +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief dram enable + * + * Enable DRAM + * + * @param[in] ptr DRAM base address + */ +static inline void dram_enable(DRAM_Type *ptr) +{ + ptr->CTRL &= ~DRAM_CTRL_DIS_MASK; +} + +/** + * @brief dram disable + * + * Disable DRAM + * + * @param[in] ptr DRAM base address + */ +static inline void dram_disable(DRAM_Type *ptr) +{ + while((ptr->STAT0 & (uint32_t) DRAM_STAT0_IDLE_MASK) == 0) {} + ptr->CTRL |= DRAM_CTRL_DIS_MASK; +} + +/** + * @brief dram software reset + * + * Perform software reset + * + * @param[in] ptr DRAM base address + */ +static inline void dram_sw_reset(DRAM_Type *ptr) +{ + ptr->CTRL = DRAM_CTRL_RST_MASK; + while((ptr->CTRL & (uint32_t) DRAM_CTRL_RST_MASK) != 0) {} +} + +/** + * @brief dram get default config + * + * Get DRAM default parameters + * + * @param[in] ptr DRAM base address + * @param[out] config dram_config_t address + */ +void dram_default_config(DRAM_Type *ptr, dram_config_t *config); + +/** + * @brief dram init controller + * + * Initialize DRAM with give dram_config_t + * + * @param[in] ptr DRAM base address + * @param[in] config dram_config_t to initialize dram + */ +void dram_init(DRAM_Type *ptr, dram_config_t *config); + +/** + * @brief dram get typical sdram config + * + * Fill out the structure of dram_sdram_config_t with typical SDRAM parameters which should work + * with most SDRAMs. + * + * @param[in] ptr DRAM base address + * @param[out] config dram_sdram_config_t sdram configuration struction to config dram + */ +void dram_get_typical_sdram_config(DRAM_Type *ptr, dram_sdram_config_t *config); + +/** + * @brief dram config sdram + * + * Configure DRAM controlling external SDRAM using parameters specified in dram_sdram_config + * + * @param[in] ptr DRAM base address + * @param[in] clk_in_hz dram source clock frequency in Hz + * @param[in] config dram_sdram_config_t sdram configuration struction to config dram + */ +hpm_stat_t dram_config_sdram(DRAM_Type *ptr, uint32_t clk_in_hz, dram_sdram_config_t *config); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* _HPM_DRAM_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h new file mode 100644 index 0000000000..769cae31aa --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h @@ -0,0 +1,559 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ENET_DRV_H +#define HPM_ENET_DRV_H + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_common.h" +#include "hpm_enet_regs.h" +#include "hpm_soc_feature.h" +#include "hpm_enet_soc_drv.h" + +/** + * @brief Enet driver APIs + * @defgroup enet_interface Enet driver APIs + * @ingroup communication_interfaces + * @{ + */ + +/*---------------------------------------------------------------------* + * Macro Constant Declarations + *---------------------------------------------------------------------*/ +#define ENET_HEADER (14U) /**< 6-byte Dest addr, 6-byte Src addr, 2-byte type */ +#define ENET_EXTRA (2U) /**< Extra bytes in some cases */ +#define ENET_VLAN_TAG (4U) /**< optional 802.1q VLAN Tag */ +#define ENET_CRC (4U) /**< Ethernet CRC */ +#define ENET_MIN_PAYLOAD (46U) /**< Minimum Ethernet payload size */ +#define ENET_MAX_PAYLOAD (1500U) /**< Maximum Ethernet payload size */ +#define ENET_MAX_FRAME_SIZE (1524U) /**< ENET_HEADER + ENET_EXTRA + VLAN_TAG + MAX_ENET_PAYLOAD + ENET_CRC */ +#define ENET_JUMBO_FRAME_PAYLOAD (9000U) /**< Jumbo frame payload size */ + +#define ENET_ERROR (0) /**< ENET error */ +#define ENET_SUCCESS (1) /**< ENET success */ + +#define ENET_ADJ_FREQ_BASE_ADDEND (0x7fffffffUL) /**< PTP base adjustment addend */ +#define ENET_ONE_SEC_IN_NANOSEC (1000000000UL) /**< one second in nanoseconds */ +/*---------------------------------------------------------------------* + * Typedef Enum Declarations + *---------------------------------------------------------------------*/ +/** @brief Programmable burst length selections */ +typedef enum { + enet_pbl_1 = 1, + enet_pbl_2 = 2, + enet_pbl_4 = 4, + enet_pbl_8 = 8, + enet_pbl_16 = 16, + enet_pbl_32 = 32 +} enet_pbl_t; + +/** @brief Checksum insertion control selections */ +typedef enum { + enet_cic_bypass = 0, + enet_cic_insert_ipv4_header, + enet_cic_insert_tcp_udp_icmp, + enet_cic_insert_tcp_upd_icmp, +} enet_insert_t; + +/** @brief PHY opeartion selections */ +typedef enum { + enet_phy_op_read = 0, + enet_phy_op_write +} enet_phy_op_t; + + +/** @brief PHY status */ +typedef enum { + enet_phy_idle = 0, + enet_phy_busy +} enet_phy_status_t; + +/** @brief CSR clock range and MDC clock selections */ +/** @note The suggested range of CSR clock is approximately + * between the frequency range 1.0MHz-2.5MHz. + * You can achieve higher frequency of the MDC clock than the frequency limit of 2.5MHz(specified in the IEEE Std 802.3) + * and program a clock divider of lower value. Program the value which is no less than enet_csr_60m_to_100m_mdc_csr_div_4 + * only if the interfacing chips support faster MDC clocks. + */ +typedef enum { + enet_csr_60m_to_100m_mdc_csr_div_42 = 0, /**< CSR clock range: 60-100MHz <==> MDC clock: CSR clock / 42 */ + enet_csr_100m_to_150m_mdc_csr_div_62, /**< CSR clock range: 100-150MHz <==> MDC clock: CSR clock / 62 */ + enet_csr_20m_to_35m_mdc_csr_div_16, /**< CSR clock range: 20-35MHz <==> MDC clock: CSR clock / 16 */ + enet_csr_35m_to_60m_mdc_csr_div_26, /**< CSR clock range: 35-60MHz <==> MDC clock: CSR clock / 26 */ + enet_csr_150m_to_250m_mdc_csr_div_102, /**< CSR clock range: 150-250MHz <==> MDC clock: CSR clock / 102 */ + enet_csr_250m_to_300m_mdc_csr_div_124, /**< CSR clock range: 250-300MHz <==> MDC clock: CSR clock / 124 */ + + enet_csr_60m_to_100m_mdc_csr_div_4 = 8, /**< CSR clock / 4 */ + enet_csr_60m_to_100m_mdc_csr_div_6, /**< CSR clock / 6 */ + enet_csr_60m_to_100m_mdc_csr_div_8, /**< CSR clock / 8 */ + enet_csr_60m_to_100m_mdc_csr_div_10, /**< CSR clock / 10 */ + enet_csr_60m_to_100m_mdc_csr_div_12, /**< CSR clock / 12 */ + enet_csr_60m_to_100m_mdc_csr_div_14, /**< CSR clock / 14 */ + enet_csr_60m_to_100m_mdc_csr_div_16, /**< CSR clock / 16 */ + enet_csr_60m_to_100m_mdc_csr_div_18 /**< CSR clock / 18 */ +} enet_csr_clk_range_t; + +/** @brief enet interface selections */ +typedef enum { + enet_inf_rmii = 4, + enet_inf_rgmii = 1 +} enet_inf_type_t; + +/** @brief enet timestamp update methods */ +typedef enum { + enet_ptp_time_coarse_update = 0, + enet_ptp_time_fine_update +} enet_ptp_time_update_method_t; + +/** @brief PTP versions */ +typedef enum { + enet_ptp_v1 = 0, + enet_ptp_v2 +} enet_ptp_version_t; + +/** @brief PTP frame types */ +typedef enum { + enet_ptp_frame_ipv4 = 0, + enet_ptp_frame_ipv6, + enet_ptp_frame_ethernet +} enet_ptp_frame_type_t; + +/** @brief PTP message type for snapshots */ +typedef enum { + enet_ts_ss_ptp_msg_0 = 0, /* SYNC, Follow_Up, Delay_Req, Delay_Resp */ + enet_ts_ss_ptp_msg_1 = 1, /* SYNC */ + enet_ts_ss_ptp_msg_2 = 3, /* Delay_Req */ + enet_ts_ss_ptp_msg_3 = 4, /* SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, Pdelay_Resp_Follow_Up */ + enet_ts_ss_ptp_msg_4 = 5, /* SYNC, Pdelay_Req, Pdelay_Resp */ + enet_ts_ss_ptp_msg_5 = 7, /* Delay_Req, Pdelay_Req, Pdelay_Resp */ + enet_ts_ss_ptp_msg_6 = 8, /* SYNC, Delay_Req */ + enet_ts_ss_ptp_msg_7 = 12 /* Pdelay_Req, Pdelay_Resp */ +} enet_ts_ss_ptp_msg_t; + +typedef enum { + enet_ptp_count_res_high = 0, /* ptp sub-second count resolution at 0.465 ns */ + enet_ptp_count_res_low /* ptp su-second count resolution at 1 ns */ +} enet_ptp_count_res_t; + +/*---------------------------------------------------------------------* + * Typedef Struct Declarations + *---------------------------------------------------------------------*/ +/** @brief enet buffer config struct */ +typedef struct { + uint32_t buffer; + uint32_t count; + uint16_t size; +} enet_buff_config_t; + + +/** @brief enet mac config struct */ +typedef struct { + uint32_t mac_addr_high[ENET_SOC_ADDR_MAX_COUNT]; + uint32_t mac_addr_low[ENET_SOC_ADDR_MAX_COUNT]; + uint8_t valid_max_count; +} enet_mac_config_t; + +/** @brief transmission descriptor struct */ +typedef struct { + union { + uint32_t tdes0; + struct { + uint32_t db: 1; /**< * Deferred Bit*/ + uint32_t uf: 1; /**< * Underflow Error */ + uint32_t ed: 1; /**< * Excessive Deferral */ + uint32_t cc: 4; /**< * Collision Count */ + uint32_t vf: 1; /**< * VLAN Frame */ + uint32_t ec: 1; /**< * Excessive Collision */ + uint32_t lc: 1; /**< * Late Collision */ + uint32_t nc: 1; /**< * No Carrier */ + uint32_t loc: 1; /**< * Loss of Carrier */ + uint32_t ipe: 1; /**< * IP Payload Error */ + uint32_t ff: 1; /**< * Frame Flushed */ + uint32_t jt: 1; /**< * Jabber Timeout */ + uint32_t es: 1; /**< * Error Summary */ + uint32_t ihe: 1; /**< * IP Header Error */ + uint32_t ttss: 1; /**< * Transmit Timestamp Status */ + uint32_t vlic: 2; /**< * VLAN Insertion Control */ + uint32_t tch: 1; /**< * Second Address Chained */ + uint32_t ter: 1; /**< * Transmit End of Ring */ + uint32_t cic: 2; /**< * Checksum Insertion Control */ + uint32_t crcr: 1; /**< * CRC Replacement Control */ + uint32_t ttse: 1; /**< * Transmit Timestamp Enable */ + uint32_t dp: 1; /**< * Disable Pad */ + uint32_t dc: 1; /**< * Disable CRC */ + uint32_t fs: 1; /**< * First Segment */ + uint32_t ls: 1; /**< * Last Segment */ + uint32_t ic: 1; /**< * Interrupt on Completion */ + uint32_t own: 1; /**< * Own Bit */ + } tdes0_bm; + }; + + union { + uint32_t tdes1; + struct { + uint32_t tbs1 : 13; /**< Transmit Buffer 1 Size */ + uint32_t reserved: 3; /**< Reserved */ + uint32_t tbs2 : 13; /**< Transmit Buffer 2 Size */ + uint32_t saic : 3; /**< SA Inertion Control */ + } tdes1_bm; + }; + + union { + uint32_t tdes2; + struct { + uint32_t buffer1; /**< Buffer 1 Address */ + } tdes2_bm; + }; + + union { + uint32_t tdes3; + union { + uint32_t buffer2; /**< Buffer 2 Address */ + uint32_t next_desc; /**< Next Descriptor Address */ + } tdes3_bm; + }; + +#if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN + struct { + uint32_t reserved; + } tdes4_bm; + + struct { + uint32_t reserved; + } tdes5_bm; + + struct { + uint32_t ttsl; /**< Transmit Frame Timestamp Low */ + } tdes6_bm; + + struct { + uint32_t ttsh; /**< Transmit Frame Timestamp High */ + } tdes7_bm; +#endif +} enet_tx_desc_t; + + +/** @brief reception descriptor struct */ +typedef struct +{ + union { + uint32_t rdes0; + + struct { + uint32_t ex_sta_rx_addr : 1; /**< Extended Status Available or Rx MAC Address*/ + uint32_t ce : 1; /**< CRC Error */ + uint32_t dbe : 1; /**< Dribble Bit Error */ + uint32_t re : 1; /**< Receive Error */ + uint32_t rwt : 1; /**< Receive Watchdog Timeout */ + uint32_t ft : 1; /**< Frame Type */ + uint32_t lc : 1; /**< Late Collision */ + uint32_t ts_ip_gf : 1; /**< Timestamp Available, IP Checksum Error or Giant Frame*/ + uint32_t ls : 1; /**< Last Descriptor */ + uint32_t fs : 1; /**< First Descriptor */ + uint32_t vlan : 1; /**< VLAN Tag */ + uint32_t oe : 1; /**< Overflow Error */ + uint32_t le : 1; /**< Length Error */ + uint32_t saf : 1; /**< Source Address Filter Fail */ + uint32_t dse : 1; /**< Descriptor Error */ + uint32_t es : 1; /**< Error Summary */ + uint32_t fl : 14; /**< Frame Length */ + uint32_t afm : 1; /**< Destination Address Filter Fail */ + uint32_t own : 1; /**< Own Bit */ + } rdes0_bm; + }; + + union { + uint32_t rdes1; + struct { + uint32_t rbs1 : 13; /**< Receive Buffer 1 Size */ + uint32_t reserved0: 1; /**< Reserved */ + uint32_t rch : 1; /**< Second Address Chained */ + uint32_t rer : 1; /**< Receive End of Ring */ + uint32_t rbs2 : 13; /**< Receive Buffer 2 Size */ + uint32_t reserved1: 2; /**< Reserved */ + uint32_t dic : 1; /**< Disable Interrupt on Completion */ + } rdes1_bm; + }; + + union { + uint32_t rdes2; + struct { + uint32_t buffer1; /**< Buffer 1 Address */ + } rdes2_bm; + }; + + union { + uint32_t rdes3; + union { + uint32_t buffer2; /**< Buffer 2 Address */ + uint32_t next_desc; /**< Next Descriptor Address */ + } rdes3_bm; + }; + +#if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN + union { + uint32_t rdes4; + struct { + uint32_t ip_payload_type : 3; /**< IP Payload Type */ + uint32_t ip_header_err : 1; /**< IP Header Error */ + uint32_t ip_payload_err : 1; /**< IP Payload Error */ + uint32_t ip_chksum_bypassed : 1; /**< IP Checksum Bypassed */ + uint32_t ipv4_pkt_received : 1; /**< IPv4 Packet Received */ + uint32_t ipv6_pkt_received : 1; /**< IPv6 Packet Received */ + uint32_t msg_type : 4; /**< Message Type */ + uint32_t ptp_frame_type : 1; /**< PTP Frame Type */ + uint32_t ptp_version : 1; /**< PTP Version */ + uint32_t ts_dp : 1; /**< Timestamp Dropped */ + uint32_t reserved0 : 1; /**< Reserved */ + uint32_t av_pkt_recv : 1; /**< AV Packet Received */ + uint32_t av_tagged_pkt_recv : 1; /**< AV Tagged Packet Received */ + uint32_t vlan_tag_pri_value : 3; /**< VLAN Tag Priority Value */ + uint32_t reserved1 : 3; /**< Reserved */ + uint32_t l3_fm : 1; /**< Layer 3 Filter Matched */ + uint32_t l4_fm : 1; /**< Layer 4 Filter Matched */ + uint32_t l3_l4_fnl : 2; /**< Layer 3 and Layer 4 Filter Number Matched */ + uint32_t reserved2 : 4; /**< Reserved */ + } rdes4_bm; + }; + + struct { + uint32_t reserved; + } rdes5_bm; + + struct { + uint32_t rtsl; /**< Receive Frame Timestamp Low */ + }rdes6_bm; + + struct { + uint32_t rtsh; /**< Receive Frame Timestamp High */ + } rdes7_bm; +#endif +} enet_rx_desc_t; + +/** @brief enet frame struct */ +typedef struct{ + uint32_t length; + uint32_t buffer; + enet_rx_desc_t *rx_desc; +} enet_frame_t; + +/** @brief enet reception frame info struct */ +typedef struct { + enet_rx_desc_t *fs_rx_desc; + enet_rx_desc_t *ls_rx_desc; + uint32_t seg_count; +} enet_rx_frame_info_t; + +/** @brief enet description struct */ +typedef struct { + enet_tx_desc_t *tx_desc_list_head; + enet_rx_desc_t *rx_desc_list_head; + enet_tx_desc_t *tx_desc_list_cur; + enet_rx_desc_t *rx_desc_list_cur; + enet_buff_config_t tx_buff_cfg; + enet_buff_config_t rx_buff_cfg; + enet_rx_frame_info_t rx_frame_info; +} enet_desc_t; + +/** @brief PTP timestamp struct */ +typedef struct { + uint32_t sec; + uint32_t nsec; + uint8_t sign; +} enet_ptp_time_t; + +/* PTP config strcut */ +typedef struct { + uint8_t ssinc; + uint8_t sub_sec_count_res; + uint8_t update_method; + uint32_t addend; +} enet_ptp_config_t; + +/* + * @brief Bit definition of TDES1 + */ +#define ENET_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /**< Transmit Buffer2 Size */ +#define ENET_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /**< Transmit Buffer1 Size */ + +#if defined __cplusplus +extern "C" { +#endif /* __cplusplus */ +/*---------------------------------------------------------------------* + * Exported Functions + *---------------------------------------------------------------------*/ +/** + * @brief Initialize controller + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] inf_type the specified interface + * @param[in] desc A pointer to descriptor config + * @param[in] config A pointer to mac config + * @param[in] intr A mask of all required interrupts + * @pramm[in] mask_intr A mask of all not required interrupts + */ +int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, uint32_t intr, uint32_t mask_intr); +/** + * @brief Read phy + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] phy_addr the specified address of phy + * @param[in] addr the specified address of register + * @retval A value corresponding to the specifeid register address + */ +uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr); + +/** + * @brief Write phy + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] phy_addr a specified address of phy + * @param[in] addr a specified address of the register + * @param[in] data a specified data to be written + */ +void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data); + +/** + * @brief Check if there is a received frame + * + * @param[out] parent_rx_desc_list_cur a parrent pointer to the current reception descritpion list + * @param[in] rx_frame_info A pointer to the information of the reception frames + * @retval A result of reception frame. + * 1 means that a reception of frame is successful. + * 0 means that a reception of frame is unsuccessful. + */ +uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); + +/** + * @brief get a received frame + * + * @param[out] parent_rx_desc_list_cur A parrent pointer to the current reception descritpion list + * @param[in] rx_frame_info A pointer to the information of the reception frames + * @retval A struct of the current reception frame + */ +enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); + +/** + * @brief get a received frame from interrupt + * + * @param[out] parent_rx_desc_list_cur the parrent pointer to the current reception descritpion list + * @param[in] rx_frame_info A pointer to the information of the reception frames + * @param[in] rx_desc_count A total count of the reception descriptors + * @retval A struct of the current reception frame + */ +enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count); + +/** + * @brief prepare for the transmission descriptors + * + * @param[in] ptr An Ethernet peripheral base address + * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames + * @param[in] frame_length the length of the transmission + * @param[in] tx_buff_size the size of the transmission buffer + * @retval a result of the transmission preparation. + * 1 means that the preparation is successful. + * 0 means that the prepartion is unsuccessful. + */ +uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size); + +/** + * @brief Initialize DMA transmission descriptors in chain mode + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] desc A pointer to transmission descriptors + */ +void enet_dma_tx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); + +/** + * @brief Initialize DMA reception descriptors in chain mode + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] desc A pointer to reception descriptors + */ +void enet_dma_rx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); + +/** + * @brief Flush DMA + * + * @param[in] ptr An Ethernet peripheral base address + */ +void enet_dma_flush(ENET_Type *ptr); + +/** + * @brief Initialize a PTP timer + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] config A pointer to an enet_ptp_config struct instance + */ +void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config); + +/** + * @brief Set a timestamp to the PTP timer + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] timestamp A pointer to a timestamp structure instance + */ +void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp); + +/** + * @brief Get a timestamp from the PTP timer + * + * @param[in] ptr An Ethernet peripheral base address + * @param[out] timestamp A pointer to a timestamp structure instance + */ +void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp); + +/** + * @brief Update a timestamp to the PTP timer + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] timeoffset A pointer to a timestamp structure instance + */ +void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_time_t *timeoffset); + +/** + * @brief Adjust the count frequency of the PTP timer + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] adj An adjustment value for the count frequency of the PTP timer + */ +void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj); + +/** + * @brief Set the PTP version + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] ptp_ver An enum value indicating the PTP protocol + */ +void enet_set_ptp_version(ENET_Type *ptr, enet_ptp_version_t ptp_ver); + +/** + * @brief Enable the specified ptp frame type for MAC process + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] ptp_frame_type An enum value indicating the transport protocol of PTP frames + * @param[in] enable A value to enable or disable the transport protocol of PTP frames which is specified by ptp_frame_type parameter + * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success + */ +hpm_stat_t enet_enable_ptp_frame_type(ENET_Type *ptr, enet_ptp_frame_type_t ptp_frame_type, bool enable); + +/** + * @brief Set the ptp message type for snapshots + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] ts_ss_ptp_msg An enum value indicating the specified ptp message type for snapshots + */ +void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ss_ptp_msg); + +#if defined __cplusplus +} +#endif /* __cplusplus */ + +/** @} */ +#endif /* HPM_ENET_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h new file mode 100644 index 0000000000..915f7c1727 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_FFA_DRV_H +#define HPM_FFA_DRV_H + +#include "hpm_common.h" +#include "hpm_ffa_regs.h" + +/** + * @brief FFA driver APIs + * @defgroup ffa_interface FFA driver APIs + * @ingroup ffa_interfaces + * @{ + * + */ + +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ +/** + * @brief Operation commands supported by FFA + */ +#define FFA_OPCMD_FIR (0U) /* !< FIR operation command index */ +#define FFA_OPCMD_FFT (2U) /* !< FFT operation command index */ + +/** + * @brief Data type supported by FFA + */ +#define FFA_DATA_TYPE_REAL_Q31 (0U) /* !< FFA Data type: Real Q31 */ +#define FFA_DATA_TYPE_REAL_Q15 (1U) /* !< FFA Data type: Real Q15 */ +#define FFA_DATA_TYPE_COMPLEX_Q31 (2U) /* !< FFA Data type: Complex Q31 */ +#define FFA_DATA_TYPE_COMPLEX_Q15 (3U) /* !< FFA Data type: Complex Q15 */ + +/** + * @brief FFA Q31 data type definition + */ +typedef int32_t ffa_q31_t; + +/** + * @brief FFA Q15 data type definition + */ +typedef int16_t ffa_q15_t; + +/** + * @brief FFA complex Q31 data type definition + */ +typedef struct { + ffa_q31_t real; + ffa_q31_t image; +} ffa_complex_q31_t; + +/** + * @brief FFA complex Q15 data type definition + */ +typedef struct { + ffa_q15_t real; + ffa_q15_t image; +} ffa_complex_q15_t; + +/** + * @brief FFT transform context + */ +typedef struct { + uint16_t is_ifft; /* !< Is Inverse FFT transform */ + uint8_t src_data_type; /* !< Source data type */ + uint8_t dst_data_type; /* !< Destination date type */ + uint32_t num_points; /* !< Number of points */ + const void *src; /* !< Source data buffer */ + void *dst; /* !< Destination Data buffer */ + uint32_t interrupt_mask; /* !< Interrupt mask */ +} fft_xfer_t; + +/** + * @brief FIR transform context + */ +typedef struct { + uint16_t data_type; /* !< Data type */ + uint16_t coef_taps; /* !< Coefficient taps */ + uint32_t input_taps; /* !< Input data taps */ + const void *src; /* !< Source data buffer */ + const void *coeff; /* !< Coefficient data buffer */ + void *dst; /* !< Destination data buffer */ + uint32_t interrupt_mask; /* !< Interrupt mask */ +} fir_xfer_t; + +/** + * @brief FFA error codes + */ +enum { + status_ffa_fir_overflow = MAKE_STATUS(status_group_ffa, 0), /* !< FIR overflow */ + status_ffa_fft_overflow = MAKE_STATUS(status_group_ffa, 1), /* !< FFR overflow */ + status_ffa_write_error = MAKE_STATUS(status_group_ffa, 2), /* !< FFA write error */ + status_ffa_read_next_error = MAKE_STATUS(status_group_ffa, 3), /* !< FFA read next data error */ + status_ffa_read_error = MAKE_STATUS(status_group_ffa, 4), /*!< FFA read error */ +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable FFA module and start an specified FFA operation + * + * @param [in] ptr FFA base address + */ +static inline void ffa_enable(FFA_Type *ptr) +{ + ptr->CTRL = (ptr->CTRL & ~FFA_CTRL_SFTRST_MASK) | FFA_CTRL_EN_MASK; +} + +/** + * @brief Stop FFA module + * + * @param [in] ptr FFA base address + */ +static inline void ffa_disable(FFA_Type *ptr) +{ + ptr->CTRL = (ptr->CTRL & ~FFA_CTRL_EN_MASK) | FFA_CTRL_SFTRST_MASK; +} + +/** + * @brief Get FFA status + * + * @param [in] ptr FFA base address + * @return FFA status register value + */ +static inline uint32_t ffa_get_status(FFA_Type *ptr) +{ + return ptr->STATUS; +} + +/** + * @brief Enable FFA Interrupt + * + * @param [in] ptr FFA base address + * @param [in] mask FFA interrupt mask + */ +static inline void ffa_enable_interrupt(FFA_Type *ptr, uint32_t mask) +{ + ptr->INT_EN |= mask; +} + +/** + * @brief Disable FFA interrupt + * + * @param [in] ptr FFA base address + * @param [in] mask FFA interrupt mask + */ +static inline void ffa_disable_interrupt(FFA_Type *ptr, uint32_t mask) +{ + ptr->INT_EN &= ~mask; +} + +/** + * @brief Start an FFT operation + * + * @param [in] ptr FFA base address + * @param [in] fft_xfer FFT transform context + */ +void ffa_start_fft(FFA_Type *ptr, fft_xfer_t *fft_xfer); + +/** + * @brief Start an FIR operation + * + * @param [in] ptr FFA base address + * @param [in] fir_xfer FIR transform context + */ +void ffa_start_fir(FFA_Type *ptr, fir_xfer_t *fir_xfer); + +/** + * @brief Perform FFT transformation in blocking mode + * + * @param [in] ptr FFA base address + * @param [in, out] fft_xfer FFT transform context + * @return FFT operation result + */ +hpm_stat_t ffa_calculate_fft_blocking(FFA_Type *ptr, fft_xfer_t *fft_xfer); + +/** + * @brief Perform FIR transform in blocking mode + * + * @param [in] ptr FFA base address + * @param [in, out] fir_xfer FIR transform context + * @return FIR operation result + */ +hpm_stat_t ffa_calculate_fir_blocking(FFA_Type *ptr, fir_xfer_t *fir_xfer); + + +#ifdef __cplusplus +} +#endif +/** + * @} + * + */ + + +#endif /* HPM_FFA_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h new file mode 100644 index 0000000000..c15c19b1e2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIO_DRV_H +#define HPM_GPIO_DRV_H + +#include "hpm_common.h" +#include "hpm_gpio_regs.h" + +#ifndef PORT_PIN_COUNT +#define PORT_PIN_COUNT (32U) +#endif +#define GPIO_GET_PORT_INDEX(x) (x / PORT_PIN_COUNT) +#define GPIO_GET_PIN_INDEX(x) (x % PORT_PIN_COUNT) + +/** + * + * @brief GPIO driver APIs + * @defgroup gpio_interface GPIO driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Interrupt trigger type + */ +typedef enum gpio_interrupt_trigger { + gpio_interrupt_trigger_level_high = 0, + gpio_interrupt_trigger_level_low, + gpio_interrupt_trigger_edge_rising, + gpio_interrupt_trigger_edge_falling, +} gpio_interrupt_trigger_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Read target pin level + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + * + * @return Pin status mask + */ +static inline uint8_t gpio_read_pin(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + return (ptr->DI[port].VALUE & (1 << pin)) >> pin; +} + +/** + * @brief Toggle pin level + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + */ +static inline void gpio_toggle_pin(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + ptr->DO[port].TOGGLE = 1 << pin; +} + +/** + * @brief Write pin level + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + * @param high Pin level set to high when it is set to true + */ +static inline void gpio_write_pin(GPIO_Type *ptr, uint32_t port, uint8_t pin, uint8_t high) +{ + if (high) { + ptr->DO[port].SET = 1 << pin; + } else { + ptr->DO[port].CLEAR = 1 << pin; + } +} + +/** + * @brief Set pin to input mode + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + */ +static inline void gpio_set_pin_input(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + ptr->OE[port].CLEAR = 1 << pin; +} + +/** + * @brief Set pin to output mode + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + */ +static inline void gpio_set_pin_output(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + ptr->OE[port].SET = 1 << pin; +} + +/** + * @brief Set pin to output mode with initial value + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + * @param initial Initial value + */ +void gpio_set_pin_output_with_initial(GPIO_Type *ptr, uint32_t port, uint8_t pin, uint8_t initial); + +/** + * @brief Check specific pin interrupt status + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + * + * @return true if interrupt flag is set + */ +static inline bool gpio_check_pin_interrupt_flag(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + return ptr->IF[port].VALUE & (1 << pin); +} + +/** + * @brief Clear specific pin interrupt flag + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + */ +static inline void gpio_clear_pin_interrupt_flag(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + ptr->IF[port].VALUE = 1 << pin; +} + +/** + * @brief Check if specific pin interrupt is enabled or not + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + * + * @return true if interrupt is enabled + */ +static inline bool gpio_check_pin_interrupt_enabled(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + return (ptr->IE[port].VALUE & (1 << pin)) == (1 << pin); +} + +/** + * @brief Enable interrupt for specific pin + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + */ +static inline void gpio_enable_pin_interrupt(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + ptr->IE[port].SET = 1 << pin; +} + +/** + * @brief Disable interrupt for specific pin + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + */ +static inline void gpio_disable_pin_interrupt(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + ptr->IE[port].CLEAR = 1 << pin; +} + +/** + * @brief Check interrupt flag of specific pin and clear if it is set + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + * + * @return true if the interrupt flag is set and cleared + * @return false if the interrupt flag is not set + */ +static inline bool gpio_check_clear_interrupt_flag(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + if (!gpio_check_pin_interrupt_flag(ptr, port, pin)) { + return false; + } + gpio_clear_pin_interrupt_flag(ptr, port, pin); + return true; +} + + +/** + * @brief Read all pins level on specific port + * + * @param ptr GPIO base address + * @param port Port index + * + * @return Port pin level status + */ +static inline uint32_t gpio_read_port(GPIO_Type *ptr, uint32_t port) +{ + return ptr->DI[port].VALUE; +} + +/** + * @brief Toggle port with specific pin mask + * + * @param ptr GPIO base address + * @param port Port index + * @param mask Mask pins to be toggled + */ +static inline void gpio_toggle_port_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) +{ + ptr->DO[port].TOGGLE = mask; +} + +/** + * @brief Write specific port with value + * + * @param ptr GPIO base address + * @param port Port index + * @param value Value to be written + */ +static inline void gpio_write_port(GPIO_Type *ptr, uint32_t port, uint32_t value) +{ + ptr->DO[port].VALUE = value; +} + +/** + * @brief Set spcific port pin high according to the given mask + * + * @param ptr GPIO base address + * @param port Port index + * @param mask Mask of pins to be set to low + */ +static inline void gpio_set_port_low_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) +{ + ptr->DO[port].CLEAR = mask; +} + +/** + * @brief Set spcific port pin high according to the given mask + * + * @param ptr GPIO base address + * @param port Port index + * @param mask Mask of pins to be set to high + */ +static inline void gpio_set_port_high_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) +{ + ptr->DO[port].SET = mask; +} + +/** + * @brief Enable pins output of specific port according to the given mask + * + * @param ptr GPIO base address + * @param port Port index + * @param mask Mask of pins to be enabled + */ +static inline void gpio_enable_port_output_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) +{ + ptr->OE[port].SET = mask; +} + +/** + * @brief Disable pins output of specific port according to the given mask + * + * @param ptr GPIO base address + * @param port Port index + * @param mask Mask of pins to be disabled + */ +static inline void gpio_disable_port_output_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) +{ + ptr->OE[port].CLEAR = mask; +} + +/** + * @brief Get current interrupt flags on specific port + * + * @param ptr GPIO base address + * @param port Port index + * + * @return Current interrupt flags on specific port + */ +static inline uint32_t gpio_get_port_interrupt_flags(GPIO_Type *ptr, uint32_t port) +{ + return ptr->IF[port].VALUE; +} + + +/** + * @brief Clear interrupt flags with given mask on specific port + * + * @param ptr GPIO base address + * @param port Port index + * @param mask Mask of interrupts to be cleared + */ +static inline void gpio_clear_port_interrupt_flags_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) +{ + ptr->IF[port].VALUE |= mask; +} + +/** + * @brief Enable interrupts with given mask on specific port + * + * @param ptr GPIO base address + * @param port Port index + * @param mask Mask of interrupts to be enabled + */ +static inline void gpio_enable_port_interrupt_with_mask(GPIO_Type *ptr, uint32_t port, uint8_t mask) +{ + ptr->IE[port].SET = mask; +} + +/** + * @brief Disable interrupts with given mask on specific port + * + * @param ptr GPIO base address + * @param port Port index + * @param mask Mask of interrupts to be disabled + */ +static inline void gpio_disable_port_interrupt_with_mask(GPIO_Type *ptr, uint32_t port, uint8_t mask) +{ + ptr->IE[port].CLEAR = mask; +} + + +/** + * @brief Config pin interrupt + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + * @param trigger Trigger type + */ +void gpio_config_pin_interrupt(GPIO_Type *ptr, uint32_t port, uint8_t pin, gpio_interrupt_trigger_t trigger); + + +/** + * @brief Toggle pin interrupt trigger polarity + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + */ +void gpio_toggle_pin_interrupt_trigger_polarity(GPIO_Type *ptr, uint32_t port, uint8_t pin); + +/** + * @brief Toggle pin interrupt trigger type + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + */ +void gpio_toggle_pin_interrupt_trigger_type(GPIO_Type *ptr, uint32_t port, uint8_t pin); +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_GPIO_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h new file mode 100644 index 0000000000..fa64b0c388 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIOM_DRV_H +#define HPM_GPIOM_DRV_H + +#include "hpm_gpiom_regs.h" +#include "hpm_gpiom_soc_drv.h" + +/** + * + * @brief GPIOM driver APIs + * @defgroup gpiom_interface GPIOM driver APIs + * @ingroup io_interfaces + * @{ + */ + +/* @brief pin visibility */ +typedef enum gpiom_pin_visibility { + gpiom_pin_visible = 0, + gpiom_pin_invisible = 1, +} gpiom_pin_visibility_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get pin's controller + * + * @param ptr GPIOM base address + * @param gpio_index gpio port index + * @param pin_index pin index + * + * @retval pin control module + */ +static inline gpiom_gpio_t gpiom_get_pin_controller(GPIOM_Type *ptr, + uint8_t gpio_index, + uint8_t pin_index) +{ + return (gpiom_gpio_t)((ptr->ASSIGN[gpio_index].PIN[pin_index] + & (GPIOM_PIN_SELECT_MASK)) >> GPIOM_PIN_SELECT_SHIFT); +} + +/** + * @brief set pin's controller + * + * @param ptr GPIOM base address + * @param gpio_index gpio port index + * @param pin_index pin index + * @param gpio gpio module index + */ +static inline void gpiom_set_pin_controller(GPIOM_Type *ptr, + uint8_t gpio_index, + uint8_t pin_index, + gpiom_gpio_t gpio) +{ + ptr->ASSIGN[gpio_index].PIN[pin_index] = + (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~(GPIOM_PIN_SELECT_MASK)) + | GPIOM_PIN_SELECT_SET(gpio); +} + +/** + * @brief Check if pin is visibility for specified module + * + * @param ptr GPIOM base address + * @param gpio_index gpio port index + * @param pin_index pin index + * @param gpio gpio module index + * + * @retval true if pin is visible by specified module + * @retval false if pin is not visible by specified module + */ +static inline bool gpiom_check_pin_visibility(GPIOM_Type *ptr, + uint8_t gpio_index, + uint8_t pin_index, + gpiom_gpio_t gpio) +{ + return (ptr->ASSIGN[gpio_index].PIN[pin_index] & ((1 << gpio) << GPIOM_PIN_HIDE_SHIFT)) + >> GPIOM_PIN_HIDE_SHIFT >> gpio == gpiom_pin_visible; +} + +/** + * @brief enable pin visibility for specified module + * + * @param ptr GPIOM base address + * @param gpio_index gpio port index + * @param pin_index pin index + * @param gpio gpio module index + */ +static inline void gpiom_enable_pin_visibility(GPIOM_Type *ptr, + uint8_t gpio_index, + uint8_t pin_index, + gpiom_gpio_t gpio) +{ + ptr->ASSIGN[gpio_index].PIN[pin_index] = + (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~((1 << gpio) << GPIOM_PIN_HIDE_SHIFT)); +} + +/** + * @brief disable pin visibility for specified module + * + * @param ptr GPIOM base address + * @param gpio_index gpio port index + * @param pin_index pin index + * @param gpio gpio module index + */ +static inline void gpiom_disable_pin_visibility(GPIOM_Type *ptr, + uint8_t gpio_index, + uint8_t pin_index, + gpiom_gpio_t gpio) +{ + ptr->ASSIGN[gpio_index].PIN[pin_index] = + (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~((1 << gpio) << GPIOM_PIN_HIDE_SHIFT)) + | GPIOM_PIN_HIDE_SET(1 << gpio); +} + +/** + * @brief Check if pin management is locked + * + * @param ptr GPIOM base address + * @param gpio_index gpio port index + * @param pin_index pin index + * + * @retval true if pin management is locked + * @retval false if pin management is not locked + */ +static inline bool gpiom_pin_is_locked(GPIOM_Type *ptr, + uint8_t gpio_index, + uint8_t pin_index) +{ + return (ptr->ASSIGN[gpio_index].PIN[pin_index] & GPIOM_PIN_LOCK_MASK) + == GPIOM_PIN_LOCK_MASK; +} + +/** + * @brief lock pin management + * + * @param ptr GPIOM base address + * @param gpio_index gpio port index + * @param pin_index pin index + */ +static inline void gpiom_lock_pin(GPIOM_Type *ptr, + uint8_t gpio_index, + uint8_t pin_index) +{ + ptr->ASSIGN[gpio_index].PIN[pin_index] |= GPIOM_PIN_LOCK_MASK; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_GPIOM_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h new file mode 100644 index 0000000000..d661f7c311 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPTMR_DRV_H +#define HPM_GPTMR_DRV_H +#include "hpm_common.h" +#include "hpm_gptmr_regs.h" + +/** + * @brief GPTMR driver APIs + * @defgroup gptmr_interface GPTMR driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief GPTMR channel IRQ mask + */ +#define GPTMR_CH_CMP_IRQ_MASK(ch, cmp) (1 << (ch * 4 + 2 + cmp)) +#define GPTMR_CH_CAP_IRQ_MASK(ch) (1 << (ch * 4 + 1)) +#define GPTMR_CH_RLD_IRQ_MASK(ch) (1 << (ch * 4)) + +/** + * @brief GPTMR channel status + */ +#define GPTMR_CH_CMP_STAT_MASK(ch, cmp) (1 << (ch * 4 + 2 + cmp)) +#define GPTMR_CH_CAP_STAT_MASK(ch) (1 << (ch * 4 + 1)) +#define GPTMR_CH_RLD_STAT_MASK(ch) (1 << (ch * 4)) + +/** + * @brief GPTMR one channel support output comparator count + */ +#define GPTMR_CH_CMP_COUNT (2U) + +/** + * @brief GPTMR synci valid edge + */ +typedef enum gptmr_synci_edge { + gptmr_synci_edge_none = 0, + gptmr_synci_edge_falling = GPTMR_CHANNEL_CR_SYNCIFEN_MASK, + gptmr_synci_edge_rising = GPTMR_CHANNEL_CR_SYNCIREN_MASK, + gptmr_synci_edge_both = gptmr_synci_edge_falling | gptmr_synci_edge_rising, +} gptmr_synci_edge_t; + +/** + * @brief GPTMR work mode + */ +typedef enum gptmr_work_mode { + gptmr_work_mode_no_capture = 0, + gptmr_work_mode_capture_at_rising_edge = 1, + gptmr_work_mode_capture_at_falling_edge = 2, + gptmr_work_mode_capture_at_both_edge = 3, + gptmr_work_mode_measure_width = 4, +} gptmr_work_mode_t; + +/** + * @brief GPTMR DMA request event + */ +typedef enum gptmr_dma_request_event { + gptmr_dma_request_on_reload = 0, + gptmr_dma_request_on_input_signal_toggle = 1, + gptmr_dma_request_on_cmp0 = 2, + gptmr_dma_request_on_cmp1 = 3, + gptmr_dma_request_disabled = 0xFF, +} gptmr_dma_request_event_t; + +/** + * @brief GPTMR counter type + */ +typedef enum gptmr_counter_type { + gptmr_counter_type_rising_edge, + gptmr_counter_type_falling_edge, + gptmr_counter_type_measured_period, + gptmr_counter_type_measured_duty_cycle, + gptmr_counter_type_normal, +} gptmr_counter_type_t; + +/** + * @brief GPTMR channel config + */ +typedef struct gptmr_channel_config { + gptmr_work_mode_t mode; + gptmr_dma_request_event_t dma_request_event; + gptmr_synci_edge_t synci_edge; + uint32_t cmp[GPTMR_CH_CMP_COUNT]; + uint32_t reload; + bool cmp_initial_polarity_high; + bool enable_cmp_output; + bool enable_sync_follow_previous_channel; + bool enable_software_sync; + bool debug_mode; +} gptmr_channel_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief gptmr channel enable + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @param [in] enable + * @arg true: enable + * @arg false: disable + */ +static inline void gptmr_channel_enable(GPTMR_Type *ptr, uint8_t ch_index, bool enable) +{ + ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR + & ~(GPTMR_CHANNEL_CR_CNTRST_MASK | GPTMR_CHANNEL_CR_CMPEN_MASK)) + | GPTMR_CHANNEL_CR_CMPEN_SET(enable); +} + +/** + * @brief gptmr channel reset counter + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + */ +static inline void gptmr_channel_reset_count(GPTMR_Type *ptr, uint8_t ch_index) +{ + ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTRST_MASK; + ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CNTRST_MASK; +} + +/** + * @brief gptmr channel update counter + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @param [in] value updated vaue + */ +static inline void gptmr_channel_update_count(GPTMR_Type *ptr, + uint8_t ch_index, + uint32_t value) +{ + ptr->CHANNEL[ch_index].CNTUPTVAL = GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(value); + ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTUPT_MASK; +} + +/** + * @brief gptmr channel slect synci valid edge + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @param [in] edge gptmr_synci_edge_t + */ +static inline void gptmr_channel_select_synci_valid_edge(GPTMR_Type *ptr, + uint8_t ch_index, + gptmr_synci_edge_t edge) +{ + ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR + & ~(GPTMR_CHANNEL_CR_SYNCIFEN_MASK + | GPTMR_CHANNEL_CR_SYNCIREN_MASK)) | edge; +} + +/** + * @brief gptmr channel enable dma request + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @param [in] enable + * @arg true: enable + * @arg false: disable + */ +static inline void gptmr_channel_enable_dma_request(GPTMR_Type *ptr, + uint8_t ch_index, + bool enable) +{ + ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR + & ~(GPTMR_CHANNEL_CR_DMAEN_MASK)) | GPTMR_CHANNEL_CR_DMAEN_SET(enable); +} + +/** + * @brief gptmr channel get counter value + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @param [in] capture gptmr_counter_type_t + */ +static inline uint32_t gptmr_channel_get_counter(GPTMR_Type *ptr, + uint8_t ch_index, + gptmr_counter_type_t capture) +{ + uint32_t value; + switch (capture) { + case gptmr_counter_type_rising_edge: + value = (ptr->CHANNEL[ch_index].CAPPOS & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT; + break; + case gptmr_counter_type_falling_edge: + value = (ptr->CHANNEL[ch_index].CAPNEG & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT; + break; + case gptmr_counter_type_measured_period: + value = (ptr->CHANNEL[ch_index].CAPPRD & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT; + break; + case gptmr_counter_type_measured_duty_cycle: + value = (ptr->CHANNEL[ch_index].CAPDTY & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT; + break; + default: + value = (ptr->CHANNEL[ch_index].CNT & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT; + break; + } + return value; +} + +/** + * @brief gptmr trigger channel software sync + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index_mask channel index mask + */ +static inline void gptmr_trigger_channel_software_sync(GPTMR_Type *ptr, uint32_t ch_index_mask) +{ + ptr->GCR = ch_index_mask; +} + +/** + * @brief gptmr enable irq + * + * @param [in] ptr GPTMR base address + * @param [in] irq_mask irq mask + */ +static inline void gptmr_enable_irq(GPTMR_Type *ptr, uint32_t irq_mask) +{ + ptr->IRQEN |= irq_mask; +} + +/** + * @brief gptmr disable irq + * + * @param [in] ptr GPTMR base address + * @param [in] irq_mask irq mask + */ +static inline void gptmr_disable_irq(GPTMR_Type *ptr, uint32_t irq_mask) +{ + ptr->IRQEN &= ~irq_mask; +} + +/** + * @brief gptmr check status + * + * @param [in] ptr GPTMR base address + * @param [in] mask channel flag mask + */ +static inline bool gptmr_check_status(GPTMR_Type *ptr, uint32_t mask) +{ + return (ptr->SR & mask) == mask; +} + +/** + * @brief gptmr clear status + * + * @param [in] ptr GPTMR base address + * @param [in] mask channel flag mask + */ +static inline void gptmr_clear_status(GPTMR_Type *ptr, uint32_t mask) +{ + ptr->SR |= mask; +} + +/** + * @brief gptmr get status + * + * @param [in] ptr GPTMR base address + * @retval SR register value + */ +static inline uint32_t gptmr_get_status(GPTMR_Type *ptr) +{ + return ptr->SR; +} + +/** + * @brief gptmr channel start counter + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + */ +static inline void gptmr_start_counter(GPTMR_Type *ptr, uint8_t ch_index) +{ + ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CEN_MASK; +} + +/** + * @brief gptmr channel stop counter + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + */ +static inline void gptmr_stop_counter(GPTMR_Type *ptr, uint8_t ch_index) +{ + ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CEN_MASK; +} + +/** + * @brief gptmr channel update comparator + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @param [in] cmp_index comparator index + * @param [in] cmp comparator value + */ +static inline void gptmr_update_cmp(GPTMR_Type *ptr, uint8_t ch_index, uint8_t cmp_index, uint32_t cmp) +{ + ptr->CHANNEL[ch_index].CMP[cmp_index] = GPTMR_CMP_CMP_SET(cmp); +} + +/** + * @brief gptmr channel update reload + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @param [in] reload reload value + */ +static inline void gptmr_channel_config_update_reload(GPTMR_Type *ptr, uint8_t ch_index, uint32_t reload) +{ + ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(reload); +} + +/** + * @brief gptmr channel config + * + * @param [in] ptr GPTMR base address + * @param [in] ch_index channel index + * @param [in] config gptmr_channel_config_t + * @param [in] enable + * @arg true: enable + * @arg false: disable + * + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr, + uint8_t ch_index, + gptmr_channel_config_t *config, + bool enable); + +/** + * @brief gptmr channel get default config + * + * @param [in] ptr GPTMR base address + * @param [out] config gptmr_channel_config_t + */ +void gptmr_channel_get_default_config(GPTMR_Type *ptr, gptmr_channel_config_t *config); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_GPTMR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h new file mode 100644 index 0000000000..f61aec179f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_HALL_DRV_H +#define HPM_HALL_DRV_H + +#include "hpm_common.h" +#include "hpm_hall_regs.h" + +/** + * @brief HALL driver APIs + * @defgroup hall_interface HALL driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +#define HALL_EVENT_WDOG_FLAG_MASK (1U << 31) /**< wdg flag */ +#define HALL_EVENT_PHUPT_FLAG_MASK (1U << 30) /**< phupt flag */ +#define HALL_EVENT_PHPRE_FLAG_MASK (1U << 29) /**< phpre flag */ +#define HALL_EVENT_PHDLYEN_FLAG_MASK (1U << 28) /**< phdly flag */ +#define HALL_EVENT_U_FLAG_MASK (1U << 23) /**< u flag */ +#define HALL_EVENT_V_FLAG_MASK (1U << 22) /**< v flag */ +#define HALL_EVENT_W_FLAG_MASK (1U << 21) /**< w flag */ +#define HALL_UVW_STAT_MASK (HALL_COUNT_U_USTAT_MASK | HALL_COUNT_U_VSTAT_MASK | HALL_COUNT_U_WSTAT_MASK) +#define HALL_U_STAT_MASK HALL_COUNT_U_USTAT_MASK +#define HALL_V_STAT_MASK HALL_COUNT_U_VSTAT_MASK +#define HALL_W_STAT_MASK HALL_COUNT_U_WSTAT_MASK + +/** + * @brief select delay start time + * + */ +typedef enum hall_count_delay_start { + hall_count_delay_start_after_uvw_toggle = 0, /**< start counting delay after u,v,w toggle */ + hall_count_delay_start_after_pre_trigger = 1, /**< start counting delay after pre-trigger */ +} hall_count_delay_start_t; + +/** + * @brief return value of motor movement direction + * + */ +typedef enum hall_rotate_direction { + hall_rotate_direction_forward = 0, /**< direction forward */ + hall_rotate_direction_reversed = 1 /**< direction reversed */ +} hall_rotate_direction_t; + +/** + * @brief counter type config + * + */ +typedef enum hall_counter_type { + hall_counter_type_w = 0, /**< type w */ + hall_counter_type_v = 1, /**< type v */ + hall_counter_type_u = 2, /**< type u */ + hall_counter_type_timer = 3, /**< type timer */ +} hall_counter_type_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable the watchdog + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] timeout watch dog timeout value , unit is HALL system clock + */ +static inline void hall_wdog_enable(HALL_Type *hall_x, uint32_t timeout) +{ + hall_x->WDGCFG = HALL_WDGCFG_WDGTO_SET(timeout) + | HALL_WDGCFG_WDGEN_SET(true); +} + +/** + * @brief disable the watchdog + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + */ +static inline void hall_wdog_disable(HALL_Type *hall_x) +{ + hall_x->WDGCFG = HALL_WDGCFG_WDGEN_SET(false); +} + +/** + * @brief delay a certain number of clock cycles after receiving a trigger event + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] delay_count delay clock cycles number + * @param[in] delay_start select the trigger moment + */ +static inline void hall_phase_config(HALL_Type *hall_x, uint32_t delay_count, + hall_count_delay_start_t delay_start) +{ + hall_x->PHCFG = HALL_PHCFG_DLYSEL_SET(delay_start) + | HALL_PHCFG_DLYCNT_SET(delay_count); +} + +/** + * @brief early trigger configuration + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] counter the clock cycle number + */ +static inline void hall_pre_uvw_transition_config(HALL_Type *hall_x, uint32_t counter) +{ + hall_x->UVWCFG = HALL_UVWCFG_PRECNT_SET(counter); +} + +/** + * @brief enable trigger event mask + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] event_mask event mask to be checked + * @arg @ref HALL_EVENT_WDOG_FLAG_MASK + * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK + * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK + * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK + * @arg @ref HALL_EVENT_U_FLAG_MASK + * @arg @ref HALL_EVENT_V_FLAG_MASK + * @arg @ref HALL_EVENT_W_FLAG_MASK + */ +static inline void hall_trigger_output_event_enable(HALL_Type *hall_x, + uint32_t event_mask) +{ + hall_x->TRGOEN = (hall_x->TRGOEN & ~event_mask) | event_mask; +} + +/** + * @brief disable trigger event mask + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] event_mask event mask to bo checked + * @arg @ref HALL_EVENT_WDOG_FLAG_MASK + * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK + * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK + * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK + * @arg @ref HALL_EVENT_U_FLAG_MASK + * @arg @ref HALL_EVENT_V_FLAG_MASK + * @arg @ref HALL_EVENT_W_FLAG_MASK + */ +static inline void hall_trigger_output_event_disable(HALL_Type *hall_x, + uint32_t event_mask) +{ + hall_x->TRGOEN &= ~event_mask; +} + +/** + * @brief enable hardware read event + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] event_mask read registers flag + * @arg @ref HALL_EVENT_WDOG_FLAG_MASK + * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK + * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK + * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK + * @arg @ref HALL_EVENT_U_FLAG_MASK + * @arg @ref HALL_EVENT_V_FLAG_MASK + * @arg @ref HALL_EVENT_W_FLAG_MASK + */ +static inline void hall_load_read_trigger_event_enable(HALL_Type *hall_x, + uint32_t event_mask) +{ + hall_x->READEN = (hall_x->READEN & ~event_mask) | event_mask; +} + +/** + * @brief disable hardware read event + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] event_mask read registers flag + * @arg @ref HALL_EVENT_WDOG_FLAG_MASK + * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK + * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK + * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK + * @arg @ref HALL_EVENT_U_FLAG_MASK + * @arg @ref HALL_EVENT_V_FLAG_MASK + * @arg @ref HALL_EVENT_W_FLAG_MASK + */ +static inline void hall_load_read_trigger_event_disable(HALL_Type *hall_x, + uint32_t event_mask) +{ + hall_x->READEN &= ~event_mask; +} + +/** + * @brief clear status register + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] mask hall event flag + * @arg @ref HALL_EVENT_WDOG_FLAG_MASK + * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK + * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK + * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK + * @arg @ref HALL_EVENT_U_FLAG_MASK + * @arg @ref HALL_EVENT_V_FLAG_MASK + * @arg @ref HALL_EVENT_W_FLAG_MASK + */ +static inline void hall_clear_status(HALL_Type *hall_x, uint32_t mask) +{ + hall_x->SR = mask; +} + +/** + * @brief get status register + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @retval uint32_t value: + * @retval HALL_EVENT_WDOG_FLAG_MASK if watchdog counter timeout + * @retval HALL_EVENT_PHUPT_FLAG_MASK if U/V/W Flip any input signal + * @retval HALL_EVENT_PHPRE_FLAG_MASK if early trigger events occur + * @retval HALL_EVENT_PHDLYEN_FLAG_MASK if time delay events occur + * @retval HALL_EVENT_U_FLAG_MASK if U signal flip + * @retval HALL_EVENT_V_FLAG_MASK if V signal flip + * @retval HALL_EVENT_W_FLAG_MASK if W signal flip + */ +static inline uint32_t hall_get_status(HALL_Type *hall_x) +{ + return hall_x->SR; +} + +/** + * @brief enable irq + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] mask hall event flag + * @arg @ref HALL_EVENT_WDOG_FLAG_MASK + * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK + * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK + * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK + * @arg @ref HALL_EVENT_U_FLAG_MASK + * @arg @ref HALL_EVENT_V_FLAG_MASK + * @arg @ref HALL_EVENT_W_FLAG_MASK + */ +static inline void hall_irq_enable(HALL_Type *hall_x, uint32_t mask) +{ + hall_x->IRQEN = (hall_x->IRQEN & ~mask) | mask; +} + +/** + * @brief disable irq + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] mask hall event flag + * @arg @ref HALL_EVENT_WDOG_FLAG_MASK + * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK + * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK + * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK + * @arg @ref HALL_EVENT_U_FLAG_MASK + * @arg @ref HALL_EVENT_V_FLAG_MASK + * @arg @ref HALL_EVENT_W_FLAG_MASK + */ +static inline void hall_irq_disable(HALL_Type *hall_x, uint32_t mask) +{ + hall_x->IRQEN &= ~mask; +} + +/** + * @brief enable dma request + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] mask hall event flag + * @arg @ref HALL_EVENT_WDOG_FLAG_MASK + * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK + * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK + * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK + * @arg @ref HALL_EVENT_U_FLAG_MASK + * @arg @ref HALL_EVENT_V_FLAG_MASK + * @arg @ref HALL_EVENT_W_FLAG_MASK + */ +static inline void hall_dma_request_enable(HALL_Type *hall_x, uint32_t mask) +{ + hall_x->DMAEN = (hall_x->DMAEN & ~mask) | mask; +} + +/** + * @brief disable dma request + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] mask hall event flag + * @arg @ref HALL_EVENT_WDOG_FLAG_MASK + * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK + * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK + * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK + * @arg @ref HALL_EVENT_U_FLAG_MASK + * @arg @ref HALL_EVENT_V_FLAG_MASK + * @arg @ref HALL_EVENT_W_FLAG_MASK + */ +static inline void hall_dma_request_disable(HALL_Type *hall_x, uint32_t mask) +{ + hall_x->DMAEN &= ~mask; +} + +/** + * @brief get rotate direction + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @retval hall_rotate_direction_t + */ +static inline hall_rotate_direction_t hall_get_rotate_direction(HALL_Type *hall_x) +{ + return (hall_rotate_direction_t)HALL_COUNT_U_DIR_GET(hall_x->COUNT[HALL_COUNT_CURRENT].U); +} + +/** + * @brief get three bits indicate UVW state + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @retval three bits UVW state + */ +static inline uint32_t hall_get_current_uvw_stat(HALL_Type *hall_x) +{ + return (hall_x->COUNT[HALL_COUNT_CURRENT].U & (HALL_UVW_STAT_MASK)) >> HALL_COUNT_U_WSTAT_SHIFT; +} + +/** + * @brief get current count U or V or W + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] type @ref hall_counter_type_t + * @retval count value + */ +static inline uint32_t hall_get_current_count(HALL_Type *hall_x, + hall_counter_type_t type) +{ + return *(&hall_x->COUNT[HALL_COUNT_CURRENT].W + type) & HALL_COUNT_U_UCNT_MASK; +} + +/** + * @brief get count when read event generated + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] type hall_counter_type_t + * @retval count value + */ +static inline uint32_t hall_get_count_on_read_event(HALL_Type *hall_x, + hall_counter_type_t type) +{ + return *(&hall_x->COUNT[HALL_COUNT_READ].W + type); +} + +/** + * @brief get count when snap0 event generated + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] type @ref hall_counter_type_t + * @retval count value + */ +static inline uint32_t hall_get_count_on_snap0_event(HALL_Type *hall_x, + hall_counter_type_t type) +{ + return *(&hall_x->COUNT[HALL_COUNT_SNAP0].W + type); +} + +/** + * @brief get count when snap1 event generated + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @param[in] type @ref hall_counter_type_t + * @retval count value + */ +static inline uint32_t hall_get_count_on_snap1_event(HALL_Type *hall_x, + hall_counter_type_t type) +{ + return *(&hall_x->COUNT[HALL_COUNT_SNAP1].W + type); +} + +/** + * @brief get the history count of u when u signal transition from 0 to 1 + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @retval count value + */ +static inline uint32_t hall_get_u_history0(HALL_Type *hall_x) +{ + return hall_x->HIS[0].HIS0; +} + +/** + * @brief get the history count of u when u signal transition from 1 to 0 + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @retval count value + */ +static inline uint32_t hall_get_u_history1(HALL_Type *hall_x) +{ + return hall_x->HIS[0].HIS1; +} + +/** + * @brief get the history count of v when v signal transition from 0 to 1 + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @retval count value + */ +static inline uint32_t hall_get_v_history0(HALL_Type *hall_x) +{ + return hall_x->HIS[1].HIS0; +} + +/** + * @brief get the history count of v when v signal transition from 1 to 0 + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @retval count value + */ +static inline uint32_t hall_get_v_history1(HALL_Type *hall_x) +{ + return hall_x->HIS[1].HIS1; +} + +/** + * @brief get the history count of w when w signal transition from 0 to 1 + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @retval count value + */ +static inline uint32_t hall_get_w_history0(HALL_Type *hall_x) +{ + return hall_x->HIS[2].HIS0; +} + +/** + * @brief get the history count of w when w signal transition from 1 to 0 + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + * @retval count value + */ +static inline uint32_t hall_get_w_history1(HALL_Type *hall_x) +{ + return hall_x->HIS[2].HIS1; +} + +/** + * @brief load ucnt, vcnt, wcnt and tmrcnt into their read registers. + * Hardware auto-clear; + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + */ +static inline void hall_load_count_to_read_registers(HALL_Type *hall_x) +{ + hall_x->CR |= HALL_CR_READ_MASK; +} + +/** + * @brief enable hall snap + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + */ +static inline void hall_snap_enable(HALL_Type *hall_x) +{ + hall_x->CR |= HALL_CR_SNAPEN_SET(1); +} + +/** + * @brief disable hall snap + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + */ +static inline void hall_snap_disable(HALL_Type *hall_x) +{ + hall_x->CR &= ~HALL_CR_SNAPEN_MASK; +} + +/** + * @brief reset all counter and related snapshots assert + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + */ +static inline void hall_counter_reset_assert(HALL_Type *hall_x) +{ + hall_x->CR |= HALL_CR_RSTCNT_MASK; +} + +/** + * @brief reset all counter and related snapshots release + * + * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) + */ +static inline void hall_counter_reset_release(HALL_Type *hall_x) +{ + hall_x->CR &= ~HALL_CR_RSTCNT_MASK; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_HALL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h new file mode 100644 index 0000000000..4bf0515246 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h @@ -0,0 +1,469 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_I2C_DRV_H +#define HPM_I2C_DRV_H +#include "hpm_common.h" +#include "hpm_i2c_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief I2C driver APIs + * @defgroup i2c_interface I2C driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief I2C status + */ +enum { + status_i2c_no_ack = MAKE_STATUS(status_group_i2c, 1), + status_i2c_invalid_data = MAKE_STATUS(status_group_i2c, 2), + status_i2c_no_addr_hit = MAKE_STATUS(status_group_i2c, 3), + status_i2c_transmit_not_completed = MAKE_STATUS(status_group_i2c, 4), + status_i2c_not_supported = MAKE_STATUS(status_group_i2c, 9), +}; + +/** + * @brief I2C CMD + */ +#define I2C_CMD_NO_ACTION (I2C_CMD_CMD_SET(0)) +#define I2C_CMD_ISSUE_DATA_TRANSMISSION (I2C_CMD_CMD_SET(1)) +#define I2C_CMD_ACK (I2C_CMD_CMD_SET(2)) +#define I2C_CMD_NACK (I2C_CMD_CMD_SET(3)) +#define I2C_CMD_CLEAR_FIFO (I2C_CMD_CMD_SET(4)) +#define I2C_CMD_RESET (I2C_CMD_CMD_SET(5)) + +/** + * @brief I2C data direction + */ +#define I2C_DIR_MASTER_WRITE (0U) +#define I2C_DIR_MASTER_READ (1U) +#define I2C_DIR_SLAVE_READ (0U) +#define I2C_DIR_SLAVE_WRITE (1U) + +/** + * @brief I2C events for interrupt enable and status check + */ +#define I2C_EVENT_TRANSACTION_COMPLETE I2C_INTEN_CMPL_MASK +#define I2C_EVENT_BYTE_RECEIVED I2C_INTEN_BYTERECV_MASK +#define I2C_EVENT_BYTE_TRANSMIT I2C_INTEN_BYTETRANS_MASK +#define I2C_EVENT_START_CONDITION I2C_INTEN_START_MASK +#define I2C_EVENT_STOP_CONDITION I2C_INTEN_STOP_MASK +#define I2C_EVENT_LOSS_ARBITRATION I2C_INTEN_ARBLOSE_MASK +#define I2C_EVENT_ADDRESS_HIT I2C_INTEN_ADDRHIT_MASK +#define I2C_EVENT_FIFO_HALF I2C_INTEN_FIFOHALF_MASK +#define I2C_EVENT_FIFO_FULL I2C_INTEN_FIFOFULL_MASK +#define I2C_EVENT_FIFO_EMPTY I2C_INTEN_FIFOEMPTY_MASK + +#define I2C_EVENT_ALL_MASK (I2C_INTEN_CMPL_MASK \ + | I2C_INTEN_BYTERECV_MASK \ + | I2C_INTEN_BYTETRANS_MASK \ + | I2C_INTEN_START_MASK \ + | I2C_INTEN_STOP_MASK \ + | I2C_INTEN_ARBLOSE_MASK \ + | I2C_INTEN_ADDRHIT_MASK \ + | I2C_INTEN_FIFOHALF_MASK \ + | I2C_INTEN_FIFOFULL_MASK \ + | I2C_INTEN_FIFOEMPTY_MASK) +/** + * @brief I2C status for status check only + */ +#define I2C_STATUS_LINE_SDA I2C_STATUS_LINESDA_MASK +#define I2C_STATUS_LINE_SCL I2C_STATUS_LINESCL_MASK +#define I2C_STATUS_GENERAL_CALL I2C_STATUS_GENCALL_MASK +#define I2C_STATUS_BUS_BUSY I2C_STATUS_BUSBUSY_MASK +#define I2C_STATUS_ACK I2C_STATUS_ACK_MASK + +/** + * @brief I2C config + */ +typedef struct { + bool is_10bit_addressing; + uint8_t i2c_mode; +} i2c_config_t; + +/** + * @brief I2C mode + */ +typedef enum i2c_mode { + i2c_mode_normal, + i2c_mode_fast, + i2c_mode_fast_plus, +} i2c_mode_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief respond NACK + * + * @param [in] ptr I2C base address + */ +static inline void i2c_respond_Nack(I2C_Type *ptr) +{ + ptr->CMD = I2C_CMD_NACK; +} + +/** + * @brief respond ACK + * + * @param [in] ptr I2C base address + */ +static inline void i2c_respond_ack(I2C_Type *ptr) +{ + ptr->CMD = I2C_CMD_ACK; +} + +/** + * @brief clear I2C fifo + * + * @param [in] ptr I2C base address + */ +static inline void i2c_clear_fifo(I2C_Type *ptr) +{ + ptr->CMD = I2C_CMD_CLEAR_FIFO; +} + +/** + * @brief check data count + * + * @details It indicates number of bytes to transfer + * + * @param [in] ptr I2C base address + * @retval data count value in byte + */ +static inline uint8_t i2c_get_data_count(I2C_Type *ptr) +{ + return I2C_CTRL_DATACNT_GET(ptr->CTRL); +} + +/** + * @brief check if I2C FIFO is full + * + * @param [in] ptr I2C base address + * @retval true if FIFO is full + */ +static inline bool i2c_fifo_is_full(I2C_Type *ptr) +{ + return ptr->STATUS & I2C_STATUS_FIFOFULL_MASK; +} + +/** + * @brief check if I2C FIFO is half + * + * @note When I2C is transmitting data, it indicates if fifo is half-empty; + * @note When I2C is receiving data, it indicates if fifo is half full. + * + * @param [in] ptr I2C base address + * @retval true if FIFO is half empty or full + */ +static inline bool i2c_fifo_is_half(I2C_Type *ptr) +{ + return ptr->STATUS & I2C_STATUS_FIFOHALF_MASK; +} + +/** + * @brief check if I2C FIFO is empty + * + * @param [in] ptr I2C base address + * @retval true if FIFO is empty + */ +static inline bool i2c_fifo_is_empty(I2C_Type *ptr) +{ + return ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK; +} + +/** + * @brief check if I2C is writing + * + * @param [in] ptr I2C base address + * @retval bool value + * @arg true: receive data if master mode, send data in slave mode + * @arg false: send data if master mode, reveive data in slave mode + * + */ +static inline bool i2c_is_writing(I2C_Type *ptr) +{ + return (ptr->CTRL & I2C_CTRL_DIR_MASK); +} + +/** + * @brief check if I2C is reading + * + * @param [in] ptr I2C base address + * @retval bool value + * @arg true: send data if master mode, receive data in slave mode + * @arg false: receive data if master mode, send data in slave mode + * + */ +static inline bool i2c_is_reading(I2C_Type *ptr) +{ + return !i2c_is_writing(ptr); +} + +/** + * @brief clear status + * + * @details Clear status based on mask + * + * @param [in] ptr I2C base address + * @param [in] mask mask to clear status + */ +static inline void i2c_clear_status(I2C_Type *ptr, uint32_t mask) +{ + ptr->STATUS |= (mask & I2C_EVENT_ALL_MASK); +} + +/** + * @brief get status + * + * @details Get current I2C status bits + * + * @param [in] ptr I2C base address + * @retval current I2C status + */ +static inline uint32_t i2c_get_status(I2C_Type *ptr) +{ + return ptr->STATUS; +} + +/** + * @brief disable interrupts + * + * @details Disable interrupts based on given mask + * + * @param [in] ptr I2C base address + * @param [in] mask interrupt mask to be disabled + */ +static inline void i2c_disable_irq(I2C_Type *ptr, uint32_t mask) +{ + ptr->INTEN &= ~mask; +} + +/** + * @brief enable interrupts + * + * @details Enable interrupts based on given mask + * + * @param [in] ptr I2C base address + * @param [in] mask interrupt mask to be enabled + */ +static inline void i2c_enable_irq(I2C_Type *ptr, uint32_t mask) +{ + ptr->INTEN |= mask; +} + +/** + * @brief enable 10 bit address mode + * + * @details enable 10 bit address mode, if not, address is 7 bit mode + * + * @param [in] ptr I2C base address + * @param [in] enable + * @arg true: enable 10 bit address mode + * @arg false: enable 7 bit address mode + */ +static inline void i2c_enable_10bit_address_mode(I2C_Type *ptr, bool enable) +{ + ptr->SETUP |= I2C_SETUP_ADDRESSING_SET(enable); +} + +/** + * @brief I2C master initialization + * + * @details Initialized I2C controller working at master mode + * + * @param [in] ptr I2C base address + * @param [in] src_clk_in_hz I2C controller source clock source frequency in Hz + * @param [in] config i2c_config_t + * @retval hpm_stat_t: status_success if initialization is completed without any error + */ +hpm_stat_t i2c_init_master(I2C_Type *ptr, + uint32_t src_clk_in_hz, + i2c_config_t *config); + +/** + * @brief I2C master write data to specific address of certain slave device + * + * @details Write to certain I2C device at specific address within that device + * + * @param [in] ptr I2C base address + * @param [in] device_address I2C slave address + * @param [in] addr address in that I2C device + * @param [in] addr_size_in_byte I2C address in byte + * @param [in] buf pointer of the data to be sent + * @param [in] size_in_byte size of data to be sent in bytes + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t i2c_master_address_write(I2C_Type *ptr, + const uint16_t device_address, + uint8_t *addr, + uint8_t addr_size_in_byte, + uint8_t *buf, + const uint32_t size_in_byte); + +/** + * @brief I2C master read data from specific address of certain slave device + * + * @details Read fram certain I2C device at specific address within that device + * + * @param [in] ptr I2C base address + * @param [in] device_address I2C slave address + * @param [in] addr address in that I2C device + * @param [in] addr_size_in_byte I2C address in byte + * @param [out] buf pointer of the buffer to receive data read from the device + * @param [in] size size of data to be read in bytes + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t i2c_master_address_read(I2C_Type *ptr, + const uint16_t device_address, + uint8_t *addr, + uint8_t addr_size_in_byte, + uint8_t *buf, + const uint32_t size); + +/** + * @brief I2C master write data to certain slave device + * + * @details Write data to I2C device + * + * @param [in] ptr I2C base address + * @param [in] device_address I2C slave address + * @param [in] buf pointer of the data to be sent + * @param [in] size size of data to be sent in bytes + * @retval hpm_stat_t: status_success if writing is completed without any error + */ +hpm_stat_t i2c_master_write(I2C_Type *ptr, + const uint16_t device_address, + uint8_t *buf, + const uint32_t size); + +/** + * @brief I2C master start write data by DMA + * + * @details Write data to I2C device by DMA + * + * @param [in] i2c_ptr I2C base address + * @param [in] device_address I2C slave address + * @param [in] size size of data to be sent in bytes + */ +void i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); + +/** + * @brief I2C master start read data by DMA + * + * @details Read data to I2C device by DMA + * + * @param [in] i2c_ptr I2C base address + * @param [in] device_address I2C slave address + * @param [in] size size of data to be read in bytes + */ +void i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); + +/** + * @brief I2C master read data from certain slave device + * + * @details Read data from I2C device + * + * @param [in] ptr I2C base address + * @param [in] device_address I2C slave address + * @param [out] buf pointer of the buffer to store data read from device + * @param [in] size size of data to be read in bytes + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t i2c_master_read(I2C_Type *ptr, + const uint16_t device_address, + uint8_t *buf, + const uint32_t size); +/** + * @brief I2C slave initialization + * + * @details Initialize I2C controller working at slave mode + * + * @param [in] ptr I2C base address + * @param [in] src_clk_in_hz I2C controller source clock source frequency in Hz + * @param [in] config I2C configuration structure + * @param [in] slave_address I2C address to be used at slave mode + * @retval hpm_stat_t: status_success if initialization is completed without any error + */ +hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz, + i2c_config_t *config, const uint16_t slave_address); + +/** + * @brief I2C slave read data + * + * @details Read data at slave mode + * + * @param [in] ptr I2C base address + * @param [in] buf pointer of the buffer to store data read from device + * @param [in] size size of data to be read in bytes + * @retval hpm_stat_t: status_success if reading is completed without any error + */ +hpm_stat_t i2c_slave_read(I2C_Type *ptr, uint8_t *buf, const uint32_t size); + +/** + * @brief I2C slave write data + * + * @details Write data at slave mode. + * + * @param [in] ptr I2C base address + * @param [in] buf pointer of the buffer to store data sent from device + * @param [in] size size of data to be sent in bytes + * @retval hpm_stat_t status_success if writing is completed without any error + */ +hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size); + +/** + * @brief reset I2C + * + * @param [in] ptr I2C base address + */ +void i2c_reset(I2C_Type *ptr); + +/** + * @brief Enable i2c DMA + * + * @param [in] ptr I2C base address + */ +static inline void i2c_dma_enable(I2C_Type *ptr) +{ + ptr->SETUP |= I2C_SETUP_DMAEN_MASK; +} + +/** + * @brief Disable i2c DMA + * + * @param [in] ptr I2C base address + */ +static inline void i2c_dma_disable(I2C_Type *ptr) +{ + ptr->SETUP &= ~I2C_SETUP_DMAEN_MASK; +} + +/** + * @brief I2C slave dma transfer data + * + * @note The direction of data transmission depends on Master setting + * + * @param [in] ptr I2C base address + * @param [in] size size of data in bytes + */ +void i2c_slave_dma_transfer(I2C_Type *ptr, const uint32_t size); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_I2C_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h new file mode 100644 index 0000000000..91e99f6315 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_I2S_COMMON_H +#define HPM_I2S_COMMON_H + +/** + * @brief I2S common driver APIs + * @defgroup i2s_common_interface I2S common driver APIs + * @ingroup io_interfaces + * @{ + */ + +#define I2S_PROTOCOL_I2S_PHILIPS (0U) +#define I2S_PROTOCOL_MSB_JUSTIFIED (1U) +#define I2S_PROTOCOL_LEFT_JUSTIFIED (1U) +#define I2S_PROTOCOL_LSB_JUSTIFIED (2U) +#define I2S_PROTOCOL_RIGHT_JUSTIFIED (2U) +#define I2S_PROTOCOL_PCM (3U) + +#define I2S_AUDIO_DEPTH_16_BITS (0U) +#define I2S_AUDIO_DEPTH_24_BITS (1U) +#define I2S_AUDIO_DEPTH_32_BITS (2U) +#define I2S_AUDIO_DEPTH_IS_NOT_VALID(x) ((x) > I2S_AUDIO_DEPTH_32_BITS) + +#define I2S_CHANNEL_LENGTH_16_BITS (0U) +#define I2S_CHANNEL_LENGTH_32_BITS (1U) + +/** + * @brief I2S stereo/mono channel + */ +enum { + i2s_mono_left = 0, + i2s_mono_right = 1, + i2s_stereo = 2, +}; + +/** + * @} + */ + +#endif /* HPM_I2S_COMMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h new file mode 100644 index 0000000000..3e5ab32d89 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h @@ -0,0 +1,510 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_I2S_DRV_H +#define HPM_I2S_DRV_H +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_i2s_regs.h" +#include "hpm_i2s_common.h" + +/** + * @brief I2S driver APIs + * @defgroup i2s_interface I2S driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief I2S IRQ mask + */ +#define I2S_IRQ_TX_FIFO_EMPTY I2S_CTRL_TXDNIE_MASK +#define I2S_IRQ_RX_FIFO_DATA_AVAILABLE I2S_CTRL_RXDAIE_MASK +#define I2S_IRQ_ERROR I2S_CTRL_ERRIE_MASK + +/** + * @brief I2S data line + */ +#define I2S_DATA_LINE_0 (0U) +#define I2S_DATA_LINE_1 (1U) +#define I2S_DATA_LINE_2 (2U) +#define I2S_DATA_LINE_3 (3U) +#define I2S_DATA_LINE_MAX I2S_DATA_LINE_3 + +/* i2s channel slot mask */ +#define I2S_CHANNEL_SLOT_MASK(x) ((1U << (x)) & I2S_RXDSLOT_EN_MASK) + +/** + * @brief I2S config + */ +typedef struct i2s_config { + bool invert_mclk_out; + bool invert_mclk_in; + bool use_external_mclk; + bool invert_bclk_out; + bool invert_bclk_in; + bool use_external_bclk; + bool invert_fclk_out; + bool invert_fclk_in; + bool use_external_fclk; + bool enable_mclk_out; + bool frame_start_at_rising_edge; + uint16_t fifo_threshold; +} i2s_config_t; + +/** + * @brief I2S transfer config + */ +typedef struct i2x_transfer_config { + uint32_t sample_rate; + bool enable_tdm_mode; + uint8_t channel_num_per_frame; + uint8_t channel_length; /* 16-bit or 32-bit */ + uint8_t audio_depth; /* 8-bit, 24-bit, 32-bit */ + bool master_mode; + uint8_t protocol; + uint8_t data_line; + uint32_t channel_slot_mask; +} i2s_transfer_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable TDM + * + * @param [in] ptr I2S base address + */ +static inline void i2s_enable_tdm(I2S_Type *ptr) +{ + ptr->CFGR |= I2S_CFGR_TDM_EN_MASK; +} + +/** + * @brief disable TDM + * + * @param [in] ptr I2S base address + */ +static inline void i2s_disable_tdm(I2S_Type *ptr) +{ + ptr->CFGR &= ~I2S_CFGR_TDM_EN_MASK; +} + +/** + * @brief update rx fifo threshold + * + * @param [in] ptr I2S base address + * @param [in] threshold fifo threshold value + */ +static inline void i2s_update_rx_fifo_threshold(I2S_Type *ptr, uint8_t threshold) +{ + ptr->FIFO_THRESH = (ptr->FIFO_THRESH & ~I2S_FIFO_THRESH_RX_MASK) + | I2S_FIFO_THRESH_RX_SET(threshold); +} + +/** + * @brief update tx fifo threshold + * + * @param [in] ptr I2S base address + * @param [in] threshold fifo threshold value + */ +static inline void i2s_update_tx_fifo_threshold(I2S_Type *ptr, uint8_t threshold) +{ + ptr->FIFO_THRESH = (ptr->FIFO_THRESH & ~I2S_FIFO_THRESH_TX_MASK) + | I2S_FIFO_THRESH_TX_SET(threshold); +} + +/** + * @brief open BCLK + * + * @param [in] ptr I2S base address + */ +static inline void i2s_ungate_bclk(I2S_Type *ptr) +{ + ptr->CFGR &= ~I2S_CFGR_BCLK_GATEOFF_MASK; +} + +/** + * @brief gete off BCLK + * + * @param [in] ptr I2S base address + */ +static inline void i2s_gate_bclk(I2S_Type *ptr) +{ + ptr->CFGR |= I2S_CFGR_BCLK_GATEOFF_MASK; +} + +/** + * @brief open MCLK + * + * @param [in] ptr I2S base address + */ +static inline void i2s_ungate_mclk(I2S_Type *ptr) +{ + ptr->MISC_CFGR &= ~I2S_MISC_CFGR_MCLK_GATEOFF_MASK; +} + +/** + * @brief gate off MCLK + * + * @param [in] ptr I2S base address + */ +static inline void i2s_gate_mclk(I2S_Type *ptr) +{ + ptr->MISC_CFGR |= I2S_MISC_CFGR_MCLK_GATEOFF_MASK; +} + +/** + * @brief enable TX dma request + * + * @param [in] ptr I2S base address + */ +static inline void i2s_enable_tx_dma_request(I2S_Type *ptr) +{ + ptr->CTRL |=I2S_CTRL_TX_DMA_EN_MASK; +} + +/** + * @brief disable TX dma request + * + * @param [in] ptr I2S base address + */ +static inline void i2s_disable_tx_dma_request(I2S_Type *ptr) +{ + ptr->CTRL &= ~I2S_CTRL_TX_DMA_EN_MASK; +} + +/** + * @brief enable RX dma request + * + * @param [in] ptr I2S base address + */ +static inline void i2s_enable_rx_dma_request(I2S_Type *ptr) +{ + ptr->CTRL |=I2S_CTRL_RX_DMA_EN_MASK; +} + +/** + * @brief disable RX dma request + * + * @param [in] ptr I2S base address + */ +static inline void i2s_disable_rx_dma_request(I2S_Type *ptr) +{ + ptr->CTRL &= ~I2S_CTRL_RX_DMA_EN_MASK; +} + +/** + * @brief enable IRQ + * + * @param [in] ptr I2S base address + * @param [in] mask irq bit mask + */ +static inline void i2s_enable_irq(I2S_Type *ptr, uint32_t mask) +{ + ptr->CTRL |= mask; +} + +/** + * @brief disable IRQ + * + * @param [in] ptr I2S base address + * @param [in] mask irq bit mask + */ +static inline void i2s_disable_irq(I2S_Type *ptr, uint32_t mask) +{ + ptr->CTRL &= ~mask; +} + +/** + * @brief I2S enable + * + * @param [in] ptr I2S base address + */ +static inline void i2s_enable(I2S_Type *ptr) +{ + ptr->CTRL |= ~I2S_CTRL_I2S_EN_MASK; +} + +/** + * @brief I2S disable + * + * @param [in] ptr I2S base address + */ +static inline void i2s_disable(I2S_Type *ptr) +{ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; +} + +/** + * @brief I2S enable rx function + * + * @param [in] ptr I2S base address + * @param [in] rx_mask rx data line mask + */ +static inline void i2s_enable_rx(I2S_Type *ptr, uint8_t rx_mask) +{ + ptr->CTRL |= I2S_CTRL_RX_EN_SET(rx_mask); +} + +/** + * @brief I2S disable rx function + * + * @param [in] ptr I2S base address + * @param [in] rx_mask rx data line mask + */ +static inline void i2s_disable_rx(I2S_Type *ptr, uint8_t rx_mask) +{ + ptr->CTRL &= ~I2S_CTRL_RX_EN_SET(rx_mask); +} + +/** + * @brief I2S enable tx function + * + * @param [in] ptr I2S base address + * @param [in] tx_mask tx data line mask + */ +static inline void i2s_enable_tx(I2S_Type *ptr, uint8_t tx_mask) +{ + ptr->CTRL |= I2S_CTRL_TX_EN_SET(tx_mask); +} + +/** + * @brief I2S disbale tx function + * + * @param [in] ptr I2S base address + * @param [in] tx_mask tx data line mask + */ +static inline void i2s_disable_tx(I2S_Type *ptr, uint8_t tx_mask) +{ + ptr->CTRL &= ~I2S_CTRL_TX_EN_SET(tx_mask); +} + +/** + * @brief I2S clear tx fifo + * + * @param [in] ptr I2S base address + */ +static inline void i2s_clear_tx_fifo(I2S_Type *ptr) +{ + ptr->CTRL |= I2S_CTRL_TXFIFOCLR_MASK; + while (ptr->CTRL & I2S_CTRL_TXFIFOCLR_MASK) {} +} + +/** + * @brief I2S clear rx fifo + * + * @param [in] ptr I2S base address + */ +static inline void i2s_clear_rx_fifo(I2S_Type *ptr) +{ + ptr->CTRL |= I2S_CTRL_RXFIFOCLR_MASK; + while (ptr->CTRL & I2S_CTRL_RXFIFOCLR_MASK) {} +} + +/** + * @brief I2S reset clock generator + * + * @param [in] ptr I2S base address + */ +static inline void i2s_reset_clock_gen(I2S_Type *ptr) +{ + ptr->CTRL |= I2S_CTRL_SFTRST_CLKGEN_MASK; + ptr->CTRL &= ~I2S_CTRL_SFTRST_CLKGEN_MASK; +} + +/** + * @brief I2S reset tx function + * + * @param [in] ptr I2S base address + */ +static inline void i2s_reset_tx(I2S_Type *ptr) +{ + ptr->CTRL |= I2S_CTRL_SFTRST_TX_MASK; + ptr->CTRL &= ~I2S_CTRL_SFTRST_TX_MASK; +} + +/** + * @brief I2S reset rx function + * + * @param [in] ptr I2S base address + */ +static inline void i2s_reset_rx(I2S_Type *ptr) +{ + ptr->CTRL |= I2S_CTRL_SFTRST_RX_MASK; + ptr->CTRL &= ~I2S_CTRL_SFTRST_RX_MASK; +} + +/** + * @brief I2S get tx fifo level + * + * @param [in] ptr I2S base address + * + * @retval I2S tx fifo level + */ +static inline uint32_t i2s_get_tx_fifo_level(I2S_Type *ptr) +{ + return ptr->TFIFO_FILLINGS; +} + +/** + * @brief I2S get data line tx fifo level + * + * @param [in] ptr I2S base address + * @param [in] line I2S data line + * + * @retval I2S data line tx fifo level + */ +static inline uint32_t i2s_get_tx_line_fifo_level(I2S_Type *ptr, uint8_t line) +{ + return i2s_get_tx_fifo_level(ptr) & (0xFF << (line << 3)); +} + +/** + * @brief I2S get rx fifo level + * + * @param [in] ptr I2S base address + * + * @retval I2S rx fifo level + */ +static inline uint32_t i2s_get_rx_fifo_level(I2S_Type *ptr) +{ + return ptr->RFIFO_FILLINGS; +} + +/** + * @brief I2S get data line rx fifo level + * + * @param [in] ptr I2S base address + * @param [in] line I2S data line + * + * @retval I2S data line rx fifo level + */ +static inline uint32_t i2s_get_rx_line_fifo_level(I2S_Type *ptr, uint8_t line) +{ + return i2s_get_rx_fifo_level(ptr) & (0xFF << (line << 3)); +} + +/** + * @brief I2S get IRQ status + * + * @param [in] ptr I2S base address + * + * @retval I2S STA register value + */ +static inline uint32_t i2s_get_irq_status(I2S_Type *ptr) +{ + return ptr->STA; +} + +/** + * @brief I2S stop transfer + * + * @param [in] ptr I2S base address + */ +static inline void i2s_stop_transfer(I2S_Type *ptr) +{ + i2s_disable(ptr); +} + +/** + * @brief I2S config tx + * + * @param [in] ptr I2S base address + * @param [in] mclk_in_hz mclk frequency in Hz + * @param [in] config i2s_transfer_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); + +/** + * @brief I2S config rx + * + * @param [in] ptr I2S base address + * @param [in] mclk_in_hz mclk frequency in Hz + * @param [in] config i2s_transfer_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); + +/** + * @brief I2S config transfer + * + * @param [in] ptr I2S base address + * @param [in] mclk_in_hz mclk frequency in Hz + * @param [in] config i2s_transfer_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); + +/** + * @brief I2S send data + * + * @param [in] ptr I2S base address + * @param [in] tx_line_index data line + * @param [in] src source data buff + * @param [in] size data size + */ +uint32_t i2s_send_data(I2S_Type *ptr, uint8_t tx_line_index, uint32_t *src, uint32_t size); + +/** + * @brief I2S receive data + * + * @param [in] ptr I2S base address + * @param [in] rx_line_index data line + * @param [out] dst target data buff + * @param [in] size data size + */ +uint32_t i2s_receive_data(I2S_Type *ptr, uint8_t rx_line_index, uint32_t *dst, uint32_t size); + +/** + * @brief I2S get default config + * + * @param [in] ptr I2S base address + * @param [out] config i2s_config_t + */ +void i2s_get_default_config(I2S_Type *ptr, i2s_config_t *config); + +/** + * @brief I2S initialization + * + * @param [in] ptr I2S base address + * @param [in] config i2s_config_t + */ +void i2s_init(I2S_Type *ptr, i2s_config_t *config); + +/** + * @brief I2S get default transfer config for pdm + * + * @param [out] transfer i2s_transfer_config_t + */ +void i2s_get_default_transfer_config_for_pdm(i2s_transfer_config_t *transfer); + +/** + * @brief I2S get default transfer config for dao + * + * @param [out] transfer i2s_transfer_config_t + */ +void i2s_get_default_transfer_config_for_dao(i2s_transfer_config_t *transfer); + +/** + * @brief I2S get default transfer config + * + * @param [out] transfer i2s_transfer_config_t + */ +void i2s_get_default_transfer_config(i2s_transfer_config_t *transfer); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_I2S_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h new file mode 100644 index 0000000000..b32e4b3547 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_JPEG_DRV_H +#define HPM_JPEG_DRV_H + +#include "hpm_common.h" +#include "hpm_jpeg_regs.h" + +/** + * @brief Jpeg driver APIs + * @defgroup Jpeg_interface JPEG driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Define events of the jpeg module + */ +#define JPEG_EVENT_BUSY JPEG_STAT_BUSY_MASK +#define JPEG_EVENT_OUT_DMA_FINISH JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK +#define JPEG_EVENT_IN_DMA_FINISH JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK +#define JPEG_EVENT_ERROR (JPEG_STAT_RESTART_MARKER_ERROR_MASK | (0xF << 7)) + +/** + * @brief byte order in a word + */ +#define JPEG_BYTE_ORDER_3210 (0U) /**< CAN Receive event *//* no order change, {A3, A2, A1, A0} */ +#define JPEG_BYTE_ORDER_2301 (1U) /**< order change, {A2, A3, A0, A1} */ +#define JPEG_BYTE_ORDER_1032 (2U) /**< order change, {A1, A0, A2, A3} */ +#define JPEG_BYTE_ORDER_0123 (3U) /**< order change, {A0, A1, A2, A3} */ + +/** + * @brief jpeg pixel conversion format + */ +#define JPEG_PIXEL_FORMAT_AS_ORIGIN (0U) +#define JPEG_PIXEL_FORMAT_ARGB8888 (1U) +#define JPEG_PIXEL_FORMAT_RGB565 (2U) +#define JPEG_PIXEL_FORMAT_YUV422H1P (3U) + +/** + * @brief jpeg data format definition + */ +#define JPEG_SUPPORTED_FORMAT_420 (0U) /**< hy=2, vy=2, hc=1, vc=1 */ +#define JPEG_SUPPORTED_FORMAT_422H (1U) /**< hy=2, vy=1, hc=1, vc=1 */ +#define JPEG_SUPPORTED_FORMAT_422V (2U) /**< hy=1, vy=2, hc=1, vc=1 */ +#define JPEG_SUPPORTED_FORMAT_444 (3U) /**< hy=1, vy=1, hc=1, vc=1 */ +#define JPEG_SUPPORTED_FORMAT_400 (4U) /**< hy=2, vy=2, hc=0, vc=0 */ + +/** + * @brief data format definition + */ +typedef struct { + uint8_t hy:2; /**< bit: 1-0 --> horizontal y component */ + uint8_t vy:2; /**< bit: 3-2 --> Vertical y component */ + uint8_t hc:2; /**< bit: bit: 5-4 --> horizontal c component */ + uint8_t vc:2; /**< bit: 7-6 --> Vertical c component */ +} jpeg_sampling_t; + +/** + * @brief jpeg encoding and decoding configuration parameters + * @arg bit: 31-27 --> name + * @arg bit: 26-23 --> WIDTH IN BYTE + * @arg bit: 22-3 --> ELEMENT COUNT + * @arg bit: 2-0 --> TYPE + */ +typedef enum jpeg_table { + jpeg_table_qmem = 0x201002, /**< definition Decoder and Encoder Q. values */ + jpeg_table_huffenc = 0x201803, /**< definition Huffman Encoder table */ + jpeg_table_huffmin = 0x400104, /**< definition Huffman min values */ + jpeg_table_huffbase = 0x200405, /**< definition Huffman BASE mem values */ + jpeg_table_huffsymb = 0x101506, /**< definition Huffman SYMB mem values */ +} jpeg_table_t; + +/** + * @brief jpeg encoding and decoding configuration parameters + */ +typedef struct { + uint8_t jpeg_format; /**< supported jpeg format */ + uint8_t in_pixel_format; /**< input pixel format */ + uint8_t out_pixel_format; /**< output pixel format */ + uint8_t byte_order; /**< byte order */ + bool enable_csc; /**< enable color space covertion */ + bool enable_ycbcr; /**< enable YCbCr or YUV */ + uint16_t width_in_pixel; /**< Image width register*/ + uint16_t height_in_pixel; /**< Image height register*/ + uint32_t in_buffer; /**< input buffer */ + uint32_t out_buffer; /**< output buffer */ +} jpeg_job_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief clear jpeg cfg Register + * + * @param [in] ptr JPEG base address, HPM_JPEG + */ +static inline void jpeg_clear_cfg(JPEG_Type *ptr) +{ + ptr->CFG = 0; +} + +/** + * @brief jpeg function disable + * + * @param [in] ptr JPEG base address, HPM_JPEG + */ +static inline void jpeg_disable(JPEG_Type *ptr) +{ + ptr->CFG &= ~JPEG_CFG_JPEG_EN_MASK; +} + +/** + * @brief jpeg function enable + * + * @param [in] ptr JPEG base address, HPM_JPEG + */ +static inline void jpeg_enable(JPEG_Type *ptr) +{ + ptr->CFG |= JPEG_CFG_JPEG_EN_MASK; +} + +/** + * @brief stop a encoder/decoder conversion + * + * @param [in] ptr JPEG base address, HPM_JPEG + */ +static inline void jpeg_stop(JPEG_Type *ptr) +{ + ptr->CFG &= ~JPEG_CFG_START_MASK; +} + +/** + * @brief start a new encoder/decoder conversion + * + * @param [in] ptr JPEG base address, HPM_JPEG + */ +static inline void jpeg_start(JPEG_Type *ptr) +{ + ptr->CFG |= JPEG_CFG_START_MASK; +} + +/** + * @brief obtain jpeg Status Register + * + * @param [in] ptr JPEG base address, HPM_JPEG + * @retval jpeg register's status + */ +static inline uint32_t jpeg_get_status(JPEG_Type *ptr) +{ + return ptr->STAT; +} + +/** + * @brief clear jpeg Status Register + * + * @param [in] ptr JPEG base address, HPM_JPEG + * @param [in] mask + * @arg JPEG_EVENT_BUSY: the module is busy doing conversion and data transfer + * @arg JPEG_EVENT_OUT_DMA_FINISH: OutDMA process done + * @arg JPEG_EVENT_IN_DMA_FINISH: InDMA process done + * @arg JPEG_EVENT_ERROR: the axi err + * + */ +static inline void jpeg_clear_status(JPEG_Type *ptr, uint32_t mask) +{ + ptr->STAT |= mask; +} + +/** + * @brief Out DMA Bytes Counter + * + * @param [in] ptr JPEG base address, HPM_JPEG + * @retval The out DMA counter + */ +static inline uint32_t jpeg_get_encoded_length(JPEG_Type *ptr) +{ + return JPEG_OUTDMACNT_VAL_GET(ptr->OUTDMACNT); +} + +/** + * @brief jpeg Software Reset + * + * @param [in] ptr JPEG base address, HPM_JPEG + */ +static inline void jpeg_software_reset(JPEG_Type *ptr) +{ + ptr->CFG |= JPEG_CFG_JPEG_SFTRST_MASK; + ptr->CFG &= ~JPEG_CFG_JPEG_SFTRST_MASK; +} + +/** + * @brief stop a encoder/decoder conversion and Software Reset + * + * @param [in] ptr JPEG base address, HPM_JPEG + */ +void jpeg_reset(JPEG_Type *ptr); + +/** + * @brief jpeg enable interrupt + * + * @param [in] ptr JPEG base address, HPM_JPEG + * @param [in] mask + * @arg JPEG_EVENT_IN_DMA_FINISH: In DMA Done enable + * @arg JPEG_EVENT_OUT_DMA_FINISH: interrupt enable for all interrupt sources of In DMA module + * @arg JPEG_EVENT_ERROR: The jpg endec restart error interrupt enable + * + */ +void jpeg_enable_irq(JPEG_Type *ptr, uint32_t mask); + +/** + * @brief jpeg disable interrupt + * + * @param [in] ptr JPEG base address, HPM_JPEG + * @param [in] mask + * @arg JPEG_EVENT_IN_DMA_FINISH: In DMA Done disable + * @arg JPEG_EVENT_OUT_DMA_FINISH: interrupt disable for all interrupt sources of In DMA module + * @arg JPEG_EVENT_ERROR: The jpg endec restart error interrupt disable + * + */ +void jpeg_disable_irq(JPEG_Type *ptr, uint32_t mask); + +/** + * @brief stop a encoder/decoder conversion and Software Reset + * + * @param [in] ptr JPEG base address, HPM_JPEG + */ +void jpeg_init(JPEG_Type *ptr); + +/** + * @brief fill tables for jpeg controller + * + * @param [in] ptr JPEG base address, HPM_JPEG + * @param [in] table + * @arg jpeg_table_qmem: file describe for Decoder and Encoder Q. values + * @arg jpeg_table_huffenc: file describe for Huffman Encoder table + * @arg jpeg_table_huffmin: file describe for Huffman min values + * @arg jpeg_table_huffbase: file describe for Huffman BASE mem values + * @arg jpeg_table_huffsymb: file describe for Huffman SYMB mem values + * @param [in] data + * @arg huffenc: data for Huffman Encoder table + * @arg huffmin: data for Huffman min values + * @arg huffbase: data for Huffman BASE mem values + * @arg huffsymb: data for Huffman SYMB mem values + * @arg qetable: data for Encoder Q. values + * @arg qdtable: data for Decoder Q. values + * @param [in] count data length + * @retval fill tables's status + * + */ +hpm_stat_t jpeg_fill_table(JPEG_Type *ptr, jpeg_table_t table, uint8_t *data, uint32_t count); + +/** + * @brief it will start decoding, and the process status needs to be checked by + * querying JPEG_EVENT + * + * @param [in] ptr JPEG base address, HPM_JPEG + * @param [in] config config A pointer to the configuration struct of "jpeg_job_config_t" + * @param [in] length Decoded data length + * @retval jpeg decoding's status + * + */ +hpm_stat_t jpeg_start_decode(JPEG_Type *ptr, jpeg_job_config_t *config, uint32_t length); + +/** + * @brief * it will start encoding, and the process status needs to be checked by + * querying JPEG_EVENT + * + * @param [in] ptr JPEG base address, HPM_JPEG + * @param [in] config config A pointer to the configuration struct of "jpeg_job_config_t" + * @retval jpeg encoding's status + * + */ +hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif +#endif /* HPM_JPEG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h new file mode 100644 index 0000000000..6d75a3805c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h @@ -0,0 +1,451 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_LCDC_DRV_H +#define HPM_LCDC_DRV_H +#include "hpm_display_common.h" +#include "hpm_soc_feature.h" +#include "hpm_lcdc_regs.h" + +/** + * + * @brief LCD driver APIs + * @defgroup lcd_interface LCD driver APIs + * @ingroup io_interfaces + * @{ + */ + +#define LCDC_TEST_MODE_DISABLE (0U) +#define LCDC_TEST_MODE_BACKGROUND (1U) +#define LCDC_TEST_MODE_COLOR_BAR_COL (2U) +#define LCDC_TEST_MODE_COLOR_BAR_ROW (3U) + +/* @brief LCD driver specific status */ +enum { + status_lcdc_no_active_layer_yet = MAKE_STATUS(status_group_lcdc, 1), + status_lcdc_layer_not_supported = MAKE_STATUS(status_group_lcdc, 2), +}; + +/* @brief LCD line pattern */ +typedef enum lcdc_line_pattern { + lcdc_line_pattern_rgb = 0, + lcdc_line_pattern_rbg, + lcdc_line_pattern_gbr, + lcdc_line_pattern_grb, + lcdc_line_pattern_brg, + lcdc_line_pattern_bgr, +} lcdc_line_pattern_t; + +/* @brief LCD display mode */ +typedef enum lcdc_display_mode { + lcdc_display_mode_normal = 0, + lcdc_display_mode_test_mode_1, + lcdc_display_mode_test_mode_2, + lcdc_display_mode_test_mode_3, +} lcdc_display_mode_t; + +/* @brief LCD layer transfer max bytes */ +typedef enum lcdc_layer_max_bytes_per_transfer { + lcdc_layer_max_bytes_64 = 0, + lcdc_layer_max_bytes_128, + lcdc_layer_max_bytes_256, + lcdc_layer_max_bytes_512, + lcdc_layer_max_bytes_1024, +} lcdc_layer_max_bytes_per_transfer_t; + +/* @brief LCD control */ +typedef struct lcdc_control { + lcdc_line_pattern_t line_pattern; /**< Line pattern setting */ + lcdc_display_mode_t display_mode; /**< Display mode setting */ + bool invert_pixel_data; /**< Invert pixel data level */ + bool invert_pixel_clock; /**< Invert pixel clock level */ + bool invert_href; /**< Invert href level */ + bool invert_vsync; /**< Invert vsync level */ + bool invert_hsync; /**< Invert hsync level */ +} lcdc_control_t; + +/* @brief LCD hsync/vsync config */ +typedef struct lcdc_xsync_config { + uint16_t front_porch_pulse; /**< Front porch pulse */ + uint16_t back_porch_pulse; /**< Back porch pulse */ + uint16_t pulse_width; /**< Pulse width */ +} lcdc_xsync_config_t; + +/* @brief LCD config */ +typedef struct lcdc_config { + uint16_t resolution_x; /**< Horizontal resolution in pixel */ + uint16_t resolution_y; /**< Vertial resolution in pixel */ + lcdc_xsync_config_t hsync; /**< Hsync config */ + lcdc_xsync_config_t vsync; /**< Vsync config */ + display_color_32b_t background; /**< Background color */ + lcdc_control_t control; /**< LCD control */ +} lcdc_config_t; + +/* @brief LCD layer config */ +typedef struct lcdc_layer_config { + uint8_t max_ot; /**< Maximum outstanding transfer */ + display_byteorder_t byteorder; /**< Byte order */ + display_yuv_format_t yuv; /**< YUV format */ + display_pixel_format_t pixel_format; /**< Pixel format */ + display_alphablend_option_t alphablend; /**< Alphablending option */ + display_yuv2rgb_config_t csc_config; /**< Color space conversion config */ + lcdc_layer_max_bytes_per_transfer_t max_bytes; /**< Layer max transfer bytes */ + uint16_t height; /**< Layer height in pixel */ + uint16_t width; /**< Layer width in pixel */ + uint16_t position_x; /**< Layer output position X coord */ + uint16_t position_y; /**< Layer output position Y coord */ + display_color_32b_t background; /**< Background color */ + uint32_t buffer; /**< Pointer of layer display buffer */ +} lcdc_layer_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @brief Layer config + * + * @param[in] ptr LCD base address + */ +static inline void lcdc_software_reset(LCDC_Type *ptr) +{ + ptr->CTRL |= LCDC_CTRL_SW_RST_MASK; + ptr->CTRL &= ~LCDC_CTRL_SW_RST_MASK; +} + +/** + * + * @brief Enable interrupt according to the given mask + * + * @param[in] ptr LCD base address + * @param[in] interrupt_mask Mask of interrupts to be enabled + */ +static inline void lcdc_enable_interrupt(LCDC_Type *ptr, uint32_t interrupt_mask) +{ + ptr->INT_EN |= interrupt_mask; +} + +/** + * + * @brief Disable interrupt according to the given mask + * + * @param[in] ptr LCD base address + * @param[in] interrupt_mask Mask of interrupts to be disabled + */ +static inline void lcdc_disable_interrupt(LCDC_Type *ptr, uint32_t interrupt_mask) +{ + ptr->INT_EN &= ~interrupt_mask; +} + +/** + * + * @brief Clear specific status according to the given mask + * + * @param[in] ptr LCD base address + * @param[in] mask Status mask of status to be cleared + */ +static inline void lcdc_clear_status(LCDC_Type *ptr, uint32_t mask) +{ + ptr->ST |= mask; +} + +/** + * + * @brief Make layer control shadow registers take effect + * + * @param[in] ptr LCD base address + * @param[in] layer_index Index of layer to be controlled + */ +static inline bool lcdc_layer_control_shadow_loaded(LCDC_Type *ptr, uint8_t layer_index) +{ + return !(ptr->LAYER[layer_index].LAYCTRL & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK); +} + +/** + * + * @brief Get DMA status + * + * @param[in] ptr LCD base address + * @retval DMA status + */ +static inline uint32_t lcdc_get_dma_status(LCDC_Type *ptr) +{ + return ptr->DMA_ST; +} + +/** + * + * @brief Check DMA status against the given mask + * + * @param[in] ptr LCD base address + * @param[in] mask Mask of expected DMA status + * @retval true if all bits set to 1 in mask are set + * @retval false if any bit set to 1 in mask is not set + */ +static inline bool lcdc_check_dma_status(LCDC_Type *ptr, uint32_t mask) +{ + return ((ptr->DMA_ST & mask) == mask); +} + +/** + * + * @brief Clear DMA status according to the given mask + * + * @param[in] ptr LCD base address + * @param[in] mask Mask of expected DMA status + */ +static inline void lcdc_clear_dma_status(LCDC_Type *ptr, uint32_t mask) +{ + ptr->DMA_ST |= mask; +} + +/** + * + * @brief Get status + * + * @param[in] ptr LCD base address + * @retval current status + */ +static inline uint32_t lcdc_get_status(LCDC_Type *ptr) +{ + return ptr->ST; +} + +/** + * + * @brief Check status against the given mask + * + * @param[in] ptr LCD base address + * @param[in] mask Mask of expected status + * @retval true if all bits set to 1 in mask are set + * @retval false if any bit set to 1 in mask is not set + */ +static inline bool lcdc_check_status(LCDC_Type *ptr, uint32_t mask) +{ + return (ptr->ST & mask) == mask; +} + +/** + * + * @brief Set next buffer for certain layer + * + * @param[in] ptr LCD base address + * @param[in] layer_index target layer to be configured + * @param[in] buffer display buffer to be set + */ +static inline void lcdc_layer_set_next_buffer(LCDC_Type *ptr, uint32_t layer_index, uint32_t buffer) +{ + ptr->LAYER[layer_index].START0 = LCDC_LAYER_START0_ADDR0_SET(buffer); + ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; +} + +/** + * + * @brief Update specific layer background + * + * @param[in] ptr LCD base address + * @param[in] layer_index target layer to be configured + * @param[in] background color to be set as background + */ +static inline void lcdc_layer_update_background(LCDC_Type *ptr, + uint8_t layer_index, display_color_32b_t background) +{ + ptr->LAYER[layer_index].BG_CL = LCDC_LAYER_BG_CL_ARGB_SET(background.u); + ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; +} + +/** + * + * @brief Update specific layer position + * + * @param[in] ptr LCD base address + * @param[in] layer_index target layer to be configured + * @param[in] x Position X coord + * @param[in] y Position Y coord + */ +static inline void lcdc_layer_update_position(LCDC_Type *ptr, + uint8_t layer_index, uint16_t x, uint32_t y) +{ + ptr->LAYER[layer_index].LAYPOS = LCDC_LAYER_LAYPOS_X_SET(x) + | LCDC_LAYER_LAYPOS_Y_SET(y); + ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; +} + +/** + * + * @brief Update specific layer dimension + * + * @param[in] ptr LCD base address + * @param[in] layer_index target layer to be configured + * @param[in] width Width in pixel + * @param[in] height Height in pixel + */ +static inline void lcdc_layer_update_dimension(LCDC_Type *ptr, + uint8_t layer_index, uint8_t width, uint8_t height) +{ + ptr->LAYER[layer_index].LAYSIZE = LCDC_LAYER_LAYSIZE_WIDTH_SET(width) + | LCDC_LAYER_LAYSIZE_HEIGHT_SET(height); + ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; +} + +/** + * + * @brief Update specific layer region + * + * @param[in] ptr LCD base address + * @param[in] layer_index target layer to be configured + * @param[in] x1 X coord of the top left pixel + * @param[in] y1 Y coord of the top left pixel + * @param[in] x2 X coord of the bottom right pixel + * @param[in] y2 Y coord of the bottom right pixel + */ +static inline void lcdc_layer_set_region(LCDC_Type *ptr, uint8_t layer_index, + uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) +{ + ptr->LAYER[layer_index].LAYPOS = LCDC_LAYER_LAYPOS_X_SET(x1) + | LCDC_LAYER_LAYPOS_Y_SET(y1); + ptr->LAYER[layer_index].LAYSIZE = LCDC_LAYER_LAYSIZE_WIDTH_SET(x2 - x1 + 1) + | LCDC_LAYER_LAYSIZE_HEIGHT_SET(y2 - y1 + 1); + ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; +} + +/** + * + * @brief Update specific layer configuration + * + * @param[in] ptr LCD base address + * @param[in] layer_index target layer to be configured + */ +static inline void lcdc_layer_update(LCDC_Type *ptr, uint8_t layer_index) +{ + ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; +} + +/** + * + * @brief Enable specific layer + * + * @param[in] ptr LCD base address + * @param[in] layer_index target layer to be configured + */ +static inline void lcdc_layer_enable(LCDC_Type *ptr, uint32_t layer_index) +{ + ptr->LAYER[layer_index].LAYCTRL |= + (LCDC_LAYER_LAYCTRL_EN_MASK | LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK); +} + +/** + * + * @brief Disable specific layer + * + * @param[in] ptr LCD base address + * @param[in] layer_index target layer to be configured + */ +static inline void lcdc_layer_disable(LCDC_Type *ptr, uint32_t layer_index) +{ + ptr->LAYER[layer_index].LAYCTRL = + (ptr->LAYER[layer_index].LAYCTRL & (~LCDC_LAYER_LAYCTRL_EN_MASK)) + | LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; +} + +/** + * + * @brief Set test mode + * + * @param[in] ptr LCD base address + * @param[in] test_mode target test mode to be enabled + */ +static inline void lcdc_set_testmode(LCDC_Type *ptr, uint8_t test_mode) +{ + ptr->CTRL = ((ptr->CTRL & ~LCDC_CTRL_DISP_MODE_MASK)) + | LCDC_CTRL_DISP_MODE_SET(test_mode) + | LCDC_CTRL_DISP_ON_MASK; +} + +/** + * + * @brief Set background + * + * @param[in] ptr LCD base address + * @param[in] color background color + */ +static inline void lcdc_set_background(LCDC_Type *ptr, + display_color_32b_t color) +{ + ptr->BGND_CL = LCDC_BGND_CL_R_SET(color.r) + | LCDC_BGND_CL_G_SET(color.g) + | LCDC_BGND_CL_B_SET(color.b); +} + +/** + * + * @brief Get default layer configuration value + * + * @param[in] ptr LCD base address + * @param[out] layer Pointer of layer configuration struct buffer + * @param[in] pixel_format Pixel format to be used for this layer + * @param[in] layer_index target layer to be configured + */ +void lcdc_get_default_layer_config(LCDC_Type *ptr, + lcdc_layer_config_t *layer, display_pixel_format_t pixel_format, uint8_t layer_index); + +/** + * + * @brief Get default configuration value + * + * @param[in] ptr LCD base address + * @param[out] config Pointer of configuration struct buffer + */ +void lcdc_get_default_config(LCDC_Type *ptr, lcdc_config_t *config); + +/** + * + * @brief Initialize LCD controller + * + * @param[in] ptr LCD base address + * @param[in] config Pointer of configuration struct buffer + */ +void lcdc_init(LCDC_Type *ptr, lcdc_config_t *config); + +/** + * + * @brief Configure specific layer + * + * @param[in] ptr LCD base address + * @param[in] layer_index target layer to be configured + * @param[in] layer_config Pointer of layer configuration struct buffer + * @param[in] enable_layer Set true if the layer needs to be enabled right after being configured + */ +hpm_stat_t lcdc_config_layer(LCDC_Type *ptr, uint8_t layer_index, + lcdc_layer_config_t *layer_config, bool enable_layer); + +/** + * + * @brief Turn on display + * + * @param[in] ptr LCD base address + */ +void lcdc_turn_on_display(LCDC_Type *ptr); + +/** + * + * @brief Turn off display + * + * @param[in] ptr LCD base address + */ +void lcdc_turn_off_display(LCDC_Type *ptr); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_LCDC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h new file mode 100644 index 0000000000..1c9c15b993 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MBX_DRV_H +#define HPM_MBX_DRV_H +#include "hpm_common.h" +#include "hpm_mbx_regs.h" + +/** + * @brief MBX driver APIs + * @defgroup mbx_interface MBX driver APIs + * @ingroup io_interfaces + * @{ + */ + +/* + * @brief Bus access responses + */ +typedef enum { + no_bus_error_no_wait = 0, + generate_bus_error = 1, +} mbx_bus_access_resp_t; + +/* + * @brief MBX specific status + */ +enum { + status_mbx_not_available = MAKE_STATUS(status_group_mbx, 2), +}; + +#define MBX_CR_ALL_INTERRUPTS_MASK (MBX_CR_TFMAIE_MASK | MBX_CR_RFMAIE_MASK \ + | MBX_CR_RFMFIE_MASK | MBX_CR_TWMEIE_MASK) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set bus access response + * + * @param[in] ptr MBX base address + * @param[in] resp response value type + */ +static inline void mbx_set_bus_access_response(MBX_Type *ptr, mbx_bus_access_resp_t resp) +{ + ptr->CR = (ptr->CR & ~(MBX_CR_BARCTL_MASK)) | MBX_CR_BARCTL_SET(resp); +} + +/** + * @brief Enable interrupt with mask + * + * @param[in] ptr MBX base address + * @param[in] mask Mask of interrupts to be enabled + */ +static inline void mbx_enable_intr(MBX_Type *ptr, uint8_t mask) +{ + ptr->CR |= mask; +} + +/** + * @brief Disable interrupt with mask + * + * @param[in] ptr MBX base address + * @param[in] mask Mask of interrupts to be disabled + */ +static inline void mbx_disable_intr(MBX_Type *ptr, uint8_t mask) +{ + ptr->CR &= ~mask; +} + +/** + * @brief Empty fifo + * + * @param[in] ptr MBX base address + */ +static inline void mbx_empty_txfifo(MBX_Type *ptr) +{ + ptr->CR |= MBX_CR_TXRESET_MASK; +} + +/** + * @brief Initialization + * + * @param[in] ptr MBX base address + */ +static inline void mbx_init(MBX_Type *ptr) +{ + mbx_empty_txfifo(ptr); + mbx_disable_intr(ptr, MBX_CR_ALL_INTERRUPTS_MASK); +} + +/** + * @brief Send message + * + * @param[in] ptr MBX base address + * @param[in] msg Message data in 32 bits + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t mbx_send_message(MBX_Type *ptr, uint32_t msg) +{ + if (ptr->SR & MBX_SR_TWME_MASK) { + ptr->TXREG = msg; + return status_success; + } + return status_mbx_not_available; +} + + +/** + * @brief Retrieve message + * + * @param[in] ptr MBX base address + * @param[out] msg Pointer to buffer to save message data + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t mbx_retrieve_message(MBX_Type *ptr, uint32_t *msg) +{ + if (ptr->SR & MBX_SR_RWMV_MASK) { + *msg = ptr->RXREG; + return status_success; + } + return status_mbx_not_available; +} + +/** + * @brief Send message to fifo + * + * @param[in] ptr MBX base address + * @param[in] msg Pointer to message array to be sent + * @param[in] count Number of 32-bit data to be sent + * + * @return status_success if everything is okay + * @return status_not_available if fifo is full + */ +static inline hpm_stat_t mbx_send_fifo(MBX_Type *ptr, uint32_t *msg, uint32_t count) +{ + uint32_t i; + hpm_stat_t status = status_success; + for(i = 0; i < 4; i++) { + if (ptr->SR & MBX_SR_TFMA_MASK) { + ptr->TXWRD[0] = MBX_TXWRD_TXFIFO_SET(*(msg + i)); + count--; + if (!count) { + break; + } + } else { + status = status_mbx_not_available; + break; + } + } + return status; +} + + + +/** + * @brief Retrieve data from fifo + * + * @param[in] ptr MBX base address + * @param[out] msg Pointer of buffer to receive data + * @param[in] count Number of 32-bit data to be retrieved + * + * @return status_success if everything is okay + * @return status_mbx_not_available if fifo is empty + */ +static inline hpm_stat_t mbx_retrieve_fifo(MBX_Type *ptr, uint32_t *msg, uint32_t count) +{ + uint32_t i; + hpm_stat_t status = status_success; + for(i = 0; i < 4; i++) { + if (ptr->SR & MBX_SR_RFMA_MASK) { + *(msg + i) = (ptr->RXWRD[0] & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT; + count--; + if (!count) { + break; + } + } else { + status = status_mbx_not_available; + break; + } + } + return status; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_MBX_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h new file mode 100644 index 0000000000..1226441a6a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MCHTMR_DRV_H +#define HPM_MCHTMR_DRV_H +#include "hpm_common.h" +#include "hpm_mchtmr_regs.h" + +/** + * @brief MCHTMR driver APIs + * @defgroup mchtmr_interface MCHTMR driver APIs + * @ingroup io_interfaces + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief mchtmr get counter value + * + * @param [in] ptr MCHTMR base address + */ +static inline uint64_t mchtmr_get_count(MCHTMR_Type *ptr) +{ + return (ptr->MTIME & MCHTMR_MTIME_MTIME_MASK) >> MCHTMR_MTIME_MTIME_SHIFT; +} + +/** + * @brief mchtmr set comparator value + * + * @param [in] ptr MCHTMR base address + * @param [in] target comparator target value + */ +static inline void mchtmr_set_compare_value(MCHTMR_Type *ptr, uint64_t target) +{ + ptr->MTIMECMP = MCHTMR_MTIMECMP_MTIMECMP_SET(target); +} + +/** + * @brief mchtmr set delay value + * + * @param [in] ptr MCHTMR base address + * @param [in] delay delay cycles + */ +static inline void mchtmr_delay(MCHTMR_Type *ptr, uint64_t delay) +{ + mchtmr_set_compare_value(ptr, mchtmr_get_count(ptr) + delay); +} + +/** + * @brief initialize mchtmr counter + * + * @param [in] ptr MCHTMR base address + * @param [in] v value to be set + */ +void mchtmr_init_counter(MCHTMR_Type *ptr, uint64_t v); + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* HPM_MCHTMR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h new file mode 100644 index 0000000000..6ffbb406ab --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MONO_DRV_H +#define HPM_MONO_DRV_H + +#include "hpm_common.h" +#include "hpm_mono_regs.h" + +/** + * + * @brief MONO driver APIs + * @defgroup mono_interface MONO driver APIs + * @ingroup io_interfaces + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get counter high + * + * @param[in] ptr MONO base address + * + * @return counter value high 16 bits + */ +static inline uint16_t mono_get_counter_high(MONO_Type *ptr) +{ + return MONO_MONOH_COUNTER_GET(ptr->MONOH); +} + +/** + * @brief Get counter low + * + * @param[in] ptr MONO base address + * + * @return counter value low 32 bits + */ +static inline uint32_t mono_get_counter_low(MONO_Type *ptr) +{ + return MONO_MONOL_COUNTER_GET(ptr->MONOL); +} + +/** + * @brief Get counter + * + * @param[in] ptr MONO base address + * + * @return 48 bits counter value + */ +static inline uint64_t mono_get_counter(MONO_Type *ptr) +{ + return (uint64_t)((uint64_t)mono_get_counter_high(ptr) << 32) + | (uint64_t)mono_get_counter_low(ptr); +} + +/** + * @brief Get epoch + * + * @param[in] ptr MONO Base address + * + * @return epoch value 16 bits + */ +static inline uint32_t mono_get_epoch(MONO_Type *ptr) +{ + return MONO_MONOH_EPOCH_GET(ptr->MONOH); +} + + +/** + * @brief Update MONO counter by 1 + * + * @param[in] ptr MONO base + */ +static inline void mono_update(MONO_Type *ptr) +{ + ptr->MONOL = 1; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_MONO_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pcfg_drv.h new file mode 100644 index 0000000000..4f0b34dc8b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pcfg_drv.h @@ -0,0 +1,557 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PCFG_DRV_H +#define HPM_PCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_pcfg_regs.h" + +/** + * + * @brief PCFG driver APIs + * @defgroup pcfg_interface PCFG driver APIs + * @ingroup io_interfaces + * @{ + */ + +#define PCFG_DCDC_MODE_TURN_OFF (0U) +#define PCFG_DCDC_MODE_PERFORMACE (1U) +#define PCFG_DCDC_MODE_GENERIC (2U) +#define PCFG_DCDC_MODE_EXPERT (3U) + +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x11U) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x10U) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x01U) + +/* @brief PCFG modules */ +typedef enum { + pcfg_module_fuse = 0, + pcfg_module_sram, + pcfg_module_vad, + pcfg_module_gpio, + pcfg_module_ioc, + pcfg_module_timer, + pcfg_module_wdog, + pcfg_module_uart, + pcfg_module_debug, +} pcfg_module_t; + +/* @brief PCFG irc24m reference */ +typedef enum { + pcfg_irc24m_reference_32k = 0, + pcfg_irc24m_reference_24m_xtal = 1 +} pcfg_irc24m_reference_t; + +/* @brief PCFG status */ +enum { + status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), +}; + +/* @brief PCFG irc24m config */ +typedef struct { + uint32_t freq_in_hz; + pcfg_irc24m_reference_t reference; + bool return_to_default_on_xtal_loss; + bool free_run; +} pcfg_irc24m_config_t; + + +#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ + ((uint32_t) (mode) << ((module) << 1)) + +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE0 (PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE0 (0) +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE1 (PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE1 (0) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief bandgap disable power save mode + * + * @param ptr base address + */ +static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap enable power save mode + * + * @param ptr base address + */ +static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; +} + +static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief bandgap enable low power mode + * + * @param ptr base address + */ +static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief check if bandgap is trimmed or not + * + * @param ptr base address + * + * @return true if bandgap is trimmed + */ +static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) +{ + return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief bandgap reload trim value + * + * @param ptr base address + */ +static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief turn off LDO 1V + * + * @param ptr base address + */ +static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) +{ + ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn of LDO 1V + * + * @param ptr base address + */ +static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) +{ + ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; +} + +/* + * @brief set output voltage of LDO 1V in mV + * @param ptr base address + * @param mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/** + * @brief turn off LDO2P5 + * + * @param ptr base address + */ +static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) +{ + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief turn on LDO 2.5V + * + * @param ptr base address + */ +static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) +{ + ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief check if LDO 2.5V is stable + * + * @param ptr base address + * + * @return true if LDO2P5 is stable + */ +static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) +{ + return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); +} +/* + * @brief set output voltage of LDO 2.5V in mV + * @param ptr base address + * @param mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param ptr base address + * @param mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief check if DCDC is stable or not + * @param ptr base address + * @retval true if DCDC is stable + */ +static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); +} + +/* + * @brief check if DCDC is stable or not + * @param ptr base address + */ +static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(ptr->DCDC_MODE); +} + +/* + * @brief set DCDC voltage at standby mode + * @param ptr base address + * @param mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/** + * @brief set low power current limit + * + * @param ptr base address + * @param limit current limit at low power mode + * @param under_limit set to true means current is less than limit + */ +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, uint8_t limit, bool under_limit) +{ + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(!under_limit); +} + +/** + * @brief disable power loss protection + * + * @param ptr base address + */ +static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief enable power loss protection + * + * @param ptr base address + */ +static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief check if power loss flag is set + * + * @param ptr base address + * + * @return true if power loss is set + */ +static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over voltage protection + * + * @param ptr base address + */ +static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable over voltage protection + * + * @param ptr base address + */ +static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover voltage flag + * + * @param ptr base address + * @return true if flag is set + */ +static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; +} + +/** + * @brief disable current measurement + * + * @param ptr base address + */ +static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable current measurement + * + * @param ptr base address + */ +static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured current is valid + * + * @param ptr base address + * + * @return true if measured current is valid + */ +static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; +} + +/* + * @brief get current DCDC current level in mA + * + * @param ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + +/** + * @brief get DCDC start time in number of 24MHz clock cycles + * + * @param ptr base address + * + * @return dcdc start time in cycles + */ +static inline uint32_t pcfg_get_dcdc_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); +} + +/** + * @brief get DCDC resume time in number of 24MHz clock cycles + * + * @param ptr base address + * + * @return dcdc resuem time in cycles + */ +static inline uint32_t pcfg_get_dcdc_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); +} + +/** + * @brief set DCDC start time in 24MHz clock cycles + * + * @param ptr base address + * @param cycles start time in cycles + */ +static inline void pcfg_set_dcdc_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set DCDC resuem time in 24MHz clock cycles + * + * @param ptr base address + * @param cycles resume time in cycles + */ +static inline void pcfg_set_dcdc_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief disable power trap + * + * @param ptr base address + */ +static inline void pcfg_disable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief enable power trap + * + * @param ptr base address + */ +static inline void pcfg_enable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief check if power trap is triggered + * + * @param ptr base address + * + * @return true if power trap is triggered + */ +static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) +{ + return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief clear power trap trigger flag + * + * @param ptr base address + */ +static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief disable dcdc retention + * + * @param ptr base address + */ +static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief enable dcdc retention to retain soc sram data + * + * @param ptr base address + */ +static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief clear wakeup cause flag + * + * @param ptr base address + * @param mask mask of flags to be cleared + */ +static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_CAUSE |= mask; +} + +/** + * @brief get wakeup cause + * + * @param ptr base address + * + * @return mask of wake cause + */ +static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) +{ + return ptr->WAKE_CAUSE; +} + +/** + * @brief enable wakeup source + * + * @param ptr base address + * @param mask wakeup source mask + */ +static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK &= ~mask; +} + +/** + * @brief disable wakeup source + * + * @param ptr base address + * @param mask source to be disabled as wakeup source + */ +static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK |= mask; +} + +/** + * @brief set clock gate mode in pmic domain + * + * @param ptr base address + * @param mode clock gate mode mask + */ +static inline void pcfg_set_clock_gate_in_pmic(PCFG_Type *ptr, uint32_t mode) +{ + ptr->SCG_CTRL = mode; +} + +static inline void pcfg_config_debug_stop_source(PCFG_Type *ptr, uint8_t mask) +{ + ptr->DEBUG_STOP = mask; +} + +/** + * @brief check if irc24m is trimmed + * + * @param ptr base address + * + * @return true if it is trimmed + */ +static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) +{ + return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief reload irc24m trim value + * + * @param ptr base address + */ +static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) +{ + ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief config irc24m track + * + * @param ptr base address + * @param config config data + */ +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PMIC_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h new file mode 100644 index 0000000000..3d010fe702 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PDM_DRV_H +#define HPM_PDM_DRV_H + +#include "hpm_common.h" +#include "hpm_pdm_regs.h" + +/** + * @brief PDM driver APIs + * @defgroup pdm_interface PDM driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief PDM event + */ +#define PDM_EVENT_FILT_CRX_ERROR (PDM_ST_FILT_CRX_ERR_MASK) +#define PDM_EVENT_OFIFO_OVERFLOW_ERROR (PDM_ST_OFIFO_OVFL_ERR_MASK) +#define PDM_EVENT_CIC_OVERLOAD_ERROR (PDM_ST_CIC_OVLD_ERR_MASK) +#define PDM_EVENT_CIC_SAT_ERROR (PDM_ST_CIC_SAT_ERR_MASK) + +/** + * @brief PDM CIC sidma-delta filter order + */ +#define PDM_CIC_SIGMA_DELTA_ORDER_5 (2U) +#define PDM_CIC_SIGMA_DELTA_ORDER_6 (1U) +#define PDM_CIC_SIGMA_DELTA_ORDER_7 (0U) + +/** + * @brief PDM config + */ +typedef struct pdm_config { + bool sof_at_ref_clk_falling_edge; + bool bypass_pdm_clk_div; + bool enable_pdm_clk_out; + bool enable_hpf; + uint8_t pdm_clk_div; + uint8_t capture_delay; + uint8_t dec_after_cic; + uint8_t post_scale; + uint8_t sigma_delta_order; + uint8_t cic_dec_ratio; +} pdm_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief config high pass filter + * + * @param [in] ptr PDM base address + * @param [in] hpf_coef_ma high pass filter a coefficient's complement + * @param [in] hpf_coef_b high pass filter b coefficient + */ +static inline void pdm_config_hpf(PDM_Type *ptr, + uint32_t hpf_coef_ma, + uint32_t hpf_coef_b) +{ + ptr->HPF_MA = PDM_HPF_MA_COEF_SET(hpf_coef_ma); + ptr->HPF_B = PDM_HPF_B_COEF_SET(hpf_coef_b); +} + +/** + * @brief enable high pass filter + * + * @param [in] ptr PDM base address + */ +static inline void pdm_enable_hpf(PDM_Type *ptr) +{ + ptr->CTRL |= PDM_CTRL_HPF_EN_MASK; +} + +/** + * @brief disable high pass filter + * + * @param [in] ptr PDM base address + */ +static inline void pdm_disable_hpf(PDM_Type *ptr) +{ + ptr->CTRL &= ~PDM_CTRL_HPF_EN_MASK; +} + +/** + * @brief check whether PDM is running + * + * @param [in] ptr PDM base address + * @retval true in PDM is running + */ +static inline bool pdm_is_running(PDM_Type *ptr) +{ + return ptr->RUN & PDM_RUN_PDM_EN_MASK; +} + +/** + * @brief stop pdm + * + * @param [in] ptr PDM base address + */ +static inline void pdm_stop(PDM_Type *ptr) +{ + ptr->RUN &= ~PDM_RUN_PDM_EN_MASK; +} + +/** + * @brief start pdm + * + * @param [in] ptr PDM base address + */ +static inline void pdm_start(PDM_Type *ptr) +{ + ptr->RUN |= PDM_RUN_PDM_EN_MASK; +} + +/** + * @brief disable channel + * + * @param [in] ptr PDM base address + * @param [in] channel_disable_mask channel mask + */ +static inline void pdm_disable_channel(PDM_Type *ptr, + uint16_t channel_disable_mask) +{ + ptr->CH_CTRL &= ~PDM_CH_CTRL_CH_EN_SET(channel_disable_mask); +} + +/** + * @brief enable channel + * + * @param [in] ptr PDM base address + * @param [in] capture_high_level_mask capture when PDM_CLK is high + * @param [in] channel_enable_mask channel mask + */ +static inline void pdm_enable_channel(PDM_Type *ptr, + uint16_t capture_high_level_mask, + uint16_t channel_enable_mask) +{ + ptr->CH_CTRL |= PDM_CH_CTRL_CH_POL_SET(capture_high_level_mask) + | PDM_CH_CTRL_CH_EN_SET(channel_enable_mask); +} + +/** + * @brief disable pdm clock out + * + * @param [in] ptr PDM base address + */ +static inline void pdm_disable_pdm_clock_out(PDM_Type *ptr) +{ + ptr->CTRL &= ~PDM_CTRL_PDM_CLK_OE_MASK; +} + +/** + * @brief enable pdm clock out + * + * @param [in] ptr PDM base address + */ +static inline void pdm_enable_pdm_clock_out(PDM_Type *ptr) +{ + ptr->CTRL |= PDM_CTRL_PDM_CLK_OE_MASK; +} + +/** + * @brief pdm config cic + * + * @param [in] ptr PDM base address + * @param [in] sigma_delta_order sidma-delta filter order + * @param [in] div Rate of down sampling + * @param [in] post_scale output value post scale + */ +static inline void pdm_config_cic(PDM_Type *ptr, + uint8_t sigma_delta_order, + uint8_t div, + uint8_t post_scale) +{ + ptr->CIC_CFG = PDM_CIC_CFG_POST_SCALE_SET(post_scale) + | PDM_CIC_CFG_SGD_SET(sigma_delta_order) + | PDM_CIC_CFG_CIC_DEC_RATIO_SET(div); +} + +/** + * @brief pdm software reset + * + * @param [in] ptr PDM base address + */ +static inline void pdm_software_reset(PDM_Type *ptr) +{ + ptr->CTRL |= PDM_CTRL_SFTRST_MASK; + ptr->CTRL &= ~PDM_CTRL_SFTRST_MASK; +} + +/** + * @brief pdm enable irq + * + * @param [in] ptr PDM base address + * @param [in] mask pdm irq mask in ST register + */ +static inline void pdm_enable_irq(PDM_Type *ptr, uint8_t mask) +{ + ptr->CTRL |= mask << (PDM_CTRL_CIC_SAT_ERR_IE_SHIFT - PDM_ST_CIC_SAT_ERR_SHIFT); +} + +/** + * @brief pdm disable irq + * + * @param [in] ptr PDM base address + * @param [in] mask pdm irq mask in ST register + */ +static inline void pdm_disable_irq(PDM_Type *ptr, uint8_t mask) +{ + ptr->CTRL &= ~(mask << (PDM_CTRL_CIC_SAT_ERR_IE_SHIFT - PDM_ST_CIC_SAT_ERR_SHIFT)); +} + +/** + * @brief pdm initialization + * + * @param [in] ptr PDM base address + * @param [in] config pdm_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t pdm_init(PDM_Type *ptr, pdm_config_t *config); + +/** + * @brief pdm get default config + * + * @param [in] ptr PDM base address + * @param [out] config pdm_config_t + */ +void pdm_get_default_config(PDM_Type *ptr, pdm_config_t *config); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_PDM_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h new file mode 100644 index 0000000000..5b27e076a2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PDMA_DRV_H +#define HPM_PDMA_DRV_H +#include "hpm_soc_feature.h" +#include "hpm_display_common.h" +#include "hpm_pdma_regs.h" + +/** + * @brief PDMA driver APIs + * @defgroup pdma_interface PDMA driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief PDMA status + */ +enum { + status_pdma_done = status_success, + status_pdma_error = MAKE_STATUS(status_group_pdma, 1), + status_pdma_busy = MAKE_STATUS(status_group_pdma, 2), + status_pdma_idle = MAKE_STATUS(status_group_pdma, 3), +}; + +/** + * @brief PDMA plane + */ +typedef enum pdma_plane { + pdma_plane_src = 0, + pdma_plane_dst = 1, + pdma_plane_both, + pdma_plane_none, +} pdma_plane_t; + +/** + * @brief PDMA flip + */ +typedef enum pdma_flip { + pdma_flip_none = 0, + pdma_flip_horizontal = 1 << 0, + pdma_flip_vertical = 1 << 1, + pdma_flip_both = pdma_flip_horizontal | pdma_flip_vertical, +} pdma_flip_t; + +/** + * @brief PDMA rotate + */ +typedef enum pdma_rotate { + pdma_rotate_0_degree = 0, + pdma_rotate_90_degree = 1, + pdma_rotate_180_degree = 2, + pdma_rotate_270_degree = 3, +} pdma_rotate_t; + +/** + * @brief PDMA decimation + */ +typedef enum pdma_decimation { + pdma_decimation_by_1 = 0, + pdma_decimation_by_2 = 1, + pdma_decimation_by_4 = 2, + pdma_decimation_by_8 = 3, +} pdma_decimation_t; + +/** + * @brief PDMA block size + */ +typedef enum pdma_blocksize { + pdma_blocksize_16x16, + pdma_blocksize_8x8, +} pdma_blocksize_t; + +/** + * @brief PDMA make scale value + */ +#define PDMA_MAKE_SCALE_SET(integer, fractional) \ + (((integer) & 0x3) << 12 | ((fractional) & 0xFFF)) + +/** + * @brief PDMA plane config + */ +typedef struct pdma_plane_config { + bool swap_byte3_byte1; /**< set true to swap byte [31:24] and byte [15:8] */ + bool use_background_as_clear; /**< set true to use background color at blending clear mode */ + bool ycbcr_mode; /**< set true if it is YCbCr mode */ + bool bypass_colorspace_conversion; /**< set true to bypass color space conversion */ + bool byte_swap; /**< set true to swap [31:16] and [15:0] */ + display_byteorder_t byteorder; /**< packing byte order type */ + pdma_flip_t flip; /**< flip type */ + pdma_rotate_t rotate; /**< rotate type */ + pdma_decimation_t x_dec; /**< horizontal decimation */ + pdma_decimation_t y_dec; /**< vertical decimation */ + display_pixel_format_t pixel_format; /**< pixel format */ + uint32_t buffer; /**< buffer address */ + uint32_t background; /**< background color */ + uint32_t colorkey_high; /**< colorkey high limit */ + uint32_t colorkey_low; /**< colorkey low limit */ + uint16_t x_scale; /**< 14-bit horizontal scale */ + uint16_t y_scale; /**< 14-bit vertical scale */ + uint16_t pitch; /**< pitch value */ + uint16_t x_offset; /**< horizontal offset */ + uint16_t y_offset; /**< vertical offset */ + uint16_t width; /**< width */ + uint16_t height; /**< height */ +} pdma_plane_config_t; + +/** + * @brief PDMA output config + */ +typedef struct pdma_output_config { + display_alphablend_option_t alphablend; /**< alpha blending mode */ + display_pixel_format_t pixel_format; /**< pixel format */ + display_rgb2yuv_config_t rgb2yuv_config; /**< RGB to YUV config */ + uint32_t buffer; /**< buffer */ + struct { + uint16_t x; /**< plane origin X coord */ + uint16_t y; /**< plane origin Y coord */ + uint16_t width; /**< plane width */ + uint16_t height; /**< plane height */ + } plane[PDMA_SOC_PS_MAX_COUNT]; /**< plane config */ + uint16_t width; /**< output plane width */ + uint16_t height; /**< output plane height */ + uint16_t pitch; +} pdma_output_config_t; + +/** + * @brief PDMA config + */ +typedef struct pdma_config { + display_byteorder_t byteorder; /**< byte order */ + pdma_blocksize_t block_size; /**< block size */ + pdma_plane_t enable_plane; /**< plane to be enabled */ +} pdma_config_t; + +/** + * @brief PDMA plane info + */ +typedef struct pdma_plane_info { + uint32_t buffer; /**< buffer */ + uint32_t x; /**< plane origin X coord */ + uint32_t y; /**< plane origin Y coord */ + uint32_t width; /**< plane width */ + uint32_t height; /**< plane height */ + display_pixel_format_t format; /**< pixel format */ +} pdma_plane_info_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get default configuration according to input pixel format + * + * @param [in] ptr PDMA base address + * @param [out] config pdma_config_t + * @param [in] pixel_format display_pixel_format_t + */ +void pdma_get_default_config(PDMA_Type *ptr, pdma_config_t *config, display_pixel_format_t pixel_format); + +/** + * @brief Get default plane configuration according input pixel format + * + * @param [in] ptr PDMA base address + * @param [out] config pdma_plane_config_t + * @param [in] pixel_format display_pixel_format_t + */ +void pdma_get_default_plane_config(PDMA_Type *ptr, pdma_plane_config_t *config, display_pixel_format_t pixel_format); + +/** + * @brief Get default YUV2RGB coefficient configuration according to input pixel format + * + * @note The two plane share one YUV2RGB_COEF, so not support convert one plane YUV422 format + * and another plane YCbCr422 format at same time + * + * @param [in] ptr PDMA base address + * @param [out] yuv2rgb_coef display_yuv2rgb_coef_t + * @param [in] source_format the YUV2RGB input source pixel format + */ +void pdma_get_default_yuv2rgb_coef_config(PDMA_Type *ptr, display_yuv2rgb_coef_t *yuv2rgb_coef, display_pixel_format_t source_format); + +/** + * @brief Get default output configuration + * + * @param [in] ptr PDMA base address + * @param [out] config pdma_output_config_t + * @param [in] pixel_format output data pixel format + */ +void pdma_get_default_output_config(PDMA_Type *ptr, + pdma_output_config_t *config, display_pixel_format_t pixel_format); + +/** + * @brief PDMA enable/disable irq + * + * @param [in] ptr PDMA base address + * @param [in] mask irq mask + * @param [in] enable : + * @arg true: enable + * @arg false: disable + */ +void pdma_enable_irq(PDMA_Type *ptr, uint32_t mask, bool enable); + +/** + * @brief PDMA config output + * + * @param [in] ptr PDMA base address + * @param [in] config pdma_output_config_t + */ +void pdma_config_output(PDMA_Type *ptr, pdma_output_config_t *config); + +/** + * @brief Configure PDMA planes + * + * Note: The plane_src and plane_dst share one YUV2RGB_COEF, so not support convert one plane YUV422 format + * and another plane YCbCr422 format at same time + * + * @param [in] ptr PDMA base address + * @param [in] plane_src_config Pointer to plane_src configuration structure + * @param [in] plane_dst_config Pointer to plan_dst configuration structure + * @param [in] yuv2rgb_coef Pointer to yuv2rgb_coef configuration structure + */ +void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_config, void *yuv2rgb_coef); + +/** + * @brief PDMA initialization + * + * @param [in] ptr PDMA base address + * @param [in] config pdma_output_config_t + */ +void pdma_init(PDMA_Type *ptr, pdma_config_t *config); + +/** + * @brief PDMA check status + * + * @param [in] ptr PDMA base address + * @param [out] status pdma status + */ +hpm_stat_t pdma_check_status(PDMA_Type *ptr, uint32_t *status); + +/** + * @brief PDMA fill color + * + * @param [in] ptr PDMA base address + * @param [in] dst target buff address + * @param [in] dst_width target buff pixel width + * @param [in] width output image width + * @param [in] height output image height + * @param [in] color color value + * @param [in] alpha alpha value + * @param [in] format display_pixel_format_t + * @param [in] wait wait for execution to complete + * @param [out] status pdma status + * @retval hpm_stat_t: status_success if flip and rotate plane without any error + */ +hpm_stat_t pdma_fill_color(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, + uint32_t width, uint32_t height, + uint32_t color, uint8_t alpha, + display_pixel_format_t format, + bool wait, uint32_t *status); + +/** + * @brief PDMA flip rotate plane + * + * @param [in] ptr PDMA base address + * @param [in] dst target buff address + * @param [in] dst_width target buff pixel width + * @param [in] src source buff address + * @param [in] src_width source buff pixel width + * @param [in] x x coordinate n buffer + * @param [in] y y coordinate n buffer + * @param [in] width output image width + * @param [in] height output image height + * @param [in] flip pdma_flip_t + * @param [in] rotate pdma_rotate_t + * @param [in] alpha alpha value + * @param [in] format display_pixel_format_t + * @param [in] wait wait for execution to complete + * @param [out] status pdma status + * @retval hpm_stat_t: status_success if flip and rotate plane without any error + */ +hpm_stat_t pdma_flip_rotate(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, + uint32_t src, uint32_t src_width, uint32_t x, uint32_t y, + uint32_t width, uint32_t height, + pdma_flip_t flip, pdma_rotate_t rotate, uint8_t alpha, + display_pixel_format_t format, + bool wait, uint32_t *status); + +/** + * @brief PDMA blit plane + * + * @param [in] ptr PDMA base address + * @param [in] dst target buff address + * @param [in] dst_width target buff pixel width + * @param [in] src source buff address + * @param [in] src_width source buff pixel width + * @param [in] x x coordinate n buffer + * @param [in] y y coordinate n buffer + * @param [in] width output image width + * @param [in] height output image height + * @param [in] alpha alpha value + * @param [in] format display_pixel_format_t + * @param [in] wait wait for execution to complete + * @param [out] status pdma status + * @retval hpm_stat_t: status_success if flip and rotate plane without any error + */ +hpm_stat_t pdma_blit(PDMA_Type *ptr, + uint32_t dst, uint32_t dst_width, + uint32_t src, uint32_t src_width, + uint32_t x, uint32_t y, uint32_t width, uint32_t height, + uint8_t alpha, + display_pixel_format_t format, + bool wait, uint32_t *status); + +/** + * @brief PDMA scale plane + * + * @param [in] ptr PDMA base address + * @param [in] dst target buff address + * @param [in] dst_width target buff pixel width + * @param [in] src source buff address + * @param [in] src_width source buff pixel width + * @param [in] x x coordinate n buffer + * @param [in] y y coordinate n buffer + * @param [in] width input image width + * @param [in] height input image height + * @param [in] target_width output image width + * @param [in] target_height output image height + * @param [in] alpha alpha value + * @param [in] format display_pixel_format_t + * @param [in] wait wait for execution to complete + * @param [out] status pdma status + * @retval hpm_stat_t: status_success if flip and rotate plane without any error + */ +hpm_stat_t pdma_scale(PDMA_Type *ptr, + uint32_t dst, uint32_t dst_width, + uint32_t src, uint32_t src_width, + uint32_t x, uint32_t y, uint32_t width, uint32_t height, + uint32_t target_width, uint32_t target_height, + uint8_t alpha, + display_pixel_format_t format, + bool wait, uint32_t *status); + +/** + * @brief PDMA set block size + * + * @param [in] ptr PDMA base address + * @param [in] size pdma_blocksize_t + */ +void pdma_set_block_size(PDMA_Type *ptr, pdma_blocksize_t size); + +/** + * @brief PDMA stop + * + * @param [in] ptr PDMA base address + */ +void pdma_stop(PDMA_Type *ptr); + +/** + * @brief PDMA stop + * + * @param [in] ptr PDMA base address + * + * @retval STAT register value + */ +static inline uint32_t pdma_get_status(PDMA_Type *ptr) +{ + return ptr->STAT; +} + +/** + * @brief PDMA start + * + * @param [in] ptr PDMA base address + */ +static inline void pdma_start(PDMA_Type *ptr) +{ + ptr->CTRL |= PDMA_CTRL_PDMA_EN_MASK; + __asm volatile ("" : : "r" (ptr->CTRL)); +} + +/** + * @brief PDMA software reset + * + * @param [in] ptr PDMA base address + */ +static inline void pdma_software_reset(PDMA_Type *ptr) +{ + ptr->CTRL |= PDMA_CTRL_PDMA_SFTRST_MASK; + ptr->CTRL &= ~(PDMA_CTRL_PDMA_SFTRST_MASK); + __asm volatile ("" : : "r" (ptr->CTRL)); +} + +/** + * @brief PDMA set plane color key limits + * + * @param [in] ptr PDMA base address + * @param [in] plane_index plane index + * @param [in] key_high color key high limits + * @param [in] key_low color key low limits + */ +static inline void pdma_set_plane_colorkey(PDMA_Type *ptr, + uint8_t plane_index, + uint32_t key_high, + uint32_t key_low) +{ + ptr->PS[plane_index].CLRKEY_LOW = PDMA_PS_CLRKEY_LOW_LIMIT_SET(key_low); + ptr->PS[plane_index].CLRKEY_HIGH = PDMA_PS_CLRKEY_HIGH_LIMIT_SET(key_high); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* HPM_PDMA_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h new file mode 100644 index 0000000000..56d52a2049 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h @@ -0,0 +1,447 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLLCTL_DRV_H +#define HPM_PLLCTL_DRV_H +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_pllctl_regs.h" + +/** + * + * @brief PLLCTL driver APIs + * @defgroup pllctl_interface PLLCTL driver APIs + * @{ + */ + +#define PLLCTL_PLL_VCO_FREQ_MIN (375000000U) +#define PLLCTL_PLL_VCO_FREQ_MAX (2200000000U) + +/* + * @brief PLL parts with lock + */ +#define PLLCTL_PLL_LOCK_SS_RESET PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK +#define PLLCTL_PLL_LOCK_REFDIV PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK +#define PLLCTL_PLL_LOCK_POSTDIV1 PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK +#define PLLCTL_PLL_LOCK_SS_SPREAD PLLCTL_PLL_LOCK_LOCK_SS_SPREAD_MASK +#define PLLCTL_PLL_LOCK_SS_DIVVAL PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK +#define PLLCTL_PLL_LOCK_ALL (PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK \ + | PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK \ + | PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK \ + | PLLCTL_PLL_LOCK_LOCK_SS_SPREAD_MASK \ + | PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK \ + | PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) + +/* + * @brief PLLCTL specific status + */ +enum { + status_pllctl_not_enabled = MAKE_STATUS(status_group_pllctl, 1), + status_pllctl_out_of_range = MAKE_STATUS(status_group_pllctl, 2), +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Unlock pll + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] lock_mask Mask of PLL parts to be unlocked + */ +static inline void pllctl_pll_unlock(PLLCTL_Type *ptr, uint8_t pll, uint32_t lock_mask) +{ + ptr->PLL[pll].LOCK &= ~lock_mask; +} + +/** + * @brief Lock pll + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] lock_mask Mask of PLL parts to be locked + */ + +static inline void pllctl_pll_lock(PLLCTL_Type *ptr, uint8_t pll, uint32_t lock_mask) +{ + ptr->PLL[pll].LOCK = lock_mask; +} + +/** + * @brief Disable spread spectrum + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t pllctl_pll_ss_disable(PLLCTL_Type *ptr, uint8_t pll) +{ + if (pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) { + return status_invalid_argument; + } + + ptr->PLL[pll].CFG0 |= (PLLCTL_PLL_CFG0_SS_RSTPTR_MASK + | PLLCTL_PLL_CFG0_SS_RESET_MASK); + ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK; + return status_success; +} + +/** + * @brief Power down target PLL + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t pllctl_pll_powerdown(PLLCTL_Type *ptr, uint8_t pll) +{ + if (pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) { + return status_invalid_argument; + } + + ptr->PLL[pll].CFG1 = (ptr->PLL[pll].CFG1 & + ~(PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK | PLLCTL_PLL_CFG1_CLKEN_SW_MASK)) + | PLLCTL_PLL_CFG1_PLLPD_SW_MASK; + return status_success; +} + +/** + * @brief Power on target PLL + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t pllctl_pll_poweron(PLLCTL_Type *ptr, uint8_t pll) +{ + uint32_t cfg; + if (pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) { + return status_invalid_argument; + } + + cfg = ptr->PLL[pll].CFG1; + if (!(cfg & PLLCTL_PLL_CFG1_PLLPD_SW_MASK)) { + return status_success; + } + + if (cfg & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) { + ptr->PLL[pll].CFG1 &= ~PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK; + } + + ptr->PLL[pll].CFG1 &= ~PLLCTL_PLL_CFG1_PLLPD_SW_MASK; + + /* + * put back to hardware mode + */ + ptr->PLL[pll].CFG1 |= PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK; + return status_success; +} + +/** + * @brief Enable spread spectrum mode + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] spread Spread spectrum depth (1-31, from 0.1% to 3.1%) + * @param[in] div Spread spectrum divider (1-63, divide by 1 to 63) + * @param[in] down_spread Set true if need down-spread, otherwise center-spread + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t pllctl_pll_ss_enable(PLLCTL_Type *ptr, uint8_t pll, + uint8_t spread, uint8_t div, + bool down_spread) +{ + if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) + || (spread > (PLLCTL_PLL_CFG0_SS_SPREAD_MASK >> PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT)) + || (div > (PLLCTL_PLL_CFG0_SS_DIVVAL_MASK >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT))) { + return status_invalid_argument; + } + if (!(ptr->PLL[pll].CFG1 & PLLCTL_PLL_CFG1_PLLPD_SW_MASK)) { + pllctl_pll_powerdown(ptr, pll); + } + + ptr->PLL[pll].CFG0 &= ~(PLLCTL_PLL_CFG0_SS_RSTPTR_MASK + | PLLCTL_PLL_CFG0_SS_RESET_MASK); + ptr->PLL[pll].CFG0 &= ~PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK; + ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 + & ~(PLLCTL_PLL_CFG0_SS_SPREAD_MASK | PLLCTL_PLL_CFG0_SS_DIVVAL_MASK)) + | PLLCTL_PLL_CFG0_SS_SPREAD_SET(spread) + | PLLCTL_PLL_CFG0_SS_DIVVAL_SET(div) + | PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SET(down_spread); + + pllctl_pll_poweron(ptr, pll); + return status_success; +} + +/** + * @brief Set postdiv1 for PLL + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] div Postdiv1 value (0x1~0x7) + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t pllctl_set_postdiv1(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) +{ + if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) + || (!div) + || ((div) > (PLLCTL_PLL_CFG0_POSTDIV1_MASK >> PLLCTL_PLL_CFG0_POSTDIV1_SHIFT))) { + return status_invalid_argument; + } + + ptr->PLL[pll].CFG0 = ((ptr->PLL[pll].CFG0 & ~(PLLCTL_PLL_CFG0_POSTDIV1_MASK))) | PLLCTL_PLL_CFG0_POSTDIV1_SET(div); + return status_success; +} + +/** + * @brief Set fbdiv for PLL integer mode + * + * Fout = Fref/refdiv * fbdiv / postdiv1 + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] fbdiv Fbdiv value (0x1~0x1000) + * @note fbdiv value can not set too large, if Fref/refdiv * fbdiv > 2GHz, it might cause irrecoverable damage to that PLL + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t pllctl_set_fbdiv_int(PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) +{ + if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) + || ((fbdiv - 1) > (PLLCTL_PLL_CFG2_FBDIV_INT_MASK >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT))) { + return status_invalid_argument; + } + + ptr->PLL[pll].CFG2 = ((ptr->PLL[pll].CFG2 & ~(PLLCTL_PLL_CFG2_FBDIV_INT_MASK))) | PLLCTL_PLL_CFG2_FBDIV_INT_SET(fbdiv - 1); + return status_success; +} + +/** + * @brief Set fbdiv for PLL fraction mode + * + * Fout = Fref/refdive * (fbdiv + frac/2^24)/postdiv1 + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] fbdiv Fbdiv value (0x1~0x1000) + * @note fbdiv value can not set too large, if Fref/refdiv * fbdiv > 2GHz, it might cause irrecoverable damage to that PLL + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t pllctl_set_fbdiv_frac(PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) +{ + if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) + || ((fbdiv - 1) > (PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT))) { + return status_invalid_argument; + } + + ptr->PLL[pll].FREQ = (ptr->PLL[pll].FREQ & ~(PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK)) + | PLLCTL_PLL_FREQ_FBDIV_FRAC_SET(fbdiv - 1); + return status_success; +} + +/** + * @brief Set fraction for PLL fraction mode + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] frac 24-bit fixed float point value + * + * @return + */ +static inline hpm_stat_t pllctl_set_frac(PLLCTL_Type *ptr, uint8_t pll, uint32_t frac) +{ + if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) + || (frac > (PLLCTL_PLL_FREQ_FRAC_MASK >> PLLCTL_PLL_FREQ_FRAC_SHIFT))) { + return status_invalid_argument; + } + ptr->PLL[pll].FREQ = (ptr->PLL[pll].FREQ & ~(PLLCTL_PLL_FREQ_FRAC_MASK)) + | PLLCTL_PLL_FREQ_FRAC_SET(frac); + return status_success; +} + +/** + * @brief Get PLL divx value + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] div_index Target DIV to query + * + * @return Divider value of target DIV + */ +static inline hpm_stat_t pllctl_get_div(PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index) +{ + if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) + || !(PLLCTL_SOC_PLL_HAS_DIV0(pll))) { + return status_invalid_argument; + } + if (div_index) { + return PLLCTL_PLL_DIV0_DIV_GET(ptr->PLL[pll].DIV1) + 1; + } else { + return PLLCTL_PLL_DIV0_DIV_GET(ptr->PLL[pll].DIV0) + 1; + } +} + +/** + * @brief Set divider + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] div_index DIV index + * @param[in] div Divider value (starting from 1) + * + * @return status_success if everything is okay + */ +static inline hpm_stat_t pllctl_set_div(PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index, uint16_t div) +{ + if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) + || !(PLLCTL_SOC_PLL_HAS_DIV0(pll)) + || ((div - 1) > (PLLCTL_PLL_DIV0_DIV_MASK >> PLLCTL_PLL_DIV0_DIV_SHIFT))) { + return status_invalid_argument; + } + + if (div_index) { + ptr->PLL[pll].DIV1 = (ptr->PLL[pll].DIV1 & ~(PLLCTL_PLL_DIV1_DIV_MASK)) + | PLLCTL_PLL_DIV1_DIV_SET(div - 1); + } else { + ptr->PLL[pll].DIV0 = (ptr->PLL[pll].DIV0 & ~(PLLCTL_PLL_DIV0_DIV_MASK)) + | PLLCTL_PLL_DIV0_DIV_SET(div - 1); + } + return status_success; +} + +/** + * @brief Check if specific PLL DIV is stable + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] div_index Target DIV to check + * + * @return true if target PLL DIV is stable + */ +static inline bool pllctl_div_is_stable(PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index) +{ + if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) || !(PLLCTL_SOC_PLL_HAS_DIV0(pll))) { + return false; + } + if (div_index) { + return ptr->PLL[pll].DIV1 & PLLCTL_PLL_DIV0_RESPONSE_MASK; + } else { + return ptr->PLL[pll].DIV0 & PLLCTL_PLL_DIV0_RESPONSE_MASK; + } +} + +/** + * @brief Check if target PLL is enabled + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * + * @return true if target PLL is enabled + */ +static inline bool pllctl_pll_is_enabled(PLLCTL_Type *ptr, uint8_t pll) +{ + return (ptr->PLL[pll].STATUS & PLLCTL_PLL_STATUS_ENABLE_MASK); +} + +/** + * @brief Check if XTAL is stable + * + * @param[in] ptr PLLCTL base address + * + * @return true if XTAL is stable + */ +static inline bool pllctl_xtal_is_stable(PLLCTL_Type *ptr) +{ + return ptr->XTAL & PLLCTL_XTAL_RESPONSE_MASK; +} + +/** + * @brief Check if XTAL is enabled + * + * @param[in] ptr PLLCTL base address + * + * @return true if XTAL is enabled + */ +static inline bool pllctl_xtal_is_enabled(PLLCTL_Type *ptr) +{ + return ptr->XTAL & PLLCTL_XTAL_ENABLE_MASK; +} + +/* + * @brief set XTAL rampup time in cycles of IRC24M + * + * @param[in] ptr PLLCTL base address + */ +static inline void pllctl_xtal_set_rampup_time(PLLCTL_Type *ptr, uint32_t cycles) +{ + ptr->XTAL = (ptr->XTAL & ~PLLCTL_XTAL_RAMP_TIME_MASK) | PLLCTL_XTAL_RAMP_TIME_SET(cycles); +} + +/** + * @brief Set refdiv + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] div Divider value (0x1-0x3F) + * + * @return status_success if everything is okay + */ +hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div); + +/** + * @brief Initialize PLL working at integer mode with specific frequency + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] freq_in_hz Target frequency, expected >= 375000000Hz + * + * @return status_success if everything is okay + * + * @note The actual frequency might be slightly different from freq_in_hz due to calculation. + */ +hpm_stat_t pllctl_init_int_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, + uint32_t freq_in_hz); + +/** + * @brief Initialize PLL working at franction mode with specific frequency + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] freq_in_hz Target frequency, expected >= 375000000Hz + * + * @return status_success if everything is okay + * @note The actual frequency might be slightly different from freq_in_hz due to calculation. + */ +hpm_stat_t pllctl_init_frac_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, + uint32_t freq_in_hz); + +/** + * @brief Get frequency of target PLL + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * + * @return current frequency of target PLL in Hz + */ +uint32_t pllctl_get_pll_freq_in_hz(PLLCTL_Type *ptr, uint8_t pll); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_PLLCTL_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h new file mode 100644 index 0000000000..631a0bc9a9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLLCTLV2_DRV_H +#define HPM_PLLCTLV2_DRV_H + + +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_pllctlv2_regs.h" + +#define PLLCTLV2_CLK_SRC_XTAL24M (0U) +#define PLLCTLV2_CLK_SRC_IRC24M (1U) + +/** + * @brief PLLCTLV2 driver APIs + * @defgroup pllctlv2_interface PLLCTLV2 driver APIs + * @{ + */ + +/** + * @brief Check if external crystal is stable + * @param [in] ptr PLLCTLV2 base address + * @return true if external crystal is stable + */ +static inline bool pllctlv2_xtal_is_stable(PLLCTLV2_Type *ptr) +{ + return IS_HPM_BITMASK_SET(ptr->XTAL, PLLCTLV2_XTAL_RESPONSE_MASK); +} + +/** + * @brief Check if external crystal is enabled + * @param [in] ptr PLLCTLV2 base address + * @return true if external crystal is enabled + */ +static inline bool pllctlv2_xtal_is_enabled(PLLCTLV2_Type *ptr) +{ + return IS_HPM_BITMASK_SET(ptr->XTAL, PLLCTLV2_XTAL_ENABLE_MASK); +} + +/** + * @brief Set external crystal ramp-up time + * @param [in] ptr PLLCTLV2 base address + * @param [in] rc24m_cycles Cycles of RC24M clock + */ +static inline void pllctlv2_xtal_set_rampup_time(PLLCTLV2_Type *ptr, uint32_t rc24m_cycles) +{ + ptr->XTAL = (ptr->XTAL & ~PLLCTLV2_XTAL_RAMP_TIME_MASK) | PLLCTLV2_XTAL_RAMP_TIME_SET(rc24m_cycles); +} + +/** + * @brief Check is PLL is stable + * @param [in] ptr PLLCTLv2 base address + * @param [in] pll PLL index + * @return true if PLL is stable + */ +static inline bool pllctlv2_pll_is_stable(PLLCTLV2_Type *ptr, uint8_t pll) +{ + return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_BUSY_MASK); +} + +/** + * @brief Check if PLL is enabled + * @param [in] ptr PLLCTLV2 base address + * @param [in] pll PLL index + * @return true if PLL is enabled + */ +static inline bool pllctlv2_pll_is_enabled(PLLCTLV2_Type *ptr, uint8_t pll) +{ + return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_ENABLE_MASK); +} + +/** + * @brief Select the PLL reference clock + * @param [in] ptr PLLCTLV2 base address + * @param [in] pll PLL index + * @param [in] src PLL reference lcock source + * @arg 0 - XTAL24M + * @arg 1 - IRC24M + */ +static inline void pllctlv2_select_reference_clock(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t src) +{ + ptr->PLL[pll].CONFIG = (ptr->PLL[pll].CONFIG & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) | PLLCTLV2_PLL_CONFIG_REFSEL_SET(src); +} + +/** + * @brief Enable PLL Spread Spectrum feature + * @param [in] ptr PLLCTLV2 base address + * @param [in] pll PLL index + * @param [in] step Step of spread spectrum modulator + * @param [in] stop Stop point of spread spectrum modulator + */ +void pllctlv2_enable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t step, uint32_t stop); + +/** + * @brief Disable PLL Spread spectrum + * @param [in] ptr PLLCTLV2 base address + * @param [in] pll PLL index + */ +static inline void pllctlv2_disable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll) +{ + ptr->PLL[pll].CONFIG &= ~PLLCTLV2_PLL_CONFIG_SPREAD_MASK; +} + +/** + * @brief Set PLL lock time + * @param [in] ptr PLLCTLV2 base address + * @param [in] pll PLL index + * @param [in] xtal_cycles external Crystal cycles + */ +static inline void pllctlv2_set_pll_lock_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles) +{ + ptr->PLL[pll].LOCKTIME = PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(xtal_cycles); +} + +/** + * @brief Set PLL step time + * @param [in] ptr PLLCTLV2 base address + * @param [in] pll PLL index + * @param [in] xtal_cycles external Crystal cycles + */ +static inline void pllctlv2_set_pll_step_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles) +{ + ptr->PLL[pll].STEPTIME = PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(xtal_cycles); +} + +/** + * @brief Set PLL Post divider + * @param [in] ptr PLLCTLV2 base + * @param [in] pll PLL index + * @param [in] div_index Divider index + * @param [in] div_value divider value, divider factor is 1 + div_value / 5 + */ +void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index, uint8_t div_value); + +/** + * @brief Initialize PLL to specified frequency + * @param [in] ptr PLLCTLV2 base + * @param [in] pll PLL index + * @param [in] freq_in_hz expected PLL frequency + * @retval status_invalid_argument some parameters are invalid + * @retval status_success operation is successful + */ +hpm_stat_t pllctlv2_init_pll_with_freq(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t freq_in_hz); + +/** + * @brief Get the specified PLl clock frequency + * @param [in] ptr PLLCTLV2 base + * @param [in] pll PLL index + * @return PLL frequency in Hz + */ +uint32_t pllctlv2_get_pll_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll); + +/** + * @brief Get the selected PLL post divider frequency + * @param [in] ptr PLLCTLV2 base + * @param [in] pll PLL index + * @param [in] div_index Post divider index + * @return PLL frequency in Hz + */ +uint32_t pllctlv2_get_pll_postdiv_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index); + + +/** + * @} + */ +#endif /* HPM_PLLCTLV2_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h new file mode 100644 index 0000000000..7893fb2a36 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PMON_DRV_H +#define HPM_PMON_DRV_H +#include "hpm_common.h" +#include "hpm_pmon_regs.h" + +#define PMON_EVENT_GLITCH0 (1U << 0) +#define PMON_EVENT_GLITCH1 (1U << 1) +#define PMON_EVENT_CLOCK0 (1U << 2) +#define PMON_EVENT_CLOCK1 (1U << 3) + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void pmon_enable(PMON_Type *ptr, + uint8_t monitor_index, + bool enable) +{ + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL + & ~PMON_MONITOR_CONTROL_ENABLE_MASK) + | PMON_MONITOR_CONTROL_ENABLE_SET(enable); +} + +static inline void pmon_select_glitch_mode(PMON_Type *ptr, + uint8_t monitor_index, + bool active_mode) +{ + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL + & ~PMON_MONITOR_CONTROL_ACTIVE_MASK) + | PMON_MONITOR_CONTROL_ACTIVE_SET(active_mode); +} + +static inline bool pmon_glich_detected(PMON_Type *ptr, uint8_t monitor_index) +{ + return ptr->MONITOR[monitor_index].STATUS; +} + +static inline void pmon_test_mode_enable(PMON_Type *ptr, bool enable) +{ + ptr->TEST_MODE = (ptr->TEST_MODE & ~PMON_TEST_MODE_DISABLE_MASK) + | PMON_TEST_MODE_DISABLE_SET(!enable); +} + +static inline void pmon_irq_enable(PMON_Type *ptr, uint32_t mask, bool enable) +{ + ptr->IRQ_ENABLE = (ptr->IRQ_ENABLE & ~mask) | (enable ? mask : 0); +} + +static inline uint32_t pmon_irq_get_status(PMON_Type *ptr) +{ + return ptr->IRQ_FLAG; +} + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_PMON_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h new file mode 100644 index 0000000000..e735dc0073 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_PMP_DRV_H +#define HPM_PMP_DRV_H + +#include "hpm_common.h" + +/** + * @brief PMP Entry structure + */ +typedef struct pmp_entry_struct { + union { + struct { + uint8_t read_access_ctrl: 1; + uint8_t write_access_ctrl: 1; + uint8_t execution_ctrl: 1; + uint8_t addr_matching_mode: 2; + uint8_t reserved: 2; + uint8_t lock: 1; + }; + uint8_t val; + } pmp_cfg; + uint8_t reserved0[3]; + uint32_t pmp_addr; + union { + struct { + uint8_t entry_addr_matching_mode: 2; + uint8_t mem_type_attribute: 4; + uint8_t automic_mem_operation_ctrl: 1; + uint8_t reserved: 1; + }; + uint8_t val; + } pma_cfg; + uint8_t reserved1[3]; + uint32_t pma_addr; +} pmp_entry_t; + +/** + * @brief PMP Configuration definitions + */ +#define READ_EN (1U) +#define READ_DIS (0U) +#define WRITE_EN (1U) +#define WRITE_DIS (0U) +#define EXECUTE_EN (1U) +#define EXECUTE_DIS (0U) +#define ADDR_MATCH_MODE_OFF (0U) +#define ADDR_MATCH_TOR (1U) +#define ADDR_MATCH_NAPOT (3U) +#define REG_LOCK (1U) +#define REG_UNLOCK (0U) + +/** + * @brief PMA Configuration definitions + */ +#define MEM_TYPE_DEV_NON_BUF (0U) +#define MEM_TYPE_DEV_BUF (1U) +#define MEM_TYPE_MEM_NON_CACHE_NON_BUF (2U) +#define MEM_TYPE_MEM_NON_CACHE_BUF (3U) +#define MEM_TYPE_MEM_WT_NO_ALLOC (4U) +#define MEM_TYPE_MEM_WT_READ_ALLOC (5U) +#define MEM_TYPE_MEM_WB_NO_ALLOC (8U) +#define MEM_TYPE_MEM_WB_READ_ALLOC (9U) +#define MEM_TYPE_MEM_WB_WRITE_ALLOC (10U) +#define MEM_TYPE_MEM_WB_READ_WRITE_ALLOC (11U) +#define MEM_TYPE_EMPTY_HOLE (15U) + +#define AMO_EN (0U) +#define AMO_DIS (1U) + +/** + * @brief PMP Configuration + * @param r - READ Access control, valid value: READ_EN, READ_DIS + * @param w - Write access control, valid value: WRITE_EN, WRITE_DIS + * @param x - Instruction Execution control, valid value: EXECUTE_EN, EXECUTE_DIS + * @param m - Address matching mode, valid value: + * ADDR_MATCH_MODE_OFF - Null region + * ADDR_MATCH_TOR - Top of range. For pmp_addr0, any address < pmp_addr0 matches, for other regions, + * any address which meets ( pmp_addr[i-1] <= addr < pmp_addr) matches. + * ADDR_MATCH_NAPOT - Naturally aligned power-of-2 region, minimal size must be 8 bytes + * @param l - Write lock and permission enforcement bit for Machine mode, valid value: REG_LOCK, REG_UNLOCK + */ +#define PMP_CFG(r, w, x, m, l) ((r) | ((w) << 1) | ((x) << 2) | ((m) << 3) | ((l) << 7)) +/** + * @brief PMA Configuration + * @param m - Entry address matching mode, valid value: + * ADDR_MATCH_MODE_OFF - This PMA entry is disabled + * ADDR_MATCH_NAPOT - Naturally aligned power-of-2 region， the granularity is 4K bytes + * @param t - Memory type attributes, valid value: + * MEM_TYPE_DEV_NON_BUF - Device, Non-bufferable + * MEM_TYPE_DEV_BUF - Device, bufferable + * MEM_TYPE_MEM_NON_CACHE_NON_BUF - Memory, Non-cacheable, Non-bufferable + * MEM_TYPE_MEM_NON_CACHE_BUF - Memory, Non-cacheable, bufferable + * MEM_TYPE_MEM_WT_NO_ALLOC - Memory, Write-through, No-allocate + * MEM_TYPE_MEM_WT_READ_ALLOC - Memory, Write-through, read-allocate + * MEM_TYPE_MEM_WB_NO_ALLOC - Memory, Write-back, No-allocate + * MEM_TYPE_MEM_WB_READ_ALLOC - Memory, Write-back, Read-allocate + * MEM_TYPE_MEM_WB_READ_WRITE_ALLOC - Memory, Write-back, Write-Allocate, Read-Allocate + * MEM_TYPE_EMPTY_HOLE - Empty hole, nothing exists + * + * @param n - Indicate Whether Atomic Memory Operation instructions are not supported in this region, valid value: + * AMO_EN - Atomic Memory Operations are supported + * AMO_DIS - Atomic Memory Operations are not supported + */ +#define PMA_CFG(m, t, n) ((m) | ((t) << 2) | ((n) << 6)) +/** + * @brief Format Top Address Region + */ +#define PMP_TOR_ADDR(addr) ((addr) >> 2) +/** + * @brief Format PMP Natural Aligned Region + * @param x - start address + * @param n - power-of-2 aligned length + */ +#define PMP_NAPOT_ADDR(x, n) (((uint32_t)(x) >> 2) | (((uint32_t)(n)-1U) >> 3)) +/** + * @brief Format PMA Natural Aligned Region + * @param x - start address + * @param n - power-of-2 aligned length + */ +#define PMA_NAPOT_ADDR(x, n) (((uint32_t)(x) >> 2) | ((((uint32_t)(n)-1U) >> 3))) + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @brief Write PMP Configuration to corresponding PMP_CFG register + * @param value PMP configuration + * @param idx PMP entry index, valid value is 0-15 + */ +void write_pmp_cfg(uint32_t value, uint32_t idx); + +/** + * @brief Write PMA Configuration to corresponding PMA_CFG register + * @param value PMA configuration + * @param idx PMA entry index, valid value is 0-15 + */ +void write_pma_cfg(uint32_t value, uint32_t idx); + +/** + * @brief Read PMP configuration + * @param idx PMP entry index + * @return PMP configuration + */ +uint32_t read_pmp_cfg(uint32_t idx); + +/** + * @brief Read PMA configuration + * @param idx PMA entry index + * @return PMA configuration + */ +uint32_t read_pma_cfg(uint32_t idx); + +/** + * @brief Write PMP address to corresponding PMP_ADDR register + * @param value PMP address + * @param idx PMP address entry index, valid value is 0-15 + */ +void write_pmp_addr(uint32_t value, uint32_t idx); + +/** + * @brief Write PMA address to corresponding PMA_ADDR register + * @param value PMA address + * @param idx PMA address entry index, valid value is 0-15 + */ +void write_pma_addr(uint32_t value, uint32_t idx); + +/** + * @brief Read PMP address entry + * @param idx PMP address entry index + * @return PMP address + */ +uint32_t read_pmp_addr(uint32_t idx); + +/** + * @brief Read PMA address entry + * @param idx PMA address entry index, valid value is 0-15 + * @return PMA address + */ +uint32_t read_pma_addr(uint32_t idx); + +/** + * @brief Configure PMP and PMA based on the PMP entry list + * @param entry start of the PMP entry list + * @param num_of_entries Number of entries in the PMP entry list + * @return #status_invalid_argument - Invalid Arguments were detected + * #status_success - Configuration completed without errors + */ +hpm_stat_t pmp_config(const pmp_entry_t *entry, uint32_t num_of_entries); + +/** + * @brief Disable PMP and PMA + */ +void pmp_disable(void); + +#ifdef __cplusplus +} +#endif + + +#endif /* HPM_PMP_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppor_drv.h new file mode 100644 index 0000000000..a0b2c0da32 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppor_drv.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PPOR_DRV_H +#define HPM_PPOR_DRV_H +#include "hpm_ppor_regs.h" + +typedef enum { + ppor_reset_brownout = 1 << 0, + ppor_reset_temperature = 1 << 1, + ppor_reset_pin = 1 << 2, + ppor_reset_debug = 1 << 4, + ppor_reset_security_violation = 1 << 5, + ppor_reset_jtag = 1 << 6, + ppor_reset_cpu0_lockup = 1 << 8, + ppor_reset_cpu1_lockup = 1 << 9, + ppor_reset_cpu0_request = 1 << 10, + ppor_reset_cpu1_request = 1 << 11, + ppor_reset_wdog0 = 1 << 16, + ppor_reset_wdog1 = 1 << 17, + ppor_reset_wdog2 = 1 << 18, + ppor_reset_wdog3 = 1 << 19, + ppor_reset_pmic_wdog = 1 << 20, + ppor_reset_software = 1 << 31, +} ppor_reset_source_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * perform software reset in counter * (1/24Mhz) seconds + */ +static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) +{ + ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } + +/* + * clear enable reset source according to the given mask + */ +static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE &= ~mask; +} + +/* + * set enable reset source according to the given mask + */ +static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE |= mask; +} + +/* + * set enable reset source + */ +static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) +{ + ptr->RESET_ENABLE = reset_sources; +} + +/* + * get enabled reset source + */ +static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) +{ + return ptr->RESET_ENABLE; +} + +/* + * get reset status + */ +static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) +{ + return ptr->RESET_STATUS; +} + +/* + * get reset flags + */ +static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) +{ + return ptr->RESET_FLAG; +} + +/* + * clear reset flags + */ +static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_FLAG |= mask; +} + +/* + * set cold reset + */ +static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD = mask; +} + +/* + * clear cold reset + */ +static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD &= ~mask; +} + +/* + * set hot reset + */ +static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT = mask; +} + +/* + * clear hot reset + */ +static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT &= ~mask; +} + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h new file mode 100644 index 0000000000..3cc5c1606e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PSEC_DRV_H +#define HPM_PSEC_DRV_H +#include "hpm_common.h" +#include "hpm_psec_regs.h" + +typedef enum psec_lifecycle { + psec_lifecycle_unknown = 1 << 0, + psec_lifecycle_create = 1 << 1, + psec_lifecycle_nonsecucre = 1 << 2, + psec_lifecycle_secucre = 1 << 3, + psec_lifecycle_return = 1 << 4, + psec_lifecycle_no_return = 1 << 5, + psec_lifecycle_scribe = 1 << 6, + psec_lifecycle_debate = 1 << 7, +} psec_lifecycle_t; + +typedef enum batt_sec_state { + batt_sec_state_ins = 0, + batt_sec_state_secure = 1, + batt_sec_state_non_secure = 2, + batt_sec_state_fail = 3, +} batt_sec_state_t; + +typedef enum psec_state { + psec_state_ins = 0, + psec_state_secure = 1, + psec_state_non_secure = 2, + psec_state_fail = 3, +} psec_state_t; + +enum { + status_psec_switch_state_not_allowed = MAKE_STATUS(status_group_psec, 1), +}; + +#define PSEC_PSECURE_STATE_MASK \ + (0xFU << PSEC_SECURE_STATE_PMIC_INS_SHIFT) +#define PSEC_BATT_SECURE_STATE_MASK \ + (0xFU << PSEC_SECURE_STATE_BATT_INS_SHIFT) + +#ifdef __cplusplus +extern "C" { +#endif + +static inline psec_lifecycle_t psec_get_pmic_lifecycle(PSEC_Type *ptr) +{ + return (psec_lifecycle_t) PSEC_LIFECYCLE_LIFECYCLE_GET(ptr->LIFECYCLE); +} + +static inline hpm_stat_t psec_switch_pmic_state(PSEC_Type *ptr, psec_state_t state) +{ + if ((state == psec_state_secure)) { + if (!PSEC_SECURE_STATE_ALLOW_SEC_GET(ptr->SECURE_STATE)) { + return status_psec_switch_state_not_allowed; + } + } else if ((state == psec_state_non_secure)) { + if (!PSEC_SECURE_STATE_ALLOW_NSC_GET(ptr->SECURE_STATE)) { + return status_psec_switch_state_not_allowed; + } + } + ptr->SECURE_STATE = (ptr->SECURE_STATE & ~PSEC_PSECURE_STATE_MASK) + | (1U << (PSEC_SECURE_STATE_PMIC_INS_SHIFT + state)); + return status_success; +} + +static inline void psec_allow_psecure_state_restart(PSEC_Type *ptr, bool allow) +{ + ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG + & ~PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) + | PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(allow); +} + +static inline void psec_lock_psecure_state_restart(PSEC_Type *ptr, bool lock) +{ + ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG + & ~PSEC_SECURE_STATE_CONFIG_LOCK_MASK) + | PSEC_SECURE_STATE_CONFIG_LOCK_SET(lock); +} + +static inline void psec_pmic_rom_secrets_present(PSEC_Type *ptr, bool presented) +{ + ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG + & ~PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_MASK) + | PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_SET(presented); +} + +static inline void psec_psec_secure_state_config(PSEC_Type *ptr, + bool rom_secrets_presented, + bool allow_secure_state_restart, + bool lock_secure_state_restart) +{ + ptr->SECURE_STATE_CONFIG = PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_SET(rom_secrets_presented) + | PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(allow_secure_state_restart) + | PSEC_SECURE_STATE_CONFIG_LOCK_SET(lock_secure_state_restart); +} + +static inline void psec_pmic_non_secure_violation_config(PSEC_Type *ptr, + uint32_t violation_setting, + bool lock) +{ + ptr->VIOLATION_CONFIG = (ptr->VIOLATION_CONFIG + & ~(PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK + | PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK)) + | PSEC_VIOLATION_CONFIG_LOCK_NSC_SET(lock) + | PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(violation_setting); +} + +static inline void psec_psecure_violation_config(PSEC_Type *ptr, + uint32_t violation_setting, + bool lock) +{ + ptr->VIOLATION_CONFIG = (ptr->VIOLATION_CONFIG + & ~(PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK + | PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK)) + | PSEC_VIOLATION_CONFIG_LOCK_SEC_SET(lock) + | PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(violation_setting); +} + +static inline void psec_pmic_non_secure_escalate_config(PSEC_Type *ptr, + uint32_t violation_setting, + bool lock) +{ + ptr->ESCALATE_CONFIG = (ptr->ESCALATE_CONFIG + & ~(PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK + | PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK)) + | PSEC_ESCALATE_CONFIG_LOCK_NSC_SET(lock) + | PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(violation_setting); +} + +static inline void psec_psecure_escalate_config(PSEC_Type *ptr, + uint32_t violation_setting, + bool lock) +{ + ptr->ESCALATE_CONFIG = (ptr->ESCALATE_CONFIG + & ~(PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK + | PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK)) + | PSEC_ESCALATE_CONFIG_LOCK_SEC_SET(lock) + | PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(violation_setting); +} + +static inline uint32_t psec_get_pmic_status(PSEC_Type *ptr) +{ + return ptr->EVENT; +} + +static inline psec_lifecycle_t psec_get_batt_lifecycle(PSEC_Type *ptr) +{ + return (psec_lifecycle_t) PSEC_LIFECYCLE_LIFECYCLE_GET(ptr->LIFECYCLE); +} + +static inline hpm_stat_t psec_switch_batt_state(PSEC_Type *ptr, batt_sec_state_t state) +{ + if ((state == batt_sec_state_secure)) { + if (!PSEC_SECURE_STATE_ALLOW_SEC_GET(ptr->SECURE_STATE)) { + return status_psec_switch_state_not_allowed; + } + } else if ((state == batt_sec_state_non_secure)) { + if (!PSEC_SECURE_STATE_ALLOW_NSC_GET(ptr->SECURE_STATE)) { + return status_psec_switch_state_not_allowed; + } + } + ptr->SECURE_STATE = (ptr->SECURE_STATE & ~PSEC_BATT_SECURE_STATE_MASK) + | (1U << (PSEC_SECURE_STATE_BATT_INS_SHIFT + state)); + return status_success; +} + +static inline void psec_allow_batt_secure_state_restart(PSEC_Type *ptr, bool allow) +{ + ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG + & ~PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) + | PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(allow); +} + +static inline void psec_lock_batt_secure_state_restart(PSEC_Type *ptr, bool lock) +{ + ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG + & ~PSEC_SECURE_STATE_CONFIG_LOCK_MASK) + | PSEC_SECURE_STATE_CONFIG_LOCK_SET(lock); +} + +static inline void psec_batt_rom_secrets_present(PSEC_Type *ptr, bool presented) +{ + ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG + & ~PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_MASK) + | PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_SET(presented); +} + +static inline void psec_batt_set_secure_state_config(PSEC_Type *ptr, + bool rom_secrets_presented, + bool allow_secure_state_restart, + bool lock_secure_state_restart) +{ + ptr->SECURE_STATE_CONFIG = PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_SET(rom_secrets_presented) + | PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(allow_secure_state_restart) + | PSEC_SECURE_STATE_CONFIG_LOCK_SET(lock_secure_state_restart); +} + +static inline void psec_batt_non_secure_violation_config(PSEC_Type *ptr, + uint32_t violation_setting, + bool lock) +{ + ptr->VIOLATION_CONFIG = (ptr->VIOLATION_CONFIG + & ~(PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK + | PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK)) + | PSEC_VIOLATION_CONFIG_LOCK_NSC_SET(lock) + | PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(violation_setting); +} + +static inline void psec_batt_secure_violation_config(PSEC_Type *ptr, + uint32_t violation_setting, + bool lock) +{ + ptr->VIOLATION_CONFIG = (ptr->VIOLATION_CONFIG + & ~(PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK + | PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK)) + | PSEC_VIOLATION_CONFIG_LOCK_SEC_SET(lock) + | PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(violation_setting); +} + +static inline void psec_batt_non_secure_escalate_config(PSEC_Type *ptr, + uint32_t violation_setting, + bool lock) +{ + ptr->ESCALATE_CONFIG = (ptr->ESCALATE_CONFIG + & ~(PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK + | PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK)) + | PSEC_ESCALATE_CONFIG_LOCK_NSC_SET(lock) + | PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(violation_setting); +} + +static inline void psec_batt_secure_escalate_config(PSEC_Type *ptr, + uint32_t violation_setting, + bool lock) +{ + ptr->ESCALATE_CONFIG = (ptr->ESCALATE_CONFIG + & ~(PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK + | PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK)) + | PSEC_ESCALATE_CONFIG_LOCK_SEC_SET(lock) + | PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(violation_setting); +} + +static inline uint32_t psec_get_batt_status(PSEC_Type *ptr) +{ + return ptr->EVENT; +} +#ifdef __cplusplus +} +#endif + +#endif /* HPM_PSEC_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h new file mode 100644 index 0000000000..34e42a244a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PTPC_DRV_H +#define HPM_PTPC_DRV_H + +#include "hpm_common.h" +#include "hpm_ptpc_regs.h" + +/** + * @brief PTPC driver + * @defgroup ptpc_interface PTPC driver APIs + * @ingroup timer_interfaces Timers + * @{ + */ + +#define PTPC_EVENT_COMPARE0_MASK PTPC_INT_STS_COMP_INT_STS0_MASK +#define PTPC_EVENT_CAPTURE0_MASK PTPC_INT_STS_CAPTURE_INT_STS0_MASK +#define PTPC_EVENT_PPS0_MASK PTPC_INT_STS_PPS_INT_STS0_MASK +#define PTPC_EVENT_COMPARE1_MASK PTPC_INT_STS_COMP_INT_STS1_MASK +#define PTPC_EVENT_CAPTURE1_MASK PTPC_INT_STS_CAPTURE_INT_STS1_MASK +#define PTPC_EVENT_PPS1_MASK PTPC_INT_STS_PPS_INT_STS1_MASK + +#define PTPC_MAX_NS_COUNTER (0x3B9ACA00UL) + +/** + * @brief Counter types + */ +typedef enum ptpc_ns_counter_rollover_type { + ptpc_ns_counter_rollover_binary = 0, /**< binary mode, resolution ~0.466ns, overflow at 0x7FFFFFFF */ + ptpc_ns_counter_rollover_digital = 1, /**< digital mode, resolution 1ns, overflow at 0x3B9ACA00 */ +} ptpc_ns_counter_rollover_type_t; + +/** + * @brief Capture trigger types + */ +typedef enum ptpc_capture_trigger_type { + ptpc_capture_trigger_none = 0, + ptpc_capture_trigger_on_rising_edge = PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK, + ptpc_capture_trigger_on_failing_edge = PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK, + ptpc_capture_trigger_on_both_edges = PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK + | PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK, +} ptpc_capture_trigger_type_t; + +/** + * @brief Capture trigger types + */ +typedef enum ptpc_counting_mode { + ptpc_counting_increment = 0, /**< Increment the counter */ + ptpc_counting_decrement = 1, /**< Decrement the counter */ +} ptpc_counting_mode; + +/** + * @brief Timer config + */ +typedef struct { + ptpc_capture_trigger_type_t capture_trigger; /**< Capture trigger */ + ptpc_ns_counter_rollover_type_t ns_rollover_mode; /**< Ns rollover mode */ + bool coarse_increment; /**< Set false to use fine increment */ + bool capture_keep; /**< Keep captured timer counter */ + uint32_t src_frequency; /**< Source frequency */ +} ptpc_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configure ns counter rollover mode + * + * @param[in] ptr PTPC base address + * @param[in] index Index of target counter + * @param[in] rollover Rollover type + */ +static inline void ptpc_set_ns_counter_rollover(PTPC_Type *ptr, uint8_t index, + ptpc_ns_counter_rollover_type_t rollover) +{ + ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) + | PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(rollover); +} + +/** + * @brief Enable capture keep + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + */ +static inline void ptpc_enable_capture_keep(PTPC_Type *ptr, uint8_t index) +{ + ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK; +} + +/** + * @brief Disable capture keep + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + */ +static inline void ptpc_disable_capture_keep(PTPC_Type *ptr, uint8_t index) +{ + ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK; +} + +/** + * @brief Update ns counter update type + * + * @param[in] ptr PTPC base address + * @param[in] index Index of target counter + * @param[in] coarse_update Counter will be increment by 1 on + */ +static inline void ptpc_set_ns_counter_update_type(PTPC_Type *ptr, uint8_t index, bool coarse_update) +{ + ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) + | PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(coarse_update); +} + +/** + * @brief Set ns counter increment step + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] ns_step Increment step + */ +static inline void ptpc_set_ns_counter_step(PTPC_Type *ptr, uint8_t index, uint32_t ns_step) +{ + ptr->PTPC[index].CTRL1 = PTPC_PTPC_CTRL1_SS_INCR_SET(ns_step); +} + +/** + * @brief Set Second portion update value + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] sec Second value + */ +static inline void ptpc_set_second_update(PTPC_Type *ptr, uint8_t index, uint32_t sec) +{ + ptr->PTPC[index].TS_UPDTH = PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(sec); +} + +/** + * @brief Set ns portion update value + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] ns Ns value (31 bits, 0x3B9ACA00 max) + * @param[in] mode Counting mode + * + * @return status_success if everything is okay + */ +hpm_stat_t ptpc_set_ns_update(PTPC_Type *ptr, uint8_t index, uint32_t ns, ptpc_counting_mode mode); + +/** + * @brief Get current timestamp Second portion + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * + * @return Seconds value + */ +static inline uint32_t ptpc_get_timestamp_second(PTPC_Type *ptr, uint8_t index) +{ + return PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(ptr->PTPC[index].TIMEH); +} + +/** + * @brief Get timestamp ns portion + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * + * @return ns value + */ +static inline uint32_t ptpc_get_timestamp_ns(PTPC_Type *ptr, uint8_t index) +{ + return PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(ptr->PTPC[index].TIMEL); +} + +/** + * @brief Config compare + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] sec Target second + * @param[in] ns Target ns + */ +static inline void ptpc_config_compare(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns) +{ + ptr->PTPC[index].TARH = PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(sec); + ptr->PTPC[index].TARL = PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(ns); + ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_COMP_EN_MASK; +} + +/** + * @brief Update Second portion + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] sec Target second + */ +static inline void ptpc_update_timestamp_second(PTPC_Type *ptr, uint8_t index, uint32_t sec) +{ + ptr->PTPC[index].TS_UPDTH = PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(sec); +} + +/** + * @brief Update Ns portion + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] ns Target ns + * @param[in] mode Counting mode + */ +static inline void ptpc_update_timestamp_ns(PTPC_Type *ptr, uint8_t index, uint32_t ns, ptpc_counting_mode mode) +{ + ptr->PTPC[index].TS_UPDTL = PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(ns) | PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(mode); +} + +/** + * @brief Enable timer + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + */ +static inline void ptpc_enable_timer(PTPC_Type *ptr, uint8_t index) +{ + ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK; +} + +/** + * @brief Disable timer + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + */ +static inline void ptpc_disable_timer(PTPC_Type *ptr, uint8_t index) +{ + ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK; +} + +/** + * @brief Config capture trigger event + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] trigger Capture trigger type + */ +static inline void ptpc_config_capture(PTPC_Type *ptr, uint8_t index, + ptpc_capture_trigger_type_t trigger) +{ + ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~(PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK + | PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK)) | trigger; +} + +/** + * @brief Get snapped ns value + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * + * @return ns portion on capture + */ +static inline uint32_t ptpc_get_capture_ns(PTPC_Type *ptr, uint8_t index) +{ + return PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(ptr->PTPC[index].CAPT_SNAPL); +} + +/** + * @brief Get captured second + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * + * @return second portion on capture + */ +static inline uint32_t ptpc_get_capture_second(PTPC_Type *ptr, uint8_t index) +{ + return PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(ptr->PTPC[index].CAPT_SNAPH); +} + +/** + * @brief Clear interrupt status + * + * @param[in] ptr PTPC base address + * @param[in] mask Mask of interrupts to be cleared + */ +static inline void ptpc_clear_irq_status(PTPC_Type *ptr, uint32_t mask) +{ + ptr->INT_STS |= mask; +} + +/** + * @brief Get interrupt status + * + * @param[in] ptr PTPC base address + * + * @return interrupt status mask + */ +static inline uint32_t ptpc_get_irq_status(PTPC_Type *ptr) +{ + return ptr->INT_STS; +} + +/** + * @brief Disable interrupt with mask + * + * @param[in] ptr PTPC base address + * @param[in] mask Mask of interrupts to be disabled + */ +static inline void ptpc_irq_disable(PTPC_Type *ptr, uint32_t mask) +{ + ptr->INT_EN &= ~mask; +} + +/** + * @brief Enable interrupt with mask + * + * @param[in] ptr PTPC base address + * @param[in] mask Mask of interrupts to be enabled + */ +static inline void ptpc_irq_enable(PTPC_Type *ptr, uint32_t mask) +{ + ptr->INT_EN |= mask; +} + +/** + * @brief Initialize PTPC module + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] config Pointer to configuration struct + * + * @return status_success if everything is okay + */ +hpm_stat_t ptpc_init(PTPC_Type *ptr, uint8_t index, ptpc_config_t *config); + +/** + * @brief Set PTPC output destination + * + * @param[in] ptr PTPC base address + * @param[in] can_index Target CAN instance + * @param[in] use_ptpc1 Use PTPC1 if set to true, otherwise PTPC0 + * + * @return status_success if everything is okay + */ +hpm_stat_t ptpc_set_timer_output(PTPC_Type *ptr, uint8_t can_index, bool use_ptpc1); + +/** + * @brief Get default config + * + * @param[in] ptr PTPC base address + * @param[out] config Pointer of config struct + */ +void ptpc_get_default_config(PTPC_Type *ptr, ptpc_config_t *config); + +/** + * @brief Initialize timer to count from 0 + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * + */ +void ptpc_init_timer(PTPC_Type *ptr, uint8_t index); + +/** + * @brief Initialize timer with initial values + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] sec Seconds + * @param[in] ns Ns + * @param[in] mode Counting mode + * + * @return status_success if everything is okay + */ +hpm_stat_t ptpc_init_timer_with_initial(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode); + +/** + * @brief Update timestamp counter + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] sec Seconds + * @param[in] ns Ns + * @param[in] mode Counting mode + * @return status_success if everything is okay + */ +hpm_stat_t ptpc_update_timer(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode); + +/** + * @brief Set period of pulse generated per second + * + * @param[in] ptr PTPC base address + * @param[in] index Target index + * @param[in] p (2^power Hz, from [0 - 15]) + * + * @return true if requested frequency can be set + * @return false if requested frequency can not be set + */ +hpm_stat_t ptpc_set_pps(PTPC_Type *ptr, uint8_t index, uint8_t p); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PTPC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h new file mode 100644 index 0000000000..34b403f6da --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h @@ -0,0 +1,789 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PWM_DRV_H +#define HPM_PWM_DRV_H + +#include "hpm_common.h" +#include "hpm_pwm_regs.h" +/** + * @brief PWM driver APIs + * @defgroup pwm_interface PWM driver APIs + * @ingroup io_interfaces + * @{ + * + */ +#define PWM_UNLOCK_KEY (0xB0382607UL) + +/* IRQ enable bit mask */ +#define PWM_IRQ_FAULT PWM_IRQEN_FAULTIRQE_MASK +#define PWM_IRQ_EX_RELOAD PWM_IRQEN_XRLDIRQE_MASK +#define PWM_IRQ_HALF_RELOAD PWM_IRQEN_HALFRLDIRQE_MASK +#define PWM_IRQ_RELOAD PWM_IRQEN_RLDIRQE_MASK +#define PWM_IRQ_CMP(x) PWM_IRQEN_CMPIRQEX_SET((1 << x)) + +/* PWM force output mask */ +#define PWM_FORCE_OUTPUT(pwm_index, force_output) \ + (force_output << (pwm_index << 1)) + +#define PWM_DUTY_CYCLE_FP_MAX ((1U << 24) - 1) + +/** + * @brief pwm trigger mode + * + */ +typedef enum pwm_counter_type { + pwm_counter_type_capture_rising_edge, /**< rising edge trigger*/ + pwm_counter_type_capture_falling_edge, /**< falling edge trigger*/ +} pwm_counter_type_t; + +/** + * @brief pwm cmp mode + * + */ +typedef enum pwm_cmp_mode { + pwm_cmp_mode_output_compare = 0, /**< output compare*/ + pwm_cmp_mode_input_capture = 1, /**< input compare*/ +} pwm_cmp_mode_t; + +/** + * @brief update time of the shadow register + * + */ +typedef enum pwm_register_update { + pwm_shadow_register_update_on_shlk = 0, /**< after software set shlk bit of shlk register*/ + pwm_shadow_register_update_on_modify = 1, /**< immediately after the register being modified*/ + pwm_shadow_register_update_on_hw_event = 2, /**< after hardware event assert*/ + pwm_shadow_register_update_on_sh_synci = 3, /**< after SHSYNCI assert */ +} pwm_shadow_register_update_trigger_t; + +/** + * @brief configure the state of channel 0∼7 outputs when the forced output is in effect + * + */ +typedef enum pwm_fault_mode { + pwm_fault_mode_force_output_0 = 0, /**< fault forced output logic 0 */ + pwm_fault_mode_force_output_1 = 1, /**< fault forced output logic 1 */ + pwm_fault_mode_force_output_highz = 2, /**< turn off output, pin becomes high resistance */ +} pwm_fault_mode_t; + +/** + * @brief select when to recover PWM output after fault + * + */ +typedef enum pwm_fault_recovery_trigger { + pwm_fault_recovery_immediately = 0, /**< immediately*/ + pwm_fault_recovery_on_reload = 1, /**< after pwm timer counter reload time*/ + pwm_fault_recovery_on_hw_event = 2, /**< after hardware event assert*/ + pwm_fault_recovery_on_fault_clear = 3, /**< after software write faultclr bit in GCR register*/ +} pwm_fault_recovery_trigger_t; + +/** + * @brief fault input signal + * + */ +typedef enum pwm_fault_source { + pwm_fault_source_internal_0 = PWM_GCR_FAULTI0EN_MASK, /**< FAULTI0 */ + pwm_fault_source_internal_1 = PWM_GCR_FAULTI1EN_MASK, /**< FAULTI1 */ + pwm_fault_source_internal_2 = PWM_GCR_FAULTI2EN_MASK, /**< FAULTI2 */ + pwm_fault_source_internal_3 = PWM_GCR_FAULTI3EN_MASK, /**< FAULTI3 */ + pwm_fault_source_external_0 = PWM_GCR_FAULTE0EN_MASK, /**< EXFAULTI0 */ + pwm_fault_source_external_1 = PWM_GCR_FAULTE1EN_MASK, /**< EXFAULTI1 */ +} pwm_fault_source_t; + +/** + * @brief Select sources for force output + * + */ +typedef enum pwm_force_source { + pwm_force_source_force_input = 0, /**< force output is enabled when FRCI assert */ + pwm_force_source_software = 1, /**< force output is enabled by software write swfrc to 1 */ +} pwm_force_source_t; +/** + * @brief select when the FRCMD shadow register will be loaded to its work register + * + */ +typedef enum pwm_force_cmd_timing { + pwm_force_immediately = 0, /**< after software set shlk bit of shlk register */ + pwm_force_at_reload = 1, /**< immediately after the register being modified */ + pwm_force_at_synci = 2, /**< after hardware event assert */ + pwm_force_none = 3, /**< after SHSYNCI assert */ +} pwm_force_cmd_timing_t; + +/** + * @brief pwm output type + * + */ +typedef enum pwm_output_type { + pwm_output_0 = 0, /**< output 0 */ + pwm_output_1 = 1, /**< output 1 */ + pwm_output_high_z = 2, /**< output */ + pwm_output_no_force = 3, +} pwm_output_type_t; + +/** + * @brief pwm compare config + * + */ +typedef struct pwm_cmp_config { + uint32_t cmp; /**< compare value */ + bool enable_ex_cmp; /**< enable extended compare value */ + uint8_t mode; /**< compare work mode: pwm_cmp_mode_output_compare or pwm_cmp_mode_input_capture */ + uint8_t update_trigger; /**< compare configuration update trigger */ + uint8_t ex_cmp; /**< extended compare value */ + uint8_t half_clock_cmp; /**< half clock compare value*/ + uint8_t jitter_cmp; /**< jitter compare value */ +} pwm_cmp_config_t; + +/** + * @brief pwm output channel config + * + */ +typedef struct pwm_output_channel { + uint8_t cmp_start_index; /**< output channel compare start index */ + uint8_t cmp_end_index; /**< output channel compare end index */ + bool invert_output; /**< invert output */ +} pwm_output_channel_t; +/** + * @brief pwm fault source config + * + */ +typedef struct pwm_fault_source_config { + uint32_t source_mask; /**< fault source mask*/ + bool fault_recover_at_rising_edge; /**< recover fault at rising edge */ + bool external_fault_active_low; /**< active external fault by low */ + uint8_t fault_output_recovery_trigger; /**< fault output recoverty trigger */ +} pwm_fault_source_config_t; + +/** + * @brief pwm config data + * + */ +typedef struct pwm_config { + bool enable_output; /**< enable pwm output */ + bool invert_output; /**< invert pwm output level */ + uint8_t update_trigger; /**< pwm config update trigger */ + uint8_t fault_mode; /**< fault mode */ + uint8_t fault_recovery_trigger; /**< fault recoverty trigger */ + uint8_t force_source; /**< fault source */ + uint32_t dead_zone_in_half_cycle; /**< dead zone in half cycle*/ +} pwm_config_t; + +/** + * @brief pair pwm config + * + */ +typedef struct pwm_pair_config { + pwm_config_t pwm[2]; /**< pwm config data */ +} pwm_pair_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief issue all shawdow register + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_issue_shadow_register_lock_event(PWM_Type *pwm_x) +{ + if (pwm_x->SHCR & PWM_SHCR_SHLKEN_MASK) { + /* + * if lock shadow register has been enabled in SHCR, it has to set + * the lock bit twice to issue shadow register lock event. + */ + pwm_x->SHLK = PWM_SHLK_SHLK_MASK; + } + pwm_x->SHLK = PWM_SHLK_SHLK_MASK; +} + +/** + * @brief lock all shawdow register + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_shadow_register_lock(PWM_Type *pwm_x) +{ + pwm_x->SHCR |= PWM_SHCR_SHLKEN_MASK; + pwm_x->SHLK = PWM_SHLK_SHLK_MASK; +} + +/** + * @brief unlock all shadow register + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_shadow_register_unlock(PWM_Type *pwm_x) +{ + pwm_x->UNLK = PWM_UNLOCK_KEY; +} + +/** + * @brief set counter start value and extended start value + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] ex_start pwm timer counter extended start value + * @param[in] start pwm timer counter start value + */ +static inline void pwm_set_start_count(PWM_Type *pwm_x, + uint8_t ex_start, + uint32_t start) +{ + pwm_x->STA = PWM_STA_XSTA_SET(ex_start) + | PWM_STA_STA_SET(start); +} + +/** + * @brief set the reload value + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] ex_reload pwm timer counter extended reload value + * @param[in] reload pwm timer counter reload value + */ +static inline void pwm_set_reload(PWM_Type *pwm_x, + uint8_t ex_reload, + uint32_t reload) +{ + pwm_shadow_register_unlock(pwm_x); + pwm_x->RLD = PWM_RLD_XRLD_SET(ex_reload) + | PWM_RLD_RLD_SET(reload); +} + +/** + * @brief clear pwm status register + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] mask : + * @arg PWM_IRQ_FAULT: fault condition flag + * @arg PWM_IRQ_EX_RELOAD : extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + * @arg PWM_IRQ_HALF_RELOAD: half reload flag, this flag set when cnt count to rld/2 + * @arg PWM_IRQ_RELOAD: reload flag, this flag set when cnt count to rld value or when SYNCI assert + * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag + */ +static inline void pwm_clear_status(PWM_Type *pwm_x, uint32_t mask) +{ + pwm_x->SR |= mask; +} + +/** + * @brief get pwm status register + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @retval uint32_t SR register value + */ +static inline uint32_t pwm_get_status(PWM_Type *pwm_x) +{ + return pwm_x->SR; +} + +/** + * @brief disable pwm irq + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] mask : + * @arg PWM_IRQ_FAULT: fault condition interrupt enable + * @arg PWM_IRQ_EX_RELOAD: extended reload flag interrupt enable + * @arg PWM_IRQ_HALF_RELOAD: half reload flag interrupt enable + * @arg PWM_IRQ_RELOAD: reload flag interrupt enable + * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag interrupt enable + */ +static inline void pwm_disable_irq(PWM_Type *pwm_x, uint32_t mask) +{ + pwm_x->IRQEN &= ~mask; +} + +/** + * @brief enable pwm irq + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] mask : + * @arg PWM_IRQ_FAULT: fault condition interrupt enable + * @arg PWM_IRQ_EX_RELOAD: extended reload flag interrupt enable + * @arg PWM_IRQ_HALF_RELOAD: half reload flag interrupt enable + * @arg PWM_IRQ_RELOAD: reload flag interrupt enable + * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag interrupt enable + */ +static inline void pwm_enable_irq(PWM_Type *pwm_x, uint32_t mask) +{ + pwm_x->IRQEN |= mask; +} + +/** + * @brief disable pwm dma request + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] mask : + * @arg PWM_IRQ_FAULT: fault condition DMA request enable + * @arg PWM_IRQ_EX_RELOAD: extended reload flag DMA request enable + * @arg PWM_IRQ_HALF_RELOAD: half reload flag DMA request enable + * @arg PWM_IRQ_RELOAD: reload flag DMA request enable + * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag DMA request enable + * + */ +static inline void pwm_disable_dma_request(PWM_Type *pwm_x, uint32_t mask) +{ + pwm_x->DMAEN &= ~mask; +} + +/** + * @brief enable pwm dma request + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] mask : + * @arg PWM_IRQ_FAULT: fault condition DMA request enable + * @arg PWM_IRQ_EX_RELOAD: extended reload flag DMA request enable + * @arg PWM_IRQ_HALF_RELOAD: half reload flag DMA request enable + * @arg PWM_IRQ_RELOAD: reload flag DMA request enable + * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag DMA request enable + * + */ +static inline void pwm_enable_dma_request(PWM_Type *pwm_x, uint32_t mask) +{ + pwm_x->DMAEN |= mask; +} + +/** + * @brief set target cmp as hardware event to trigger force cmd output + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] target_cmp_index cmp index select one of the cmp as hardware event time to load FRCMD shadow registers [0-23] + */ +static inline void pwm_set_force_cmd_shadow_register_hwevent(PWM_Type *pwm_x, + uint8_t target_cmp_index) +{ + pwm_x->SHCR = ((pwm_x->SHCR & ~(PWM_SHCR_FRCSHDWSEL_MASK)) + | PWM_SHCR_FRCSHDWSEL_SET(target_cmp_index)); +} +/** + * @note if trigger is not set to hardware event, target_cmp_index can be + * passed with any value + * + */ + +/** + * @brief set shadow register control register + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] trigger select when the counter related shadow registers @ref pwm_shadow_register_update_trigger_t + * @param[in] target_cmp_index select one of the comparators as hardware event (0..(PWM_SOC_CMP_MAX_COUNT-1)) + */ +static inline void pwm_set_load_counter_shadow_register_trigger(PWM_Type *pwm_x, + pwm_shadow_register_update_trigger_t trigger, + uint8_t target_cmp_index) +{ + if (trigger == pwm_shadow_register_update_on_hw_event) { + pwm_x->SHCR = ((pwm_x->SHCR & ~(PWM_SHCR_CNTSHDWSEL_MASK + | PWM_SHCR_CNTSHDWUPT_MASK)) + | PWM_SHCR_CNTSHDWSEL_SET(target_cmp_index) + | PWM_SHCR_CNTSHDWUPT_SET(trigger)); + } else { + pwm_x->SHCR = ((pwm_x->SHCR & ~(PWM_SHCR_CNTSHDWUPT_MASK)) + | PWM_SHCR_CNTSHDWUPT_SET(trigger)); + } +} + +/** + * @brief configure the hardware to trigger the shadow register to update the CMP + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + * @param[in] edge which edge is used as shadow register hardware load event + * @arg 1- falling edge + * @arg 0- rising edge + */ +static inline void pwm_load_cmp_shadow_on_capture(PWM_Type *pwm_x, + uint8_t index, + bool edge) +{ + pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK; + pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_CMPSHDWSEL_MASK | PWM_GCR_HWSHDWEDG_MASK)) + | PWM_GCR_CMPSHDWSEL_SET(index) + | PWM_GCR_HWSHDWEDG_SET(edge)); +} + +/** + * @brief disable pwn cmp half clock + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + */ +static inline void pwm_cmp_disable_half_clock(PWM_Type *pwm_x, uint8_t index) +{ + pwm_x->CMP[index] &= ~PWM_CMP_CMPHLF_MASK; +} + +/** + * @brief enable pwm cmp half clock + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + */ +static inline void pwm_cmp_enable_half_clock(PWM_Type *pwm_x, uint8_t index) +{ + pwm_x->CMP[index] |= PWM_CMP_CMPHLF_MASK; +} + +/** + * @brief update pwm cmp jitter counter compare value + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + * @param[in] jitter jitter value + */ +static inline void pwm_cmp_update_jitter_value(PWM_Type *pwm_x, uint8_t index, uint8_t jitter) +{ + pwm_x->CMP[index] = (pwm_x->CMP[index] & ~PWM_CMP_CMPJIT_MASK) | PWM_CMP_CMPJIT_SET(jitter); +} + +/** + * @brief update pwm cmp value + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + * @param[in] cmp clock counter compare value + * @param[in] ex_cmp extended counter compare value + */ +static inline void pwm_cmp_update_cmp_value(PWM_Type *pwm_x, uint8_t index, + uint32_t cmp, uint16_t ex_cmp) +{ + pwm_x->CMP[index] = (pwm_x->CMP[index] & ~(PWM_CMP_CMP_MASK | PWM_CMP_XCMP_MASK)) + | PWM_CMP_CMP_SET(cmp) | PWM_CMP_XCMP_SET(ex_cmp); +} + +/** + * @brief config pwm cmp + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + * @param[in] config @ref pwm_cmp_config_t + */ +static inline void pwm_config_cmp(PWM_Type *pwm_x, uint8_t index, pwm_cmp_config_t *config) +{ + pwm_shadow_register_unlock(pwm_x); + if (config->mode == pwm_cmp_mode_output_compare) { + pwm_x->CMPCFG[index] = PWM_CMPCFG_XCNTCMPEN_SET(config->enable_ex_cmp) + | PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); + pwm_x->CMP[index] = PWM_CMP_CMP_SET(config->cmp) + | PWM_CMP_XCMP_SET(config->ex_cmp) + | PWM_CMP_CMPHLF_SET(config->half_clock_cmp) + | PWM_CMP_CMPJIT_SET(config->jitter_cmp); + } else { + pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK; + } +} + +/** + * @brief config pwm output channel + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index channel index (0..(PWM_SOC_PWM_MAX_COUNT-1)) + * @param[in] config @ref pwm_output_channel_t + */ +static inline void pwm_config_output_channel(PWM_Type *pwm_x, uint8_t index, pwm_output_channel_t *config) +{ + pwm_x->CHCFG[index] = PWM_CHCFG_CMPSELBEG_SET(config->cmp_start_index) + | PWM_CHCFG_CMPSELEND_SET(config->cmp_end_index) + | PWM_CHCFG_OUTPOL_SET(config->invert_output); +} + +/** + * @brief config pwm fault source + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] config @ref pwm_fault_source_config_t + */ +static inline void pwm_config_fault_source(PWM_Type *pwm_x, pwm_fault_source_config_t *config) +{ + pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_FAULTI0EN_MASK | PWM_GCR_FAULTI1EN_MASK + | PWM_GCR_FAULTI2EN_MASK | PWM_GCR_FAULTI3EN_MASK + | PWM_GCR_FAULTE0EN_MASK | PWM_GCR_FAULTE1EN_MASK + | PWM_GCR_FAULTRECEDG_MASK | PWM_GCR_FAULTEXPOL_MASK + | PWM_GCR_FAULTRECHWSEL_MASK)) + | config->source_mask + | PWM_GCR_FAULTEXPOL_SET(config->external_fault_active_low) + | PWM_GCR_FAULTRECEDG_SET(config->fault_recover_at_rising_edge) + | PWM_GCR_FAULTRECHWSEL_SET(config->fault_output_recovery_trigger); +} + +/** + * @brief clear pwm fault status + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_clear_fault(PWM_Type *pwm_x) +{ + pwm_x->GCR |= PWM_GCR_FAULTCLR_MASK; +} + +/** + * @brief stop the pwm timer counter + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_stop_counter(PWM_Type *pwm_x) +{ + pwm_x->GCR &= ~PWM_GCR_CEN_MASK; +} + +/** + * @brief start pwm timer counter + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_start_counter(PWM_Type *pwm_x) +{ + pwm_x->GCR |= PWM_GCR_CEN_MASK; +} + +/** + * @brief enable software force + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_enable_sw_force(PWM_Type *pwm_x) +{ + pwm_x->GCR |= PWM_GCR_SWFRC_MASK; +} + +/** + * @brief disable software force , force will take effect + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_disable_sw_force(PWM_Type *pwm_x) +{ + pwm_x->GCR &= ~PWM_GCR_SWFRC_MASK; +} + +/** + * @brief enable pwm reload value by synci + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_enable_reload_at_synci(PWM_Type *pwm_x) +{ + pwm_x->GCR |= PWM_GCR_XRLDSYNCEN_MASK | PWM_GCR_RLDSYNCEN_MASK; +} + +/** + * @brief disable pwm output + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index pwm index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + */ +static inline void pwm_disable_output(PWM_Type *pwm_x, uint8_t index) +{ + pwm_x->PWMCFG[index] &= ~PWM_PWMCFG_OEN_MASK; +} + +/** + * @brief enable pwm output + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index pwm index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + */ +static inline void pwm_enable_output(PWM_Type *pwm_x, uint8_t index) +{ + pwm_x->PWMCFG[index] |= PWM_PWMCFG_OEN_MASK; +} + +/** + * @brief config pwm force output level per output channel + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] output_mask PWM output channel force level, set it using the macro + * @arg PWM_FORCE_OUTPUT(pwm_index, force_output) + */ +static inline void pwm_set_force_output(PWM_Type *pwm_x, uint32_t output_mask) +{ + pwm_x->FRCMD = PWM_FRCMD_FRCMD_SET(output_mask); +} + +/** + * @brief config pwm force polarity + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] polarity polarity of input pwm_force + * @arg 1- active low + * @arg 0- active high + */ +static inline void pwm_config_force_polarity(PWM_Type *pwm_x, bool polarity) +{ + pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_FRCPOL_MASK)) | PWM_GCR_FRCPOL_SET(polarity); +} + +/** + * @brief config the force effective time + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] timing @ref pwm_force_cmd_timing_t + */ +static inline void pwm_config_force_cmd_timing(PWM_Type *pwm_x, pwm_force_cmd_timing_t timing) +{ + pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_FRCTIME_MASK)) | PWM_GCR_FRCTIME_SET(timing); +} + +/** + * @brief enable pwm sw force output + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index pwm cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + */ +static inline void pwm_enable_pwm_sw_force_output(PWM_Type *pwm_x, uint8_t index) +{ + pwm_x->PWMCFG[index] |= PWM_PWMCFG_OEN_MASK | PWM_PWMCFG_FRCSRCSEL_MASK + | PWM_PWMCFG_FRCSHDWUPT_SET(pwm_shadow_register_update_on_modify); +} + +/** + * @brief disable pwm sw force output + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index pwm cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + */ +static inline void pwm_disable_pwm_sw_force_output(PWM_Type *pwm_x, uint8_t index) +{ + pwm_x->PWMCFG[index] &= ~PWM_PWMCFG_FRCSRCSEL_MASK; +} + +/** + * @brief config PWM channel configure registe + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index pwm channel index (0..(PWM_SOC_PWM_MAX_COUNT-1)) + * @param[in] config @ref pwm_config_t + * @param[in] enable_pair_mode enable pair mode + * @arg 1- PWM output is in pair mode + * @arg 0- PWM output is in indepandent mode + */ +static inline void pwm_config_pwm(PWM_Type *pwm_x, uint8_t index, + pwm_config_t *config, bool enable_pair_mode) +{ + pwm_x->PWMCFG[index] = PWM_PWMCFG_OEN_SET(config->enable_output) + | PWM_PWMCFG_FRCSHDWUPT_SET(config->update_trigger) + | PWM_PWMCFG_FAULTMODE_SET(config->fault_mode) + | PWM_PWMCFG_FAULTRECTIME_SET(config->fault_recovery_trigger) + | PWM_PWMCFG_FRCSRCSEL_SET(config->force_source) + | PWM_PWMCFG_PAIR_SET(enable_pair_mode) + | PWM_PWMCFG_DEADAREA_SET(config->dead_zone_in_half_cycle); +} + +/** + * @brief pwm load cmp shadow on match + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + * @param[in] config @ref pwm_cmp_config_t + * @retval status_invalid_argument or status_success + */ +hpm_stat_t pwm_load_cmp_shadow_on_match(PWM_Type *pwm_x, + uint8_t index, + pwm_cmp_config_t *config); + +/** + * @brief pwm get captured count + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[out] buf count value + * @param[in] counter @ref pwm_counter_type_t + * @param[in] start_index start capture index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + * @param[in] num capture num (1..PWM_SOC_CMP_MAX_COUNT) + */ +void pwm_get_captured_count(PWM_Type *pwm_x, uint32_t *buf, pwm_counter_type_t counter, uint8_t start_index, uint8_t num); + +/** + * @brief get default cmp config + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[out] config @ref pwm_cmp_config_t + */ +void pwm_get_default_cmp_config(PWM_Type *pwm_x, pwm_cmp_config_t *config); + +/** + * @brief get default output channel config + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[out] config @ref pwm_output_channel_t + */ +void pwm_get_default_output_channel_config(PWM_Type *pwm_x, pwm_output_channel_t *config); + +/** + * @brief get default pwm config + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[out] config @ref pwm_config_t + */ +void pwm_get_default_pwm_config(PWM_Type *pwm_x, pwm_config_t *config); + +/** + * @brief get default pwm pair config + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[out] config @ref pwm_pair_config_t + */ +void pwm_get_default_pwm_pair_config(PWM_Type *pwm_x, pwm_pair_config_t *config); + +/** + * @brief setup waveform + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] pwm_index pwm channel index (0..(PWM_SOC_PWM_MAX_COUNT-1)) + * @param[in] pwm_config @ref pwm_config_t + * @param[in] cmp_start_index pwm cmp index (0..(PWM_SOC_PWM_MAX_COUNT-1)) + * @param[in] cmp @ref pwm_cmp_config_t + * @param[in] cmp_num cmp num (1..PWM_SOC_CMP_MAX_COUNT), cmp[cmp_num-1] must not overflow + * @retval hpm_stat_t + */ +hpm_stat_t pwm_setup_waveform(PWM_Type *pwm_x, + uint8_t pwm_index, pwm_config_t *pwm_config, + uint8_t cmp_start_index, pwm_cmp_config_t *cmp, uint8_t cmp_num); +/** + * @brief setup pwm waveform in pair + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] pwm_index pwm channel index (0..(PWM_SOC_PWM_MAX_COUNT-1)) + * @param[in] pwm_pair_config @ref pwm_pair_config_t + * @param[in] cmp_start_index pwm cmp index (0..(PWM_SOC_PWM_MAX_COUNT-1)) + * @param[in] cmp @ref pwm_cmp_config_t + * @param[in] cmp_num cmp num (1..PWM_SOC_CMP_MAX_COUNT), cmp[cmp_num-1] must not overflow + * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success + */ +hpm_stat_t pwm_setup_waveform_in_pair(PWM_Type *pwm_x, + uint8_t pwm_index, pwm_pair_config_t *pwm_pair_config, + uint8_t cmp_start_index, pwm_cmp_config_t *cmp, uint8_t cmp_num); + +/** + * @brief update raw compare value for edge aligned waveform + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] cmp_index index of cmp to be adjusted (0..(PWM_SOC_PWM_MAX_COUNT-1)) + * @param[in] target_cmp target compare value + * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success + */ +hpm_stat_t pwm_update_raw_cmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, + uint32_t target_cmp); + +/** + * @brief update raw compare value for central aligned waveform + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] cmp1_index index of cmp1 to be adjusted (cmp1_index must even number) + * @param[in] cmp2_index index of cmp2 to be adjusted (cmp2_index must odd number) + * @param[in] target_cmp1 target compare value for cmp1 + * @param[in] target_cmp2 target compare value for cmp2 + * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success cmp1_index + */ +hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, + uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_PWM_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h new file mode 100644 index 0000000000..098210d5e0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_QEI_DRV_H +#define HPM_QEI_DRV_H + +#include "hpm_common.h" +#include "hpm_qei_regs.h" +/** + * @brief QEI driver APIs + * @defgroup qei_interface QEI driver APIs + * @ingroup io_interfaces + * @{ + * + */ +#define QEI_EVENT_WDOG_FLAG_MASK (1U << 31) /**< watchdog flag */ +#define QEI_EVENT_HOME_FLAG_MASK (1U << 30) /**< home flag */ +#define QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK (1U << 29) /**< postion compare match flag */ +#define QEI_EVENT_Z_PHASE_FLAG_MASK (1U << 28) /**< z input flag */ + +/** + * @brief counting mode of Z-phase counter + * + */ +typedef enum qei_z_count_inc_mode { + qei_z_count_inc_on_z_input_assert = 0, /**< zcnt will increment or decrement when Z input assert */ + qei_z_count_inc_on_phase_count_max = 1, /**< zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 */ +} qei_z_count_inc_mode_t; + +/** + * @brief motor rotation direction + * + */ +typedef enum qei_rotation_dir_cmp { + qei_rotation_dir_cmp_positive = 0, /**< position compare need positive rotation */ + qei_rotation_dir_cmp_negative = 1, /**< position compare need negative rotation */ + qei_rotation_dir_cmp_ignore = 2, /**< ignore */ +} qei_rotation_dir_cmp_t; + +/** + * @brief counter type + * + */ +typedef enum qei_counter_type { + qei_counter_type_z = 0, /**< Z counter */ + qei_counter_type_phase = 1, /**< Phase counter */ + qei_counter_type_speed = 2, /**< Speed counter */ + qei_counter_type_timer = 3, /**< Timer counter */ +} qei_counter_type_t; + +/** + * @brief qei work mode + * + */ +typedef enum qei_work_mode { + qei_work_mode_abz = 0, /**< Orthogonal decoder mode */ + qei_work_mode_pd = 1, /**< Directional (PD) mode */ + qei_work_mode_ud = 2, /**< Up and Down (UD) mode */ +} qei_work_mode_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable qei watchdog + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + */ +static inline void qei_wdog_enable(QEI_Type *qei_x) +{ + qei_x->WDGCFG |= QEI_WDGCFG_WDGEN_MASK; +} + +/** + * @brief disable qei watchdog + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + */ +static inline void qei_wdog_disable(QEI_Type *qei_x) +{ + qei_x->WDGCFG &= ~QEI_WDGCFG_WDGEN_MASK; +} + +/** + * @brief config watchdog + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] timeout watchdog timeout time + * @param[in] enable + * @arg 1 - enable watchdog, You can use the @ref qei_wdog_disable open watchdog + * @arg 0 - disable watchdog, You can use the @ref qei_wdog_enable open watchdog + */ +static inline void qei_wdog_config(QEI_Type *qei_x, uint32_t timeout, bool enable) +{ + qei_x->WDGCFG = QEI_WDGCFG_WDGTO_SET(timeout) | QEI_WDGCFG_WDGEN_SET(enable); +} + +/** + * @brief + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] phase_count maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + * @param[in] mode + * @arg 1 zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 + * @arg 0 zcnt will increment or decrement when Z input assert + * @param[in] z_calibrate 1- phcnt will set to phidx when Z input assert + */ +static inline void qei_phase_config(QEI_Type *qei_x, uint32_t phase_count, + qei_z_count_inc_mode_t mode, bool z_calibrate) +{ + qei_x->PHCFG = QEI_PHCFG_ZCNTCFG_SET(mode) | QEI_PHCFG_PHCALIZ_SET(z_calibrate) + | QEI_PHCFG_PHMAX_SET(phase_count - 1); +} + +/** + * @brief set phase index + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] phase_index phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + */ +static inline void qei_phase_set_index(QEI_Type *qei_x, uint32_t phase_index) +{ + qei_x->PHIDX = QEI_PHIDX_PHIDX_SET(phase_index); +} + +/** + * @brief enable trigger event + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] event_mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline void qei_output_trigger_event_enable(QEI_Type *qei_x, uint32_t event_mask) +{ + qei_x->TRGOEN |= event_mask; +} + +/** + * @brief disable trigger event + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] event_mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline void qei_output_trigger_event_disable(QEI_Type *qei_x, uint32_t event_mask) +{ + qei_x->TRGOEN &= ~event_mask; +} + +/** + * @brief enable load read trigger event + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] event_mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline void qei_load_read_trigger_event_enable(QEI_Type *qei_x, uint32_t event_mask) +{ + qei_x->READEN |= event_mask; +} + +/** + * @brief disable load read trigger event + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] event_mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline void qei_load_read_trigger_event_disable(QEI_Type *qei_x, uint32_t event_mask) +{ + qei_x->READEN &= ~event_mask; +} + +/** + * @brief set zcnt postion compare value + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] cmp zcnt postion compare value + */ +static inline void qei_z_cmp_set(QEI_Type *qei_x, uint32_t cmp) +{ + qei_x->ZCMP = QEI_ZCMP_ZCMP_SET(cmp); +} + +/** + * @brief set spdcnt position compare value + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] cmp spdcnt position compare value + */ +static inline void qei_speed_cmp_set(QEI_Type *qei_x, uint32_t cmp) +{ + qei_x->SPDCMP = QEI_SPDCMP_SPDCMP_SET(cmp); +} + +/** + * @brief set Phase comparator value + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] cmp phcnt position compare value + * @param[in] cmp_z 1- postion compare not include zcnt + * @param[in] rotation_dir @ref qei_rotation_dir_cmp_t + */ +static inline void qei_phase_cmp_set(QEI_Type *qei_x, uint32_t cmp, + bool cmp_z, qei_rotation_dir_cmp_t rotation_dir) +{ + qei_x->PHCMP = QEI_PHCMP_PHCMP_SET(cmp) + | QEI_PHCMP_ZCMPDIS_SET(!cmp_z) + | ((rotation_dir == qei_rotation_dir_cmp_ignore) + ? QEI_PHCMP_DIRCMPDIS_MASK : (QEI_PHCMP_DIRCMP_SET(rotation_dir))); +} + +/** + * @brief clear qei status register + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline void qei_clear_status(QEI_Type *qei_x, uint32_t mask) +{ + qei_x->SR = mask; +} + +/** + * @brief get qei status + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @retval qei status: + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline uint32_t qei_get_status(QEI_Type *qei_x) +{ + return qei_x->SR; +} + +/** + * @brief get qei bit status + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + * @retval true or false + */ +static inline bool qei_get_bit_status(QEI_Type *qei_x, uint32_t mask) +{ + if ((qei_x->SR & mask) == mask) { + return true; + } + else{ + return false; + } +} + +/** + * @brief enable qei irq + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline void qei_irq_enable(QEI_Type *qei_x, uint32_t mask) +{ + qei_x->IRQEN |= mask; +} + +/** + * @brief disable qei irq + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline void qei_irq_disable(QEI_Type *qei_x, uint32_t mask) +{ + qei_x->IRQEN &= ~mask; +} + +/** + * @brief enable dma request + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline void qei_dma_request_enable(QEI_Type *qei_x, uint32_t mask) +{ + qei_x->DMAEN |= mask; +} + +/** + * @brief disable qei dma + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] mask + * @arg @ref QEI_EVENT_WDOG_FLAG_MASK + * @arg @ref QEI_EVENT_HOME_FLAG_MASK + * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK + * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK + */ +static inline void qei_dma_request_disable(QEI_Type *qei_x, uint32_t mask) +{ + qei_x->DMAEN &= ~mask; +} + +/** + * @brief get current counter value + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] type @ref qei_counter_type_t + * @retval counter value + */ +static inline uint32_t qei_get_current_count(QEI_Type *qei_x, + qei_counter_type_t type) +{ + return *(&qei_x->COUNT[QEI_COUNT_CURRENT].Z + type); +} + +/** + * @brief get read event count value + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] type @ref qei_counter_type_t + * @retval counter value + */ +static inline uint32_t qei_get_count_on_read_event(QEI_Type *qei_x, + qei_counter_type_t type) +{ + return *(&(qei_x->COUNT[QEI_COUNT_READ].Z) + type); +} + +/** + * @brief read the value of each phase snapshot 0 counter + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] type @ref qei_counter_type_t + * @retval counter value + */ +static inline uint32_t qei_get_count_on_snap0_event(QEI_Type *qei_x, + qei_counter_type_t type) +{ + return *(&qei_x->COUNT[QEI_COUNT_SNAP0].Z + type); +} + +/** + * @brief read the value of each phase snapshot 1 counter + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] type @ref qei_counter_type_t + * @retval counter value + */ +static inline uint32_t qei_get_count_on_snap1_event(QEI_Type *qei_x, + qei_counter_type_t type) +{ + return *(&qei_x->COUNT[QEI_COUNT_SNAP1].Z + type); +} + +/** + * @brief get speed history + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] hist_index @ref QEI_SPDHIS_SPDHIS1 ,QEI_SPDHIS_SPDHISx(x=0...n) + * @retval speed history value + * @arg 0 - hist_index out of range + * @arg counter value + */ +static inline uint32_t qei_get_speed_history(QEI_Type *qei_x, uint8_t hist_index) +{ + if (hist_index > QEI_SPDHIS_SPDHIS3) { + return 0; + } + return QEI_SPDHIS_SPDHIS0_GET(qei_x->SPDHIS[hist_index]); +} + +/** + * @brief load phcnt, zcnt, spdcnt and tmrcnt into their read registers + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + */ +static inline void qei_load_counter_to_read_registers(QEI_Type *qei_x) +{ + qei_x->CR |= QEI_CR_READ_MASK; +} + +/** + * @brief reset spdcnt/phcnt/zcnt + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] counter_mask + * @arg 1 reset zcnt when H assert + * @arg (1<<1) reset phcnt when H assert + * @arg (1<<2) reset spdcnt when H assert + */ +static inline void qei_reset_counter_on_h_assert(QEI_Type *qei_x, + uint32_t counter_mask) +{ + qei_x->CR |= counter_mask << 16; +} + +/** + * @brief pause spdcnt when PAUSE assert + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] counter_mask + * @arg 1 pause spdcnt when PAUSE assert + * @arg (1<<1) pause spdcnt when PAUSE assert + * @arg (1<<2) pause spdcnt when PAUSE assert + */ +static inline void qei_pause_counter_on_pause(QEI_Type *qei_x, + uint32_t counter_mask) +{ + qei_x->CR |= counter_mask << 12; +} + +/** + * @brief load phcnt, zcnt, spdcnt and tmrcnt into their snap registers + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + */ +static inline void qei_snap_enable(QEI_Type *qei_x) +{ + qei_x->CR |= QEI_CR_SNAPEN_MASK; +} + +/** + * @brief disable snap + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + */ +static inline void qei_snap_disable(QEI_Type *qei_x) +{ + qei_x->CR &= ~QEI_CR_SNAPEN_MASK; +} + +/** + * @brief reset zcnt, spdcnt and tmrcnt to 0 + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + */ +static inline void qei_counter_reset_assert(QEI_Type *qei_x) +{ + qei_x->CR |= QEI_CR_RSTCNT_MASK; +} + +/** + * @brief qei counter reset release + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + */ +static inline void qei_counter_reset_release(QEI_Type *qei_x) +{ + qei_x->CR &= ~QEI_CR_RSTCNT_MASK; +} + +/** + * @brief set work mode + * + * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) + * @param[in] mode @ref qei_work_mode_t + */ +static inline void qei_set_work_mode(QEI_Type *qei_x, qei_work_mode_t mode) +{ + qei_x->CR = (qei_x->CR & ~QEI_CR_ENCTYP_MASK) | QEI_CR_ENCTYP_SET(mode); +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_QEI_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h new file mode 100644 index 0000000000..665a228b97 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_RNG_DRV_H +#define HPM_RNG_DRV_H +#include "hpm_common.h" +#include "hpm_rng_regs.h" + +enum { + status_rng_busy = MAKE_STATUS(status_group_rng, 1), + status_rng_selftest_failed = MAKE_STATUS(status_group_rng, 2), + status_rng_not_available = MAKE_STATUS(status_group_rng, 3), +}; + +#ifdef __cplusplus +extern "C" { +#endif + +hpm_stat_t rng_init(RNG_Type *ptr); + +hpm_stat_t rng_rand_wait(RNG_Type *ptr, void *buf, uint32_t count_in_byte); + +hpm_stat_t rng_rand_no_wait(RNG_Type *ptr, void *buf, uint32_t count_in_byte); + +hpm_stat_t rng_feed_rand_to_sdp(RNG_Type *ptr); + +hpm_stat_t rng_run_selftest(RNG_Type *ptr); + +static inline void rng_sw_reset(RNG_Type *ptr) +{ + ptr->CMD |= RNG_CMD_SFTRST_MASK; +} + +static inline void rng_clear_interrupt_error(RNG_Type *ptr) +{ + ptr->CMD |= RNG_CMD_CLRERR_MASK; +} + +static inline void rng_clear_interrupt(RNG_Type *ptr) +{ + ptr->CMD |= RNG_CMD_CLRINT_MASK; +} + +static inline bool rng_is_busy(RNG_Type *ptr) +{ + return ((ptr->STA & RNG_STA_BUSY_MASK) == RNG_STA_BUSY_MASK) ? true : false; +} + +static inline bool rng_need_reseed(RNG_Type *ptr) +{ + return ((ptr->STA & RNG_STA_RSDREQ_MASK) == RNG_STA_RSDREQ_MASK) ? true : false; +} + +#ifdef __cplusplus +} +#endif +#endif /* HPM_RNG_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h new file mode 100644 index 0000000000..7a4514caa8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ROMAPI_XPI_DEF_H +#define HPM_ROMAPI_XPI_DEF_H + +/** + * @brief XPI ROM APIs + * @defgroup xpi_interface XPI driver APIs + * @{ + */ + +#include "hpm_common.h" + +/** + * @brief XPI_Type definitions for + * @note For compatibility + */ +typedef uint32_t XPI_Type; + +/** + * @brief XPI Read Sample Clock source options + */ +typedef enum { + xpi_rxclksrc_internal_loopback = 0, /**< Internal loopback */ + xpi_rxclksrc_dqs_loopback = 1, /**< Loopback from DQS pad */ + xpi_rxclksrc_external_dqs = 3, /**< Read is driven by External DQS pad */ +} xpi_rxclksrc_type_t; + + +/** + * @brief XPI pad definitions + */ +#define XPI_1PAD (0U) /**< Single pad */ +#define XPI_2PADS (1U) /**< Dual pads */ +#define XPI_4PADS (2U) /**< Quad pads */ +#define XPI_8PADS (3U) /**< Octal pads */ + +/** + * @brief XPI IO pin group options + */ +typedef enum { + xpi_io_1st_group, /**< First/Primary group */ + xpi_io_2nd_group, /**< Second/Secondary group */ +} xpi_io_group_t; + +/** + * @brief XPI Transfer Channel type definitions + */ +typedef enum { + xpi_xfer_channel_a1, /**< The address is based on the device connected to Channel A1 */ + xpi_xfer_channel_a2, /**< The address is based on the device connected to Channel A2 */ + xpi_xfer_channel_b1, /**< The address is based on the device connected to Channel B1 */ + xpi_xfer_channel_b2, /**< The address is based on the device connected to Channel B2 */ + xpi_xfer_channel_auto, /**< The channel is auto determined */ +} xpi_xfer_channel_t; + +/** + * @brief XPI Channel defitions + */ +typedef enum { + xpi_channel_a1, /**< Port: Channel A1 */ + xpi_channel_a2, /**< Port: Channel A2 */ + xpi_channel_b1, /**< Port: Channel B1 */ + xpi_channel_b2, /**< Port: Channel B2 */ +} xpi_channel_t; + +/** + * @brief XPI APB Transfer type + */ +typedef enum { + xpi_apb_xfer_type_cmd, /**< APB Command Type: Command only */ + xpi_apb_xfer_type_config, /**< APB Command Type: Configuration */ + xpi_apb_xfer_type_read, /**< APB Command Type: Read */ + xpi_apb_xfer_type_write, /**< APB Command Type: Write */ +} xpi_apb_xfer_type_t; + +/** + * @brief XPI Xfer Mode + */ +typedef enum { + xpi_xfer_mode_polling, /**< Transfer mode: Polling */ + xpi_xfer_mode_dma, /**< Transfer mode: DMA */ + xpi_xfer_mode_interrupt, /**< Transfer mode: Interrupt */ +} xpi_xfer_mode_t; + +/** + * @brief XPI Xfer context + */ +typedef struct { + uint32_t addr; /**< device address for XPI transfer */ + uint8_t channel; /**< channel for XPI transfer */ + uint8_t cmd_type; /**< command type for XPI transfer */ + uint8_t seq_idx; /**< Sequence index for XPI transfer */ + uint8_t seq_num; /**< Sequence number for XPI transfer */ + uint32_t *buf; /**< Buffer for XPI transfer */ + uint32_t xfer_size; /**< Transfer size in bytes */ +} xpi_xfer_ctx_t; + +/** + * @brief XPI instruction sequence + */ +typedef struct { + uint32_t entry[4]; +} xpi_instr_seq_t; + +/** + * @brief XPI Phase definitions + */ +#define XPI_PHASE_STOP (0x00U) /**< Phase: Stop */ +#define XPI_PHASE_CMD_SDR (0x01U) /**< Phase: Send CMD in SDR mode */ +#define XPI_PHASE_RADDR_SDR (0x02U) /**< Phase: Send Row Address in SDR Mode */ +#define XPI_PHASE_CADDR_SDR (0x03U) /**< Phase: Send Column Address in SDR Mode */ +#define XPI_PHASE_MODE4_SDR (0x06U) /**< Phase: Send Mode 4 in SDR Mode */ +#define XPI_PHASE_MODE8_SDR (0x07U) /**< Phase: Send Mode 8 in SDR Mode */ +#define XPI_PHASE_WRITE_SDR (0x08U) /**< Phase: Write data in SDR Mode */ +#define XPI_PHASE_READ_SDR (0x09U) /**< Phase: Read data in SDR Mode */ +#define XPI_PHASE_DUMMY_SDR (0X0CU) /**< Phase: Send Dummy in SDR Mode */ +#define XPI_PHASE_DUMMY_RWDS_SDR (0x0DU) /**< Phase: Send Dummy RWDS in SDR Mode */ + +#define XPI_PHASE_CMD_DDR (0x21U) /**< Phase: Send CMD in DDR Mode */ +#define XPI_PHASE_RADDR_DDR (0x22U) /**< Phase: Send Raw Address in DDR Mode */ +#define XPI_PHASE_CADDR_DDR (0x23U) /**< Phase: Send Column address in DDR Mode */ +#define XPI_PHASE_MODE4_DDR (0x26U) /**< Phase: Send Mode 4 in DDR Mode */ +#define XPI_PHASE_MODE8_DDR (0x27U) /**< Phase: Send Mode 8 in DDR Mode */ +#define XPI_PHASE_WRITE_DDR (0x28U) /**< Phase: Write data in DDR Mode */ +#define XPI_PHASE_READ_DDR (0x29U) /**< Phase: Read data in SDR Mode */ +#define XPI_PHASE_DUMMY_DDR (0x2CU) /**< Phase: Send DUMMY in DDR Mode */ +#define XPI_PHASE_DUMMY_RWDS_DDR (0x2DU) /**< Phase: Send DUMMY RWDS in DDR Mode */ + +/** + * @brief XPI API command error codes + */ +enum { + status_xpi_apb_jump_on_cs = MAKE_STATUS(status_group_xpi, 1), + status_xpi_apb_unknown_inst = MAKE_STATUS(status_group_xpi, 2), + status_xpi_apb_dummy_sdr_in_ddr_seq = MAKE_STATUS(status_group_xpi, 3), + status_xpi_apb_dummy_ddr_in_sdr_seq = MAKE_STATUS(status_group_xpi, 4), + status_xpi_apb_exceed_addr_range = MAKE_STATUS(status_group_xpi, 5), + status_xpi_apb_seq_timeout = MAKE_STATUS(status_group_xpi, 6), + status_xpi_apb_cross_boundary = MAKE_STATUS(status_group_xpi, 7), +}; + +/** + * @brief Delay line definitions + */ +enum { + xpi_dll_half_cycle = 0xFU, + xpi_dll_quarter_cycle = 0x7U, + xpi_dll_sdr_default_cycle = xpi_dll_half_cycle, + xpi_dll_ddr_default_cycle = xpi_dll_quarter_cycle, +}; + +/** + * @brief XPI configuration structure + */ +typedef struct { + uint8_t rxclk_src; /**< Read sample clock source */ + uint8_t reserved0[7]; /**< Reserved */ + uint8_t tx_watermark_in_dwords; /**< Tx watermark in double words */ + uint8_t rx_watermark_in_dwords; /**< Rx watermark in double words */ + uint8_t enable_differential_clk; /**< Enable differential clock */ + uint8_t reserved1[5]; /**< Reserved */ + uint32_t access_flags; /**< Access flags */ +}xpi_config_t; + +/** + * @brief XPI Device Configuration structure + */ +typedef struct { + uint32_t size_in_kbytes; /**< Device size in kbytes */ + uint32_t serial_root_clk_freq; /**< XPI serial root clock frequency */ + + uint8_t enable_write_mask; /**< Enable write mask, typically for PSRAM/HyperRAM */ + uint8_t data_valid_time; /**< Data valid time, Unit 0.1ns */ + uint8_t reserved0[2]; + + uint8_t cs_hold_time; /**< CS hold time, cycles in terms of FLASH clock */ + uint8_t cs_setup_time; /**< CS setup time, cycles in terms of FLASH clock */ + uint16_t cs_interval; /**< CS interval, cycles in terms of FLASH clock */ + + uint8_t reserved1; + uint8_t column_addr_size; /**< Column address bits */ + uint8_t enable_word_address; /**< Enable word address, for HyperFLASH/HyperRAM */ + uint8_t dly_target; /**< Delay target */ + + uint8_t ahb_write_seq_idx; /**< AHB write sequence index */ + uint8_t ahb_write_seq_num; /**< AHB write sequence number */ + uint8_t ahb_read_seq_idx; /**< AHB read sequence index */ + uint8_t ahb_read_seq_num; /**< AHB read sequence number */ + + uint8_t ahb_write_wait_interval; /**< AHB write wait interval, in terms of FLASH clock */ + uint8_t reserved2[3]; +} xpi_device_config_t; + +/** + * @brief SUB Instruction + * @param [in] phase Phase + * @param [in] pad Pad for Phase + * @param [in] op Operand for Phase + */ +#define SUB_INSTR(phase, pad, op) ((uint32_t)(((uint16_t)(phase) << 10) | ((uint16_t)(pad) << 8) | ((uint16_t)(op)))) +/** + * @brief Generate a single word INSTRUCTION sequence word + * @note Here intentionally use the MACRO because when the arguments are constant value, the compiler + * can generate the const entry word during pre-processing + */ +#define XPI_INSTR_SEQ(phase0, pad0, op0, phase1, pad1, op1) (SUB_INSTR(phase0, pad0, op0) | (SUB_INSTR(phase1, pad1, op1)<<16)) + + +/** + * @} + */ + +#endif /* HPM_ROMAPI_XPI_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h new file mode 100644 index 0000000000..b9af512fad --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ROMAPI_XPI_NOR_DEF_H +#define HPM_ROMAPI_XPI_NOR_DEF_H + +/** + * @brief XPI NOR ROM APIs + * @defgroup xpi_nor_interface XPI NOR driver APIs + * @ingroup romapi_interfaces + * @{ + */ + + +#include "hpm_common.h" +#include "hpm_romapi_xpi_def.h" + +#define XPI_NOR_CFG_TAG 0x524f4E58U /**< ASCII: "XNOR" */ + +/** + * @brief XPI NOR properties + */ +enum { + xpi_nor_property_total_size, /**< Total size in bytes */ + xpi_nor_property_page_size, /**< Page size in bytes */ + xpi_nor_property_sector_size, /** + +/** + * @brief RTC alarm configuration + */ +typedef struct { + uint16_t index; /**< RTC alarm index */ + uint16_t type; /**< Alarm type */ + time_t period; /**< ALarm period */ +} rtc_alarm_config_t; + +/** + * @brief RTC Alarm type + */ +#define RTC_ALARM_TYPE_ONE_SHOT (0U) /**< The RTC alarm will be triggered only once */ +#define RTC_ALARM_TYPE_PERIODIC (1U) /**< The RTC alarm will be triggered periodically */ + +/** + * @brief Typical RTC alarm period definitions + */ +#define ALARM_PERIOD_ONE_SEC (1UL) /**< Alarm period: 1 second */ +#define ALARM_PERIOD_ONE_MIN (60UL) /**< Alarm period: 1 minute */ +#define ALARM_PERIOD_ONE_HOUR (3600U) /**< Alarm period: 1 hour */ +#define ALARM_PERIOD_ONE_DAY (ALARM_PERIOD_ONE_HOUR * 24UL) /**< Alarm period: 1 day */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configure the RTC time + * @param [in] base RTC base address + * @param [in] time seconds since 1970.1.1, 0:0:0 + * @retval API execution status status_success or status_invalid_argument + */ +hpm_stat_t rtc_config_time(RTC_Type *base, time_t time); + +/** + * @brief Configure RTC Alarm + * @param [in] base RTC base address + * @param [in] config RTC alarm configuration pointer + * @retval API execution status status_success or status_invalid_arugment; + */ +hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config); + +/** + * @brief Get the time returned by RTC module + * @param [in] base RTC base address + * @retval RTC time + */ +time_t rtc_get_time(RTC_Type *base); + +/** + * @brief Enable RTC alarm interrupt + * @param [in] base RTC base address + * @param [in] index RTC alarm index, valid value is 0 or 1 + * @param [in] enable RTC alarm enable flag + * @arg true Enable specified RTC alarm + * @arg false Disable specified RTC alarm + */ +static inline void rtc_enable_alarm_interrupt(RTC_Type *base, uint32_t index, bool enable) +{ + if (index > 1) { + return; + } + + uint32_t mask = (index == 0U) ? RTC_ALARM_EN_ENABLE0_MASK : RTC_ALARM_EN_ENABLE1_MASK; + + if (enable) { + base->ALARM_EN |= mask; + } + else { + base->ALARM_EN &= ~mask; + } +} + +/** + * @brief Clear RTC alarm flag + * @param [in] base RTC base address + * @param [in] index RTC alarm index, valid value is 0 or 1 + */ +static inline void rtc_clear_alarm_flag(RTC_Type *base, uint32_t index) +{ + if (index > 1) { + return; + } + uint32_t mask = (index == 0U) ? RTC_ALARM_FLAG_ALARM0_MASK : RTC_ALARM_FLAG_ALARM1_MASK; + + base->ALARM_FLAG = mask; +} + +/** + * @brief Check whether RTC alarm flag is set or not + * @param [in] base RTC base address + * @param [in] index RTC alarm index, valid value is 0 or 1 + * @retval RTC alarm flag. Valid value is true or false + */ +static inline bool rtc_is_alarm_flag_asserted(RTC_Type *base, uint32_t index) +{ + if (index > 1) { + return false; + } + uint32_t mask = (index == 0U) ? RTC_ALARM_FLAG_ALARM0_MASK : RTC_ALARM_FLAG_ALARM1_MASK; + + return IS_HPM_BITMASK_SET(base->ALARM_FLAG, mask); +} + + +#ifdef __cplusplus +} +#endif + +/** + * @} + * + */ + +#endif // HPM_RTC_DRV_H diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h new file mode 100644 index 0000000000..319af4f7df --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SDP_DRV_H +#define HPM_SDP_DRV_H + +/** + * @brief SDP driver APIs + * @defgroup sdp_interface SDP driver APIs + * @ingroup sdp_interfaces + * @{ + * + */ + +#include "hpm_common.h" +#include "hpm_sdp_regs.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * @brief SDP AES key bit options + */ +typedef enum { + sdp_aes_keybits_128, /**< 128 bit AES key */ + sdp_aes_keybits_256, /**< 256 bit AES key */ +} sdp_aes_key_bits_t; + +/** + * @brief AES operation option + */ +typedef enum { + sdp_aes_op_encrypt, /**< AES Encrypt operation */ + sdp_aes_op_decrypt, /**< AES Decrypt operation */ +} sdp_aes_op_t; + +/** + * @brief SDP HASH algorithm definitions + */ +typedef enum { + sdp_hash_alg_sha1, /**< SDP SHA1 */ + sdp_hash_alg_crc32, /**< SDP CRC32 */ + sdp_hash_alg_sha256, /**< SDP SHA256 */ + sdp_hash_alg_max = sdp_hash_alg_sha256, +} sdp_hash_alg_t; + +#define HASH_BLOCK_SIZE (64U) /**< Hash block size in bytes */ +#define AES_BLOCK_SIZE (16U) /**< AES block size in bytes */ +#define AES_128_KEY_SIZE (0x10U) /**< AES 128-bit key size in bytes */ +#define AES_256_KEY_SIZE (0x20U) /**< AES 256-bit key size in bytes */ +/** + * @brief Bitfield definitions for the PKT_CTRL + */ +#define SDP_PKT_CTRL_DERSEMA_MASK (1U << 2) +#define SDP_PKT_CTRL_CHAIN_MASK (1U << 3) +#define SDP_PKT_CTRL_HASHINIT_MASK (1U << 4) +#define SDP_PKT_CTRL_HASHFINISH_MASK (1U << 5) +#define SDP_PKT_CTRL_CIPHIV_MASK (1U << 6) + +/** + * @brief SDP packet data structure + */ +typedef struct _sdp_packet_struct { + struct _sdp_packet_struct *next_cmd; + union { + struct { + uint32_t RESERVED0 : 1; + uint32_t PKTINT : 1; /**< Packet interrupt flag */ + uint32_t DCRSEMA : 1; /**< Descrement Semaphore flag */ + uint32_t CHAIN : 1; /**< Chain Packet flag */ + uint32_t HASHINIT : 1; /**< Hash initialize flag */ + uint32_t HASHFINISH : 1; /**< Hash finish flag */ + uint32_t CIPHIV : 1; /**< Cipher IV flag */ + uint32_t RESERVED1 : 17; + uint32_t PKTTAG : 8; /**< Packet tag flag, not used */ + }; + uint32_t PKT_CTRL; /**< Packet control word */ + } pkt_ctrl; + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + uint32_t buf_size; /**< Data buffer size in bytes */ + uint32_t reserved[3]; +} sdp_pkt_struct_t; + +/** + * @brief SDP AES context structure + */ +typedef struct { + uint8_t key_idx; /**< AES key index */ + uint8_t key_bits; /**< AES key bits */ + uint16_t reserved; + sdp_pkt_struct_t sdp_pkt; /**< SDP packet for AES operation */ + uint32_t buf0[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf0 */ + uint32_t buf1[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf1 */ + uint32_t buf2[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf2 */ + uint32_t buf3[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf3 */ +} sdp_aes_ctx_t; + +/** + * @brief SDP DMA context + */ +typedef struct { + sdp_pkt_struct_t sdp_pkt; /**< SDP packet for DMA operation (memset/memcpy) */ +} sdp_dma_ctx_t; + +/** + * @brief SDP HASH context + */ +typedef struct { + sdp_pkt_struct_t sdp_pkt; /**< SDP packet for HASH operation */ + uint32_t internal[64]; /**< internal buffer */ +} sdp_hash_ctx_t; + +/** + * @brief SDP error status definitions + */ +enum { + status_sdp_no_crypto_support = MAKE_STATUS(status_group_sdp, 0), /**< The crypto algorithm is not supported */ + status_sdp_no_hash_support = MAKE_STATUS(status_group_sdp, 1), /**< The hash algorithm is not supported */ + status_sdp_invalid_key_src = MAKE_STATUS(status_group_sdp, 2), /**< Invalid AES key source */ + status_sdp_error_packet = MAKE_STATUS(status_group_sdp, 3), /**< Error packet */ + status_sdp_aes_busy = MAKE_STATUS(status_group_sdp, 4), /**< AES engine is busy */ + status_sdp_hash_busy = MAKE_STATUS(status_group_sdp, 5), /**< HASH engine is busy */ + status_sdp_error_setup = MAKE_STATUS(status_group_sdp, 6), /**< Error setup in SDP IP */ + status_sdp_error_src = MAKE_STATUS(status_group_sdp, 7), /**< Error source address */ + status_sdp_error_dst = MAKE_STATUS(status_group_sdp, 8), /**< Error destination address */ + status_sdp_error_hash = MAKE_STATUS(status_group_sdp, 9), /**< Error Hash digest */ + status_sdp_error_chain = MAKE_STATUS(status_group_sdp, 10), /**< Error packet chain */ + status_sdp_error_invalid_mac, /**< Inavlid Message Athenticaion Code (MAC) */ + +}; + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ + /** + * @brief Initialize the SDP controller + * @param [in] base SDP base address + * @retval API execution status. + */ + hpm_stat_t sdp_init(SDP_Type * base); + + /** + * @brief De-initialize the SDP controller + * @param [in] base SDP base address + * @retval API execution status. + */ + hpm_stat_t sdp_deinit(SDP_Type *base); + + /** + * @brief Set the AES key for the SDP AES operation + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] key AES key + * @param [in] key_bits AES key-bit option + * @param [in] key_idx AES key index + * @retval API execution status. + */ + hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t key_bits, + uint32_t key_idx); + + /** + * @brief Perform the basic AES ECB operation + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] op AES operation option + * @param [in] len AES data length in bytes + * @param [in] in Input buffer + * @param [out] out Output buffer + * @retval API execution status. + */ + hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, + uint8_t *out); + + /** + * @brief Perform the AES CBC operation + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] op AES operation option + * @param [in] length AES data length in bytes + * @param [in] iv Initial vector/nonce + * @param [in] input Input buffer + * @param [out] output Output buffer + * @retval API execution status. + */ + hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, + const uint8_t iv[16], const uint8_t *input, uint8_t *output); + + /** + * @brief Perform the AES-CTR operation + * See NIST Special Publication800-38A for more details + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] nonce_counter AES-CTR nounce/counter + * @param [in] input Input buffer + * @param [out] output Output buffer + * @param [in] length Length of data for AES-CTR operation + * @retval API execution status. + */ + hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_counter, uint8_t *input, + uint8_t *output, uint32_t length); + + /** + * @brief Perform the AES-CCM generate and encrypt + * See NIST Special Publication 800-38C for more details + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [out] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ + hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, + uint8_t *output, uint8_t *tag, uint32_t tag_len); + + /** + * @brief Perform the AES-CCM decrypt and verify + * See NIST Special Publication 800-38C for more details + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [in] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ + hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, + uint8_t *output, const uint8_t *tag, uint32_t tag_len); + + /** + * @brief Perform the DMA accelerated memcpy + * @param [in] base SDP base address + * @param [in] sdp_ctx SDP DMA context + * @param [out] dst Destination address for memcpy operation + * @param [in] src Source address for memcpy operation + * @param [in] length Length of the data to be copied + * @retval API execution status. + */ + hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, const void *src, uint32_t length); + + /** + * @brief Perform the DMA accelerated memset + * @param [in] base SDP base address + * @param [in] sdp_ctx SDP DMA context + * @param [out] dst SDP destination address for memset operation + * @param [in] pattern pattern for memset operation + * @param [in] length length of the memory for memset operation + * @retval API execution status. + */ + hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t pattern, uint32_t length); + + /** + * @brief Initialize the HASH engine + * @param [in] base SDP base address + * @param [in] hash_ctx HASH operation context + * @param [in] alg Hash algorithm + * @retval API execution status. status_success or status_invalid_argument + */ + hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + + /** + * @brief Compute the HASH digest + * @param [in] base SDP base address + * @param [in] hash_ctx HASH operation context + * @param [in] data Data for HASH computing + * @param [in] length Data size for HASH computing + * @retval API execution status. + */ + hpm_stat_t sdp_hash_update(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + + /** + * @brief Finish the HASH calculation and output the digest + * @param [in] base SDP base address + * @param [in] hash_ctx HASH operation context + * @param [out] digest Digest buffer + * @retval API execution status. + */ + hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *digest); + + /** + * @brief Wait until the SDP operation gets done + * @retval API execution status. + */ + hpm_stat_t sdp_wait_done(SDP_Type *base); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_SDP_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h new file mode 100644 index 0000000000..cf8ca7cb8e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h @@ -0,0 +1,1065 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SDXC_DRV_H +#define HPM_SDXC_DRV_H + +/** + * + * @brief SDXC driver APIs + * @defgroup sdxc_interface SDXC driver APIs + * @ingroup sdxc_interfaces + * @{ + * + */ + +#include "hpm_common.h" +#include "hpm_sdxc_regs.h" +#include "hpm_sdxc_soc_drv.h" + + +/** + * @brief Command Response Type Selection + */ +#define SDXC_CMD_RESP_TYPE_NO_RESP (0U) /**< No Response */ +#define SDXC_CMD_RESP_TYPE_RESP_LEN_136 (1U) /**< Response Length 136 */ +#define SDXC_CMD_RESP_TYPE_RESP_LEN_48 (2U) /**< Response Length 48 */ +#define SDXC_CMD_RESP_TYPE_RESP_LEN_48B (3U) /**< Response Length 48; Check busy after response */ + + +#define SDXC_STS_CMD_ERR (SDXC_INT_STAT_CMD_TOUT_ERR_MASK | SDXC_INT_STAT_CMD_CRC_ERR_MASK |\ + SDXC_INT_STAT_CMD_END_BIT_ERR_MASK | SDXC_INT_STAT_CMD_IDX_ERR_MASK | SDXC_INT_STAT_AUTO_CMD_ERR_MASK) +#define SDXC_STS_DATA_ERR (SDXC_INT_STAT_DATA_TOUT_ERR_MASK| SDXC_INT_STAT_DATA_CRC_ERR_MASK | \ + SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) +#define SDXC_STS_CARD_ERR (SDXC_INT_STAT_CARD_REMOVAL_MASK) +#define SDXC_STS_ERROR (SDXC_INT_STAT_ERR_INTERRUPT_MASK | SDXC_STS_CMD_ERR | SDXC_STS_DATA_ERR | SDXC_STS_CARD_ERR) +#define SDXC_STS_CMD_FLAGS (SDXC_STS_CMD_ERR | SDXC_INT_STAT_CMD_COMPLETE_MASK) + +#define SDXC_STS_ALL_FLAGS (SDXC_INT_STAT_ERR_INTERRUPT_MASK | SDXC_INT_STAT_CQE_EVENT_MASK | \ + SDXC_INT_STAT_FX_EVENT_MASK | SDXC_INT_STAT_RE_TUNE_EVENT_MASK | SDXC_INT_STAT_CARD_INTERRUPT_MASK | \ + SDXC_INT_STAT_CARD_REMOVAL_MASK | SDXC_INT_STAT_CARD_INSERTION_MASK | SDXC_INT_STAT_BUF_RD_READY_MASK | \ + SDXC_INT_STAT_BUF_WR_READY_MASK | SDXC_INT_STAT_DMA_INTERRUPT_MASK | SDXC_INT_STAT_BGAP_EVENT_MASK | \ + SDXC_INT_STAT_XFER_COMPLETE_MASK | SDXC_INT_STAT_CMD_COMPLETE_MASK | SDXC_INT_STAT_BOOT_ACK_ERR_MASK | \ + SDXC_INT_STAT_RESP_ERR_MASK | SDXC_INT_STAT_TUNING_ERR_MASK | SDXC_INT_STAT_ADMA_ERR_MASK | \ + SDXC_INT_STAT_AUTO_CMD_ERR_MASK | SDXC_INT_STAT_CUR_LMT_ERR_MASK | SDXC_INT_STAT_DATA_END_BIT_ERR_MASK |\ + SDXC_INT_STAT_DATA_CRC_ERR_MASK | SDXC_INT_STAT_DATA_TOUT_ERR_MASK | SDXC_INT_STAT_CMD_IDX_ERR_MASK |\ + SDXC_INT_STAT_CMD_END_BIT_ERR_MASK | SDXC_INT_STAT_CMD_CRC_ERR_MASK | SDXC_INT_STAT_CMD_TOUT_ERR_MASK) + + +/** + * @brief Software reset flag definitions + */ +typedef enum _sdxc_software_reset { + sdxc_reset_all, /**< Reset both command line and data line */ + sdxc_reset_cmd_line, /**< Reset command line */ + sdxc_reset_data_line, /**< Reset data line */ +} sdxc_sw_reset_type_t; + +/** + * @brief SDXC Bus voltage options + */ +typedef enum _sdxc_bus_voltage_option { + sdxc_bus_voltage_sd_1v8 = 0x01U, + sdxc_bus_voltage_sd_3v3 = 0x00U, + sdxc_bus_voltage_emmc_1v8 = 0x01U, + sdxc_bus_voltage_emmc_3v3 = 0x00U, +} sdxc_bus_voltage_option_t; + +/** + * @brief SDXC wakeup events + */ +typedef enum _sdxc_wakeup_event { + sdxc_wakeup_card_removal = 0x4U, /**< Wake-up event: Card removal */ + sdxc_wakeup_card_insert = 0x02U, /**< Wake-up event: Card insertion */ + sdxc_wakeup_card_interrupt = 0x01U, /**< Wake-up event: Card interrupt */ +} sdxc_wakeup_event_t; + +/** + * @brief SDXC DMA types + */ +typedef enum _sdxc_dma_type { + sdxc_dmasel_sdma = 0U, /**< SDXC DMA type: SDMA */ + sdxc_dmasel_adma2 = 2U, /**< SDXC DMA type: ADMA2 */ + sdxc_dmasel_adma2_or_3 = 3U, /**< SDXC DMA type: ADMA2 or ADMA3 */ + sdxc_dmasel_nodma = 0xFU, +} sdxc_dma_type_t; + +/** + * @brief SDXC Bus width options + */ +typedef enum _sdxc_bus_width { + sdxc_bus_width_1bit, /**< SDXC bus width: 1 bit */ + sdxc_bus_width_4bit, /**< SDXC bus width: 4 bits */ + sdxc_bus_width_8bit, /**< SDXC bus width: 8 bits */ +} sdxc_bus_width_t; + +/** + * @brief SDXC Speed mode options + */ +typedef enum _sdxc_speed_mode { + sdxc_sd_speed_sdr12 = 0U, /**< SDXC speed: SDR12 */ + sdxc_sd_speed_sdr25 = 1U, /**< SDXC speed: SDR25 */ + sdxc_sd_speed_sdr50 = 2U, /**< SDXC speed: SDR50 */ + sdxc_sd_speed_sdr104 = 3U, /**< SDXC speed: SDR104 */ + sdxc_sd_speed_ddr50 = 4U, /**< SDXC speed: DDR50 */ + sdxc_sd_speed_normal = sdxc_sd_speed_sdr12, /**< SDXC speed: Normal Speed */ + sdxc_sd_speed_high = sdxc_sd_speed_sdr25, /**< SDXC speed: High Speed */ + + sdxc_emmc_speed_legacy = 0U, /**< SDXC speed: MMC legacy speed */ + sdxc_emmc_speed_high_speed_sdr = 1U, /**< SDXC speed: MMC High Speed */ + sdxc_emmc_speed_hs200 = 3U, /**< SDXC speed: MMC HS200 speed */ + sdxc_emmc_speed_high_speed_ddr = 4U, /**< SDXC speed: MMC High Speed DDR */ + sdxc_emmc_speed_hs400 = 7U, /**< SDXC speed: MMC HS400 */ + + sdxc_sdmmc_speed_card_init = 0x10, + +} sdxc_speed_mode_t; + +/** + * @brief SDXC auto command types + */ +typedef enum _sdxc_auto_cmd_sel { + sdxc_auto_cmd_disabled = 0U, /**< Auto Command type: Disabled */ + sdxc_auto_cmd12_enabled = 1U, /**< Auto Command type: CMD12 enabled */ + sdxc_auto_cmd23_enabled = 2U, /**< Auto Command type: CMD23 enabled */ + sdxc_auto_cmd_auto_select = 3U, /**< Auto Command type: AUto selected */ +} sdxc_auto_cmd_sel_t; + +/** + * @brief SDXC trnasfer direction options + */ +typedef enum _sdxc_xfer_direction { + sdxc_xfer_dir_write, + sdxc_xfer_dir_read, +} sdxc_xfer_direction_t; + +/** + * @brief SDXC Command types + */ +typedef enum _sdxc_command_type { + sdxc_cmd_type_normal_cmd = 0U, + sdxc_cmd_type_suspend_cmd, + sdxc_cmd_tye_resume_cmd, + sdxc_cmd_type_abort_cmd, + sdxc_cmd_type_empty, + +} sdxc_command_type_t; + +/** + * @brief Command Type + */ +#define SDXC_CMD_TYPE_NORMAL (0UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) +#define SDXC_CMD_TYPE_SUSPEND (1UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) +#define SDXC_CMD_TYPE_RESUME (2UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) +#define SDXC_CMD_TYPE_ABORT (3UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) + +/** + * @brief SDXC boot mode types + */ +typedef enum _sdxc_boot_mode { + sdxc_boot_mode_normal = 0, + sdxc_boot_mode_alternative +} sdxc_boot_mode_t; + +/** + * @brief SDXC response types + */ +typedef enum _sdxc_response_type { + sdxc_response_type_no_resp, + sdxc_response_type_resp_len_136bit, + sdxc_response_type_resp_len_48bit, + sdxc_response_type_resp_len_48bit_check_busy, +} sdxc_response_type_t; + +#define SDXC_CMD_RESP_NO_RESPONSE (0UL << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) +#define SDXC_CMD_RESP_LEN_136 (1UL << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) +#define SDXC_CMD_RESP_LEN_48 (2UL << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) +#define SDXC_CMD_RESP_LEN_48B (3UL << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) + +#define SDXC_CMD_CMD_IS_MAIN_CMD (0U) +#define SDXC_CMD_CMD_IS_SUB_CMD (SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) + +#define SDXC_CMD_CMD_CRC_CHK_EN (SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) +#define SDXC_CMD_CMD_CRC_CHK_DIS (0U) + +#define SDXC_CMD_CMD_IDX_CHK_EN (SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) +#define SDXC_CMD_CMD_IDX_CHK_DIS (0U) + +#define SDXC_CMD_DATA_PRESENT (SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) +#define SDXC_CMD_DATA_NO_PRESENT (0U) + +#define SDXC_CMD_CMD_TYPE_NORMAL (0U) +#define SDXC_CMD_CMD_TYPE_SUSPEND (1UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) +#define SDXC_CMD_CMD_TYPE_RESUME (2U << SDXC_CMD_XFER_CMD_TYPE_SHIFT) +#define SDXC_CMD_CMD_TYPE_ABORT (3U << SDXC_CMD_XFER_CMD_TYPE_SHIFT) + +/** + * @brief SDXC error codes + */ +enum { + status_sdxc_busy = MAKE_STATUS(status_group_sdxc, 0), /**< SDXC is busy */ + status_sdxc_error = MAKE_STATUS(status_group_sdxc, 1), /**< SDXC error */ + status_sdxc_send_cmd_failed = MAKE_STATUS(status_group_sdxc, 2), /**< SDXC command failed */ + status_sdxc_cmd_timeout_error = MAKE_STATUS(status_group_sdxc, 3), /**< SDXC command timed out */ + status_sdxc_cmd_crc_error = MAKE_STATUS(status_group_sdxc, 4), /**< SDXC command CRC error */ + status_sdxc_cmd_end_bit_error = MAKE_STATUS(status_group_sdxc, 5), /**< SDXC command end bit error */ + status_sdxc_cmd_index_error = MAKE_STATUS(status_group_sdxc, 6), /**< SDXC command index error */ + status_sdxc_data_timeout_error = MAKE_STATUS(status_group_sdxc, 7), /**< SDXC data timeout error */ + status_sdxc_data_crc_error = MAKE_STATUS(status_group_sdxc, 8), /**< SDXC data CRC error */ + status_sdxc_data_end_bit_error = MAKE_STATUS(status_group_sdxc, 9), /**< SDXC data end bit error */ + status_sdxc_auto_cmd_error = MAKE_STATUS(status_group_sdxc, 10), /**< SDXC auto command error */ + status_sdxc_adma_error = MAKE_STATUS(status_group_sdxc, 11), /**< SDXC ADMA error */ + status_sdxc_tuning_error = MAKE_STATUS(status_group_sdxc, 12), /**< SDXC tuning error */ + status_sdxc_response_error = MAKE_STATUS(status_group_sdxc, 13), /**< SDXC response error */ + status_sdxc_boot_ack_error = MAKE_STATUS(status_group_sdxc, 14), /**< SDXC boot ack error */ + status_sdxc_retuning_request = MAKE_STATUS(status_group_sdxc, 15), /**< SDXC retuning request */ + status_sdxc_autocmd_cmd12_not_exec = MAKE_STATUS(status_group_sdxc, 16), /**< SDXC Auto CMD12 command not executed */ + status_sdxc_autocmd_cmd_timeout_error = MAKE_STATUS(status_group_sdxc, 17), /**< SDXC Auto CMD timed out */ + status_sdxc_autocmd_cmd_crc_error = MAKE_STATUS(status_group_sdxc, 18), /**< SDXC Auto CMD crc error */ + status_sdxc_autocmd_end_bit_error = MAKE_STATUS(status_group_sdxc, 19), /**< SDXC Auto CMD end bit error */ + status_sdxc_autocmd_cmd_index_error = MAKE_STATUS(status_group_sdxc, 20), /**< SDXC Auto CMD index error */ + status_sdxc_autocmd_cmd_response_error = MAKE_STATUS(status_group_sdxc, 21), /**< SDXC Auto CMD response error */ + status_sdxc_autocmd_cmd_not_issued_auto_cmd12 = MAKE_STATUS(status_group_sdxc, 22), /**< SDXC Auto CMD not issued auto CMD12 */ + status_sdxc_unsupported = MAKE_STATUS(status_group_sdxc, 23), /**< SDXC unsupported operation */ + status_sdxc_transfer_data_completed = MAKE_STATUS(status_group_sdxc, 24), /**< SDXC transfer data completed */ + status_sdxc_send_cmd_successful = MAKE_STATUS(status_group_sdxc, 25), /**< SDXC send command succedded */ + status_sdxc_transfer_dma_completed = MAKE_STATUS(status_group_sdxc, 26), /**< SDXC transfer DMA completed */ + status_sdxc_transfer_data_failed = MAKE_STATUS(status_group_sdxc, 27), /**< SDXC transfer data failed */ + status_sdxc_dma_addr_unaligned = MAKE_STATUS(status_group_sdxc, 28), /**< SDXC DMA address unaligned */ + status_sdxc_tuning_failed = MAKE_STATUS(status_group_sdxc, 29), /**< SDXC tuning failed */ + status_sdxc_card_removed = MAKE_STATUS(status_group_sdxc, 30), /**< SDXC Card removed */ + status_sdxc_non_recoverable_error = MAKE_STATUS(status_group_sdxc, 30), /**< SDXC non-recoverable error */ + status_sdxc_recoverable_error = MAKE_STATUS(status_group_sdxc, 31), /**< SDXC recoverable error */ +}; + +/** + * @brief SDXC Capacities + */ +typedef struct { + union { + struct { + uint32_t tout_clk_freq: 6; /**< Timeout clock frequency */ + uint32_t : 1; + uint32_t tout_clk_unit: 1; /**< Timeout clock unit */ + uint32_t base_clk_freq: 8; /**< Base clock frequency */ + uint32_t max_blk_len: 2; /**< Maximum Block length */ + uint32_t embedded_8_bit_support: 1; /**< Embedded 8-bit support */ + uint32_t adma2_support: 1; /**< ADMA2 support */ + uint32_t : 1; + uint32_t high_speed_support: 1; /**< High speed support */ + uint32_t sdma_support: 1; /**< SDMA support */ + uint32_t suspend_resume_support: 1; /**< Suspend resume support */ + uint32_t voltage_3v3_support: 1; /**< 3.3v support */ + uint32_t voltage_3v0_support: 1; /**< 3.0v support */ + uint32_t voltage_1v8_support: 1; /**< 1.8v support */ + uint32_t sys_addr_64_bit_v4_support: 1; /**< SD Host Version 4 support */ + uint32_t sys_addr_64_bit_v3_support: 1; /**< SD Host Version 3 support */ + uint32_t asysnc_interrupt_support: 1; /**< Asynchronous interrupt support */ + uint32_t slot_type_r: 2; /**< Slot type */ + }; + uint32_t U; + } capabilities1; + + union { + struct { + uint32_t sdr50_support: 1; /**< SDR50 support */ + uint32_t sdr104_support: 1; /**< SDR104 support */ + uint32_t ddr50_support: 1; /**< DDR50 support */ + uint32_t uhs2_support: 1; /**< UHS2 support */ + uint32_t drv_type_a: 1; /**< Drive TypeA support */ + uint32_t drv_type_c: 1; /**< Drive TypeC support */ + uint32_t drv_type_d: 1; /**< Drive TypeD support */ + uint32_t reserved0: 1; + uint32_t retune_cnt: 4; /**< Retune count support */ + uint32_t : 1; + uint32_t use_tuning_sdr50: 1; /**< Use tuning sdr50 support */ + uint32_t re_tuning_modes: 2; /**< Retune modes */ + uint32_t clk_mul: 8; /**< Clock multiplier */ + uint32_t : 3; + uint32_t adma3_support: 1; /**< ADMA3 support */ + uint32_t vdd2_1v8_support: 1; /**< VDD2 1v8 support */ + uint32_t : 3; + }; + uint32_t U; + } capabilities2; + + union { + struct { + uint32_t max_current_3v3: 8; /**< Maximum current at 3.3V */ + uint32_t max_current_3v0: 8; /**< Maximum current at 3.0V */ + uint32_t max_current_1v8: 8; /**< Maximum current at 1.8V */ + uint32_t reserved: 8; + }; + uint32_t U; + } curr_capabilities1; + + union { + struct { + uint32_t max_current_vdd2_1v8: 8; /**< Maximum current at VDD2 1.8V */ + uint32_t reserved: 24; + }; + uint32_t U; + } curr_capabilities2; + +} sdxc_capabilities_t; + +/** + * @brief SDXC Device response type + */ +typedef enum _sdxc_dev_resp_type { + sdxc_dev_resp_none = 0, + sdxc_dev_resp_r1, + sdxc_dev_resp_r1b, + sdxc_dev_resp_r2, + sdxc_dev_resp_r3, + sdxc_dev_resp_r4, + sdxc_dev_resp_r5, + sdxc_dev_resp_r5b, + sdxc_dev_resp_r6, + sdxc_dev_resp_r7, +} sdxc_dev_resp_type_t; + +/** + * @brief SDXC command structure + */ +typedef struct _sdxc_command { + uint32_t cmd_index; /**< Command index */ + uint32_t cmd_argument; /**< Command argument */ + uint32_t cmd_flags; /**< Command flags */ + sdxc_command_type_t cmd_type; /**< Command type */ + sdxc_dev_resp_type_t resp_type; /**< Command response type */ + uint32_t resp_error_flags; /**< Command response error flags */ + uint32_t response[4]; /**< Response buffer */ + uint32_t auto_cmd_resp; /**< Auto command response */ + uint32_t cmd_timeout_ms; /**< Command Timeout in ms, 0 - means use default short timeout */ +} sdxc_command_t; + +/** + * @brief SDXC data list + */ +typedef struct _sdxc_data_list { + uint32_t *data_addr; + uint32_t data_size; + struct _sdxc_data_list *data_list; +} sdxc_data_list_t; + +/** + * @brief SDXC data structure + */ +typedef struct _sdxc_data { + bool enable_auto_cmd12; + bool enable_auto_cmd23; + bool enable_ignore_error; + uint8_t data_type; + uint32_t block_size; + uint32_t block_cnt; + uint32_t *rx_data; + const uint32_t *tx_data; +} sdxc_data_t; + +/** + * @brief SDXC transfer data type + */ +enum { + sdxc_xfer_data_normal = 0U, /**< Transfer normal read/write data */ + sdxc_xfer_data_tuning = 1U, /**< Transfer Tuning data */ + sdxc_xfer_data_boot = 2U, /**< Transfer boot data */ + sdxc_xfer_data_boot_continuous = 3U, /**< Transfer boot data continuously */ +}; + +/** + * @brief SDXC transfer context + */ +typedef struct _sdxc_xfer { + sdxc_data_t *data; + sdxc_command_t *command; +} sdxc_xfer_t; + +/** + * @brief SDXC ADMA configuration + */ +typedef struct _sdxc_adma_config { + sdxc_dma_type_t dma_type; + uint32_t *adma_table; + uint32_t adma_table_words; +} sdxc_adma_config_t; + +enum { + sdxc_adma_desc_single_flag = 0U, + sdxc_adma_desc_multi_flag = 1U, +}; + +/** + * @brief SDXC configuration + */ +typedef struct _sdxc_config { + uint32_t data_timeout; /**< Data timeout in milliseconds */ +} sdxc_config_t; + +/** + * @brief SDXC ADMA2 descriptor + */ +typedef struct _sdxc_adma2_descriptor { + union { + struct { + uint32_t valid: 1; /**< Valid flag */ + uint32_t end: 1; /**< End flag */ + uint32_t interrupt: 1; /**< Interrupt flag */ + uint32_t act: 3; /**INT_STAT; +} + +/** + * @brief Check whether SD card is inserted + * @retval SD Card instertion status + * @arg true SD Card is inserted + * @arg false SD card is not inserted + */ +static inline bool sdxc_is_card_inserted(SDXC_Type *base) +{ + return IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CARD_INSERTED_MASK); +} + +/** + * @brief Clear SDXC interrupt status + * @param [in] base SDXC base address + * @param [in] status_mask the status mask to be cleared + */ +static inline void sdxc_clear_interrupt_status(SDXC_Type *base, uint32_t status_mask) +{ + base->INT_STAT = status_mask; +} + +/** + * @brief Enable SDXC interrupt status + * @param [in] base SDXC base address + * @param [in] mask SDXC interrupt status mask + * @param [in] enable Interrupt status enable flag + */ +static inline void sdxc_enable_interrupt_status(SDXC_Type *base, uint32_t mask, bool enable) +{ + if (enable) { + base->INT_STAT_EN |= mask; + } else { + base->INT_STAT_EN &= ~mask; + } +} + +/** + * @brief Enable SDXC interrupt signal + * @param [in] base SDXC base address + * @param [in] mask SDXC interrupt signal mask + * @param [in] enable Interrupt signal enable flag + */ +static inline void sdxc_enable_interrupt_signal(SDXC_Type *base, uint32_t mask, bool enable) +{ + if (enable) { + base->INT_SIGNAL_EN |= mask; + } else { + base->INT_SIGNAL_EN &= ~mask; + } +} + +/** + * @brief Get SDXC capabilities + * @param [in] base SDXC base address + * @param [out] capabilities buffer + */ +hpm_stat_t sdxc_get_capabilities(SDXC_Type *base, sdxc_capabilities_t *capabilities); + + +/** + * @brief Get SDXC ADMA error status + * @param [in] base SDXC base address + * @retval AMDA error status register value + */ +static inline uint8_t sdxc_get_adma_error_status(SDXC_Type *base) +{ + return base->ADMA_ERR_STAT; +} + +/** + * @brief Configure SDXC data timeout interal + * @param [in] base SDXC base address + * @param [in] timeout SDXC data timeout option + */ +static inline void sdxc_configure_data_timeout(SDXC_Type *base, uint8_t timeout) +{ + base->SYS_CTRL = (base->SYS_CTRL & ~SDXC_SYS_CTRL_TOUT_CNT_MASK) | SDXC_SYS_CTRL_TOUT_CNT_SET(timeout); +} + +/** + * @brief Configure SDXC interrupt at block gap + * @param [in] base SDXC base address + * @param [in] enable Enable Interrupt_at_Block_Gap flag + */ +static inline void sdxc_interrupt_at_block_gap(SDXC_Type *base, bool enable) +{ + if (enable) { + base->PROT_CTRL |= SDXC_PROT_CTRL_INT_AT_BGAP_MASK; + } else { + base->PROT_CTRL &= ~SDXC_PROT_CTRL_INT_AT_BGAP_MASK; + } +} + +/** + * @brief Enable or Disable SDXC Read Wait + * @param [in] base SDXC base address + * @param [in] enable Enable SDXC Read Wait flag + */ +static inline void sdxc_read_wait_control(SDXC_Type *base, bool enable) +{ + if (enable) { + base->PROT_CTRL |= SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK; + } else { + base->PROT_CTRL &= ~SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK; + } +} + +/** + * @brief Configure SDXC continue request + * @param [in] base SDXC base address + * @param [in] enable Flag to enable/disable SDXC continue request + */ +static inline void sdxc_continue_request(SDXC_Type *base, bool enable) +{ + if (enable) { + base->PROT_CTRL |= SDXC_PROT_CTRL_CONTINUE_REQ_MASK; + } else { + base->PROT_CTRL &= ~SDXC_PROT_CTRL_CONTINUE_REQ_MASK; + } +} + +/** + * @brief Configure SDXC StopAtBlockGap request + * @param [in] base SDXC base address + * @param [in] enable Flag to enable/disable StopAtBlockGap request + */ +static inline void sdxc_stop_at_block_gap_request(SDXC_Type *base, bool enable) +{ + if (enable) { + base->PROT_CTRL |= SDXC_PROT_CTRL_STOP_BG_REQ_MASK; + } else { + base->PROT_CTRL &= ~SDXC_PROT_CTRL_STOP_BG_REQ_MASK; + } +} + +/** + * @brief Control the SDXC high-speed support + * @param [in] base SDXC base address + * @param [in] enable flag to Enable/disable SDXC high-speed support + */ +static inline void sdxc_enable_high_speed(SDXC_Type *base, bool enable) +{ + if (enable) { + base->PROT_CTRL |= SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; + } else { + base->PROT_CTRL &= ~SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; + } +} + +/** + * @brief Enable SDXC asynchronous interrupt support + * @param [in] base SDXC base address + * @param [in] enable Flag to enable/disable SDXC asynchronous interrupt support + */ +static inline void sdxc_enable_async_interrupt(SDXC_Type *base, bool enable) +{ + if (enable) { + base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK; + } else { + base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK; + } +} + +/** + * @brief Enable SDXC Preset support + * @param [in] base SDXC base address + * @param [in] enable flag to enable/disable SDXC Preset support + */ +static inline void sdxc_enable_preset(SDXC_Type *base, bool enable) +{ + if (enable) { + base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK; + } else { + base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK; + } +} + +/** + * @brief Enable SD Host version 4 + * @param [in] base SDXC base address + * @param [in] enable flag to enable/disable SD Host version 4 support + */ +static inline void sdxc_enable_host_version4(SDXC_Type *base, bool enable) +{ + if (enable) { + base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK; + } else { + base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK; + } +} + +/** + * @brief Start SDXC tuning process + * @param [in] base SDXC base address + */ +static inline void sdxc_execute_tuning(SDXC_Type *base) +{ + base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK | SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK; +} + +/** + * @brief Enable SDXC software tuning process + * @param [in] base SDXC base address + * @param [in] enable flag to enable/disable SDXC software tuning + */ +static inline void sdxc_enable_software_tuning(SDXC_Type *base, bool enable) +{ + if (enable) { + base->AUTO_TUNING_CTRL |= SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK; + } + else { + base->AUTO_TUNING_CTRL &= ~SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK; + } +} + +/** + * @brief Reset SDXC tuning engine + * @param [in] base SDXC base address + */ +static inline void sdxc_reset_tuning_engine(SDXC_Type *base) +{ + base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK; +} + +/** + * @brief Switch SDXC to 1.8V signaling mode + * @param [in] base SDXC base address + * @param [in] enable Flag to switch to 1.8v signaling mode/stay at 3.0v signaling mode + */ +static inline void sdxc_switch_to_1v8_signal(SDXC_Type *base, bool enable) +{ + if (enable) { + base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; + } else { + base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; + } +} + +/** + * @brief Enable/Disable SDXC internal clock + * @param[in] base SDXC base address + * @param [in] enable Flag to enable/disable SDXC internal clock + */ +static inline void sdxc_enable_internal_clock(SDXC_Type *base, bool enable) +{ + if (enable) { + base->SYS_CTRL |= SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK; + } else { + base->SYS_CTRL &= ~SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK; + } +} + +/** + * @brief Get Present status register value + * @param [in] base SDXC base address + * @retval SDXC PRESENT register value + */ +static inline uint32_t sdxc_get_present_status(SDXC_Type *base) +{ + return base->PSTATE; +} + +/** + * @brief Read data from SDXC using non-DMA mode + * @param [in] base SDXC base address + * @retval Data read from SDXC + */ +static inline uint32_t sdxc_read_data(SDXC_Type *base) +{ + return base->BUF_DATA; +} + +/** + * @brief Write data to SDXC using non-DMA mode + * @param [in] base SDXC base address + * @param [in] data Data to be written to SDXC + */ +static inline void sdxc_write_data(SDXC_Type *base, uint32_t data) +{ + base->BUF_DATA = data; +} + +/** + * @brief Get SDXC DATA3-DATA0 IO level + * @param [in] base SDXC base address + * @retval SDXC data3-data0 IO level + */ +static inline uint32_t sdxc_get_data3_0_level(SDXC_Type *base) +{ + return SDXC_PSTATE_DAT_3_0_GET(base->PSTATE); +} + +/** + * @brief Enable SDXC auto tuning + * @param [in] base SDXC base address + * @param [in] enable Flag to enable/disable SDXC auto tuning + */ +static inline void sdxc_enable_auto_tuning(SDXC_Type *base, bool enable) +{ + if (enable) { + base->AUTO_TUNING_CTRL |= SDXC_AUTO_TUNING_CTRL_AT_EN_MASK; + } else { + base->AUTO_TUNING_CTRL &= ~SDXC_AUTO_TUNING_CTRL_AT_EN_MASK; + } +} + +/** + * @brief Enable/Disable SDXC MMC boot + * @param [in] base SDXC base address + * @param [in] enable FLag to enable/disable SDXC MMC boot + */ +static inline void sdxc_enable_mmc_boot(SDXC_Type *base, bool enable) +{ + if (enable) { + base->EMMC_BOOT_CTRL |= SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK; + } else { + base->EMMC_BOOT_CTRL &= ~SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK; + } +} + +/** + * @brief Set SDXC force event + * @param [in] base SDXC base address + * @param [in] mask SDXC event mask + */ +static inline void sdxc_force_event(SDXC_Type *base, uint32_t mask) +{ + base->FORCE_EVENT = mask; +} + +/** + * @brief Enable/disable SDXC SD clock output + * @param [in] base SDXC base address + * @param [in] enable Flag to enable/disable SDXC SD clock output + */ +static inline void sdxc_enable_sd_clock(SDXC_Type *base, bool enable) +{ + if (enable) { + base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; + while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_SD_CLK_EN_MASK)) { + } + } else { + base->SYS_CTRL &= ~SDXC_SYS_CTRL_SD_CLK_EN_MASK; + while (IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_SD_CLK_EN_MASK)) { + } + } +} + +/** + * @brief Set SDXC center phase code + * @param [in] base SDXC base address + * @param [in] value SDXC center phase value + */ +static inline void sdxc_set_center_phase_code(SDXC_Type *base, uint32_t value) +{ + base->AUTO_TUNING_STAT = (base->AUTO_TUNING_STAT & ~SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) | + SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET(value); +} + +/** + * @brief Enable SDXC enhanced strobe + * @param [in] base SDXC base address + * @param [in] enable flag to enable/disable SSDXC enhanced strobe + */ +static inline void sdxc_enable_enhanced_strobe(SDXC_Type *base, bool enable) +{ + if (enable) { + base->EMMC_BOOT_CTRL |= SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK; + } + else { + base->EMMC_BOOT_CTRL &= ~SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK; + } +} + +/** + * @brief Set MMC boot configuration + * @param [in] base SDXC base address + * @param [in] config MMC boot configuration + */ +void sdxc_set_mmc_boot_config(SDXC_Type *base, const sdxc_boot_config_t *config); + +/** + * @brief Send Command via SDXC + * @param [in] base SDXC base address + * @param [in] cmd Command + * @retval status_timeout Sending command timed out + * @retval status_success Command was sent out successfully + */ +hpm_stat_t sdxc_send_command(SDXC_Type *base, sdxc_command_t *cmd); + +/** + * @brief Receive command response + * @param [in] base SDXC base address + * @param [in/out] cmd Command + * @return status_success if no error happened + */ +hpm_stat_t sdxc_receive_cmd_response(SDXC_Type *base, sdxc_command_t *cmd); + +/** + * @brief Parse the SDXC interrupt status to HPM encoded status + * @param [in] base SDXC base status + * @return status_success if no error happened + */ +hpm_stat_t sdxc_parse_interrupt_status(SDXC_Type *base); + +/** + * @brief Wait until SDXC command completes + * @param [in] base SDXC base address + * @param [in] cmd Command + * @param [out] polling_cmd_done flag to determine whether to use blocking wait + * @retval SDXC command execution status + */ +hpm_stat_t sdxc_wait_cmd_done(SDXC_Type *base, sdxc_command_t *cmd, bool polling_cmd_done); + +/** + * @brief Set Data transfer configuration + * @param [in] base SDXC base address + * @param [in] data_dir Data transfer direction + * @param [in] block_cnt Block count for data transfer + * @param [in] block_size Block size for data transfer + */ +void sdxc_set_data_config(SDXC_Type *base, sdxc_xfer_direction_t data_dir, uint32_t block_cnt, uint32_t block_size); + +/** + * @brief Set ADMA table configuration + * @param [in] base SDXC base address + * @param [in] dma_cfg DMA configuration + * @param [in] data_cfg Data configuration + * @param [in] flags Flags for AMDA transfer + * @retval API execution status + */ +hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, + sdxc_data_t *data_cfg, uint32_t flags); + +/** + * @brief Set ADMA2 descriptor + * @param [in] adma_tbl ADMA2 table + * @param [in] adma_table_words ADMA2 table size in words + * @param [in] data_buf pointer to the Data to be trnasferred + * @param [in] data_bytes Data size for transfer + * @param [in] flags Flags for ADMA2 descriptor + * @retval API execution status + */ +hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, uint32_t adma_table_words, const uint32_t *data_buf, + uint32_t data_bytes, uint32_t flags); + +/** + * @brief Set DMA configuration + * @param [in] base SDXC base address + * @param [in] dma_cfg DMA configuration data structure + * @param [in] data_addr Buffer holds incoming/outgoing data + * @param [in] enable_auto_cmd23 Flag to determine whether to enable auto CMD23 or not + * @retval API execution status + */ +hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, const uint32_t *data_addr, + bool enable_auto_cmd23); + +/** + * @brief Initialize SDXC controller + * @param [in] base SDXC base address + * @param [in] config SDXC configuration + */ +void sdxc_init(SDXC_Type *base, const sdxc_config_t *config); + +/** + * @brief Set the Data Timeout Counter value for an SD/eMMC device + * @param [in] base SDXC base address + * @param [in] timeout_in_ms Required timeout value in milliseconds, maximum value is 131,072ms + * @param [out] actual_timeout_us Actual timeout in milliseconds, reported by this API + */ +void sdxc_set_data_timeout(SDXC_Type *base, uint32_t timeout_in_ms, uint32_t *actual_timeout_ms); + +/** + * @brief Set SDXC speed mode + * @param [in] base SDXC base address + * @param [in] mode SDXC speed mode option + */ +void sdxc_set_speed_mode(SDXC_Type *base, sdxc_speed_mode_t mode); + + +/** + * @brief Set SDXC Data bus width + * @param [in] base SDXC base address + * @param [in] width SDXC bus width option + */ +void sdxc_set_data_bus_width(SDXC_Type *base, sdxc_bus_width_t width); + +/** + * @brief Get SDXC Data bus width + * @param [in] base SDXC base address + * @return Actual bus width, valid value: 1 / 4 / 8 + */ +uint32_t sdxc_get_data_bus_width(SDXC_Type *base); + +/** + * @brief Set SDXC IO voltage + * @param [in] base SDXC base address + * @param [option] SDXC voltage option + */ +void sdxc_select_voltage(SDXC_Type *base, sdxc_bus_voltage_option_t option); + +/** + * @brief Reset SDXC + * @param [in] base SDXC base address + * @param [in] reset_type SDXC reset type + * @param [in] timeout timeout ticks + * @retval SDXC reset result + */ +bool sdxc_reset(SDXC_Type *base, sdxc_sw_reset_type_t reset_type, uint32_t timeout); + +/** + * @brief Enable SDXC wakeup interrupt + * @param [in] base SDXC base address + * @param [in] evt SDXC wakeup interrupt + * @param [in] enable Flag to control whether to enable SDXC wakeup event + */ +void sdxc_enable_wakeup_event(SDXC_Type *base, sdxc_wakeup_event_t evt, bool enable); + +/** + * @brief Start SDXC transfer in blocking way + * @param [in] base SDXC base address + * @param [in] dma_config SDXC DMA configuration + * @param [in] xfer SDXC transfer context + * @retval SDXC transfer status + */ +hpm_stat_t sdxc_transfer_blocking(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); + +/** + * @brief Start SDXC transfer in nonblocking way + * @param [in] base SDXC base address + * @param [in] dma_config SDXC DMA configuration + * @param [in] xfer SDXC transfer context + * @retval SDXC transfer status + */ +hpm_stat_t sdxc_transfer_nonblocking(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); + +/** + * @brief SDXC Error recovery + * @param [in] base SDXC base address + * @retval SDXC error recovery status + */ +hpm_stat_t sdxc_error_recovery(SDXC_Type *base); + +/** + * @brief Perform SDXC tuning flow sequence + * @param [in] base SDXC base address + * @param [in] tuning_cmd Tuning command + * @retval Tuning status + */ +hpm_stat_t sdxc_perform_tuning_flow_sequence(SDXC_Type *base, uint8_t tuning_cmd); + +/** + * @brief Perform SDXC software tuning + * @param [in] base SDXC base address + * @param [in] tuning_cmd Tuning command + * @retval Tuning status + */ +hpm_stat_t sdxc_perform_software_tuning(SDXC_Type *base, uint8_t tuning_cmd); + +/** + * @brief Perform SDXC auto tuning + * @param [in] base SDXC base address + * @param [in] tuning_cmd tuning command + * @retval Tuning status + */ +hpm_stat_t sdxc_perform_auto_tuning(SDXC_Type *base, uint8_t tuning_cmd); + +#if defined(__cplusplus) +} +#endif + +/** + * @} + */ + +#endif /*HPM_SDXC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h new file mode 100644 index 0000000000..3521aec688 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SPI_DRV_H +#define HPM_SPI_DRV_H +#include "hpm_spi_regs.h" + +/** + * @brief SPI driver APIs + * @defgroup spi_interface SPI driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief spi mode selection + */ +typedef enum { + spi_master_mode = 0, + spi_slave_mode +} spi_mode_selection_t; + +/** + * @brief spi clock polarity + */ +typedef enum { + spi_sclk_low_idle = 0, + spi_sclk_high_idle +} spi_sclk_idle_state_t; + +/** + * @brief spi clock phase + */ +typedef enum { + spi_sclk_sampling_odd_clk_edges = 0, + spi_sclk_sampling_even_clk_edges +} spi_sclk_sampling_clk_edges_t; + +/** + * @brief spi cs to sclk edge duration + */ +typedef enum { + spi_cs2sclk_half_sclk_1 = 0, + spi_cs2sclk_half_sclk_2, + spi_cs2sclk_half_sclk_3, + spi_cs2sclk_half_sclk_4 +} spi_cs2sclk_duration_t; + +/** + * @brief spi cs high level duration + */ +typedef enum { + spi_csht_half_sclk_1 = 0, + spi_csht_half_sclk_2, + spi_csht_half_sclk_3, + spi_csht_half_sclk_4, + spi_csht_half_sclk_5, + spi_csht_half_sclk_6, + spi_csht_half_sclk_7, + spi_csht_half_sclk_8, + spi_csht_half_sclk_9, + spi_csht_half_sclk_10, + spi_csht_half_sclk_11, + spi_csht_half_sclk_12, + spi_csht_half_sclk_13, + spi_csht_half_sclk_14, + spi_csht_half_sclk_15, + spi_csht_half_sclk_16, +} spi_csht_duration_t; + +/** + * @brief spi address phase format + */ +typedef enum { + spi_address_phase_format_single_io_mode = 0, + spi_address_phase_format_dualquad_io_mode +} spi_addr_phase_format_t; + +/** + * @brief spi transfer mode + */ +typedef enum { + spi_trans_write_read_together = 0, + spi_trans_write_only, + spi_trans_read_only, + spi_trans_write_read, + spi_trans_read_write, + spi_trans_write_dummy_read, + spi_trans_read_dummy_write, + spi_trans_no_data, + spi_trans_dummy_write, + spi_trans_dummy_read +} spi_trans_mode_t; + +/** + * @brief spi data phase format + */ +typedef enum { + spi_single_io_mode = 0, + spi_dual_io_mode, + spi_quad_io_mode, +} spi_data_phase_format_t; + +/** + * @brief spi token value + */ +typedef enum { + spi_token_value_0x00 = 0, + spi_token_value_0x69 +} spi_token_value_t; + +/** + * @brief spi dummy count + */ +typedef enum { + spi_dummy_count_1 = 0, + spi_dummy_count_2, + spi_dummy_count_3, + spi_dummy_count_4 +} spi_dummy_count_t; + +/** + * @brief spi master interface timing config structure + */ +typedef struct { + uint32_t clk_src_freq_in_hz; + uint32_t sclk_freq_in_hz; + uint8_t cs2sclk; + uint8_t csht; +} spi_master_timing_config_t; + +/** + * @brief spi interface timing config structure + */ +typedef struct { + spi_master_timing_config_t master_config; +} spi_timing_config_t; + +/** + * @brief spi master transfer format config structure + */ +typedef struct { + uint8_t addr_len_in_bytes; +} spi_master_format_config_t; + +/** + * @brief spi common format config structure + */ +typedef struct { + uint8_t data_len_in_bits; + bool data_merge; + bool mosi_bidir; + bool lsb; + uint8_t mode; + uint8_t cpol; + uint8_t cpha; +} spi_common_format_config_t; + +/** + * @brief spi format config structure + */ +typedef struct { + spi_master_format_config_t master_config; + spi_common_format_config_t common_config; +} spi_format_config_t; + +/** + * @brief spi master transfer control config structure + */ +typedef struct { + bool cmd_enable; + bool addr_enable; + uint8_t addr_phase_fmt; + bool token_enable; + uint8_t token_value; +} spi_master_control_config_t; + +/** + * @brief spi slave transfer control config structure + */ +typedef struct { + bool slave_data_only; +} spi_slave_control_config_t; + +/** + * @brief spi common transfer control config structure + */ +typedef struct { + bool tx_dma_enable; + bool rx_dma_enable; + uint8_t trans_mode; + uint8_t data_phase_fmt; + uint8_t dummy_cnt; +} spi_common_control_config_t; + +/** + * @brief spi control config structure + */ +typedef struct { + spi_master_control_config_t master_config; + spi_slave_control_config_t slave_config; + spi_common_control_config_t common_config; +} spi_control_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief spi master get default timing config + * + * @param [out] config spi_timing_config_t + */ +void spi_master_get_default_timing_config(spi_timing_config_t *config); + +/** + * @brief spi master get default format config + * + * @param [out] config spi_format_config_t + */ +void spi_master_get_default_format_config(spi_format_config_t *config); + +/** + * @brief spi master get default control config + * + * @param [out] config spi_control_config_t + */ +void spi_master_get_default_control_config(spi_control_config_t *config); + +/** + * @brief spi slave get default format config + * + * @param [out] config spi_format_config_t + */ +void spi_slave_get_default_format_config(spi_format_config_t *config); + +/** + * @brief spi slave get default control config + * + * @param [out] config spi_control_config_t + */ +void spi_slave_get_default_control_config(spi_control_config_t *config); + +/** + * @brief spi master timing initialization + * + * @param [in] ptr SPI base address + * @param [in] config spi_timing_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t spi_master_timing_init(SPI_Type *ptr, spi_timing_config_t *config); + +/** + * @brief spi format initialization + * + * @param [in] ptr SPI base address + * @param [in] config spi_format_config_t + */ +void spi_format_init(SPI_Type *ptr, spi_format_config_t *config); + +/** + * @brief spi transfer + * + * @param [in] ptr SPI base address + * @param [in] config spi_control_config_t + * @param [in] cmd spi transfer mode + * @param [in] addr spi transfer target address + * @param [in] wbuff spi sent data buff address + * @param [in] wsize spi sent data size in byte + * @param [in] rbuff spi receive data buff address + * @param [in] rsize spi receive data size + * @retval hpm_stat_t status_success if spi transfer without any error + */ +hpm_stat_t spi_transfer(SPI_Type *ptr, + spi_control_config_t *config, + uint8_t *cmd, uint32_t *addr, + uint8_t *wbuff, uint32_t wsize, uint8_t *rbuff, uint32_t rsize); + +/** + * @brief spi setup dma transfer + * + * @param [in] ptr SPI base address + * @param [in] config spi_control_config_t + * @param [in] cmd spi transfer mode + * @param [in] addr spi transfer target address + * @param [in] wsize spi sent data size in byte + * @param [in] rsize spi receive data size + * @retval hpm_stat_t status_success if spi setup dma transfer without any error + */ +hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, + spi_control_config_t *config, + uint8_t *cmd, uint32_t *addr, + uint32_t wsize, uint32_t rsize); + +/** + * @brief spi wait for idle status + * + * @param [in] ptr SPI base address + * @retval hpm_stat_t status_success if spi in idle status + */ +hpm_stat_t spi_wait_for_idle_status(SPI_Type *ptr); + +/** + * @brief spi wait for busy status + * + * @param [in] ptr SPI base address + * @retval hpm_stat_t status_success if spi in busy status + */ +hpm_stat_t spi_wait_for_busy_status(SPI_Type *ptr); + +/** + * @} + */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* HPM_SPI_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h new file mode 100644 index 0000000000..cba7cb967f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SYNT_DRV_H +#define HPM_SYNT_DRV_H +#include "hpm_common.h" +#include "hpm_synt_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void synt_enable_counter(SYNT_Type *ptr, bool enable) +{ + ptr->GCR = (ptr->GCR & ~(SYNT_GCR_CEN_MASK)) | SYNT_GCR_CEN_SET(enable); +} + +static inline void synt_reset_counter(SYNT_Type *ptr) +{ + ptr->GCR |= SYNT_GCR_CRST_MASK; + ptr->GCR &= ~SYNT_GCR_CRST_MASK; +} + +static inline hpm_stat_t synt_set_comparator(SYNT_Type *ptr, + uint8_t cmp_index, + uint32_t count) +{ + if (cmp_index > SYNT_CMP_3) { + return status_invalid_argument; + } + ptr->CMP[cmp_index] = SYNT_CMP_CMP_SET(count); + return status_success; +} + +static inline void synt_set_reload(SYNT_Type *ptr, uint32_t reload_count) +{ + ptr->RLD = SYNT_RLD_RLD_SET(reload_count); +} + +static inline uint32_t synt_get_current_count(SYNT_Type *ptr) +{ + return (ptr->CNT & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT; +} + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_SYNT_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h new file mode 100644 index 0000000000..a42ee6f8f5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_TRGM_DRV_H +#define HPM_TRGM_DRV_H + +#include "hpm_common.h" +#include "hpm_trgm_drv.h" +#include "hpm_trgmmux_src.h" + +/** + * + * @brief TRGM driver APIs + * @defgroup trgm_interface TRGM driver APIs + * @{ + */ + +/** + * @brief Filter mode + */ +typedef enum trgm_filter_mode { + trgm_filter_mode_bypass = 0, + trgm_filter_mode_rapid_change = 1, + trgm_filter_mode_delay = 2, + trgm_filter_mode_stable_low = 3, + trgm_filter_mode_stable_high = 4, +} trgm_filter_mode_t; + +/** + * @brief Output type + */ +typedef enum trgm_output_type { + trgm_output_same_as_input = 0, + trgm_output_pulse_at_input_falling_edge = TRGM_TRGOCFG_FEDG2PEN_MASK, + trgm_output_pulse_at_input_rising_edge = TRGM_TRGOCFG_REDG2PEN_MASK, + trgm_output_pulse_at_input_both_edge = trgm_output_pulse_at_input_falling_edge + | trgm_output_pulse_at_input_rising_edge, +} trgm_output_type_t; + +/** + * @brief Input filter configuration + */ +typedef struct trgm_input_filter { + bool invert; /**< Invert output */ + bool sync; /**< Sync with TRGM clock */ + uint16_t filter_length; /**< Filter length in TRGM clock cycle */ + trgm_filter_mode_t mode; /**< Filter working mode */ +} trgm_input_filter_t; + +/** + * @brief Output configuration + */ +typedef struct trgm_output { + bool invert; /**< Invert output */ + trgm_output_type_t type; /**< Output type */ + uint8_t input; /**< Input selection */ +} trgm_output_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable IO output + * + * @param[in] ptr TRGM base address + * @param[in] mask Mask of IOs to be enabled + */ +static inline void trgm_enable_io_output(TRGM_Type *ptr, uint32_t mask) +{ + ptr->GCR |= mask; +} + +/** + * @brief Disable IO output + * + * @param[in] ptr TRGM base address + * @param[in] mask Mask of IOs to be disabled + */ +static inline void trgm_disable_io_output(TRGM_Type *ptr, uint32_t mask) +{ + ptr->GCR &= ~mask; +} + +/** + * @brief Set filter length + * + * @param[in] ptr TRGM base address + * @param[in] input Input selection + * @param[in] length Filter length in TRGM clock cycles (0 ~ 0xFFF) + */ +static inline void trgm_input_filter_set_filter_length(TRGM_Type *ptr, uint8_t input, uint16_t length) +{ + ptr->FILTCFG[input] = (ptr->FILTCFG[input] & TRGM_FILTCFG_FILTLEN_MASK) + | TRGM_FILTCFG_FILTLEN_SET(length); +} + +/** + * @brief Enable sync input with TRGM clock + * + * @param[in] ptr TRGM base address + * @param[in] input Input selection + */ +static inline void trgm_input_filter_enable_sync(TRGM_Type *ptr, uint8_t input) +{ + ptr->FILTCFG[input] |= TRGM_FILTCFG_SYNCEN_MASK; +} + +/** + * @brief Disable sync input with TRGM clock + * + * @param[in] ptr TRGM base address + * @param[in] input Input selection + */ +static inline void trgm_input_filter_disable_sync(TRGM_Type *ptr, uint8_t input) +{ + ptr->FILTCFG[input] &= ~TRGM_FILTCFG_SYNCEN_MASK; +} + +/** + * @brief Set filter working mode + * + * @param[in] ptr TRGM base address + * @param[in] input Input selection + * @param[in] mode Working mode + */ +static inline void trgm_input_filter_set_mode(TRGM_Type *ptr, uint8_t input, trgm_filter_mode_t mode) +{ + ptr->FILTCFG[input] = (ptr->FILTCFG[input] & TRGM_FILTCFG_MODE_MASK) + | TRGM_FILTCFG_MODE_SET(mode); +} + +/** + * @brief Invert filter output + * + * @param[in] ptr TRGM base address + * @param[in] input Input selection + * @param[in] invert Set true to invert output + */ +static inline void trgm_input_filter_invert(TRGM_Type *ptr, uint8_t input, bool invert) +{ + ptr->FILTCFG[input] = (ptr->FILTCFG[input] & TRGM_FILTCFG_OUTINV_MASK) + | TRGM_FILTCFG_OUTINV_SET(invert); +} + +/** + * @brief Configure filter + * + * @param[in] ptr TRGM base address + * @param[in] input Input selection + * @param[in] filter Pointer to filter configuration + */ +static inline void trgm_input_filter_config(TRGM_Type *ptr, uint8_t input, trgm_input_filter_t *filter) +{ + ptr->FILTCFG[input] = TRGM_FILTCFG_OUTINV_SET(filter->invert) + | TRGM_FILTCFG_MODE_SET(filter->mode) + | TRGM_FILTCFG_SYNCEN_SET(filter->sync) + | TRGM_FILTCFG_FILTLEN_SET(filter->filter_length); +} + +/** + * @brief Update source for TRGM output + * + * @param[in] ptr TRGM base address + * @param[in] output Target output + * @param[in] source Source for output + */ +static inline void trgm_output_update_source(TRGM_Type *ptr, uint8_t output, uint8_t source) +{ + ptr->TRGOCFG[output] = (ptr->TRGOCFG[output] & ~TRGM_TRGOCFG_TRIGOSEL_MASK) + | TRGM_TRGOCFG_TRIGOSEL_SET(source); +} + +/** + * @brief Configure output + * + * @param[in] ptr TRGM base address + * @param[in] output Target output + * @param[in] config Pointer to output configuration + */ +static inline void trgm_output_config(TRGM_Type *ptr, uint8_t output, trgm_output_t *config) +{ + ptr->TRGOCFG[output] = TRGM_TRGOCFG_TRIGOSEL_SET(config->input) + | TRGM_TRGOCFG_FEDG2PEN_SET(config->type) + | TRGM_TRGOCFG_REDG2PEN_SET(config->type); +} + +/** + * @brief Configure DMA request + * + * @param[in] ptr TRGM base address + * @param[in] dma_out Target DMA out + * @param[in] dma_src DMA source selection + */ +static inline void trgm_dma_request_config(TRGM_Type *ptr, uint8_t dma_out, uint8_t dma_src) +{ + ptr->DMACFG[dma_out] = TRGM_DMACFG_DMASRCSEL_SET(dma_src); +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_TRGM_DRV_H */ + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h new file mode 100644 index 0000000000..ff58d6ce91 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h @@ -0,0 +1,417 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TSNS_DRV_H +#define HPM_TSNS_DRV_H + +#include "hpm_common.h" +#include "hpm_tsns_regs.h" + +/** + * @brief TSNS driver APIs + * @defgroup tsns_interface TSNS driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ +#define TSNS_TEMP_SCALE 256 + +typedef enum { + tsns_clear_min = TSNS_FLAG_RECORD_MIN_CLR_MASK, + tsns_clear_max = TSNS_FLAG_RECORD_MAX_CLR_MASK, + tsns_clear_under_temp = TSNS_FLAG_UNDER_TEMP_MASK, + tsns_clear_over_temp = TSNS_FLAG_OVER_TEMP_MASK, + tsns_clear_irq = TSNS_FLAG_IRQ_MASK, +} tsns_clear_type_mask_t; + +typedef enum { + tsns_event_irq = 0, + tsns_event_reset, +} tsns_event_t; + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Enable temperature sensor + * + * @param ptr base address + */ +static inline void tsns_enable(TSNS_Type *ptr) +{ + ptr->CONFIG |= TSNS_CONFIG_ENABLE_MASK; +} + +/** + * @brief Disable temperature sensor + * + * @param ptr base address + */ +static inline void tsns_disable(TSNS_Type *ptr) +{ + ptr->CONFIG &= ~TSNS_CONFIG_ENABLE_MASK; +} + +/** + * @brief Check if current temperature value is valid or not + * + * @param ptr base address + * + * @return true the value is valid + */ +static inline bool tsns_temperature_is_valid(TSNS_Type *ptr) +{ + return ptr->STATUS & TSNS_STATUS_VALID_MASK; +} + +/** + * @brief Get maximum measured temperature in raw + * + * @param ptr base address + * + * @return raw maximum temperature value scaled by TSNS_TEMP_SCALE + */ +static inline int32_t tsns_get_max_temp_raw(TSNS_Type *ptr) +{ + return TSNS_TMAX_T_GET(ptr->TMAX); +} + +/** + * @brief Get minimum measured temperature in raw + * + * @param ptr base address + * + * @return raw minimum temperature value scaled by TSNS_TEMP_SCALE + */ +static inline int32_t tsns_get_min_temp_raw(TSNS_Type *ptr) +{ + return TSNS_TMIN_T_GET(ptr->TMIN); +} + +/** + * @brief Get current temperature in raw + * + * @param ptr base address + * + * @return raw temperature value scaled by TSNS_TEMP_SCALE + */ +static inline int32_t tsns_get_current_temp_in_raw(TSNS_Type *ptr) +{ + while (!tsns_temperature_is_valid(ptr)) { + ; + } + return TSNS_T_T_GET(ptr->T); +} + +/** + * @brief Get current temperature in celsius degree + * + * @param ptr base address + * + * @return current temperature in celsius degree + */ +static inline float tsns_get_current_temp(TSNS_Type *ptr) +{ + return (float)(((int32_t)tsns_get_current_temp_in_raw(ptr) / TSNS_TEMP_SCALE)); +} + +/** + * @brief Get temperature age + * + * @param ptr base address + * + * @return temperature age + */ +static inline uint32_t tsns_get_temp_age(TSNS_Type *ptr) +{ + return TSNS_AGE_AGE_GET(ptr->AGE); +} + +/** + * @brief Set temperature high limit to trigger rest + * + * @param ptr base address + * @param high temperature value + */ +static inline void tsns_set_reset_threshold_high(TSNS_Type *ptr, uint32_t high) +{ + ptr->UPPER_LIM_IRQ = TSNS_UPPER_LIM_RST_T_SET(high); +} + +/** + * @brief Set temperature low limit to trigger reset + * + * @param ptr base address + * @param low temperature value + */ +static inline void tsns_set_reset_threshold_low(TSNS_Type *ptr, uint32_t low) +{ + ptr->LOWER_LIM_IRQ = TSNS_LOWER_LIM_RST_T_SET(low); +} + +/** + * @brief Enable temperature limit to trigger irq + * + * @param ptr base address + */ +static inline void tsns_enable_limit_trigger_reset(TSNS_Type *ptr) +{ + ptr->CONFIG |= TSNS_CONFIG_RST_EN_MASK; +} + +/** + * @brief Disable temperature limit to trigger irq + * + * @param ptr base address + */ +static inline void tsns_disable_limit_trigger_irq(TSNS_Type *ptr) +{ + ptr->CONFIG &= ~TSNS_CONFIG_RST_EN_MASK; +} + +/** + * @brief Set temperature high limit to trigger irq + * + * @param ptr base address + * @param high temperature value + */ +static inline void tsns_set_irq_threshold_high(TSNS_Type *ptr, uint32_t high) +{ + ptr->UPPER_LIM_IRQ = TSNS_UPPER_LIM_IRQ_T_SET(high); +} + +/** + * @brief Set temperature low limit to trigger irq + * + * @param ptr base address + * @param low temperature value + */ +static inline void tsns_set_irq_threshold_low(TSNS_Type *ptr, uint32_t low) +{ + ptr->LOWER_LIM_IRQ = TSNS_LOWER_LIM_IRQ_T_SET(low); +} + +/** + * @brief Enable temperature limit to trigger irq + * + * @param ptr base address + */ +static inline void tsns_enable_limit_trigger_irq(TSNS_Type *ptr) +{ + ptr->CONFIG |= TSNS_CONFIG_IRQ_EN_MASK; +} + +/** + * @brief Set validity of current measured temperature in 24Mhz clock cycles + * + * @param ptr base address + * @param validity clock cycle count + */ +static inline void tsns_set_validity(TSNS_Type *ptr, uint32_t validity) +{ + ptr->VALIDITY = TSNS_VALIDITY_VALIDITY_SET(validity); +} + +/** + * @brief Set temperature limit to trigger irq + * + * @param ptr base address + * @param high high temperature + * @param low low temperature + */ +static inline void tsns_config_irq_threshold(TSNS_Type *ptr, uint32_t high, uint32_t low) +{ + tsns_set_irq_threshold_low(ptr, low); + tsns_set_irq_threshold_high(ptr, high); +} + +/** + * @brief Set temperature limit to trigger reset + * + * @param ptr base address + * @param high high temperature + * @param low low temperature + */ +static inline void tsns_config_reset_threshold(TSNS_Type *ptr, uint32_t high, uint32_t low) +{ + tsns_set_reset_threshold_low(ptr, low); + tsns_set_reset_threshold_high(ptr, high); +} + +/** + * @brief Enable compare max temperature + * + * @param ptr base address + */ +static inline void tsns_enable_compare_max(TSNS_Type *ptr) +{ + ptr->CONFIG |= TSNS_CONFIG_COMPARE_MAX_EN_MASK; +} + +/** + * @brief Enable compare min temperature + * + * @param ptr base address + */ +static inline void tsns_enable_compare_min(TSNS_Type *ptr) +{ + ptr->CONFIG |= TSNS_CONFIG_COMPARE_MIN_EN_MASK; +} + +/** + * @brief Disable compare max temperature + * + * @param ptr base address + */ +static inline void tsns_disable_compare_max(TSNS_Type *ptr) +{ + ptr->CONFIG &= ~TSNS_CONFIG_COMPARE_MAX_EN_MASK; +} + +/** + * @brief Disable compare min temperature + * + * @param ptr base address + */ +static inline void tsns_disable_compare_min(TSNS_Type *ptr) +{ + ptr->CONFIG &= ~TSNS_CONFIG_COMPARE_MIN_EN_MASK; +} + +/** + * @brief Set measurement speed + * + * @param ptr base address + * @param speed speed from 24-255 + */ +static inline void tsns_set_speed(TSNS_Type *ptr, uint8_t speed) +{ + assert(speed >= 24); + ptr->CONFIG = (ptr->CONFIG & TSNS_CONFIG_SPEED_MASK) | TSNS_CONFIG_SPEED_SET(speed); +} + +/** + * @brief Set average + * + * @param ptr base address + * @param average range 0 - 7 (0: 2^0 = 1 means measure once and return ... 2: 2^2 = 4 means measure 4 times and average) + */ +static inline void tsns_set_average(TSNS_Type *ptr, uint8_t average) +{ + ptr->CONFIG = (ptr->CONFIG & TSNS_CONFIG_AVERAGE_MASK) | TSNS_CONFIG_AVERAGE_SET(average); +} + +/** + * @brief Enable Async mode + * + * @param ptr base address + */ +static inline void tsns_enable_async_mode(TSNS_Type *ptr) +{ + ptr->CONFIG |= TSNS_CONFIG_ASYNC_MASK; +} + +/** + * @brief Disable Async mode and switch to active mode + * + * @param ptr base address + */ +static inline void tsns_disable_async_mode(TSNS_Type *ptr) +{ + ptr->CONFIG &= ~TSNS_CONFIG_ASYNC_MASK; +} + +/** + * @brief Enable trigger mode + * + * @param ptr base address + */ +static inline void tsns_enable_trigger_mode(TSNS_Type *ptr) +{ + ptr->CONFIG &= ~TSNS_CONFIG_CONTINUOUS_MASK; +} + +/** + * @brief Enable continuous mode + * + * @param ptr base address + */ +static inline void tsns_enable_continuous_mode(TSNS_Type *ptr) +{ + ptr->CONFIG |= TSNS_CONFIG_CONTINUOUS_MASK; +} + +/** + * @brief trigger measurement + * + * @param ptr base address + */ +static inline void tsns_trigger_measurement(TSNS_Type *ptr) +{ + uint32_t tmp = ptr->CONFIG; + ptr->CONFIG &= ~TSNS_CONFIG_CONTINUOUS_MASK; + ptr->STATUS |= TSNS_STATUS_TRIGGER_MASK; + ptr->CONFIG = tmp; +} + +/** + * @brief clear tsns flag or recorded data + * + * @param ptr base address + * @param mask flag or data to be cleared + */ +static inline void tsns_clear_with_mask(TSNS_Type *ptr, tsns_clear_type_mask_t mask) +{ + ptr->FLAG |= mask; +} + + +/** + * @brief configure low temperature limite to trigger event + * + * @param ptr base address + * @param low temperature value + * @param e event type, tsns_event_irq or tsns_event_reset + */ +void tsns_configure_low_limit_event(TSNS_Type *ptr, int32_t low, tsns_event_t e); + +/** + * @brief configure high temperature limite to trigger event + * + * @param ptr base address + * @param high temperature value + * @param e event type, tsns_event_irq or tsns_event_reset + */ +void tsns_configure_high_limit_event(TSNS_Type *ptr, int32_t high, tsns_event_t e); + +/** + * @brief configure temperature limite to trigger event + * + * @param ptr base address + * @param high temperature value + * @param low temperature value + * @param e event type, tsns_event_irq or tsns_event_reset + */ +void tsns_configure_limit_event(TSNS_Type *ptr, int32_t high, int32_t low, tsns_event_t e); + +#ifdef __cplusplus +} +#endif +/** + * @} + * + */ +#endif /* HPM_TSNS_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h new file mode 100644 index 0000000000..a1f465afa1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h @@ -0,0 +1,431 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_UART_DRV_H +#define HPM_UART_DRV_H +#include "hpm_common.h" +#include "hpm_uart_regs.h" + +/** + * + * @brief UART driver APIs + * @defgroup uart_interface UART driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief UART status + */ +enum { + status_uart_no_suitable_baudrate_parameter_found = MAKE_STATUS(status_group_uart, 1), +}; + +/* @brief Parity */ +typedef enum parity { + parity_none = 0, + parity_odd, + parity_even, + parity_always_1, + parity_always_0, +} parity_setting_t; + +/* @brief Stop bits */ +typedef enum num_of_stop_bits { + stop_bits_1 = 0, + stop_bits_1_5, + stop_bits_2, +} num_of_stop_bits_t; + +/* @brief Word length */ +typedef enum word_length { + word_length_5_bits = 0, + word_length_6_bits, + word_length_7_bits, + word_length_8_bits, +} word_length_t; + +/* @brief UART fifo trigger levels */ +typedef enum uart_fifo_trg_lvl { + uart_rx_fifo_trg_not_empty = 0, + uart_rx_fifo_trg_gt_one_quarter = 1, + uart_rx_fifo_trg_gt_half = 2, + uart_rx_fifo_trg_gt_three_quarters = 3, + + uart_tx_fifo_trg_not_full = 0, + uart_tx_fifo_trg_lt_three_quarters = 1, + uart_tx_fifo_trg_lt_half = 2, + uart_tx_fifo_trg_lt_one_quarter = 3, +} uart_fifo_trg_lvl_t; + +/* @brief UART signals */ +typedef enum uart_signal { + uart_signal_rts = UART_MCR_RTS_MASK, +} uart_signal_t; + +/* @brief UART signal levels */ +typedef enum uart_signal_level { + uart_signal_level_high, + uart_signal_level_low, +} uart_signal_level_t; + +/* @brief UART modem status */ +typedef enum uart_modem_stat { + uart_modem_stat_cts = UART_MSR_CTS_MASK, + uart_modem_stat_dcts_changed = UART_MSR_DCTS_MASK, +} uart_modem_stat_t; + +/* @brief UART interrupt enable masks */ +typedef enum uart_intr_enable { + uart_intr_rx_data_avail_or_timeout = UART_IER_ERBI_MASK, + uart_intr_tx_slot_avail = UART_IER_ETHEI_MASK, + uart_intr_rx_line_stat = UART_IER_ELSI_MASK, + uart_intr_modem_stat = UART_IER_EMSI_MASK, +} uart_intr_enable_t; + +/* @brief UART interrupt IDs */ +typedef enum uart_intr_id { + uart_intr_id_modem_stat = 0x0, + uart_intr_id_tx_slot_avail = 0x2, + uart_intr_id_rx_data_avail = 0x4, + uart_intr_id_rx_line_stat = 0x6, + uart_intr_id_rx_timeout = 0xc, +} uart_intr_id_t; + +/* @brief UART status */ +typedef enum uart_stat { + uart_stat_data_ready = UART_LSR_DR_MASK, + uart_stat_overrun_error = UART_LSR_OE_MASK, + uart_stat_parity_error = UART_LSR_PE_MASK, + uart_stat_framing_error = UART_LSR_FE_MASK, + uart_stat_line_break = UART_LSR_LBREAK_MASK, + uart_stat_tx_slot_avail = UART_LSR_THRE_MASK, + uart_stat_transmitter_empty = UART_LSR_TEMT_MASK, + uart_stat_rx_fifo_error = UART_LSR_ERRF_MASK, +} uart_stat_t; + +/** + * @brief UART modem config + */ +typedef struct uart_modem_config { + bool auto_flow_ctrl_en; /**< Auto flow control enable flag */ + bool loop_back_en; /**< Loop back enable flag */ + bool set_rts_high; /**< Set signal RTS level high flag */ +} uart_modem_config_t; + +/** + * @brief UART config + */ +typedef struct hpm_uart_config { + + uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ + uint32_t baudrate; /**< Baudrate */ + uint8_t num_of_stop_bits; /**< Number of stop bits */ + uint8_t word_length; /**< Word length */ + uint8_t parity; /**< Parity */ + uint8_t tx_fifo_level; /**< TX Fifo level */ + uint8_t rx_fifo_level; /**< RX Fifo level */ + bool dma_enable; /**< DMA Enable flag */ + bool fifo_enable; /**< Fifo Enable flag */ + uart_modem_config_t modem_config; /**< Modem config */ +} uart_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get fifo size + * + * @param ptr UART base address + * @retval size of Fifo + */ +static inline uint8_t uart_get_fifo_size(UART_Type *ptr) +{ + return 16 << ((ptr->CFG & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT); +} + +/** + * @brief Reset TX Fifo + * + * @param ptr UART base address + */ +static inline void uart_reset_tx_fifo(UART_Type *ptr) +{ + if (ptr->FCR & UART_FCR_FIFOE_MASK) { + ptr->FCR |= UART_FCR_TFIFORST_MASK; + } +} + +/** + * @brief Reset RX Fifo + * + * @param ptr UART base address + */ +static inline void uart_reset_rx_fifo(UART_Type *ptr) +{ + if (ptr->FCR & UART_FCR_FIFOE_MASK) { + ptr->FCR |= UART_FCR_RFIFORST_MASK; + } +} + +/** + * @brief Reset both TX and RX Fifo + * + * @param ptr UART base address + */ +static inline void uart_reset_all_fifo(UART_Type *ptr) +{ + if (ptr->FCR & UART_FCR_FIFOE_MASK) { + ptr->FCR |= UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK; + } +} + +/** + * @brief Enable modem loopback + * + * @param ptr UART base address + */ +static inline void uart_modem_enable_loopback(UART_Type *ptr) +{ + ptr->MCR |= UART_MCR_LOOP_MASK; +} + +/** + * @brief Disable modem loopback + * + * @param ptr UART base address + */ +static inline void uart_modem_disable_loopback(UART_Type *ptr) +{ + ptr->MCR &= ~UART_MCR_LOOP_MASK; +} + +/** + * @brief Disable modem auto flow control + * + * @param ptr UART base address + */ + +static inline void uart_modem_disable_auto_flow_control(UART_Type *ptr) +{ + ptr->MCR &= ~UART_MCR_AFE_MASK; +} + +/** + * @brief Enable modem auto flow control + * + * @param ptr UART base address + */ +static inline void uart_modem_enable_auto_flow_control(UART_Type *ptr) +{ + ptr->MCR |= UART_MCR_AFE_MASK; +} + +/** + * @brief Configure modem + * + * @param ptr UART base address + * @param config Pointer to modem config struct + */ +static inline void uart_modem_config(UART_Type *ptr, uart_modem_config_t *config) +{ + ptr->MCR = UART_MCR_AFE_SET(config->auto_flow_ctrl_en) + | UART_MCR_LOOP_SET(config->loop_back_en) + | UART_MCR_RTS_SET(!config->set_rts_high); +} + +/** + * @brief Get modem status + * + * @param ptr UART base address + * @retval Current modem status + */ +static inline uint8_t uart_get_modem_status(UART_Type *ptr) +{ + return ptr->MSR; +} + + +/** + * @brief Check modem status with given mask + * + * @param ptr UART base address + * @param mask Status mask value to be checked against + * @retval true if any bit in given mask is set + * @retval false if none of any bit in given mask is set + */ +static inline bool uart_check_modem_status(UART_Type *ptr, uart_modem_stat_t mask) +{ + return (ptr->MSR & mask); +} + +/** + * @brief Disable IRQ with mask + * + * @param ptr UART base address + * @param irq_mask IRQ mask value to be disabled + */ +static inline void uart_disable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) +{ + ptr->IER &= ~irq_mask; +} + +/** + * @brief Enable IRQ with mask + * + * @param ptr UART base address + * @param irq_mask IRQ mask value to be enabled + */ +static inline void uart_enable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) +{ + ptr->IER |= irq_mask; +} + +/** + * @brief Get Enabled IRQ + * + * @param ptr UART base address + * @return enabled irq + */ +static inline uint32_t uart_get_enabled_irq(UART_Type *ptr) +{ + return ptr->IER; +} + +/** + * @brief Get interrupt identification + * + * @param ptr UART base address + * @retval interrupt id + */ +static inline uint8_t uart_get_irq_id(UART_Type *ptr) +{ + return (ptr->IIR & UART_IIR_INTRID_MASK); +} + +/** + * @brief Get status + * + * @param ptr UART base address + * @retval current status + */ +static inline uint8_t uart_get_status(UART_Type *ptr) +{ + return ptr->LSR; +} + +/** + * @brief Check uart status according to the given status mask + * + * @param ptr UART base address + * @param mask Status mask value to be checked against + * @retval true if any bit in given mask is set + * @retval false if none of any bit in given mask is set + */ +static inline bool uart_check_status(UART_Type *ptr, uart_stat_t mask) +{ + return (ptr->LSR & mask); +} + +/** + * @brief Get default config + * + * @param ptr UART base address + * @param config Pointer to the buffer to save default values + */ +void uart_default_config(UART_Type *ptr, uart_config_t *config); + +/** + * @brief Initialization + * + * @param ptr UART base address + * @param config Pointer to config struct + * @retval status_success only if it succeeds + */ +hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config); + +/** + * @brief Send one byte + * + * @param ptr UART base address + * @param c Byte to be sent + * @retval status_success only if it succeeds + */ +hpm_stat_t uart_send_byte(UART_Type *ptr, uint8_t c); + +/** + * @brief Receive one byte + * + * @param ptr UART base address + * @param c Pointer to buffer to save the byte received on UART + * @retval status_success only if it succeeds + */ +hpm_stat_t uart_receive_byte(UART_Type *ptr, uint8_t *c); + +/** + * @brief Set uart signal output level + * + * @param ptr UART base address + * @param signal Target signal + * @param level Target signal level + */ +void uart_set_signal_level(UART_Type *ptr, + uart_signal_t signal, + uart_signal_level_t level); + +/** + * @brief Flush sending buffer/fifo + * + * @param ptr UART base address + * @retval status_success only if it succeeds + */ +hpm_stat_t uart_flush(UART_Type *ptr); + +/** + * @brief Receive bytes blocking + * + * @param ptr UART base address + * @param buf Pointer to the buffer to save received data + * @param size_in_byte Size in byte to be sent + * @retval status_success only if it succeeds + */ +hpm_stat_t uart_receive_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte); + +/** + * @brief Send bytes blocking + * + * @param ptr UART base address + * @param buf Pointer to the buffer to be sent + * @param size_in_byte Size in byte to be sent + * @retval status_success only if it succeeds + */ +hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte); + + +/** + * @brief Sets UART baudrate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the uart_init. + * + * @param ptr UART base address + * @param baudrate UART baudrate to be set + * @param src_clock_hz UART clock source frequency in Hz. + * @retval status_uart_no_suitable_baudrate_parameter_found Baudrate is not supported in the current clock source + * @retval status_success Set baudrate succeeded. + */ +hpm_stat_t uart_set_baudrate(UART_Type *ptr, uint32_t baudrate, uint32_t src_clock_hz); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_UART_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h new file mode 100644 index 0000000000..b0d7bda720 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h @@ -0,0 +1,450 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_USB_DRV_H +#define HPM_USB_DRV_H +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_common.h" +#include "hpm_usb_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief USB driver APIs + * @defgroup usb_interface USB driver APIs + * @ingroup communication_interfaces + * @{ + */ + +/*---------------------------------------------------------------------* + * Macro Constant Declarations + *---------------------------------------------------------------------*/ +#define USB_PHY_INIT_DELAY_COUNT (16U) /**< a delay count for USB phy initialization */ +#define USB_HOST_FRAMELIST_SIZE (8U) /**< a frame list size in USB host mode */ + +/*---------------------------------------------------------------------* + * Macro Enum Declarations + *---------------------------------------------------------------------*/ +/** + * @brief USB transfer direction types + */ +typedef enum { + usb_dir_out = 0, + usb_dir_in = 1, + usb_dir_in_mask = 0x80 +} usb_dir_t; + +/** + * @brief USB transfer types + */ +typedef enum { + usb_xfer_control = 0, + usb_xfer_isochronous, + usb_xfer_bulk, + usb_xfer_interrupt +} usb_xfer_type_t; + +/** + * @brief USB controller work modes + */ +typedef enum { + usb_ctrl_mode_otg = 0, + usb_ctrl_mode_device = 2, + usb_ctrl_mode_host = 3 +} usb_controller_mode_t; + +/** + * @brief USB line state + */ +typedef enum { + usb_line_state0 = 0, + usb_line_state1 = 1, + usb_line_state2 = 2 +} usb_line_state_t; + +/** + * @brief USB transceiver + */ +typedef enum { + usb_tran_parallel = 0, + usb_tran_serial = 1 +} usb_transceiver_t; +/*---------------------------------------------------------------------* + * Structure Declarations + *---------------------------------------------------------------------*/ +/** + * @brief Control request structure + */ +typedef struct __attribute__ ((packed)){ + union { + struct __attribute__ ((packed)) { + uint8_t recipient : 5; + uint8_t type : 2; + uint8_t direction : 1; + } bmRequestType_bit; + + uint8_t bmRequestType; + }; + + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} usb_control_request_t; + +/** + * @brief Endpoint config structure + */ +typedef struct { + uint8_t xfer; + uint8_t ep_addr; + uint16_t max_packet_size; +} usb_endpoint_config_t; + +#if defined __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*---------------------------------------------------------------------* + * Common API + *---------------------------------------------------------------------*/ + +/** + * @brief Get the mask of all enabled interrupts + * + * @param[in] ptr A USB peripheral base address. + * @retval Mask of all enabled interrupts. + */ +static inline uint32_t usb_get_interrupts(USB_Type *ptr) +{ + return ptr->USBINTR; +} + +/** + * @brief Enable interrupts + * + * @param[in] ptr A USB peripheral base address + * @param[in] mask Mask value for interrupt events + */ +static inline void usb_enable_interrupts(USB_Type *ptr, uint32_t mask) +{ + ptr->USBINTR |= mask; +} + +/** + * @brief Get all USB status flags + * + * @param[in] ptr A USB peripheral base address + * @retval The USB interrupt status flags + */ +static inline uint32_t usb_get_status_flags(USB_Type *ptr) +{ + return ptr->USBSTS; +} + +/** + * @brief Clear status flags + * + * Only the specified flags can be cleared by writing USBSTS register. + * + * @param[in] ptr A USB peripheral base address + * @param[in] mask Mask value for flags to be cleared. + */ + +static inline void usb_clear_status_flags(USB_Type *ptr, uint32_t mask) +{ + ptr->USBSTS |= mask; +} + +/** + * @brief Get USB suspend status + * + * @param[in] ptr A USB peripheral base address + * @retval The USB controller suspend status + */ +static inline uint8_t usb_get_suspend_status(USB_Type *ptr) +{ + return USB_PORTSC1_SUSP_GET(ptr->PORTSC1); +} + +/** + * @brief Get USB reset status + * + * @param[in] ptr A USB peripheral base address + * @retval The USB controller reset status + */ +static inline bool usb_get_port_reset_status(USB_Type *ptr) +{ + return USB_PORTSC1_PR_GET(ptr->PORTSC1); +} + +/** + * @brief Get USB current connect status + * + * @param[in] ptr A USB peripheral base address + * @retval The USB controller reset status + */ +static inline bool usb_get_port_ccs(USB_Type *ptr) +{ + return USB_PORTSC1_CCS_GET(ptr->PORTSC1); +} + +/** + * @brief Get USB port speed status + * + * @param[in] ptr A USB peripheral base address + * @retval The USB controller port speed status + */ +static inline uint8_t usb_get_port_speed(USB_Type *ptr) +{ + return USB_PORTSC1_PSPD_GET(ptr->PORTSC1); +} + +/*---------------------------------------------------------------------* + * Device API + *---------------------------------------------------------------------*/ + +/** + * @brief USB device bus reset + * + * @param[in] ptr A USB peripheral base address + * @param[in] ep0_max_packet_size The maximum packet size of endpoint 0 + */ +void usb_dcd_bus_reset(USB_Type *ptr, uint16_t ep0_max_packet_size); + +/** + * @brief Initialize controller to device mode + * + * @param[in] ptr A USB peripheral base address + */ +void usb_dcd_init(USB_Type *ptr); + +/** + * @brief Deinitialize controller to device + * + * @param[in] ptr A USB peripheral base address + */ +void usb_dcd_deinit(USB_Type *ptr); + +/** + * @brief Wakeup from host + * + * @param[in] ptr A USB peripheral base address + */ +void usb_dcd_remote_wakeup(USB_Type *ptr); + +/** + * @brief Open an endpoint + * + * @param[in] ptr A USB peripheral base address + * @param[in] config A pointer to the specified endpoint config struct + */ +void usb_dcd_edpt_open(USB_Type *ptr, usb_endpoint_config_t *config); +/** + * @brief Submit a transfer + * + * @param[in] ptr A USB peripheral base address + * @param[in] ep_idx An index of the specified endpoint + */ +void usb_dcd_edpt_xfer(USB_Type *ptr, uint8_t ep_idx); + +/** + * @brief Stall endpoint + * + * @param[in] ptr A USB peripheral base address + * @param[in] ep_addr An address of the specified endpoint + */ +void usb_dcd_edpt_stall(USB_Type *ptr, uint8_t ep_addr); + +/** + * @brief Clear stall + * + * @param[in] ptr A USB peripheral base address + * @param[in] ep_addr An address of the specified endpoint + */ +void usb_dcd_edpt_clear_stall(USB_Type *ptr, uint8_t ep_addr); + +/** + * @brief Close a specified endpoint + * + * @param[in] ptr A USB peripheral base address + * @param[in] ep_addr An address of the specified endpoint + */ +void usb_dcd_edpt_close(USB_Type *ptr, uint8_t ep_addr); + +/** + * @brief Connect by enabling internal pull-up resistor on D+/D- + * + * @param[in] ptr A USB peripheral base address + */ +void usb_dcd_connect(USB_Type *ptr); + +/** + * @brief Disconnect by disabling internal pull-up resistor on D+/D- + * + * @param[in] ptr A USB peripheral base address + */ +void usb_dcd_disconnect(USB_Type *ptr); + +/** + * @brief Get setup status of endpoint + * + * @param[in] ptr A USB peripheral base address + * @retval The status of setup endpoint + */ +static inline uint32_t usb_dcd_get_edpt_setup_status(USB_Type *ptr) +{ + return ptr->ENDPTSETUPSTAT; +} + +/** + * @brief Clear the setup status of all specified endpoints + * + * @param[in] ptr A USB peripheral base address + * @param[in] mask A mask of all specified endpoints + */ +static inline void usb_dcd_clear_edpt_setup_status(USB_Type *ptr, uint32_t mask) +{ + ptr->ENDPTSETUPSTAT |= mask; +} + +/** + * @brief Set address + * + * @param[in] ptr A USB peripheral base address + * @param[in] dev_addr An assigned endpoint address from USB host + */ +static inline void usb_dcd_set_address(USB_Type *ptr, uint8_t dev_addr) +{ + ptr->DEVICEADDR = USB_DEVICEADDR_USBADR_SET(dev_addr) | USB_DEVICEADDR_USBADRA_MASK; +} + +/** + * @brief Set endpoint list address + * + * @param[in] ptr A USB peripheral base address + * @param[in] addr A start address of the endpoint qtd list + */ +static inline void usb_dcd_set_edpt_list_addr(USB_Type *ptr, uint32_t addr) +{ + ptr->ENDPTLISTADDR = addr & USB_ENDPTLISTADDR_EPBASE_MASK; +} + +/** + * @brief Get device address + * + * @param[in] ptr A USB peripheral base address + * @retval The endpoint address + */ +static inline uint8_t usb_dcd_get_device_addr(USB_Type *ptr) +{ + return USB_DEVICEADDR_USBADR_GET(ptr->DEVICEADDR); +} + +/** + * @brief Get complete status of endpoint + * + * @param[in] ptr A USB peripheral base address + * @retval The complete status od endpoint + */ +static inline uint32_t usb_dcd_get_edpt_complete_status(USB_Type *ptr) +{ + return ptr->ENDPTCOMPLETE; +} + +/** + * @brief Clear complete status of endpoint + * + * @param[in] ptr A USB peripheral base address + * @param[in] mask A mask of the specified endpoints + */ +static inline void usb_dcd_clear_edpt_complete_status(USB_Type *ptr, uint32_t mask) +{ + ptr->ENDPTCOMPLETE |= mask; +} + +/*---------------------------------------------------------------------* + * Host API + *---------------------------------------------------------------------*/ +/** + * @brief Initialize controller to host mode + * + * @param[in] ptr A USB peripheral base address + * @param[in] int_mask A mask of all required interrupts + * @param[in] framelist_size A size of the frame list + */ +bool usb_hcd_init(USB_Type *ptr, uint32_t int_mask, uint16_t framelist_size); + +/** + * @brief Initialize controller to host modeHost Reset port + * + * @param[in] ptr A USB peripheral base address + */ +void usb_hcd_port_reset(USB_Type *ptr); + +/** + * @brief Initialize controller to host modeHost set command register + * + * @param[in] ptr A USB peripheral base address + * @param[in] mask A mask of all required commands + */ +static inline void usb_hcd_set_command(USB_Type *ptr ,uint32_t mask) +{ + ptr->USBCMD |= mask; +} + +/** + * @brief Get frame index + * + * @param[in] ptr A USB peripheral base address + * @retval A index of the current frame list + */ +static inline uint32_t usb_hcd_get_frame_index(USB_Type *ptr) +{ + return ptr->FRINDEX; +} + +/** + * @brief Get port connect status change + * + * @param[in] ptr A USB peripheral base address + * @retval A connect status change + */ +static inline bool usb_hcd_get_port_csc(USB_Type *ptr) +{ + return USB_PORTSC1_CSC_GET(ptr->PORTSC1); +} + +/** + * @brief Get port connect status changeSet async list address + * + * @param[in] ptr A USB peripheral base address + * @param[in] addr An the start address of the async endpoint list + */ +static inline void usb_hcd_set_async_list_addr(USB_Type *ptr, uint32_t addr) +{ + ptr->ASYNCLISTADDR = addr & USB_ASYNCLISTADDR_ASYBASE_MASK; +} + +/** + * @brief Set periodic list address + * + * @param[in] ptr A USB peripheral base address + * @param[in] addr An start address of the periodic endpoint list + */ +static inline void usb_hcd_set_periodic_list_addr(USB_Type *ptr, uint32_t addr) +{ + ptr->PERIODICLISTBASE = addr & USB_PERIODICLISTBASE_BASEADR_MASK; +} + +#if defined __cplusplus +} +#endif /* __cplusplus */ + +/** @} */ +#endif /* HPM_USB_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h new file mode 100644 index 0000000000..b0661bde27 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_VAD_DRV_H +#define HPM_VAD_DRV_H + +#include "hpm_common.h" +#include "hpm_vad_regs.h" + +/** + * @brief VAD driver APIs + * @defgroup vad_interface VAD driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief vad event + */ +#define VAD_EVENT_VAD (1U << 7) +#define VAD_EVENT_FIFO_DATA_AVAILABLE (1U << 6) +#define VAD_EVENT_MEMBUF_EMPTY (1U << 5) +#define VAD_EVENT_FIFO_OVERFLOW (1U << 4) +#define VAD_EVENT_IIR_OVERLOAD (1U << 3) +#define VAD_EVENT_IIR_OVERFLOW (1U << 2) +#define VAD_EVENT_CIC_OVERLOAD_ERROR (1U << 1) +#define VAD_EVENT_CIC_STA_ERROR (1U << 0) + +/** + * @brief vad config + */ +typedef struct vad_config { + bool enable_buffer; + bool enable_pdm_clock_out; + bool enable_two_channels; + uint8_t capture_delay; + uint8_t pdm_half_div; + uint8_t fifo_threshold; + uint8_t post_scale; + bool channel_polarity_high[2]; +} vad_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief set capture deplay cycle + * + * @param [in] ptr VAD base address + * @param [in] delay delay cycle value + */ +static inline void vad_set_capture_delay(VAD_Type *ptr, uint8_t delay) +{ + ptr->CTRL = (ptr->CTRL & ~VAD_CTRL_CAPT_DLY_MASK) + | VAD_CTRL_CAPT_DLY_SET(delay); +} + +/** + * @brief set pdm clock hald_divider + * + * @param [in] ptr VAD base address + * @param [in] div divider value + */ +static inline void vad_set_pdm_clock_half_div(VAD_Type *ptr, uint8_t div) +{ + ptr->CTRL = (ptr->CTRL & ~VAD_CTRL_PDM_CLK_HFDIV_MASK) + | VAD_CTRL_PDM_CLK_HFDIV_SET(div); +} + +/** + * @brief enable irq + * + * @param [in] ptr VAD base address + * @param [in] irq_mask irq mask value + */ +static inline void vad_enable_irq(VAD_Type *ptr, uint32_t irq_mask) +{ + ptr->CTRL |= irq_mask; +} + +/** + * @brief disable irq + * + * @param [in] ptr VAD base address + * @param [in] irq_mask irq mask value + */ +static inline void vad_disable_irq(VAD_Type *ptr, uint32_t irq_mask) +{ + ptr->CTRL &= ~irq_mask; +} + +/** + * @brief disable buffer + * + * @param [in] ptr VAD base address + */ +static inline void vad_disable_buffer(VAD_Type *ptr) +{ + ptr->CTRL |= VAD_CTRL_MEMBUF_DISABLE_MASK; +} + +/** + * @brief enable buffer + * + * @param [in] ptr VAD base address + */ +static inline void vad_enable_buffer(VAD_Type *ptr) +{ + ptr->CTRL &= ~VAD_CTRL_MEMBUF_DISABLE_MASK; +} + +/** + * @brief set fifo threshold + * + * @param [in] ptr VAD base address + * @param [in] threshold fifo threshold value + */ +static inline void vad_set_fifo_threshold(VAD_Type *ptr, uint8_t threshold) +{ + ptr->CTRL = (ptr->CTRL & ~(VAD_CTRL_FIFO_THRSH_MASK)) + | VAD_CTRL_FIFO_THRSH_SET(threshold); +} + +/** + * @brief enable pdm clock out + * + * @param [in] ptr VAD base address + */ +static inline void vad_enable_pdm_clock_out(VAD_Type *ptr) +{ + ptr->CTRL |= VAD_CTRL_PDM_CLK_OE_MASK; +} + +/** + * @brief disable pdm clock out + * + * @param [in] ptr VAD base address + */ +static inline void vad_disable_pdm_clock_out(VAD_Type *ptr) +{ + ptr->CTRL &= ~VAD_CTRL_PDM_CLK_OE_MASK; +} + +/** + * @brief set pdm clock polarity + * + * @param [in] ptr VAD base address + * @param [in] level clock polarity + */ +static inline void vad_set_pdm_clock_capture_level(VAD_Type *ptr, uint8_t level) +{ + ptr->CTRL = (ptr->CTRL & ~VAD_CTRL_CH_POL_MASK) + | VAD_CTRL_CH_POL_SET(level); +} + +/** + * @brief set channel number + * + * @param [in] ptr VAD base address + * @param [in] two_channels: + * @arg true: set two channels + * @arg false: set one channel + */ +static inline void vad_set_channel_number(VAD_Type *ptr, bool two_channels) +{ + ptr->CTRL = (ptr->CTRL & ~VAD_CTRL_CHNUM_MASK) + | (two_channels ? VAD_CTRL_CHNUM_MASK : 0); +} + +/** + * @brief get status + * + * @param [in] ptr VAD base address + * @retval ST register value + */ +static inline uint32_t vad_get_status(VAD_Type *ptr) +{ + return ptr->ST; +} + +/** + * @brief slear status + * + * @param [in] ptr VAD base address + * @param [in] mask status mask value + */ +static inline void vad_clear_status(VAD_Type *ptr, uint32_t mask) +{ + ptr->ST |= mask; +} + +/** + * @brief get data + * + * @param [in] ptr VAD base address + * @retval OFIFO register value + */ +static inline uint32_t vad_get_data(VAD_Type *ptr) +{ + return ptr->OFIFO; +} + +/** + * @brief software reset + * + * @param [in] ptr VAD base address + */ +static inline void vad_software_reset(VAD_Type *ptr) +{ + ptr->RUN |= VAD_RUN_SFTRST_MASK; + ptr->RUN &= ~VAD_RUN_SFTRST_MASK; +} + +/** + * @brief start + * + * @param [in] ptr VAD base address + */ +static inline void vad_start(VAD_Type *ptr) +{ + ptr->RUN |= VAD_RUN_VAD_EN_MASK; +} + +/** + * @brief stop + * + * @param [in] ptr VAD base address + */ +static inline void vad_stop(VAD_Type *ptr) +{ + ptr->RUN &= ~VAD_RUN_VAD_EN_MASK; +} + +/** + * @brief check whether vad is running + * + * @param [in] ptr VAD base address + * @retval true if vad is running + */ +static inline bool vad_is_running(VAD_Type *ptr) +{ + return ptr->RUN & VAD_RUN_VAD_EN_MASK; +} + +/** + * @brief enable fifo + * + * @param [in] ptr VAD base address + */ +static inline void vad_enable_fifo(VAD_Type *ptr) +{ + ptr->OFIFO_CTRL |= VAD_OFIFO_CTRL_EN_MASK; +} + +/** + * @brief disable fifo + * + * @param [in] ptr VAD base address + */ +static inline void vad_disable_fifo(VAD_Type *ptr) +{ + ptr->OFIFO_CTRL &= ~VAD_OFIFO_CTRL_EN_MASK; +} + +/** + * @brief get coefficient value + * + * @param [in] ptr VAD base address + * @param [in] index coefficient index + */ +static inline uint32_t vad_get_coef_value(VAD_Type *ptr, uint32_t index) +{ + return ptr->COEF[index]; +} + +/** + * @brief set ouptput value post scale + * + * @param [in] ptr VAD base address + * @param [in] post_scale post scale value + */ +static inline void vad_set_post_scale(VAD_Type *ptr, uint8_t post_scale) +{ + ptr->CIC_CFG |= (ptr->CIC_CFG & ~VAD_CIC_CFG_POST_SCALE_MASK) + | VAD_CIC_CFG_POST_SCALE_SET(post_scale); +} + +/** + * @brief set sampling signal amplitude limits + * + * @param [in] ptr VAD base address + * @param [in] high high limit + * @param [in] low low limit + */ +static inline void vad_set_amplify(VAD_Type *ptr, uint16_t high, uint16_t low) +{ + ptr->DEC_CTRL2 = VAD_DEC_CTRL2_AMP_HIGH_SET(high) + | VAD_DEC_CTRL2_AMP_LOW_SET(low); +} + +/** + * @brief get default config + * + * @param [in] ptr VAD base address + * @param [out] config vad_config_t + */ +void vad_get_default_config(VAD_Type *ptr, vad_config_t *config); + +/** + * @brief initialization + * + * @param [in] ptr VAD base address + * @param [in] config vad_config_t + */ +void vad_init(VAD_Type *ptr, vad_config_t *config); + +/** + * @brief reset + * + * @param [in] ptr VAD base address + */ +void vad_reset(VAD_Type *ptr); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_VAD_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h new file mode 100644 index 0000000000..21b9782ed3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_WDG_DRV_H +#define HPM_WDG_DRV_H + +/** + * @brief WDG APIs + * @defgroup wdg_interface WDG driver APIs + * @ingroup wdg_interfaces + * @{ + */ + + +#include "hpm_common.h" +#include "hpm_wdg_regs.h" + +/** + * @brief WDG Reset Interval definitions + */ +typedef enum reset_interval_enum { + reset_interval_clock_period_mult_128 = 0, + reset_interval_clock_period_mult_256, + reset_interval_clock_period_mult_512, + reset_interval_clock_period_mult_1k, + reset_interval_clock_period_mult_2k, + reset_interval_clock_period_mult_4k, + reset_interval_clock_period_mult_8k, + reset_interval_clock_period_mult_16k, + reset_interval_max = reset_interval_clock_period_mult_16k, + reset_interval_out_of_range, +} reset_interval_t; + +/** + * @brief WDG Interrupt interval definitions + */ +typedef enum interrupt_interval_enum { + interrupt_interval_clock_period_multi_64, + interrupt_interval_clock_period_multi_256, + interrupt_interval_clock_period_multi_1k, + interrupt_interval_clock_period_multi_2k, + interrupt_interval_clock_period_multi_4k, + interrupt_interval_clock_period_multi_8k, + interrupt_interval_clock_period_multi_16k, + interrupt_interval_clock_period_multi_32k, + interrupt_interval_clock_period_multi_128k, + interrupt_interval_clock_period_multi_512k, + interrupt_interval_clock_period_multi_2m, + interrupt_interval_clock_period_multi_4m, + interrupt_interval_clock_period_multi_8m, + interrupt_interval_clock_period_multi_32m, + interrupt_interval_clock_period_multi_128m, + interrupt_interval_clock_period_multi_512m, + interrupt_interval_clock_period_multi_2g, + interrupt_interval_max = interrupt_interval_clock_period_multi_2g, + interrupt_interval_out_of_range, +} interrupt_interval_t; + +/** + * @brief WDG clock source definitions + */ +typedef enum wdg_clksrc_enum { + wdg_clksrc_extclk, /**< WDG clock source: external clock */ + wdg_clksrc_pclk, /**< WDG clock source: Peripheral clock */ + wdg_clksrc_max = wdg_clksrc_pclk +} wdg_clksrc_t; + +/** + * @brief WDG Control configuration structure + * @note WDG reset time = reset_interval + interrupt interval + */ +typedef struct wdg_control_struct { + reset_interval_t reset_interval; /**< WDG reset interval */ + interrupt_interval_t interrupt_interval; /**< WDG interrupt interval */ + bool reset_enable; /**< WDG reset enable */ + bool interrupt_enable; /**< WDG interrupt enable */ + wdg_clksrc_t clksrc; /**< WDG clock source */ + bool wdg_enable; /**< WDG enable */ +} wdg_control_t; + +#define WDG_WRITE_ENABLE_MAGIC_NUM (0x5AA5UL) /**< WDG enable magic number */ +#define WDG_RESTART_MAGIC_NUM (0xCAFEUL) /**< WDG restart magic number */ + +#define WDG_EXT_CLK_FREQ (32768UL) /**< WDG External CLock frequency: 32768 Hz */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief WDG write enable function + * + * @param [in] base WDG base address + */ +static inline void wdg_write_enable(WDG_Type *base) +{ + base->WREN = WDG_WRITE_ENABLE_MAGIC_NUM; +} + +/** + * @brief WDG Enable function + * + * @param [in] base WDG base address + */ +static inline void wdg_enable(WDG_Type *base) +{ + wdg_write_enable(base); + base->CTRL |= WDG_CTRL_EN_MASK; +} + +/** + * @brief WDG Disable function + * + * @param [in] base WDG base address + */ +static inline void wdg_disable(WDG_Type *base) +{ + wdg_write_enable(base); + base->CTRL &= ~WDG_CTRL_EN_MASK; +} + +/** + * @brief WDG reset enable function + * + * @param [in] base WDG base address + */ +static inline void wdg_reset_enable(WDG_Type *base) +{ + wdg_write_enable(base); + base->CTRL |= WDG_CTRL_RSTEN_MASK; +} + +/** + * @brief WDG reset disable function + * + * @param [in] base WDG base address + */ +static inline void wdg_reset_disable(WDG_Type *base) +{ + wdg_write_enable(base); + base->CTRL &= ~WDG_CTRL_RSTEN_MASK; +} + + +/** + * @brief WDG interrupt enable function + * + * @param [in] base WDG base address + */ +static inline void wdg_interrupt_enable(WDG_Type *base) +{ + wdg_write_enable(base); + base->CTRL |= WDG_CTRL_INTEN_MASK; +} + +/** + * @brief WDG interrupt disable function + * + * @param [in] base WDG base address + */ +static inline void wdg_interrupt_disable(WDG_Type *base) +{ + wdg_write_enable(base); + base->CTRL &= ~WDG_CTRL_INTEN_MASK; +} + +/** + * @brief WDG Clock Source selection function + * + * @param [in] base WDG base address + * @param [in] clksrc WDG clock source + * @arg wdg_clksrc_extclk External clock + * @arg wdg_clksrc_pclk Peripheral clock + */ +static inline void wdg_clksrc_select(WDG_Type *base, wdg_clksrc_t clksrc) +{ + if (clksrc == wdg_clksrc_extclk) { + base->CTRL &= ~WDG_CTRL_CLKSEL_MASK; + } + else { + base->CTRL |= WDG_CTRL_CLKSEL_MASK; + } +} + +/** + * @brief WDG restart function + * + * @param [in] base WDG base address + */ +static inline void wdg_restart(WDG_Type *base) +{ + wdg_write_enable(base); + base->RESTART = WDG_RESTART_MAGIC_NUM; +} + +/** + * @brief WDG Get Status function + * + * @param [in] base WDG base address + * @retval WDG status register value + */ +static inline uint32_t wdg_get_status(WDG_Type *base) +{ + return base->ST; +} + +/** + * @brief WDG clear status function + * + * @param [in] base WDG base address + * @param [in] status_mask WDG status mask value + */ +static inline void wdg_clear_status(WDG_Type *base, uint32_t status_mask) +{ + base->ST = status_mask; +} + +/** + * @brief WDG initialization function + * + * @param [in] base WDG base address + * @param [in] wdg_ctrl WDG control structure + * @retval API execution status + */ +hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl); + +/** + * @brief Convert the Reset interval value based on the WDG source clock frequency and the expected reset interval + * in terms of microseconds + * + * @param [in] src_freq WDG source clock frequency + * @param [in] reset_us Expected Reset interval in terms of microseconds + * @retval Converted WDG reset interval + */ +reset_interval_t wdg_convert_reset_interval_from_us(const uint32_t src_freq, const uint32_t reset_us); + +/** + * @brief Convert the interrupt interval value based on the WDG source clock frequency and the expected interrupt interval + * in terms of microseconds + * + * @param [in] src_freq WDG source clock frequency + * @param [in] interval_us Expected Interrupt interval in terms of microseconds + * @retval Converted WDG interrupt interval + */ +interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_freq, uint32_t interval_us); + +/** + * @brief Get Actual WDG Interrupt Interval in terms of microseconds + * + * @param [in] base WDG base address + * @param [in] src_freq WDG source clock frequency + * @return Converted WDG interrupt interval in terms of microseconds + */ +uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq); + +/** + * @brief Get Actual WDG Reset Interval in terms of microseconds + * + * @param [in] base WDG base address + * @param [in] src_freq WDG source clock frequency + * @return Converted WDG total reset interval in terms of microseconds + */ +uint32_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_WDG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c new file mode 100644 index 0000000000..3b2ed8cf80 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_acmp_drv.h" + +hpm_stat_t acmp_channel_config(ACMP_Type *ptr, uint8_t ch, acmp_channel_config_t *config, bool enable) +{ + acmp_channel_enable_cmp(ptr, ch, false); + ptr->CHANNEL[ch].CFG = ACMP_CHANNEL_CFG_CMPEN_SET(enable) + | ACMP_CHANNEL_CFG_MINSEL_SET(config->minus_input) + | ACMP_CHANNEL_CFG_PINSEL_SET(config->plus_input) + | ACMP_CHANNEL_CFG_FLTMODE_SET(config->filter_mode) + | ACMP_CHANNEL_CFG_HYST_SET(config->hyst_level) + | ACMP_CHANNEL_CFG_CMPOEN_SET(config->enable_cmp_output) + | ACMP_CHANNEL_CFG_WINEN_SET(config->enable_window_mode) + | ACMP_CHANNEL_CFG_OPOL_SET(config->invert_output) + | ACMP_CHANNEL_CFG_SYNCEN_SET(config->enable_clock_sync) + | ACMP_CHANNEL_CFG_FLTBYPS_SET(config->bypass_filter) + | ACMP_CHANNEL_CFG_DACEN_SET(config->enable_dac) + | ACMP_CHANNEL_CFG_HPMODE_SET(config->enable_hpmode) + | ACMP_CHANNEL_CFG_FLTLEN_SET(config->filter_length); + if (enable) { + acmp_channel_enable_cmp(ptr, ch, true); + } + return status_success; +} + +void acmp_channel_get_default_config(ACMP_Type *ptr, acmp_channel_config_t *config) +{ + config->plus_input = ACMP_INPUT_DAC_OUT; + config->minus_input = ACMP_INPUT_DAC_OUT; + config->filter_mode = ACMP_FILTER_MODE_BYPASS; + config->hyst_level = ACMP_HYST_LEVEL_0; + config->enable_cmp_output = false; + config->enable_window_mode = false; + config->invert_output = false; + config->enable_clock_sync = false; + config->bypass_filter = true; + config->enable_dac = false; + config->enable_hpmode = false; + config->filter_length = 0; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c new file mode 100644 index 0000000000..a8b0c2cd52 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_adc12_drv.h" +#include "hpm_soc_feature.h" + +void adc12_get_default_config(adc12_config_t *config) +{ + config->res = adc12_res_12_bits; + config->conv_mode = adc12_conv_mode_oneshot; + config->adc_clk_div = 1; + config->wait_dis = 0; + config->sel_sync_ahb = true; + config->adc_ahb_en = false; +} + +void adc12_get_channel_default_config(adc12_channel_config_t *config) +{ + config->ch = 0; + config->diff_sel = adc12_sample_signal_single_ended; + config->sample_cycle = 10; + config->sample_cycle_shift = 0; + config->thshdh = 0; + config->thshdl = 0; +} + +static hpm_stat_t adc12_do_calibration(ADC12_Type *ptr, adc12_sample_signal_t diff_sel) +{ + uint8_t cal_out; + uint32_t loop_cnt = ADC12_SOC_CALIBRATION_WAITING_LOOP_CNT; + + if (ADC12_IS_SIGNAL_TYPE_INVALID(diff_sel)) { + return status_invalid_argument; + } + + /*Set diff_sel temporarily */ + ptr->SAMPLE_CFG[0] = ADC12_SAMPLE_CFG_DIFF_SEL_SET(diff_sel); + + /* Set resetcal and resetadc */ + ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_RESETCAL_MASK; + + /* Clear resetcal and resetadc */ + ptr->ANA_CTRL0 &= ~(ADC12_ANA_CTRL0_RESETCAL_MASK | ADC12_ANA_CTRL0_RESETADC_MASK); + + /* Set startcal */ + ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_STARTCAL_MASK; + + /* Clear startcal */ + ptr->ANA_CTRL0 &= ~ADC12_ANA_CTRL0_STARTCAL_MASK; + + /* Set HW rearm_en */ + ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_REARM_EN_MASK; + + /* Polling calibration status */ + while (ADC12_ANA_STATUS_CALON_GET(ptr->ANA_STATUS) && loop_cnt--) { + /* TODO: Call a common delay function */ + } + + /* Check if the calibration is timeout */ + if (loop_cnt == 0) { + return status_timeout; + } + + /* Read calculation result */ + cal_out = ADC12_ANA_STATUS_CAL_OUT_GET(ptr->ANA_STATUS); + + /* Update cal_out */ + if (diff_sel == adc12_sample_signal_single_ended) { + ptr->ANA_CTRL0 = (ptr->ANA_CTRL0 & ~ADC12_ANA_CTRL0_CAL_VAL_SE_MASK) + | ADC12_ANA_CTRL0_CAL_VAL_SE_SET(cal_out); + } else { + ptr->ANA_CTRL0 = (ptr->ANA_CTRL0 & ~ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK) + | ADC12_ANA_CTRL0_CAL_VAL_DIFF_SET(cal_out); + } + + return status_success; +} + +hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) +{ + uint32_t adc_clk_div; + + /** + * disable adc + * When the adc is processing data, it will generate an error to initialize the adc again, + * so you need to shut down the adc before initializing it. + */ + + ptr->ANA_CTRL0 &= ~(ADC12_ANA_CTRL0_ENADC_MASK); + + /* Check the resolution */ + if (config->res > adc12_res_12_bits) { + return status_invalid_argument; + } + + /* Set resolution */ + ptr->ANA_CTRL1 = (ptr->ANA_CTRL1 & ~ADC12_ANA_CTRL1_SELRES_MASK) + | ADC12_ANA_CTRL1_SELRES_SET(config->res); + + /* Set convert clock number and clock period */ + if (config->adc_clk_div > ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) { + return status_invalid_argument; + } + + /* Set ADC minimum conversion cycle and ADC clock divider */ + ptr->CONV_CFG1 = ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(2 * config->res + 7) + | ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div); + + /* Set ADC Config0 */ + ptr->ADC_CFG0 = ADC12_ADC_CFG0_SEL_SYNC_AHB_SET(config->sel_sync_ahb) + | ADC12_ADC_CFG0_ADC_AHB_EN_SET(config->adc_ahb_en); + + /* Set wait_dis */ + if (config->conv_mode == adc12_conv_mode_oneshot) { + /* Set wait_dis */ + ptr->BUF_CFG0 = ADC12_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); + } + + /*------------------------------------------------------------------------------- + * Calibration + *------------------------------------------------------------------------------ + */ + /* Set enldo */ + ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_ENLDO_MASK; + + /* TODO: wait 20us after setting enlado for adc0~adc2 */ + + adc_clk_div = config->adc_clk_div; + + if (adc_clk_div == ADC12_SOC_CLOCK_CLK_DIV) { + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div + 1); + } + + /* Set enadc */ + ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_ENADC_MASK; + + /* Do a calibration for single-ended mode */ + adc12_do_calibration(ptr, adc12_sample_signal_single_ended); + + /* Do a calibration for differential mode */ + adc12_do_calibration(ptr, adc12_sample_signal_differential); + + /* Set ADC clock divider */ + if (adc_clk_div == ADC12_SOC_CLOCK_CLK_DIV) { + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div); + } + + /*------------------------------------------------------------------------------- + * End of calibration + *------------------------------------------------------------------------------*/ + + return status_success; +} + +hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config) +{ + /* Check the specified channel number */ + if (ADC12_IS_CHANNEL_INVALID(ptr, config->ch)) { + return status_invalid_argument; + } + + /* Set warning threshold */ + ptr->PRD_CFG[config->ch].PRD_THSHD_CFG = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(config->thshdh) + | ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(config->thshdl); + + /* Select single-ended mode or differential mode */ + /* Set ADC sample cycles multiple */ + /* Set ADC sample cycles */ + ptr->SAMPLE_CFG[config->ch] = ADC12_SAMPLE_CFG_DIFF_SEL_SET(config->diff_sel) + | ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(config->sample_cycle_shift) + | ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(config->sample_cycle); + + return status_success; +} + +hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *dma_config) +{ + /* Check the DMA buffer length */ + if (ADC12_IS_SEQ_DMA_BUFF_LEN_INVLAID(dma_config->buff_len_in_4bytes)) { + return status_invalid_argument; + } + + /* Reset ADC DMA */ + ptr->SEQ_DMA_CFG |= ADC12_SEQ_DMA_CFG_DMA_RST_MASK; + + /* Reset memory to clear all of cycle bits */ + memset(dma_config->start_addr, 0x00, dma_config->buff_len_in_4bytes * sizeof(uint32_t)); + + /* De-reset ADC DMA */ + ptr->SEQ_DMA_CFG &= ~ADC12_SEQ_DMA_CFG_DMA_RST_MASK; + + /* Set ADC DMA target address which should be 4-byte aligned */ + ptr->SEQ_DMA_ADDR = (uint32_t)dma_config->start_addr & ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK; + + /* Set ADC DMA memory dword length */ + ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC12_SEQ_DMA_CFG_BUF_LEN_MASK) + | ADC12_SEQ_DMA_CFG_BUF_LEN_SET(dma_config->buff_len_in_4bytes - 1); + + /* Set stop_en and stop_pos */ + if (dma_config->stop_en) { + ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC12_SEQ_DMA_CFG_STOP_POS_MASK) + | ADC12_SEQ_DMA_CFG_STOP_EN_MASK + | ADC12_SEQ_DMA_CFG_STOP_POS_SET(dma_config->stop_pos); + } + + return status_success; +} + +hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config) +{ + /* Check the specified channel number */ + if (ADC12_IS_CHANNEL_INVALID(ptr, config->ch)) { + return status_invalid_argument; + } + + /* Check the prescale */ + if (config->prescale > (ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK >> ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT)) { + return status_invalid_argument; + } + + /* Set periodic prescale */ + ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK) + | ADC12_PRD_CFG_PRD_CFG_PRESCALE_SET(config->prescale); + + + /* Set period count */ + ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC12_PRD_CFG_PRD_CFG_PRD_MASK) + | ADC12_PRD_CFG_PRD_CFG_PRD_SET(config->period_count); + + return status_success; +} + +void adc12_trigger_seq_by_sw(ADC12_Type *ptr) +{ + ptr->SEQ_CFG0 |= ADC12_SEQ_CFG0_SW_TRIG_MASK; +} + +/* Note: the sequence length can not be larger or equal than 2 in HPM6750EVK Revision A0 */ +hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config) +{ + /* Check sequence length */ + if (ADC12_IS_SEQ_LEN_INVLAID(config->seq_len)) { + return status_invalid_argument; + } + + ptr->SEQ_CFG0 = ADC12_SEQ_CFG0_SEQ_LEN_SET(config->seq_len - 1) + | ADC12_SEQ_CFG0_RESTART_EN_SET(config->restart_en) + | ADC12_SEQ_CFG0_CONT_EN_SET(config->cont_en) + | ADC12_SEQ_CFG0_SW_TRIG_EN_SET(config->sw_trig_en) + | ADC12_SEQ_CFG0_HW_TRIG_EN_SET(config->hw_trig_en); + + /* Set sequence queue */ + for (int i = 0; i < config->seq_len; i++) { + /* Check the specified channel number */ + if (ADC12_IS_CHANNEL_INVALID(ptr, config->queue[i].ch)) { + return status_invalid_argument; + } + + ptr->SEQ_QUE[i] = ADC12_SEQ_QUE_SEQ_INT_EN_SET(config->queue[i].seq_int_en) + | ADC12_SEQ_QUE_CHAN_NUM_4_0_SET(config->queue[i].ch); + } + + return status_success; +} + +hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config) +{ + uint32_t temp = 0; + + /* Check the specified trigger length */ + if (ADC12_IS_TRIG_LEN_INVLAID(config->trig_len)) { + return status_invalid_argument; + } + + temp |= ADC12_CONFIG_TRIG_LEN_SET(config->trig_len - 1); + + for (int i = 0; i < config->trig_len; i++) { + if (ADC12_IS_CHANNEL_INVALID(ptr, config->trig_ch)) { + return status_invalid_argument; + } + + temp |= config->inten[i] << (ADC12_CONFIG_INTEN0_SHIFT + i * ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE) + | config->adc_ch[i] << (ADC12_CONFIG_CHAN0_SHIFT + i * ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE); + } + + ptr->CONFIG[config->trig_ch] = temp; + + return status_success; +} + +hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result) +{ + /* Check the specified channel number */ + if (ADC12_IS_CHANNEL_INVALID(ptr, ch)) { + return status_invalid_argument; + } + + *result = ADC12_BUS_RESULT_CHAN_RESULT_GET(ptr->BUS_RESULT[ch]); + + return status_success; +} + +hpm_stat_t adc12_get_prd_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result) +{ + /* Check the specified channel number */ + if (ADC12_IS_CHANNEL_INVALID(ptr, ch)) { + return status_invalid_argument; + } + + *result = ptr->PRD_CFG[ch].PRD_RESULT; + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c new file mode 100644 index 0000000000..ca90cf24d0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_adc16_drv.h" +#include "hpm_soc_feature.h" + +void adc16_get_default_config(adc16_config_t *config) +{ + config->conv_mode = adc16_conv_mode_oneshot; + config->adc_clk_div = 1; + config->wait_dis = 0; + config->conv_duration = 0; + config->sel_sync_ahb = true; + config->port3_rela_time = false; + config->adc_ahb_en = false; +} + +void adc16_get_channel_default_config(adc16_channel_config_t *config) +{ + config->ch = 0; + config->sample_cycle = 10; + config->sample_cycle_shift = 0; + config->thshdh = 0; + config->thshdl = 0; +} + +static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) +{ + int i, j; + uint32_t clk_div_temp; + uint32_t adc16_params[ADC16_SOC_PARAMS_LEN]; + int32_t param01; + uint32_t param02; + uint64_t param64; + uint32_t param32; + uint32_t temp; + + /* Get input clock divider */ + clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); + + /* Set input clock divider temporarily */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); + + /* Enable ADC clock */ + ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + for (i = 0; i < ADC16_SOC_PARAMS_LEN; i++) { + adc16_params[i] = 0; + } + + /* Enable reg_en */ + /* Enable bandgap_en */ + ptr->ADC16_CONFIG0 |= ADC16_ADC16_CONFIG0_REG_EN_MASK + | ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK; + + /* Set cal_avg_cfg for 5 loops */ + ptr->ADC16_CONFIG0 = (ptr->ADC16_CONFIG0 & ~ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) + | ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(5); + + /* Enable ahb_en */ + ptr->ADC_CFG0 |= ADC16_ADC_CFG0_ADC_AHB_EN_MASK; + + /* Disable ADC clock */ + ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Recover input clock divider */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); + + for(j = 0; j < 4; j++) { + /* Set startcal */ + ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_STARTCAL_MASK; + + /* Clear startcal */ + ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_STARTCAL_MASK; + + /* Polling calibration status */ + while (ADC16_ANA_STATUS_CALON_GET(ptr->ANA_STATUS)) {} + + /* Read parameters */ + for (i = 0; i < ADC16_SOC_PARAMS_LEN; i++) { + adc16_params[i] += ADC16_ADC16_PARAMS_PARAM_VAL_GET(ptr->ADC16_PARAMS[i]); + } + } + + adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA33] -= 0x800; + param01 = adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA32] - adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA33]; + adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA32] = adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA00] - + adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA33]; + adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA00] = 0; + + for (i = 1; i < ADC16_SOC_PARAMS_LEN - 2; i++) { + adc16_params[i] = adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA32] + adc16_params[i] - + adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA33] + adc16_params[i - 1]; + } + + param02 = (param01 + adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA31] + adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA32]) >> 6; + param64 = 0x10000ll * param02; + param64 = param64 / (0x20000 - param02 / 2); + param32 = (uint32_t)param64; + + for (i = 0; i < ADC16_SOC_PARAMS_LEN; i++) { + adc16_params[i] >>= 6; + } + + /* Enable ADC clock */ + ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); + + /* Write parameters */ + for (i = 0; i < ADC16_SOC_PARAMS_LEN ; i++) { + ptr->ADC16_PARAMS[i] = (uint16_t)(adc16_params[i]); + } + + /* Set ADC16 Config0 */ + temp = ptr->ADC16_CONFIG0; + + temp &= ~(ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK | ADC16_ADC16_CONFIG0_CONV_PARAM_MASK); + + temp |= ADC16_ADC16_CONFIG0_REG_EN_MASK + | ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK + | ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK + | ADC16_ADC16_CONFIG0_CONV_PARAM_SET(param32); + + ptr->ADC16_CONFIG0 = temp; + + /* Recover input clock divider */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); + + /* Disable ADC clock */ + ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + return status_success; +} + +hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) +{ + /* Set convert clock number and clock period */ + if (config->adc_clk_div > ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) { + return status_invalid_argument; + } + + /* Set ADC minimum conversion cycle and ADC clock divider */ + ptr->CONV_CFG1 = ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(21) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div); + + /* Set ahb_en */ + /* Set convert duration */ + ptr->ADC_CFG0 = ADC16_ADC_CFG0_ADC_AHB_EN_SET(config->sel_sync_ahb) + | ADC16_ADC_CFG0_CONVERT_DURATION_SET(config->conv_duration); + + /* Set wait_dis */ + if (config->conv_mode == adc16_conv_mode_oneshot) { + /* Set wait_dis */ + ptr->BUF_CFG0 = ADC16_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); + } + + /* Do a calibration */ + adc16_do_calibration(ptr); + + return status_success; +} + +hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config) +{ + /* Check the specified channel number */ + if (ADC16_IS_CHANNEL_INVALID(config->ch)) { + return status_invalid_argument; + } + + /* Set warning threshold */ + ptr->PRD_CFG[config->ch].PRD_THSHD_CFG = ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(config->thshdh) + | ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(config->thshdl); + + /* Set ADC sample cycles multiple */ + /* Set ADC sample cycles */ + ptr->SAMPLE_CFG[config->ch] = ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(config->sample_cycle_shift) + | ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(config->sample_cycle); + + return status_success; +} + +void adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) +{ + /* Reset ADC DMA */ + ptr->SEQ_DMA_CFG |= ADC16_SEQ_DMA_CFG_DMA_RST_MASK; + + /* Reset memory to clear all of cycle bits */ + memset(dma_config->start_addr, 0x00, dma_config->buff_len_in_4bytes * sizeof(uint32_t)); + + /* De-reset ADC DMA */ + ptr->SEQ_DMA_CFG &= ~ADC16_SEQ_DMA_CFG_DMA_RST_MASK; + + /* Set ADC DMA target address which should be 4-byte aligned */ + ptr->SEQ_DMA_ADDR = (uint32_t)dma_config->start_addr & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK; + + /* Set ADC DMA memory dword length */ + ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) + | ADC16_SEQ_DMA_CFG_BUF_LEN_SET(dma_config->buff_len_in_4bytes); + + /* Set stop_en and stop_pos */ + if (dma_config->stop_en) { + ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_STOP_POS_MASK) + | ADC16_SEQ_DMA_CFG_STOP_EN_MASK + | ADC16_SEQ_DMA_CFG_STOP_POS_SET(dma_config->stop_pos); + } +} + +hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config) +{ + /* Check the specified channel number */ + if (ADC16_IS_CHANNEL_INVALID(config->ch)) { + return status_invalid_argument; + } + + if (config->prescale > (ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT)) { + return status_invalid_argument; + } + + /* periodic prescale */ + ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) + | ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(config->prescale); + + + /* Set period count */ + ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC16_PRD_CFG_PRD_CFG_PRD_MASK) + | ADC16_PRD_CFG_PRD_CFG_PRD_SET(config->period_count); + + return status_success; +} + +void adc16_trigger_seq_by_sw(ADC16_Type *ptr) +{ + ptr->SEQ_CFG0 |= ADC16_SEQ_CFG0_SW_TRIG_MASK; +} + +/* Note: the sequence length can not be larger or equal than 2 in HPM6750EVK Revision A0 */ +hpm_stat_t adc16_set_seq_config(ADC16_Type *ptr, adc16_seq_config_t *config) +{ + if (config->seq_len > ADC_SOC_SEQ_MAX_LEN) { + return status_invalid_argument; + } + + ptr->SEQ_CFG0 = ADC16_SEQ_CFG0_SEQ_LEN_SET(config->seq_len - 1) + | ADC16_SEQ_CFG0_RESTART_EN_SET(config->restart_en) + | ADC16_SEQ_CFG0_CONT_EN_SET(config->cont_en) + | ADC16_SEQ_CFG0_SW_TRIG_EN_SET(config->sw_trig_en) + | ADC16_SEQ_CFG0_HW_TRIG_EN_SET(config->hw_trig_en); + + /* Set sequence queue */ + for (int i = 0; i < config->seq_len; i++) { + /* Check the specified channel number */ + if (ADC16_IS_CHANNEL_INVALID(config->queue[i].ch)) { + return status_invalid_argument; + } + + ptr->SEQ_QUE[i] = ADC16_SEQ_QUE_SEQ_INT_EN_SET(config->queue[i].seq_int_en) + | ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(config->queue[i].ch); + } + + return status_success; +} + +hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config) +{ + uint32_t temp = 0; + + /* Check the specified trigger length */ + if (ADC16_IS_TRIG_LEN_INVLAID(config->trig_len)) { + return status_invalid_argument; + } + + temp |= ADC16_CONFIG_TRIG_LEN_SET(config->trig_len - 1); + + for (int i = 0; i < config->trig_len; i++) { + if (ADC16_IS_CHANNEL_INVALID(config->trig_ch)) { + return status_invalid_argument; + } + + temp |= config->inten[i] << (ADC16_CONFIG_INTEN0_SHIFT + i * ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE) + | config->adc_ch[i] << (ADC16_CONFIG_CHAN0_SHIFT + i * ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE); + } + + ptr->CONFIG[config->trig_ch] = temp; + + return status_success; +} + +hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool enable) +{ +#if ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT == 1 + /* Check the specified trigger channel */ + if (ADC16_IS_TRIG_CH_INVLAID(trig_ch)) { + return status_invalid_argument; + } + + /* Set queue enable control */ + ptr->CONFIG[trig_ch] |= ADC16_CONFIG_QUEUE_EN_SET(enable); + return status_success; +#else + return status_success; +#endif +} + +/* one shot mode */ +hpm_stat_t adc16_get_oneshot_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result) +{ + if (ADC16_IS_CHANNEL_INVALID(ch)) { + return status_invalid_argument; + } + + *result = ADC16_BUS_RESULT_CHAN_RESULT_GET(ptr->BUS_RESULT[ch]); + + return status_success; +} + +/* period mode */ +hpm_stat_t adc16_get_prd_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result) +{ + if (ADC16_IS_CHANNEL_INVALID(ch)) { + return status_invalid_argument; + } + + *result = ptr->PRD_CFG[ch].PRD_RESULT; + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c new file mode 100644 index 0000000000..e4bd1f3b4d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_cam_drv.h" + +#define CAM_RX_FIFO_THRESHOLD (6U) + +void cam_get_default_config(CAM_Type *ptr, cam_config_t *config, display_pixel_format_t pixel_format) +{ + config->width = 320; + config->height = 240; + config->pixclk_sampling_falling = false; + config->hsync_active_low = false; + config->vsync_active_low = false; + config->color_ext = false; + config->data_pack_msb = false; + config->enable_buffer2 = false; + config->data_store_mode = CAM_DATA_STORE_MODE_NORMAL; + config->color_format = CAM_COLOR_FORMAT_RGB565; + config->sensor_bitwidth = CAM_SENSOR_BITWIDTH_10BITS; + + switch(pixel_format) { + case display_pixel_format_yuv422: + config->csc_config.enable = true; + config->csc_config.ycbcr_mode = false; + config->csc_config.yuv2rgb_coef.c0 = 0x100; + config->csc_config.yuv2rgb_coef.uv_offset = 0; + config->csc_config.yuv2rgb_coef.y_offset = 0; + config->csc_config.yuv2rgb_coef.c1 = 0x123; + config->csc_config.yuv2rgb_coef.c2 = 0x76B; + config->csc_config.yuv2rgb_coef.c3 = 0x79C; + config->csc_config.yuv2rgb_coef.c4 = 0x208; + break; + case display_pixel_format_ycbcr422: + config->csc_config.enable = true; + config->csc_config.ycbcr_mode = true; + config->csc_config.yuv2rgb_coef.c0 = 0x12A; + config->csc_config.yuv2rgb_coef.uv_offset = 0x180; + config->csc_config.yuv2rgb_coef.y_offset = 0x1F0; + config->csc_config.yuv2rgb_coef.c1 = 0x198; + config->csc_config.yuv2rgb_coef.c2 = 0x730; + config->csc_config.yuv2rgb_coef.c3 = 0x79C; + config->csc_config.yuv2rgb_coef.c4 = 0x204; + break; + default: + config->csc_config.enable = false; + config->csc_config.ycbcr_mode = false; + config->csc_config.yuv2rgb_coef.c0 = 0; + config->csc_config.yuv2rgb_coef.uv_offset = 0; + config->csc_config.yuv2rgb_coef.y_offset = 0; + config->csc_config.yuv2rgb_coef.c1 = 0; + config->csc_config.yuv2rgb_coef.c2 = 0; + config->csc_config.yuv2rgb_coef.c3 = 0; + config->csc_config.yuv2rgb_coef.c4 = 0; + break; + } +} + +void cam_reset(CAM_Type *ptr) +{ + cam_stop(ptr); + ptr->CR1 = CAM_CR1_ASYNC_RXFIFO_CLR_MASK; + ptr->INT_EN = 0; + ptr->CR2 = CAM_CR2_FRMCNT_RST_MASK; + ptr->STA = 0xFFFFFFFF; + ptr->CR20 = 0; +} + +hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) +{ + hpm_stat_t stat = status_success; + + cam_reset(ptr); + + ptr->CR1 = CAM_CR1_INV_PIXCLK_SET(config->pixclk_sampling_falling) + | CAM_CR1_INV_HSYNC_SET(config->hsync_active_low) + | CAM_CR1_INV_VSYNC_SET(config->vsync_active_low) + | CAM_CR1_RESTART_BUSPTR_MASK + | CAM_CR1_COLOR_EXT_SET(config->color_ext) + | CAM_CR1_PACK_DIR_SET(config->data_pack_msb) + | config->data_store_mode + | config->color_format + | config->sensor_bitwidth; + + ptr->IDEAL_WN_SIZE = CAM_IDEAL_WN_SIZE_HEIGHT_SET(config->height) + | CAM_IDEAL_WN_SIZE_WIDTH_SET(config->width); + + ptr->MAX_WN_CYCLE = CAM_MAX_WN_CYCLE_ROW_SET(1200) + | CAM_MAX_WN_CYCLE_COL_SET(2090); + + ptr->CR2 = CAM_CR2_DMA_REQ_EN_RFF_MASK + | CAM_CR2_RXFF_LEVEL_SET(CAM_RX_FIFO_THRESHOLD); + ptr->DMASA_FB1 = config->buffer1; + if (config->enable_buffer2) { + ptr->DMASA_FB2 = config->buffer2; + } + + ptr->CSC_COEF0 = CAM_CSC_COEF0_ENABLE_SET(config->csc_config.enable) + | CAM_CSC_COEF0_YCBCR_MODE_SET(config->csc_config.ycbcr_mode) + | CAM_CSC_COEF0_C0_SET(config->csc_config.yuv2rgb_coef.c0) + | CAM_CSC_COEF0_UV_OFFSET_SET(config->csc_config.yuv2rgb_coef.uv_offset) + | CAM_CSC_COEF0_Y_OFFSET_SET(config->csc_config.yuv2rgb_coef.y_offset); + ptr->CSC_COEF1 = CAM_CSC_COEF1_C1_SET(config->csc_config.yuv2rgb_coef.c1) + | CAM_CSC_COEF1_C4_SET(config->csc_config.yuv2rgb_coef.c4); + ptr->CSC_COEF2 = CAM_CSC_COEF2_C2_SET(config->csc_config.yuv2rgb_coef.c2) + | CAM_CSC_COEF2_C3_SET(config->csc_config.yuv2rgb_coef.c3); + + return stat; +} + +void cam_stop(CAM_Type *ptr) +{ + ptr->CR18 &= ~CAM_CR18_CAM_ENABLE_MASK; +} + +void cam_start(CAM_Type *ptr) +{ + ptr->CR18 |= CAM_CR18_CAM_ENABLE_MASK; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c new file mode 100644 index 0000000000..c52908c32b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c @@ -0,0 +1,732 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_can_drv.h" +#include + +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ +#define TSEG1_MIN_FOR_CAN2_0 (2U) +#define TSEG1_MAX_FOR_CAN2_0 (65U) + +#define TSEG1_MIN_FOR_CANFD_NORMINAL (2U) +#define TSEG1_MAX_FOR_CANFD_NORMINAL (65U) + +#define TSEG1_MIN_FOR_CANFD_DATA (2U) +#define TSEG1_MAX_FOR_CANFD_DATA (17U) + +#define TSEG2_MIN_FOR_CAN2_0 (1U) +#define TSEG2_MAX_FOR_CAN2_0 (8U) + +#define TSEG2_MIN_FOR_CANFD_NORMINAL (1U) +#define TSEG2_MAX_FOR_CANFD_NORMINAL (32U) + +#define TSEG2_MIN_FOR_CANFD_DATA (1U) +#define TSEG2_MAX_FOR_CANFD_DATA (8U) + +#define TSJW_MIN_FOR_CAN2_0 (1U) +#define TSJW_MAX_FOR_CAN2_0 (16U) + +#define TSJW_MIN_FOR_CANFD_NORMINAL (1U) +#define TSJW_MAX_FOR_CANFD_NORMINAL (16U) + +#define TSJW_MIN_FOR_CANFD_DATA (1U) +#define TSJW_MAX_FOR_CANFD_DATA (8U) + +#define NUM_TQ_MIN_FOR_CAN2_0 (8U) +#define NUM_TQ_MAX_FOR_CAN2_0 (TSEG1_MAX_FOR_CAN2_0 + TSEG2_MAX_FOR_CAN2_0) + +#define NUM_TQ_MIN_FOR_CANFD_NOMINAL (8U) +#define NUM_TQ_MAX_FOR_CANFD_NOMINAL (TSEG1_MAX_FOR_CANFD_NORMINAL + TSEG2_MAX_FOR_CANFD_NORMINAL) + +#define NUM_TQ_MIN_FOR_CANFD_DATA (8U) +#define NUM_TQ_MAX_FOR_CANFD_DATA (TSEG1_MAX_FOR_CANFD_DATA + TSEG2_MAX_FOR_CANFD_DATA) + +#define MIN_TQ_MUL_PRESCALE (10U) + +#define NUM_PRESCALE_MAX (256U) + +#define CAN_FILTER_INDEX_MAX (15U) +#define CAN_FILTER_NUM_MAX (16U) + +#define PRESCALER_MAX (256U) + +#define CAN_TIMEOUT_CNT (0xFFFFFFUL) + +#define CAN_SAMPLEPOINT_MIN (750U) +#define CAN_SAMPLEPOINT_MAX (875U) + + +#define CAN_DEFAULT_FILTER_SETTING {0, can_filter_id_mode_both_frames, true, 0, (1UL << 29) - 1U } + +/* + * @brief CAN bit-timing table + */ +typedef struct { + uint8_t tq_min; + uint8_t tq_max; + uint8_t seg1_min; + uint8_t seg1_max; + uint8_t seg2_min; + uint8_t seg2_max; + uint8_t sjw_min; + uint8_t sjw_max; + uint8_t min_diff_seg1_minus_seg2; +} can_bit_timing_table_t; + +/** + * @brief CAN bit timing list for all supported bit timing modes + */ +static const can_bit_timing_table_t s_can_bit_timing_tbl[3] = + { + { + .tq_min = NUM_TQ_MIN_FOR_CAN2_0, + .tq_max = NUM_TQ_MAX_FOR_CAN2_0, + .seg1_min = TSEG1_MIN_FOR_CAN2_0, + .seg1_max = TSEG1_MAX_FOR_CAN2_0, + .seg2_min = TSEG2_MIN_FOR_CAN2_0, + .seg2_max = TSEG2_MAX_FOR_CAN2_0, + .sjw_min = TSJW_MIN_FOR_CAN2_0, + .sjw_max = TSJW_MAX_FOR_CAN2_0, + .min_diff_seg1_minus_seg2 = 2, + }, + { + .tq_min = NUM_TQ_MIN_FOR_CANFD_NOMINAL, + .tq_max = NUM_TQ_MAX_FOR_CANFD_NOMINAL, + .seg1_min = TSEG1_MIN_FOR_CANFD_NORMINAL, + .seg1_max = TSEG1_MAX_FOR_CANFD_NORMINAL, + .seg2_min = TSEG2_MIN_FOR_CANFD_NORMINAL, + .seg2_max = TSEG2_MAX_FOR_CANFD_NORMINAL, + .sjw_min = TSJW_MIN_FOR_CANFD_NORMINAL, + .sjw_max = TSJW_MAX_FOR_CANFD_NORMINAL, + .min_diff_seg1_minus_seg2 = 2, + }, + { + .tq_min = NUM_TQ_MIN_FOR_CANFD_DATA, + .tq_max = NUM_TQ_MAX_FOR_CANFD_DATA, + .seg1_min = TSEG1_MIN_FOR_CANFD_DATA, + .seg1_max = TSEG1_MAX_FOR_CANFD_DATA, + .seg2_min = TSEG2_MIN_FOR_CANFD_DATA, + .seg2_max = TSEG2_MAX_FOR_CANFD_DATA, + .sjw_min = TSJW_MIN_FOR_CANFD_DATA, + .sjw_max = TSJW_MAX_FOR_CANFD_DATA, + .min_diff_seg1_minus_seg2 = 1, + } + }; + +/*********************************************************************************************************************** + * + * Prototypes + */ +static uint32_t find_closest_prescaler(uint32_t num_tq_mul_prescaler, uint32_t start_prescaler, + uint32_t max_tq, uint32_t min_tq); + +static uint8_t can_get_data_words_from_dlc(uint32_t dlc); + +static void can_fill_tx_buffer(CAN_Type *base, const can_transmit_buf_t *message); + + +/*********************************************************************************************************************** + * + * Codes + */ +static uint32_t find_closest_prescaler(uint32_t num_tq_mul_prescaler, uint32_t start_prescaler, + uint32_t max_tq, uint32_t min_tq) +{ + bool has_found = false; + + uint32_t prescaler = start_prescaler; + + while (!has_found) { + + if ((num_tq_mul_prescaler / prescaler > max_tq) || (num_tq_mul_prescaler % prescaler != 0)) { + ++prescaler; + continue; + } else { + has_found = true; + break; + } + uint32_t tq = num_tq_mul_prescaler / prescaler; + if (tq * prescaler == num_tq_mul_prescaler) { + has_found = true; + break; + } else if (tq < min_tq) { + has_found = false; + break; + } + } + + return has_found ? prescaler : 0U; +} + + +hpm_stat_t can_calculate_bit_timing(uint32_t src_clk_freq, can_bit_timing_option_t option, uint32_t baudrate, + uint16_t samplepoint_min, uint16_t samplepoint_max, + can_bit_timing_param_t *timing_param) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((option > can_bit_timing_canfd_data) || (baudrate == 0U) || + (src_clk_freq / baudrate < MIN_TQ_MUL_PRESCALE) || (timing_param == NULL)) { + break; + } + + const can_bit_timing_table_t *tbl = &s_can_bit_timing_tbl[(uint8_t) option]; + + /* According to the CAN specification 2.0, + * the Tq must be in range specified in the above CAN bit-timing table + */ + if (src_clk_freq / baudrate < tbl->tq_min) { + break; + } + + uint32_t num_tq_mul_prescaler = src_clk_freq / baudrate; + uint32_t start_prescaler = 1U; + uint32_t num_seg1, num_seg2; + bool has_found = false; + + /* Find out the minimum prescaler */ + uint32_t current_prescaler; + while (!has_found) { + current_prescaler = find_closest_prescaler(num_tq_mul_prescaler, start_prescaler, + tbl->tq_max, + tbl->tq_min); + if ((current_prescaler < start_prescaler) || (current_prescaler > NUM_PRESCALE_MAX)) { + break; + } + uint32_t num_tq = num_tq_mul_prescaler / current_prescaler; + + num_seg2 = (num_tq - tbl->min_diff_seg1_minus_seg2) / 2U; + num_seg1 = num_tq - num_seg2; + while (num_seg2 > tbl->seg2_max) { + num_seg2--; + num_seg1++; + } + + /* Recommended sample point is 75% - 87.5% */ + while ((num_seg1 * 1000U) / num_tq < samplepoint_min) { + ++num_seg1; + --num_seg2; + } + + if ((num_seg1 * 1000U) / num_tq > samplepoint_max) { + break; + } + + if ((num_seg2 >= tbl->seg2_min) && (num_seg1 <= tbl->seg1_max)) { + has_found = true; + } else { + start_prescaler = current_prescaler + 1U; + } + } + + if (has_found) { + uint32_t num_sjw = MIN(tbl->sjw_max, num_seg2); + timing_param->num_seg1 = num_seg1; + timing_param->num_seg2 = num_seg2; + timing_param->num_sjw = num_sjw; + timing_param->prescaler = current_prescaler; + status = status_success; + } + } while (false); + + return status; +} + + +hpm_stat_t can_set_bit_timing(CAN_Type *base, can_bit_timing_option_t option, + uint32_t src_clk_freq, uint32_t baudrate, + uint16_t samplepoint_min, uint16_t samplepoint_max) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if (base == NULL) { + break; + } + + can_bit_timing_param_t timing_param; + status = can_calculate_bit_timing(src_clk_freq, option, baudrate, samplepoint_min, samplepoint_max, &timing_param); + + if (status == status_success) { + if (option < can_bit_timing_canfd_data) { + base->S_PRESC = CAN_S_PRESC_S_PRESC_SET(timing_param.prescaler - 1U) | CAN_S_PRESC_S_SEG_1_SET(timing_param.num_seg1 - 2U) | + CAN_S_PRESC_S_SEG_2_SET(timing_param.num_seg2 - 1U) | CAN_S_PRESC_S_SJW_SET(timing_param.num_sjw - 1U); + } else { + base->F_PRESC = CAN_F_PRESC_F_PRESC_SET(timing_param.prescaler - 1U) | CAN_F_PRESC_F_SEG_1_SET(timing_param.num_seg1 - 2U) | + CAN_F_PRESC_F_SEG_2_SET(timing_param.num_seg2 - 1U) | CAN_F_PRESC_F_SJW_SET(timing_param.num_sjw - 1U); + + } + status = status_success; + } + + } while (false); + + return status; +} + +hpm_stat_t can_set_filter(CAN_Type *base, const can_filter_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((base == NULL) || (config == NULL)) { + break; + } + if (config->index > CAN_FILTER_INDEX_MAX) { + status = status_can_filter_index_invalid; + break; + } + + /* Configure acceptance code */ + base->ACFCTRL = CAN_ACFCTRL_ACFADR_SET(config->index); + base->ACF = CAN_ACF_CODE_MASK_SET(config->code); + + /* Configure acceptance mask */ + uint32_t acf_value = CAN_ACF_CODE_MASK_SET(config->mask); + if (config->id_mode == can_filter_id_mode_standard_frames) { + acf_value |= CAN_ACF_AIDEE_MASK; + } else if (config->id_mode == can_filter_id_mode_extended_frames) { + acf_value |= CAN_ACF_AIDEE_MASK | CAN_ACF_AIDE_MASK; + } else { + /* Treat it as the default mode */ + acf_value |= 0; + } + + base->ACFCTRL = CAN_ACFCTRL_SELMASK_MASK | CAN_ACFCTRL_ACFADR_SET(config->index); + base->ACF = acf_value; + + if (config->enable) { + base->ACF_EN |= (1U << config->index); + } else { + base->ACF_EN &= (uint16_t) ~(1U << config->index); + } + status = status_success; + } while (false); + + return status; +} + +static uint8_t can_get_data_words_from_dlc(uint32_t dlc) +{ + uint32_t copy_words = 0; + + dlc &= 0xFU; + if (dlc <= 8U) { + copy_words = (dlc + 3U) / sizeof(uint32_t); + } else { + switch (dlc) { + case can_payload_size_12: + copy_words = 3U; + break; + case can_payload_size_16: + copy_words = 4U; + break; + case can_payload_size_20: + copy_words = 5U; + break; + case can_payload_size_24: + copy_words = 6U; + break; + case can_payload_size_32: + copy_words = 8U; + break; + case can_payload_size_48: + copy_words = 12U; + break; + case can_payload_size_64: + copy_words = 16U; + break; + default: + /* Code should never touch here */ + break; + } + } + + return copy_words; +} + +static void can_fill_tx_buffer(CAN_Type *base, const can_transmit_buf_t *message) +{ + base->TBUF[0] = message->buffer[0]; + base->TBUF[1] = message->buffer[1]; + + uint32_t copy_words = can_get_data_words_from_dlc(message->dlc); + for (uint32_t i = 0U; i < copy_words; i++) { + base->TBUF[2U + i] = message->buffer[2U + i]; + } +} + +hpm_stat_t can_send_message_blocking(CAN_Type *base, const can_transmit_buf_t *message) +{ + hpm_stat_t status = status_invalid_argument; + + do { + + if ((base == NULL) || (message == NULL)) { + break; + } + + status = status_success; + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; + + can_fill_tx_buffer(base, message); + + /* Wait until STB is not full */ + int32_t timeout_cnt = CAN_TIMEOUT_CNT; + while (CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL) == CAN_STB_IS_FULL) { + timeout_cnt--; + if (timeout_cnt <= 0) { + status = status_timeout; + break; + } + } + if (status != status_success) { + break; + } + + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK | CAN_CMD_STA_CMD_CTRL_TSONE_MASK; + timeout_cnt = CAN_TIMEOUT_CNT; + while (CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL) != CAN_STB_IS_EMPTY) { + timeout_cnt--; + if (timeout_cnt <= 0) { + status = status_timeout; + break; + } + } + + } while (false); + + return status; +} + +hpm_stat_t can_send_high_priority_message_blocking(CAN_Type *base, const can_transmit_buf_t *message) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF ((base == NULL) || (message == NULL)); + status = status_success; + + /* Select the high-priority buffer */ + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; + + can_fill_tx_buffer(base, message); + + /* Send the data out */ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPE_MASK; + /* Wait until the data is sent out */ + int32_t timeout_cnt = CAN_TIMEOUT_CNT; + while (IS_HPM_BITMASK_SET(base->CMD_STA_CMD_CTRL, CAN_CMD_STA_CMD_CTRL_TPE_MASK)) { + timeout_cnt--; + if (timeout_cnt <= 0) { + status = status_timeout; + break; + } + } + } while (false); + + return status; +} + +hpm_stat_t can_send_message_nonblocking(CAN_Type *base, const can_transmit_buf_t *message) +{ + hpm_stat_t status = status_invalid_argument; + + do { + + if ((base == NULL) || (message == NULL)) { + break; + } + + if (CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL) == CAN_STB_IS_FULL) { + status = status_can_tx_fifo_full; + break; + } + + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; + can_fill_tx_buffer(base, message); + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK | CAN_CMD_STA_CMD_CTRL_TSONE_MASK; + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t can_send_high_priority_message_nonblocking(CAN_Type *base, const can_transmit_buf_t *message) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF((base == NULL) || (message == NULL)); + status = status_success; + + if (IS_HPM_BITMASK_SET(base->CMD_STA_CMD_CTRL, CAN_CMD_STA_CMD_CTRL_TPE_MASK)) { + status = status_can_tx_fifo_full; + break; + } + /* Select the high-priority buffer */ + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; + + can_fill_tx_buffer(base, message); + + /* Send the data out */ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPE_MASK; + } while (false); + + return status; +} + +hpm_stat_t can_receive_message_blocking(CAN_Type *base, can_receive_buf_t *message) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF ((base == NULL) || (message == NULL)); + + while (CAN_CMD_STA_CMD_CTRL_RSTAT_GET(base->CMD_STA_CMD_CTRL) == CAN_RXBUF_IS_EMPTY) { + + } + + /* Get the first 2 words (including CAN ID, Data length and other control bits) */ + message->buffer[0] = base->RBUF[0]; + message->buffer[1] = base->RBUF[1]; + + if (message->error_type != 0U) { + switch (message->error_type) { + case 1: + status = status_can_bit_error; + break; + case 2: + status = status_can_form_error; + break; + case 3: + status = status_can_stuff_error; + break; + case 4: + status = status_can_ack_error; + break; + case 5: + status = status_can_crc_error; + break; + default: + status = status_can_other_error; + break; + } + break; + } + + if (message->remote_frame == 0U) { + uint32_t copy_words = can_get_data_words_from_dlc(message->dlc); + + for (uint32_t i = 0; i < copy_words; i++) { + message->buffer[2U + i] = base->RBUF[2U + i]; + } + } + /* Release the current buffer */ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RREL_MASK; + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t can_read_received_message(CAN_Type *base, can_receive_buf_t *message) +{ + hpm_stat_t status; + + assert((base != NULL) && (message != NULL)); + + do { + /* Get the first 2 words (including CAN ID, Data length and other control bits) */ + message->buffer[0] = base->RBUF[0]; + message->buffer[1] = base->RBUF[1]; + + if (message->error_type != 0U) { + switch (message->error_type) { + case 1: + status = status_can_bit_error; + break; + case 2: + status = status_can_form_error; + break; + case 3: + status = status_can_stuff_error; + break; + case 4: + status = status_can_ack_error; + break; + case 5: + status = status_can_crc_error; + break; + default: + status = status_can_other_error; + break; + } + break; + } + + if (message->remote_frame == 0U) { + uint32_t copy_words = can_get_data_words_from_dlc(message->dlc); + + for (uint32_t i = 0; i < copy_words; i++) { + message->buffer[2U + i] = base->RBUF[2U + i]; + } + } + /* Release the current buffer */ + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RREL_MASK; + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t can_get_default_config(can_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + if (config != NULL) { + + /* Default timing mode */ + config->baudrate = 1000000UL; /* 1Mbit/s */ + config->baudrate_fd = 0U; + config->use_lowlevel_timing_setting = false; + config->can20_samplepoint_min = CAN_SAMPLEPOINT_MIN; + config->can20_samplepoint_max = CAN_SAMPLEPOINT_MAX; + config->canfd_samplepoint_min = CAN_SAMPLEPOINT_MIN; + config->canfd_samplepoint_max = CAN_SAMPLEPOINT_MAX; + config->enable_canfd = false; + config->enable_can_fd_iso_mode = true; + + config->mode = can_mode_normal; + config->enable_self_ack = false; + config->disable_re_transmission_for_stb = false; + config->disable_re_transmission_for_ptb = false; + config->enable_tx_buffer_priority_mode = false; + config->enable_tdc = false; + + /* Default filter settings */ + config->filter_list_num = 0; + config->filter_list = NULL; + + /* Default Interrupt enable settings */ + config->irq_txrx_enable_mask = 0; + config->irq_error_enable_mask = 0; + + status = status_success; + } + + return status; +} + +hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) +{ + hpm_stat_t status = status_invalid_argument; + + do { + + HPM_BREAK_IF((base == NULL) || (config == NULL) || (src_clk_freq == 0U) || (config->filter_list_num > 16U)); + + can_reset(base, true); + + base->TTCFG &= ~CAN_TTCFG_TTEN_MASK; + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TTTBM_MASK; + + if (!config->use_lowlevel_timing_setting) { + if (config->enable_canfd) { + status = can_set_bit_timing(base, can_bit_timing_canfd_norminal, + src_clk_freq, config->baudrate, + config->can20_samplepoint_min, config->can20_samplepoint_max); + HPM_BREAK_IF(status != status_success); + status = can_set_bit_timing(base, can_bit_timing_canfd_data, + src_clk_freq, config->baudrate_fd, + config->canfd_samplepoint_min, config->canfd_samplepoint_max); + } else { + status = can_set_bit_timing(base, can_bit_timing_can2_0, + src_clk_freq, config->baudrate, + config->can20_samplepoint_min, config->can20_samplepoint_max); + } + } else { + can_set_slow_speed_timing(base, &config->can_timing); + if (config->enable_canfd) { + can_set_fast_speed_timing(base, &config->canfd_timing); + } + status = status_success; + } + + /* Enable Transmitter Delay Compensation as needed */ + uint32_t ssp_offset = CAN_F_PRESC_F_SEG_1_GET(base->F_PRESC) + 2U; + can_set_transmitter_delay_compensation(base, ssp_offset, config->enable_tdc); + + HPM_BREAK_IF(status != status_success); + + if (config->disable_re_transmission_for_ptb) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPSS_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TPSS_MASK; + } + + if (config->disable_re_transmission_for_stb) { + base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSSS_MASK; + } else { + base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TSSS_MASK; + } + + can_enable_self_ack(base, config->enable_self_ack); + + /* Configure CAN filters */ + if (config->filter_list_num > CAN_FILTER_NUM_MAX) { + status = status_can_filter_num_invalid; + break; + } else if (config->filter_list_num == 0) { + can_filter_config_t default_filter = CAN_DEFAULT_FILTER_SETTING; + for (uint32_t i = 0; i < CAN_FILTER_NUM_MAX; i++) { + can_disable_filter(base, i); + } + (void) can_set_filter(base, &default_filter); + } else { + for (uint32_t i = 0; i < CAN_FILTER_NUM_MAX; i++) { + can_disable_filter(base, i); + } + for (uint32_t i = 0; i < config->filter_list_num; i++) { + status = can_set_filter(base, &config->filter_list[i]); + if (status != status_success) { + return status; + } + } + } + + /* Set CAN FD standard */ + can_enable_can_fd_iso_mode(base, config->enable_can_fd_iso_mode); + + can_reset(base, false); + + /* Set CAN work mode */ + can_set_mode(base, config->mode); + + /* Configure TX Buffer priority mode */ + can_select_tx_buffer_priority_mode(base, config->enable_tx_buffer_priority_mode); + + /* Configure interrupt */ + can_disable_tx_rx_irq(base, 0xFFU); + can_disable_error_irq(base, 0xFFU); + can_enable_tx_rx_irq(base, config->irq_txrx_enable_mask); + can_enable_error_irq(base, config->irq_error_enable_mask); + + status = status_success; + } while (false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c new file mode 100644 index 0000000000..32db96de46 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_dac_drv.h" + +ATTR_PLACE_AT_NONCACHEABLE_BSS static uint32_t dac_cfg0; + +void dac_get_default_config(dac_config_t *config) +{ + config->sync_mode = false; + config->dac_mode = dac_mode_direct; + config->clk_dac_div = dac_ana_div_2; + config->div_cfg = 167; +} + +hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config) +{ + if (config->dac_mode > dac_mode_buffer) { + return status_invalid_argument; + } + + if (config->clk_dac_div > dac_ana_div_8) { + return status_invalid_argument; + } + + /* reset DAC output data */ + dac_cfg0 &= ~DAC_CFG0_SW_DAC_DATA_MASK; + + /* set sync mode */ + dac_cfg0 &= ~DAC_CFG0_SYNC_MODE_MASK; + dac_cfg0 |= DAC_CFG0_SYNC_MODE_SET(config->sync_mode); + + /* set DAC mode */ + dac_cfg0 &= ~DAC_CFG0_DAC_MODE_MASK; + dac_cfg0 |= DAC_CFG0_DAC_MODE_SET(config->dac_mode); + + /* refresh the CFG0 */ + ptr->CFG0 = dac_cfg0; + + /* set DAC clock config */ + ptr->CFG1 &= ~DAC_CFG1_ANA_DIV_CFG_MASK; + ptr->CFG1 |= DAC_CFG1_ANA_DIV_CFG_SET(config->clk_dac_div); + + if (config->dac_mode == dac_mode_direct) { + /* set ANA_CLK_EN */ + ptr->CFG1 |= DAC_CFG1_ANA_CLK_EN_MASK; + } + + return status_success; +} + +hpm_stat_t dac_set_step_config(DAC_Type *ptr, uint8_t step_cfg_idx, dac_step_config_t *config) +{ + uint16_t temp; + + /* check the validity */ + if (step_cfg_idx > DAC_STEP_CFG_STEP3) { + return status_invalid_argument; + } + + if (config->up_down == dac_step_up) { + if (config->start_point > config->end_point) { + return status_invalid_argument; + } + } else { + if (config->start_point < config->end_point) { + return status_invalid_argument; + } + } + + /* check if the output data can reach the end point */ + if (config->step_num != 0) { + if (config->start_point <= config->end_point) { + temp = config->end_point - config->start_point; + } else { + temp = config->start_point - config->end_point; + } + + if (temp % config->step_num != 0) { + return status_invalid_argument; + } + } + + /* set the round mode */ + ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_ROUND_MODE_MASK; + ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_ROUND_MODE_SET(config->round_mode); + + /* set the step direction */ + ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_UP_DOWN_MASK; + ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_UP_DOWN_SET(config->up_down); + + /* set the start point */ + ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_START_POINT_MASK; + ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_START_POINT_SET(config->start_point); + + /* set the end point */ + ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_END_POINT_MASK; + ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_END_POINT_SET(config->end_point); + + /* set the step value */ + ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_STEP_NUM_MASK; + ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_STEP_NUM_SET(config->step_num); + + return status_success; +} + +hpm_stat_t dac_set_buffer_config(DAC_Type *ptr, dac_buffer_config_t *config) +{ + if (config->buf0.len == 0) { + return status_invalid_argument; + } + + /* disable the internal DMA */ + dac_cfg0 &= ~DAC_CFG0_DMA_AHB_EN_MASK; + + /* refresh the CFG0 */ + ptr->CFG0 = dac_cfg0; + + /* set buffer data mode */ + dac_cfg0 &= ~DAC_CFG0_BUF_DATA_MODE_MASK; + dac_cfg0 |= DAC_CFG0_BUF_DATA_MODE_SET(config->buf_data_mode); + + /* set burst type */ + dac_cfg0 &= ~DAC_CFG0_HBURST_CFG_MASK; + dac_cfg0 |= DAC_CFG0_HBURST_CFG_SET(config->burst); + + /* reset DMA and FIFO */ + ptr->CFG2 |= DAC_CFG2_DMA_RST1_MASK | DAC_CFG2_DMA_RST0_MASK | DAC_CFG2_FIFO_CLR_MASK; + + /* set buffer 0 start address for DMA */ + ptr->BUF_ADDR[DAC_BUF_ADDR_BUF0] &= ~DAC_BUF_ADDR_BUF_START_ADDR_MASK; + ptr->BUF_ADDR[DAC_BUF_ADDR_BUF0] |= config->buf0.start_addr & DAC_BUF_ADDR_BUF_START_ADDR_MASK; + + /* set buffer 0 stop */ + ptr->BUF_ADDR[DAC_BUF_ADDR_BUF0] &= ~DAC_BUF_ADDR_BUF_STOP_MASK; + ptr->BUF_ADDR[DAC_BUF_ADDR_BUF0] |= DAC_BUF_ADDR_BUF_STOP_SET(config->buf0.stop); + + /* set buffer 0 length */ + ptr->BUF_LENGTH &= ~DAC_BUF_LENGTH_BUF0_LEN_MASK; + ptr->BUF_LENGTH |= DAC_BUF_LENGTH_BUF0_LEN_SET(config->buf0.len - 1); + + /* set buffer 1 start address for DMA */ + ptr->BUF_ADDR[DAC_BUF_ADDR_BUF1] &= ~DAC_BUF_ADDR_BUF_START_ADDR_MASK; + ptr->BUF_ADDR[DAC_BUF_ADDR_BUF1] |= config->buf1.start_addr & DAC_BUF_ADDR_BUF_START_ADDR_MASK; + + /* set buffer 1 stop */ + ptr->BUF_ADDR[DAC_BUF_ADDR_BUF1] &= ~DAC_BUF_ADDR_BUF_STOP_MASK; + ptr->BUF_ADDR[DAC_BUF_ADDR_BUF1] |= DAC_BUF_ADDR_BUF_STOP_SET(config->buf1.stop); + + /* set buffer 1 length */ + ptr->BUF_LENGTH &= ~DAC_BUF_LENGTH_BUF1_LEN_MASK; + ptr->BUF_LENGTH |= DAC_BUF_LENGTH_BUF1_LEN_SET(config->buf1.len - 1); + + /* enable the internal DMA */ + dac_cfg0 |= DAC_CFG0_DMA_AHB_EN_MASK; + + /* refresh the CFG0 */ + ptr->CFG0 = dac_cfg0; + + return status_success; +} + +hpm_stat_t dac_set_direct_config(DAC_Type *ptr, uint16_t data) +{ + if (data > DAC_SOC_MAX_DATA) { + return status_invalid_argument; + } + + /* set dac data to analog output */ + dac_cfg0 &= ~DAC_CFG0_SW_DAC_DATA_MASK; + dac_cfg0 |= DAC_CFG0_SW_DAC_DATA_SET(data); + + /* refresh the CFG0 */ + ptr->CFG0 = dac_cfg0; + + return status_success; +} + +hpm_stat_t dac_set_output_frequency(DAC_Type *ptr, uint32_t dac_input_freq, uint32_t dac_output_freq) +{ + if (dac_output_freq > DAC_SOC_MAX_OUTPUT_FREQ) { + return status_invalid_argument; + } + + /* set output frequency config */ + ptr->CFG1 &= ~DAC_CFG1_DIV_CFG_MASK; + ptr->CFG1 |= DAC_CFG1_DIV_CFG_SET(dac_input_freq % dac_output_freq ? (dac_input_freq / dac_output_freq + 1) : (dac_input_freq / dac_output_freq)); + + return status_success; +} + +hpm_stat_t dac_set_step_sw_trigger(DAC_Type *ptr, uint8_t step_sw_trig_idx) +{ + if (step_sw_trig_idx > DAC_STEP_CFG_STEP3) { + return status_invalid_argument; + } + + /* disable hw trigger */ + dac_cfg0 &= ~DAC_CFG0_HW_TRIG_EN_MASK; + + /* refresh the CFG0 */ + ptr->CFG0 = dac_cfg0; + + /* enable sw trigger */ + ptr->CFG2 |= 1 << step_sw_trig_idx; + + return status_success; +} + +void dac_set_buffer_sw_trigger(DAC_Type *ptr) +{ + /* disable hw trigger */ + dac_cfg0 &= ~DAC_CFG0_HW_TRIG_EN_MASK; + + /* refresh the CFG0 */ + ptr->CFG0 = dac_cfg0; + + /* enable sw trigger */ + ptr->CFG2 |= DAC_CFG2_BUF_SW_TRIG_MASK; +} + +void dac_set_buffer_DMA_reset(DAC_Type *ptr) +{ + ptr->CFG2 |= DAC_CFG2_DMA_RST1_MASK | DAC_CFG2_DMA_RST0_MASK | DAC_CFG2_FIFO_CLR_MASK; +} + +void dac_set_hw_trigger_enable(DAC_Type *ptr, bool enable) +{ + dac_cfg0 &= ~DAC_CFG0_HW_TRIG_EN_MASK; + dac_cfg0 |= DAC_CFG0_HW_TRIG_EN_SET(enable); + + /* refresh the CFG0 */ + ptr->CFG0 = dac_cfg0; +} + +void dac_enable_conversion(DAC_Type *ptr, bool enable) +{ + ptr->ANA_CFG0 &= ~DAC_ANA_CFG0_DAC12BIT_EN_MASK; + ptr->ANA_CFG0 |= DAC_ANA_CFG0_DAC12BIT_EN_SET(enable); +} + +hpm_stat_t dac_external_DMA_request_enable(DAC_Type *ptr, uint8_t buf_idx, bool enable) +{ + if (buf_idx > DAC_BUF_ADDR_BUF1) { + return status_invalid_argument; + } + + ptr->DMA_EN &= ~(1 << buf_idx); + ptr->DMA_EN |= enable << buf_idx; + + return status_success; +} + +void dac_enable_interrupts(DAC_Type *ptr, uint32_t mask) +{ + ptr->IRQ_EN |= mask; +} + +uint32_t dac_get_status_flags(DAC_Type *ptr) +{ + return ptr->IRQ_STS; +} + +void dac_set_status_flags(DAC_Type *ptr, uint32_t mask) +{ + ptr->IRQ_STS |= mask; +} + +uint8_t dac_get_current_buffer_index(DAC_Type *ptr) +{ + return DAC_STATUS0_CUR_BUF_INDEX_GET(ptr->STATUS0); +} + +uint16_t dac_get_current_buffer_offset(DAC_Type *ptr) +{ + return DAC_STATUS0_CUR_BUF_OFFSET_GET(ptr->STATUS0); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c new file mode 100644 index 0000000000..fb6110b149 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c @@ -0,0 +1,38 @@ +/* +* Copyright (c) 2021 hpmicro +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ +#include "hpm_dao_drv.h" + +void dao_get_default_config(DAO_Type *ptr, dao_config_t *config) +{ + config->enable_mono_output = false; + config->default_output_level = DAO_DEFAULT_OUTPUT_ALL_LOW; + config->channel_count = 2; +} + +hpm_stat_t dao_init(DAO_Type *ptr, dao_config_t *config) +{ + if (dao_is_running(ptr)) { + dao_stop(ptr); + } + dao_software_reset(ptr); + + ptr->CTRL = DAO_CTRL_MONO_SET(config->enable_mono_output) + | DAO_CHANNEL_BOTH + | DAO_CTRL_REMAP_MASK + | DAO_CTRL_FALSE_LEVEL_SET(config->default_output_level); + ptr->RX_CFGR = DAO_RX_CFGR_CH_MAX_SET(config->channel_count); + if (config->channel_count < 31) { + ptr->RXSLT = (1 << config->channel_count) - 1; + } else if (config->channel_count == 32) { + ptr->RXSLT = 0xFFFFFFFF; + } else { + /* channel count is not correct */ + return status_fail; + } + return status_success; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c new file mode 100644 index 0000000000..23991b5642 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_dma_drv.h" + +hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint32_t ch_num, dma_channel_config_t *ch) +{ + uint32_t tmp; + if ((ch->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (ch->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr))) { + return status_invalid_argument; + } + if ((ch->size_in_byte & ((1 << ch->dst_width) - 1)) + || (ch->src_addr & ((1 << ch->src_width) - 1)) + || (ch->src_addr & (((1 << ch->src_width) << ch->src_burst_size) - 1)) + || (ch->dst_addr & ((1 << ch->dst_width) - 1)) + || (ch->dst_addr & (((1 << ch->dst_width) << ch->src_burst_size) - 1)) + || ((1 << ch->src_width) & ((1 << ch->dst_width) - 1)) + || (((1 << ch->src_width) << ch->src_burst_size) & ((1 << ch->dst_width) - 1)) + || ((ch->linked_ptr & 0x7))) { + return status_dma_alignment_error; + } + ptr->CHCTRL[ch_num].SRCADDR = DMA_CHCTRL_SRCADDR_SRCADDRL_SET(ch->src_addr); + ptr->CHCTRL[ch_num].DSTADDR = DMA_CHCTRL_DSTADDR_DSTADDRL_SET(ch->dst_addr); + ptr->CHCTRL[ch_num].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(ch->size_in_byte >> ch->src_width); + ptr->CHCTRL[ch_num].LLPOINTER = DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(ch->linked_ptr >> 3); + +#if DMA_SUPPORT_64BIT_ADDR + ptr->CHCTRL[ch_num].SRCADDRH = DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(ch->src_addr_high); + ptr->CHCTRL[ch_num].DSTADDRH = DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(ch->dst_addr_high); + ptr->CHCTRL[ch_num].LLPOINTERH = DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(ch->linked_ptr_high); +#endif + + ptr->INTSTATUS = (DMA_INTSTATUS_TC_SET(1) | DMA_INTSTATUS_ABORT_SET(1) | DMA_INTSTATUS_ERROR_SET(1)) << ch_num; + tmp = DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(0) + | DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(0) + | DMA_CHCTRL_CTRL_PRIORITY_SET(ch->priority) + | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(ch->src_burst_size) + | DMA_CHCTRL_CTRL_SRCWIDTH_SET(ch->src_width) + | DMA_CHCTRL_CTRL_DSTWIDTH_SET(ch->dst_width) + | DMA_CHCTRL_CTRL_SRCMODE_SET(ch->src_mode) + | DMA_CHCTRL_CTRL_DSTMODE_SET(ch->dst_mode) + | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(ch->src_addr_ctrl) + | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(ch->dst_addr_ctrl) + | DMA_CHCTRL_CTRL_SRCREQSEL_SET(ch_num) + | DMA_CHCTRL_CTRL_DSTREQSEL_SET(ch_num) + | ch->interrupt_mask + | DMA_CHCTRL_CTRL_ENABLE_MASK; + ptr->CHCTRL[ch_num].CTRL = tmp; + if ((ptr->CHEN == 0) || !(ptr->CHEN & 1 << ch_num)) { + return status_fail; + } + + return status_success; +} + + +void dma_default_channel_config(DMA_Type *ptr, dma_channel_config_t *ch) +{ + ch->priority = 0; + ch->src_mode = DMA_HANDSHAKE_MODE_NORMAL; + ch->dst_mode = DMA_HANDSHAKE_MODE_NORMAL; + ch->src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + ch->src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch->dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch->interrupt_mask = DMA_INTERRUPT_MASK_NONE; + ch->linked_ptr= 0; +#if DMA_SUPPORT_64BIT_ADDR + ch->linked_ptr_high = 0; +#endif +} + +hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, + uint32_t dst, uint32_t src, + uint32_t size, uint32_t burst_len_in_byte) +{ + hpm_stat_t stat = status_success; + uint32_t width, count; + int32_t burst_size; + dma_channel_config_t config = {0}; + dma_default_channel_config(ptr, &config); + + /* burst size checking (1-byte burst length will cause heavy overhead */ + if (!burst_len_in_byte || burst_len_in_byte == 1 || burst_len_in_byte > size + || burst_len_in_byte > + ((1 << DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) << DMA_SOC_TRANSFER_PER_BURST_MAX(ptr))) { + return status_invalid_argument; + } + + count = count_set_bits(burst_len_in_byte); + if ((count > 1) || (burst_len_in_byte & 0x1)) { + /* dma only supports 2^n bytes as burst size */ + return status_invalid_argument; + } + + if ((size & (burst_len_in_byte - 1)) + || (dst & (burst_len_in_byte - 1)) + || (src & (burst_len_in_byte - 1))) { + return status_dma_alignment_error; + } + burst_size = get_first_set_bit_from_lsb(burst_len_in_byte); + + config.src_width = DMA_TRANSFER_WIDTH_HALF_WORD; + config.dst_width = DMA_TRANSFER_WIDTH_HALF_WORD; + for (width = DMA_SOC_TRANSFER_WIDTH_MAX(ptr); width > DMA_TRANSFER_WIDTH_HALF_WORD; width--) { + if (!(burst_len_in_byte & ((1 << width) - 1)) + && !(dst & ((1 << width) - 1)) + && !(src & ((1 << width) - 1)) + && !(size & ((1 << width) - 1))) { + config.src_width = width; + config.dst_width = width; + break; + } + } + + burst_size -= config.src_width; + do { + if (!(src & (((1 << config.src_width) << burst_size) - 1))) { + break; + } + burst_size--; + } while (burst_size > 0); + + config.src_addr = src; + config.dst_addr = dst; + config.size_in_byte = size; + + config.src_burst_size = burst_size; + stat = dma_setup_channel(ptr, ch_num, &config); + if (stat != status_success) { + return stat; + } + + return stat; +} + +hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig) +{ + hpm_stat_t stat = status_success; + dma_channel_config_t config = {0}; + dma_default_channel_config(ptr, &config); + + if (true == pconfig->dst_fixed) { + config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + } + if (true == pconfig->src_fixed) { + config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + } + + if (pconfig->ch_index > DMA_SOC_CHANNEL_NUM) { + return status_invalid_argument; + } + + /* In DMA handshake case, source width and destination width must be BYTE. */ + config.src_width = DMA_TRANSFER_WIDTH_BYTE; + config.dst_width = DMA_TRANSFER_WIDTH_BYTE; + config.src_addr = pconfig->src; + config.dst_addr = pconfig->dst; + config.size_in_byte = pconfig->size_in_byte; + /* In DMA handshake case, source burst size must be 1 transfer, that is 0. */ + config.src_burst_size = 0; + stat = dma_setup_channel(ptr, pconfig->ch_index, &config); + if (stat != status_success) { + return stat; + } + return stat; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dram_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dram_drv.c new file mode 100644 index 0000000000..9c6f7febbd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dram_drv.c @@ -0,0 +1,338 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_dram_drv.h" + +#ifndef HPM_DRAM_DRV_DEFAULT_PRESCALER +#define HPM_DRAM_DRV_DEFAULT_PRESCALER (0x3UL) +#endif + +#ifndef HPM_DRAM_DRV_RETRY_COUNT +#define HPM_DRAM_DRV_RETRY_COUNT (5000U) +#endif + +#define DRAM_PRESCALER_MAX (256UL) + +static void dram_config_delay_cell(DRAM_Type *ptr, uint32_t delay_cell_value) +{ + ptr->DLYCFG &= ~DRAM_DLYCFG_OE_MASK; + ptr->DLYCFG = DRAM_DLYCFG_DLYSEL_SET(delay_cell_value) | DRAM_DLYCFG_DLYEN_MASK; + ptr->DLYCFG |= DRAM_DLYCFG_OE_MASK; +} + +static hpm_stat_t dram_ip_cmd_done(DRAM_Type *ptr) +{ + uint32_t intr_status = 0; + uint32_t retry = 0; + do { + if (retry > HPM_DRAM_DRV_RETRY_COUNT) { + break; + } + retry++; + intr_status = ptr->INTR + & (uint32_t)(DRAM_INTR_IPCMDDONE_MASK | DRAM_INTR_IPCMDERR_MASK); + } while (intr_status == 0); + + if (retry > HPM_DRAM_DRV_RETRY_COUNT) { + return status_timeout; + } + + ptr->INTR |= DRAM_INTR_IPCMDDONE_MASK | DRAM_INTR_IPCMDERR_MASK; + if (intr_status & DRAM_INTR_IPCMDERR_MASK) { + return status_dram_cmd_err; + } + return status_success; +} + +static uint32_t dram_make_cmd(uint32_t opcode) +{ + return (opcode & ~DRAM_CMD_WRITE_FLAG) | DRAM_CMD_KEY; +} + +static bool dram_is_write_cmd(uint32_t opcode) +{ + return ((opcode & DRAM_CMD_WRITE_FLAG) == DRAM_CMD_WRITE_FLAG); +} + +uint32_t dram_issue_ip_cmd(DRAM_Type *ptr, uint32_t base_address, dram_cmd_t *cmd) +{ + bool read_data = !dram_is_write_cmd(cmd->opcode); + ptr->SADDR = base_address; + if (!read_data) { + ptr->IPTX = cmd->data; + } + ptr->IPCMD = dram_make_cmd(cmd->opcode); + + if (dram_ip_cmd_done(ptr) < 0) { + return status_dram_cmd_err; + } + + if (read_data) { + cmd->data = ptr->IPRX; + } + return status_success; +} + +void dram_default_config(DRAM_Type *ptr, dram_config_t *config) +{ + dram_axi_q_weight_t *q; + config->dqs = DRAM_DQS_FROM_PAD; + config->cmd_timeout = 0; + config->bus_timeout = 0x10; + q = &config->axi_q_weight[DRAM_AXI_Q_A]; + q->enable = true; + q->qos = 4; + q->age = 2; + q->slave_hit = 0x5; + q->slave_hit_wo_rw = 0x3; + + q = &config->axi_q_weight[DRAM_AXI_Q_B]; + q->enable = true; + q->qos = 4; + q->age = 2; + q->page_hit = 0x5; + q->slave_hit_wo_rw = 0x3; + q->bank_rotation = 0x6; +} + +void dram_get_typical_sdram_config(DRAM_Type *ptr, dram_sdram_config_t *config) +{ + config->col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; + config->cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + config->bank_num = DRAM_SDRAM_BANK_NUM_4; + config->prescaler = HPM_DRAM_DRV_DEFAULT_PRESCALER; + config->burst_len_in_byte = 8; + config->auto_refresh_count_in_one_burst = 1; + config->precharge_to_act_in_ns = 20; + config->act_to_rw_in_ns = 20; + config->refresh_recover_in_ns = 70; + config->write_recover_in_ns = 12; + config->cke_off_in_ns = 42; + config->act_to_precharge_in_ns = 42; + + config->self_refresh_recover_in_ns = 70; + config->refresh_to_refresh_in_ns = 60; + config->act_to_act_in_ns = 12; + config->idle_timeout_in_ns = 6; + config->cs_mux_pin = DRAM_IO_MUX_NOT_USED; +} + +void dram_init(DRAM_Type *ptr, dram_config_t *config) +{ + uint32_t i; + dram_axi_q_weight_t *q; + for (i = 0; i < DRAM_BR_COUNT; i++) { + ptr->BR[i] = 0; + } + + dram_sw_reset(ptr); + dram_disable(ptr); + ptr->CTRL |= DRAM_CTRL_BTO_SET(config->bus_timeout) + | DRAM_CTRL_CTO_SET(config->cmd_timeout) + | DRAM_CTRL_DQS_SET(config->dqs); + + q = &config->axi_q_weight[DRAM_AXI_Q_A]; + if (q->enable) { + ptr->BMW0 = DRAM_BMW0_QOS_SET(q->qos) + | DRAM_BMW0_AGE_SET(q->age) + | DRAM_BMW0_SH_SET(q->slave_hit) + | DRAM_BMW0_RWS_SET(q->slave_hit_wo_rw); + } else { + ptr->BMW0 = 0; + } + + q = &config->axi_q_weight[DRAM_AXI_Q_B]; + if (q->enable) { + ptr->BMW1 = DRAM_BMW1_QOS_SET(q->qos) + | DRAM_BMW1_AGE_SET(q->age) + | DRAM_BMW1_PH_SET(q->page_hit) + | DRAM_BMW1_BR_SET(q->bank_rotation) + | DRAM_BMW1_RWS_SET(q->slave_hit_wo_rw); + } else { + ptr->BMW1 = 0; + } + + dram_enable(ptr); +} + +static uint8_t dram_convert_actual_size_to_memory_size(uint32_t size_in_kb) +{ + uint8_t size = 0; + if (size_in_kb == 4) { + return 0; + } + + if (size_in_kb > 2 * 1 << 20) { + return 0x1F; + } + + size = 1; + size_in_kb >>= 3; + while (size_in_kb > 1) { + size_in_kb >>= 1; + size++; + } + return size; +} + +static uint8_t dram_convert_burst_len(uint8_t burst_len_in_byte) +{ + if ((burst_len_in_byte == 0) + || (burst_len_in_byte > DRAM_SDRAM_MAX_BURST_LENGTH_IN_BYTE)) { + return DRAM_SDRAM_MAX_BURST_LENGTH_IN_BYTE + 1; + } + + switch (burst_len_in_byte) { + case 1: + case 2: + case 4: + return burst_len_in_byte >> 1; + case 8: + return (burst_len_in_byte - 1) >> 1; + default: + return DRAM_SDRAM_MAX_BURST_LENGTH_IN_BYTE + 1; + } +} + +static uint32_t ns2cycle(uint32_t freq_in_hz, uint32_t ns) +{ + uint32_t ns_per_cycle; + ns_per_cycle = 1000000000 / freq_in_hz ; + if (ns < ns_per_cycle) { + return 1; + } + return ns / ns_per_cycle; +} + +hpm_stat_t dram_config_sdram(DRAM_Type *ptr, uint32_t clk_in_hz, dram_sdram_config_t *config) +{ + hpm_stat_t err; + uint32_t prescaler; + uint32_t refresh_cycle; + uint32_t clk_in_khz = clk_in_hz / 1000; + dram_cmd_t cmd = {0}; + uint8_t size = dram_convert_actual_size_to_memory_size(config->size_in_byte >> 10); + uint8_t burst_len = dram_convert_burst_len(config->burst_len_in_byte); + + prescaler = ((config->prescaler == 0) ? DRAM_PRESCALER_MAX : config->prescaler); + refresh_cycle = clk_in_khz * config->refresh_in_ms / config->refresh_count / (prescaler << 4); + + if ((prescaler == 0) || (prescaler > DRAM_PRESCALER_MAX) + || (refresh_cycle == 0) || (refresh_cycle > DRAM_PRESCALER_MAX)) { + return status_invalid_argument; + } + + if (prescaler == DRAM_PRESCALER_MAX) { + prescaler = 0; + } + + if (refresh_cycle == DRAM_PRESCALER_MAX) { + refresh_cycle = 0; + } + + ptr->BR[config->cs] = DRAM_BR_BASE_SET(config->base_address >> DRAM_BR_BASE_SHIFT) + | DRAM_BR_SIZE_SET(size) | DRAM_BR_VLD_MASK; + + ptr->SDRCTRL0 = DRAM_SDRCTRL0_PORTSZ_SET(config->port_size) + | DRAM_SDRCTRL0_BURSTLEN_SET(burst_len) + | DRAM_SDRCTRL0_COL_SET(config->col_addr_bits) + | DRAM_SDRCTRL0_COL8_SET(config->col_addr_bits == DRAM_SDRAM_COLUMN_ADDR_8_BITS) + | DRAM_SDRCTRL0_CAS_SET(config->cas_latency) + | DRAM_SDRCTRL0_BANK2_SET(config->bank_num); + + ptr->SDRCTRL1 = DRAM_SDRCTRL1_PRE2ACT_SET(ns2cycle(clk_in_hz, config->precharge_to_act_in_ns)) + | DRAM_SDRCTRL1_ACT2RW_SET(ns2cycle(clk_in_hz, config->act_to_rw_in_ns)) + | DRAM_SDRCTRL1_RFRC_SET(ns2cycle(clk_in_hz, config->refresh_recover_in_ns)) + | DRAM_SDRCTRL1_WRC_SET(ns2cycle(clk_in_hz, config->write_recover_in_ns)) + | DRAM_SDRCTRL1_CKEOFF_SET(ns2cycle(clk_in_hz, config->cke_off_in_ns)) + | DRAM_SDRCTRL1_ACT2PRE_SET(ns2cycle(clk_in_hz, config->act_to_precharge_in_ns)); + + ptr->SDRCTRL2 = DRAM_SDRCTRL2_SRRC_SET(ns2cycle(clk_in_hz, config->self_refresh_recover_in_ns)) + | DRAM_SDRCTRL2_REF2REF_SET(ns2cycle(clk_in_hz, config->refresh_to_refresh_in_ns)) + | DRAM_SDRCTRL2_ACT2ACT_SET(ns2cycle(clk_in_hz, config->act_to_act_in_ns)) + | DRAM_SDRCTRL2_ITO_SET(ns2cycle(clk_in_hz, config->idle_timeout_in_ns)); + + ptr->SDRCTRL3 = DRAM_SDRCTRL3_PRESCALE_SET(prescaler) + | DRAM_SDRCTRL3_RT_SET(refresh_cycle) + | DRAM_SDRCTRL3_UT_SET(refresh_cycle) + | DRAM_SDRCTRL3_REBL_SET(config->auto_refresh_count_in_one_burst - 1); + /* + * + * DATSZ[2:0]: Data size in byte + * 0b - 4 + * 1b - 1 + * 2b - 2 + * 3b - 3 + * > 3b - 4 + */ + ptr->DATSZ = DRAM_DATSZ_DATSZ_SET((config->data_width_in_byte & (0x3UL))); + ptr->BYTEMSK = 0; + + cmd.opcode = DRAM_CMD_SDRAM_PRECHARGE_ALL; + cmd.data = 0; + err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + + cmd.opcode = DRAM_CMD_SDRAM_AUTO_REFRESH; + err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + + /* + * + * DATSZ[2:0]: Data size in byte + * 0b - 4 + * 1b - 1 + * 2b - 2 + * 3b - 3 + * > 3b - 4 + */ + ptr->DATSZ = DRAM_DATSZ_DATSZ_SET((config->data_width_in_byte & (0x3UL))); + ptr->BYTEMSK = 0; + + /* + * config delay cell + */ + dram_config_delay_cell(ptr, config->delay_cell_value); + + cmd.opcode = DRAM_CMD_SDRAM_PRECHARGE_ALL; + cmd.data = 0; + err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + + cmd.opcode = DRAM_CMD_SDRAM_AUTO_REFRESH; + err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + + cmd.opcode = DRAM_CMD_SDRAM_MODE_SET; + /* FIXME: the mode register layout definition better to be passed in? */ + cmd.data = (uint32_t)(burst_len | config->cas_latency << 4); + err = dram_issue_ip_cmd(ptr, config->base_address, &cmd); + if (status_success != err) { + return err; + } + ptr->SDRCTRL3 |= DRAM_SDRCTRL3_REN_MASK; + + return status_success; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c new file mode 100644 index 0000000000..bcd2de27b9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*---------------------------------------------------------------------* + * Includes + *---------------------------------------------------------------------*/ +#include "hpm_enet_drv.h" +#include "hpm_enet_soc_drv.h" + +/*---------------------------------------------------------------------* + * Internal API + *---------------------------------------------------------------------*/ +static void enet_mode_init(ENET_Type *ptr, uint32_t intr) +{ + /* receive and transmit store and forward */ + ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_RSF_MASK | ENET_DMA_OP_MODE_TSF_MASK; + + /* enalbe hardware flow control */ + ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_EFC_MASK; + + /* enable error frame and undersized good frame forwarding */ + ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_FEF_MASK; + + /* disable osf mode */ + ptr->DMA_OP_MODE &= ~ENET_DMA_OP_MODE_OSF_MASK; + + ptr->DMA_INTR_EN |= intr; + + while (ENET_DMA_BUS_STATUS_AXIRDSTS_GET(ptr->DMA_BUS_STATUS) || ENET_DMA_BUS_STATUS_AXWHSTS_GET(ptr->DMA_BUS_STATUS)) {} + + /* start the receive and transmit dma */ + ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_ST_MASK | ENET_DMA_OP_MODE_SR_MASK; +} + +static int enet_dma_init(ENET_Type *ptr, enet_desc_t *desc, uint32_t intr) +{ + /* generate software reset */ + ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_SWR_MASK; + + /* wait for the completion of reset process */ + while (ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE)) {} + + /* initialize bus mode register */ + ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_AAL_MASK; + + ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_FB_MASK; + + /* enable pblx8 mode */ + ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_PBLX8_MASK; + + /* set programmable burst length */ + ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_PBL_SET(enet_pbl_32); + + /* disable separate pbl */ + ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_USP_MASK; + + /* descriptor length */ +#if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MIN_LEN + ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_ATDS_MASK; +#elif ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN + ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_ATDS_MASK; + #endif + + /* set the maximum enabled burst length */ + if (ENET_DMA_BUS_MODE_FB_GET(ptr->DMA_BUS_MODE) == 0) { + ptr->DMA_AXI_MODE |= ENET_DMA_AXI_MODE_BLEN4_MASK | ENET_DMA_AXI_MODE_BLEN8_MASK | ENET_DMA_AXI_MODE_BLEN16_MASK; + } + else { + /* TODO: set BLENX_MASK */ + } + + /* initialize Tx descriptors list: chain mode */ + enet_dma_tx_desc_chain_init(ptr, desc); + + /* initialize Rx descriptors list: Chain Mode */ + enet_dma_rx_desc_chain_init(ptr, desc); + + enet_mode_init(ptr, intr); + + enet_dma_flush(ptr); + + return true; +} + +static int enet_mac_init(ENET_Type *ptr, enet_mac_config_t *config, enet_inf_type_t inf_type, uint32_t mask_intr) +{ + for (int i = 0; i < config->valid_max_count; i++) { + if (i == 0) { + ptr->MAC_ADDR_0_HIGH = ENET_MAC_ADDR_0_HIGH_AE_MASK; + ptr->MAC_ADDR_0_HIGH |= ENET_MAC_ADDR_0_HIGH_ADDRHI_SET(config->mac_addr_high[i]); + ptr->MAC_ADDR_0_LOW = ENET_MAC_ADDR_0_LOW_ADDRLO_SET(config->mac_addr_low[i]); + } else { + ptr->MAC_ADDR[i].HIGH |= ENET_MAC_ADDR_HIGH_ADDRHI_SET(config->mac_addr_high[i]); + ptr->MAC_ADDR[i].LOW |= ENET_MAC_ADDR_LOW_ADDRLO_SET(config->mac_addr_low[i]); + } + } + + + /* set the appropriate filters for the incoming frames */ + ptr->MACFF |= ENET_MACFF_RA_SET(1); /* receive all */ + + /* replace the content of the mac address 0 in the sa field of all transmitted frames */ + ptr->MACCFG &= ENET_MACCFG_SARC_MASK; + ptr->MACCFG |= ENET_MACCFG_SARC_SET(0x3); + + ptr->MACCFG |= ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK; + + if (inf_type == enet_inf_rgmii) { + ptr->MACCFG &= ~ENET_MACCFG_PS_MASK; + } else if (inf_type == enet_inf_rmii) { + ptr->MACCFG |= ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK; + } else { + return status_invalid_argument; + } + + ptr->MACCFG |= ENET_MACCFG_DM_MASK; + + if (ENET_MACCFG_DM_GET(ptr->MACCFG) == 0) { + ptr->MACCFG |= ENET_MACCFG_IFG_SET(4); + } else { + ptr->MACCFG |= ENET_MACCFG_IFG_SET(2); + } + + + /* enable transmitter enable and receiver */ + ptr->MACCFG |= ENET_MACCFG_TE_MASK | ENET_MACCFG_RE_MASK; + + /* enable mask interrupt */ + ptr->INTR_MASK |= mask_intr; + + return true; +} + +/*---------------------------------------------------------------------* + * Driver API + *---------------------------------------------------------------------*/ +void enet_dma_flush(ENET_Type *ptr) +{ + /* flush DMA transmit FIFO */ + ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_FTF_MASK; + while (ENET_DMA_OP_MODE_FTF_GET(ptr->DMA_OP_MODE)) { + + } +} + +void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data) +{ + /* set data to be written */ + ptr->GMII_DATA = ENET_GMII_DATA_GD_SET(data); + + /* set phy address , register address, write operation and busy flag */ + ptr->GMII_ADDR = ENET_GMII_ADDR_PA_SET(phy_addr) + | ENET_GMII_ADDR_GR_SET(addr) + | ENET_GMII_ADDR_CR_SET(enet_csr_150m_to_250m_mdc_csr_div_102) + | ENET_GMII_ADDR_GW_SET(enet_phy_op_write) + | ENET_GMII_ADDR_GB_SET(enet_phy_busy); + + /* wait until the write operation is completed */ + while (ENET_GMII_ADDR_GB_GET(ptr->GMII_ADDR)) {} +} + +uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) +{ + /* set phy address, register address, read operation and busy flag */ + ptr->GMII_ADDR = ENET_GMII_ADDR_PA_SET(phy_addr) + | ENET_GMII_ADDR_GR_SET(addr) + | ENET_GMII_ADDR_CR_SET(enet_csr_150m_to_250m_mdc_csr_div_102) + | ENET_GMII_ADDR_GW_SET(enet_phy_op_read) + | ENET_GMII_ADDR_GB_SET(enet_phy_busy); + + /* wait until the write operation is completed */ + while (ENET_GMII_ADDR_GB_GET(ptr->GMII_ADDR)) {} + + /* read and return data */ + return (uint16_t)ENET_GMII_DATA_GD_GET(ptr->GMII_DATA); +} + +void enet_set_mask_interrupt(ENET_Type *ptr, uint32_t mask_intr) +{ + ptr->INTR_MASK |= mask_intr; +} + +int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, uint32_t intr, uint32_t mask_intr) +{ + /* select RGMII */ + enet_intf_selection(ptr, inf_type); + + /* initialize DMA */ + enet_dma_init(ptr, desc, intr); + + /* Initialize MAC */ + enet_mac_init(ptr, config, inf_type, mask_intr); + + return true; +} + +/******************************************************************************/ +/* DMA API */ +/******************************************************************************/ +uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info) +{ + enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; + + /* check if the last segment */ + if ((rx_desc_list_cur->rdes0_bm.own == 0) && + (rx_desc_list_cur->rdes0_bm.ls == 1)) { + rx_frame_info->seg_count++; + if (rx_frame_info->seg_count == 1) { + rx_frame_info->fs_rx_desc = rx_desc_list_cur; + } + rx_frame_info->ls_rx_desc = rx_desc_list_cur; + return 1; + } + /* check if the first segment */ + else if ((rx_desc_list_cur->rdes0_bm.own == 0) && + (rx_desc_list_cur->rdes0_bm.fs == 1) && + (rx_desc_list_cur->rdes0_bm.ls == 0)) { + rx_frame_info->fs_rx_desc = rx_desc_list_cur; + rx_frame_info->ls_rx_desc = NULL; + rx_frame_info->seg_count = 1; + rx_desc_list_cur = (enet_rx_desc_t *)rx_desc_list_cur->rdes3_bm.next_desc; + *parent_rx_desc_list_cur = rx_desc_list_cur; + } + + /* check if intermediate segments */ + else if ((rx_desc_list_cur->rdes0_bm.own == 0) && + (rx_desc_list_cur->rdes0_bm.fs == 0) && + (rx_desc_list_cur->rdes0_bm.ls == 0)) { + rx_frame_info->seg_count++; + rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); + *parent_rx_desc_list_cur = rx_desc_list_cur; + } + + return 0; +} + +enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info) +{ + uint32_t frame_length = 0; + enet_frame_t frame = {0, 0, 0}; + enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; + + /* get the frame length of the received packet: substruct 4 bytes of the CRC */ + frame_length = rx_desc_list_cur->rdes0_bm.fl - 4; + frame.length = frame_length; + + /* get the address of the first frame descriptor and the buffer start address */ + frame.rx_desc = rx_frame_info->fs_rx_desc; + frame.buffer = rx_frame_info->fs_rx_desc->rdes2_bm.buffer1; + + /* update the Ethernet dma global Rx descriptor with next Rx descriptor */ + /* chained mode */ + /* selects the next dma Rx descriptor list for next buffer to read */ + rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); + *parent_rx_desc_list_cur = rx_desc_list_cur; + + return frame; +} + +enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count) +{ + enet_frame_t frame = {0, 0, 0}; + uint32_t desc_scan_counter = 0; + enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; + + /* scan descriptors owned by CPU */ + while ((rx_desc_list_cur->rdes0_bm.own == 0) && + (desc_scan_counter < rx_desc_count)) { + + desc_scan_counter++; + + /* check if first segment in frame */ + if ((rx_desc_list_cur->rdes0_bm.fs == 1) && + (rx_desc_list_cur->rdes0_bm.ls == 0)) { + rx_frame_info->fs_rx_desc = rx_desc_list_cur; + rx_frame_info->seg_count = 1; + rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); + *parent_rx_desc_list_cur = rx_desc_list_cur; + } + + /* check if intermediate segment */ + else if ((rx_desc_list_cur->rdes0_bm.ls == 0) && + (rx_desc_list_cur->rdes0_bm.fs == 0)) { + rx_frame_info->seg_count++; + rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); + *parent_rx_desc_list_cur = rx_desc_list_cur; + } + + /* should be last segment */ + else { + /* last segment */ + rx_frame_info->ls_rx_desc = rx_desc_list_cur; + + rx_frame_info->seg_count++; + + /* first segment is last segment */ + if (rx_frame_info->seg_count == 1) { + rx_frame_info->fs_rx_desc = rx_desc_list_cur; + } + + /* get the frame length of the received packet: substruct 4 bytes of the crc */ + frame.length = rx_desc_list_cur->rdes0_bm.fl - 4; + + /* get the address of the buffer start address */ + /* check if more than one segment in the frame */ + if (rx_frame_info->seg_count > 1) { + frame.buffer = rx_frame_info->fs_rx_desc->rdes2_bm.buffer1; + } else { + frame.buffer = rx_desc_list_cur->rdes2_bm.buffer1; + } + + frame.rx_desc = rx_frame_info->fs_rx_desc; + + rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); + *parent_rx_desc_list_cur = rx_desc_list_cur; + + return frame; + } + } + + return frame; +} + +uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size) +{ + uint32_t buf_count = 0, size = 0, i = 0; + enet_tx_desc_t *dma_tx_desc; + enet_tx_desc_t *tx_desc_list_cur = *parent_tx_desc_list_cur; + + if (tx_buff_size == 0) { + return ENET_ERROR; + } + /* check if the descriptor is owned by the Ethernet DMA (when set) or CPU (when reset) */ + dma_tx_desc = tx_desc_list_cur; + if (frame_length > tx_buff_size) { + buf_count = frame_length / tx_buff_size; + if (frame_length % tx_buff_size) { + buf_count++; + } + } else { + buf_count = 1; + } + + if (buf_count == 1) { + /*set the last and the first segment */ + dma_tx_desc->tdes0_bm.own = 0; + dma_tx_desc->tdes0_bm.fs = 1; + dma_tx_desc->tdes0_bm.ls = 1; + dma_tx_desc->tdes0_bm.dc = 1; + dma_tx_desc->tdes0_bm.dp = 0; + dma_tx_desc->tdes0_bm.crcr = 0; + dma_tx_desc->tdes1_bm.saic = 2; + + /* set the frame size */ + dma_tx_desc->tdes1_bm.tbs1 = (frame_length & ENET_DMATxDesc_TBS1); + /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ + dma_tx_desc->tdes0_bm.own = 1; + ptr->DMA_TX_POLL_DEMAND = 1; + + dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); + } else { + for (i = 0; i < buf_count; i++) { + /* clear first and last segment bits */ + dma_tx_desc->tdes0_bm.fs = 0; + dma_tx_desc->tdes0_bm.ls = 0; + + if (i == 0) { + /* setting the first segment bit */ + dma_tx_desc->tdes0_bm.fs = 1; + } + + /* set the buffer 1 size */ + dma_tx_desc->tdes1_bm.tbs1 = (tx_buff_size & ENET_DMATxDesc_TBS1); + + if (i == (buf_count - 1)) { + /* set the last segment bit */ + dma_tx_desc->tdes0_bm.ls = 1; + size = frame_length - (buf_count - 1) * tx_buff_size; + dma_tx_desc->tdes1_bm.tbs1 = (size & ENET_DMATxDesc_TBS1); + + /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ + dma_tx_desc->tdes0_bm.own = 1; + ptr->DMA_TX_POLL_DEMAND = 1; + } + + dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); + } + } + + tx_desc_list_cur = dma_tx_desc; + *parent_tx_desc_list_cur = tx_desc_list_cur; + + return ENET_SUCCESS; +} + +void enet_dma_tx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc) +{ + uint32_t i = 0; + enet_tx_desc_t *dma_tx_desc; + + /* set the tx_desc_list_cur pointer with the first one of the dma_tx_desc_tab list */ + desc->tx_desc_list_cur = desc->tx_desc_list_head; + + /* fill each dma_tx_desc descriptor with the right values */ + for (i = 0; i < desc->tx_buff_cfg.count; i++) { + + /* get the pointer on the ith member of the Tx desc list */ + dma_tx_desc = desc->tx_desc_list_head + i; + + /* set second address chained bit */ + dma_tx_desc->tdes0_bm.tch = 1; + + /* set buffer 1 address pointer */ + dma_tx_desc->tdes2_bm.buffer1 = (uint32_t)(&((uint8_t *)desc->tx_buff_cfg.buffer)[i * desc->tx_buff_cfg.size]); + + /* link all Tx descriptors */ + if (i < desc->tx_buff_cfg.count - 1) { + /* set next descriptor address register with the next descriptor base address */ + dma_tx_desc->tdes3_bm.next_desc = (uint32_t)(desc->tx_desc_list_head + i + 1); + } else { + /* for last descriptor, set next descriptor address register equal to the first descriptor base address */ + dma_tx_desc->tdes3_bm.next_desc = (uint32_t)desc->tx_desc_list_head; + } + } + + /* set transmit descriptor list address register */ + ptr->DMA_TX_DESC_LIST_ADDR = (uint32_t)desc->tx_desc_list_head; +} + +void enet_dma_rx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc) +{ + uint32_t i = 0; + enet_rx_desc_t *dma_rx_desc; + + /* set the rx_desc_list_cur pointer with the first one of the dma_rx_desc_tab list */ + desc->rx_desc_list_cur = desc->rx_desc_list_head; + /* fill each dma_rx_desc descriptor with the right values */ + for (i = 0; i < desc->rx_buff_cfg.count; i++) { + /* get the pointer on the ith member of the Rx desc list */ + dma_rx_desc = desc->rx_desc_list_head + i; + /* set own bit of the rx descriptor status */ + dma_rx_desc->rdes0_bm.own = 1; + + /* set buffer 1 size and second address chained bit */ + dma_rx_desc->rdes1_bm.rch = 1; + dma_rx_desc->rdes1_bm.rbs1 = desc->rx_buff_cfg.size; + + /* set buffer 1 address pointer */ + dma_rx_desc->rdes2_bm.buffer1 = (uint32_t)(&((uint8_t *)desc->rx_buff_cfg.buffer)[i * desc->rx_buff_cfg.size]); + + /* link all Rx descriptors */ + if (i < desc->rx_buff_cfg.count - 1) { + /* set next descriptor address register with next descriptor base address */ + dma_rx_desc->rdes3_bm.next_desc = (uint32_t)(desc->rx_desc_list_head + i + 1); + } else { + /* for last descriptor, set next descriptor address register equal to the first descriptor base address */ + dma_rx_desc->rdes3_bm.next_desc = (uint32_t)desc->rx_desc_list_head; + } + } + /* set receive descriptor list address register */ + ptr->DMA_RX_DESC_LIST_ADDR = (uint32_t)desc->rx_desc_list_head; +} + +void enet_mask_interrupt_event(ENET_Type *ptr, uint32_t mask) +{ + /* mask the specified interrupts */ + ptr->INTR_MASK |= mask; +} + +void enet_timestamp_enable(ENET_Type *ptr, bool enable) +{ + /* enable the timestamp */ + ptr->TS_CTRL &= ~ENET_TS_CTRL_TSENA_MASK; + ptr->TS_CTRL |= ENET_TS_CTRL_TSENA_SET(enable); +} + +void enet_set_subsecond_increment(ENET_Type *ptr, uint8_t ssinc) +{ + ptr->SUB_SEC_INCR &= ~ENET_SUB_SEC_INCR_SSINC_MASK; + ptr->SUB_SEC_INCR |= ENET_SUB_SEC_INCR_SSINC_SET(ssinc); +} + +void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp) +{ + ptr->SYST_SEC_UPD = timestamp->sec; + ptr->SYST_NSEC_UPD = timestamp->nsec; + ptr->TS_CTRL |= ENET_TS_CTRL_TSINIT_MASK; + + while (ENET_TS_CTRL_TSINIT_GET(ptr->TS_CTRL) == 1) { + + } +} + +void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_time_t *timestamp) +{ + timestamp->sec = ptr->SYST_SEC; + timestamp->nsec = ptr->SYST_NSEC; +} + +void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_time_t *timeoffset) +{ + /* write the offset (positive or negative ) in the timestamp update high and low registers */ + ptr->SYST_SEC_UPD = ENET_SYST_SEC_UPD_TSS_SET(timeoffset->sec); + ptr->SYST_NSEC_UPD = ENET_SYST_NSEC_UPD_ADDSUB_SET(timeoffset->sign) | ENET_SYST_NSEC_UPD_TSSS_SET(timeoffset->nsec / ptr->SUB_SEC_INCR); + + /* update the timestamp */ + ptr->TS_CTRL |= ENET_TS_CTRL_TSUPDT_MASK; + + /* wait for the updating to finish */ + while (ENET_TS_CTRL_TSUPDT_GET(ptr->TS_CTRL)) { + + } +} + +void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj) +{ + ptr->TS_ADDEND = (uint32_t)((int64_t)adj * ENET_ADJ_FREQ_BASE_ADDEND / (ENET_ONE_SEC_IN_NANOSEC - adj) + ENET_ADJ_FREQ_BASE_ADDEND);; + + ptr->TS_CTRL |= ENET_TS_CTRL_TSADDREG_MASK; + + while (ENET_TS_CTRL_TSADDREG_GET(ptr->TS_CTRL)) { + + } +} + +void enet_eanble_timestamp(ENET_Type *ptr) +{ + ptr->TS_CTRL |= ENET_TS_CTRL_TSENA_MASK; +} + +void enet_set_ptp_version(ENET_Type *ptr, enet_ptp_version_t ptp_ver) +{ + ptr->TS_CTRL &= ~ENET_TS_CTRL_TSVER2ENA_MASK; + ptr->TS_CTRL |= ENET_TS_CTRL_TSVER2ENA_SET(ptp_ver); +} + +hpm_stat_t enet_enable_ptp_frame_type(ENET_Type *ptr, enet_ptp_frame_type_t ptp_frame_type, bool enable) +{ + hpm_stat_t stat = status_success; + + if (ptp_frame_type == enet_ptp_frame_ipv4) { + ptr->TS_CTRL &= ~ENET_TS_CTRL_TSIPV4ENA_MASK; + ptr->TS_CTRL |= ENET_TS_CTRL_TSIPV4ENA_SET(enable); + } else if (ptp_frame_type == enet_ptp_frame_ipv6) { + ptr->TS_CTRL &= ~ENET_TS_CTRL_TSIPV6ENA_MASK; + ptr->TS_CTRL |= ENET_TS_CTRL_TSIPV6ENA_SET(enable); + } else if (ptp_frame_type == enet_ptp_frame_ethernet) { + ptr->TS_CTRL &= ~ENET_TS_CTRL_TSIPENA_MASK; + ptr->TS_CTRL |= ENET_TS_CTRL_TSIPENA_SET(enable); + } else { + return status_invalid_argument; + } + + return stat; +} + +void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ss_ptp_msg) +{ + /* set ptp message type for snapshots */ + ptr->TS_CTRL &= ~ENET_TS_CTRL_SNAPTYPSEL_MASK; + ptr->TS_CTRL &= ~ENET_TS_CTRL_TSMSTRENA_MASK; + ptr->TS_CTRL &= ~ENET_TS_CTRL_TSEVNTENA_MASK; + ptr->TS_CTRL |= ts_ss_ptp_msg << ENET_TS_CTRL_TSEVNTENA_SHIFT; +} + +void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config) +{ + enet_mask_interrupt_event(ptr, ENET_INTR_STATUS_TSIS_MASK); + + /* select the resolution of nanosecond */ + ptr->TS_CTRL &= ~ENET_TS_CTRL_TSCTRLSSR_MASK; + ptr->TS_CTRL |= ENET_TS_CTRL_TSCTRLSSR_SET(config->sub_sec_count_res); + + /* enable timestamping */ + ptr->TS_CTRL |= ENET_TS_CTRL_TSENALL_MASK | ENET_TS_CTRL_TSENA_MASK; + + /* set sub-second increment */ + ptr->SUB_SEC_INCR &= ~ENET_SUB_SEC_INCR_SSINC_MASK; + ptr->SUB_SEC_INCR |= ENET_SUB_SEC_INCR_SSINC_SET(config->ssinc); + + if (config->update_method == enet_ptp_time_fine_update) { + /* set the addend */ + ptr->TS_ADDEND = config->addend; + + /* update the addend */ + ptr->TS_CTRL |= ENET_TS_CTRL_TSADDREG_MASK; + + /* poll the status of updating the addend */ + while (ENET_TS_CTRL_TSADDREG_GET(ptr->TS_CTRL)) { + + } + + /* fine update */ + ptr->TS_CTRL |= ENET_TS_CTRL_TSCFUPDT_MASK; + } else { + /* coarse update */ + ptr->TS_CTRL &= ~ENET_TS_CTRL_TSCFUPDT_MASK; + } +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c new file mode 100644 index 0000000000..8be0349a1f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_ffa_drv.h" +#include + +#define FFA_ERROR_MASKS (FFA_STATUS_FIR_OV_MASK | FFA_STATUS_FFT_OV_MASK | FFA_STATUS_WR_ERR_MASK | FFA_STATUS_RD_NXT_ERR_MASK | FFA_STATUS_RD_ERR_MASK) + +static bool is_point_num_valid(uint16_t num_point); +static uint32_t get_fft_misc_reg_fft_len(uint16_t num_point); +static hpm_stat_t get_fft_error_kind(uint32_t ffa_status); + +static bool is_point_num_valid(uint16_t num_point) +{ + return ((num_point & (num_point - 1U)) == 0U) && (num_point >= 8U); +} + +static uint32_t get_fft_misc_reg_fft_len(uint16_t num_point) +{ + uint32_t count = 0U; + num_point /= 8; + while (num_point > 0) { + count++; + num_point >>= 1U; + } + + return (count - 1U); +} + +void ffa_start_fft(FFA_Type *ptr, fft_xfer_t *fft_xfer) +{ + + assert((ptr != NULL) && (fft_xfer != NULL) && is_point_num_valid(fft_xfer->num_points)); + + ffa_disable(ptr); + + ffa_enable_interrupt(ptr, fft_xfer->interrupt_mask); + + ptr->OP_CTRL = FFA_OP_CTRL_EN_MASK; + + uint32_t op_cmd = FFA_OP_CMD_CMD_SET(FFA_OPCMD_FFT) | FFA_OP_CMD_IND_TYPE_SET(fft_xfer->src_data_type) | + FFA_OP_CMD_OUTD_TYPE_SET(fft_xfer->dst_data_type); + ptr->OP_CMD = op_cmd; + + uint32_t fft_len = get_fft_misc_reg_fft_len(fft_xfer->num_points); + uint32_t fft_misc = + FFA_OP_FFT_MISC_FFT_LEN_SET(fft_len) | FFA_OP_FFT_MISC_TMP_BLK_SET(1) | FFA_OP_FFT_MISC_IND_BLK_SET(0); + if (fft_xfer->is_ifft) { + fft_misc |= FFA_OP_FFT_MISC_IFFT_MASK; + } + ptr->OP_REG0 = fft_misc; + + ptr->OP_REG1 = 0; + ptr->OP_REG2 = (uint32_t) fft_xfer->src; + ptr->OP_REG4 = (uint32_t) fft_xfer->dst; + + ffa_enable(ptr); +} + +void ffa_start_fir(FFA_Type *ptr, fir_xfer_t *fir_xfer) +{ + assert((ptr != NULL) && (fir_xfer != NULL)); + + ffa_disable(ptr); + + ffa_enable_interrupt(ptr, fir_xfer->interrupt_mask); + + ptr->OP_CTRL = FFA_OP_CTRL_EN_MASK; + + uint32_t op_cmd = FFA_OP_CMD_CMD_SET(FFA_OPCMD_FIR) | FFA_OP_CMD_IND_TYPE_SET(fir_xfer->data_type) | + FFA_OP_CMD_OUTD_TYPE_SET(fir_xfer->data_type) | FFA_OP_CMD_COEF_TYPE_SET(fir_xfer->data_type); + ptr->OP_CMD = op_cmd; + + uint32_t fir_misc = FFA_OP_FIR_MISC_FIR_COEF_TAPS_SET(fir_xfer->coef_taps); + ptr->OP_REG0 = fir_misc; + + uint32_t fir_misc1 = FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SET(0) | FFA_OP_FIR_MISC1_COEF_MEM_BLK_SET(1) | + FFA_OP_FIR_MISC1_IND_MEM_BLK_SET(2) | FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SET(fir_xfer->input_taps); + + ptr->OP_REG1 = fir_misc1; + ptr->OP_REG2 = 0xFFFFFFFFUL; + ptr->OP_REG3 = (uint32_t) fir_xfer->src; + ptr->OP_REG4 = (uint32_t) fir_xfer->coeff; + ptr->OP_REG5 = (uint32_t) fir_xfer->dst; + + ffa_enable(ptr); +} + +static hpm_stat_t get_fft_error_kind(uint32_t ffa_status) +{ + hpm_stat_t status; + if (IS_HPM_BITMASK_SET(ffa_status, FFA_ERROR_MASKS)) { + if (IS_HPM_BITMASK_SET(ffa_status, FFA_STATUS_FIR_OV_MASK)) { + status = status_ffa_fir_overflow; + } else if (IS_HPM_BITMASK_SET(ffa_status, FFA_STATUS_FFT_OV_MASK)) { + status = status_ffa_fft_overflow; + } else if (IS_HPM_BITMASK_SET(ffa_status, FFA_STATUS_WR_ERR_MASK)) { + status = status_ffa_write_error; + } else if (IS_HPM_BITMASK_SET(ffa_status, FFA_STATUS_RD_NXT_ERR_MASK)) { + status = status_ffa_read_next_error; + } else { + status = status_ffa_read_error; + } + } else { + status = status_success; + } + return status; +} + +hpm_stat_t ffa_calculate_fft_blocking(FFA_Type *ptr, fft_xfer_t *fft_xfer) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF((ptr == NULL) || (fft_xfer == NULL) || !is_point_num_valid(fft_xfer->num_points)); + + fft_xfer->interrupt_mask = 0; + + ffa_start_fft(ptr, fft_xfer); + + while (!IS_HPM_BITMASK_SET(ptr->STATUS, FFA_STATUS_OP_CMD_DONE_MASK)) { + } + + uint32_t ffa_status = ptr->STATUS; + status = get_fft_error_kind(ffa_status); + } while (false); + + return status; +} + +hpm_stat_t ffa_calculate_fir_blocking(FFA_Type *ptr, fir_xfer_t *fir_xfer) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF((ptr == NULL) || (fir_xfer == NULL)); + + fir_xfer->interrupt_mask = 0; + + ffa_start_fir(ptr, fir_xfer); + + while (!IS_HPM_BITMASK_SET(ptr->STATUS, FFA_STATUS_OP_CMD_DONE_MASK)) { + } + + uint32_t ffa_status = ptr->STATUS; + status = get_fft_error_kind(ffa_status); + } while (false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c new file mode 100644 index 0000000000..822f2acb49 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_gpio_drv.h" + +void gpio_toggle_pin_interrupt_trigger_polarity(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_index) +{ + bool intr_was_enabled = gpio_check_pin_interrupt_enabled(ptr, gpio_index, pin_index); + gpio_disable_pin_interrupt(ptr, gpio_index, pin_index); + ptr->PL[gpio_index].TOGGLE = 1 << pin_index; + if (intr_was_enabled) { + gpio_enable_pin_interrupt(ptr, gpio_index, pin_index); + } +} + +void gpio_toggle_pin_interrupt_trigger_type(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_index) +{ + bool intr_was_enabled = gpio_check_pin_interrupt_enabled(ptr, gpio_index, pin_index); + gpio_disable_pin_interrupt(ptr, gpio_index, pin_index); + ptr->TP[gpio_index].TOGGLE = 1 << pin_index; + if (intr_was_enabled) { + gpio_enable_pin_interrupt(ptr, gpio_index, pin_index); + } +} + + +void gpio_config_pin_interrupt(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_index, gpio_interrupt_trigger_t trigger) +{ + switch(trigger) { + case gpio_interrupt_trigger_level_high: + case gpio_interrupt_trigger_level_low: + ptr->TP[gpio_index].CLEAR = 1 << pin_index; + if (trigger == gpio_interrupt_trigger_level_high) { + ptr->PL[gpio_index].CLEAR = 1 << pin_index; + } else { + ptr->PL[gpio_index].SET = 1 << pin_index; + } + break; + case gpio_interrupt_trigger_edge_falling: + case gpio_interrupt_trigger_edge_rising: + ptr->TP[gpio_index].SET = 1 << pin_index; + if (trigger == gpio_interrupt_trigger_edge_rising) { + ptr->PL[gpio_index].CLEAR = 1 << pin_index; + } else { + ptr->PL[gpio_index].SET = 1 << pin_index; + } + break; + default: + return; + } +} + +void gpio_set_pin_output_with_initial(GPIO_Type *ptr, uint32_t port, uint8_t pin, uint8_t initial) +{ + if (initial & 1) { + ptr->DO[port].SET = 1 << pin; + } else { + ptr->DO[port].CLEAR = 1 << pin; + } + ptr->OE[port].SET = 1 << pin; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c new file mode 100644 index 0000000000..4f8d62be6c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_gptmr_drv.h" + +void gptmr_channel_get_default_config(GPTMR_Type *ptr, gptmr_channel_config_t *config) +{ + config->mode = gptmr_work_mode_no_capture; + config->dma_request_event = gptmr_dma_request_disabled; + config->synci_edge = gptmr_synci_edge_none; + for(uint8_t i = 0; i < GPTMR_CH_CMP_COUNT; i++) { + config->cmp[i] = 0; + } + config->reload = 0xFFFFFFFFUL; + config->cmp_initial_polarity_high = true; + config->enable_cmp_output = true; + config->enable_sync_follow_previous_channel = false; + config->enable_software_sync = false; + config->debug_mode = true; +} + +hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr, + uint8_t ch_index, + gptmr_channel_config_t *config, + bool enable) +{ + uint32_t v = 0; + if (config->enable_sync_follow_previous_channel && !ch_index) { + return status_invalid_argument; + } + + if (config->dma_request_event != gptmr_dma_request_disabled) { + v |= GPTMR_CHANNEL_CR_DMAEN_MASK + | GPTMR_CHANNEL_CR_DMASEL_SET(config->dma_request_event); + } + v |= GPTMR_CHANNEL_CR_CAPMODE_SET(config->mode) + | GPTMR_CHANNEL_CR_DBGPAUSE_SET(config->debug_mode) + | GPTMR_CHANNEL_CR_SWSYNCIEN_SET(config->enable_software_sync) + | GPTMR_CHANNEL_CR_CMPINIT_SET(config->cmp_initial_polarity_high) + | GPTMR_CHANNEL_CR_SYNCFLW_SET(config->enable_sync_follow_previous_channel) + | GPTMR_CHANNEL_CR_CMPEN_SET(config->enable_cmp_output) + | GPTMR_CHANNEL_CR_CEN_SET(enable) + | config->synci_edge; + + for (uint8_t i = 0; i < GPTMR_CH_CMP_COUNT; i++) { + ptr->CHANNEL[ch_index].CMP[i] = GPTMR_CMP_CMP_SET(config->cmp[i]); + } + ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(config->reload); + ptr->CHANNEL[ch_index].CR = v; + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c new file mode 100644 index 0000000000..ddb1a8cc59 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_i2c_drv.h" + +#ifndef HPM_I2C_DRV_DEFAULT_TPM +#define HPM_I2C_DRV_DEFAULT_TPM (0U) +#endif + +#ifndef HPM_I2C_DRV_DEFAULT_SCL_RATIO +#define HPM_I2C_DRV_DEFAULT_SCL_RATIO (1U) +#endif + +#ifndef HPM_I2C_DRV_DEFAULT_RETRY_COUNT +#define HPM_I2C_DRV_DEFAULT_RETRY_COUNT (5000U) +#endif + +#define period_in_ns(freq) (1000000000UL / (freq)) + +typedef struct { + uint32_t t_high; + uint32_t t_low; + uint16_t t_sp; + uint16_t t_sudat; + uint16_t t_hddat; + uint16_t t_sclhi_min1; + uint16_t t_sclhi_min2; + uint16_t t_sclratio; +} i2c_timing_t; + +static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, + i2c_mode_t i2c_mode, + i2c_timing_t *timing) +{ + switch (i2c_mode) { + /* + * |Standard mode | Fast mode | Fast mode plus | Uint + * ---------+--------------+-----------+----------------+------- + * t_high | 4.0 | 0.6 | 0.26 | us + * t_low | 4.7 | 1.3 | 0.5 | us + * + */ + case i2c_mode_fast: + timing->t_high = 600; + timing->t_low = 1300; + break; + case i2c_mode_fast_plus: + timing->t_high = 260; + timing->t_low = 500; + break; + case i2c_mode_normal: + timing->t_high = 4000; + timing->t_low = 4700; + break; + default: + return status_i2c_not_supported; + } + + /* + * Spike Suppression | Standard | Fast mode | Fast mode plus | Uint + * | mode | | | + * ------------------+----------+-----------+----------------+------- + * t_sp (min) | - | 0 - 50 | 0 - 50 | ns + * + * T_SP = 50ns / (25ns * (TPM + 1)) + */ + timing->t_sp = 50 / period_in_ns(src_clk_in_hz) / (HPM_I2C_DRV_DEFAULT_TPM + 1); + + /* + * Setup time |Standard mode | Fast mode | Fast mode plus | Uint + * -----------------+--------------+-----------+----------------+------- + * t_sudat (min) | 250 | 100 | 50 | ns + * + * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk * (TPM + 1) + */ + timing->t_sudat = (250 - 2 * period_in_ns(src_clk_in_hz)) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp; + + /* + * Hold time |Standard mode | Fast mode | Fast mode plus | Uint + * ----------------+--------------+-----------+----------------+------- + * t_hddata (min) | 300 | 300 | 0 | ns + * + * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk * (TPM + 1) + */ + timing->t_hddat = (300 - 2 * period_in_ns(src_clk_in_hz)) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp; + + /* + * SCLK High period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk * (TPM + 1) > t_high; + */ + timing->t_sclhi_min1 = (timing->t_high - 2 * period_in_ns(src_clk_in_hz)) + / (HPM_I2C_DRV_DEFAULT_TPM + 1) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp; + + /* + * SCLK Low period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM + 1) > t_low; + */ + timing->t_sclhi_min2 = ((timing->t_low - 2 * period_in_ns(src_clk_in_hz)) + / (HPM_I2C_DRV_DEFAULT_TPM + 1) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp) + / (timing->t_sclratio); + + return status_success; +} + +void i2c_reset(I2C_Type *ptr) +{ + ptr->CTRL = 0; + ptr->CMD = I2C_CMD_RESET; + ptr->SETUP &= ~I2C_SETUP_IICEN_MASK; +} + +hpm_stat_t i2c_init_master(I2C_Type *ptr, uint32_t src_clk_in_hz, i2c_config_t *config) +{ + hpm_stat_t stat = status_success; + i2c_timing_t timing = {0}; + + i2c_reset(ptr); + + timing.t_sclratio = HPM_I2C_DRV_DEFAULT_SCL_RATIO; + stat = i2c_configure_timing(src_clk_in_hz, config->i2c_mode, &timing); + if (status_success != stat) { + return stat; + } + + ptr->TPM = I2C_TPM_TPM_SET(HPM_I2C_DRV_DEFAULT_TPM); + + ptr->SETUP = I2C_SETUP_T_SP_SET(timing.t_sp) + | I2C_SETUP_T_SUDAT_SET(timing.t_sudat) + | I2C_SETUP_T_HDDAT_SET(timing.t_hddat) + | I2C_SETUP_T_SCLRADIO_SET(timing.t_sclratio - 1) + | I2C_SETUP_T_SCLHI_SET(MAX(timing.t_sclhi_min1, timing.t_sclhi_min2)) + | I2C_SETUP_ADDRESSING_SET(config->is_10bit_addressing) + | I2C_SETUP_IICEN_MASK + | I2C_SETUP_MASTER_MASK; + + return status_success; +} + +hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, + uint8_t *addr, uint8_t addr_size_in_byte, + uint8_t *buf, const uint32_t size_in_byte) +{ + hpm_stat_t stat = status_success; + uint32_t left; + uint32_t retry; + + ptr->CMD = I2C_CMD_RESET; + + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->CTRL = I2C_CTRL_PHASE_START_MASK + | I2C_CTRL_PHASE_STOP_MASK + | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_SET(addr_size_in_byte); + + ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + + left = addr_size_in_byte; + while (left) { + ptr->DATA = *(addr++); + left--; + } + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->CTRL = I2C_CTRL_PHASE_START_MASK + | I2C_CTRL_PHASE_STOP_MASK + | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) + | I2C_CTRL_DATACNT_SET(size_in_byte); + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + retry = 0; + left = size_in_byte; + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { + *(buf++) = ptr->DATA; + left--; + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + ptr->STATUS |= I2C_STATUS_CMPL_MASK; + return stat; +} + +hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address, + uint8_t *addr, uint8_t addr_size_in_byte, + uint8_t *buf, const uint32_t size_in_byte) +{ + hpm_stat_t stat = status_success; + uint32_t left; + uint32_t retry; + + ptr->CMD = I2C_CMD_RESET; + + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + ptr->CTRL = I2C_CTRL_PHASE_START_MASK + | I2C_CTRL_PHASE_STOP_MASK + | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_SET(size_in_byte + addr_size_in_byte); + + left = addr_size_in_byte; + while (left) { + ptr->DATA = *(addr++); + left--; + } + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + retry = 0; + left = size_in_byte; + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { + ptr->DATA = *(buf++); + left--; + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } else { + retry++; + } + } + + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + ptr->STATUS |= I2C_STATUS_CMPL_MASK; + + ptr->CMD = I2C_CMD_RESET; + return stat; +} + +hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size) +{ + hpm_stat_t stat = status_success; + uint32_t left; + uint32_t retry; + + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + ptr->CTRL = I2C_CTRL_PHASE_START_MASK + | I2C_CTRL_PHASE_STOP_MASK + | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) + | I2C_CTRL_DATACNT_SET(size); + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + retry = 0; + left = size; + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { + *(buf++) = ptr->DATA; + left--; + if (left) { + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + } + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + }; + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + if (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { + /* I2C slave did not receive this transaction correctly. */ + return status_fail; + } + + ptr->STATUS |= I2C_STATUS_CMPL_MASK | I2C_STATUS_ADDRHIT_MASK; + + ptr->INTEN = 0; + if (i2c_get_data_count(ptr)) { + return status_i2c_transmit_not_completed; + } + + return stat; +} + +hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, + uint8_t *buf, const uint32_t size) +{ + hpm_stat_t stat = status_success; + uint32_t retry; + uint32_t left; + + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + ptr->CTRL = I2C_CTRL_PHASE_START_MASK + | I2C_CTRL_PHASE_STOP_MASK + | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_SET(size); + + retry = 0; + left = size; + while (left) { + if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { + ptr->DATA = *(buf++); + left--; + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + ptr->STATUS |= I2C_STATUS_CMPL_MASK; + + ptr->INTEN = 0; + if (i2c_get_data_count(ptr)) { + return status_i2c_transmit_not_completed; + } + + ptr->CMD = I2C_CMD_RESET; + return stat; +} + +hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz, + i2c_config_t *config, const uint16_t slave_address) +{ + hpm_stat_t stat = status_success; + i2c_timing_t timing = {0}; + + i2c_reset(ptr); + + ptr->ADDR = I2C_ADDR_ADDR_SET(slave_address); + + timing.t_sclratio = HPM_I2C_DRV_DEFAULT_SCL_RATIO; + stat = i2c_configure_timing(src_clk_in_hz, config->i2c_mode, &timing); + if (status_success != stat) { + return stat; + } + + ptr->TPM = I2C_TPM_TPM_SET(HPM_I2C_DRV_DEFAULT_TPM); + + ptr->SETUP = I2C_SETUP_T_SP_SET(timing.t_sp) + | I2C_SETUP_T_SUDAT_SET(timing.t_sudat) + | I2C_SETUP_T_HDDAT_SET(timing.t_hddat) + | I2C_SETUP_T_SCLRADIO_SET(timing.t_sclratio - 1) + | I2C_SETUP_T_SCLHI_SET(MAX(timing.t_sclhi_min1, timing.t_sclhi_min2)) + | I2C_SETUP_ADDRESSING_SET(config->is_10bit_addressing) + | I2C_SETUP_IICEN_MASK; + + return stat; +} + +hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size) +{ + volatile uint32_t status; + uint32_t retry; + uint32_t left; + + retry = 0; + left = size; + while (left) { + status = ptr->STATUS; + if (!(status & I2C_STATUS_FIFOFULL_MASK)) { + ptr->DATA = *(buf++); + left--; + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + /* clear status, CMPL must to be cleared at slave mode before next transaction */ + i2c_clear_status(ptr, ptr->STATUS); + + if (i2c_get_data_count(ptr) != size) { + return status_i2c_transmit_not_completed; + } + + return status_success; +} + +hpm_stat_t i2c_slave_read(I2C_Type *ptr, + uint8_t *buf, + const uint32_t size) +{ + volatile uint32_t status; + uint32_t retry; + uint32_t left; + + retry = 0; + left = size; + while (left) { + status = ptr->STATUS; + if (!(status & I2C_STATUS_FIFOEMPTY_MASK)) { + *(buf++) = ptr->DATA; + left--; + retry = 0; + } else { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + /* clear status, CMPL must to be cleared at slave mode before next transaction */ + i2c_clear_status(ptr, ptr->STATUS); + + if (i2c_get_data_count(ptr) != size) { + return status_i2c_transmit_not_completed; + } + + return status_success; +} + +void i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) +{ + i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK + | I2C_CTRL_PHASE_STOP_MASK + | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_SET(size); + + i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; + + i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; +} + +void i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) +{ + i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK + | I2C_CTRL_PHASE_STOP_MASK + | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) + | I2C_CTRL_DATACNT_SET(size); + + i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; + + i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; +} + +void i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) +{ + i2c_ptr->CTRL |= I2C_CTRL_DATACNT_SET(size); + + i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c new file mode 100644 index 0000000000..0d34d1bc92 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_i2s_drv.h" + +void i2s_reset_all(I2S_Type *ptr) +{ + /* gate off bclk */ + ptr->CFGR |= I2S_CFGR_BCLK_GATEOFF_MASK; + /* gate off mclk */ + ptr->MISC_CFGR |= I2S_MISC_CFGR_MCLK_GATEOFF_MASK; + /* + * clear fifos + */ + ptr->CTRL |= I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK; + ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK); + + /* + * software reset all blocks + */ + ptr->CTRL |= I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK; + ptr->CTRL &= ~(I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); + /* + * disable i2s + */ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; +} + +void i2s_get_default_config(I2S_Type *ptr, i2s_config_t *config) +{ + config->invert_mclk_out = false; + config->invert_mclk_in = false; + config->use_external_mclk = false; + config->invert_bclk_out = false; + config->invert_bclk_in = false; + config->use_external_bclk = false; + config->invert_fclk_out = false; + config->invert_fclk_in = false; + config->use_external_fclk = false; + config->enable_mclk_out = false; + config->frame_start_at_rising_edge = false; + config->fifo_threshold = 4; +} + +void i2s_init(I2S_Type *ptr, i2s_config_t *config) +{ + i2s_reset_all(ptr); + + ptr->CFGR = I2S_CFGR_INV_MCLK_OUT_SET(config->invert_mclk_out) + | I2S_CFGR_INV_MCLK_IN_SET(config->invert_mclk_in) + | I2S_CFGR_MCK_SEL_OP_SET(config->use_external_mclk) + | I2S_CFGR_INV_BCLK_OUT_SET(config->invert_bclk_out) + | I2S_CFGR_INV_BCLK_IN_SET(config->invert_bclk_in) + | I2S_CFGR_BCLK_SEL_OP_SET(config->use_external_bclk) + | I2S_CFGR_INV_FCLK_OUT_SET(config->invert_fclk_out) + | I2S_CFGR_INV_FCLK_IN_SET(config->invert_fclk_in) + | I2S_CFGR_FCLK_SEL_OP_SET(config->use_external_fclk) + | I2S_CFGR_FRAME_EDGE_SET(config->frame_start_at_rising_edge); + ptr->MISC_CFGR = (ptr->MISC_CFGR + & ~(I2S_MISC_CFGR_MCLKOE_MASK + | I2S_MISC_CFGR_MCLK_GATEOFF_MASK)) + | I2S_MISC_CFGR_MCLKOE_SET(config->enable_mclk_out); + ptr->FIFO_THRESH = I2S_FIFO_THRESH_TX_SET(config->fifo_threshold) + | I2S_FIFO_THRESH_RX_SET(config->fifo_threshold); + /** + * @brief i2s interrupt work_around + * + */ + for (uint32_t i = 0; i < I2S_DATA_LINE_MAX; i++) { + ptr->TXDSLOT[i] = 0; + for (uint32_t j = 0; j < I2S_SOC_MAX_TX_CHANNEL_NUM; j++) { + ptr->TXD[i] = 0x01; + } + } +} + +static void i2s_config_cfgr(I2S_Type *ptr, + uint32_t bclk_div, + i2s_transfer_config_t *config) +{ + i2s_gate_bclk(ptr); + ptr->CFGR = I2S_CFGR_BCLK_DIV_SET(bclk_div) + | I2S_CFGR_TDM_EN_SET(config->enable_tdm_mode) + | I2S_CFGR_CH_MAX_SET(config->channel_num_per_frame) + | I2S_CFGR_STD_SET(config->protocol) + | I2S_CFGR_DATSIZ_SET(config->audio_depth) + | I2S_CFGR_CHSIZ_SET(config->channel_length); + i2s_ungate_bclk(ptr); +} + +hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +{ + uint32_t bclk_freq_in_hz; + uint32_t bclk_div; + if (I2S_AUDIO_DEPTH_IS_NOT_VALID(config->audio_depth) + || !config->sample_rate + || !config->channel_num_per_frame + || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) + || !(config->channel_slot_mask & ((1U << config->channel_num_per_frame) - 1U))) { + return status_invalid_argument; + } + + bclk_freq_in_hz = config->sample_rate * ((config->channel_length << 4) + 16) * config->channel_num_per_frame; + bclk_div = mclk_in_hz / bclk_freq_in_hz; + if ((bclk_div > (I2S_CFGR_BCLK_DIV_MASK >> I2S_CFGR_BCLK_DIV_SHIFT))) { + return status_invalid_argument; + } + if ((bclk_div * bclk_freq_in_hz) < mclk_in_hz) { + bclk_div++; + } + + i2s_disable(ptr); + i2s_config_cfgr(ptr, bclk_div, config); + + if (config->channel_slot_mask) { + ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; + } + ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_TX_EN_MASK)) + | I2S_CTRL_TX_EN_SET(1 << config->data_line) + | I2S_CTRL_I2S_EN_MASK; + return status_success; +} + +hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +{ + uint32_t bclk_freq_in_hz; + uint32_t bclk_div; + if (I2S_AUDIO_DEPTH_IS_NOT_VALID(config->audio_depth) + || !config->sample_rate + || !config->channel_num_per_frame + || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) + || !(config->channel_slot_mask & ((1U << config->channel_num_per_frame) - 1U))) { + return status_invalid_argument; + } + + bclk_freq_in_hz = config->sample_rate * ((config->channel_length << 4) + 16) * config->channel_num_per_frame; + bclk_div = mclk_in_hz / bclk_freq_in_hz; + if (!bclk_div || (bclk_div > (I2S_CFGR_BCLK_DIV_MASK >> I2S_CFGR_BCLK_DIV_SHIFT))) { + return status_invalid_argument; + } + if ((bclk_div * bclk_freq_in_hz) < mclk_in_hz) { + bclk_div++; + } + + i2s_disable(ptr); + i2s_config_cfgr(ptr, bclk_div, config); + + if (config->channel_slot_mask) { + ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; + } + ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK)) + | I2S_CTRL_RX_EN_SET(1 << config->data_line) + | I2S_CTRL_I2S_EN_MASK; + return status_success; +} + +hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +{ + uint32_t bclk_freq_in_hz; + uint32_t bclk_div; + if (I2S_AUDIO_DEPTH_IS_NOT_VALID(config->audio_depth) + || !config->sample_rate + || !config->channel_num_per_frame + || (config->channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) + || !(config->channel_slot_mask & ((1U << config->channel_num_per_frame) - 1U))) { + return status_invalid_argument; + } + + bclk_freq_in_hz = config->sample_rate * ((config->channel_length << 4) + 16) * config->channel_num_per_frame; + bclk_div = mclk_in_hz / bclk_freq_in_hz; + if (!bclk_div || (bclk_div > (I2S_CFGR_BCLK_DIV_MASK >> I2S_CFGR_BCLK_DIV_SHIFT))) { + return status_invalid_argument; + } + if ((bclk_div * bclk_freq_in_hz) < mclk_in_hz) { + bclk_div++; + } + + i2s_disable(ptr); + i2s_config_cfgr(ptr, bclk_div, config); + + if (config->channel_slot_mask) { + /* Suppose RX and TX use same channel */ + ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; + ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; + } else { + /** + * @brief i2s interrupt work_around + * + */ + ptr->TXDSLOT[config->data_line] = 0x0000ffff; + } + ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK | I2S_CTRL_TX_EN_MASK)) + | I2S_CTRL_RX_EN_SET(1 << config->data_line) + | I2S_CTRL_TX_EN_SET(1 << config->data_line) + | I2S_CTRL_I2S_EN_MASK; + return status_success; +} + +uint32_t i2s_send_data(I2S_Type *ptr, uint8_t tx_line_index, uint32_t *src, uint32_t size) +{ + register uint32_t count; + for (count = 0; count < size; count ++) { + ptr->TXD[tx_line_index] = *(src + count); + } + return count; +} + +uint32_t i2s_receive_data(I2S_Type *ptr, uint8_t rx_line_index, uint32_t *dst, uint32_t size) +{ + register uint32_t count; + for (count = 0; count < size; count++) { + *(dst + count) = ptr->RXD[rx_line_index]; + } + return count; +} + +void i2s_get_default_transfer_config_for_pdm(i2s_transfer_config_t *transfer) +{ + transfer->sample_rate = PDM_SOC_SAMPLE_RATE_IN_HZ; + transfer->channel_num_per_frame = 16; + transfer->channel_length = I2S_CHANNEL_LENGTH_32_BITS; + transfer->audio_depth = I2S_AUDIO_DEPTH_32_BITS; + transfer->enable_tdm_mode = true; + transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; +} + +void i2s_get_default_transfer_config_for_dao(i2s_transfer_config_t *transfer) +{ + transfer->sample_rate = DAO_SOC_SAMPLE_RATE_IN_HZ; + transfer->channel_num_per_frame = 2; + transfer->channel_length = I2S_CHANNEL_LENGTH_32_BITS; + transfer->audio_depth = I2S_AUDIO_DEPTH_32_BITS; + transfer->enable_tdm_mode = false; + transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; + transfer->data_line = I2S_DATA_LINE_0; + transfer->channel_slot_mask = 0xFFFF; +} + +void i2s_get_default_transfer_config(i2s_transfer_config_t *transfer) +{ + transfer->sample_rate = 48000U; + transfer->channel_num_per_frame = 2; + transfer->channel_length = I2S_CHANNEL_LENGTH_32_BITS; + transfer->audio_depth = I2S_AUDIO_DEPTH_32_BITS; + transfer->enable_tdm_mode = false; + transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; + transfer->data_line = I2S_DATA_LINE_0; + transfer->channel_slot_mask = 0xFFFF; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c new file mode 100644 index 0000000000..03fb6ab440 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_jpeg_drv.h" + +const jpeg_sampling_t jpeg_supported_sampling[5] = { + {2, 2, 1, 1}, /* 420 */ + {2, 1, 1, 1}, /* 422H */ + {1, 2, 1, 1}, /* 422V */ + {1, 1, 1, 1}, /* 444 */ + {1, 1, 0, 0}, /* 400 */ +}; + +void jpeg_disable_irq(JPEG_Type *ptr, uint32_t mask) +{ + if (mask & JPEG_EVENT_IN_DMA_FINISH) { + ptr->INDMA_MISC &= ~(JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK + | JPEG_INDMA_MISC_IRQ_EN_MASK); + } + if (mask & JPEG_EVENT_OUT_DMA_FINISH) { + ptr->OUTDMA_MISC &= ~(JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK + | JPEG_OUTDMA_MISC_IRQ_EN_MASK); + } + if (mask & JPEG_EVENT_ERROR) { + ptr->CFG &= ~(JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK); + } +} + +void jpeg_enable_irq(JPEG_Type *ptr, uint32_t mask) +{ + if (mask & JPEG_EVENT_IN_DMA_FINISH) { + ptr->INDMA_MISC |= JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK + | JPEG_INDMA_MISC_IRQ_EN_MASK; + } + if (mask & JPEG_EVENT_OUT_DMA_FINISH) { + ptr->OUTDMA_MISC |= JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK + | JPEG_OUTDMA_MISC_IRQ_EN_MASK; + } + if (mask & JPEG_EVENT_ERROR) { + ptr->CFG |= JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK; + } +} + +void jpeg_reset(JPEG_Type *ptr) +{ + jpeg_stop(ptr); + jpeg_software_reset(ptr); + ptr->STAT = 0xFFFFFFFFUL; +} + +void jpeg_init(JPEG_Type *ptr) +{ + jpeg_clear_cfg(ptr); + jpeg_reset(ptr); +} + +static uint8_t jpeg_get_pixel_size(uint8_t pixel_format) +{ + return (pixel_format == JPEG_PIXEL_FORMAT_ARGB8888) ? 4 : 2; +} + +static bool jpeg_is_valid_size(uint8_t format, uint32_t width, uint32_t height) +{ + uint32_t align; + if (format > ARRAY_SIZE(jpeg_supported_sampling)) { + return false; + } + align = jpeg_supported_sampling[format].hy * 8; + if (width % align) { + return false; + } + align = jpeg_supported_sampling[format].vy * 8; + if (height % align) { + return false; + } + return true; +} + +#define JPEG_HY(x) ((x)->hy) +#define JPEG_VY(x) ((x)->vy) +#define JPEG_HC(x) ((x)->hc) +#define JPEG_VC(x) ((x)->vc) + +static uint32_t jpeg_calculate_macro_block_count(uint32_t width, uint32_t height, jpeg_sampling_t *sampling) +{ + return (width / (JPEG_HY(sampling) << 3)) * (height / (JPEG_VY(sampling) << 3)); +} + +static void jpeg_config_interal_regs(JPEG_Type *ptr, + bool decoding, + uint32_t macro_block_count, + uint8_t format) +{ + uint8_t hy, vy, hc, vc; + hy = JPEG_HY(&jpeg_supported_sampling[format]); + vy = JPEG_VY(&jpeg_supported_sampling[format]); + hc = JPEG_HC(&jpeg_supported_sampling[format]); + vc = JPEG_VC(&jpeg_supported_sampling[format]); + + if (format == JPEG_SUPPORTED_FORMAT_400) { + ptr->IMGREG1 = JPEG_IMGREG1_RE_MASK; + } else { + ptr->IMGREG1 = JPEG_IMGREG1_RE_MASK | JPEG_IMGREG1_NCOL_SET(2); + } + ptr->IMGREG2 = JPEG_IMGREG2_NMCU_SET(macro_block_count - 1); + ptr->IMGREG3 = JPEG_IMGREG3_NRST_SET(1); + ptr->IMGREG[0] = JPEG_IMGREG_NBLOCK_SET(hy * vy -1); + if (format == JPEG_SUPPORTED_FORMAT_400) { + ptr->IMGREG[1] = 0; + ptr->IMGREG[2] = 0; + } else { + ptr->IMGREG[1] = JPEG_IMGREG_NBLOCK_SET(hc * vc - 1) + | JPEG_IMGREG_QT_SET(1) + | JPEG_IMGREG_HA_SET(1) + | JPEG_IMGREG_HD_SET(1); + ptr->IMGREG[2] = JPEG_IMGREG_NBLOCK_SET(hc * vc - 1) + | JPEG_IMGREG_QT_SET(1) + | JPEG_IMGREG_HA_SET(1) + | JPEG_IMGREG_HD_SET(1); + } + ptr->IMGREG[3] = 0; +} + +hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config) +{ + uint32_t macro_block_count; + uint32_t macro_block_bytes; + uint32_t total_bytes; + jpeg_sampling_t *sampling; + + if (!jpeg_is_valid_size(config->jpeg_format, config->width_in_pixel, config->height_in_pixel)) { + return status_invalid_argument; + } + + sampling = (jpeg_sampling_t *)&jpeg_supported_sampling[config->jpeg_format]; + macro_block_count = jpeg_calculate_macro_block_count(config->width_in_pixel, config->height_in_pixel, sampling); + macro_block_bytes = (JPEG_HY(sampling) * JPEG_VY(sampling) + + 2 * JPEG_HC(sampling) * JPEG_VC(sampling)) << 6; + total_bytes = macro_block_count * macro_block_bytes; + + /* input DMA setting */ + ptr->INDMA_MISC = JPEG_INDMA_MISC_IN_DMA_ID_SET(0) + | JPEG_INDMA_MISC_PACK_DIR_SET(config->byte_order) + | JPEG_INDMA_MISC_MAX_OT_SET(4) + | JPEG_INDMA_MISC_INDMA2D_MASK + | JPEG_INDMA_MISC_IN_DMA_REQ_MASK ; + + ptr->INDMA_CTRL0 = JPEG_INDMA_CTRL0_TTLEN_SET(total_bytes) + | JPEG_INDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_get_pixel_size(config->in_pixel_format)); + ptr->INDMABASE = JPEG_INDMABASE_ADDR_SET(config->in_buffer); + ptr->INXT_CMD = JPEG_INXT_CMD_ADDR_SET(5) | JPEG_INXT_CMD_OP_VALID_MASK; + + /* output DMA setting */ + ptr->OUTDMA_MISC = JPEG_OUTDMA_MISC_EN_OUTCNT_MASK + | JPEG_OUTDMA_MISC_INI_OUTCNT_MASK + | JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(1) + | JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK + | JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK; + ptr->OUTDMABASE = JPEG_OUTDMABASE_ADDR_SET(config->out_buffer); + ptr->OUTDMA_CTRL0 = JPEG_OUTDMA_CTRL0_TTLEN_SET(total_bytes); + ptr->OUTDMA_CTRL1 = JPEG_OUTDMA_CTRL1_ROWLEN_SET(2); + ptr->ONXT_CMD = JPEG_ONXT_CMD_ADDR_SET(5) | JPEG_ONXT_CMD_OP_VALID_MASK; + + jpeg_config_interal_regs(ptr, false, macro_block_count, config->jpeg_format); + + ptr->WIDTH = config->width_in_pixel - 1; + ptr->HEIGHT = config->height_in_pixel - 1; + + if (config->enable_csc) { + if (config->enable_ycbcr) { + ptr->RGB2YUV_COEF0 = JPEG_RGB2YUV_COEF0_C0_SET(0x42) + | JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(0x80) + | JPEG_RGB2YUV_COEF0_Y_OFFSET_SET(0x10) + | JPEG_RGB2YUV_COEF0_ENABLE_MASK + | JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK; + ptr->RGB2YUV_COEF1 = JPEG_RGB2YUV_COEF1_C1_SET(0x81) + | JPEG_RGB2YUV_COEF1_C4_SET(0x7B5); + ptr->RGB2YUV_COEF2 = JPEG_RGB2YUV_COEF2_C2_SET(0x19) + | JPEG_RGB2YUV_COEF2_C3_SET(0x7DA); + ptr->RGB2YUV_COEF3 = JPEG_RGB2YUV_COEF3_C6_SET(0x70) + | JPEG_RGB2YUV_COEF3_C5_SET(0x70); + ptr->RGB2YUV_COEF4 = JPEG_RGB2YUV_COEF4_C8_SET(0x7EE) + | JPEG_RGB2YUV_COEF4_C7_SET(0x7A2); + } else { + ptr->RGB2YUV_COEF0 = JPEG_RGB2YUV_COEF0_C0_SET(0x4D) + | JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(0) + | JPEG_RGB2YUV_COEF0_Y_OFFSET_SET(0x0) + | JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK + | JPEG_RGB2YUV_COEF0_ENABLE_MASK; + ptr->RGB2YUV_COEF1 = JPEG_RGB2YUV_COEF1_C1_SET(0x96) + | JPEG_RGB2YUV_COEF1_C4_SET(0x7B6); + ptr->RGB2YUV_COEF2 = JPEG_RGB2YUV_COEF2_C2_SET(0x1D) + | JPEG_RGB2YUV_COEF2_C3_SET(0x7DA); + ptr->RGB2YUV_COEF3 = JPEG_RGB2YUV_COEF3_C6_SET(0x9D) + | JPEG_RGB2YUV_COEF3_C5_SET(0x70); + ptr->RGB2YUV_COEF4 = JPEG_RGB2YUV_COEF4_C8_SET(0x7E6) + | JPEG_RGB2YUV_COEF4_C7_SET(0x77C); + } + } else { + ptr->RGB2YUV_COEF0 = 0x04030000; + } + + ptr->CFG = JPEG_CFG_CFG_IPATH_SEL_SET(config->in_pixel_format) + | JPEG_CFG_JDATA_FORMAT_SET(config->jpeg_format) + | JPEG_CFG_JPEG_EN_MASK + | JPEG_CFG_START_MASK; + return status_success; +} + + +hpm_stat_t jpeg_start_decode(JPEG_Type *ptr, + jpeg_job_config_t *config, + uint32_t length) +{ + uint32_t macro_block_count; + uint32_t macro_block_bytes; + uint32_t total_bytes; + jpeg_sampling_t *sampling; + + if (!jpeg_is_valid_size(config->jpeg_format, config->width_in_pixel, config->height_in_pixel)) { + return status_invalid_argument; + } + + sampling = (jpeg_sampling_t *)&jpeg_supported_sampling[config->jpeg_format]; + macro_block_count = jpeg_calculate_macro_block_count(config->width_in_pixel, config->height_in_pixel, sampling); + macro_block_bytes = (JPEG_HY(sampling) * JPEG_VY(sampling) + + 2 * JPEG_HC(sampling) * JPEG_VC(sampling)) << 6; + total_bytes = macro_block_count * macro_block_bytes; + + /* input DMA setting */ + ptr->INDMA_MISC = JPEG_INDMA_MISC_IN_DMA_ID_SET(1) + | JPEG_INDMA_MISC_IN_DMA_REQ_MASK; + ptr->INDMABASE = JPEG_INDMABASE_ADDR_SET(config->in_buffer); + /* TODO: check if it has to use the compressed length */ + ptr->INDMA_CTRL0 = JPEG_INDMA_CTRL0_TTLEN_SET(length); + ptr->INDMA_CTRL1 = JPEG_INDMA_CTRL1_ROWLEN_SET(length >> 16); + ptr->INXT_CMD = JPEG_INXT_CMD_ADDR_SET(0x14) | JPEG_INXT_CMD_OP_VALID_MASK; + + /* output DMA setting */ + ptr->OUTDMA_MISC = JPEG_OUTDMA_MISC_EN_OUTCNT_MASK + | JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(0) + | JPEG_OUTDMA_MISC_PACK_DIR_SET(config->byte_order) + | JPEG_OUTDMA_MISC_INI_OUTCNT_MASK + | JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK + | JPEG_OUTDMA_MISC_OUTDMA2D_MASK; + ptr->OUTDMABASE = JPEG_OUTDMABASE_ADDR_SET(config->out_buffer); + ptr->OUTDMA_CTRL0 = JPEG_OUTDMA_CTRL0_TTLEN_SET(total_bytes) + | JPEG_OUTDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_get_pixel_size(config->out_pixel_format)); + ptr->OUTDMA_CTRL1 = JPEG_OUTDMA_CTRL1_ROWLEN_SET(2); + ptr->ONXT_CMD = JPEG_ONXT_CMD_ADDR_SET(0x14) | JPEG_ONXT_CMD_OP_VALID_MASK; + + jpeg_config_interal_regs(ptr, true, macro_block_count, config->jpeg_format); + + ptr->WIDTH = config->width_in_pixel - 1; + ptr->HEIGHT = config->height_in_pixel - 1; + + ptr->CSC_COEF0 = 0x04AB01F0 + | JPEG_CSC_COEF0_YCBCR_MODE_SET(config->enable_ycbcr) + | JPEG_CSC_COEF0_ENABLE_SET(config->enable_csc); + ptr->CSC_COEF1 = 0x01980204; + ptr->CSC_COEF2 = 0x0730079C; + + ptr->CFG = JPEG_CFG_CFG_OPATH_SEL_SET(config->out_pixel_format) + | JPEG_CFG_JDATA_FORMAT_SET(config->jpeg_format) + | JPEG_CFG_JPEG_EN_MASK + | JPEG_CFG_START_MASK + | JPEG_CFG_MODE_MASK; + return status_success; +} + +#define JPEG_TABLE_WIDTH(x) (((x) & 0xF00000UL) >> 20) +#define JPEG_TABLE_LENGTH(x) (((x) & 0xFFFF0UL) >> 4) +#define JPEG_TABLE_TYPE(x) (((x) & 0xFUL)) +#define JPEG_TABLE_VALUE_MASK(x) (((x) == 4) ? (0xFFFFFFFFUL) : ((1 << ((x) << 3)) - 1)) + +hpm_stat_t jpeg_fill_table(JPEG_Type *ptr, jpeg_table_t table, uint8_t *data, uint32_t count) +{ + uint32_t i = 0; + uint32_t width = JPEG_TABLE_WIDTH(table); + uint32_t length = JPEG_TABLE_LENGTH(table); + uint32_t type = JPEG_TABLE_TYPE(table); + uint32_t *p; + + if (length != count) { + return status_invalid_argument; + } + + ptr->BUFADDR = type << 28; + for (i = 0; i < count; i++) { + p = (uint32_t *) &data[i * width]; + ptr->BUFDATA = JPEG_BUFADDR_ADDR_SET(*p & JPEG_TABLE_VALUE_MASK(width)); + } + return status_success; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c new file mode 100644 index 0000000000..480f57af9c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_lcdc_drv.h" + +#define LCDC_FIFO_THRESHOLD (0x70) + +static uint32_t lcdc_pixel_format(display_pixel_format_t format) +{ + switch (format) { + case display_pixel_format_argb8888: + return 9; + case display_pixel_format_rgb565: + return 4; + case display_pixel_format_yuv422: + return 7; + case display_pixel_format_ycbcr422: + return 7; + default: + return 9; + } +} + +/*! + * @brief Get LCDC byteorder value. + * + * @param byteorder Dispaly byteorder value. + * @return LCDC byteorder value. + */ +static uint8_t lcdc_byteorder(display_byteorder_t byteorder) +{ + switch (byteorder) { + case display_byteorder_a3a2a1a0: /* LSB */ + return 0; + case display_byteorder_a0a1a2a3: /* MSB */ + return 1; + default: + return 0; + } +} + +void lcdc_get_default_layer_config(LCDC_Type *ptr, lcdc_layer_config_t *layer, display_pixel_format_t pixel_format, uint8_t layer_index) +{ + layer->max_bytes = lcdc_layer_max_bytes_64; + /* different layer has different max_ot configuration */ + if (layer_index < LCDC_SOC_MAX_CSC_LAYER_COUNT) { + layer->max_ot = 0; + } else { + layer->max_ot = 2; + } + layer->byteorder = display_byteorder_a3a2a1a0; + if (display_pixel_format_is_yuv_format(pixel_format)) { + layer->yuv = display_yuv_mode_422_y1u1y2v1; /* If YUV format, change byte sequence to YUYV */ + } else { + layer->yuv = display_yuv_mode_422_u1y1v1y2; /* Not change byte sequence */ + } + layer->pixel_format = pixel_format; + + layer->alphablend.src_alpha = 0; + layer->alphablend.dst_alpha = 0; + layer->alphablend.src_alpha_op = display_alpha_op_invalid; + layer->alphablend.dst_alpha_op = display_alpha_op_invalid; + layer->alphablend.mode = display_alphablend_mode_clear; + + switch(pixel_format) { + case display_pixel_format_yuv422: + layer->csc_config.enable = true; + layer->csc_config.ycbcr_mode = false; + layer->csc_config.yuv2rgb_coef.c0 = 0x100; + layer->csc_config.yuv2rgb_coef.uv_offset = 0; + layer->csc_config.yuv2rgb_coef.y_offset = 0; + layer->csc_config.yuv2rgb_coef.c1 = 0x123; + layer->csc_config.yuv2rgb_coef.c2 = 0x76B; + layer->csc_config.yuv2rgb_coef.c3 = 0x79C; + layer->csc_config.yuv2rgb_coef.c4 = 0x208; + break; + case display_pixel_format_ycbcr422: + layer->csc_config.enable = true; + layer->csc_config.ycbcr_mode = true; + layer->csc_config.yuv2rgb_coef.c0 = 0x12A; + layer->csc_config.yuv2rgb_coef.uv_offset = 0x180; + layer->csc_config.yuv2rgb_coef.y_offset = 0x1F0; + layer->csc_config.yuv2rgb_coef.c1 = 0x198; + layer->csc_config.yuv2rgb_coef.c2 = 0x730; + layer->csc_config.yuv2rgb_coef.c3 = 0x79C; + layer->csc_config.yuv2rgb_coef.c4 = 0x204; + break; + default: + layer->csc_config.enable = false; + layer->csc_config.ycbcr_mode = false; + layer->csc_config.yuv2rgb_coef.c0 = 0; + layer->csc_config.yuv2rgb_coef.uv_offset = 0; + layer->csc_config.yuv2rgb_coef.y_offset = 0; + layer->csc_config.yuv2rgb_coef.c1 = 0; + layer->csc_config.yuv2rgb_coef.c2 = 0; + layer->csc_config.yuv2rgb_coef.c3 = 0; + layer->csc_config.yuv2rgb_coef.c4 = 0; + break; + } +} + +void lcdc_get_default_config(LCDC_Type *ptr, lcdc_config_t *config) +{ + config->resolution_x = 480; + config->resolution_y = 272; + config->hsync.front_porch_pulse = 40; + config->hsync.back_porch_pulse = 50; + config->hsync.pulse_width = 30; + config->vsync.front_porch_pulse = 20; + config->vsync.back_porch_pulse = 20; + config->vsync.pulse_width = 10; + config->background.u = 0x0; + + config->control.display_mode = lcdc_display_mode_normal; + config->control.line_pattern = lcdc_line_pattern_rgb; + config->control.invert_pixel_clock = false; + config->control.invert_pixel_data = false; + config->control.invert_href = false; + config->control.invert_vsync = false; + config->control.invert_hsync = false; +} + +void lcdc_reset_register_values(LCDC_Type *ptr) +{ + uint8_t i = 0; + + lcdc_turn_off_display(ptr); + + ptr->DISP_WN_SIZE = 0; + ptr->INT_EN = 0; + ptr->ST = 0xFFFFFFFFU; + ptr->DMA_ST = 0xFFFFFFFFU; + ptr->VSYNC_PARA = 0x00C01803U; + ptr->HSYNC_PARA = 0x00C01803U; + + for (i = 0; i < LCDC_SOC_MAX_LAYER_COUNT; i++) { + ptr->LAYER[i].LAYCTRL = 0; + ptr->LAYER[i].ALPHAS = 0; + ptr->LAYER[i].LAYSIZE = 0; + ptr->LAYER[i].LAYPOS = 0; + ptr->LAYER[i].START0 = 0; + ptr->LAYER[i].LINECFG = 0; + ptr->LAYER[i].BG_CL = 0; + } + + for (i = 0; i < LCDC_SOC_MAX_CSC_LAYER_COUNT; i++) { + ptr->LAYER[i].CSC_COEF0 = 0; + ptr->LAYER[i].CSC_COEF1 = 0; + ptr->LAYER[i].CSC_COEF2 = 0; + } +} + +void lcdc_init(LCDC_Type *ptr, lcdc_config_t *config) +{ + lcdc_reset_register_values(ptr); + + ptr->DISP_WN_SIZE = LCDC_DISP_WN_SIZE_X_SET(config->resolution_x) | + LCDC_DISP_WN_SIZE_Y_SET(config->resolution_y); + ptr->HSYNC_PARA = + LCDC_HSYNC_PARA_FP_SET(config->hsync.front_porch_pulse) + | LCDC_HSYNC_PARA_BP_SET(config->hsync.back_porch_pulse) + | LCDC_HSYNC_PARA_PW_SET(config->hsync.pulse_width); + ptr->BGND_CL = LCDC_BGND_CL_B_SET(config->background.b) + | LCDC_BGND_CL_G_SET(config->background.g) + | LCDC_BGND_CL_R_SET(config->background.r); + ptr->VSYNC_PARA = + LCDC_VSYNC_PARA_FP_SET(config->vsync.front_porch_pulse) + | LCDC_VSYNC_PARA_BP_SET(config->vsync.back_porch_pulse) + | LCDC_VSYNC_PARA_PW_SET(config->vsync.pulse_width); + ptr->TXFIFO = LCDC_TXFIFO_THRSH_SET(LCDC_FIFO_THRESHOLD); + ptr->CTRL = LCDC_CTRL_DISP_MODE_SET(config->control.display_mode) + | LCDC_CTRL_LINE_PATTERN_SET(config->control.line_pattern) + | LCDC_CTRL_INV_PXDATA_SET(config->control.invert_pixel_data) + | LCDC_CTRL_INV_PXCLK_SET(config->control.invert_pixel_clock) + | LCDC_CTRL_INV_HREF_SET(config->control.invert_href) + | LCDC_CTRL_INV_VSYNC_SET(config->control.invert_vsync) + | LCDC_CTRL_INV_HSYNC_SET(config->control.invert_hsync); +} + +hpm_stat_t lcdc_config_layer(LCDC_Type *ptr, + uint8_t layer_index, + lcdc_layer_config_t *layer, + bool enable_layer) +{ + uint8_t byteorder; + uint32_t pitch; + uint32_t format; + uint32_t ctrl = ptr->LAYER[layer_index].LAYCTRL; + + if ((!LCDC_SOC_LAYER_SUPPORTS_CSC(layer_index) && layer->csc_config.enable) + || (!LCDC_SOC_LAYER_SUPPORTS_YUV(layer_index) + && (display_pixel_format_is_yuv_format(layer->pixel_format)))) { + return status_lcdc_layer_not_supported; + } + + ptr->LAYER[layer_index].LAYSIZE = + LCDC_LAYER_LAYSIZE_HEIGHT_SET(layer->height) + | LCDC_LAYER_LAYSIZE_WIDTH_SET(layer->width); + ptr->LAYER[layer_index].LAYPOS = + LCDC_LAYER_LAYPOS_X_SET(layer->position_x) + | LCDC_LAYER_LAYPOS_Y_SET(layer->position_y); + ptr->LAYER[layer_index].START0 = LCDC_LAYER_START0_ADDR0_SET((uint32_t)layer->buffer); + ptr->LAYER[layer_index].ALPHAS = LCDC_LAYER_ALPHAS_LOCD_SET(layer->alphablend.src_alpha) + | LCDC_LAYER_ALPHAS_IND_SET(layer->alphablend.dst_alpha); + + pitch = display_get_pitch_length_in_byte(layer->pixel_format, layer->width); + ptr->LAYER[layer_index].LINECFG = LCDC_LAYER_LINECFG_MPT_SIZE_SET(layer->max_bytes) + | LCDC_LAYER_LINECFG_MAX_OT_SET(layer->max_ot) + | LCDC_LAYER_LINECFG_PITCH_SET(pitch); + ptr->LAYER[layer_index].BG_CL = LCDC_LAYER_BG_CL_ARGB_SET(layer->background.u); + + ptr->LAYER[layer_index].CSC_COEF0 = + LCDC_LAYER_CSC_COEF0_ENABLE_SET(layer->csc_config.enable) + | LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SET(layer->csc_config.ycbcr_mode) + | LCDC_LAYER_CSC_COEF0_C0_SET(layer->csc_config.yuv2rgb_coef.c0) + | LCDC_LAYER_CSC_COEF0_UV_OFFSET_SET(layer->csc_config.yuv2rgb_coef.uv_offset) + | LCDC_LAYER_CSC_COEF0_Y_OFFSET_SET(layer->csc_config.yuv2rgb_coef.y_offset); + ptr->LAYER[layer_index].CSC_COEF1 = + LCDC_LAYER_CSC_COEF1_C1_SET(layer->csc_config.yuv2rgb_coef.c1) + | LCDC_LAYER_CSC_COEF1_C4_SET(layer->csc_config.yuv2rgb_coef.c4); + ptr->LAYER[layer_index].CSC_COEF2 = + LCDC_LAYER_CSC_COEF2_C2_SET(layer->csc_config.yuv2rgb_coef.c2) + | LCDC_LAYER_CSC_COEF2_C3_SET(layer->csc_config.yuv2rgb_coef.c3); + + /* bit18 is reserved but has to be set to 1 */ + ctrl |= 1 << 18; + + byteorder = lcdc_byteorder(layer->byteorder); + format = lcdc_pixel_format(layer->pixel_format); + ctrl = (ctrl & ~(LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK + | LCDC_LAYER_LAYCTRL_AB_MODE_MASK + | LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK + | LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK + | LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK)) + | LCDC_LAYER_LAYCTRL_PACK_DIR_SET(byteorder) + | LCDC_LAYER_LAYCTRL_PIXFORMAT_SET(format) + | LCDC_LAYER_LAYCTRL_AB_MODE_SET(layer->alphablend.mode) + | LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SET(layer->alphablend.src_alpha_op) + | LCDC_LAYER_LAYCTRL_INALPHA_OP_SET(layer->alphablend.dst_alpha_op) + | LCDC_LAYER_LAYCTRL_YUV_FORMAT_SET(layer->yuv); + + if (enable_layer) { + ctrl |= LCDC_LAYER_LAYCTRL_EN_MASK; + } + ptr->LAYER[layer_index].LAYCTRL = ctrl | LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; + return status_success; +} + +void lcdc_turn_off_display(LCDC_Type *ptr) +{ + if (ptr->CTRL & LCDC_CTRL_DISP_ON_MASK) { + ptr->INT_EN = 0; + + /* 1. wait for current frame end */ + ptr->ST = 0xFFFFFFFF; + while((ptr->ST & LCDC_ST_VS_BLANK_MASK) == 0); + + /* 2. issue display off */ + ptr->ST = 0xFFFFFFFF; + lcdc_software_reset(ptr); + ptr->CTRL &= ~LCDC_CTRL_DISP_ON_MASK; + while((ptr->ST & LCDC_ST_VS_BLANK_MASK) == 0); + } + return; +} + +void lcdc_turn_on_display(LCDC_Type *ptr) +{ + if (!(ptr->CTRL & LCDC_CTRL_DISP_ON_MASK)) { + ptr->CTRL |= LCDC_CTRL_DISP_ON_MASK; + } +} + +void lcdc_layer_update_pixel_format(LCDC_Type *ptr, uint8_t layer_index, + uint8_t pixel_format) +{ + uint32_t pitch; + uint32_t width = (ptr->LAYER[layer_index].LAYSIZE & LCDC_LAYER_LAYSIZE_WIDTH_MASK) + >> LCDC_LAYER_LAYSIZE_WIDTH_SHIFT; + pitch = display_get_pitch_length_in_byte(pixel_format, width); + ptr->LAYER[layer_index].LINECFG = (ptr->LAYER[layer_index].LINECFG & ~LCDC_LAYER_LINECFG_PITCH_MASK) + | LCDC_LAYER_LINECFG_PITCH_SET(pitch); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c new file mode 100644 index 0000000000..68cdc573ff --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mchtmr_drv.h" + +void mchtmr_init_counter(MCHTMR_Type *ptr, uint64_t v) +{ + volatile uint32_t *p = (volatile uint32_t *) &ptr->MTIME; + /* + * When [31:29] == 7, low 32 bits need to be set to 0 first, + * then set high 32 bits and low 32 bits; otherwise, + * low 32 bit can be set firstly then high 32 bits. + */ + if ((v & 0xE0000000) == 0xE0000000) { + *p = 0; + *(p + 1) = v >> 32; + *p = v & 0xFFFFFFFF; + } else { + *p = v & 0xFFFFFFFF; + *(p + 1) = v >> 32; + } +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c new file mode 100644 index 0000000000..695a56ecc5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_pcfg_drv.h" +#include "hpm_soc_feature.h" + +#define PCFG_CURRENT_MEASUREMENT_STEP (50U) +#define HPM_PMU_DRV_RETRY_COUNT (5000U) + +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv) +{ + if ((mv < PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV) + || (mv > PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV)) { + return status_pcfg_ldo_out_of_range; + } + ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; + ptr->LDO1P1 = PCFG_LDO1P1_ENABLE_MASK | PCFG_LDO1P1_VOLT_SET(mv); + return status_success; +} + +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv) +{ + uint32_t retry = 0; + if ((mv < PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV) + || (mv > PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV)) { + return status_pcfg_ldo_out_of_range; + } + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; + ptr->LDO2P5 = PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(mv); + + while (!PCFG_LDO2P5_READY_GET(ptr->LDO2P5)) { + if (retry > HPM_PMU_DRV_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_PMU_DRV_RETRY_COUNT) { + return status_timeout; + } + + return status_success; +} + +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr) +{ + uint32_t retry = 0; + while (!pcfg_dcdc_is_measure_current_valid(ptr)) { + if (retry > HPM_PMU_DRV_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_PMU_DRV_RETRY_COUNT) { + return 0; + } + + return PCFG_DCDC_CURRENT_LEVEL_GET(ptr->DCDC_CURRENT) * PCFG_CURRENT_MEASUREMENT_STEP; +} + +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv) +{ + hpm_stat_t stat = status_success; + if ((mv < PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV) || (mv > PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV)) { + return status_invalid_argument; + } + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_VOLT_MASK) | PCFG_DCDC_MODE_VOLT_SET(mv); + return stat; +} + +#define PCFG_RC24M_FREQ (24000000UL) +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config) +{ + uint32_t calculated_freq; + uint16_t mul = 1; + uint16_t div = 1; + + if (!(config->freq_in_hz < PCFG_RC24M_FREQ)) { + /* calculate div */ + div = PCFG_RC24M_FREQ / config->freq_in_hz; + } + calculated_freq = PCFG_RC24M_FREQ / div; + while (calculated_freq < config->freq_in_hz) { + calculated_freq *= (mul++); + } + ptr->TRACK_TARGET = PCFG_TRACK_TARGET_PRE_DIV_SET(div - 1) + | PCFG_TRACK_TARGET_TARGET_SET(mul - 1); + ptr->RC24M_TRACK = PCFG_RC24M_TRACK_SEL24M_SET(config->reference) + | PCFG_RC24M_TRACK_RETURN_SET(config->return_to_default_on_xtal_loss) + | PCFG_RC24M_TRACK_TRACK_SET(config->free_run); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c new file mode 100644 index 0000000000..087f49bec8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_pdm_drv.h" +#define PDM_WORKING_CLOCK_FREQ_IN_HZ (48000UL) + +void pdm_get_default_config(PDM_Type *ptr, pdm_config_t *config) +{ + config->sof_at_ref_clk_falling_edge = true; + config->bypass_pdm_clk_div = false; + config->enable_pdm_clk_out = true; + config->pdm_clk_div = 3; + config->capture_delay = 1; + config->dec_after_cic = 3; + config->post_scale = 12; + config->sigma_delta_order = PDM_CIC_SIGMA_DELTA_ORDER_6; + config->cic_dec_ratio = 64; + config->enable_hpf = true; +} + +hpm_stat_t pdm_init(PDM_Type *ptr, pdm_config_t *config) +{ + if (pdm_is_running(ptr)) { + pdm_stop(ptr); + } + /* pdm_software_reset(ptr); */ + + /* ptr->CTRL = PDM_CTRL_DIS_CLK_GATE_MASK; */ + ptr->CTRL = PDM_CTRL_SOF_FEDGE_SET(config->sof_at_ref_clk_falling_edge) + | PDM_CTRL_DEC_AFT_CIC_SET(config->dec_after_cic) + | PDM_CTRL_CAPT_DLY_SET(config->capture_delay) + | PDM_CTRL_PDM_CLK_HFDIV_SET(config->pdm_clk_div) + | PDM_CTRL_PDM_CLK_DIV_BYPASS_SET(config->bypass_pdm_clk_div) + | PDM_CTRL_PDM_CLK_OE_SET(config->enable_pdm_clk_out) + | PDM_CTRL_HPF_EN_SET(config->enable_hpf); + + ptr->CH_CTRL = 0xF000FF; + ptr->CH_CFG = 0x50000; + ptr->CIC_CFG = PDM_CIC_CFG_POST_SCALE_SET(config->post_scale) + | PDM_CIC_CFG_SGD_SET(config->sigma_delta_order) + | PDM_CIC_CFG_CIC_DEC_RATIO_SET(config->cic_dec_ratio); + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c new file mode 100644 index 0000000000..cbadccaafa --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c @@ -0,0 +1,777 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_pdma_drv.h" + +#define PDMA_SCALE_FRAC_BITS 12 + +void pdma_set_block_size(PDMA_Type *ptr, pdma_blocksize_t size) +{ + ptr->CTRL = (ptr->CTRL & ~PDMA_CTRL_BS16_MASK) + | ((size == pdma_blocksize_16x16) ? PDMA_CTRL_BS16_MASK : 0); +} + +void pdma_enable_plane(PDMA_Type *ptr, pdma_plane_t enable_plane, bool enable) +{ + uint32_t mask; + switch (enable_plane) { + case pdma_plane_both: + mask = (PDMA_CTRL_P0_EN_MASK | PDMA_CTRL_P1_EN_MASK); + break; + case pdma_plane_src: + mask = PDMA_CTRL_P0_EN_MASK; + break; + case pdma_plane_dst: + mask = PDMA_CTRL_P1_EN_MASK; + break; + default: + mask = 0; + break; + } + if (!mask) { + return; + } + if (enable) { + ptr->CTRL |= mask; + } else { + ptr->CTRL &= ~mask; + } +} + +void pdma_enable_irq(PDMA_Type *ptr, uint32_t mask, bool enable) +{ + mask &= PDMA_CTRL_AXIERR_IRQ_EN_MASK | PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK; + if (enable) { + ptr->CTRL |= mask | PDMA_CTRL_IRQ_EN_MASK; + } else { + ptr->CTRL &= ~mask; + } +} + +void pdma_get_default_config(PDMA_Type *ptr, pdma_config_t *config, display_pixel_format_t pixel_format) +{ + config->block_size = pdma_blocksize_16x16; + config->enable_plane = pdma_plane_src; + + if (display_pixel_format_is_yuv_format(pixel_format)) { + config->byteorder = display_byteorder_a0a1a2a3; /* change yuv fromat output byte order to YUYV format */ + } else { + config->byteorder = display_byteorder_a3a2a1a0; + } +} + +void pdma_get_default_plane_config(PDMA_Type *ptr, pdma_plane_config_t *config, display_pixel_format_t pixel_format) +{ + config->swap_byte3_byte1 = false; + config->byteorder = display_byteorder_a3a2a1a0; + config->use_background_as_clear = true; + config->flip = pdma_flip_none; + config->rotate = pdma_rotate_0_degree; + config->x_dec = pdma_decimation_by_1; + config->y_dec = pdma_decimation_by_1; + config->byte_swap = false; + config->pixel_format = pixel_format; + config->buffer = 0; + config->background = 0xFFFFFFFF; + config->x_scale = PDMA_MAKE_SCALE_SET(1, 0); + config->y_scale = PDMA_MAKE_SCALE_SET(1, 0); + config->x_offset = 0; + config->y_offset = 0; + config->colorkey_high = 0; + config->colorkey_low = 0xFFFFFF; + config->width = 0; + config->height = 0; + config->pitch = 0; + + switch(pixel_format) { + case display_pixel_format_yuv422: + config->ycbcr_mode = false; + config->bypass_colorspace_conversion = false; + break; + case display_pixel_format_ycbcr422: + config->ycbcr_mode = true; + config->bypass_colorspace_conversion = false; + break; + default: + config->ycbcr_mode = false; + config->bypass_colorspace_conversion = true; + break; + } +} + +void pdma_get_default_yuv2rgb_coef_config(PDMA_Type *ptr, display_yuv2rgb_coef_t *yuv2rgb_coef, display_pixel_format_t source_format) +{ + /* Two plane share one YUV2RGB_COEF, not support one plane format is yuv422 and another is ycbcr422 */ + + switch(source_format) { + case display_pixel_format_yuv422: + yuv2rgb_coef->c0 = 0x100; + yuv2rgb_coef->uv_offset = 0; + yuv2rgb_coef->y_offset = 0; + yuv2rgb_coef->c1 = 0x123; + yuv2rgb_coef->c2 = 0x76B; + yuv2rgb_coef->c3 = 0x79C; + yuv2rgb_coef->c4 = 0x208; + break; + case display_pixel_format_ycbcr422: + yuv2rgb_coef->c0 = 0x12A; + yuv2rgb_coef->uv_offset = 0x180; + yuv2rgb_coef->y_offset = 0x1F0; + yuv2rgb_coef->c1 = 0x198; + yuv2rgb_coef->c2 = 0x730; + yuv2rgb_coef->c3 = 0x79C; + yuv2rgb_coef->c4 = 0x204; + break; + default: + yuv2rgb_coef->c0 = 0; + yuv2rgb_coef->uv_offset = 0; + yuv2rgb_coef->y_offset = 0; + yuv2rgb_coef->c1 = 0; + yuv2rgb_coef->c2 = 0; + yuv2rgb_coef->c3 = 0; + yuv2rgb_coef->c4 = 0; + break; + } +} + +void pdma_get_default_output_config(PDMA_Type *ptr, pdma_output_config_t *config, display_pixel_format_t pixel_format) +{ + uint8_t i; + config->alphablend.dst_alpha = 0x0; + config->alphablend.src_alpha = 0x0; + config->alphablend.src_alpha_op = display_alpha_op_invalid; + config->alphablend.dst_alpha_op = display_alpha_op_invalid; + config->alphablend.mode = display_alphablend_mode_plus; + config->pixel_format = pixel_format; + config->buffer = 0; + for (i = 0; i < PDMA_SOC_PS_MAX_COUNT; i++) { + config->plane[i].x = 0; + config->plane[i].y = 0; + config->plane[i].width = 0; + config->plane[i].height = 0; + } + config->width = 0; + config->height = 0; + config->pitch = 0; + + switch(pixel_format) { + case display_pixel_format_yuv422: + config->rgb2yuv_config.enable = true; + config->rgb2yuv_config.ycbcr_mode = false; + config->rgb2yuv_config.c0 = 0x4D; + config->rgb2yuv_config.uv_offset = 0; + config->rgb2yuv_config.y_offset = 0; + config->rgb2yuv_config.c1 = 0x96; + config->rgb2yuv_config.c2 = 0x1D; + config->rgb2yuv_config.c3 = 0x7DA; + config->rgb2yuv_config.c4 = 0x7B6; + config->rgb2yuv_config.c5 = 0x70; + config->rgb2yuv_config.c6 = 0x9D; + config->rgb2yuv_config.c7 = 0x77C; + config->rgb2yuv_config.c8 = 0x7E6; + break; + case display_pixel_format_ycbcr422: + config->rgb2yuv_config.enable = true; + config->rgb2yuv_config.ycbcr_mode = true; + config->rgb2yuv_config.c0 = 0x42; + config->rgb2yuv_config.uv_offset = 0x80; + config->rgb2yuv_config.y_offset = 0x10; + config->rgb2yuv_config.c1 = 0x81; + config->rgb2yuv_config.c2 = 0x19; + config->rgb2yuv_config.c3 = 0x7DA; + config->rgb2yuv_config.c4 = 0x7B5; + config->rgb2yuv_config.c5 = 0x70; + config->rgb2yuv_config.c6 = 0x70; + config->rgb2yuv_config.c7 = 0x7A2; + config->rgb2yuv_config.c8 = 0x7EE; + break; + default: + config->rgb2yuv_config.enable = false; + config->rgb2yuv_config.ycbcr_mode = false; + config->rgb2yuv_config.c0 = 0; + config->rgb2yuv_config.uv_offset = 0; + config->rgb2yuv_config.y_offset = 0; + config->rgb2yuv_config.c1 = 0; + config->rgb2yuv_config.c2 = 0; + config->rgb2yuv_config.c3 = 0; + config->rgb2yuv_config.c4 = 0; + config->rgb2yuv_config.c5 = 0; + config->rgb2yuv_config.c6 = 0; + config->rgb2yuv_config.c7 = 0; + config->rgb2yuv_config.c8 = 0; + break; + } +} + +void pdma_stop(PDMA_Type *ptr) +{ + ptr->CTRL &= ~PDMA_CTRL_PDMA_EN_MASK; + pdma_software_reset(ptr); + ptr->STAT = 0x21F; +} + +void pdma_init(PDMA_Type *ptr, pdma_config_t *config) +{ + uint32_t mask; + pdma_stop(ptr); + switch (config->enable_plane) { + case pdma_plane_both: + mask = (PDMA_CTRL_P0_EN_MASK | PDMA_CTRL_P1_EN_MASK); + break; + case pdma_plane_dst: + mask = PDMA_CTRL_P1_EN_MASK; + break; + case pdma_plane_src: + mask = PDMA_CTRL_P0_EN_MASK; + break; + default: + mask = 0; + break; + } + + if (config->block_size == pdma_blocksize_16x16) { + mask |= PDMA_CTRL_BS16_MASK; + } + + ptr->CTRL = PDMA_CTRL_PACK_DIR_SET(config->byteorder) | mask; +} + +static uint32_t pdma_pixel_format(display_pixel_format_t display_format) +{ + switch (display_format) { + case display_pixel_format_rgb565: + return 0xE; + case display_pixel_format_argb8888: + return 0; + case display_pixel_format_yuv422: + return 0x13; + case display_pixel_format_ycbcr422: + return 0x13; + default: + return 0; + } +} + +void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_config, void *yuv2rgb_coef) +{ + uint32_t pitch; + uint32_t format; + + assert((plane_src_config != NULL) || (plane_dst_config != NULL)); + + pdma_plane_config_t *plane_src = (pdma_plane_config_t *)plane_src_config; + pdma_plane_config_t *plane_dst = (pdma_plane_config_t *)plane_dst_config; + display_yuv2rgb_coef_t *yuv2rgb = (display_yuv2rgb_coef_t *)yuv2rgb_coef; + + if (plane_src != NULL) { + assert((plane_src->bypass_colorspace_conversion) || (yuv2rgb != NULL)); + } + if (plane_dst != NULL) { + assert((plane_dst->bypass_colorspace_conversion) || (yuv2rgb != NULL)); + } + if ((plane_src != NULL) || (plane_dst != NULL)) { + assert(!(display_pixel_format_is_yuv_format(plane_src->pixel_format) && display_pixel_format_is_yuv_format(plane_dst->pixel_format)) + || (plane_src->pixel_format == plane_dst->pixel_format)); + } + + if (plane_src != NULL) { + if (plane_src->pitch == 0) { + pitch = display_get_pitch_length_in_byte(plane_src->pixel_format, plane_src->width); + } else { + pitch = plane_src->pitch; + } + format = pdma_pixel_format(plane_src->pixel_format); + ptr->PS[pdma_plane_src].BUF = PDMA_PS_BUF_ADDR_SET((uint32_t) plane_src->buffer); + ptr->PS[pdma_plane_src].PITCH = PDMA_PS_PITCH_BYTELEN_SET(pitch); + ptr->PS[pdma_plane_src].BKGD = PDMA_PS_BKGD_COLOR_SET(plane_src->background); + ptr->PS[pdma_plane_src].SCALE = PDMA_PS_SCALE_X_SET(plane_src->x_scale) + | PDMA_PS_SCALE_Y_SET(plane_src->y_scale); + ptr->PS[pdma_plane_src].OFFSET = PDMA_PS_OFFSET_X_SET(plane_src->x_offset) + | PDMA_PS_OFFSET_Y_SET(plane_src->y_offset); + ptr->PS[pdma_plane_src].CLRKEY_LOW = PDMA_PS_CLRKEY_LOW_LIMIT_SET(plane_src->colorkey_low); + ptr->PS[pdma_plane_src].CLRKEY_HIGH = PDMA_PS_CLRKEY_HIGH_LIMIT_SET(plane_src->colorkey_high); + ptr->PS[pdma_plane_src].ORG = PDMA_PS_ORG_HIGHT_SET(plane_src->height) + | PDMA_PS_ORG_WIDTH_SET(plane_src->width); + ptr->PS[pdma_plane_src].CTRL = PDMA_PS_CTRL_INB13_SWAP_SET(plane_src->swap_byte3_byte1) + | PDMA_PS_CTRL_PACK_DIR_SET(plane_src->byteorder) + | PDMA_PS_CTRL_BKGCL4CLR_SET(plane_src->use_background_as_clear) + | PDMA_PS_CTRL_YCBCR_MODE_SET(plane_src->ycbcr_mode) + | PDMA_PS_CTRL_BYPASS_SET(plane_src->bypass_colorspace_conversion) + | ((plane_src->flip << PDMA_PS_CTRL_HFLIP_SHIFT) + & (PDMA_PS_CTRL_VFLIP_MASK| PDMA_PS_CTRL_HFLIP_MASK)) + | PDMA_PS_CTRL_ROTATE_SET(plane_src->rotate) + | PDMA_PS_CTRL_DECY_SET(plane_src->y_dec) + | PDMA_PS_CTRL_DECX_SET(plane_src->x_dec) + | PDMA_PS_CTRL_HW_BYTE_SWAP_SET(plane_src->byte_swap) + | PDMA_PS_CTRL_FORMAT_SET(format); + } + + if (plane_dst != NULL) { + if (plane_dst->pitch == 0) { + pitch = display_get_pitch_length_in_byte(plane_src->pixel_format, plane_src->width); + } else { + pitch = plane_dst->pitch; + } + format = pdma_pixel_format(plane_dst->pixel_format); + ptr->PS[pdma_plane_dst].BUF = PDMA_PS_BUF_ADDR_SET((uint32_t) plane_dst->buffer); + ptr->PS[pdma_plane_dst].PITCH = PDMA_PS_PITCH_BYTELEN_SET(pitch); + ptr->PS[pdma_plane_dst].BKGD = PDMA_PS_BKGD_COLOR_SET(plane_dst->background); + ptr->PS[pdma_plane_dst].SCALE = PDMA_PS_SCALE_X_SET(plane_dst->x_scale) + | PDMA_PS_SCALE_Y_SET(plane_dst->y_scale); + ptr->PS[pdma_plane_dst].OFFSET = PDMA_PS_OFFSET_X_SET(plane_dst->x_offset) + | PDMA_PS_OFFSET_Y_SET(plane_dst->y_offset); + ptr->PS[pdma_plane_dst].CLRKEY_LOW = PDMA_PS_CLRKEY_LOW_LIMIT_SET(plane_dst->colorkey_low); + ptr->PS[pdma_plane_dst].CLRKEY_HIGH = PDMA_PS_CLRKEY_HIGH_LIMIT_SET(plane_dst->colorkey_high); + ptr->PS[pdma_plane_dst].ORG = PDMA_PS_ORG_HIGHT_SET(plane_dst->height) + | PDMA_PS_ORG_WIDTH_SET(plane_dst->width); + ptr->PS[pdma_plane_dst].CTRL = PDMA_PS_CTRL_INB13_SWAP_SET(plane_dst->swap_byte3_byte1) + | PDMA_PS_CTRL_PACK_DIR_SET(plane_dst->byteorder) + | PDMA_PS_CTRL_BKGCL4CLR_SET(plane_dst->use_background_as_clear) + | PDMA_PS_CTRL_YCBCR_MODE_SET(plane_dst->ycbcr_mode) + | PDMA_PS_CTRL_BYPASS_SET(plane_dst->bypass_colorspace_conversion) + | ((plane_dst->flip << PDMA_PS_CTRL_HFLIP_SHIFT) + & (PDMA_PS_CTRL_VFLIP_MASK| PDMA_PS_CTRL_HFLIP_MASK)) + | PDMA_PS_CTRL_ROTATE_SET(plane_dst->rotate) + | PDMA_PS_CTRL_DECY_SET(plane_dst->y_dec) + | PDMA_PS_CTRL_DECX_SET(plane_dst->x_dec) + | PDMA_PS_CTRL_HW_BYTE_SWAP_SET(plane_dst->byte_swap) + | PDMA_PS_CTRL_FORMAT_SET(format); + } + + if(yuv2rgb != NULL) { + ptr->YUV2RGB_COEF0 = PDMA_YUV2RGB_COEF0_C0_SET(yuv2rgb->c0) + | PDMA_YUV2RGB_COEF0_UV_OFFSET_SET(yuv2rgb->uv_offset) + | PDMA_YUV2RGB_COEF0_Y_OFFSET_SET(yuv2rgb->y_offset); + ptr->YUV2RGB_COEF1 = PDMA_YUV2RGB_COEF1_C1_SET(yuv2rgb->c1) + | PDMA_YUV2RGB_COEF1_C4_SET(yuv2rgb->c4); + ptr->YUV2RGB_COEF2 = PDMA_YUV2RGB_COEF2_C2_SET(yuv2rgb->c2) + | PDMA_YUV2RGB_COEF2_C3_SET(yuv2rgb->c3); + } +} + +void pdma_config_output(PDMA_Type *ptr, pdma_output_config_t *config) +{ + uint32_t pitch; + uint32_t format; + + if (config->pitch == 0) { + pitch = display_get_pitch_length_in_byte(config->pixel_format, + config->width); + } else { + pitch = config->pitch; + } + format = pdma_pixel_format(config->pixel_format); + ptr->OUT_BUF = PDMA_OUT_BUF_ADDR_SET((uint32_t) config->buffer); + ptr->OUT_PITCH = PDMA_OUT_PITCH_BYTELEN_SET(pitch); + ptr->OUT_LRC = PDMA_OUT_LRC_X_SET(config->width) + | PDMA_OUT_LRC_Y_SET(config->height); + ptr->OUT_PS[0].ULC = PDMA_OUT_PS_ULC_X_SET(config->plane[0].x) + | PDMA_OUT_PS_ULC_Y_SET(config->plane[0].y); + ptr->OUT_PS[0].LRC = PDMA_OUT_PS_LRC_X_SET(config->plane[0].width) + | PDMA_OUT_PS_LRC_Y_SET(config->plane[0].height); + ptr->OUT_PS[1].ULC = PDMA_OUT_PS_ULC_X_SET(config->plane[1].x) + | PDMA_OUT_PS_ULC_Y_SET(config->plane[1].y); + ptr->OUT_PS[1].LRC = PDMA_OUT_PS_LRC_X_SET(config->plane[1].width) + | PDMA_OUT_PS_LRC_Y_SET(config->plane[1].height); + ptr->OUT_CTRL = PDMA_OUT_CTRL_DSTALPHA_SET(config->alphablend.dst_alpha) + | PDMA_OUT_CTRL_SRCALPHA_SET(config->alphablend.src_alpha) + | PDMA_OUT_CTRL_DSTALPHA_OP_SET(config->alphablend.dst_alpha_op) + | PDMA_OUT_CTRL_SRCALPHA_OP_SET(config->alphablend.src_alpha_op) + | PDMA_OUT_CTRL_ABLEND_MODE_SET(config->alphablend.mode) + | PDMA_OUT_CTRL_FORMAT_SET(format); + + ptr->RGB2YUV_COEF0 = PDMA_RGB2YUV_COEF0_ENABLE_SET(config->rgb2yuv_config.enable) + | PDMA_RGB2YUV_COEF0_YCBCR_MODE_SET(config->rgb2yuv_config.ycbcr_mode) + | PDMA_RGB2YUV_COEF0_C0_SET(config->rgb2yuv_config.c0) + | PDMA_RGB2YUV_COEF0_UV_OFFSET_SET(config->rgb2yuv_config.uv_offset) + | PDMA_RGB2YUV_COEF0_Y_OFFSET_SET(config->rgb2yuv_config.y_offset); + ptr->RGB2YUV_COEF1 = PDMA_RGB2YUV_COEF1_C1_SET(config->rgb2yuv_config.c1) + | PDMA_RGB2YUV_COEF1_C4_SET(config->rgb2yuv_config.c4); + ptr->RGB2YUV_COEF2 = PDMA_RGB2YUV_COEF2_C2_SET(config->rgb2yuv_config.c2) + | PDMA_RGB2YUV_COEF2_C3_SET(config->rgb2yuv_config.c3); + ptr->RGB2YUV_COEF3 = PDMA_RGB2YUV_COEF3_C6_SET(config->rgb2yuv_config.c6) + | PDMA_RGB2YUV_COEF3_C5_SET(config->rgb2yuv_config.c5); + ptr->RGB2YUV_COEF4 = PDMA_RGB2YUV_COEF4_C8_SET(config->rgb2yuv_config.c8) + | PDMA_RGB2YUV_COEF4_C7_SET(config->rgb2yuv_config.c7); +} + +#define PDMA_ERROR_STATUS_MASK (PDMA_STAT_AXI_0_WRITE_ERR_MASK \ + | PDMA_STAT_AXI_1_READ_ERR_MASK \ + | PDMA_STAT_AXI_0_READ_ERR_MASK) +#define PDMA_BUSY_STATUS_MASK (PDMA_STAT_BLOCKY_MASK \ + | PDMA_STAT_BLOCKX_MASK) + +hpm_stat_t pdma_check_status(PDMA_Type *ptr, uint32_t *status) +{ + uint32_t stat = ptr->STAT; + if (stat & PDMA_BUSY_STATUS_MASK) { + if (status) { + *status = stat; + } + return status_pdma_busy; + } + if (stat & PDMA_ERROR_STATUS_MASK) { + if (status) { + *status = stat; + } + ptr->STAT = PDMA_ERROR_STATUS_MASK; + return status_pdma_error; + } + if ((stat & PDMA_STAT_PDMA_DONE_MASK) == PDMA_STAT_PDMA_DONE_MASK) { + return status_pdma_done; + } + return status_pdma_idle; +} + +hpm_stat_t pdma_fill_color(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, + uint32_t width, uint32_t height, + uint32_t color, uint8_t alpha, + display_pixel_format_t format, + bool wait, uint32_t *status) +{ + pdma_config_t config; + pdma_plane_config_t plane_src; + pdma_plane_config_t plane_dst; + display_yuv2rgb_coef_t yuv2rgb_coef; + pdma_output_config_t output; + + if (((display_pixel_format_is_yuv_format(format)) && (width & 2)) + || !(width > 8 || height > 8)) { + return status_invalid_argument; + } + + pdma_get_default_config(ptr, &config, format); + pdma_get_default_plane_config(ptr, &plane_src, format); + pdma_get_default_plane_config(ptr, &plane_dst, format); + pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, format); + pdma_get_default_output_config(ptr, &output, format); + + config.enable_plane = pdma_plane_both; + if (width <= 16) { + config.block_size = pdma_blocksize_8x8; + } else { + config.block_size = pdma_blocksize_16x16; + } + pdma_init(ptr, &config); + + plane_src.buffer = dst; + plane_src.width = 1; + plane_src.height = 1; + plane_src.background = 0; + + plane_dst.buffer = dst; + plane_dst.width = 1; + plane_dst.height = 1; + plane_dst.background = (alpha << 24) | (color & ~(0xFF << 24)); + pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); + + output.buffer = dst; + output.plane[pdma_plane_dst].x = 0; + output.plane[pdma_plane_dst].y = 0; + output.plane[pdma_plane_dst].width = width; + output.plane[pdma_plane_dst].height = height; + output.pitch = display_get_pitch_length_in_byte(format, dst_width); + + output.alphablend.mode = display_alphablend_mode_clear; + + output.width = width; + output.height = height; + + pdma_config_output(ptr, &output); + pdma_start(ptr); + if (wait) { + hpm_stat_t stat; + do { + stat = pdma_check_status(ptr, status); + } while((stat != status_pdma_done) && (stat != status_pdma_error)); + pdma_stop(ptr); + return stat; + } + return status_success; +} + +hpm_stat_t pdma_flip_rotate(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, + uint32_t src, uint32_t src_width, uint32_t x, uint32_t y, + uint32_t width, uint32_t height, + pdma_flip_t flip, pdma_rotate_t rotate, uint8_t alpha, + display_pixel_format_t format, + bool wait, uint32_t *status) +{ + pdma_config_t config; + pdma_plane_config_t plane_src; + pdma_plane_config_t plane_dst; + display_yuv2rgb_coef_t yuv2rgb_coef; + pdma_output_config_t output; + + if ((width + x > dst_width) + /* YUV422 requires width to be 2-byte aligned */ + || ((display_pixel_format_is_yuv_format(format)) && (width & 2)) + || !(width > 8 || height > 8)) { + return status_invalid_argument; + } + + pdma_get_default_config(ptr, &config, format); + pdma_get_default_plane_config(ptr, &plane_src, format); + pdma_get_default_plane_config(ptr, &plane_dst, format); + pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, format); + pdma_get_default_output_config(ptr, &output, format); + + config.enable_plane = pdma_plane_both; + if (width <= 16) { + config.block_size = pdma_blocksize_8x8; + } else { + config.block_size = pdma_blocksize_16x16; + } + pdma_init(ptr, &config); + + plane_src.buffer = src; + plane_src.height = height; + plane_src.width = width; + plane_src.pitch = display_get_pitch_length_in_byte(format, src_width); + plane_src.flip = flip; + plane_src.rotate = rotate; + + plane_dst.buffer = src; + plane_dst.height = 1; + plane_dst.width = 1; + plane_dst.pitch = display_get_pitch_length_in_byte(format, dst_width); + plane_dst.flip = pdma_flip_none; + plane_dst.rotate = pdma_rotate_0_degree; + pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); + + output.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); + + output.alphablend.src_alpha = alpha; + output.alphablend.src_alpha_op = display_alpha_op_override; + output.alphablend.mode = display_alphablend_mode_src_over; + + output.plane[pdma_plane_src].x = 0; + output.plane[pdma_plane_src].y = 0; + output.pitch = display_get_pitch_length_in_byte(format, dst_width); + + if ((rotate == pdma_rotate_90_degree) + || (rotate == pdma_rotate_270_degree)) { + output.width = height; + output.height = width; + output.plane[pdma_plane_src].width = height; + output.plane[pdma_plane_src].height = width; + } else { + output.plane[pdma_plane_src].width = width; + output.plane[pdma_plane_src].height = height; + output.width = width; + output.height = height; + } + + pdma_config_output(ptr, &output); + pdma_start(ptr); + if (wait) { + hpm_stat_t stat; + do { + stat = pdma_check_status(ptr, status); + } while((stat != status_pdma_done) && (stat != status_pdma_error)); + pdma_stop(ptr); + return stat; + } + return status_success; +} + +hpm_stat_t pdma_blit(PDMA_Type *ptr, + uint32_t dst, uint32_t dst_width, + uint32_t src, uint32_t src_width, + uint32_t x, uint32_t y, uint32_t width, uint32_t height, + uint8_t alpha, + display_pixel_format_t format, + bool wait, uint32_t *status) +{ + pdma_config_t config; + pdma_plane_config_t plane_src; + pdma_plane_config_t plane_dst; + display_yuv2rgb_coef_t yuv2rgb_coef; + pdma_output_config_t output; + + if ((width + x > dst_width) + /* YUV422 requires width to be 2-byte aligned */ + || ((display_pixel_format_is_yuv_format(format)) && (width & 2)) + || !(width > 8 || height > 8)) { + return status_invalid_argument; + } + + pdma_get_default_config(ptr, &config, format); + pdma_get_default_plane_config(ptr, &plane_src, format); + pdma_get_default_plane_config(ptr, &plane_dst, format); + pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, format); + pdma_get_default_output_config(ptr, &output, format); + + config.enable_plane = pdma_plane_both; + if (width <= 16) { + config.block_size = pdma_blocksize_8x8; + } else { + config.block_size = pdma_blocksize_16x16; + } + pdma_init(ptr, &config); + + plane_src.buffer = src; + plane_src.width = width; + plane_src.height = height; + plane_src.pitch = display_get_pitch_length_in_byte(format, src_width); + plane_src.background = 0x00FFFFFF; + + plane_dst.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); + plane_dst.width = width; + plane_dst.height = height; + plane_dst.pitch = display_get_pitch_length_in_byte(format, dst_width); + pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); + + output.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); + + output.plane[pdma_plane_src].x = 0; + output.plane[pdma_plane_src].y = 0; + output.plane[pdma_plane_src].width = width; + output.plane[pdma_plane_src].height = height; + + output.plane[pdma_plane_dst].x = 0; + output.plane[pdma_plane_dst].y = 0; + output.plane[pdma_plane_dst].width = width; + output.plane[pdma_plane_dst].height = height; + + output.alphablend.src_alpha = alpha; + output.alphablend.src_alpha_op = display_alpha_op_override; + output.alphablend.mode = display_alphablend_mode_src_over; + + output.width = width; + output.height = height; + output.pitch = display_get_pitch_length_in_byte(format, dst_width); + + pdma_config_output(ptr, &output); + pdma_start(ptr); + if (wait) { + hpm_stat_t stat; + do { + stat = pdma_check_status(ptr, status); + } while((stat != status_pdma_done) && (stat != status_pdma_error)); + pdma_stop(ptr); + return stat; + } + return status_success; +} + +static void pdma_calculate_scale(uint32_t t, uint32_t target_t, + pdma_decimation_t *dec, uint32_t *scale) +{ + uint32_t tmp; + tmp = ((t << PDMA_SCALE_FRAC_BITS) / target_t) >> PDMA_SCALE_FRAC_BITS; + if (tmp >= 16) { + *dec = pdma_decimation_by_8; + *scale = 2; + return; + } + if (tmp >= 8) { + *dec = pdma_decimation_by_8; + } else if (tmp >= 4) { + *dec = pdma_decimation_by_4; + } else if (tmp >= 2) { + *dec = pdma_decimation_by_2; + } else { + *dec = pdma_decimation_by_1; + } + + *scale = (((t >> *dec) << PDMA_SCALE_FRAC_BITS) / target_t); + return; +} + +hpm_stat_t pdma_scale(PDMA_Type *ptr, + uint32_t dst, uint32_t dst_width, + uint32_t src, uint32_t src_width, + uint32_t x, uint32_t y, uint32_t width, uint32_t height, + uint32_t target_width, uint32_t target_height, + uint8_t alpha, + display_pixel_format_t format, + bool wait, uint32_t *status) +{ + uint32_t scale; + pdma_decimation_t dec; + + pdma_config_t config; + pdma_plane_config_t plane_src; + pdma_plane_config_t plane_dst; + display_yuv2rgb_coef_t yuv2rgb_coef; + pdma_output_config_t output; + + if ((width + x > dst_width) + /* YUV422 requires width to be 2-byte aligned */ + || ((display_pixel_format_is_yuv_format(format)) && (width & 2)) + || !(width > 8 || height > 8)) { + return status_invalid_argument; + } + + pdma_get_default_config(ptr, &config, format); + pdma_get_default_plane_config(ptr, &plane_src, format); + pdma_get_default_plane_config(ptr, &plane_dst, format); + pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, format); + pdma_get_default_output_config(ptr, &output, format); + + config.enable_plane = pdma_plane_both; + if (width <= 16) { + config.block_size = pdma_blocksize_8x8; + } else { + config.block_size = pdma_blocksize_16x16; + } + pdma_init(ptr, &config); + + plane_src.buffer = src; + plane_src.width = width; + plane_src.height = height; + plane_src.pitch = display_get_pitch_length_in_byte(format, src_width); + + pdma_calculate_scale(width, target_width, &dec, &scale); + plane_src.x_scale = scale; + plane_src.x_dec = dec, + pdma_calculate_scale(height, target_height, &dec, &scale); + plane_src.y_scale = scale; + plane_src.y_dec = dec, + plane_src.background = 0x00FFFFFF; + + plane_dst.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); + plane_dst.width = width; + plane_dst.height = height; + plane_dst.pitch = display_get_pitch_length_in_byte(format, dst_width); + pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); + + output.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); + + output.plane[pdma_plane_src].x = 0; + output.plane[pdma_plane_src].y = 0; + output.plane[pdma_plane_src].width = target_width; + output.plane[pdma_plane_src].height = target_height; + + output.plane[pdma_plane_dst].x = 0; + output.plane[pdma_plane_dst].y = 0; + output.plane[pdma_plane_dst].width = target_width; + output.plane[pdma_plane_dst].height = target_height; + + output.alphablend.src_alpha = alpha; + output.alphablend.src_alpha_op = display_alpha_op_override; + output.alphablend.mode = display_alphablend_mode_src_over; + + output.width = target_width; + output.height = target_height; + output.pitch = display_get_pitch_length_in_byte(format, dst_width); + + pdma_config_output(ptr, &output); + pdma_start(ptr); + if (wait) { + hpm_stat_t stat; + do { + stat = pdma_check_status(ptr, status); + } while((stat != status_pdma_done) && (stat != status_pdma_error)); + pdma_stop(ptr); + return stat; + } + return status_success; + +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c new file mode 100644 index 0000000000..7e5c002a86 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_pllctl_drv.h" + +#define PLLCTL_INT_PLL_MAX_FBDIV (2400U) +#define PLLCTL_INT_PLL_MIN_FBDIV (16U) + +#define PLLCTL_FRAC_PLL_MAX_FBDIV (240U) +#define PLLCTL_FRAC_PLL_MIN_FBDIV (20U) + +#define PLLCTL_PLL_MAX_REFDIV (63U) +#define PLLCTL_PLL_MIN_REFDIV (1U) + +#define PLLCTL_PLL_MAX_POSTDIV1 (7U) +#define PLLCTL_PLL_MIN_POSTDIV1 (1U) + +#define PLLCTL_FRAC_PLL_MIN_REF (10000000U) +#define PLLCTL_INT_PLL_MIN_REF (1000000U) + +hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) +{ + uint32_t min_ref; + + if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) + || (!div) + || (div > (PLLCTL_PLL_CFG0_REFDIV_MASK >> PLLCTL_PLL_CFG0_REFDIV_SHIFT))) { + return status_invalid_argument; + } + + if (ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK) { + min_ref = PLLCTL_INT_PLL_MIN_REF; + } else { + min_ref = PLLCTL_FRAC_PLL_MIN_REF; + } + + if ((PLLCTL_SOC_PLL_REFCLK_FREQ / div) < min_ref) { + return status_pllctl_out_of_range; + } + + if (PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0) != div) { + /* if div is different, it needs to be power down */ + pllctl_pll_powerdown(ptr, pll); + ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 & ~PLLCTL_PLL_CFG0_REFDIV_MASK) + | PLLCTL_PLL_CFG0_REFDIV_SET(div); + } + return status_success; +} + +hpm_stat_t pllctl_init_int_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, + uint32_t freq_in_hz) +{ + uint32_t freq, fbdiv, refdiv, postdiv; + if ((freq_in_hz < PLLCTL_PLL_VCO_FREQ_MIN) + || (freq_in_hz > PLLCTL_PLL_VCO_FREQ_MAX)) { + return status_invalid_argument; + } + + freq = freq_in_hz; + refdiv = PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0); + postdiv = PLLCTL_PLL_CFG0_POSTDIV1_GET(ptr->PLL[pll].CFG0); + fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); + if (fbdiv > PLLCTL_INT_PLL_MAX_FBDIV) { + /* current refdiv can't be used for the given frequency */ + refdiv--; + do { + fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); + if (fbdiv > PLLCTL_INT_PLL_MAX_FBDIV) { + refdiv--; + } else { + break; + } + } while (refdiv > PLLCTL_PLL_MIN_REFDIV); + } else if (fbdiv < PLLCTL_INT_PLL_MIN_FBDIV) { + /* current refdiv can't be used for the given frequency */ + refdiv++; + do { + fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); + if (fbdiv < PLLCTL_INT_PLL_MIN_FBDIV) { + refdiv++; + } else { + break; + } + } while (refdiv < PLLCTL_PLL_MAX_REFDIV); + } + + if ((refdiv > PLLCTL_PLL_MAX_REFDIV) + || (refdiv < PLLCTL_PLL_MIN_REFDIV) + || (fbdiv > PLLCTL_INT_PLL_MAX_FBDIV) + || (fbdiv < PLLCTL_INT_PLL_MIN_FBDIV) + || (((PLLCTL_SOC_PLL_REFCLK_FREQ / refdiv) < PLLCTL_INT_PLL_MIN_REF))) { + return status_pllctl_out_of_range; + } + + if (!(ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK)) { + /* it was at frac mode, then it needs to be power down */ + pllctl_pll_powerdown(ptr, pll); + ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_DSMPD_MASK; + } + + if (PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0) != refdiv) { + /* if refdiv is different, it needs to be power down */ + pllctl_pll_powerdown(ptr, pll); + ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 & ~PLLCTL_PLL_CFG0_REFDIV_MASK) + | PLLCTL_PLL_CFG0_REFDIV_SET(refdiv); + } + + ptr->PLL[pll].CFG2 = (ptr->PLL[pll].CFG2 & ~(PLLCTL_PLL_CFG2_FBDIV_INT_MASK)) | PLLCTL_PLL_CFG2_FBDIV_INT_SET(fbdiv); + + pllctl_pll_poweron(ptr, pll); + return status_success; +} + +hpm_stat_t pllctl_init_frac_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, + uint32_t freq_in_hz) +{ + uint32_t frac, refdiv, fbdiv, freq, postdiv; + double div; + if ((freq_in_hz < PLLCTL_PLL_VCO_FREQ_MIN) + || (freq_in_hz > PLLCTL_PLL_VCO_FREQ_MAX)) { + return status_invalid_argument; + } + + freq = freq_in_hz; + refdiv = PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0); + postdiv = PLLCTL_PLL_CFG0_POSTDIV1_GET(ptr->PLL[pll].CFG0); + fbdiv = (freq / postdiv) / (PLLCTL_SOC_PLL_REFCLK_FREQ / refdiv); + + if (fbdiv > PLLCTL_FRAC_PLL_MAX_FBDIV) { + /* current refdiv can't be used for the given frequency */ + refdiv--; + do { + fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); + if (fbdiv > PLLCTL_FRAC_PLL_MAX_FBDIV) { + refdiv--; + } else { + break; + } + } while (refdiv > PLLCTL_PLL_MIN_REFDIV); + } else if (fbdiv < PLLCTL_FRAC_PLL_MIN_FBDIV) { + /* current refdiv can't be used for the given frequency */ + refdiv++; + do { + fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); + if (fbdiv < PLLCTL_FRAC_PLL_MIN_FBDIV) { + refdiv++; + } else { + break; + } + } while (refdiv < PLLCTL_PLL_MAX_REFDIV); + } + + if ((refdiv > PLLCTL_PLL_MAX_REFDIV) + || (refdiv < PLLCTL_PLL_MIN_REFDIV) + || (fbdiv > PLLCTL_FRAC_PLL_MAX_FBDIV) + || (fbdiv < PLLCTL_FRAC_PLL_MIN_FBDIV) + || (((PLLCTL_SOC_PLL_REFCLK_FREQ / refdiv) < PLLCTL_FRAC_PLL_MIN_REF))) { + return status_pllctl_out_of_range; + } + + div = (double) freq / PLLCTL_SOC_PLL_REFCLK_FREQ * (refdiv * postdiv); + fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); + frac = (div - fbdiv) * (1 << 24); + + /* + * pll has to be powered down to configure frac mode + */ + pllctl_pll_powerdown(ptr, pll); + + ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 + & ~(PLLCTL_PLL_CFG0_REFDIV_MASK | PLLCTL_PLL_CFG0_DSMPD_MASK)) + | PLLCTL_PLL_CFG0_REFDIV_SET(refdiv); + + pllctl_pll_ss_disable(ptr, pll); + ptr->PLL[pll].FREQ = (ptr->PLL[pll].FREQ + & ~(PLLCTL_PLL_FREQ_FRAC_MASK | PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK)) + | PLLCTL_PLL_FREQ_FBDIV_FRAC_SET(fbdiv) | PLLCTL_PLL_FREQ_FRAC_SET(frac); + + pllctl_pll_poweron(ptr, pll); + return status_success; +} + +uint32_t pllctl_get_pll_freq_in_hz(PLLCTL_Type *ptr, uint8_t pll) +{ + uint32_t fbdiv, frac, refdiv, postdiv, refclk, freq; + if (ptr->PLL[pll].CFG1 & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) { + /* pll is powered down */ + return 0; + } + + refdiv = PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0); + postdiv = PLLCTL_PLL_CFG0_POSTDIV1_GET(ptr->PLL[pll].CFG0); + refclk = PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv); + + if (ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK) { + /* pll int mode */ + fbdiv = PLLCTL_PLL_CFG2_FBDIV_INT_GET(ptr->PLL[pll].CFG2); + freq = refclk * fbdiv; + } else { + /* pll frac mode */ + fbdiv = PLLCTL_PLL_FREQ_FBDIV_FRAC_GET(ptr->PLL[pll].FREQ); + frac = PLLCTL_PLL_FREQ_FRAC_GET(ptr->PLL[pll].FREQ); + freq = refclk * (fbdiv + ((double) frac / (1 << 24))); + } + return freq; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c new file mode 100644 index 0000000000..bb60f4694c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_pllctlv2_drv.h" + +#define PLLCTLV2_PLL_MFI_MIN (16U) +#define PLLCTLV2_PLL_MFI_MAX (42U) +#define PLLCTLV2_PLL_XTAL_FREQ (24000000UL) + +#define PLLCTLV2_PLL_FREQ_MIN (PLLCTLV2_PLL_MFI_MIN * PLLCTLV2_PLL_XTAL_FREQ) +#define PLLCTLV2_PLL_FREQ_MAX ((PLLCTLV2_PLL_MFI_MAX + 1U) * PLLCTLV2_PLL_XTAL_FREQ) + +hpm_stat_t pllctlv2_init_pll_with_freq(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t freq_in_hz) +{ + if ((ptr == NULL) || (freq_in_hz < PLLCTLV2_PLL_FREQ_MIN) || (freq_in_hz > PLLCTLV2_PLL_FREQ_MAX) || + (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { + return status_invalid_argument; + } + + uint32_t mfn = freq_in_hz % PLLCTLV2_PLL_XTAL_FREQ; + uint32_t mfi = freq_in_hz / PLLCTLV2_PLL_XTAL_FREQ; + + ptr->PLL[pll].MFI = mfi; + ptr->PLL[pll].MFN = mfn * 10UL; + + while (!pllctlv2_pll_is_stable(ptr, pll)) { + } + return status_success; +} + +void pllctlv2_enable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t step, uint32_t stop) +{ + /* + * NOTE: The spread spectrum related registers cannot be configured under below conditions: + * 1. PLL is enabled + * 2. spread spectrum is enabled + */ + if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { + + ptr->PLL[pll].CONFIG &= ~PLLCTLV2_PLL_CONFIG_SPREAD_MASK; + + ptr->PLL[pll].SS_STEP = step; + ptr->PLL[pll].SS_STOP = stop; + + ptr->PLL[pll].CONFIG |= PLLCTLV2_PLL_CONFIG_SPREAD_MASK; + } +} + +void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index, uint8_t div_value) +{ + if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { + ptr->PLL[pll].DIV[div_index] = + (ptr->PLL[pll].DIV[div_index] & PLLCTLV2_DIV_DIV_MASK) | PLLCTLV2_DIV_DIV_SET(div_value) | + PLLCTLV2_DIV_ENABLE_MASK; + } +} + +uint32_t pllctlv2_get_pll_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll) +{ + uint32_t freq = 0; + if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { + uint32_t mfi = PLLCTLV2_PLL_MFI_MFI_GET(ptr->PLL[pll].MFI); + uint32_t mfn = PLLCTLV2_PLL_MFN_MFN_GET(ptr->PLL[pll].MFN); + uint32_t mfd = PLLCTLV2_PLL_MFD_MFD_GET(ptr->PLL[pll].MFD); + freq = (uint32_t) (PLLCTLV2_PLL_XTAL_FREQ * (mfi + 1.0 * mfn / mfd)); + } + return freq; +} + +uint32_t pllctlv2_get_pll_postdiv_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index) +{ + uint32_t postdiv_freq = 0; + if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { + uint32_t postdiv = PLLCTLV2_DIV_DIV_GET(ptr->PLL[pll].DIV[div_index]); + uint32_t pll_freq = pllctlv2_get_pll_freq_in_hz(ptr, pll); + postdiv_freq = (uint32_t) (pll_freq / (1 + postdiv * 1.0 / 5)); + } + + return postdiv_freq; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c new file mode 100644 index 0000000000..1e2f41cc81 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "riscv/riscv_core.h" +#include "hpm_pmp_drv.h" +#include "hpm_csr_regs.h" + +uint32_t read_pmp_cfg(uint32_t idx) +{ + uint32_t pmp_cfg = 0; + switch (idx) { + case 0: + pmp_cfg = read_csr(CSR_PMPCFG0); + break; + case 1: + pmp_cfg = read_csr(CSR_PMPCFG1); + break; + case 2: + pmp_cfg = read_csr(CSR_PMPCFG2); + break; + case 3: + pmp_cfg = read_csr(CSR_PMPCFG3); + break; + default: + /* Do nothing */ + break; + } + return pmp_cfg; +} + +uint32_t read_pma_cfg(uint32_t idx) +{ + uint32_t pma_cfg = 0; + switch (idx) { + case 0: + pma_cfg = read_csr(CSR_PMACFG0); + break; + case 1: + pma_cfg = read_csr(CSR_PMACFG1); + break; + case 2: + pma_cfg = read_csr(CSR_PMACFG2); + break; + case 3: + pma_cfg = read_csr(CSR_PMACFG3); + break; + default: + /* Do nothing */ + break; + } + return pma_cfg; +} + +void write_pmp_cfg(uint32_t value, uint32_t idx) +{ + switch (idx) { + case 0: + write_csr(CSR_PMPCFG0, value); + break; + case 1: + write_csr(CSR_PMPCFG1, value); + break; + case 2: + write_csr(CSR_PMPCFG2, value); + break; + case 3: + write_csr(CSR_PMPCFG3, value); + break; + default: + /* Do nothing */ + break; + } +} + +void write_pma_cfg(uint32_t value, uint32_t idx) +{ + switch (idx) { + case 0: + write_csr(CSR_PMACFG0, value); + break; + case 1: + write_csr(CSR_PMACFG1, value); + break; + case 2: + write_csr(CSR_PMACFG2, value); + break; + case 3: + write_csr(CSR_PMACFG3, value); + break; + default: + /* Do nothing */ + break; + } +} + +void write_pmp_addr(uint32_t value, uint32_t idx) +{ + switch (idx) { + case 0: + write_csr(CSR_PMPADDR0, value); + break; + case 1: + write_csr(CSR_PMPADDR1, value); + break; + case 2: + write_csr(CSR_PMPADDR2, value); + break; + case 3: + write_csr(CSR_PMPADDR3, value); + break; + case 4: + write_csr(CSR_PMPADDR4, value); + break; + case 5: + write_csr(CSR_PMPADDR5, value); + break; + case 6: + write_csr(CSR_PMPADDR6, value); + break; + case 7: + write_csr(CSR_PMPADDR7, value); + break; + case 8: + write_csr(CSR_PMPADDR8, value); + break; + case 9: + write_csr(CSR_PMPADDR9, value); + break; + case 10: + write_csr(CSR_PMPADDR10, value); + break; + case 11: + write_csr(CSR_PMPADDR11, value); + break; + case 12: + write_csr(CSR_PMPADDR12, value); + break; + case 13: + write_csr(CSR_PMPADDR13, value); + break; + case 14: + write_csr(CSR_PMPADDR14, value); + break; + case 15: + write_csr(CSR_PMPADDR15, value); + break; + default: + /* Do nothing */ + break; + } +} + +void write_pma_addr(uint32_t value, uint32_t idx) +{ + switch (idx) { + case 0: + write_csr(CSR_PMAADDR0, value); + break; + case 1: + write_csr(CSR_PMAADDR1, value); + break; + case 2: + write_csr(CSR_PMAADDR2, value); + break; + case 3: + write_csr(CSR_PMAADDR3, value); + break; + case 4: + write_csr(CSR_PMAADDR4, value); + break; + case 5: + write_csr(CSR_PMAADDR5, value); + break; + case 6: + write_csr(CSR_PMAADDR6, value); + break; + case 7: + write_csr(CSR_PMAADDR7, value); + break; + case 8: + write_csr(CSR_PMAADDR8, value); + break; + case 9: + write_csr(CSR_PMAADDR9, value); + break; + case 10: + write_csr(CSR_PMAADDR10, value); + break; + case 11: + write_csr(CSR_PMAADDR11, value); + break; + case 12: + write_csr(CSR_PMAADDR12, value); + break; + case 13: + write_csr(CSR_PMAADDR13, value); + break; + case 14: + write_csr(CSR_PMAADDR14, value); + break; + case 15: + write_csr(CSR_PMAADDR15, value); + break; + default: + /* Do nothing */ + break; + } +} + +uint32_t read_pmp_addr(uint32_t idx) +{ + uint32_t ret_val = 0; + switch (idx) { + case 0: + ret_val = read_csr(CSR_PMPADDR0); + break; + case 1: + ret_val = read_csr(CSR_PMPADDR1); + break; + case 2: + ret_val = read_csr(CSR_PMPADDR2); + break; + case 3: + ret_val = read_csr(CSR_PMPADDR3); + break; + case 4: + ret_val = read_csr(CSR_PMPADDR4); + break; + case 5: + ret_val = read_csr(CSR_PMPADDR5); + break; + case 6: + ret_val = read_csr(CSR_PMPADDR6); + break; + case 7: + ret_val = read_csr(CSR_PMPADDR7); + break; + case 8: + ret_val = read_csr(CSR_PMPADDR8); + break; + case 9: + ret_val = read_csr(CSR_PMPADDR9); + break; + case 10: + ret_val = read_csr(CSR_PMPADDR10); + break; + case 11: + ret_val = read_csr(CSR_PMPADDR11); + break; + case 12: + ret_val = read_csr(CSR_PMPADDR12); + break; + case 13: + ret_val = read_csr(CSR_PMPADDR13); + break; + case 14: + ret_val = read_csr(CSR_PMPADDR14); + break; + case 15: + ret_val = read_csr(CSR_PMPADDR15); + break; + default: + /* Do nothing */ + break; + } + return ret_val; +} + +uint32_t read_pma_addr(uint32_t idx) +{ + uint32_t ret_val = 0; + switch (idx) { + case 0: + ret_val = read_csr(CSR_PMAADDR0); + break; + case 1: + ret_val = read_csr(CSR_PMAADDR1); + break; + case 2: + ret_val = read_csr(CSR_PMAADDR2); + break; + case 3: + ret_val = read_csr(CSR_PMAADDR3); + break; + case 4: + ret_val = read_csr(CSR_PMAADDR4); + break; + case 5: + ret_val = read_csr(CSR_PMAADDR5); + break; + case 6: + ret_val = read_csr(CSR_PMAADDR6); + break; + case 7: + ret_val = read_csr(CSR_PMAADDR7); + break; + case 8: + ret_val = read_csr(CSR_PMAADDR8); + break; + case 9: + ret_val = read_csr(CSR_PMAADDR9); + break; + case 10: + ret_val = read_csr(CSR_PMAADDR10); + break; + case 11: + ret_val = read_csr(CSR_PMAADDR11); + break; + case 12: + ret_val = read_csr(CSR_PMAADDR12); + break; + case 13: + ret_val = read_csr(CSR_PMAADDR13); + break; + case 14: + ret_val = read_csr(CSR_PMAADDR14); + break; + case 15: + ret_val = read_csr(CSR_PMAADDR15); + break; + default: + /* Do nothing */ + break; + } + return ret_val; +} + +hpm_stat_t pmp_config(const pmp_entry_t *entry, uint32_t num_of_entries) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF((entry == NULL) || (num_of_entries < 1U) || (num_of_entries > 15U)); + + for (uint32_t i = 0; i < num_of_entries; i++) { + uint32_t idx = i / 4; + uint32_t offset = (i * 8) & 0x1F; + + uint32_t pmp_cfg = read_pmp_cfg(idx); + pmp_cfg &= ~(0xFFUL << offset); + pmp_cfg |= ((uint32_t) entry->pmp_cfg.val) << offset; + uint32_t pma_cfg = read_pma_cfg(idx); + pma_cfg &= ~(0xFFUL << offset); + pma_cfg |= ((uint32_t) entry->pma_cfg.val) << offset; + + write_pmp_addr(entry->pmp_addr, i); + write_pma_addr(entry->pma_addr, i); + + write_pma_cfg(pma_cfg, idx); + write_pmp_cfg(pmp_cfg, idx); + + ++entry; + } + fencei(); + + status = status_success; + + } while (false); + + return status; +} + +void pmp_disable(void) +{ + /* Disable caches */ + fencei(); + uint32_t mcache_ctl = read_csr(CSR_MCACHE_CTL); + write_csr(CSR_MCACHE_CTL, 0x0); + fencei(); + write_csr(CSR_PMACFG0, 0); + write_csr(CSR_PMACFG1, 0); + write_csr(CSR_PMACFG2, 0); + write_csr(CSR_PMACFG3, 0); + write_csr(CSR_PMPCFG0, 0); + write_csr(CSR_PMPCFG1, 0); + write_csr(CSR_PMPCFG2, 0); + write_csr(CSR_PMPCFG3, 0); + + write_csr(CSR_PMAADDR0, 0); + write_csr(CSR_PMAADDR1, 0); + write_csr(CSR_PMAADDR2, 0); + write_csr(CSR_PMAADDR3, 0); + write_csr(CSR_PMAADDR4, 0); + write_csr(CSR_PMAADDR5, 0); + write_csr(CSR_PMAADDR6, 0); + write_csr(CSR_PMAADDR7, 0); + write_csr(CSR_PMAADDR8, 0); + write_csr(CSR_PMAADDR9, 0); + write_csr(CSR_PMAADDR10, 0); + write_csr(CSR_PMAADDR11, 0); + write_csr(CSR_PMAADDR12, 0); + write_csr(CSR_PMAADDR13, 0); + write_csr(CSR_PMAADDR14, 0); + write_csr(CSR_PMAADDR15, 0); + fencei(); + write_csr(CSR_MCACHE_CTL, mcache_ctl); + fencei(); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c new file mode 100644 index 0000000000..7ca8226907 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_soc_feature.h" +#include "hpm_ptpc_drv.h" + +#define PTPC_SS_INCR_UINT_AT_BIN_MODE_IN_PS (446U) + +void ptpc_get_default_config(PTPC_Type *ptr, ptpc_config_t *config) +{ + config->capture_trigger = ptpc_capture_trigger_none; + config->ns_rollover_mode = ptpc_ns_counter_rollover_digital; + config->capture_keep = true; + config->coarse_increment = false; + config->src_frequency = 0; +} + +hpm_stat_t ptpc_init(PTPC_Type *ptr, uint8_t index, ptpc_config_t *config) +{ + uint8_t ss_incr; + if (!config || (index > PTPC_SOC_TIMER_MAX_COUNT) || !config->src_frequency) { + return status_invalid_argument; + } + + if (config->ns_rollover_mode == ptpc_ns_counter_rollover_digital) { + ss_incr = 1000000000 / config->src_frequency; + } else { + ss_incr = 1000000000 / config->src_frequency * 1000 / PTPC_SS_INCR_UINT_AT_BIN_MODE_IN_PS; + } + if (!ss_incr) { + return status_invalid_argument; + } + ptpc_disable_timer(ptr, index); + ptr->PTPC[index].CTRL0 = PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(config->ns_rollover_mode) + | PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(config->capture_keep) + | PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(config->coarse_increment) + | (config->capture_trigger & + ((PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK + | PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) + << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT); + ptpc_set_ns_counter_step(ptr, index, ss_incr); + ptpc_enable_timer(ptr, index); + return status_success; +} + +hpm_stat_t ptpc_set_timer_output(PTPC_Type *ptr, uint8_t can_index, bool use_ptpc1) +{ + if (can_index > CAN_SOC_MAX_COUNT) { + return status_invalid_argument; + } + ptr->TIME_SEL = (ptr->TIME_SEL & ~(1 << can_index)) | (use_ptpc1 ? (1 << can_index) : 0); + return status_success; +} + +hpm_stat_t ptpc_set_ns_update(PTPC_Type *ptr, uint8_t index, uint32_t ns, ptpc_counting_mode mode) +{ + if ((PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(ptr->PTPC[index].CTRL0) == ptpc_ns_counter_rollover_digital) + && (ns > PTPC_MAX_NS_COUNTER)) { + return status_invalid_argument; + } + ptr->PTPC[index].TS_UPDTL = PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(ns) | PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(mode); + return status_success; +} + +hpm_stat_t ptpc_update_timer(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode) +{ + if (status_success != ptpc_set_ns_update(ptr, index, ns, mode)) { + return status_invalid_argument; + } + ptpc_set_second_update(ptr, index, sec); + ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK; + return status_success; +} + +void ptpc_init_timer(PTPC_Type *ptr, uint8_t index) +{ + ptpc_set_second_update(ptr, index, 0); + ptpc_set_ns_update(ptr, index, 0, ptpc_counting_increment); + ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_INIT_TIMER_MASK; +} + +hpm_stat_t ptpc_init_timer_with_initial(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode) +{ + if (status_success != ptpc_set_ns_update(ptr, index, ns, mode)) { + return status_invalid_argument; + } + ptpc_set_second_update(ptr, index, sec); + ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_INIT_TIMER_MASK; + return status_success; +} + +hpm_stat_t ptpc_set_pps(PTPC_Type *ptr, uint8_t index, uint8_t p) +{ + if (p > 15) { + return status_invalid_argument; + } else if (p > 0) { + if (PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(ptr->PTPC[index].CTRL0) == ptpc_ns_counter_rollover_digital) { + if (p == 15) { + /* At digital mode, it can only generate interrupt at 16.384 KHz maximum */ + return status_invalid_argument; + } + } else { + if (p == 1) { + /* At binary mode, it can only generate interrupt at 2 Hz minimum, when p > 0 */ + return status_invalid_argument; + } + p--; + } + } + ptr->PTPC[index].PPS_CTRL = PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(p); + return status_success; +} + + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c new file mode 100644 index 0000000000..91373418cd --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_soc_feature.h" +#include "hpm_pwm_drv.h" + +hpm_stat_t pwm_load_cmp_shadow_on_match(PWM_Type *pwm_x, + uint8_t index, + pwm_cmp_config_t *config) +{ + if (config->mode != pwm_cmp_mode_output_compare) { + return status_invalid_argument; + } + pwm_config_cmp(pwm_x, index, config); + pwm_issue_shadow_register_lock_event(pwm_x); + pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_CMPSHDWSEL_MASK)) | PWM_GCR_CMPSHDWSEL_SET(index)); + return status_success; +} + +void pwm_get_captured_count(PWM_Type *pwm_x, uint32_t *buf, pwm_counter_type_t counter, uint8_t start_index, uint8_t num) +{ + uint32_t i; + if (counter == pwm_counter_type_capture_falling_edge) { + for (i = start_index; i < num; i++) { + *buf = pwm_x->CAPNEG[i]; + } + } else { + for (i = start_index; i < num; i++) { + *buf = pwm_x->CAPPOS[i]; + } + } +} + +void pwm_get_default_cmp_config(PWM_Type *pwm_x, pwm_cmp_config_t *config) +{ + config->mode = pwm_cmp_mode_output_compare; + config->update_trigger = pwm_shadow_register_update_on_modify; + config->enable_ex_cmp = false; + config->cmp = 0; + config->ex_cmp = 0; + config->half_clock_cmp = 0; + config->jitter_cmp = 0; +} + +void pwm_get_default_output_channel_config(PWM_Type *pwm_x, pwm_output_channel_t *config) +{ + config->cmp_start_index = 0; + config->cmp_end_index = 0; + config->invert_output = false; +} + +void pwm_get_default_pwm_config(PWM_Type *pwm_x, pwm_config_t *config) +{ + config->enable_output = false; + config->update_trigger = pwm_shadow_register_update_on_modify; + config->fault_mode = pwm_fault_mode_force_output_highz; + config->fault_recovery_trigger = pwm_fault_recovery_on_fault_clear; + config->force_source = pwm_force_source_software; + config->dead_zone_in_half_cycle = 0; +} + +void pwm_get_default_pwm_pair_config(PWM_Type *pwm_x, pwm_pair_config_t *config) +{ + pwm_get_default_pwm_config(pwm_x, &config->pwm[0]); + pwm_get_default_pwm_config(pwm_x, &config->pwm[1]); +} + +hpm_stat_t pwm_setup_waveform_in_pair(PWM_Type *pwm_x, uint8_t pwm_index, + pwm_pair_config_t *pwm_pair_config, uint8_t cmp_start_index, + pwm_cmp_config_t *cmp, uint8_t cmp_num) +{ + uint8_t i; + pwm_output_channel_t ch_config; + + if ((pwm_index > PWM_SOC_PWM_MAX_COUNT) + || !cmp_num + || (cmp_start_index > PWM_SOC_CMP_MAX_COUNT) + || (cmp_start_index + cmp_num > PWM_SOC_CMP_MAX_COUNT) + || ((pwm_index > (PWM_SOC_PWM_MAX_COUNT - 1)) + || (pwm_index & 0x1))) { + return status_invalid_argument; + } + + pwm_x->PWMCFG[pwm_index] &= ~PWM_PWMCFG_OEN_MASK; + pwm_x->PWMCFG[pwm_index + 1] &= ~PWM_PWMCFG_OEN_MASK; + + for (i = 0; i < cmp_num; i++) { + pwm_config_cmp(pwm_x, cmp_start_index + i, &cmp[i]); + } + ch_config.cmp_start_index = cmp_start_index; + ch_config.cmp_end_index = cmp_start_index + cmp_num - 1; + ch_config.invert_output = pwm_pair_config->pwm[0].invert_output; + pwm_config_output_channel(pwm_x, pwm_index, &ch_config); + + ch_config.invert_output = pwm_pair_config->pwm[1].invert_output; + pwm_config_output_channel(pwm_x, pwm_index + 1, &ch_config); + + pwm_config_pwm(pwm_x, pwm_index, &pwm_pair_config->pwm[0], true); + pwm_config_pwm(pwm_x, pwm_index + 1, &pwm_pair_config->pwm[1], true); + + return status_success; +} + +hpm_stat_t pwm_setup_waveform(PWM_Type *pwm_x, + uint8_t pwm_index, pwm_config_t *pwm_config, + uint8_t cmp_start_index, pwm_cmp_config_t *cmp, uint8_t cmp_num) +{ + uint8_t i; + pwm_output_channel_t ch_config; + if (!cmp_num + || (cmp_start_index > PWM_SOC_CMP_MAX_COUNT) + || (cmp_start_index + cmp_num > PWM_SOC_CMP_MAX_COUNT)) { + return status_invalid_argument; + } + + for (i = 0; i < cmp_num; i++) { + pwm_config_cmp(pwm_x, cmp_start_index + i, &cmp[i]); + } + ch_config.cmp_start_index = cmp_start_index; + ch_config.cmp_end_index = cmp_start_index + cmp_num - 1; + ch_config.invert_output = pwm_config->invert_output; + pwm_config_output_channel(pwm_x, pwm_index, &ch_config); + if (pwm_index < PWM_SOC_PWM_MAX_COUNT) { + pwm_config_pwm(pwm_x, pwm_index, pwm_config, false); + } + return status_success; +} + +hpm_stat_t pwm_update_raw_cmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp) +{ + pwm_shadow_register_unlock(pwm_x); + pwm_cmp_update_cmp_value(pwm_x, cmp_index, target_cmp, 0); + return status_success; +} + +hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, + uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2) +{ + uint32_t reload = PWM_RLD_RLD_GET(pwm_x->RLD); + if (!target_cmp1) { + target_cmp1 = reload + 1; + } + if (!target_cmp2) { + target_cmp2 = reload + 1; + } + pwm_shadow_register_unlock(pwm_x); + pwm_cmp_update_cmp_value(pwm_x, cmp1_index, target_cmp1, 0); + pwm_cmp_update_cmp_value(pwm_x, cmp2_index, target_cmp2, 0); + return status_success; +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c new file mode 100644 index 0000000000..72c3da50de --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_rng_drv.h" + +hpm_stat_t rng_run_selftest(RNG_Type *ptr) +{ + uint32_t status; + + ptr->CMD |= RNG_CMD_SLFCHK_MASK; + do { + status = ptr->STA; + } while (!(status & (RNG_STA_FUNCERR_MASK | RNG_STA_SCDN_MASK))); + + if ((status & (RNG_STA_SCPF_MASK | RNG_STA_FUNCERR_MASK))) { + return status; + } + + return status_success; +} + +hpm_stat_t rng_feed_rand_to_sdp(RNG_Type *ptr) +{ + uint32_t i = 0; + uint32_t status; + uint32_t fifo_level; + hpm_stat_t stat = status_success; + + for (i = 0; i < ARRAY_SIZE(ptr->R2SK); i++) { + status = ptr->STA; + if (status & RNG_STA_FUNCERR_MASK) { + stat = status_fail; + break; + } + + do { + fifo_level = (ptr->STA & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT; + } while (!fifo_level); + + __asm volatile ("" : : "r" (ptr->R2SK[i])); + } + return stat; +} + +static hpm_stat_t rng_rand(RNG_Type *ptr, void *buf, uint32_t count_in_byte, bool wait) +{ + uint32_t i; + uint32_t status; + volatile uint32_t fifo_level; + hpm_stat_t stat = status_success; + + if (count_in_byte < 4) { + return status_invalid_argument; + } + + for (i = 0; i < (count_in_byte / 4); i++) { + status = ptr->STA; + if (status & RNG_STA_FUNCERR_MASK) { + stat = status_fail; + break; + } + + do { + fifo_level = (ptr->STA & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT; + } while (!fifo_level && wait); + + if (fifo_level) { + *(uint32_t *)(buf + i * sizeof(uint32_t)) = ptr->FO2B; + } else { + stat = status_rng_not_available; + break; + } + } + + return stat; +} + +hpm_stat_t rng_rand_wait(RNG_Type *ptr, void *buf, uint32_t count_in_byte) +{ + return rng_rand(ptr, buf, count_in_byte, true); +} + +hpm_stat_t rng_rand_no_wait(RNG_Type *ptr, void *buf, uint32_t count_in_byte) +{ + return rng_rand(ptr, buf, count_in_byte, false); +} + +hpm_stat_t rng_init(RNG_Type *ptr) +{ + hpm_stat_t stat = status_success; + + /* clear interrupt and error */ + ptr->CMD |= RNG_CMD_CLRERR_MASK; + + /* generating seed */ + ptr->CMD |= RNG_CMD_GENSD_MASK; + while (!(ptr->STA & RNG_STA_FSDDN_MASK)) { + if (ptr->STA & RNG_STA_FUNCERR_MASK) { + stat = status_fail; + break; + } + } + if (stat != status_success) { + return stat; + } + + /* enable auto seeding */ + ptr->CTRL |= RNG_CTRL_AUTRSD_MASK; + + return stat; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c new file mode 100644 index 0000000000..ab71612036 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_rtc_drv.h" + + +#define RTC_ALARM_TYPE_ONE_SHOT (0U) +#define RTC_ALARM_TYPE_PERIODIC (1U) + + +hpm_stat_t rtc_config_time(RTC_Type *base, time_t time) +{ + base->SECOND = (uint32_t)time; + return status_success; +} + +time_t rtc_get_time(RTC_Type *base) +{ + time_t time = (time_t)base->SECOND; + return time; +} + +hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + do{ + if ((config == NULL) || (config->index > 1U) || (config->type > RTC_ALARM_TYPE_PERIODIC)) { + break; + } + uint32_t alarm_inc = 0; + uint32_t current_sec = base->SECOND; + uint32_t alarm = current_sec + config->period; + if (config->type == RTC_ALARM_TYPE_ONE_SHOT) { + alarm_inc = 0; + } + else { + alarm_inc = config->period; + } + if (alarm < current_sec) { + break; + } + + if (config->index == 0U) { + base->ALARM0 = alarm; + base->ALARM0_INC = alarm_inc; + } + else { + base->ALARM1 = alarm; + base->ALARM1_INC = alarm_inc; + } + }while(false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c new file mode 100644 index 0000000000..34ea15f765 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c @@ -0,0 +1,888 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_sdp_drv.h" +#include "hpm_soc_feature.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * AES Key source definition + */ +#define AES_KEY_SRC_SDP_START_IDX 0U +#define AES128_KEY_SRC_SDP_END_IDX 0xFU +#define AES256_KEY_SRC_SDP_END_IDX 0x7U +#define AES_KEY_SRC_KEYMAN_START_IDX 0x20U +#define AES128_KEY_SRC_KEYMAN_END_IDX 0x2FU +#define AES256_KEY_SRC_KEYMAN_END_IDX 0x2FU +#define AES_KEY_SRC_UNIQUE_KEY_START_IDX 0x3EU +#define AES_KEY_SRC_OTP_KEY_START_IDX 0x3FU + +#define AES_256_KEY_SIZE_IN_WORDS (8U) +#define AES_256_KEY_SIZE_IN_BYTES (32U) + +#define CRC32_DIGEST_SIZE_IN_BYTES (4U) +#define SHA1_DIGEST_SIZE_IN_BYTES (20U) +#define SHA256_DIGEST_SIZE_IN_BYTES (32U) + +#define AES_CTR_BLOCK_UNIT (16U) + +typedef enum { + sdp_state_hash_init, + sdp_state_hash_update, +} sdp_hash_alg_state_t; + +#define AES_BLOCK_SIZE (16U) +#define HASH_BLOCK_SIZE (64U) +#define HASH_DIGEST_SIZE_MAX (32) + +typedef struct { + union { + uint32_t words[HASH_BLOCK_SIZE / sizeof(uint32_t)]; + uint8_t bytes[HASH_BLOCK_SIZE]; + } block; + uint32_t blk_size; + uint32_t full_msg_size; + uint32_t running_hash[HASH_DIGEST_SIZE_MAX / sizeof(uint32_t)]; + sdp_hash_alg_t alg; + sdp_hash_alg_state_t state; + bool hash_init; + bool hash_finish; +} sdp_hash_internal_ctx_t; + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +static void sdp_hash_internal_engine_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx); + +static hpm_stat_t sdp_hash_process_message(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size); + +static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size); + +static hpm_stat_t sdp_hash_finalize(SDP_Type *base, sdp_hash_ctx_t *hash_ctx); + +static inline void sdp_clear_error_status(SDP_Type *base) +{ + base->STA = 0xFFFFFFFFUL; +} + +static void sdp_increment_bn(uint8_t *big_num, uint32_t bytes); + +static void uint32_to_be(uint8_t *dst, uint32_t len, uint32_t num); + +static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *mac, + uint32_t mac_len); + +static void aes_ccm_format_b0(uint8_t *block, const uint8_t *iv, uint32_t iv_len, uint32_t mac_len, uint32_t aad_len, + uint32_t input_len); + +static void aes_ccm_format_ctr0(uint8_t *ctr, const uint8_t *iv, uint8_t iv_len); + +static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t len); + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +hpm_stat_t sdp_wait_done(SDP_Type *base) +{ + hpm_stat_t status; + uint32_t sdp_sta; + do { + sdp_sta = base->STA; + if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRSET_MASK)) { + status = status_sdp_error_setup; + } + else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRPKT_MASK)) { + status = status_sdp_error_packet; + } + else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRSRC_MASK)) { + status = status_sdp_error_src; + } + else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRDST_MASK)) { + status = status_sdp_error_dst; + } + else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRHAS_MASK)) { + status = status_sdp_error_hash; + } + else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRCHAIN_MASK)) { + status = status_sdp_error_chain; + } + else { + status = status_success; + } + } while (IS_HPM_BITMASK_CLR(sdp_sta, SDP_STA_PKTCNT0_MASK)); + + return status; +} + +hpm_stat_t sdp_init(SDP_Type *base) +{ + hpm_stat_t status = status_invalid_argument; + if (base != NULL) { + base->SDPCR &= ~(SDP_SDPCR_CLKGAT_MASK | SDP_SDPCR_SFTRST_MASK); + + status = status_success; + } + + return status; +} + + +hpm_stat_t sdp_deinit(SDP_Type *base) +{ + hpm_stat_t status = status_invalid_argument; + if (base != NULL) { + base->SDPCR |= SDP_SDPCR_CLKGAT_MASK; + status = status_success; + } + return status; +} + +hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t key_bits, + uint32_t key_idx) +{ + union { + uint32_t words[AES_256_KEY_SIZE_IN_WORDS]; + uint8_t bytes[AES_256_KEY_SIZE_IN_BYTES]; + } aes_key; + + assert((base != NULL) && (aes_ctx != NULL) && (key_bits <= sdp_aes_keybits_256)); + + hpm_stat_t status = status_invalid_argument; + do { + //TODO: AES_KEY index validity check + + if (IS_HPM_BITMASK_SET(base->SDPCR, SDP_SDPCR_CIPDIS_MASK)) { + status = status_sdp_no_crypto_support; + break; + } + + HPM_BREAK_IF((key_bits != sdp_aes_keybits_128) && (key_bits != sdp_aes_keybits_256)); + + aes_ctx->key_bits = key_bits; + + uint32_t key128_idx = key_idx; + if (key_bits == sdp_aes_keybits_256) { + if (key_idx <= AES256_KEY_SRC_SDP_END_IDX) { + (void) memcpy(aes_key.bytes, key, 32); + key128_idx = key_idx * 2U; + uint32_t idx = 0; + for (uint32_t i = 0; i < 2; i++) { + base->KEYADDR = SDP_KEYADDR_INDEX_SET(key128_idx + i); + for (uint32_t j = 0; j < 4; j++) { + base->KEYDAT = aes_key.words[idx++]; + } + } + } + else if ((key_idx >= AES_KEY_SRC_KEYMAN_START_IDX) && (key_idx <= AES256_KEY_SRC_KEYMAN_END_IDX)) { + key128_idx = (key_idx - AES_KEY_SRC_KEYMAN_START_IDX) * 2U + AES_KEY_SRC_KEYMAN_START_IDX; + } + } + else { + if (key_idx <= AES128_KEY_SRC_SDP_END_IDX) { + (void) memcpy(aes_key.bytes, key, 16); + base->KEYADDR = SDP_KEYADDR_INDEX_SET(key_idx); + for (uint32_t j = 0; j < 4; j++) { + base->KEYDAT = aes_key.words[j]; + } + } + } + + aes_ctx->key_idx = key128_idx; + aes_ctx->key_bits = key_bits; + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, + uint8_t *out) +{ + assert((base != NULL) && (aes_ctx != NULL)); + + hpm_stat_t status; + + base->SDPCR = SDP_SDPCR_CIPHEN_MASK; +#if SDP_REGISTER_DESCRIPTOR_COUNT + base->SDPCR |= HPM_BITSMASK(1, 8); + base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK; + base->PKTSRC = (uint32_t) in; + base->PKTDST = (uint32_t) out; + base->PKTBUF = len; +#else + sdp_pkt_struct_t *pkt_desc = &aes_ctx->sdp_pkt; + pkt_desc->next_cmd = NULL; + pkt_desc->pkt_ctrl.PKT_CTRL = SDP_PKT_CTRL_DERSEMA_MASK; + pkt_desc->src_addr = (uint32_t) in; + pkt_desc->dst_addr = (uint32_t) out; + pkt_desc->buf_size = len; + +#endif + sdp_clear_error_status(base); + + if (aes_ctx->key_bits == sdp_aes_keybits_128) { + base->MODCTRL = SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) + | SDP_MODCTRL_AESDIR_SET(op); + } + else { + base->MODCTRL = SDP_MODCTRL_AESALG_SET(1) + | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) + | SDP_MODCTRL_AESDIR_SET(op); + } + +#if SDP_REGISTER_DESCRIPTOR_COUNT + base->CMDPTR = 0; +#else + base->CMDPTR = (uint32_t) pkt_desc; +#endif + base->PKTCNT = 1U; + + status = sdp_wait_done(base); + + return status; +} + +hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, + const uint8_t iv[16], const uint8_t *input, uint8_t *output) +{ + assert((base != NULL) && (aes_ctx != NULL)); + assert((op <= sdp_aes_op_decrypt) && (input != NULL) && (output != NULL)); + + hpm_stat_t status; + + base->SDPCR = SDP_SDPCR_CIPHEN_MASK; +#if SDP_REGISTER_DESCRIPTOR_COUNT + base->SDPCR |= HPM_BITSMASK(1, 8); + base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKT_CTRL_CIPHIV_MASK; + base->PKTSRC = (uint32_t) input; + base->PKTDST = (uint32_t) output; + base->PKTBUF = length; +#else + sdp_pkt_struct_t *pkt_desc = &aes_ctx->sdp_pkt; + pkt_desc->next_cmd = NULL; + pkt_desc->pkt_ctrl.PKT_CTRL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKT_CTRL_CIPHIV_MASK; + pkt_desc->src_addr = (uint32_t) input; + pkt_desc->dst_addr = (uint32_t) output; + pkt_desc->buf_size = length; +#endif + + sdp_clear_error_status(base); + + if (aes_ctx->key_bits == sdp_aes_keybits_128) { + base->MODCTRL = SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) + | SDP_MODCTRL_AESDIR_SET(op) + | SDP_MODCTRL_AESMOD_SET(1); + } else { + base->MODCTRL = SDP_MODCTRL_AESALG_SET(1) + | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) + | SDP_MODCTRL_AESDIR_SET(op) + | SDP_MODCTRL_AESMOD_SET(1); + } + + // Set IV, copy the IV to the context first in case the IV address is not 32-bit aligned + uint32_t iv_32[4]; + (void) memcpy(iv_32, iv, 16); + for (uint32_t i = 0; i < 4; i++) { + base->CIPHIV[i] = iv_32[i]; + } + (void) memset(iv_32, 0, sizeof(iv_32)); +#if SDP_REGISTER_DESCRIPTOR_COUNT + base->CMDPTR = 0; +#else + base->CMDPTR = (uint32_t) pkt_desc; +#endif + base->PKTCNT = 1U; + + status = sdp_wait_done(base); + + return status; +} + +/* + * In the AES-CTR algorithm, all the numbers are represented in big-endian format, namely, LSB is in last byte + */ +static void sdp_increment_bn(uint8_t *big_num, uint32_t bytes) +{ + for (uint32_t i = bytes - 1; i > 0u; i--) { + big_num[i]++; + if (big_num[i] != 0) { + break; + } + } +} + +hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_counter, uint8_t *input, + uint8_t *output, uint32_t length) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF( + (base == NULL) || (aes_ctx == NULL) || (nonce_counter == NULL) || (input == NULL) || (output == NULL)); + + uint32_t calc_len; + uint8_t *cipher_nonce = (uint8_t*)&aes_ctx->buf3; + while (length > 0) { + calc_len = (length < 16U) ? length : 16U; + status = sdp_aes_crypt_ecb(base, aes_ctx, sdp_aes_op_encrypt, 16, nonce_counter, cipher_nonce); + HPM_BREAK_IF(status != status_success); + uint8_t tmp; + for (uint32_t i = 0; i < calc_len; i++) { + tmp = *input++; + *output++ = (uint8_t) (tmp ^ cipher_nonce[i]); + } + + length -= calc_len; + /* Increment counter, (128-bit big-endian */ + sdp_increment_bn(nonce_counter, AES_CTR_BLOCK_UNIT); + } + + } while (false); + + return status; +} + +static void uint32_to_be(uint8_t *dst, uint32_t len, uint32_t num) +{ + uint32_t i = 0; + + (void) memset(dst, 0, len); + + while (num > 0) { + dst[len - 1 - i] = num & 0xFF; + num >>= 8; + i++; + } +} + +/* + * See section A2.1 in NIST Special Publication 800-38C + * q + n = 15 + * n - nonce / iv + * byte0 = FLAG + * bit[2:0] - (q-1) + * bit[5:3] - (t-2/2 + * bit[6] - adata + * bit[7] - reserved + * + * byte (1... 15-q) nonce + * byte (16-q...15) input length + * + */ +static void aes_ccm_format_b0(uint8_t *block, const uint8_t *iv, uint32_t iv_len, uint32_t mac_len, uint32_t aad_len, + uint32_t input_len) +{ + uint8_t q = 15U - iv_len; + block[0] = 0; + block[0] |= (aad_len > 0) ? (1U << 6) : 0U; + block[0] |= ((mac_len - 2U) / 2U) << 3; + block[0] |= q - 1U; + + (void) memcpy(block + 1U, iv, iv_len); + + uint32_to_be(block + 1U + iv_len, q, input_len); + +} + +/* + * See section A2.3 in NIST Special Publication 800-38C + * q + n = 15 + * n - nonce/iv + * byte 0 = FLAG + * bit[2:0] : (q - 1) + * bit[5:3] : 0 + * bit[7:6] : 0 + * + * byte (1...15-q) nonce + * byte (16-q ...15) i + */ +static void aes_ccm_format_ctr0(uint8_t *ctr, const uint8_t *iv, uint8_t iv_len) +{ + uint8_t q = 15U - iv_len; + (void) memset(ctr, 0, 16); + ctr[0] |= q - 1U; + (void) memcpy(ctr + 1U, iv, iv_len); +} + + +static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF((base == NULL) || (aes_ctx == NULL) || (input == NULL) || (output == NULL) || (tag == NULL)); + + + /*See section A.1 in NIST Special Publication 800-38C */ + + /* Valid Tlen is 4, 6, 8, 10, 12, 14, 16 */ + HPM_BREAK_IF((tag_len % 2U != 0U) || (tag_len / 2U < 2) || (tag_len / 2U > 8)); + /* Valid Nonce length is 7, 8, 9, 10, 11, 12, 13 */ + HPM_BREAK_IF((iv_len < 7U) || (iv_len > 13U)); + + /* Note, this API supports maximum 2^32 - 1 bytes of data, so the valid q value should be 2, 3, or 4 */ + uint8_t *b = (uint8_t *) &aes_ctx->buf0; + uint8_t *y = (uint8_t *) &aes_ctx->buf1; + uint8_t *ctr = (uint8_t *) &aes_ctx->buf2; + uint32_t i = 0; + + /* Format B0 */ + aes_ccm_format_b0(b, iv, iv_len, tag_len, aad_len, input_len); + + /* Calculate Y0 */ + sdp_aes_crypt_ecb(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y); + + + /* + * Follow A2.2.2 in NIST Special Publication 800-38C, only supports up to 2^32 bytes*/ + if (aad_len > 0U) { + uint32_t calc_len = 0U; + const uint8_t *aad_src = aad; + uint32_t remaining_len = aad_len; + (void) memset(b, 0, 16); + /* format B1 + * Follow A2.2.2 in NIST Special Publication 800-38C, only supports up to 2^32 bytes + */ + if (aad_len < ((1UL << 16) - (1U << 8))) { + uint32_to_be(b, 2, aad_len); + calc_len = MIN(remaining_len, 14U); + (void) memcpy(&b[2], aad_src, calc_len); + } + else { + b[0] = 0xFFU; + b[1] = 0xFEU; + uint32_to_be(&b[6], 4, calc_len); + calc_len = 10U; + (void) memcpy(&b[2], aad_src, calc_len); + } + aad_src += calc_len; + remaining_len -= calc_len; + /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ + ++i; + sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); + + while (remaining_len > 0U) { + calc_len = MIN(remaining_len, 16U); + (void) memcpy(b, aad_src, calc_len); + if (calc_len < 16U) { + (void) memset(&b[calc_len], 0, 16U - calc_len); + } + aad_src += calc_len; + remaining_len -= calc_len; + /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ + ++i; + sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); + } + } + + aes_ccm_format_ctr0(ctr, iv, iv_len); + i = 0; + /* Encryption/Decryption starts from CTR1 */ + sdp_increment_bn(ctr, 16); + ++i; + /* Continue CBC-MAC calculation + Encryption/Decryption */ + uint32_t remaining_len = input_len; + uint8_t *src = (uint8_t *) input; + uint8_t *dst = output; + while (remaining_len > 0U) { + uint32_t calc_len = MIN(remaining_len, 16U); + if (op == sdp_aes_op_encrypt) { + (void) memcpy(b, src, calc_len); + if (calc_len < 16U) { + (void) memset(&b[calc_len], 0, 16U - calc_len); + } + /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ + sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); + } + sdp_aes_crypt_ctr(base, aes_ctx, ctr, src, dst, calc_len); + if (op == sdp_aes_op_decrypt) { + (void) memcpy(b, dst, calc_len); + if (calc_len < 16U) { + (void) memset(&b[calc_len], 0, 16U - calc_len); + } + /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ + sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); + } + src += calc_len; + dst += calc_len; + remaining_len -= calc_len; + ++i; + } + + /* Get CTR0 */ + aes_ccm_format_ctr0(ctr, iv, iv_len); + /* Get MAC */ + sdp_aes_crypt_ctr(base, aes_ctx, ctr, y, b, 16); + /* Copy mac to the destination */ + (void) memcpy(tag, b, tag_len); + + /* Wipe-out temporary data */ + (void) memset(b, 0, 16U); + (void) memset(y, 0, 16); + (void) memset(ctr, 0, 16); + + status = status_success; + + } while (false); + return status; +} + +hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, + uint8_t *output, uint8_t *tag, uint32_t tag_len) +{ + return aes_ccm_auth_crypt(base, aes_ctx, sdp_aes_op_encrypt, input_len, iv, iv_len, aad, aad_len, input, output, + tag, tag_len); +} + + +static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t len) +{ + uint8_t result = 0U; + + const uint8_t *dst_8 = (const uint8_t *) dst; + const uint8_t *src_8 = (const uint8_t *) src; + + while (len-- > 0U) { + result |= *dst_8 ^ *src_8; + ++dst_8; + ++src_8; + + } + return result; +} + +hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, + uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, + uint8_t *output, const uint8_t *tag, uint32_t tag_len) +{ + hpm_stat_t status; + + do { + + uint32_t calc_mac[4]; + + status = aes_ccm_auth_crypt(base, aes_ctx, sdp_aes_op_decrypt, input_len, iv, iv_len, aad, aad_len, input, + output, (uint8_t *) &calc_mac, tag_len); + HPM_BREAK_IF(status != status_success); + if (sdp_constant_time_cmp(calc_mac, tag, tag_len) != 0U) { + status = status_sdp_error_invalid_mac; + } + else { + status = status_success; + } + + } while (false); + + return status; +} + +hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) +{ + hpm_stat_t status = status_invalid_argument; + do { + if (IS_HPM_BITMASK_SET(base->SDPCR, SDP_SDPCR_HASDIS_MASK)) { + status = status_sdp_no_hash_support; + break; + } + + // Initialize the SDP HASH context + sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; + (void) memset(ctx_internal, 0, sizeof(*ctx_internal)); + ctx_internal->alg = alg; + ctx_internal->blk_size = 0; + ctx_internal->state = sdp_state_hash_init; + ctx_internal->full_msg_size = 0; + + status = status_success; + + } while (false); + + return status; +} + +static void sdp_hash_internal_engine_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx) +{ + sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; + + ctx_internal->hash_init = true; + ctx_internal->hash_finish = false; +} + + +static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size) +{ + sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &ctx->internal; + sdp_pkt_struct_t *pkt_desc = (sdp_pkt_struct_t *) &ctx->sdp_pkt; + + pkt_desc->next_cmd = NULL; + uint32_t pkt_ctrl = SDP_PKT_CTRL_DERSEMA_MASK; + if (ctx_internal->hash_init) { + pkt_ctrl |= SDP_PKT_CTRL_HASHINIT_MASK; + ctx_internal->hash_init = false; + } + if (ctx_internal->hash_finish) { + pkt_ctrl |= SDP_PKT_CTRL_HASHFINISH_MASK; + ctx_internal->hash_finish = false; + } + + base->SDPCR = SDP_SDPCR_HASHEN_MASK; +#if SDP_REGISTER_DESCRIPTOR_COUNT + base->SDPCR |= HPM_BITSMASK(1, 8); + base->NPKTPTR = 0UL; + base->PKTCTL = pkt_ctrl; + base->PKTSRC = (uint32_t) msg; + base->PKTDST = (uint32_t) 0; + base->PKTBUF = msg_size; +#else + pkt_desc->pkt_ctrl.PKT_CTRL = pkt_ctrl; + pkt_desc->src_addr = (uint32_t) msg; + pkt_desc->dst_addr = 0; + pkt_desc->buf_size = msg_size; + pkt_desc->reserved[0] = 0; + pkt_desc->reserved[1] = 0; + pkt_desc->reserved[2] = 0; +#endif + + sdp_clear_error_status(base); + base->MODCTRL = SDP_MODCTRL_HASALG_SET(ctx_internal->alg); +#if SDP_REGISTER_DESCRIPTOR_COUNT + base->CMDPTR = 0; +#else + base->CMDPTR = (uint32_t) pkt_desc; +#endif + base->PKTCNT = 1; + + hpm_stat_t status = sdp_wait_done(base); + + return status; +} + +static hpm_stat_t sdp_hash_process_message(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size) +{ + hpm_stat_t status = status_invalid_argument; + + sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &ctx->internal; + // If there is partially filled internal buffer, fill it to full block + if (ctx_internal->blk_size > 0U) { + uint32_t size_to_copy = HASH_BLOCK_SIZE - ctx_internal->blk_size; + (void) memcpy(&ctx_internal->block.bytes[ctx_internal->blk_size], msg, size_to_copy); + msg += size_to_copy; + msg_size -= size_to_copy; + + /* process the full internal block */ + status = sdp_hash_internal_update(base, ctx, &ctx_internal->block.bytes[0], HASH_BLOCK_SIZE); + if (status != status_success) { + return status; + } + } + + // Process all full blocks in message + uint32_t full_blk_size = (msg_size >> 6) << 6; + if (full_blk_size > 0U) { + status = sdp_hash_internal_update(base, ctx, msg, full_blk_size); + if (status != status_success) { + return status; + } + msg += full_blk_size; + msg_size -= full_blk_size; + } + + (void) memcpy(&ctx_internal->block.bytes[0], msg, msg_size); + ctx_internal->blk_size = msg_size; + + return status; +} + +hpm_stat_t sdp_hash_update(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) +{ + assert((base != NULL) && (hash_ctx != NULL) && (data != NULL)); + hpm_stat_t status = status_invalid_argument; + do { + if (length == 0) { + status = status_success; + break; + } + + sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; + uint32_t block_size = HASH_BLOCK_SIZE; + ctx_internal->full_msg_size += length; + /* If the data is still less than HASH_BLOCK_SIZE, keep them only in the buffer */ + if ((ctx_internal->blk_size + length) <= block_size) { + (void) memcpy(&ctx_internal->block.bytes[0] + ctx_internal->blk_size, data, length); + ctx_internal->blk_size += length; + status = status_success; + break; + } + else { + if (ctx_internal->state != sdp_state_hash_update) { + sdp_hash_internal_engine_init(base, hash_ctx); + ctx_internal->state = sdp_state_hash_update; + } + } + + /* Process input data */ + status = sdp_hash_process_message(base, hash_ctx, data, length); + } while (false); + + return status; +} + +static hpm_stat_t sdp_hash_finalize(SDP_Type *base, sdp_hash_ctx_t *hash_ctx) +{ + sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; + hpm_stat_t status; + ctx_internal->hash_finish = true; + + status = sdp_hash_internal_update(base, hash_ctx, &ctx_internal->block.bytes[0], ctx_internal->blk_size); + + return status; +} + +hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *digest) +{ + assert((base != NULL) && (hash_ctx != NULL) && (digest != NULL)); + + hpm_stat_t status = status_invalid_argument; + do { + sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; + if (ctx_internal->state == sdp_state_hash_init) { + sdp_hash_internal_engine_init(base, hash_ctx); + } + status = sdp_hash_finalize(base, hash_ctx); + HPM_BREAK_IF(status != status_success); + + uint32_t copy_bytes = 0; + uint32_t digest_words = 0; + switch (ctx_internal->alg) { + case sdp_hash_alg_crc32: + copy_bytes = CRC32_DIGEST_SIZE_IN_BYTES; + ctx_internal->running_hash[0] = base->HASWRD[0]; + break; + case sdp_hash_alg_sha1: + copy_bytes = SHA1_DIGEST_SIZE_IN_BYTES; + digest_words = copy_bytes / sizeof(uint32_t); + for (uint32_t i = 0; i < digest_words; i++) { + ctx_internal->running_hash[i] = base->HASWRD[i]; + } + break; + case sdp_hash_alg_sha256: + copy_bytes = SHA256_DIGEST_SIZE_IN_BYTES; + digest_words = copy_bytes / sizeof(uint32_t); + for (uint32_t i = 0; i < digest_words; i++) { + ctx_internal->running_hash[i] = base->HASWRD[i]; + } + break; + default: + // Never reach here + break; + } + (void) memcpy(digest, ctx_internal->running_hash, copy_bytes); + } while (false); + + return status; +} + +hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) +{ + hpm_stat_t status = status_invalid_argument; + + if (length == 0) { + status = status_success; + return status; + } + + base->SDPCR = SDP_SDPCR_MCPEN_MASK; +#if SDP_REGISTER_DESCRIPTOR_COUNT + base->SDPCR |= HPM_BITSMASK(1, 8); + base->NPKTPTR = 0; + base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKTCTL_PKTTAG_SET(1); + base->PKTSRC = (uint32_t) src; + base->PKTDST = (uint32_t) dst; + base->PKTBUF = length; +#else + sdp_pkt_struct_t *pkt_desc = &dma_ctx->sdp_pkt; + pkt_desc->next_cmd = NULL; + pkt_desc->pkt_ctrl.PKT_CTRL = SDP_PKT_CTRL_DERSEMA_MASK; + pkt_desc->src_addr = (uint32_t) src; + pkt_desc->dst_addr = (uint32_t) dst; + pkt_desc->buf_size = length; +#endif + + sdp_clear_error_status(base); + + base->MODCTRL = 0; +#if SDP_REGISTER_DESCRIPTOR_COUNT + base->CMDPTR = 0; +#else + base->CMDPTR = (uint32_t) pkt_desc; +#endif + base->PKTCNT = 1; + + status = sdp_wait_done(base); + + return status; +} + +hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t pattern, uint32_t length) +{ + hpm_stat_t status; + + uint32_t pattern_32 = + (pattern) | ((uint32_t) pattern << 8) | ((uint32_t) pattern << 16) | ((uint32_t) pattern << 24); + + base->SDPCR = SDP_SDPCR_CONFEN_MASK; + #if SDP_REGISTER_DESCRIPTOR_COUNT + base->SDPCR |= HPM_BITSMASK(1, 8); + base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK; + base->PKTSRC = (uint32_t) pattern_32; + base->PKTDST = (uint32_t) dst; + base->PKTBUF = length; +#else + sdp_pkt_struct_t *pkt_desc = &sdp_ctx->sdp_pkt; + pkt_desc->next_cmd = NULL; + pkt_desc->pkt_ctrl.PKT_CTRL = SDP_PKT_CTRL_DERSEMA_MASK; + pkt_desc->src_addr = pattern_32; + pkt_desc->dst_addr = (uint32_t) dst; + pkt_desc->buf_size = length; +#endif + + sdp_clear_error_status(base); + base->MODCTRL = 0; +#if SDP_REGISTER_DESCRIPTOR_COUNT + base->CMDPTR = 0; +#else + base->CMDPTR = (uint32_t) pkt_desc; +#endif + base->PKTCNT = 1; + + status = sdp_wait_done(base); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c new file mode 100644 index 0000000000..df3520c794 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c @@ -0,0 +1,1097 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_sdxc_drv.h" + + + + +#define SDXC_DMA_MAX_XFER_LEN_26BIT ((1UL << 26) - 4U) +#define SDXC_DMA_MAX_XFER_LEN_16BIT ((1UL << 16) - 4U) + +#define SDXC_SYS_DMA_ALIGN_LEN (4U) + +enum { + sdxc_cmd_only = (1UL << 0), + sdxc_cmd_and_tx_data = (1UL << 1), + sdxc_cmd_and_rx_data = (1UL << 2), + sdxc_data_with_auto_cmd12 = (1UL << 3), + sdxc_data_with_auto_cmd23 = (1UL << 4), + sdxc_boot_data = (1UL << 5), + sdxc_boot_data_continuous = (1UL << 6), +}; + +static const uint32_t s_sdxc_boot_dummy = 0; + + +static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, uint32_t xfer_flags, + uint32_t block_size, uint32_t block_cnt, uint32_t *new_flags); + +static uint32_t sdxc_read_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words); + +static hpm_stat_t sdxc_read_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data); + +static uint32_t sdxc_write_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words); + +static hpm_stat_t sdxc_write_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data); + +static hpm_stat_t sdxc_transfer_data_blocking(SDXC_Type *base, sdxc_data_t *data, bool enable_dma); + +static hpm_stat_t sdxc_tuning_error_recovery(SDXC_Type *base); + +static bool sdxc_is_bus_idle(SDXC_Type *base); + +static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, uint32_t xfer_flags, + uint32_t block_size, uint32_t block_cnt, uint32_t *new_flags) +{ + uint32_t flags = base->CMD_XFER & ~(SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | + SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK | + SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | + SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK); + if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CMD_INHIBIT_MASK)) { + return status_sdxc_busy; + } else { + if (IS_HPM_BITMASK_SET(xfer_flags, sdxc_boot_data_continuous)) { + + base->PROT_CTRL &= ~SDXC_PROT_CTRL_STOP_BG_REQ_MASK; + base->PROT_CTRL |= SDXC_PROT_CTRL_CONTINUE_REQ_MASK; + return status_success; + } + + if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_DAT_INHIBIT_MASK)) { + return status_sdxc_busy; + } + + if (block_cnt > SDXC_BLK_ATTR_BLOCK_CNT_GET(SDXC_BLK_ATTR_BLOCK_CNT_MASK)) { + return status_invalid_argument; + } + + if (IS_HPM_BITMASK_SET(xfer_flags, sdxc_cmd_and_rx_data)) { + flags |= SDXC_CMD_XFER_DATA_XFER_DIR_MASK; + } + if (block_cnt > 1U) { + flags |= SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK; + if (IS_HPM_BITMASK_SET(xfer_flags, sdxc_data_with_auto_cmd12)) { + flags |= SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(sdxc_auto_cmd12_enabled); + } + } + + if (IS_HPM_BITMASK_SET(xfer_flags, sdxc_data_with_auto_cmd23)) { + flags |= SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(sdxc_auto_cmd23_enabled); + } + + if (IS_HPM_BITMASK_CLR(xfer_flags, sdxc_boot_data)) { + base->BLK_ATTR = block_size; + base->SDMASA = block_cnt; + } else { + flags |= SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK; + } + } + + *new_flags = flags; + + return status_success; +} + + +hpm_stat_t sdxc_receive_cmd_response(SDXC_Type *base, sdxc_command_t *cmd) +{ + hpm_stat_t status = status_success; + + if (cmd->resp_type != sdxc_dev_resp_none) { + + cmd->response[0] = base->RESP[0]; + if (cmd->resp_type == sdxc_dev_resp_r2) { + + /* R3-R2-R1-R0 (lowest 8 bits are invalid bits) has the same format as R2 format in SD spec + * after removing internal CRC7 and end bit + */ + cmd->response[0] = (base->RESP[0] << 8); + cmd->response[1] = (base->RESP[1] << 8) | (base->RESP[0] >> 24); + cmd->response[2] = (base->RESP[2] << 8) | (base->RESP[1] >> 24); + cmd->response[3] = (base->RESP[3] << 8) | (base->RESP[2] >> 24); + } + + if (SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(base->CMD_XFER) == sdxc_auto_cmd12_enabled) { + cmd->auto_cmd_resp = base->RESP[3]; + } + } + + /* check response flag */ + if ((cmd->resp_error_flags != 0U) && + ((cmd->resp_type == sdxc_dev_resp_r1) || (cmd->resp_type == sdxc_dev_resp_r1b) || + (cmd->resp_type == sdxc_dev_resp_r6) || (cmd->resp_type == sdxc_dev_resp_r5))) { + if ((cmd->resp_error_flags & cmd->response[0]) != 0U) { + status = status_sdxc_send_cmd_failed; + } + } + + return status; +} + +static uint32_t sdxc_read_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words) +{ + uint32_t total_words = 0U; + + if (IS_HPM_BITMASK_CLR(base->CMD_XFER, SDXC_CMD_XFER_DMA_ENABLE_MASK)) { + if (data->block_size % sizeof(uint32_t) != 0U) { + data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); + } + total_words = (data->block_size * data->block_cnt) / sizeof(uint32_t); + + uint32_t i = 0; + while (i < total_words) { + data->rx_data[transferred_words++] = sdxc_read_data(base); + i++; + } + } + return transferred_words; +} + +static hpm_stat_t sdxc_read_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data) +{ + uint32_t total_words = 0; + uint32_t transferred_words = 0; + uint32_t interrupt_status = 0; + hpm_stat_t status = status_success; + + if (data->block_size % sizeof(uint32_t) != 0U) { + data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); + } + + total_words = (data->block_size * data->block_cnt) / sizeof(uint32_t); + + uint32_t status_flags = SDXC_INT_STAT_BUF_RD_READY_MASK | SDXC_STS_DATA_ERR | SDXC_INT_STAT_TUNING_ERR_MASK; + while ((status == status_success) && (transferred_words < total_words)) { + while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)) { + interrupt_status = sdxc_get_interrupt_status(base); + } + + if ((data->data_type == (uint8_t) sdxc_xfer_data_tuning) && + IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_BUF_RD_READY_MASK)) { + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); + return status_success; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_TUNING_ERR_MASK)) { + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_TUNING_ERR_MASK); + status = status_sdxc_tuning_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_STS_DATA_ERR)) { + if (!data->enable_ignore_error) { + status = status_fail; + } + sdxc_clear_interrupt_status(base, SDXC_STS_DATA_ERR); + } else { + // Do nothing + } + + if (status == status_success) { + transferred_words = sdxc_read_data_port(base, data, transferred_words); + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); + interrupt_status = 0; + } + } + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_XFER_COMPLETE_MASK); + + return status; +} + +static uint32_t sdxc_write_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words) +{ + uint32_t total_words = 0; + + if (!IS_HPM_BITMASK_SET(base->CMD_XFER, SDXC_CMD_XFER_DMA_ENABLE_MASK)) { + if (data->block_size % sizeof(uint32_t) != 0U) { + data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); + } + + total_words = (data->block_size * data->block_cnt) / sizeof(uint32_t); + + uint32_t i = 0; + while (i < total_words) { + sdxc_write_data(base, data->tx_data[transferred_words++]); + ++i; + } + } + + return transferred_words; +} + +static hpm_stat_t sdxc_write_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data) +{ + uint32_t total_words = 0; + uint32_t transferred_words = 0; + uint32_t interrupt_status = 0; + + hpm_stat_t status = status_success; + + if (data->block_size % sizeof(uint32_t) != 0U) { + data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); + } + + total_words = (data->block_size * data->block_cnt) / sizeof(uint32_t); + + uint32_t status_flags = SDXC_INT_STAT_BUF_WR_READY_MASK | SDXC_STS_DATA_ERR | SDXC_INT_STAT_TUNING_ERR_MASK; + while ((status == status_success) && (transferred_words < total_words)) { + + while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)) { + interrupt_status = sdxc_get_interrupt_status(base); + } + + if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_TUNING_ERR_MASK)) { + return status_sdxc_tuning_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_STS_DATA_ERR)) { + if (!data->enable_ignore_error) { + status = status_fail; + } + sdxc_clear_interrupt_status(base, SDXC_STS_DATA_ERR); + } else { + // DO nothing + } + + if (status == status_success) { + transferred_words = sdxc_write_data_port(base, data, transferred_words); + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_WR_READY_MASK); + interrupt_status = 0; + } + } + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_XFER_COMPLETE_MASK | SDXC_STS_DATA_ERR); + + return status; +} + +static bool sdxc_is_bus_idle(SDXC_Type *base) +{ + uint32_t busy_mask = SDXC_PSTATE_CMD_INHIBIT_MASK | SDXC_PSTATE_DAT_LINE_ACTIVE_MASK | SDXC_PSTATE_DAT_INHIBIT_MASK; + + return IS_HPM_BITMASK_CLR(base->PSTATE, busy_mask); +} + +hpm_stat_t sdxc_get_capabilities(SDXC_Type *base, sdxc_capabilities_t *capabilities) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF((base == NULL) || (capabilities == NULL)); + + capabilities->capabilities1.U = base->CAPABILITIES1; + capabilities->capabilities2.U = base->CAPABILITIES2; + capabilities->curr_capabilities1.U = base->CURR_CAPABILITIES1; + capabilities->curr_capabilities2.U = base->CURR_CAPABILITIES2; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t sdxc_send_command(SDXC_Type *base, sdxc_command_t *cmd) +{ + sdxc_clear_interrupt_status(base, ~0U); + + uint32_t cmd_xfer = base->CMD_XFER; + uint32_t flags = cmd->cmd_flags; + + int32_t wait_cnt = 1000000L; + + while (!sdxc_is_bus_idle(base) && (wait_cnt > 0U)) { + wait_cnt--; + } + + if (wait_cnt == 0) { + return status_timeout; + } + + if (IS_HPM_BITMASK_CLR(base->PSTATE, SDXC_PSTATE_CMD_INHIBIT_MASK) && (cmd->cmd_type != sdxc_cmd_type_empty)) { + if ((cmd->resp_type == sdxc_dev_resp_r1) || (cmd->resp_type == sdxc_dev_resp_r5) || + (cmd->resp_type == sdxc_dev_resp_r6) || (cmd->resp_type == sdxc_dev_resp_r7)) { + flags |= SDXC_CMD_RESP_LEN_48 | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK | + SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK; + } else if ((cmd->resp_type == sdxc_dev_resp_r1b) || (cmd->resp_type == sdxc_dev_resp_r5b)) { + flags |= SDXC_CMD_RESP_LEN_48B | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK | + SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK; + } else if (cmd->resp_type == sdxc_dev_resp_r2) { + flags |= SDXC_CMD_RESP_LEN_136 | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK; + } else if ((cmd->resp_type == sdxc_dev_resp_r3) || (cmd->resp_type == sdxc_dev_resp_r4)) { + flags |= SDXC_CMD_RESP_LEN_48; + } else { + // do nothing + } + if (IS_HPM_BITMASK_SET(flags, SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK)) { + flags |= SDXC_CMD_XFER_RESP_INT_DISABLE_MASK; + } + } + + switch(cmd->cmd_type) { + case sdxc_cmd_type_abort_cmd: + flags |= SDXC_CMD_TYPE_ABORT; + break; + case sdxc_cmd_type_suspend_cmd: + flags |= SDXC_CMD_TYPE_SUSPEND; + break; + case sdxc_cmd_tye_resume_cmd: + flags |= SDXC_CMD_TYPE_RESUME; + break; + default: + flags |= SDXC_CMD_TYPE_NORMAL; + break; + } + + cmd_xfer &= ~(SDXC_CMD_XFER_CMD_INDEX_MASK | SDXC_CMD_XFER_CMD_TYPE_MASK | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK + | SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | + SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | + SDXC_CMD_XFER_DATA_XFER_DIR_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK | SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | + SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK); + + cmd_xfer |= SDXC_CMD_XFER_CMD_INDEX_SET(cmd->cmd_index) | + ((flags & (SDXC_CMD_XFER_CMD_TYPE_MASK | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK + | SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | + SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK | + SDXC_CMD_XFER_DATA_XFER_DIR_MASK | SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | + SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_MASK | + SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK))); + + base->CMD_ARG = cmd->cmd_argument; + base->CMD_XFER = cmd_xfer; + + return status_success; +} + + +hpm_stat_t sdxc_parse_interrupt_status(SDXC_Type *base) +{ + uint32_t interrupt_status = sdxc_get_interrupt_status(base); + hpm_stat_t status = status_success; + if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_STS_ERROR)) { + if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_TOUT_ERR_MASK)) { + status = status_sdxc_cmd_timeout_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_CRC_ERR_MASK)) { + status = status_sdxc_cmd_crc_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_END_BIT_ERR_MASK)) { + status = status_sdxc_cmd_end_bit_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_IDX_ERR_MASK)) { + status = status_sdxc_cmd_index_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_TOUT_ERR_MASK)) { + status = status_sdxc_data_timeout_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_CRC_ERR_MASK)) { + status = status_sdxc_data_crc_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_END_BIT_ERR_MASK)) { + status = status_sdxc_data_end_bit_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_AUTO_CMD_ERR_MASK)) { + uint32_t auto_cmd_err_mask = base->AC_HOST_CTRL & 0xFFFFUL; + if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK)) { + status = status_sdxc_autocmd_cmd12_not_exec; + } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK)) { + status = status_sdxc_autocmd_cmd_timeout_error; + } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK)) { + status = status_sdxc_autocmd_cmd_crc_error; + } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK)) { + status = status_sdxc_autocmd_cmd_index_error; + } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK)) { + status = status_sdxc_autocmd_end_bit_error; + } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK)) { + status = status_sdxc_autocmd_cmd_response_error; + } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK)) { + status = status_sdxc_autocmd_cmd_not_issued_auto_cmd12; + } else { + status = status_sdxc_auto_cmd_error; + } + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_ADMA_ERR_MASK)) { + status = status_sdxc_adma_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_TUNING_ERR_MASK)) { + status = status_sdxc_tuning_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_RESP_ERR_MASK)) { + status = status_sdxc_response_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_BOOT_ACK_ERR_MASK)) { + status = status_sdxc_boot_ack_error; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CARD_REMOVAL_MASK)) { + status = status_sdxc_card_removed; + } else { + status = status_sdxc_error; + } + } else { + status = status_success; + } + return status; +} + +hpm_stat_t sdxc_wait_cmd_done(SDXC_Type *base, sdxc_command_t *cmd, bool polling_cmd_done) +{ + hpm_stat_t status = status_success; + uint32_t interrupt_status = 0U; + + if (polling_cmd_done) { + while (!IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_COMPLETE_MASK)) { + interrupt_status = sdxc_get_interrupt_status(base); + status = sdxc_parse_interrupt_status(base); + HPM_BREAK_IF(status != status_success); + } + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_CMD_COMPLETE_MASK); + + if (status == status_success) { + status = sdxc_receive_cmd_response(base, cmd); + } + } + + return status; +} + + +static hpm_stat_t sdxc_transfer_data_blocking(SDXC_Type *base, sdxc_data_t *data, bool enable_dma) +{ + hpm_stat_t status = status_success; + + uint32_t interrupt_status = 0; + + if (enable_dma) { + uint32_t status_flags = SDXC_INT_STAT_XFER_COMPLETE_MASK | SDXC_STS_ERROR; + while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)) { + interrupt_status = sdxc_get_interrupt_status(base); + if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DMA_INTERRUPT_MASK)) { + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_DMA_INTERRUPT_MASK); + if (SDXC_PROT_CTRL_DMA_SEL_GET(base->PROT_CTRL) == (uint32_t) sdxc_dmasel_sdma) { + base->ADMA_SYS_ADDR += data->block_size; + } + } + } + + if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_TUNING_ERR_MASK)) { + status = status_sdxc_transfer_data_failed; + } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_STS_DATA_ERR | SDXC_INT_STAT_ADMA_ERR_MASK)) { + if ((!data->enable_ignore_error) || + IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_TOUT_ERR_MASK)) { + status = status_sdxc_transfer_data_failed; + } + } else { + // Do nothing + } + + if ((data->data_type == (uint8_t) sdxc_xfer_data_boot_continuous) && (status == status_success)) { + *(data->rx_data) = s_sdxc_boot_dummy; + } + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_DMA_INTERRUPT_MASK | SDXC_INT_STAT_TUNING_ERR_MASK); + + } else { + if (data->rx_data != NULL) { + status = sdxc_read_by_data_port_blocking(base, data); + if (status != status_success) { + return status; + } + } else { + status = sdxc_write_by_data_port_blocking(base, data); + if (status != status_success) { + return status; + } + } + } + + return status; +} + + +void sdxc_init(SDXC_Type *base, const sdxc_config_t *config) +{ + sdxc_reset(base, sdxc_reset_all, 0x10000U); + + uint32_t prot_ctrl = base->PROT_CTRL; + + prot_ctrl &= ~(SDXC_PROT_CTRL_DMA_SEL_MASK | SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK); + + prot_ctrl |= (1UL << 8); + + sdxc_set_data_timeout(base, config->data_timeout, NULL); + + base->PROT_CTRL = prot_ctrl; + + // Enable SD internal clock and the output clock + base->SYS_CTRL |= SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK; + while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK)) { + + } + base->SYS_CTRL |= SDXC_SYS_CTRL_PLL_ENABLE_MASK; + while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK)) { + + } + + base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; + + base->INT_STAT_EN = SDXC_STS_ALL_FLAGS; + base->INT_SIGNAL_EN = 0UL; + base->INT_STAT = SDXC_STS_ALL_FLAGS; + + /* Set Host to version 4, enable 26-bit ADMA2 length mode */ + base->AC_HOST_CTRL &= ~(SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK | SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK); + base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK | SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK; +} + +void sdxc_set_data_timeout(SDXC_Type *base, uint32_t timeout_in_ms, uint32_t *actual_timeout_ms) +{ + static uint32_t pre_calc_timeout_list[15] = { + 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, + 32768,65536, 131072 + }; + + uint32_t field_value = 0; + for(uint32_t i = 0; i < ARRAY_SIZE(pre_calc_timeout_list); i++) { + if (timeout_in_ms < pre_calc_timeout_list[i]) { + field_value = i; + break; + } + } + uint32_t max_index = ARRAY_SIZE(pre_calc_timeout_list) - 1U; + if (timeout_in_ms > pre_calc_timeout_list[max_index]) { + field_value = max_index; + } + + sdxc_enable_interrupt_status(base, SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK, false); + base->SYS_CTRL = (base->SYS_CTRL & ~SDXC_SYS_CTRL_TOUT_CNT_MASK) | SDXC_SYS_CTRL_TOUT_CNT_SET(field_value); + sdxc_enable_interrupt_status(base, SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK, true); + + if (actual_timeout_ms != NULL) { + *actual_timeout_ms = pre_calc_timeout_list[field_value]; + } +} + +void sdxc_set_mmc_boot_config(SDXC_Type *base, const sdxc_boot_config_t *config) +{ + uint32_t emmc_boot_reg = base->EMMC_BOOT_CTRL; + + emmc_boot_reg &= ~(SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK | SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK); + + if (config->enable_boot_ack) { + emmc_boot_reg |= SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK; + } + + //TODO: Auto stop at block gap, how to handle this? + + uint32_t block_attr_reg = base->BLK_ATTR & ~(SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK | SDXC_BLK_ATTR_BLOCK_CNT_MASK); + + block_attr_reg |= SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(config->block_size) | + SDXC_BLK_ATTR_BLOCK_CNT_SET(config->block_cnt); + + base->BLK_ATTR = block_attr_reg; + base->EMMC_BOOT_CTRL = emmc_boot_reg; +} + +void sdxc_set_data_config(SDXC_Type *base, sdxc_xfer_direction_t data_dir, uint32_t block_cnt, uint32_t block_size) +{ + uint32_t block_attr_reg = base->BLK_ATTR & ~(SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK | SDXC_BLK_ATTR_BLOCK_CNT_MASK); + + block_attr_reg |= SDXC_BLK_ATTR_BLOCK_CNT_SET(block_cnt) | SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(block_size); + + base->BLK_ATTR = block_attr_reg; + + if (data_dir == sdxc_xfer_dir_write) { + base->CMD_XFER &= ~SDXC_CMD_XFER_DATA_XFER_DIR_MASK; + } else { + base->CMD_XFER |= SDXC_CMD_XFER_DATA_XFER_DIR_MASK; + } +} + +hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, const uint32_t *data_addr, + bool enable_auto_cmd23) +{ + if (dma_cfg->dma_type == sdxc_dmasel_sdma) { + + if (((uint32_t) data_addr % SDXC_SYS_DMA_ALIGN_LEN) != 0U) { + return status_sdxc_dma_addr_unaligned; + } + + base->ADMA_SYS_ADDR = (uint32_t) data_addr; + } else { + base->ADMA_SYS_ADDR = (uint32_t) dma_cfg->adma_table; + } + + // Set DMA mode + uint32_t sys_ctl = base->SYS_CTRL; + base->PROT_CTRL = (base->PROT_CTRL & ~SDXC_PROT_CTRL_DMA_SEL_MASK) | SDXC_PROT_CTRL_DMA_SEL_SET(dma_cfg->dma_type); + base->SYS_CTRL = sys_ctl; + return status_success; +} + + +hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, uint32_t adma_table_words, const uint32_t *data_buf, + uint32_t data_bytes, uint32_t flags) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((adma_tbl == NULL) || (data_buf == NULL)) { + break; + } + if ((uint32_t) data_buf % 4U != 0U) { + status = status_sdxc_dma_addr_unaligned; + break; + } + + uint32_t start_idx = 0; + uint32_t min_entries; + uint32_t max_entries = adma_table_words * sizeof(uint32_t) / sizeof(sdxc_adma2_descriptor_t); + sdxc_adma2_descriptor_t *adma2_desc = (sdxc_adma2_descriptor_t *) adma_tbl; + + /* Ensure that the data_bytes is 4-byte aligned. */ + data_bytes += (data_bytes % sizeof(uint32_t)); + + min_entries = data_bytes / SDXC_DMA_MAX_XFER_LEN_26BIT; + if (data_bytes % SDXC_DMA_MAX_XFER_LEN_26BIT != 0U) { + min_entries += 1U; + } + + uint32_t i; + if (flags == (uint32_t) sdxc_adma_desc_multi_flag) { + + for (i = 0; i < max_entries; i++) { + if (adma2_desc[i].valid == 0U) { + break; + } + } + + start_idx = i; + + //add one entry as dummy entry + min_entries += 1U; + } + + if ((min_entries + start_idx) > max_entries) { + return status_invalid_argument; + } + + uint32_t dma_buf_len = 0U; + const uint32_t *data = data_buf; + for (i = start_idx; i < (min_entries + start_idx); i++) { + if (data_bytes > SDXC_DMA_MAX_XFER_LEN_26BIT) { + dma_buf_len = SDXC_DMA_MAX_XFER_LEN_26BIT; + } else { + dma_buf_len = (data_bytes == 0U) ? sizeof(uint32_t) : data_bytes; + } + + /* Format each adma2 descriptor entry */ + adma2_desc[i].addr = (data_bytes == 0U) ? &s_sdxc_boot_dummy : data; + adma2_desc[i].len_attr = 0U; + adma2_desc[i].len_lower = dma_buf_len & 0xFFFFU; + adma2_desc[i].len_upper = dma_buf_len >> 16; + adma2_desc[i].len_attr |= SDXC_ADMA2_DESC_VALID_FLAG; + if (data_bytes != 0U) { + adma2_desc[i].act = SDXC_ADMA2_DESC_TYPE_TRANS; + } + + data = (uint32_t *) ((uint32_t) data + dma_buf_len); + if (data_bytes != 0U) { + data_bytes -= dma_buf_len; + } + } + + if (flags == (uint32_t) sdxc_adma_desc_multi_flag) { + adma2_desc[i + 1U].len_attr |= SDXC_ADMA2_DESC_TYPE_TRANS; + } else { + adma2_desc[i - 1U].len_attr |= SDXC_ADMA2_DESC_END_FLAG; + } + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, sdxc_adma_config_t *dma_cfg, + sdxc_data_t *data_cfg, uint32_t flags) +{ + hpm_stat_t status = status_fail; + + uint32_t boot_dummy_offset = (data_cfg->data_type == (uint8_t) sdxc_xfer_data_boot_continuous) ? sizeof(uint32_t) + : 0; + const uint32_t *data; + + if (data_cfg->rx_data == NULL) { + data = (const uint32_t *) data_cfg->tx_data; + } else { + data = (const uint32_t *) data_cfg->rx_data; + } + if (boot_dummy_offset > 0) { + data++; + } + + uint32_t block_size = data_cfg->block_size * data_cfg->block_cnt - boot_dummy_offset; + + if (dma_cfg->dma_type == sdxc_dmasel_sdma) { + status = status_success; + } else if (dma_cfg->dma_type == sdxc_dmasel_adma2) { + status = sdxc_set_adma2_desc(dma_cfg->adma_table, dma_cfg->adma_table_words, data, block_size, flags); + + } else if (dma_cfg->dma_type == sdxc_dmasel_adma2_or_3) { + //TODO: To be implemented + + } else { + status = status_invalid_argument; + } + + if ((status == status_success) && (data_cfg->data_type != (uint8_t) sdxc_xfer_data_boot_continuous)) { + status = sdxc_set_dma_config(base, dma_cfg, data, data_cfg->enable_auto_cmd23); + } + + return status; +} + +bool sdxc_reset(SDXC_Type *base, sdxc_sw_reset_type_t reset_type, uint32_t timeout) +{ + uint32_t reset_mask = 0U; + + switch (reset_type) { + case sdxc_reset_all: + reset_mask = SDXC_SYS_CTRL_SW_RST_ALL_MASK; + break; + case sdxc_reset_cmd_line: + reset_mask = SDXC_SYS_CTRL_SW_RST_CMD_MASK; + break; + case sdxc_reset_data_line: + reset_mask = SDXC_SYS_CTRL_SW_RST_DAT_MASK; + break; + default: + // Do nothing + break; + } + base->SYS_CTRL |= reset_mask; + while (IS_HPM_BITMASK_SET(base->SYS_CTRL, reset_mask)) { + if (timeout == 0U) { + return false; + } + timeout--; + } + + return true; +} + +void sdxc_select_voltage(SDXC_Type *base, sdxc_bus_voltage_option_t option) +{ + uint32_t option_u32 = (uint32_t) option; + + base->PROT_CTRL = (base->PROT_CTRL & ~SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) | + SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(option_u32); + + if ((option == sdxc_bus_voltage_sd_1v8) || (option == sdxc_bus_voltage_emmc_1v8)) { + base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; + } else { + base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; + } +} + +void sdxc_enable_wakeup_event(SDXC_Type *base, sdxc_wakeup_event_t evt, bool enable) +{ + uint32_t evt_u32 = (uint32_t) evt; + + if (enable) { + base->PROT_CTRL |= evt_u32; + } else { + base->PROT_CTRL &= ~evt_u32; + } +} + +void sdxc_set_data_bus_width(SDXC_Type *base, sdxc_bus_width_t width) +{ + uint32_t host_ctrl = base->PROT_CTRL & ~(SDXC_PROT_CTRL_EXT_DAT_XFER_MASK | SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK); + + if (width == sdxc_bus_width_1bit) { + host_ctrl |= SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(0U); + } else if (width == sdxc_bus_width_4bit) { + host_ctrl |= SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(1U); + } else if (width == sdxc_bus_width_8bit) { + host_ctrl |= SDXC_PROT_CTRL_EXT_DAT_XFER_SET(1U); + } else { + // Do nothing + } + base->PROT_CTRL = host_ctrl; + + sdxc_enable_sd_clock(base, true); +} + +uint32_t sdxc_get_data_bus_width(SDXC_Type *base) +{ + uint32_t bus_width; + uint32_t bus_width_mask = base->PROT_CTRL & (SDXC_PROT_CTRL_EXT_DAT_XFER_MASK | SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK); + + if (IS_HPM_BITMASK_SET(bus_width_mask, SDXC_PROT_CTRL_EXT_DAT_XFER_MASK)) { + bus_width = 8; + } else if (IS_HPM_BITMASK_SET(bus_width_mask, SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK)) { + bus_width = 4; + } else { + bus_width = 1; + } + return bus_width; +} + +void sdxc_set_speed_mode(SDXC_Type *base, sdxc_speed_mode_t mode) +{ + uint32_t mode_u32 = (uint32_t) mode; + + base->AC_HOST_CTRL = (base->AC_HOST_CTRL & ~SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) | + SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(mode_u32); + if ((mode_u32 & 0xFU) > sdxc_sd_speed_sdr12) { + base->PROT_CTRL |= SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; + } else { + base->PROT_CTRL &= ~SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; + } +} + +hpm_stat_t sdxc_transfer_nonblocking(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) +{ + hpm_stat_t status = status_invalid_argument; + sdxc_command_t *cmd = xfer->command; + sdxc_data_t *data = xfer->data; + bool enable_tuning = ((data == NULL)) ? false : (data->data_type == (uint8_t) sdxc_xfer_data_tuning); + uint32_t xfer_flags = (uint32_t) sdxc_cmd_only; + + uint32_t block_size = 0U; + uint32_t block_cnt = 0U; + do { + if (IS_HPM_BITMASK_SET(base->INT_STAT, SDXC_INT_STAT_RE_TUNE_EVENT_MASK)) { + base->INT_STAT = SDXC_INT_STAT_RE_TUNE_EVENT_MASK; + status = status_sdxc_retuning_request; + break; + } + + uint32_t new_xfer_flags = 0; + if (data != NULL) { + + if ((dma_config != NULL) && (!enable_tuning)) { + uint32_t flags = IS_HPM_BITMASK_SET(data->data_type, sdxc_xfer_data_boot) ? sdxc_adma_desc_multi_flag + : sdxc_adma_desc_single_flag; + status = sdxc_set_adma_table_config(base, dma_config, data, flags); + if (status != status_success) { + break; + } + } + block_size = data->block_size; + block_cnt = data->block_cnt; + xfer_flags = data->enable_auto_cmd12 ? (uint32_t) sdxc_data_with_auto_cmd12 : 0; + xfer_flags |= (data->enable_auto_cmd23) ? (uint32_t) sdxc_data_with_auto_cmd23 : 0; + xfer_flags |= (data->tx_data != NULL) ? (uint32_t) sdxc_cmd_and_tx_data : 0; + xfer_flags |= (data->rx_data != NULL) ? (uint32_t) sdxc_cmd_and_rx_data : 0; + xfer_flags |= (data->data_type == sdxc_xfer_data_boot) ? (uint32_t) sdxc_boot_data : 0; + xfer_flags |= (data->data_type == sdxc_xfer_data_boot_continuous) ? (uint32_t) sdxc_boot_data_continuous + : 0; + cmd->cmd_flags |= SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK; + + if (dma_config->dma_type != sdxc_dmasel_nodma) { + cmd->cmd_flags |= SDXC_CMD_XFER_DMA_ENABLE_MASK; + } + + status = sdxc_set_transfer_config(base, xfer_flags, block_size, block_cnt, &new_xfer_flags); + if (status != status_success) { + break; + } + } + + cmd->cmd_flags |= new_xfer_flags; + status = sdxc_send_command(base, cmd); + } while (false); + + return status; +} + +hpm_stat_t sdxc_transfer_blocking(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) +{ + hpm_stat_t status = status_invalid_argument; + sdxc_command_t *cmd = xfer->command; + sdxc_data_t *data = xfer->data; + bool enable_dma = true; + do { + status = sdxc_transfer_nonblocking(base, dma_config, xfer); + HPM_BREAK_IF(status != status_success); + + bool polling_cmd_done = (data == NULL) || (data->data_type == sdxc_xfer_data_normal); + status = sdxc_wait_cmd_done(base, cmd, polling_cmd_done); + if (status != status_success) { + status = status_sdxc_send_cmd_failed; + break; + } + if (data != NULL) { + status = sdxc_transfer_data_blocking(base, data, enable_dma); + } + } while (false); + + return status; +} + +hpm_stat_t sdxc_error_recovery(SDXC_Type *base) +{ + hpm_stat_t status = status_success; + /* D8, D3-D0 of ERROR_INT_STAT */ + uint32_t cmdline_err_mask = + SDXC_INT_STAT_AUTO_CMD_ERR_MASK | SDXC_INT_STAT_CMD_TOUT_ERR_MASK | SDXC_INT_STAT_CMD_CRC_ERR_MASK | + SDXC_INT_STAT_CMD_END_BIT_ERR_MASK | SDXC_INT_STAT_CMD_IDX_ERR_MASK; + + if ((base->INT_STAT & cmdline_err_mask) != 0U) { + status = status_sdxc_send_cmd_failed; + /* Only Auto Command error */ + if ((base->INT_STAT & cmdline_err_mask) == SDXC_INT_STAT_AUTO_CMD_ERR_MASK) { + /* Will reset command line */ + } else { + if (((base->CMD_XFER & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) != 0U) || + ((base->AC_HOST_CTRL & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK))) { + /* Will reset command line */ + } else { + /* Wait until command completes */ + uint32_t timeout = 1000000UL; + while (!IS_HPM_BITMASK_SET(base->CMD_XFER, SDXC_INT_STAT_CMD_COMPLETE_MASK)) { + --timeout; + if (timeout < 1U) { + status = status_timeout; + break; + } + } + } + } + + sdxc_reset(base, sdxc_reset_cmd_line, 0xFFFFFFU); + } + + /* Check D9, D6-D4 in ERR_INT_STAT */ + uint32_t dataline_err_mask = + SDXC_INT_STAT_ADMA_ERR_MASK | SDXC_INT_STAT_DATA_TOUT_ERR_MASK | SDXC_INT_STAT_DATA_CRC_ERR_MASK | + SDXC_INT_STAT_DATA_END_BIT_ERR_MASK; + + if ((base->INT_STAT & dataline_err_mask) != 0U) { + status = status_sdxc_transfer_data_failed; + sdxc_reset(base, sdxc_reset_data_line, 0xFFFFFFU); + } + sdxc_clear_interrupt_status(base, ~0UL); + + if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CMD_INHIBIT_MASK)) { + sdxc_reset(base, sdxc_reset_cmd_line, 10000U); + } + if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_DAT_INHIBIT_MASK)) { + sdxc_reset(base, sdxc_reset_data_line, 10000U); + } + + return status; +} + +hpm_stat_t sdxc_tuning_error_recovery(SDXC_Type *base) +{ + sdxc_reset_tuning_engine(base); + sdxc_reset(base, sdxc_reset_data_line, 0xFFFFFFUL); + sdxc_reset(base, sdxc_reset_cmd_line, 0xFFFFFFUL); + + return status_success; +} + +hpm_stat_t sdxc_perform_tuning_flow_sequence(SDXC_Type *base, uint8_t tuning_cmd) +{ + hpm_stat_t status = status_success; + + /* Turn off Sampling clock */ + sdxc_enable_sd_clock(base, false); + sdxc_execute_tuning(base); + uint32_t block_size = SDXC_PROT_CTRL_EXT_DAT_XFER_GET(base->PROT_CTRL) ? 128U : 64U; + sdxc_command_t cmd; + (void) memset(&cmd, 0, sizeof(cmd)); + cmd.cmd_index = tuning_cmd; + cmd.cmd_argument = 0; + cmd.cmd_flags = SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK; + cmd.resp_type = sdxc_dev_resp_r1; + sdxc_enable_sd_clock(base, true); + do { + base->BLK_ATTR = block_size; + base->SDMASA = 1; + sdxc_send_command(base, &cmd); + while (!IS_HPM_BITMASK_SET(base->INT_STAT, SDXC_INT_STAT_BUF_RD_READY_MASK)) {} + sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); + } while (IS_HPM_BITMASK_SET(base->AC_HOST_CTRL, SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK)); + + if (!IS_HPM_BITMASK_SET(base->AC_HOST_CTRL, SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK)) { + sdxc_tuning_error_recovery(base); + status = status_sdxc_tuning_failed; + } + + return status; +} + +hpm_stat_t sdxc_perform_software_tuning(SDXC_Type *base, uint8_t tuning_cmd) +{ + hpm_stat_t status; + + sdxc_tuning_error_recovery(base); + + /* Turn off Sampling clock */ + sdxc_enable_sd_clock(base, false); + sdxc_reset_tuning_engine(base); + uint32_t block_size = SDXC_PROT_CTRL_EXT_DAT_XFER_GET(base->PROT_CTRL) ? 128U : 64U; + sdxc_command_t cmd; + (void) memset(&cmd, 0, sizeof(cmd)); + cmd.cmd_index = tuning_cmd; + cmd.cmd_argument = 0; + cmd.cmd_flags = SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK; + cmd.resp_type = sdxc_dev_resp_r1; + base->BLK_ATTR = block_size; + base->SDMASA = 0; + uint32_t tuning_cclk_sel = 0; + sdxc_enable_software_tuning(base, true); + sdxc_set_center_phase_code(base, 0); + sdxc_enable_sd_clock(base, true); + + bool center_phase_codes_valid[255]; + (void) memset(¢er_phase_codes_valid, 0, sizeof(center_phase_codes_valid)); + + do { + + sdxc_send_command(base, &cmd); + + uint32_t timeout_cnt = 0xFFFFFUL; + while (!IS_HPM_BITMASK_SET(base->INT_STAT, + SDXC_INT_STAT_BUF_RD_READY_MASK | SDXC_INT_STAT_ERR_INTERRUPT_MASK)) { + timeout_cnt--; + if (timeout_cnt < 1U) { + break; + } + } + + if (IS_HPM_BITMASK_SET(base->INT_STAT, SDXC_INT_STAT_BUF_RD_READY_MASK)) { + center_phase_codes_valid[tuning_cclk_sel] = true; + } + sdxc_clear_interrupt_status(base, ~0UL); + + sdxc_reset(base, sdxc_reset_cmd_line, 0xFFFFFFU); + sdxc_reset(base, sdxc_reset_data_line, 0xFFFFFFU); + + tuning_cclk_sel++; + + sdxc_enable_sd_clock(base, false); + sdxc_set_center_phase_code(base, tuning_cclk_sel); + sdxc_enable_sd_clock(base, true); + + } while (tuning_cclk_sel < SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK)); + + int32_t first_window_idx = -1; + int32_t last_window_idx = -1; + for (int32_t i = 0; i < ARRAY_SIZE(center_phase_codes_valid); i++) { + if (center_phase_codes_valid[i]) { + first_window_idx = i; + break; + } + } + + for (int32_t i = ARRAY_SIZE(center_phase_codes_valid) - 1; i >= 0; i--) { + if (center_phase_codes_valid[i]) { + last_window_idx = i; + break; + } + } + + if ((first_window_idx >= 0) && (last_window_idx >= 0)) { + + uint32_t center_window = (first_window_idx + last_window_idx) / 2; + sdxc_set_center_phase_code(base, center_window); + + status = status_success; + } else { + status = status_sdxc_tuning_failed; + } + + return status; +} + +hpm_stat_t sdxc_perform_auto_tuning(SDXC_Type *base, uint8_t tuning_cmd) +{ + sdxc_enable_auto_tuning(base, true); + + return sdxc_perform_tuning_flow_sequence(base, tuning_cmd); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c new file mode 100644 index 0000000000..893258e5c0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c @@ -0,0 +1,531 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_spi_drv.h" + +#ifndef HPM_SPI_DRV_DEFAULT_RETRY_COUNT +/* the waiting time of timeout status is related to retry count and CPU frequency */ +#define HPM_SPI_DRV_DEFAULT_RETRY_COUNT (5000U) +#endif + +typedef enum { + spi_data_length_8_bits = 7, + spi_data_length_16_bits = 15, + spi_data_length_31_bits = 30 +} spi_data_length_in_bits_t; + +hpm_stat_t spi_wait_for_idle_status(SPI_Type *ptr) +{ + uint32_t status; + uint32_t retry = 0; + + do { + status = ptr->STATUS; + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } while(status & SPI_STATUS_SPIACTIVE_MASK); + + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + return status_success; +} + +hpm_stat_t spi_wait_for_busy_status(SPI_Type *ptr) +{ + uint32_t status; + uint32_t retry = 0; + + do { + status = ptr->STATUS; + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } while(!(status & SPI_STATUS_SPIACTIVE_MASK)); + + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + return status_success; +} + +static hpm_stat_t spi_write_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd) +{ + if (mode == spi_master_mode) { + if (config->master_config.cmd_enable == true) { + if (cmd == NULL) { + return status_invalid_argument; + } + ptr->CMD = SPI_CMD_CMD_SET(*cmd); + } + else { + ptr->CMD = SPI_CMD_CMD_SET(0xff); /* Write a dummy byte */ + } + } + + return status_success; +} + +static void spi_read_command(SPI_Type *ptr, spi_mode_selection_t mode, uint8_t *cmd) +{ + if (mode == spi_slave_mode) { + *cmd = (uint8_t)(ptr->CMD & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT; + } +} + +static hpm_stat_t spi_write_address(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint32_t *addr) +{ + if (mode == spi_master_mode) { + if (config->master_config.addr_enable == true) { + if (addr == NULL) { + return status_invalid_argument; + } + ptr->ADDR = SPI_ADDR_ADDR_SET(*addr); + } + } + + return status_success; +} + +static hpm_stat_t spi_write_data(SPI_Type *ptr, uint8_t datalen, uint8_t *buff, uint32_t size) +{ + uint32_t status; + uint32_t transferred = 0; + uint32_t retry = 0; + + /* check parameter validity */ + if (buff == NULL || size == 0) { + return status_invalid_argument; + } + + /* data transfer */ + while (transferred < size) + { + status = ptr->STATUS; + if (!(status & SPI_STATUS_TXFULL_MASK)) { + /* write data into the txfifo */ + if (datalen <= spi_data_length_8_bits) { + ptr->DATA = *(uint8_t *)buff & ((1UL << (datalen + 1)) - 1); + buff += sizeof(uint8_t); + } + else if (datalen <= spi_data_length_16_bits) { + ptr->DATA = *(uint16_t *)buff & ((1UL << (datalen + 1)) - 1); + buff += sizeof(uint16_t); + } + else if (datalen <= spi_data_length_31_bits) { + ptr->DATA = *(uint32_t *)buff & ((1UL << (datalen + 1)) - 1); + buff += sizeof(uint32_t); + } + else { + ptr->DATA = *(uint32_t *)buff & 0xffffffff; + buff += sizeof(uint32_t); + } + /* transfer count increment */ + transferred++; + retry = 0; + } else { + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + /* dummy state may triggers timeout if dummy count, retry count, spi rate and cpu frequency are inappropriate */ + return status_timeout; + } + + return status_success; +} + +static hpm_stat_t spi_read_data(SPI_Type *ptr, uint8_t datalen, uint8_t *buff, uint32_t size) +{ + uint32_t status; + uint32_t transferred = 0; + uint32_t retry = 0; + + /* check parameter validity */ + if (buff == NULL || size == 0) { + return status_invalid_argument; + } + + /* data transfer */ + while (transferred < size) + { + status = ptr->STATUS; + if (!(status & SPI_STATUS_RXEMPTY_MASK)) { + /* read data from the txfifo */ + if (datalen <= spi_data_length_8_bits) { + *(uint8_t *)buff = (uint8_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); + buff += sizeof(uint8_t); + } + else if (datalen <= spi_data_length_16_bits) { + *(uint16_t *)buff = (uint16_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); + buff += sizeof(uint16_t); + } + else if (datalen <= spi_data_length_31_bits) { + *(uint32_t *)buff = (uint32_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); + buff += sizeof(uint32_t); + } + else { + *(uint32_t *)buff = (uint32_t)(ptr->DATA & 0xffffffff); + buff += sizeof(uint32_t); + } + /* transfer count increment */ + transferred++; + retry = 0; + } else { + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + /* dummy state may triggers timeout if dummy count, retry count, spi rate and cpu frequency are inappropriate */ + return status_timeout; + } + + return status_success; +} + +static hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t datalen, uint8_t *wbuff, uint32_t wsize, uint8_t *rbuff, uint32_t rsize) +{ + uint32_t status; + uint32_t wtransferred = 0; + uint32_t rtransferred = 0; + uint32_t retry = 0; + + /* check parameter validity */ + if (wbuff == NULL || wsize == 0 || rbuff == NULL || rsize == 0) { + return status_invalid_argument; + } + + /* data transfer */ + while (wtransferred < wsize || rtransferred < rsize) { + status = ptr->STATUS; + + if (wtransferred < wsize) { + /* write data into the txfifo */ + if (!(status & SPI_STATUS_TXFULL_MASK)) { + if (datalen <= spi_data_length_8_bits) { + ptr->DATA = *(uint8_t *)wbuff & ((1UL << (datalen + 1)) - 1); + wbuff += sizeof(uint8_t); + } + else if (datalen <= spi_data_length_16_bits) { + ptr->DATA = *(uint16_t *)wbuff & ((1UL << (datalen + 1)) - 1); + wbuff += sizeof(uint16_t); + } + else if (datalen <= spi_data_length_31_bits) { + ptr->DATA = *(uint32_t *)wbuff & ((1UL << (datalen + 1)) - 1); + wbuff += sizeof(uint32_t); + } + else { + ptr->DATA = *(uint32_t *)wbuff & 0xffffffff; + wbuff += sizeof(uint32_t); + } + /* transfer count increment */ + wtransferred++; + retry = 0; + } else { + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + + if (rtransferred < rsize) { + /* read data from the txfifo */ + if (!(status & SPI_STATUS_RXEMPTY_MASK)) { + + if (datalen <= spi_data_length_8_bits) { + *(uint8_t *)rbuff = (uint8_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); + rbuff += sizeof(uint8_t); + } + else if (datalen <= spi_data_length_16_bits) { + *(uint16_t *)rbuff = (uint16_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); + rbuff += sizeof(uint16_t); + } + else if (datalen <= spi_data_length_31_bits) { + *(uint32_t *)rbuff = (uint32_t)(ptr->DATA & ((1UL << (datalen + 1)) - 1)); + rbuff += sizeof(uint32_t); + } + else { + *(uint32_t *)rbuff = (uint32_t)(ptr->DATA & 0xffffffff); + rbuff += sizeof(uint32_t); + } + /* transfer count increment */ + rtransferred++; + retry = 0; + } else { + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + } + } + + if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { + /* dummy state may triggers timeout if dummy count, retry count, spi rate and cpu frequency are inappropriate */ + return status_timeout; + } + + return status_success; +} + +static hpm_stat_t spi_no_data(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config) +{ + hpm_stat_t stat; + if (mode == spi_master_mode) { + if (config->master_config.cmd_enable == false && config->master_config.addr_enable == false) { + return status_invalid_argument; + } + } + else { + HPM_CHECK_RET(spi_wait_for_busy_status(ptr)); + HPM_CHECK_RET(spi_wait_for_idle_status(ptr)); + } + + return status_success; +} + +void spi_master_get_default_timing_config(spi_timing_config_t *config) +{ + config->master_config.cs2sclk = spi_cs2sclk_half_sclk_4; + config->master_config.csht = spi_csht_half_sclk_12; +} + +void spi_master_get_default_format_config(spi_format_config_t *config) +{ + config->master_config.addr_len_in_bytes = 1; + config->common_config.data_len_in_bits = 32; + config->common_config.data_merge = false; + config->common_config.mosi_bidir = false; + config->common_config.lsb = false; + config->common_config.mode = spi_master_mode; + config->common_config.cpol = spi_sclk_high_idle; + config->common_config.cpha = spi_sclk_sampling_even_clk_edges; +} + +void spi_slave_get_default_format_config(spi_format_config_t *config) +{ + config->common_config.data_len_in_bits = 32; + config->common_config.data_merge = false; + config->common_config.mosi_bidir = false; + config->common_config.lsb = false; + config->common_config.mode = spi_master_mode; + config->common_config.cpol = spi_sclk_high_idle; + config->common_config.cpha = spi_sclk_sampling_even_clk_edges; +} + +void spi_master_get_default_control_config(spi_control_config_t *config) +{ + config->master_config.cmd_enable = false; + config->master_config.addr_enable = false; + config->master_config.token_enable = false; + config->master_config.token_value = spi_token_value_0x00; + config->master_config.addr_phase_fmt = spi_address_phase_format_single_io_mode; + config->common_config.tx_dma_enable = false; + config->common_config.rx_dma_enable = false; + config->common_config.trans_mode = spi_trans_write_only; + config->common_config.data_phase_fmt = spi_single_io_mode; + config->common_config.dummy_cnt = spi_dummy_count_2; +} + +void spi_slave_get_default_control_config(spi_control_config_t *config) +{ + config->slave_config.slave_data_only = false; + config->common_config.tx_dma_enable = false; + config->common_config.rx_dma_enable = false; + config->common_config.trans_mode = spi_trans_read_only; + config->common_config.data_phase_fmt = spi_single_io_mode; + config->common_config.dummy_cnt = spi_dummy_count_2; +} + +hpm_stat_t spi_master_timing_init(SPI_Type *ptr, spi_timing_config_t *config) +{ + uint8_t sclk_div; + + if (config->master_config.sclk_freq_in_hz == 0) { + return status_invalid_argument; + } + + if (config->master_config.clk_src_freq_in_hz > config->master_config.sclk_freq_in_hz) { + sclk_div = (config->master_config.clk_src_freq_in_hz / config->master_config.sclk_freq_in_hz) / 2 - 1; + } + else { + sclk_div = 0xff; + } + + ptr->TIMING = SPI_TIMING_CS2SCLK_SET(config->master_config.cs2sclk) | + SPI_TIMING_CSHT_SET(config->master_config.csht) | + SPI_TIMING_SCLK_DIV_SET(sclk_div); + + return status_success; +} + +void spi_format_init(SPI_Type *ptr, spi_format_config_t *config) +{ + ptr->TRANSFMT = SPI_TRANSFMT_ADDRLEN_SET(config->master_config.addr_len_in_bytes - 1) | + SPI_TRANSFMT_DATALEN_SET(config->common_config.data_len_in_bits - 1) | + SPI_TRANSFMT_DATAMERGE_SET(config->common_config.data_merge) | + SPI_TRANSFMT_MOSIBIDIR_SET(config->common_config.mosi_bidir) | + SPI_TRANSFMT_LSB_SET(config->common_config.lsb) | + SPI_TRANSFMT_SLVMODE_SET(config->common_config.mode) | + SPI_TRANSFMT_CPOL_SET(config->common_config.cpol) | + SPI_TRANSFMT_CPHA_SET(config->common_config.cpha); +} + +hpm_stat_t spi_transfer(SPI_Type *ptr, + spi_control_config_t *config, + uint8_t *cmd, uint32_t *addr, + uint8_t *wbuff, uint32_t wsize, uint8_t *rbuff, uint32_t rsize) +{ + hpm_stat_t stat = status_fail; + uint8_t mode ,data_len, trans_mode; + + ptr->TRANSCTRL = SPI_TRANSCTRL_SLVDATAONLY_SET(config->slave_config.slave_data_only) | + SPI_TRANSCTRL_CMDEN_SET(config->master_config.cmd_enable) | + SPI_TRANSCTRL_ADDREN_SET(config->master_config.addr_enable) | + SPI_TRANSCTRL_ADDRFMT_SET(config->master_config.addr_phase_fmt) | + SPI_TRANSCTRL_TRANSMODE_SET(config->common_config.trans_mode) | + SPI_TRANSCTRL_DUALQUAD_SET(config->common_config.data_phase_fmt) | + SPI_TRANSCTRL_TOKENEN_SET(config->master_config.token_enable) | + SPI_TRANSCTRL_WRTRANCNT_SET(wsize - 1) | + SPI_TRANSCTRL_TOKENVALUE_SET(config->master_config.token_value) | + SPI_TRANSCTRL_DUMMYCNT_SET(config->common_config.dummy_cnt) | + SPI_TRANSCTRL_RDTRANCNT_SET(rsize - 1); + + /* reset txfifo, rxfifo and control */ + ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK | SPI_CTRL_RXFIFORST_MASK | SPI_CTRL_SPIRST_MASK; + + /* read data length */ + data_len = (ptr->TRANSFMT & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT; + + /* read spi control mode */ + mode = (ptr->TRANSFMT & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT; + + /* read spi transfer mode */ + trans_mode = config->common_config.trans_mode; + + /* command phase */ + stat = spi_write_command(ptr, mode, config, cmd); + if (stat != status_success) { + return stat; + } + + /* address phase */ + stat = spi_write_address(ptr, mode, config, addr); + if (stat != status_success) { + return stat; + } + + /* data phase */ + if (trans_mode == spi_trans_write_read_together) { + stat = spi_write_read_data(ptr, data_len, wbuff, wsize, rbuff, rsize); + } + else if (trans_mode == spi_trans_write_only || trans_mode == spi_trans_dummy_write) { + stat = spi_write_data(ptr, data_len, wbuff, wsize); + } + else if (trans_mode == spi_trans_read_only || trans_mode == spi_trans_dummy_read) { + stat = spi_read_data(ptr, data_len, rbuff, rsize); + } + else if (trans_mode == spi_trans_write_read || trans_mode == spi_trans_write_dummy_read) { + stat = spi_write_read_data(ptr, data_len, wbuff, wsize, rbuff, rsize); + } + else if (trans_mode == spi_trans_read_write || trans_mode == spi_trans_read_dummy_write) { + stat = spi_write_read_data(ptr, data_len, wbuff, wsize, rbuff, rsize); + } + else if (trans_mode == spi_trans_no_data) { + stat = spi_no_data(ptr, mode, config); + } + else { + stat = status_invalid_argument; + } + + /* read command and address */ + if (stat == status_success) { + spi_read_command(ptr, mode, cmd); + } + + if (stat != status_success) { + return stat; + } + + stat = spi_wait_for_idle_status(ptr); + + return stat; +} + +hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, + spi_control_config_t *config, + uint8_t *cmd, uint32_t *addr, + uint32_t wsize, uint32_t rsize) +{ + hpm_stat_t stat = status_fail; + uint8_t mode; + + stat = spi_wait_for_idle_status(ptr); + if (stat != status_success) { + return stat; + } + + ptr->TRANSCTRL = SPI_TRANSCTRL_SLVDATAONLY_SET(config->slave_config.slave_data_only) | + SPI_TRANSCTRL_CMDEN_SET(config->master_config.cmd_enable) | + SPI_TRANSCTRL_ADDREN_SET(config->master_config.addr_enable) | + SPI_TRANSCTRL_ADDRFMT_SET(config->master_config.addr_phase_fmt) | + SPI_TRANSCTRL_TRANSMODE_SET(config->common_config.trans_mode) | + SPI_TRANSCTRL_DUALQUAD_SET(config->common_config.data_phase_fmt) | + SPI_TRANSCTRL_TOKENEN_SET(config->master_config.token_enable) | + SPI_TRANSCTRL_WRTRANCNT_SET(wsize - 1) | + SPI_TRANSCTRL_TOKENVALUE_SET(config->master_config.token_value) | + SPI_TRANSCTRL_DUMMYCNT_SET(config->common_config.dummy_cnt) | + SPI_TRANSCTRL_RDTRANCNT_SET(rsize - 1); + + /* reset txfifo, rxfifo and control */ + ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK | SPI_CTRL_RXFIFORST_MASK | SPI_CTRL_SPIRST_MASK; + + if (config->common_config.tx_dma_enable) { + ptr->CTRL |= SPI_CTRL_TXDMAEN_MASK; + } + if (config->common_config.rx_dma_enable) { + ptr->CTRL |= SPI_CTRL_RXDMAEN_MASK; + } + + /* read spi control mode */ + mode = (ptr->TRANSFMT & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT; + + /* command phase */ + stat = spi_write_command(ptr, mode, config, cmd); + if (stat != status_success) { + return stat; + } + + /* address phase */ + stat = spi_write_address(ptr, mode, config, addr); + if (stat != status_success) { + return stat; + } + + /* read command and address */ + if (stat == status_success) { + spi_read_command(ptr, mode, cmd); + } + + return stat; +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c new file mode 100644 index 0000000000..e277bfea40 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_tsns_drv.h" + +void tsns_configure_low_limit_event(TSNS_Type *ptr, int32_t low, tsns_event_t e) +{ + switch (e) { + case tsns_event_irq: + tsns_set_irq_threshold_low(ptr, low); + ptr->CONFIG |= TSNS_CONFIG_IRQ_EN_MASK | TSNS_CONFIG_COMPARE_MIN_EN_MASK; + break; + case tsns_event_reset: + tsns_set_reset_threshold_low(ptr, low); + ptr->CONFIG |= TSNS_CONFIG_RST_EN_MASK | TSNS_CONFIG_COMPARE_MIN_EN_MASK; + break; + default: + assert(NULL); + } +} + +void tsns_configure_high_limit_event(TSNS_Type *ptr, int32_t high, tsns_event_t e) +{ + switch (e) { + case tsns_event_irq: + tsns_set_irq_threshold_high(ptr, high); + ptr->CONFIG |= TSNS_CONFIG_IRQ_EN_MASK | TSNS_CONFIG_COMPARE_MAX_EN_MASK; + break; + case tsns_event_reset: + tsns_set_reset_threshold_high(ptr, high); + ptr->CONFIG |= TSNS_CONFIG_RST_EN_MASK | TSNS_CONFIG_COMPARE_MAX_EN_MASK; + break; + default: + assert(NULL); + } +} + +void tsns_configure_limit_event(TSNS_Type *ptr, int32_t high, int32_t low, tsns_event_t e) +{ + assert(high > low); + switch (e) { + case tsns_event_irq: + tsns_config_irq_threshold(ptr, high, low); + ptr->CONFIG |= TSNS_CONFIG_IRQ_EN_MASK | TSNS_CONFIG_COMPARE_MAX_EN_MASK | TSNS_CONFIG_COMPARE_MIN_EN_MASK; + break; + case tsns_event_reset: + tsns_config_reset_threshold(ptr, high, low); + ptr->CONFIG |= TSNS_CONFIG_RST_EN_MASK | TSNS_CONFIG_COMPARE_MAX_EN_MASK | TSNS_CONFIG_COMPARE_MIN_EN_MASK; + break; + default: + assert(NULL); + } +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c new file mode 100644 index 0000000000..e52c52bbaa --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_uart_drv.h" + +#define HPM_UART_DRV_RETRY_COUNT (5000U) +#define HPM_UART_MINIMUM_BAUDRATE (200U) + +#ifndef HPM_UART_BAUDRATE_TOLERANCE +#define HPM_UART_BAUDRATE_TOLERANCE (3) +#endif + +#define HPM_UART_OSC_MAX (32U) +#define HPM_UART_OSC_MIN (8U) +#define HPM_UART_BAUDRATE_DIV_MAX (0xFFFFU) +#define HPM_UART_BAUDRATE_DIV_MIN (1U) + +void uart_default_config(UART_Type *ptr, uart_config_t *config) +{ + config->baudrate = 115200; + config->word_length = word_length_8_bits; + config->parity = parity_none; + config->num_of_stop_bits = stop_bits_1; + config->fifo_enable = true; + config->rx_fifo_level = uart_rx_fifo_trg_not_empty; + config->tx_fifo_level = uart_tx_fifo_trg_not_full; + config->dma_enable = false; + config->modem_config.auto_flow_ctrl_en = false; + config->modem_config.loop_back_en = false; + config->modem_config.set_rts_high = false; +} + +static bool uart_calculate_baudrate(uint32_t freq, uint32_t baudrate, uint16_t *div_out, uint8_t *osc_out) +{ + uint16_t div, osc, delta; + float tmp; + if ((div_out == NULL) || (!freq) || (!baudrate) + || (baudrate < HPM_UART_MINIMUM_BAUDRATE) + || (freq / HPM_UART_BAUDRATE_DIV_MIN < baudrate * HPM_UART_OSC_MIN) + || (freq / HPM_UART_BAUDRATE_DIV_MAX > (baudrate * HPM_UART_OSC_MAX))) { + return 0; + } + + tmp = (float) freq / baudrate; + + for (uint8_t i = 0; i < HPM_UART_OSC_MAX; i += 2) { + /* osc range: 0 - 32, even number */ + if (i == 0) { + /* osc == 0 in bitfield, oversample rate is 32 */ + osc = HPM_UART_OSC_MAX; + } else if (i <= 8) { + /* osc <= 8 in bitfield, oversample rate is 8 */ + osc = HPM_UART_OSC_MIN; + } else { + /* osc > 8 && osc < 32 in bitfield, oversample rate is osc */ + osc = i; + } + delta = 0; + div = (uint16_t)(tmp / osc); + if (div < HPM_UART_BAUDRATE_DIV_MIN) { + /* invalid div */ + continue; + } + if (div * osc > tmp) { + delta = div * osc - tmp; + } else if (div * osc < tmp) { + delta = tmp - div * osc; + } + if (delta && ((delta * 100 / tmp) > HPM_UART_BAUDRATE_TOLERANCE)) { + continue; + } else { + *div_out = div; + *osc_out = (i <= 8 && i) ? osc : i; + return true; + } + } + return false; +} + +hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config) +{ + uint32_t tmp; + uint8_t osc; + uint16_t div; + + /* disable all interrupts */ + ptr->IER = 0; + /* Set DLAB to 1 */ + ptr->LCR |= UART_LCR_DLAB_MASK; + + if (!uart_calculate_baudrate(config->src_freq_in_hz, config->baudrate, &div, &osc)) { + return status_uart_no_suitable_baudrate_parameter_found; + } + ptr->OSCR = (ptr->OSCR & ~UART_OSCR_OSC_MASK) + | UART_OSCR_OSC_SET(osc); + ptr->DLL = UART_DLL_DLL_SET(div >> 0); + ptr->DLM = UART_DLM_DLM_SET(div >> 8); + + /* DLAB bit needs to be cleared once baudrate is configured */ + tmp = ptr->LCR & (~UART_LCR_DLAB_MASK); + + tmp &= ~(UART_LCR_SPS_MASK | UART_LCR_EPS_MASK | UART_LCR_PEN_MASK); + switch(config->parity) { + case parity_none: + break; + case parity_odd: + tmp |= UART_LCR_PEN_MASK; + break; + case parity_even: + tmp |= UART_LCR_PEN_MASK | UART_LCR_EPS_MASK; + break; + case parity_always_1: + tmp |= UART_LCR_PEN_MASK | UART_LCR_SPS_MASK; + break; + case parity_always_0: + tmp |= UART_LCR_EPS_MASK | UART_LCR_PEN_MASK + | UART_LCR_SPS_MASK; + break; + default: + /* invalid configuration */ + return status_invalid_argument; + } + + tmp &= ~(UART_LCR_STB_MASK | UART_LCR_WLS_MASK); + switch(config->num_of_stop_bits) { + case stop_bits_1: + break; + case stop_bits_1_5: + tmp |= UART_LCR_STB_MASK; + break; + case stop_bits_2: + if (config->word_length < word_length_6_bits) { + /* invalid configuration */ + return status_invalid_argument; + } + tmp |= UART_LCR_STB_MASK; + break; + default: + /* invalid configuration */ + return status_invalid_argument; + } + + ptr->LCR = tmp | UART_LCR_WLS_SET(config->word_length); + + ptr->FCR = UART_FCR_TFIFORST_MASK | UART_FCR_RFIFORST_MASK; + if (config->fifo_enable) { + /* Enable FIFO, reset TX and RX. */ + ptr->FCR = UART_FCR_TFIFORST_MASK + | UART_FCR_RFIFORST_MASK | UART_FCR_FIFOE_MASK + | UART_FCR_TFIFOT_SET(config->tx_fifo_level) + | UART_FCR_RFIFOT_SET(config->rx_fifo_level) + | UART_FCR_DMAE_SET(config->dma_enable); + } + + uart_modem_config(ptr, &config->modem_config); + return status_success; +} + +hpm_stat_t uart_set_baudrate(UART_Type *ptr, uint32_t baudrate, uint32_t src_clock_hz) +{ + uint8_t osc; + uint16_t div; + + /* Set DLAB to 1 */ + ptr->LCR |= UART_LCR_DLAB_MASK; + + if (!uart_calculate_baudrate(src_clock_hz, baudrate, &div, &osc)) { + return status_uart_no_suitable_baudrate_parameter_found; + } + + ptr->OSCR = (ptr->OSCR & ~UART_OSCR_OSC_MASK) | UART_OSCR_OSC_SET(osc); + ptr->DLL = UART_DLL_DLL_SET(div >> 0); + ptr->DLM = UART_DLM_DLM_SET(div >> 8); + + /* DLAB bit needs to be cleared once baudrate is configured */ + ptr->LCR &= ~UART_LCR_DLAB_MASK; + + return status_success; +} + +hpm_stat_t uart_send_byte(UART_Type *ptr, uint8_t c) +{ + uint32_t retry = 0; + + while (!(ptr->LSR & UART_LSR_THRE_MASK)) { + if (retry > HPM_UART_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_UART_DRV_RETRY_COUNT) { + return status_timeout; + } + + ptr->THR = UART_THR_THR_SET(c); + return status_success; +} + +hpm_stat_t uart_flush(UART_Type *ptr) +{ + uint32_t retry = 0; + + while (!(ptr->LSR & UART_LSR_TEMT_MASK)) { + if (retry > HPM_UART_DRV_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_UART_DRV_RETRY_COUNT) { + return status_timeout; + } + + return status_success; +} + +hpm_stat_t uart_receive_byte(UART_Type *ptr, uint8_t *byte) +{ + uint32_t retry = 0; + + while (!(ptr->LSR & UART_LSR_DR_MASK)) { + if (retry > HPM_UART_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_UART_DRV_RETRY_COUNT) { + return status_timeout; + } + + *byte = ptr->RBR & UART_RBR_RBR_MASK; + return status_success; +} + +void uart_set_signal_level(UART_Type *ptr, uart_signal_t signal, uart_signal_level_t level) +{ + if (level == uart_signal_level_low) + { + ptr->MCR = (ptr->MCR | signal); + } + else + { + ptr->MCR = (ptr->MCR & ~signal); + } +} + +hpm_stat_t uart_receive_data(UART_Type *ptr, uint8_t *source, uint32_t size_in_byte) +{ + for (uint32_t i = 0; i < size_in_byte; i++) { + if (status_success != uart_receive_byte(ptr, source + i)) { + return status_fail; + } + } + return status_success; +} + +hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *source, uint32_t size_in_byte) +{ + for (uint32_t i = 0; i < size_in_byte; i++) { + if (status_success != uart_send_byte(ptr, *(source + i))) { + return status_fail; + } + } + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c new file mode 100644 index 0000000000..f131c23967 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c @@ -0,0 +1,325 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/*---------------------------------------------------------------------* + * Include + *---------------------------------------------------------------------*/ +#include "hpm_usb_drv.h" +#include "hpm_misc.h" +#include "hpm_soc_feature.h" +#include "hpm_common.h" +/*---------------------------------------------------------------------* + * Macro Enum Declaration + *---------------------------------------------------------------------*/ + +/* ENDPTCTRL */ +enum { + ENDPTCTRL_STALL = HPM_BITSMASK(1, 0), + ENDPTCTRL_TYPE = HPM_BITSMASK(1, 2), + ENDPTCTRL_TOGGLE_INHIBIT = HPM_BITSMASK(1, 5), + ENDPTCTRL_TOGGLE_RESET = HPM_BITSMASK(1, 6), + ENDPTCTRL_ENABLE = HPM_BITSMASK(1, 7), +}; + +/*---------------------------------------------------------------------* + * Internal API + *---------------------------------------------------------------------*/ + +/* Initialize USB phy */ +static void usb_phy_init(USB_Type *ptr) +{ + uint32_t status; + + ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* set otg_utmi_reset_sw for naneng usbphy */ + ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* clr otg_utmi_suspend_m for naneng usbphy */ + ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* clr cfg_rst_n */ + + do { + status = USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(ptr->OTG_CTRL0); /* wait for reset status */ + } while (status == 0); + + ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* set otg_utmi_suspend_m for naneng usbphy */ + + for (int i = 0; i < USB_PHY_INIT_DELAY_COUNT; i++) { + ptr->PHY_CTRL0 = USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(0); /* used for delay */ + } + + ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* clear otg_utmi_reset_sw for naneng usbphy */ + + /* otg utmi clock detection */ + ptr->PHY_STATUS |= USB_PHY_STATUS_UTMI_CLK_VALID_MASK; /* write 1 to clear valid status */ + do { + status = USB_PHY_STATUS_UTMI_CLK_VALID_GET(ptr->PHY_STATUS); /* get utmi clock status */ + } while (status == 0); + + ptr->PHY_CTRL1 |= USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* set cfg_rst_n */ + + ptr->PHY_CTRL1 |= USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; /* set otg_suspendm */ +} + +/* De-initialize USB phy */ +static void usb_phy_deinit(USB_Type *ptr) +{ + ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* set otg_utmi_suspend_m for naneng usbphy */ + + ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* clear otg_utmi_reset_sw for naneng usbphy */ + + ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* clear cfg_rst_n */ + + ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; /* clear otg_suspendm */ +} + +static uint8_t usb_phy_get_line_state(USB_Type *ptr) +{ + return USB_PHY_STATUS_LINE_STATE_GET(ptr->PHY_STATUS); +} +/*---------------------------------------------------------------------* + * Driver API + *---------------------------------------------------------------------*/ +void usb_dcd_bus_reset(USB_Type *ptr, uint16_t ep0_max_packet_size) +{ + /* The reset value for all endpoint types is the control endpoint. If one endpoint + * direction is enabled and the paired endpoint of opposite direction is disabled, then the + * endpoint type of the unused direction must be changed from the control type to any other + * type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior + * for the data PID tracking on the active endpoint. + */ + + for(int i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { + ptr->ENDPTCTRL[i] = USB_ENDPTCTRL_TXT_SET(usb_xfer_bulk) | USB_ENDPTCTRL_RXT_SET(usb_xfer_bulk); + } + + /* Clear All Registers */ + ptr->ENDPTNAK = ptr->ENDPTNAK; + ptr->ENDPTNAKEN = 0; + ptr->USBSTS = ptr->USBSTS; + ptr->ENDPTSETUPSTAT = ptr->ENDPTSETUPSTAT; + ptr->ENDPTCOMPLETE = ptr->ENDPTCOMPLETE; + + while (ptr->ENDPTPRIME) {} + ptr->ENDPTFLUSH = 0xFFFFFFFF; + while (ptr->ENDPTFLUSH) {} +} + +void usb_dcd_init(USB_Type *ptr) +{ + /* Initialize USB phy */ + usb_phy_init(ptr); + + /* Reset controller */ + ptr->USBCMD |= USB_USBCMD_RST_MASK; + while(USB_USBCMD_RST_GET(ptr->USBCMD)) {} + + /* Set mode to device, must be set immediately after reset */ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM_SET(2); + + /* Disable setup lockout, please refer to "Control Endpoint Operation" section in RM. */ + ptr->USBMODE &= ~USB_USBMODE_SLOM_MASK; + + /* Set the endian */ + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + /* TODO Force fullspeed on non-highspeed port */ + /* ptr->PORTSC1 |= USB_PORTSC1_PFSC_MASK; */ + + /* Set parallel interface signal */ + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + + /* Set parallel transceiver width */ + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + + /* Not use interrupt threshold. */ + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; + + /* Enable VBUS discharge */ + ptr->OTGSC |= USB_OTGSC_VD_MASK; +} + +void usb_dcd_deinit(USB_Type *ptr) +{ + /* Stop */ + ptr->USBCMD &= ~USB_USBCMD_RS_MASK; + + /* Reset controller */ + ptr->USBCMD |= USB_USBCMD_RST_MASK; + while(USB_USBCMD_RST_GET(ptr->USBCMD)) {} + + /* De-initialize USB phy */ + usb_phy_deinit(ptr); + + /* Reset endpoint list address register */ + ptr->ENDPTLISTADDR = 0; + + /* Reset status register */ + ptr->USBSTS = ptr->USBSTS; + + /* Reset interrupt enable register */ + ptr->USBINTR = 0; +} + +/* Connect by enabling internal pull-up resistor on D+/D- */ +void usb_dcd_connect(USB_Type *ptr) +{ + ptr->USBCMD |= USB_USBCMD_RS_MASK; +} + +/* Disconnect by disabling internal pull-up resistor on D+/D- */ +void usb_dcd_disconnect(USB_Type *ptr) +{ + /* Stop */ + ptr->USBCMD &= ~USB_USBCMD_RS_MASK; + + /* Pullup DP to make the phy switch into full speed mode */ + ptr->USBCMD |= USB_USBCMD_RS_MASK; + + /* Clear the sof flag */ + ptr->USBSTS |= USB_USBSTS_SRI_MASK; + + /* Wait a SOF (It will not be a dead loop even usb cable is not connected.) */ + while (USB_USBSTS_SRI_GET(ptr->USBSTS) == 0) { + + } + + /* Disconnect */ + ptr->USBCMD &= ~USB_USBCMD_RS_MASK; +} + +/*---------------------------------------------------------------------* + * Endpoint API + *---------------------------------------------------------------------*/ +void usb_dcd_edpt_open(USB_Type *ptr, usb_endpoint_config_t *config) +{ + uint8_t const epnum = config->ep_addr & 0x0f; + uint8_t const dir = (config->ep_addr & 0x80) >> 7; + + /* Enable EP Control */ + ptr->ENDPTCTRL[epnum] |= ((config->xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0); +} + +void usb_dcd_edpt_xfer(USB_Type *ptr, uint8_t ep_idx) +{ + uint32_t offset = ep_idx / 2 + ((ep_idx % 2) ? 16 : 0); + + /* Start transfer */ + ptr->ENDPTPRIME = 1 << offset; +} + +void usb_dcd_edpt_stall(USB_Type *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + ptr->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); +} + +void usb_dcd_edpt_clear_stall(USB_Type *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + /* data toggle also need to be reset */ + ptr->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << (dir ? 16 : 0); + ptr->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << (dir ? 16 : 0)); +} + +void usb_dcd_edpt_close(USB_Type *ptr, uint8_t ep_addr) +{ + uint8_t const epnum = ep_addr & 0x0f; + uint8_t const dir = (ep_addr & 0x80) >> 7; + + uint32_t primebit = HPM_BITSMASK(1, epnum) + ( dir ? 16 : 0 ); + + /* Flush the endpoint to stop a transfer. */ + do { + /* Set the corresponding bit(s) in the ENDPTFLUSH register */ + ptr->ENDPTFLUSH |= primebit; + + /* Wait until all bits in the ENDPTFLUSH register are cleared. */ + while (0U != (ptr->ENDPTFLUSH & primebit)) {} + /* + * Read the ENDPTSTAT register to ensure that for all endpoints + * commanded to be flushed, that the corresponding bits + * are now cleared. + */ + } while (0U != (ptr->ENDPTSTAT & primebit)); + + /* Disable the endpoint */ + ptr->ENDPTCTRL[epnum] &= ~((ENDPTCTRL_TYPE | ENDPTCTRL_ENABLE | ENDPTCTRL_STALL) << (dir ? 16 : 0)); +} + +void usb_dcd_remote_wakeup(USB_Type *ptr) +{ + (void) ptr; +} + +bool usb_hcd_init(USB_Type *ptr, uint32_t int_mask, uint16_t framelist_size) +{ + uint8_t framelist_size_bf = 0; + + if (framelist_size > USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS || framelist_size == 0) { + return false; + } + + framelist_size_bf = 10 - get_first_set_bit_from_lsb(framelist_size); + + if (framelist_size != (1 << get_first_set_bit_from_lsb(framelist_size))) { + return false; + } + + usb_phy_init(ptr); + + /* Reset controller */ + ptr->USBCMD |= USB_USBCMD_RST_MASK; + while(USB_USBCMD_RST_GET(ptr->USBCMD)) {} + + /* Set mode to host, must be set immediately after reset */ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM_SET(usb_ctrl_mode_host); + + /* Set the endian */ + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + /* Set parallel interface signal */ + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + + /* Set parallel transceiver width */ + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + + /* Not use interrupt threshold. */ + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; + + /* USB INT Register */ + ptr->USBSTS = ptr->USBSTS; + ptr->USBINTR |= int_mask; + + /* USB CMD Register */ + ptr->USBCMD = USB_USBCMD_RS_MASK + | USB_USBCMD_ASE_MASK | USB_USBCMD_PSE_MASK + | USB_USBCMD_FS_2_SET(framelist_size_bf >> 2) + | USB_USBCMD_FS_1_SET(framelist_size_bf); + + /* enable port power */ + ptr->PORTSC1 |= USB_PORTSC1_PP_MASK; + + return true; +} + +void usb_hcd_port_reset(USB_Type *ptr) +{ + if (usb_phy_get_line_state(ptr) == usb_line_state2) { + ptr->PORTSC1 |= USB_PORTSC1_STS_MASK; + } else { + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + } + + ptr->PORTSC1 &= ~USB_PORTSC1_PE_MASK; + ptr->PORTSC1 |= USB_PORTSC1_PR_MASK; + + /* wait until port reset sequence is completed */ + while (USB_PORTSC1_PR_GET(ptr->PORTSC1)) {} +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c new file mode 100644 index 0000000000..17b73938e5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_vad_drv.h" + +void vad_get_default_config(VAD_Type *ptr, vad_config_t *config) +{ + config->enable_buffer = true; + config->enable_pdm_clock_out = true; + config->enable_two_channels = true; + config->capture_delay = 1; + config->pdm_half_div = 3; + config->fifo_threshold = 4; + config->channel_polarity_high[0] = false; + config->channel_polarity_high[1] = true; + config->post_scale = 20; +} + +void vad_init(VAD_Type *ptr, vad_config_t *config) +{ + vad_reset(ptr); + ptr->CTRL = VAD_CTRL_PDM_CLK_HFDIV_SET(config->pdm_half_div) + | VAD_CTRL_PDM_CLK_OE_SET(config->enable_pdm_clock_out) + | VAD_CTRL_MEMBUF_DISABLE_SET(!config->enable_buffer) + | VAD_CTRL_FIFO_THRSH_SET(config->fifo_threshold) + | VAD_CTRL_CAPT_DLY_SET(config->capture_delay) + | VAD_CTRL_CHNUM_SET(config->enable_two_channels) + | VAD_CTRL_CH_POL_SET((config->channel_polarity_high[1] << 1) + | config->channel_polarity_high[0]); + ptr->FILTCTRL = VAD_FILTCTRL_DECRATIO_SET(2) + | VAD_FILTCTRL_IIR_SLOT_EN_SET(0xff); + ptr->CIC_CFG = (ptr->CIC_CFG & ~VAD_CIC_CFG_POST_SCALE_MASK) + | VAD_CIC_CFG_POST_SCALE_SET(config->post_scale); + + vad_enable_fifo(ptr); +} + +void vad_reset(VAD_Type *ptr) +{ + if (vad_is_running(ptr)) { + vad_stop(ptr); + } + vad_software_reset(ptr); +} + diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c new file mode 100644 index 0000000000..581e632a6a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_wdg_drv.h" + +#define TICKS_1K (1024UL) +#define TICKS_1M (1024UL * TICKS_1K) +#define TICKS_1G (1024UL * TICKS_1M) +#define ONE_SECOND_TICKS_IN_NS (1000UL * 1000UL * 1000UL) + +typedef struct { + uint32_t top; + reset_interval_t interval; +} reset_interval_map_t; + +typedef struct { + uint32_t top; + interrupt_interval_t interval; +} interrupt_interval_map_t; + + +static const reset_interval_map_t k_reset_interval_map[reset_interval_out_of_range + 1U] = { + { 128UL, reset_interval_clock_period_mult_128 }, + { 256UL, reset_interval_clock_period_mult_256 }, + { 512UL, reset_interval_clock_period_mult_512 }, + { 1UL * TICKS_1K, reset_interval_clock_period_mult_1k }, + { 2UL * TICKS_1K, reset_interval_clock_period_mult_2k }, + { 4UL * TICKS_1K, reset_interval_clock_period_mult_4k }, + { 8UL * TICKS_1K, reset_interval_clock_period_mult_8k }, + { 16UL * TICKS_1K, reset_interval_clock_period_mult_16k }, + { 0xFFFFFFFFUL, reset_interval_out_of_range }, + }; + +static const interrupt_interval_map_t k_interrupt_interval_map[interrupt_interval_out_of_range + 1U] = { + { 64UL, interrupt_interval_clock_period_multi_64 }, + { 256UL, interrupt_interval_clock_period_multi_256 }, + { 1UL * TICKS_1K, interrupt_interval_clock_period_multi_1k }, + { 2UL * TICKS_1K, interrupt_interval_clock_period_multi_2k }, + { 4UL * TICKS_1K, interrupt_interval_clock_period_multi_4k }, + { 8UL * TICKS_1K, interrupt_interval_clock_period_multi_8k }, + { 16UL * TICKS_1K, interrupt_interval_clock_period_multi_16k }, + { 32UL * TICKS_1K, interrupt_interval_clock_period_multi_32k }, + { 128UL * TICKS_1K, interrupt_interval_clock_period_multi_128k }, + { 512UL * TICKS_1K, interrupt_interval_clock_period_multi_512k }, + { 2UL * TICKS_1M, interrupt_interval_clock_period_multi_2m }, + { 4UL * TICKS_1M, interrupt_interval_clock_period_multi_4m }, + { 8UL * TICKS_1M, interrupt_interval_clock_period_multi_8m }, + { 32UL * TICKS_1M, interrupt_interval_clock_period_multi_32m }, + { 128UL * TICKS_1M, interrupt_interval_clock_period_multi_128m }, + { 512UL * TICKS_1M, interrupt_interval_clock_period_multi_512m }, + { 2UL * TICKS_1G, interrupt_interval_clock_period_multi_2g }, + { 0xFFFFFFFFUL, interrupt_interval_out_of_range } + + }; + +/* See hpm_wdg_drv.h for more details */ +hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF((base == NULL) || (wdg_ctrl == NULL)); + + HPM_BREAK_IF((wdg_ctrl->reset_interval > reset_interval_max) || + (wdg_ctrl->interrupt_interval > interrupt_interval_max) || + (wdg_ctrl->clksrc > wdg_clksrc_pclk)); + + uint32_t rst_time = (uint32_t) wdg_ctrl->reset_interval; + uint32_t int_time = (uint32_t) wdg_ctrl->interrupt_interval; + uint32_t reset_en = wdg_ctrl->reset_enable ? 1UL : 0UL; + uint32_t int_en = wdg_ctrl->interrupt_enable ? 1UL : 0UL; + uint32_t clk_src = (wdg_ctrl->clksrc == wdg_clksrc_pclk) ? 1UL : 0UL; + uint32_t wdg_en = wdg_ctrl->wdg_enable ? 1UL : 0UL; + + uint32_t wdg_ctrl = WDG_CTRL_RSTTIME_SET(rst_time) + | WDG_CTRL_INTTIME_SET(int_time) + | WDG_CTRL_CLKSEL_SET(clk_src) + | WDG_CTRL_RSTEN_SET(reset_en) + | WDG_CTRL_INTEN_SET(int_en) + | WDG_CTRL_EN_SET(wdg_en); + + wdg_write_enable(base); + + base->CTRL = wdg_ctrl; + + status = status_success; + + } while (false); + + return status; +} + +/* See hpm_wdg_drv.h for more details */ +reset_interval_t wdg_convert_reset_interval_from_us(const uint32_t src_freq, const uint32_t reset_us) +{ + reset_interval_t reset_interval = reset_interval_out_of_range; + + uint32_t src_clk_one_tick_in_ns = ONE_SECOND_TICKS_IN_NS / src_freq; + if (src_clk_one_tick_in_ns < 1U) { + src_clk_one_tick_in_ns = 1U; + } + + uint32_t reset_interval_ticks = (reset_us * 1000UL) / src_clk_one_tick_in_ns; + + for (uint32_t i = 0; i < ARRAY_SIZE(k_reset_interval_map); i++) { + if (reset_interval_ticks <= k_reset_interval_map[i].top) { + reset_interval = k_reset_interval_map[i].interval; + break; + } + } + + return reset_interval; +} + +/* See hpm_wdg_drv.h for more details */ +interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_freq, uint32_t interval_us) +{ + interrupt_interval_t interrupt_interval = interrupt_interval_out_of_range; + + uint32_t src_clk_one_tick_in_ns = ONE_SECOND_TICKS_IN_NS / src_freq; + if (src_clk_one_tick_in_ns < 1U) { + src_clk_one_tick_in_ns = 1U; + } + + uint32_t interrupt_interval_ticks = ((uint64_t) interval_us * 1000UL) / src_clk_one_tick_in_ns; + + for (uint32_t i = 0; i < ARRAY_SIZE(k_interrupt_interval_map); i++) { + if (interrupt_interval_ticks <= k_interrupt_interval_map[i].top) { + interrupt_interval = k_interrupt_interval_map[i].interval; + break; + } + } + + return interrupt_interval; +} + + +uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq) +{ + uint32_t time_in_us = 0; + if ((base != NULL) && (src_freq != 0)) { + uint32_t interrupt_interval_in_reg = WDG_CTRL_INTTIME_GET(base->CTRL); + + double tick_in_ns = 1.0 * TICKS_1G / src_freq; + uint64_t total_interval_in_ns = (uint64_t)(tick_in_ns * k_interrupt_interval_map[interrupt_interval_in_reg].top); + + time_in_us = (uint32_t)(total_interval_in_ns / 1000UL); + } + + return time_in_us; +} + +uint32_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq) +{ + uint32_t time_in_us = 0; + if ((base != NULL) && (src_freq != 0)) { + uint32_t reset_interval_in_reg = WDG_CTRL_RSTTIME_GET(base->CTRL); + double tick_in_ns = 1.0 * TICKS_1G / src_freq; + uint64_t total_interval_in_ns = (uint64_t)(tick_in_ns * k_reset_interval_map[reset_interval_in_reg].top); + + time_in_us = (uint32_t)(total_interval_in_ns / 1000UL) + wdg_get_interrupt_interval_in_us(base, src_freq); + } + + return time_in_us; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/env.sh b/bsp/hpmicro/libraries/hpm_sdk/env.sh new file mode 100644 index 0000000000..6fe994e10b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/env.sh @@ -0,0 +1,27 @@ +# +# Copyright (c) 2021 hpmicro +# +# SPDX-License-Identifier: BSD-3-Clause +# + +if [ "X$MSYSTEM" "==" "X" ]; then + if [ "X$name" "==" "Xenv.sh" ]; then + echo "Please source this file, rather than executing it." + exit + fi + env_name=$0 +else + env_name=$1 +fi + +script=$(cd -P -- "$(dirname -- "$env_name")" && printf '%s\n' "$(pwd -P)/$(basename -- "$env_name")") +if [ "X$MSYSTEM" "==" "X" ]; then + export HPM_SDK_BASE=$(dirname "$script") +else + export HPM_SDK_BASE=$script +fi + +echo $HPM_SDK_BASE + +export OPENOCD_SCRIPTS=${HPM_SDK_BASE}/boards/openocd + diff --git a/bsp/hpmicro/libraries/hpm_sdk/index.md b/bsp/hpmicro/libraries/hpm_sdk/index.md new file mode 100644 index 0000000000..5d9467a976 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/index.md @@ -0,0 +1,15 @@ +hpm sdk +=================================== +:::{eval-rst} +.. toctree:: + :maxdepth: 1 + :caption: Contents + :name: HPM README Document + + CHANGELOG + README + boards/index + samples/index + doc/src/sdk_doc/README + +::: \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/index_zh.md b/bsp/hpmicro/libraries/hpm_sdk/index_zh.md new file mode 100644 index 0000000000..c9dad49754 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/index_zh.md @@ -0,0 +1,15 @@ +hpm sdk +=================================== + +:::{eval-rst} +.. toctree:: + :maxdepth: 1 + :caption: 目录 + :name: HPM README Document + + CHANGELOG + README_zh + boards/index_zh + samples/index_zh + doc/src/sdk_doc/README_zh +::: \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml new file mode 100644 index 0000000000..baea1d60a1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml @@ -0,0 +1,103475 @@ + + + HPMICRO + HPM6360 + HPM6300 + 1.0 + HPM6300 device + + /* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + 8 + 32 + + 32 + 0x0 + 0xFFFFFFFF + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x800 + registers + + + + DI_GPIOA_VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOA_SET + GPIO input set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOA_CLEAR + GPIO input clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOA_TOGGLE + GPIO input toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_VALUE + GPIOB input + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_SET + GPIO input set + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_CLEAR + GPIO input clear + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_TOGGLE + GPIO input toggle + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_VALUE + GPIOC input + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_SET + GPIO input set + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_CLEAR + GPIO input clear + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_TOGGLE + GPIO input toggle + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_VALUE + GPIOX input + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_SET + GPIO input set + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_CLEAR + GPIO input clear + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_TOGGLE + GPIO input toggle + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_VALUE + GPIOY input + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_SET + GPIO input set + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_CLEAR + GPIO input clear + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_TOGGLE + GPIO input toggle + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_VALUE + GPIOZ input + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_SET + GPIO input set + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_CLEAR + GPIO input clear + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_TOGGLE + GPIO input toggle + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DO_GPIOA_VALUE + GPIO output value + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOA_SET + GPIO output set + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOA_CLEAR + GPIO output clear + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOA_TOGGLE + GPIO output toggle + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_VALUE + GPIOB output + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_SET + GPIO output set + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_CLEAR + GPIO output clear + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_TOGGLE + GPIO output toggle + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_VALUE + GPIOC output + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_SET + GPIO output set + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_CLEAR + GPIO output clear + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_TOGGLE + GPIO output toggle + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_VALUE + GPIOX output + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_SET + GPIO output set + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_CLEAR + GPIO output clear + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_TOGGLE + GPIO output toggle + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_VALUE + GPIOY output + 0x1e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_SET + GPIO output set + 0x1e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_CLEAR + GPIO output clear + 0x1e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_TOGGLE + GPIO output toggle + 0x1ec + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_VALUE + GPIOZ output + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_SET + GPIO output set + 0x1f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_CLEAR + GPIO output clear + 0x1f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_TOGGLE + GPIO output toggle + 0x1fc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + OE_GPIOA_VALUE + GPIO direction value + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOA_SET + GPIO direction set + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOA_CLEAR + GPIO direction clear + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOA_TOGGLE + GPIO direction toggle + 0x20c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_VALUE + GPIOB direction + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_SET + GPIO direction set + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_CLEAR + GPIO direction clear + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_TOGGLE + GPIO direction toggle + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_VALUE + GPIOC direction + 0x220 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_SET + GPIO direction set + 0x224 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_CLEAR + GPIO direction clear + 0x228 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_TOGGLE + GPIO direction toggle + 0x22c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_VALUE + GPIOX direction + 0x2d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_SET + GPIO direction set + 0x2d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_CLEAR + GPIO direction clear + 0x2d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_TOGGLE + GPIO direction toggle + 0x2dc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_VALUE + GPIOY direction + 0x2e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_SET + GPIO direction set + 0x2e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_CLEAR + GPIO direction clear + 0x2e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_TOGGLE + GPIO direction toggle + 0x2ec + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_VALUE + GPIOZ direction + 0x2f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_SET + GPIO direction set + 0x2f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_CLEAR + GPIO direction clear + 0x2f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_TOGGLE + GPIO direction toggle + 0x2fc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + IF_GPIOA_VALUE + GPIO interrupt flag value + 0x300 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOA_SET + GPIO interrupt flag set + 0x304 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOA_CLEAR + GPIO interrupt flag clear + 0x308 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOA_TOGGLE + GPIO interrupt flag toggle + 0x30c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_VALUE + GPIOB interrupt flag + 0x310 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_SET + GPIO interrupt flag set + 0x314 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_CLEAR + GPIO interrupt flag clear + 0x318 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_TOGGLE + GPIO interrupt flag toggle + 0x31c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_VALUE + GPIOC interrupt flag + 0x320 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_SET + GPIO interrupt flag set + 0x324 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_CLEAR + GPIO interrupt flag clear + 0x328 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_TOGGLE + GPIO interrupt flag toggle + 0x32c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_VALUE + GPIOX interrupt flag + 0x3d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_SET + GPIO interrupt flag set + 0x3d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_CLEAR + GPIO interrupt flag clear + 0x3d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_TOGGLE + GPIO interrupt flag toggle + 0x3dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_VALUE + GPIOY interrupt flag + 0x3e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_SET + GPIO interrupt flag set + 0x3e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_CLEAR + GPIO interrupt flag clear + 0x3e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_TOGGLE + GPIO interrupt flag toggle + 0x3ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_VALUE + GPIOZ interrupt flag + 0x3f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_SET + GPIO interrupt flag set + 0x3f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_CLEAR + GPIO interrupt flag clear + 0x3f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_TOGGLE + GPIO interrupt flag toggle + 0x3fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IE_GPIOA_VALUE + GPIO interrupt enable value + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOA_SET + GPIO interrupt enable set + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOA_CLEAR + GPIO interrupt enable clear + 0x408 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOA_TOGGLE + GPIO interrupt enable toggle + 0x40c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_VALUE + GPIOB interrupt enable + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_SET + GPIO interrupt enable set + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_CLEAR + GPIO interrupt enable clear + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_TOGGLE + GPIO interrupt enable toggle + 0x41c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_VALUE + GPIOC interrupt enable + 0x420 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_SET + GPIO interrupt enable set + 0x424 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_CLEAR + GPIO interrupt enable clear + 0x428 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_TOGGLE + GPIO interrupt enable toggle + 0x42c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_VALUE + GPIOX interrupt enable + 0x4d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_SET + GPIO interrupt enable set + 0x4d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_CLEAR + GPIO interrupt enable clear + 0x4d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_TOGGLE + GPIO interrupt enable toggle + 0x4dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_VALUE + GPIOY interrupt enable + 0x4e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_SET + GPIO interrupt enable set + 0x4e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_CLEAR + GPIO interrupt enable clear + 0x4e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_TOGGLE + GPIO interrupt enable toggle + 0x4ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_VALUE + GPIOZ interrupt enable + 0x4f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_SET + GPIO interrupt enable set + 0x4f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_CLEAR + GPIO interrupt enable clear + 0x4f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_TOGGLE + GPIO interrupt enable toggle + 0x4fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + PL_GPIOA_VALUE + GPIO interrupt polarity value + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOA_SET + GPIO interrupt polarity set + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOA_CLEAR + GPIO interrupt polarity clear + 0x508 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOA_TOGGLE + GPIO interrupt polarity toggle + 0x50c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_VALUE + GPIOB interrupt polarity + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_SET + GPIO interrupt polarity set + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_CLEAR + GPIO interrupt polarity clear + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_TOGGLE + GPIO interrupt polarity toggle + 0x51c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_VALUE + GPIOC interrupt polarity + 0x520 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_SET + GPIO interrupt polarity set + 0x524 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_CLEAR + GPIO interrupt polarity clear + 0x528 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_TOGGLE + GPIO interrupt polarity toggle + 0x52c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_VALUE + GPIOX interrupt polarity + 0x5d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_SET + GPIO interrupt polarity set + 0x5d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_CLEAR + GPIO interrupt polarity clear + 0x5d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_TOGGLE + GPIO interrupt polarity toggle + 0x5dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_VALUE + GPIOY interrupt polarity + 0x5e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_SET + GPIO interrupt polarity set + 0x5e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_CLEAR + GPIO interrupt polarity clear + 0x5e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_TOGGLE + GPIO interrupt polarity toggle + 0x5ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_VALUE + GPIOZ interrupt polarity + 0x5f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_SET + GPIO interrupt polarity set + 0x5f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_CLEAR + GPIO interrupt polarity clear + 0x5f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_TOGGLE + GPIO interrupt polarity toggle + 0x5fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TP_GPIOA_VALUE + GPIO interrupt type value + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOA_SET + GPIO interrupt type set + 0x604 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOA_CLEAR + GPIO interrupt type clear + 0x608 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOA_TOGGLE + GPIO interrupt type toggle + 0x60c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_VALUE + GPIOB interrupt type + 0x610 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_SET + GPIO interrupt type set + 0x614 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_CLEAR + GPIO interrupt type clear + 0x618 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_TOGGLE + GPIO interrupt type toggle + 0x61c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_VALUE + GPIOC interrupt type + 0x620 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_SET + GPIO interrupt type set + 0x624 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_CLEAR + GPIO interrupt type clear + 0x628 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_TOGGLE + GPIO interrupt type toggle + 0x62c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_VALUE + GPIOX interrupt type + 0x6d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_SET + GPIO interrupt type set + 0x6d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_CLEAR + GPIO interrupt type clear + 0x6d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_TOGGLE + GPIO interrupt type toggle + 0x6dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_VALUE + GPIOY interrupt type + 0x6e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_SET + GPIO interrupt type set + 0x6e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_CLEAR + GPIO interrupt type clear + 0x6e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_TOGGLE + GPIO interrupt type toggle + 0x6ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_VALUE + GPIOZ interrupt type + 0x6f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_SET + GPIO interrupt type set + 0x6f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_CLEAR + GPIO interrupt type clear + 0x6f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_TOGGLE + GPIO interrupt type toggle + 0x6fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + AS_GPIOA_VALUE + GPIO interrupt asynchronous value + 0x700 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOA_SET + GPIO interrupt asynchronous set + 0x704 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOA_CLEAR + GPIO interrupt asynchronous clear + 0x708 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOA_TOGGLE + GPIO interrupt asynchronous toggle + 0x70c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_VALUE + GPIOB interrupt asynchronous + 0x710 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_SET + GPIO interrupt asynchronous set + 0x714 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_CLEAR + GPIO interrupt asynchronous clear + 0x718 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_TOGGLE + GPIO interrupt asynchronous toggle + 0x71c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_VALUE + GPIOC interrupt asynchronous + 0x720 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_SET + GPIO interrupt asynchronous set + 0x724 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_CLEAR + GPIO interrupt asynchronous clear + 0x728 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_TOGGLE + GPIO interrupt asynchronous toggle + 0x72c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_VALUE + GPIOX interrupt asynchronous + 0x7d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_SET + GPIO interrupt asynchronous set + 0x7d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_CLEAR + GPIO interrupt asynchronous clear + 0x7d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_TOGGLE + GPIO interrupt asynchronous toggle + 0x7dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_VALUE + GPIOY interrupt asynchronous + 0x7e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_SET + GPIO interrupt asynchronous set + 0x7e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_CLEAR + GPIO interrupt asynchronous clear + 0x7e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_TOGGLE + GPIO interrupt asynchronous toggle + 0x7ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_VALUE + GPIOZ interrupt asynchronous + 0x7f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_SET + GPIO interrupt asynchronous set + 0x7f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_CLEAR + GPIO interrupt asynchronous clear + 0x7f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_TOGGLE + GPIO interrupt asynchronous toggle + 0x7fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf0000000 + + + PGPIO + PGPIO + GPIO + 0xf40dc000 + + + BGPIO + BGPIO + GPIO + 0xf5014000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x202000 + registers + + + + FEATURE + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + PRIORITY_PRIORITY1 + Source priority + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY2 + Source priority + 0x8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY3 + Source priority + 0xc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY4 + Source priority + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY5 + Source priority + 0x14 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY6 + Source priority + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY7 + Source priority + 0x1c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY8 + Source priority + 0x20 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY9 + Source priority + 0x24 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY10 + Source priority + 0x28 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY11 + Source priority + 0x2c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY12 + Source priority + 0x30 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY13 + Source priority + 0x34 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY14 + Source priority + 0x38 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY15 + Source priority + 0x3c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY16 + Source priority + 0x40 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY17 + Source priority + 0x44 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY18 + Source priority + 0x48 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY19 + Source priority + 0x4c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY20 + Source priority + 0x50 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY21 + Source priority + 0x54 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY22 + Source priority + 0x58 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY23 + Source priority + 0x5c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY24 + Source priority + 0x60 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY25 + Source priority + 0x64 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY26 + Source priority + 0x68 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY27 + Source priority + 0x6c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY28 + Source priority + 0x70 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY29 + Source priority + 0x74 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY30 + Source priority + 0x78 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY31 + Source priority + 0x7c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY32 + Source priority + 0x80 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY33 + Source priority + 0x84 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY34 + Source priority + 0x88 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY35 + Source priority + 0x8c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY36 + Source priority + 0x90 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY37 + Source priority + 0x94 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY38 + Source priority + 0x98 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY39 + Source priority + 0x9c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY40 + Source priority + 0xa0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY41 + Source priority + 0xa4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY42 + Source priority + 0xa8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY43 + Source priority + 0xac + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY44 + Source priority + 0xb0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY45 + Source priority + 0xb4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY46 + Source priority + 0xb8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY47 + Source priority + 0xbc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY48 + Source priority + 0xc0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY49 + Source priority + 0xc4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY50 + Source priority + 0xc8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY51 + Source priority + 0xcc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY52 + Source priority + 0xd0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY53 + Source priority + 0xd4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY54 + Source priority + 0xd8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY55 + Source priority + 0xdc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY56 + Source priority + 0xe0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY57 + Source priority + 0xe4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY58 + Source priority + 0xe8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY59 + Source priority + 0xec + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY60 + Source priority + 0xf0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY61 + Source priority + 0xf4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY62 + Source priority + 0xf8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY63 + Source priority + 0xfc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY64 + Source priority + 0x100 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY65 + Source priority + 0x104 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY66 + Source priority + 0x108 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY67 + Source priority + 0x10c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY68 + Source priority + 0x110 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY69 + Source priority + 0x114 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY70 + Source priority + 0x118 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY71 + Source priority + 0x11c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY72 + Source priority + 0x120 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY73 + Source priority + 0x124 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY74 + Source priority + 0x128 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY75 + Source priority + 0x12c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY76 + Source priority + 0x130 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY77 + Source priority + 0x134 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY78 + Source priority + 0x138 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY79 + Source priority + 0x13c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY80 + Source priority + 0x140 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY81 + Source priority + 0x144 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY82 + Source priority + 0x148 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY83 + Source priority + 0x14c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY84 + Source priority + 0x150 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY85 + Source priority + 0x154 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY86 + Source priority + 0x158 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY87 + Source priority + 0x15c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY88 + Source priority + 0x160 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY89 + Source priority + 0x164 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY90 + Source priority + 0x168 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY91 + Source priority + 0x16c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY92 + Source priority + 0x170 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY93 + Source priority + 0x174 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY94 + Source priority + 0x178 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY95 + Source priority + 0x17c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY96 + Source priority + 0x180 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY97 + Source priority + 0x184 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY98 + Source priority + 0x188 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY99 + Source priority + 0x18c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY100 + Source priority + 0x190 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY101 + Source priority + 0x194 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY102 + Source priority + 0x198 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY103 + Source priority + 0x19c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY104 + Source priority + 0x1a0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY105 + Source priority + 0x1a4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY106 + Source priority + 0x1a8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY107 + Source priority + 0x1ac + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY108 + Source priority + 0x1b0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY109 + Source priority + 0x1b4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY110 + Source priority + 0x1b8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY111 + Source priority + 0x1bc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY112 + Source priority + 0x1c0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY113 + Source priority + 0x1c4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY114 + Source priority + 0x1c8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY115 + Source priority + 0x1cc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY116 + Source priority + 0x1d0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY117 + Source priority + 0x1d4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY118 + Source priority + 0x1d8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY119 + Source priority + 0x1dc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY120 + Source priority + 0x1e0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY121 + Source priority + 0x1e4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY122 + Source priority + 0x1e8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY123 + Source priority + 0x1ec + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY124 + Source priority + 0x1f0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY125 + Source priority + 0x1f4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY126 + Source priority + 0x1f8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY127 + Source priority + 0x1fc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PENDING_PENDING0 + Pending status + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + PENDING_PENDING1 + Pending status + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + PENDING_PENDING2 + Pending status + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + PENDING_PENDING3 + Pending status + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TRIGGER_TRIGGER0 + Trigger type + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + TRIGGER_TRIGGER1 + Trigger type + 0x1084 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + TRIGGER_TRIGGER2 + Trigger type + 0x1088 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + TRIGGER_TRIGGER3 + Trigger type + 0x108c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + TARGETINT_TARGET0_INTEN0 + machine interrupt enable + 0x2000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET0_INTEN1 + machine interrupt enable + 0x2004 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET0_INTEN2 + machine interrupt enable + 0x2008 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET0_INTEN3 + machine interrupt enable + 0x200c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN0 + supervisor interrupt enable + 0x2080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN1 + supervisor interrupt enable + 0x2084 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN2 + supervisor interrupt enable + 0x2088 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN3 + supervisor interrupt enable + 0x208c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET0_THRESHOLD + Target0 priority threshold + 0x200000 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET0_CLAIM + Target claim and complete + 0x200004 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + TARGETCONFIG_TARGET0_PPS + Preempted priority stack + 0x200400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET1_THRESHOLD + Target1 priority threshold + 0x201000 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET1_CLAIM + Target claim and complete + 0x201004 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + TARGETCONFIG_TARGET1_PPS + Preempted priority stack + 0x201400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + GPIOM + GPIOM + GPIOM + 0xf0008000 + + 0x0 + 0x800 + registers + + + + ASSIGN_GPIOA_PIN_PIN00 + GPIO mananger + 0x0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN01 + GPIO mananger + 0x4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN02 + GPIO mananger + 0x8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN03 + GPIO mananger + 0xc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN04 + GPIO mananger + 0x10 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN05 + GPIO mananger + 0x14 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN06 + GPIO mananger + 0x18 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN07 + GPIO mananger + 0x1c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN08 + GPIO mananger + 0x20 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN09 + GPIO mananger + 0x24 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN10 + GPIO mananger + 0x28 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN11 + GPIO mananger + 0x2c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN12 + GPIO mananger + 0x30 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN13 + GPIO mananger + 0x34 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN14 + GPIO mananger + 0x38 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN15 + GPIO mananger + 0x3c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN16 + GPIO mananger + 0x40 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN17 + GPIO mananger + 0x44 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN18 + GPIO mananger + 0x48 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN19 + GPIO mananger + 0x4c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN20 + GPIO mananger + 0x50 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN21 + GPIO mananger + 0x54 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN22 + GPIO mananger + 0x58 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN23 + GPIO mananger + 0x5c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN24 + GPIO mananger + 0x60 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN25 + GPIO mananger + 0x64 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN26 + GPIO mananger + 0x68 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN27 + GPIO mananger + 0x6c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN28 + GPIO mananger + 0x70 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN29 + GPIO mananger + 0x74 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN30 + GPIO mananger + 0x78 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN31 + GPIO mananger + 0x7c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN00 + GPIO mananger + 0x80 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN01 + GPIO mananger + 0x84 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN02 + GPIO mananger + 0x88 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN03 + GPIO mananger + 0x8c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN04 + GPIO mananger + 0x90 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN05 + GPIO mananger + 0x94 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN06 + GPIO mananger + 0x98 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN07 + GPIO mananger + 0x9c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN08 + GPIO mananger + 0xa0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN09 + GPIO mananger + 0xa4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN10 + GPIO mananger + 0xa8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN11 + GPIO mananger + 0xac + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN12 + GPIO mananger + 0xb0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN13 + GPIO mananger + 0xb4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN14 + GPIO mananger + 0xb8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN15 + GPIO mananger + 0xbc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN16 + GPIO mananger + 0xc0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN17 + GPIO mananger + 0xc4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN18 + GPIO mananger + 0xc8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN19 + GPIO mananger + 0xcc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN20 + GPIO mananger + 0xd0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN21 + GPIO mananger + 0xd4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN22 + GPIO mananger + 0xd8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN23 + GPIO mananger + 0xdc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN24 + GPIO mananger + 0xe0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN25 + GPIO mananger + 0xe4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN26 + GPIO mananger + 0xe8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN27 + GPIO mananger + 0xec + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN28 + GPIO mananger + 0xf0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN29 + GPIO mananger + 0xf4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN30 + GPIO mananger + 0xf8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN31 + GPIO mananger + 0xfc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN00 + GPIO mananger + 0x100 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN01 + GPIO mananger + 0x104 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN02 + GPIO mananger + 0x108 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN03 + GPIO mananger + 0x10c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN04 + GPIO mananger + 0x110 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN05 + GPIO mananger + 0x114 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN06 + GPIO mananger + 0x118 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN07 + GPIO mananger + 0x11c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN08 + GPIO mananger + 0x120 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN09 + GPIO mananger + 0x124 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN10 + GPIO mananger + 0x128 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN11 + GPIO mananger + 0x12c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN12 + GPIO mananger + 0x130 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN13 + GPIO mananger + 0x134 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN14 + GPIO mananger + 0x138 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN15 + GPIO mananger + 0x13c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN16 + GPIO mananger + 0x140 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN17 + GPIO mananger + 0x144 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN18 + GPIO mananger + 0x148 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN19 + GPIO mananger + 0x14c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN20 + GPIO mananger + 0x150 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN21 + GPIO mananger + 0x154 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN22 + GPIO mananger + 0x158 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN23 + GPIO mananger + 0x15c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN24 + GPIO mananger + 0x160 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN25 + GPIO mananger + 0x164 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN26 + GPIO mananger + 0x168 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN27 + GPIO mananger + 0x16c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN28 + GPIO mananger + 0x170 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN29 + GPIO mananger + 0x174 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN30 + GPIO mananger + 0x178 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN31 + GPIO mananger + 0x17c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN00 + GPIO mananger + 0x680 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN01 + GPIO mananger + 0x684 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN02 + GPIO mananger + 0x688 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN03 + GPIO mananger + 0x68c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN04 + GPIO mananger + 0x690 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN05 + GPIO mananger + 0x694 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN06 + GPIO mananger + 0x698 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN07 + GPIO mananger + 0x69c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN08 + GPIO mananger + 0x6a0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN09 + GPIO mananger + 0x6a4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN10 + GPIO mananger + 0x6a8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN11 + GPIO mananger + 0x6ac + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN12 + GPIO mananger + 0x6b0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN13 + GPIO mananger + 0x6b4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN14 + GPIO mananger + 0x6b8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN15 + GPIO mananger + 0x6bc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN16 + GPIO mananger + 0x6c0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN17 + GPIO mananger + 0x6c4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN18 + GPIO mananger + 0x6c8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN19 + GPIO mananger + 0x6cc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN20 + GPIO mananger + 0x6d0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN21 + GPIO mananger + 0x6d4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN22 + GPIO mananger + 0x6d8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN23 + GPIO mananger + 0x6dc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN24 + GPIO mananger + 0x6e0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN25 + GPIO mananger + 0x6e4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN26 + GPIO mananger + 0x6e8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN27 + GPIO mananger + 0x6ec + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN28 + GPIO mananger + 0x6f0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN29 + GPIO mananger + 0x6f4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN30 + GPIO mananger + 0x6f8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN31 + GPIO mananger + 0x6fc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN00 + GPIO mananger + 0x700 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN01 + GPIO mananger + 0x704 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN02 + GPIO mananger + 0x708 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN03 + GPIO mananger + 0x70c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN04 + GPIO mananger + 0x710 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN05 + GPIO mananger + 0x714 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN06 + GPIO mananger + 0x718 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN07 + GPIO mananger + 0x71c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN08 + GPIO mananger + 0x720 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN09 + GPIO mananger + 0x724 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN10 + GPIO mananger + 0x728 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN11 + GPIO mananger + 0x72c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN12 + GPIO mananger + 0x730 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN13 + GPIO mananger + 0x734 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN14 + GPIO mananger + 0x738 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN15 + GPIO mananger + 0x73c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN16 + GPIO mananger + 0x740 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN17 + GPIO mananger + 0x744 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN18 + GPIO mananger + 0x748 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN19 + GPIO mananger + 0x74c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN20 + GPIO mananger + 0x750 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN21 + GPIO mananger + 0x754 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN22 + GPIO mananger + 0x758 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN23 + GPIO mananger + 0x75c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN24 + GPIO mananger + 0x760 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN25 + GPIO mananger + 0x764 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN26 + GPIO mananger + 0x768 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN27 + GPIO mananger + 0x76c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN28 + GPIO mananger + 0x770 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN29 + GPIO mananger + 0x774 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN30 + GPIO mananger + 0x778 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN31 + GPIO mananger + 0x77c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN00 + GPIO mananger + 0x780 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN01 + GPIO mananger + 0x784 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN02 + GPIO mananger + 0x788 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN03 + GPIO mananger + 0x78c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN04 + GPIO mananger + 0x790 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN05 + GPIO mananger + 0x794 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN06 + GPIO mananger + 0x798 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN07 + GPIO mananger + 0x79c + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN08 + GPIO mananger + 0x7a0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN09 + GPIO mananger + 0x7a4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN10 + GPIO mananger + 0x7a8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN11 + GPIO mananger + 0x7ac + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN12 + GPIO mananger + 0x7b0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN13 + GPIO mananger + 0x7b4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN14 + GPIO mananger + 0x7b8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN15 + GPIO mananger + 0x7bc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN16 + GPIO mananger + 0x7c0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN17 + GPIO mananger + 0x7c4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN18 + GPIO mananger + 0x7c8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN19 + GPIO mananger + 0x7cc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN20 + GPIO mananger + 0x7d0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN21 + GPIO mananger + 0x7d4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN22 + GPIO mananger + 0x7d8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN23 + GPIO mananger + 0x7dc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN24 + GPIO mananger + 0x7e0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN25 + GPIO mananger + 0x7e4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN26 + GPIO mananger + 0x7e8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN27 + GPIO mananger + 0x7ec + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN28 + GPIO mananger + 0x7f0 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN29 + GPIO mananger + 0x7f4 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN30 + GPIO mananger + 0x7f8 + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN31 + GPIO mananger + 0x7fc + 32 + 0x00000000 + 0x80000301 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 2 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: cpu0 fastgpio + 0 + 1 + read-write + + + + + + + ADC0 + ADC0 + ADC16 + 0xf0010000 + + 0x0 + 0x1464 + registers + + + + CONFIG_TRG0A + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG0B + No description avaiable + 0x4 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG0C + No description avaiable + 0x8 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1A + No description avaiable + 0xc + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1B + No description avaiable + 0x10 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1C + No description avaiable + 0x14 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2A + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2B + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2C + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3A + No description avaiable + 0x24 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3B + No description avaiable + 0x28 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3C + No description avaiable + 0x2c + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + TRG_DMA_ADDR + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + BUS_RESULT_CHN0 + No description avaiable + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN1 + No description avaiable + 0x404 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN2 + No description avaiable + 0x408 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN3 + No description avaiable + 0x40c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN4 + No description avaiable + 0x410 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN5 + No description avaiable + 0x414 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN6 + No description avaiable + 0x418 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN7 + No description avaiable + 0x41c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN8 + No description avaiable + 0x420 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN9 + No description avaiable + 0x424 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN10 + No description avaiable + 0x428 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN11 + No description avaiable + 0x42c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN12 + No description avaiable + 0x430 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN13 + No description avaiable + 0x434 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN14 + No description avaiable + 0x438 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN15 + No description avaiable + 0x43c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUF_CFG0 + No description avaiable + 0x500 + 32 + 0x00000000 + 0x00000001 + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + SEQ_CFG0 + No description avaiable + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + SEQ_DMA_ADDR + No description avaiable + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + SEQ_WR_ADDR + No description avaiable + 0x808 + 32 + 0x00000000 + 0x00000FFF + + + SEQ_WR_POINTER + HW update this field after each dma write, it indicate the next dma write pointer. +dma write address is (tar_addr+seq_wr_pointer)*4 + 0 + 12 + read-only + + + + + SEQ_DMA_CFG + No description avaiable + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + SEQ_QUE_CFG0 + No description avaiable + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG1 + No description avaiable + 0x814 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG2 + No description avaiable + 0x818 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG3 + No description avaiable + 0x81c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG4 + No description avaiable + 0x820 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG5 + No description avaiable + 0x824 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG6 + No description avaiable + 0x828 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG7 + No description avaiable + 0x82c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG8 + No description avaiable + 0x830 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG9 + No description avaiable + 0x834 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG10 + No description avaiable + 0x838 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG11 + No description avaiable + 0x83c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG12 + No description avaiable + 0x840 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG13 + No description avaiable + 0x844 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG14 + No description avaiable + 0x848 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG15 + No description avaiable + 0x84c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + PRD_CFG_CHN0_PRD_CFG + No description avaiable + 0xc00 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN0_PRD_THSHD_CFG + No description avaiable + 0xc04 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN0_PRD_RESULT + No description avaiable + 0xc08 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN1_PRD_CFG + No description avaiable + 0xc10 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN1_PRD_THSHD_CFG + No description avaiable + 0xc14 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN1_PRD_RESULT + No description avaiable + 0xc18 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN2_PRD_CFG + No description avaiable + 0xc20 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN2_PRD_THSHD_CFG + No description avaiable + 0xc24 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN2_PRD_RESULT + No description avaiable + 0xc28 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN3_PRD_CFG + No description avaiable + 0xc30 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN3_PRD_THSHD_CFG + No description avaiable + 0xc34 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN3_PRD_RESULT + No description avaiable + 0xc38 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN4_PRD_CFG + No description avaiable + 0xc40 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN4_PRD_THSHD_CFG + No description avaiable + 0xc44 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN4_PRD_RESULT + No description avaiable + 0xc48 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN5_PRD_CFG + No description avaiable + 0xc50 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN5_PRD_THSHD_CFG + No description avaiable + 0xc54 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN5_PRD_RESULT + No description avaiable + 0xc58 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN6_PRD_CFG + No description avaiable + 0xc60 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN6_PRD_THSHD_CFG + No description avaiable + 0xc64 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN6_PRD_RESULT + No description avaiable + 0xc68 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN7_PRD_CFG + No description avaiable + 0xc70 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN7_PRD_THSHD_CFG + No description avaiable + 0xc74 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN7_PRD_RESULT + No description avaiable + 0xc78 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN8_PRD_CFG + No description avaiable + 0xc80 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN8_PRD_THSHD_CFG + No description avaiable + 0xc84 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN8_PRD_RESULT + No description avaiable + 0xc88 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN9_PRD_CFG + No description avaiable + 0xc90 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN9_PRD_THSHD_CFG + No description avaiable + 0xc94 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN9_PRD_RESULT + No description avaiable + 0xc98 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN10_PRD_CFG + No description avaiable + 0xca0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN10_PRD_THSHD_CFG + No description avaiable + 0xca4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN10_PRD_RESULT + No description avaiable + 0xca8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN11_PRD_CFG + No description avaiable + 0xcb0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN11_PRD_THSHD_CFG + No description avaiable + 0xcb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN11_PRD_RESULT + No description avaiable + 0xcb8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN12_PRD_CFG + No description avaiable + 0xcc0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN12_PRD_THSHD_CFG + No description avaiable + 0xcc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN12_PRD_RESULT + No description avaiable + 0xcc8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN13_PRD_CFG + No description avaiable + 0xcd0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN13_PRD_THSHD_CFG + No description avaiable + 0xcd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN13_PRD_RESULT + No description avaiable + 0xcd8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN14_PRD_CFG + No description avaiable + 0xce0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN14_PRD_THSHD_CFG + No description avaiable + 0xce4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN14_PRD_RESULT + No description avaiable + 0xce8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN15_PRD_CFG + No description avaiable + 0xcf0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN15_PRD_THSHD_CFG + No description avaiable + 0xcf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN15_PRD_RESULT + No description avaiable + 0xcf8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + SAMPLE_CFG_CHN0 + No description avaiable + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN1 + No description avaiable + 0x1004 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN2 + No description avaiable + 0x1008 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN3 + No description avaiable + 0x100c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN4 + No description avaiable + 0x1010 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN5 + No description avaiable + 0x1014 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN6 + No description avaiable + 0x1018 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN7 + No description avaiable + 0x101c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN8 + No description avaiable + 0x1020 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN9 + No description avaiable + 0x1024 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN10 + No description avaiable + 0x1028 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN11 + No description avaiable + 0x102c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN12 + No description avaiable + 0x1030 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN13 + No description avaiable + 0x1034 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN14 + No description avaiable + 0x1038 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN15 + No description avaiable + 0x103c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + CONV_CFG1 + No description avaiable + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); +user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. +set to 3 can genenerate 50MHz adc_clk at 200MHz bus_clk. + 0 + 4 + read-write + + + + + ADC_CFG0 + No description avaiable + 0x1108 + 32 + 0x00000000 + 0xAFFFF001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + CONVERT_DURATION + for trigger queue, from trg_sample_req to trg_convert_req + 12 + 16 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + INT_STS + No description avaiable + 0x1110 + 32 + 0x00000000 + 0xFFE03FFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 14 + read-write + + + + + INT_EN + No description avaiable + 0x1114 + 32 + 0x00000000 + 0xFFE03FFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 14 + read-write + + + + + ANA_CTRL0 + No description avaiable + 0x1200 + 32 + 0x00000000 + 0x00001004 + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ANA_STATUS + No description avaiable + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + ADC16_PARAMS_ADC16_PARA00 + No description avaiable + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA01 + No description avaiable + 0x1402 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA02 + No description avaiable + 0x1404 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA03 + No description avaiable + 0x1406 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA04 + No description avaiable + 0x1408 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA05 + No description avaiable + 0x140a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA06 + No description avaiable + 0x140c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA07 + No description avaiable + 0x140e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA08 + No description avaiable + 0x1410 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA09 + No description avaiable + 0x1412 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA10 + No description avaiable + 0x1414 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA11 + No description avaiable + 0x1416 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA12 + No description avaiable + 0x1418 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA13 + No description avaiable + 0x141a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA14 + No description avaiable + 0x141c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA15 + No description avaiable + 0x141e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA16 + No description avaiable + 0x1420 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA17 + No description avaiable + 0x1422 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA18 + No description avaiable + 0x1424 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA19 + No description avaiable + 0x1426 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA20 + No description avaiable + 0x1428 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA21 + No description avaiable + 0x142a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA22 + No description avaiable + 0x142c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA23 + No description avaiable + 0x142e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA24 + No description avaiable + 0x1430 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA25 + No description avaiable + 0x1432 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA26 + No description avaiable + 0x1434 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA27 + No description avaiable + 0x1436 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA28 + No description avaiable + 0x1438 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA29 + No description avaiable + 0x143a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA30 + No description avaiable + 0x143c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA31 + No description avaiable + 0x143e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA32 + No description avaiable + 0x1440 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA33 + No description avaiable + 0x1442 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_CONFIG0 + No description avaiable + 0x1444 + 32 + 0x00000000 + 0x03F07FFF + + + TEMPSNS_EN + set to enable temp senser + 25 + 1 + read-write + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + convertion parameter + 0 + 14 + read-write + + + + + ADC16_CONFIG1 + No description avaiable + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number). + 8 + 5 + read-write + + + + + + + ADC1 + ADC1 + ADC16 + 0xf0014000 + + + ADC2 + ADC2 + ADC16 + 0xf0018000 + + + ACMP + ACMP + ACMP + 0xf0020000 + + 0x0 + 0x80 + registers + + + + CHANNEL_CHN0_CFG + Configure Register + 0x0 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN0_DACCFG + DAC configure register + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN0_SR + Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN0_IRQEN + Interrupt request enable register + 0x14 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN0_DMAEN + DMA request enable register + 0x18 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN1_CFG + Configure Register + 0x20 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN1_DACCFG + DAC configure register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN1_SR + Status register + 0x30 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN1_IRQEN + Interrupt request enable register + 0x34 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN1_DMAEN + DMA request enable register + 0x38 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN2_CFG + Configure Register + 0x40 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN2_DACCFG + DAC configure register + 0x44 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN2_SR + Status register + 0x50 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN2_IRQEN + Interrupt request enable register + 0x54 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN2_DMAEN + DMA request enable register + 0x58 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN3_CFG + Configure Register + 0x60 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN3_DACCFG + DAC configure register + 0x64 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN3_SR + Status register + 0x70 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN3_IRQEN + Interrupt request enable register + 0x74 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN3_DMAEN + DMA request enable register + 0x78 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + + + DAC + DAC + DAC + 0xf0024000 + + 0x0 + 0x4c + registers + + + + CFG0 + No description avaiable + 0x0 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + write-only + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + write-only + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + write-only + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + write-only + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + write-only + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + 4 + 2 + write-only + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + write-only + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + write-only + + + + + CFG1 + No description avaiable + 0x4 + 32 + 0x00010000 + 0x0007FFFF + + + ANA_CLK_EN + set to enable analog clock(divided by ana_div_cfg) + 18 + 1 + read-write + + + ANA_DIV_CFG + clock divider config for ana_clk to dac analog; +00: div2 +01: div4 +10: div6 +11: div8 + 16 + 2 + read-write + + + DIV_CFG + how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. +Used for step mode and buffer mode, if set to continual trigger mode + 0 + 16 + read-write + + + + + CFG2 + No description avaiable + 0x8 + 32 + 0x00000000 + 0x000000FF + + + DMA_RST1 + set to reset dma read pointer to buf1_start_addr; +if set both dma_rst0&dma_rst1, will set to buf0_start_addr +user can set fifo_clr bit when use dma_rst* + 7 + 1 + write-only + + + DMA_RST0 + set to reset dma read pointer to buf0_start_addr + 6 + 1 + write-only + + + FIFO_CLR + set to clear FIFO content(set both read/write pointer to 0) + 5 + 1 + write-only + + + BUF_SW_TRIG + software trigger for buffer mode, +W1C in single mode. +RW in continual mode + 4 + 1 + read-write + + + STEP_SW_TRIG3 + No description avaiable + 3 + 1 + read-write + + + STEP_SW_TRIG2 + No description avaiable + 2 + 1 + read-write + + + STEP_SW_TRIG1 + No description avaiable + 1 + 1 + read-write + + + STEP_SW_TRIG0 + software trigger0 for step mode, +W1C in single mode. +RW in continual mode + 0 + 1 + read-write + + + + + STEP_CFG_STEP0 + No description avaiable + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description avaiable + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description avaiable + 0 + 12 + read-write + + + + + STEP_CFG_STEP1 + No description avaiable + 0x14 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description avaiable + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description avaiable + 0 + 12 + read-write + + + + + STEP_CFG_STEP2 + No description avaiable + 0x18 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description avaiable + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description avaiable + 0 + 12 + read-write + + + + + STEP_CFG_STEP3 + No description avaiable + 0x1c + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description avaiable + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description avaiable + 0 + 12 + read-write + + + + + BUF_ADDR_BUF0 + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFD + + + BUF_START_ADDR + buffer start address, should be 4-byte aligned +AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. + 2 + 30 + read-write + + + BUF_STOP + set to stop read point at end of bufffer0 + 0 + 1 + read-write + + + + + BUF_ADDR_BUF1 + No description avaiable + 0x24 + 32 + 0x00000000 + 0xFFFFFFFD + + + BUF_START_ADDR + buffer start address, should be 4-byte aligned +AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. + 2 + 30 + read-write + + + BUF_STOP + set to stop read point at end of bufffer0 + 0 + 1 + read-write + + + + + BUF_LENGTH + No description avaiable + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF1_LEN + buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer + 16 + 16 + read-write + + + BUF0_LEN + No description avaiable + 0 + 16 + read-write + + + + + IRQ_STS + No description avaiable + 0x30 + 32 + 0x00000000 + 0x0000000F + + + AHB_ERROR + set if hresp==2'b01(ERROR) + 3 + 1 + read-write + + + FIFO_EMPTY + No description avaiable + 2 + 1 + read-write + + + BUF1_CMPT + No description avaiable + 1 + 1 + read-write + + + BUF0_CMPT + No description avaiable + 0 + 1 + read-write + + + + + IRQ_EN + No description avaiable + 0x34 + 32 + 0x00000000 + 0x0000000F + + + AHB_ERROR + No description avaiable + 3 + 1 + read-write + + + FIFO_EMPTY + No description avaiable + 2 + 1 + read-write + + + BUF1_CMPT + No description avaiable + 1 + 1 + read-write + + + BUF0_CMPT + No description avaiable + 0 + 1 + read-write + + + + + DMA_EN + No description avaiable + 0x38 + 32 + 0x00000000 + 0x00000003 + + + BUF1_CMPT + No description avaiable + 1 + 1 + read-write + + + BUF0_CMPT + No description avaiable + 0 + 1 + read-write + + + + + ANA_CFG0 + No description avaiable + 0x40 + 32 + 0x00000110 + 0x000001FF + + + DAC12BIT_LP_MODE + No description avaiable + 8 + 1 + read-write + + + DAC_CONFIG + No description avaiable + 4 + 4 + read-write + + + CALI_DELTA_V_CFG + No description avaiable + 2 + 2 + read-write + + + BYPASS_CALI_GM + No description avaiable + 1 + 1 + read-write + + + DAC12BIT_EN + No description avaiable + 0 + 1 + read-write + + + + + STATUS0 + No description avaiable + 0x48 + 32 + 0x00000000 + 0x00FFFF80 + + + CUR_BUF_OFFSET + No description avaiable + 8 + 16 + read-write + + + CUR_BUF_INDEX + No description avaiable + 7 + 1 + read-write + + + + + + + SPI0 + SPI0 + SPI + 0xf0030000 + + 0x10 + 0x70 + registers + + + + TRANSFMT + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + RESERVED + No description avaiable + 18 + 14 + read-write + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + DIRECTIO + Direct IO Control Register + 0x14 + 32 + 0x00003100 + 0x013F3F3F + + + DIRECTIOEN + Enable Direct IO +0x0: Disable +0x1: Enable + 24 + 1 + read-write + + + HOLD_OE + Output enable for the SPI Flash hold signal + 21 + 1 + read-write + + + WP_OE + Output enable for the SPI Flash write protect signal + 20 + 1 + read-write + + + MISO_OE + Output enable fo the SPI MISO signal + 19 + 1 + read-write + + + MOSI_OE + Output enable for the SPI MOSI signal + 18 + 1 + read-write + + + SCLK_OE + Output enable for the SPI SCLK signal + 17 + 1 + read-write + + + CS_OE + Output enable for SPI CS (chip select) signal + 16 + 1 + read-write + + + HOLD_O + Output value for the SPI Flash hold signal + 13 + 1 + read-write + + + WP_O + Output value for the SPI Flash write protect signal + 12 + 1 + read-write + + + MISO_O + Output value for the SPI MISO signal + 11 + 1 + read-write + + + MOSI_O + Output value for the SPI MOSI signal + 10 + 1 + read-write + + + SCLK_O + Output value for the SPI SCLK signal + 9 + 1 + read-write + + + CS_O + Output value for the SPI CS (chip select) signal + 8 + 1 + read-write + + + HOLD_I + Status of the SPI Flash hold signal + 5 + 1 + read-only + + + WP_I + Status of the SPI Flash write protect signal + 4 + 1 + read-only + + + MISO_I + Status of the SPI MISO signal + 3 + 1 + read-only + + + MOSI_I + Status of the SPI MOSI signal + 2 + 1 + read-only + + + SCLK_I + Status of the SPI SCLK signal + 1 + 1 + read-only + + + CS_I + Status of the SPI CS (chip select) signal + 0 + 1 + read-only + + + + + TRANSCTRL + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + CMD + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + ADDR + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + DATA + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + CTRL + Control Register + 0x30 + 32 + 0x00000000 + 0x00FFFF1F + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + STATUS + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + INTREN + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + INTRST + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + read-write + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + read-write + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + read-write + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + read-write + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + read-write + + + + + TIMING + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SLVST + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + read-write + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SLVDATACNT + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + CONFIG + Configuration Register + 0x7c + 32 + 0x00004311 + 0x00004BFF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + DIRECTIO + Support for Direct SPI IO + 11 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0034000 + + + SPI2 + SPI2 + SPI + 0xf0038000 + + + SPI3 + SPI3 + SPI + 0xf003c000 + + + UART0 + UART0 + UART + 0xf0040000 + + 0x10 + 0x2c + registers + + + + CFG + Configuration Register + 0x10 + 32 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 2 + 30 + read-write + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: The over-sample ratio is 32 +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + 0x24 + 32 + 0x00000000 + 0x0000000F + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + 0x28 + 32 + 0x00000001 + 0x000000CF + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0x000000FF + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-write + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + UART4 + UART4 + UART + 0xf0050000 + + + UART5 + UART5 + UART + 0xf0054000 + + + UART6 + UART6 + UART + 0xf0058000 + + + UART7 + UART7 + UART + 0xf005c000 + + + PUART + PUART + UART + 0xf40e4000 + + + CAN0 + CAN0 + CAN + 0xf0080000 + + 0x0 + 0xca + registers + + + + RBUF_BUF0 + receive buffer registers and reception time stamp + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF1 + receive buffer registers and reception time stamp + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF2 + receive buffer registers and reception time stamp + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF3 + receive buffer registers and reception time stamp + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF4 + receive buffer registers and reception time stamp + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF5 + receive buffer registers and reception time stamp + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF6 + receive buffer registers and reception time stamp + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF7 + receive buffer registers and reception time stamp + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF8 + receive buffer registers and reception time stamp + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF9 + receive buffer registers and reception time stamp + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF10 + receive buffer registers and reception time stamp + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF11 + receive buffer registers and reception time stamp + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF12 + receive buffer registers and reception time stamp + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF13 + receive buffer registers and reception time stamp + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF14 + receive buffer registers and reception time stamp + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF15 + receive buffer registers and reception time stamp + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF16 + receive buffer registers and reception time stamp + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF17 + receive buffer registers and reception time stamp + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF18 + receive buffer registers and reception time stamp + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF19 + receive buffer registers and reception time stamp + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + TBUF_BUF0 + transmit buffer register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF1 + transmit buffer register + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF2 + transmit buffer register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF3 + transmit buffer register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF4 + transmit buffer register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF5 + transmit buffer register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF6 + transmit buffer register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF7 + transmit buffer register + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF8 + transmit buffer register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF9 + transmit buffer register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF10 + transmit buffer register + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF11 + transmit buffer register + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF12 + transmit buffer register + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF13 + transmit buffer register + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF14 + transmit buffer register + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF15 + transmit buffer register + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF16 + transmit buffer register + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF17 + transmit buffer register + 0x94 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TTS_WRD0 + transmission time stamp, LSB 32bit + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + TTS_WRD0 + transmission time stamp, word 0, LSB 32bit + 0 + 32 + read-only + + + + + TTS_WRD1 + transmission time stamp, MSB 32bit + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + TTS_WRD0 + transmission time stamp, word 0, LSB 32bit + 0 + 32 + read-only + + + + + CMD_STA_CMD_CTRL + config, status, command and control bits + 0xa0 + 32 + 0x00900080 + 0xFBF3FFFF + + + SACK + Self-ACKnowledge +0 – no self-ACK +1 – self-ACK when LBME=1 + 31 + 1 + read-write + + + ROM + Receive buffer Overflow Mode +In case of a full RBUF when a new message is received, then ROM selects the following: +1 – The new message will not be stored. +0 – The oldest message will be overwritten. + 30 + 1 + read-write + + + ROV + Receive buffer OVerflow +1 – Overflow. At least one message is lost. +0 – No Overflow. +ROV is cleared by setting RREL=1. + 29 + 1 + read-only + + + RREL + Receive buffer RELease +The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL +core points to the next RB slot. RSTAT gets updated. +1 – Release: The host has read the RB. +0 – No release + 28 + 1 + read-write + + + RBALL + Receive Buffer stores ALL data frames +0 – normal operation +1 – RB stores correct data frames as well as data frames with error + 27 + 1 + read-write + + + RSTAT + Receive buffer STATus +00 - empty +01 - > empty and < almost full (AFWL) +10 -  almost full (programmable threshold by AFWL) but not full and no overflow +11 - full (stays set in case of overflow – for overflow signaling see ROV) + 24 + 2 + read-only + + + FD_ISO + CAN FD ISO mode +0 - Bosch CAN FD (non-ISO) mode +1 - ISO CAN FD mode (ISO 11898-1:2015) +ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. +Both modes are incompatible and must not be mixed in one CAN network. +This bit has no impact to CAN 2.0B. +This bit is only writeable if RESET=1. + 23 + 1 + read-write + + + TSNEXT + Transmit buffer Secondary NEXT +0 - no action +1 - STB slot filled, select next slot. +After all frame bytes are written to the TBUF registers, the host controller has to set +TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF +registers to the next slot. Once a slot is marked as filled a transmission can be started +using TSONE or TSALL. +It is possible to set TSNEXT and TSONE or TSALL together in one write access. +TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL +core immediately after it was set. +Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and +automatically cleared. It does not do any harm. +If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. +TSNEXT has no meaning in TTCAN mode and is fixed to 0. + 22 + 1 + read-write + + + TSMODE + Transmit buffer Secondary operation MODE +0 - FIFO mode +1 - priority decision mode +In FIFO mode frames are transmitted in the order in that they are written into the STB. +In priority decision mode the frame with the highest priority in the STB is automatically +transmitted first. The ID of a frame is used for the priority decision. A lower ID means a +higher priority of a frame. A frame in the PTB has always the highest priority regardless of +the ID. +TSMODE shall be switched only if the STB if empty + 21 + 1 + read-write + + + TTTBM + TTCAN Transmit Buffer Mode +If TTEN=0 then TTTBM is ignored, otherwise the following is valid: +0 - separate PTB and STB, behavior defined by TSMODE +1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR +For event-driven CAN communication (TTEN=0), the system provides PTB and STB and +the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. +For time-triggered CAN communication (TTEN=1) with full support of all features including +time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are +addressable using TTPTR and TBPTR. +For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode +and the behavior can be selected by TSMODE. +TTTBM shall be switched only if the TBUF is empty. + 20 + 1 + read-write + + + TSSTAT + Transmission Secondary STATus bits +If TTEN=0 or TTTBM=0: +00 – STB is empty +01 – STB is less than or equal to half full +10 – STB is more than half full +11 – STB is full +If the STB is disabled using STB_DISABLE, then TSSTAT=00. +If TTEN=1 and TTTBM=1: +00 – PTB and STB are empty +01 – PTB and STB are not empty and not full +11 – PTB and STB are full + 16 + 2 + read-only + + + TBSEL + Transmit Buffer Select +Selects the transmit buffer to be loaded with a message. Use the TBUF registers for +access. TBSEL needs to be stable all the time the TBUF registers are written and when +TSNEXT is set. +0 - PTB (high-priority buffer) +1 - STB +The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) + 15 + 1 + read-write + + + LOM + Listen Only Mode +0 - Disabled +1 - Enabled +LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM +is enabled and LBME is disabled. +LOM=1 and LBME=0 disables all transmissions. +LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables +the transmission of own frames. + 14 + 1 + read-write + + + STBY + Transceiver Standby Mode +0 - Disabled +1 - Enabled +This register bit is connected to the output signal stby which can be used to control a +standby mode of a transceiver. +STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. +If the host sets STBY to 0 then the host needs to wait for the time required by the +transceiver to start up before the host requests a new transmission. + 13 + 1 + read-write + + + TPE + Transmit Primary Enable +1 - Transmission enable for the message in the high-priority PTB +0 - No transmission for the PTB +If TPE is set, the message from the PTB will be transmitted at the next possible transmit +position. A started transmission from the STB will be completed before, but pending new +messages are delayed until the PTB message has been transmitted. +TPE stays set until the message has been transmitted successfully or it is aborted using +TPA. +The host controller can set TPE to 1 but can not reset it to 0. This would only be possible +using TPA and aborting the message. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). + 12 + 1 + read-write + + + TPA + Transmit Primary Abort +1 – Aborts a transmission from PTB which has been requested by TPE=1 but not +started yet. (The data bytes of the message remains in the PTB.) +0 – no abort +The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA +automatically de-asserts TPE. +The host controller can set TPA to 1 but can not reset it to 0. +During the short time while the CAN-CTRL core resets the bit, it cannot be set by the +host. +The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). +TPA should not be set simultaneously with TPE. + 11 + 1 + read-write + + + TSONE + Transmit Secondary ONE frame +1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message +and in priority mode this is the one with the highest priority. +TSONE in priority mode is difficult to handle, because it is not always clear which +message will be transmitted if new messages are written to the STB meanwhile. +The controller starts the transmission as soon as the bus becomes vacant and +no request of the PTB (bit TPE) is pending. +0 – No transmission for the STB. +TSONE stays set until the message has been transmitted successfully or it is aborted +using TSA. +The host controller can set TSONE to 1 but can not reset it to 0. This would only be +possible using TSA and aborting the message. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). + 10 + 1 + read-write + + + TSALL + Transmit Secondary ALL frames +1 – Transmission enable of all messages in the STB. +The controller starts the transmission as soon as the bus becomes vacant and +no request of the PTB (bit TPE) is pending. +0 – No transmission for the STB. +TSALL stays set until all messages have been transmitted successfully or they are aborted +using TSA. +The host controller can set TSALL to 1 but can not reset it to 0. This would only be +possible using TSA and aborting the messages. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). +If during a transmission the STB is loaded with a new frame then the new frame will be +transmitted too. In other words: a transmission initiated by TSALL is finished when the +STB becomes empty. + 9 + 1 + read-write + + + TSA + Transmit Secondary Abort +1 – Aborts a transmission from STB which has been requested but not started yet. +For a TSONE transmission, only one frame is aborted while for a TSALL +Transmission, all frames are aborted. +One or all message slots will be released which updates TSSTAT. +All aborted messages are lost because they are not accessible any more. +If in priority mode a TSONE transmission is aborted, then it is not clear which +frame will be aborted if new frames are written to the STB meanwhile. +0 – no abort +The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. +The host controller can set TSA to 1 but can not reset it to 0. +The bit will be reset to the hardware reset value if RESET=1. +TSA should not be set simultaneously with TSONE or TSALL. + 8 + 1 + read-write + + + RESET + RESET request bit +1 - The host controller performs a local reset of CAN-CTRL. +0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. +Bit RESET forces several components to a reset state. +RESET is automatically set if the node enters “bus off” state. +Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. +This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. +The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. + 7 + 1 + read-write + + + LBME + Loop Back Mode, External +0 - Disabled +1 - EnabledLBME should not be enabled while a transmission is active + 6 + 1 + read-write + + + LBMI + Loop Back Mode, Internal +0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. + 5 + 1 + read-write + + + TPSS + Transmission Primary Single Shot mode for PTB +0 - Disabled +1 - Enabled + 4 + 1 + read-write + + + TSSS + Transmission Secondary Single Shot mode for STB +0 - Disabled +1 - Enabled + 3 + 1 + read-write + + + RACTIVE + Reception ACTIVE (Receive Status bit) +1 - The controller is currently receiving a frame. +0 - No receive activity. + 2 + 1 + read-only + + + TACTIVE + Transmission ACTIVE (Transmit Status bit) +1 - The controller is currently transmitting a frame. +0 - No transmit activity. + 1 + 1 + read-only + + + BUSOFF + Bus Off (Bus Status bit) +1 - The controller status is “bus off”. +0 - The controller status is “bus on”. +Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. +See Chapter 3.9.10.6 for details. + 0 + 1 + read-write + + + + + RTIE + Receive and Transmit Interrupt Enable Register RTIE + 0xa4 + 8 + 0xFE + 0xFF + + + RIE + Receive Interrupt Enable +0 – Disabled, 1 – Enabled + 7 + 1 + read-write + + + ROIE + RB Overrun Interrupt Enable +0 – Disabled, 1 – Enabled + 6 + 1 + read-write + + + RFIE + RB Full Interrupt Enable +0 – Disabled, 1 – Enabled + 5 + 1 + read-write + + + RAFIE + RB Almost Full Interrupt Enable +0 – Disabled, 1 – Enabled + 4 + 1 + read-write + + + TPIE + Transmission Primary Interrupt Enable +0 – Disabled, 1 – Enabled + 3 + 1 + read-write + + + TSIE + Transmission Secondary Interrupt Enable +0 – Disabled, 1 – Enabled + 2 + 1 + read-write + + + EIE + Error Interrupt Enable +0 – Disabled, 1 – Enabled + 1 + 1 + read-write + + + TSFF + If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag +1 - The STB is filled with the maximal number of messages. +0 - The STB is not filled with the maximal number of messages. +If the STB is disabled using STB_DISABLE, then TSFF=0. +If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag +1 - The buffer slot selected by TBPTR is filled. +0 - The buffer slot selected by TBPTR is empty. + 0 + 1 + read-only + + + + + RTIF + Receive and Transmit Interrupt Flag Register RTIF (0xa5) + 0xa5 + 8 + 0x00 + 0xFF + + + RIF + Receive Interrupt Flag +1 - Data or a remote frame has been received and is available in the receive buffer. +0 - No frame has been received. + 7 + 1 + read-write + + + ROIF + RB Overrun Interrupt Flag +1 - At least one received message has been overwritten in the RB. +0 - No RB overwritten. +In case of an overrun both ROIF and RFIF will be set. + 6 + 1 + read-write + + + RFIF + RB Full Interrupt Flag +1 - All RBs are full. If no RB will be released until the next valid message is received, +the oldest message will be lost. +0 - The RB FIFO is not full. + 5 + 1 + read-write + + + RAFIF + RB Almost Full Interrupt Flag +1 - number of filled RB slots >= AFWL_i +0 - number of filled RB slots < AFWL_i + 4 + 1 + read-write + + + TPIF + Transmission Primary Interrupt Flag +1 - The requested transmission of the PTB has been successfully completed. +0 - No transmission of the PTB has been completed. +In TTCAN mode, TPIF will never be set. Then only TSIF is valid. + 3 + 1 + read-write + + + TSIF + Transmission Secondary Interrupt Flag +1 - The requested transmission of the STB has been successfully completed. +0 - No transmission of the STB has been completed successfully. +In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of +the message. + 2 + 1 + read-write + + + EIF + Error Interrupt Flag +1 - The border of the error warning limit has been crossed in either direction, +or the BUSOFF bit has been changed in either direction. +0 - There has been no change. + 1 + 1 + read-write + + + AIF + Abort Interrupt Flag +1 - After setting TPA or TSA the appropriated message(s) have been aborted. +It is recommended to not set both TPA and TSA simultaneously because both +source AIF. +0 - No abort has been executed. +The AIF does not have an associated enable register. + 0 + 1 + read-write + + + + + ERRINT + ERRor INTerrupt Enable and Flag Register ERRINT + 0xa6 + 8 + 0x00 + 0xFF + + + EWARN + Error WARNing limit reached +1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. + 7 + 1 + read-only + + + EPASS + Error Passive mode active +0 - not active (node is error active) +1 - active (node is error passive) + 6 + 1 + read-only + + + EPIE + Error Passive Interrupt Enable + 5 + 1 + read-write + + + EPIF + Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error +active to error passive or vice versa and if this interrupt is enabled. + 4 + 1 + read-write + + + ALIE + Arbitration Lost Interrupt Enable + 3 + 1 + read-write + + + ALIF + Arbitration Lost Interrupt Flag + 2 + 1 + read-write + + + BEIE + Bus Error Interrupt Enable + 1 + 1 + read-write + + + BEIF + Bus Error Interrupt Flag + 0 + 1 + read-write + + + + + LIMIT + Warning Limits Register LIMIT + 0xa7 + 8 + 0x1B + 0xFF + + + AFWL + receive buffer Almost Full Warning Limit +AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. +AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . +AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) +AFWL_i > nRB is meaningless and automatically treated as nRB. +AFWL_i = nRB is a valid value, but note that RFIF also exists. + 4 + 4 + read-write + + + EWL + Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. +The value of EWL controls EIF. + 0 + 4 + read-write + + + + + S_PRESC + Bit Timing Register(Slow Speed) + 0xa8 + 32 + 0x01020203 + 0xFF7F7FFF + + + S_PRESC + Prescaler (slow speed) +The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + 24 + 8 + read-write + + + S_SJW + Synchronization Jump Width (slow speed) +The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + 16 + 7 + read-write + + + S_SEG_2 + Bit Timing Segment 2 (slow speed) +Time after the sample point. + 8 + 7 + read-write + + + S_SEG_1 + Bit Timing Segment 1 (slow speed) +The sample point will be set to after start of bit time. + 0 + 8 + read-write + + + + + F_PRESC + Bit Timing Register(Fast Speed) + 0xac + 32 + 0x01020203 + 0xFF0F0F0F + + + F_PRESC + Prescaler (fast speed) +The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + 24 + 8 + read-write + + + F_SJW + Synchronization Jump Width (fast speed) +The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + 16 + 4 + read-write + + + F_SEG_2 + Bit Timing Segment 2 (fast speed) +Time after the sample point + 8 + 4 + read-write + + + F_SEG_1 + Bit Timing Segment 1 (fast speed) +The sample point will be set to after start of bit time. + 0 + 4 + read-write + + + + + EALCAP + Error and Arbitration Lost Capture Register EALCAP + 0xb0 + 8 + 0x00 + 0xFF + + + KOER + Kind Of ERror (Error code) +000 - no error +001 - BIT ERROR +010 - FORM ERROR +011 - STUFF ERROR +100 - ACKNOWLEDGEMENT ERROR +101 - CRC ERROR +110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) +111 - not used +KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. + 5 + 3 + read-only + + + ALC + Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) + 0 + 5 + read-only + + + + + TDC + Transmitter Delay Compensation Register TDC + 0xb1 + 8 + 0x00 + 0xFF + + + TDCEN + Transmitter Delay Compensation ENable +TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. + 7 + 1 + read-write + + + SSPOFF + Secondary Sample Point OFFset +The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. +SSPOFF is given as a number of TQ. + 0 + 7 + read-write + + + + + RECNT + Error Counter Registers RECNT + 0xb2 + 8 + 0x00 + 0xFF + + + RECNT + Receive Error CouNT (number of errors during reception) +RECNT is incremented and decremented as defined in the CAN specification. +RECNT does not overflow. +If TXB=1, then the error counters are frozen. + 0 + 8 + read-only + + + + + TECNT + Error Counter Registers TECNT + 0xb3 + 8 + 0x00 + 0xFF + + + TECNT + Transmit Error CouNT (number of errors during transmission) +TECNT is incremented and decremented as defined in the CAN specification. +In case of the “bus off state” TECNT may overflow. +If TXB=1, then the error counters are frozen. + 0 + 8 + read-only + + + + + ACFCTRL + Acceptance Filter Control Register ACFCTRL + 0xb4 + 8 + 0x00 + 0x2F + + + SELMASK + SELect acceptance MASK +0 - Registers ACF_x point to acceptance code +1 - Registers ACF_x point to acceptance mask. +ACFADR selects one specific acceptance filter. + 5 + 1 + read-write + + + ACFADR + acceptance filter address +ACFADR points to a specific acceptance filter. +The selected filter is accessible using theregisters ACF_x. +Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. +A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. +ACF_NUMBER = 16. + 0 + 4 + read-write + + + + + TIMECFG + CiA 603 Time-Stamping TIMECFG + 0xb5 + 8 + 0x00 + 0x03 + + + TIMEPOS + TIME-stamping POSition +0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. + 1 + 1 + read-write + + + TIMEEN + TIME-stamping ENable +0 – disabled +1 – enabled + 0 + 1 + read-write + + + + + ACF_EN + Acceptance Filter Enable ACF_EN + 0xb6 + 16 + 0x0000 + 0xFFFF + + + ACF_EN + Acceptance filter Enable +1 - acceptance filter enabled +0 - acceptance filter disable +Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. +Disabled filters reject a message. Only enabled filters can accept a message if the +appropriate AMASK / ACODE configuration matches. + 0 + 16 + read-write + + + + + ACF + Acceptance CODE ACODE or ACMASK + 0xb8 + 32 + 0x00000000 + 0x7FFFFFFF + + + AIDEE + Acceptance mask IDE bit check enable +1 - acceptance filter accepts either standard or extended as defined by AIDE +0 - acceptance filter accepts both standard or extended frames +Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + 30 + 1 + read-write + + + AIDE + Acceptance mask IDE bit value +If AIDEE=1 then: +1 - acceptance filter accepts only extended frames +0 - acceptance filter accepts only standard frames +Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + 29 + 1 + read-write + + + CODE_MASK + Acceptance CODE +1 - ACC bit value to compare with ID bit of the received message +0 - ACC bit value to compare with ID bit of the received message +ACODE_x(10:0) will be used for extended frames. +ACODE_x(28:0) will be used for extended frames. +Only filter 0 is affected by the power-on reset. +Acceptance MASK(if SELMASK ==1 ) +1 - acceptance check for these bits of receive identifier disabled +0 - acceptance check for these bits of receive identifier enable +AMASK_x(10:0) will be used for extended frames. +AMASK_x(28:0) will be used for extended frames. +Disabled bits result in accepting the message. Therefore the default configuration after +reset for filter 0 accepts all messages. +Only filter 0 is affected by the power-on reset. + 0 + 29 + read-write + + + + + VER + Version Information VER + 0xbc + 16 + 0x0000 + 0xFFFF + + + VERSION + Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and +VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 + 0 + 16 + read-write + + + + + TBSLOT + TTCAN: TB Slot Pointer TBSLOT + 0xbe + 8 + 0x00 + 0xFF + + + TBE + set TB slot to “Empty” +1 - slot selected by TBPTR shall be marked as “empty” +0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. +If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the + transmissionis not active any more. +If both TBF and TBE are set, then TBE wins + 7 + 1 + read-write + + + TBF + set TB slot to “Filled” +1 - slot selected by TBPTR shall be marked as “filled” +0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. +If both TBF and TBE are set, then TBE wins. + 6 + 1 + read-write + + + TBPTR + Pointer to a TB message slot. +0x00 - Pointer to the PTB +others - Pointer to a slot in the STB +The message slot pointed to by TBPTR is readable / writable using the TBUF registers. +Write access is only possible if TSFF=0. +Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. +TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. +TBPTR can only point to buffer slots, that exist in the hardware. +Unusable bits ofTBPTR are fixed to 0. +TBPTR is limited to the PTB and 63 STB slots. + More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. + 0 + 6 + read-write + + + + + TTCFG + TTCAN: Time Trigger Configuration TTCFG + 0xbf + 8 + 0x00 + 0xFF + + + WTIE + Watch Trigger Interrupt Enable + 7 + 1 + read-write + + + WTIF + Watch Trigger Interrupt Flag +WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. + 6 + 1 + read-write + + + TEIF + Trigger Error Interrupt Flag +The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF + 5 + 1 + read-write + + + TTIE + Time Trigger Interrupt Enable +If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. + 4 + 1 + read-write + + + TTIF + Time Trigger Interrupt Flag +TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. +Writing an one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. +If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. + 3 + 1 + read-write + + + T_PRESC + TTCAN Timer PRESCaler +00b - 1 +01b - 2 +10b - 4 +11b - 8 +The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. +T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. + 1 + 2 + read-write + + + TTEN + Time Trigger Enable +1 - TTCAN enabled, timer is running0 - disabled + 0 + 1 + read-write + + + + + REF_MSG + TTCAN: Reference Message REF_MSG + 0xc0 + 32 + 0x00000000 + 0x9FFFFFFF + + + REF_IDE + REFerence message IDE bit. + 31 + 1 + read-write + + + REF_MSG + REFerence message IDentifier. +If REF_IDE is +1 - REF_ID(28:0) is valid (extended ID) +0 - REF_ID(10:0) is valid (standard ID) +REF_ID is used in TTCAN mode to detect a reference message. This holds for time +slaves (reception) as well as for the time master (transmission). If the reference +message is detected and there are no errors, then the Sync_Mark of this frame will +become the Ref_Mark. +REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. +These bits are used for up to 8 potential time masters. +CAN-CTRL recognizes the reference message only by ID. The payload is not tested. +Additional note: A time master will transmit a reference message in the same way as a +normal frame. REF_ID is intended for detection of a successful transmission of a +reference message. + 0 + 29 + read-write + + + + + TRIG_CFG + TTCAN: Trigger Configuration TRIG_CFG + 0xc4 + 16 + 0x0000 + 0xF73F + + + TEW + Transmit Enable Window +For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time +where the frame is allowed to start. TWE+1 defines the number of ticks. +TEW=0 is a valid setting and shortens the transmit enable window to 1 tick + 12 + 4 + read-write + + + TTYPE + Trigger Type +000b - Immediate Trigger for immediate transmission +001b - Time Trigger for receive triggers +010b - Single Shot Transmit Trigger for exclusive time windows +011b - Transmit Start Trigger for merged arbitrating time windows +100b - Transmit Stop Trigger for merged arbitrating time windows +others - no action +The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the +transmit triggers. See Chapter 6.4 for more details. + 8 + 3 + read-write + + + TTPTR + Transmit Trigger TB slot Pointer +If TTPTR is too big and points to a slot that is not available, then TEIF is set and no +new trigger can be activated after a write access to TT_TRIG_1. +If TTPTR points to an empty slot, then TEIF will be set at the moment, when the +trigger time is reached. + 0 + 6 + read-write + + + + + TT_TRIG + TTCAN: Trigger Time TT_TRIG + 0xc6 + 16 + 0x0000 + 0xFFFF + + + TT_TRIG + Trigger Time +TT_TRIG(15:0) defines the cycle time for a trigger. +For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. + 0 + 16 + read-write + + + + + TT_WTRIG + TTCAN: Watch Trigger Time TT_WTRIG + 0xc8 + 16 + 0x0000 + 0xFFFF + + + TT_WTRIG + Watch Trigger Time +TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. + 0 + 16 + read-write + + + + + + + CAN1 + CAN1 + CAN + 0xf0084000 + + + WDG0 + WDG0 + WDOG + 0xf0090000 + + 0x10 + 0x10 + registers + + + + CTRL + Control Register + 0x10 + 32 + 0x00000000 + 0x000007FF + + + RSTTIME + The time interval of the reset stage: +0: Clock period x 2^7 +1: Clock period x 2^8 +2: Clock period x 2^9 +3: Clock period x 2^10 +4: Clock period x 2^11 +5: Clock period x 2^12 +6: Clock period x 2^13 +7: Clock period x 2^14 + 8 + 3 + read-write + + + INTTIME + The timer interval of the interrupt stage: +0: Clock period x 2^6 +1: Clock period x 2^8 +2: Clock period x 2^10 +3: Clock period x 2^11 +4: Clock period x 2^12 +5: Clock period x 2^13 +6: Clock period x 2^14 +7: Clock period x 2^15 +8: Clock period x 2^17 +9: Clock period x 2^19 +10: Clock period x 2^21 +11: Clock period x 2^23 +12: Clock period x 2^25 +13: Clock period x 2^27 +14: Clock period x 2^29 +15: Clock period x 2^31 + 4 + 4 + read-write + + + RSTEN + Enable or disable the watchdog reset +0: Disable +1: Enable + 3 + 1 + read-write + + + INTEN + Enable or disable the watchdog interrupt +0: Disable +1: Enable + 2 + 1 + read-write + + + CLKSEL + Clock source of timer: +0: EXTCLK +1: PCLK + 1 + 1 + read-write + + + EN + Enable or disable the watchdog timer +0: Disable +1: Enable + 0 + 1 + read-write + + + + + RESTART + Restart Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + RESTART + Write the magic number +ATCWDT200_RESTART_NUM to restart the +watchdog timer. + 0 + 16 + write-only + + + + + WREN + Write Protection Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + WEN + Write the magic code to disable the write +protection of the Control Register and the +Restart Register. + 0 + 16 + write-only + + + + + ST + Status Register + 0x1c + 32 + 0x00000000 + 0x00000001 + + + INTEXPIRED + The status of the watchdog interrupt timer +0: timer is not expired yet +1: timer is expired + 0 + 1 + read-write + + + + + + + WDG1 + WDG1 + WDOG + 0xf0094000 + + + PWDG + PWDG + WDOG + 0xf40e8000 + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x24 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + RESERVED + Reserved + 16 + 15 + read-only + + + BARCTL + Bus Acccess Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + RESERVED + Reserved + 9 + 5 + read-only + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + RESERVED + Reserved + 2 + 2 + read-only + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RESERVED + Not used + 24 + 8 + read-only + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + read-write + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + read-write + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + read-write + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + read-write + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + read-write + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + read-write + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + RESERVED + Not used + 2 + 2 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + TXWRD_TXFIFO0 + TXFIFO for sending message to other core + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + RXWRD_RXFIFO0 + RXFIFO for receiving message from other core + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + PTPC + PTPC + PTPC + 0xf00b0000 + + 0x0 + 0x200c + registers + + + + PTPC_0_CTRL0 + Control Register 0 + 0x0 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description avaiable + 6 + 1 + read-write + + + RESERVED + No description avaiable + 5 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow +1: coarse update, ns counter add ss_incr[7:0] each clk + 1 + 1 + read-write + + + TIMER_ENABLE + No description avaiable + 0 + 1 + read-write + + + + + PTPC_0_CTRL1 + Control Register 1 + 0x4 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + PTPC_0_TIMEH + timestamp high + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description avaiable + 0 + 32 + read-only + + + + + PTPC_0_TIMEL + timestamp low + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description avaiable + 0 + 32 + read-only + + + + + PTPC_0_TS_UPDTH + timestamp update high + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + PTPC_0_TS_UPDTL + timestamp update low + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description avaiable + 0 + 31 + read-write + + + + + PTPC_0_ADDEND + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + PTPC_0_TARH + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + PTPC_0_TARL + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description avaiable + 0 + 32 + read-write + + + + + PTPC_0_PPS_CTRL + No description avaiable + 0x2c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description avaiable + 0 + 4 + read-write + + + + + PTPC_0_CAPT_SNAPH + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + PTPC_0_CAPT_SNAPL + No description avaiable + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description avaiable + 0 + 32 + read-write + + + + + PTPC_1_CTRL0 + Control Register 0 + 0x1000 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description avaiable + 6 + 1 + read-write + + + RESERVED + No description avaiable + 5 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow +1: coarse update, ns counter add ss_incr[7:0] each clk + 1 + 1 + read-write + + + TIMER_ENABLE + No description avaiable + 0 + 1 + read-write + + + + + PTPC_1_CTRL1 + Control Register 1 + 0x1004 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + PTPC_1_TIMEH + timestamp high + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description avaiable + 0 + 32 + read-only + + + + + PTPC_1_TIMEL + timestamp low + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description avaiable + 0 + 32 + read-only + + + + + PTPC_1_TS_UPDTH + timestamp update high + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + PTPC_1_TS_UPDTL + timestamp update low + 0x1014 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description avaiable + 0 + 31 + read-write + + + + + PTPC_1_ADDEND + No description avaiable + 0x1018 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + PTPC_1_TARH + No description avaiable + 0x101c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + PTPC_1_TARL + No description avaiable + 0x1020 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description avaiable + 0 + 32 + read-write + + + + + PTPC_1_PPS_CTRL + No description avaiable + 0x102c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description avaiable + 0 + 4 + read-write + + + + + PTPC_1_CAPT_SNAPH + No description avaiable + 0x1030 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + PTPC_1_CAPT_SNAPL + No description avaiable + 0x1034 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description avaiable + 0 + 32 + read-write + + + + + TIME_SEL + No description avaiable + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + CAN3_TIME_SEL + No description avaiable + 3 + 1 + read-write + + + CAN2_TIME_SEL + No description avaiable + 2 + 1 + read-write + + + CAN1_TIME_SEL + No description avaiable + 1 + 1 + read-write + + + CAN0_TIME_SEL + set to use ptpc1 for canx +clr to use ptpc0 for canx + 0 + 1 + read-write + + + + + INT_STS + No description avaiable + 0x2004 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description avaiable + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description avaiable + 17 + 1 + read-write + + + PPS_INT_STS1 + No description avaiable + 16 + 1 + read-write + + + COMP_INT_STS0 + No description avaiable + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description avaiable + 1 + 1 + read-write + + + PPS_INT_STS0 + No description avaiable + 0 + 1 + read-write + + + + + INT_EN + No description avaiable + 0x2008 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description avaiable + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description avaiable + 17 + 1 + read-write + + + PPS_INT_STS1 + No description avaiable + 16 + 1 + read-write + + + COMP_INT_STS0 + No description avaiable + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description avaiable + 1 + 1 + read-write + + + PPS_INT_STS0 + No description avaiable + 0 + 1 + read-write + + + + + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c0000 + + 0x0 + 0x40 + registers + + + + MUXCFG_HDMA_MUX0 + HDMA MUX0 Configuration + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX1 + HDMA MUX1 Configuration + 0x4 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX2 + HDMA MUX2 Configuration + 0x8 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX3 + HDMA MUX3 Configuration + 0xc + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX4 + HDMA MUX4 Configuration + 0x10 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX5 + HDMA MUX5 Configuration + 0x14 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX6 + HDMA MUX6 Configuration + 0x18 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX7 + HDMA MUX7 Configuration + 0x1c + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX0 + XDMA MUX0 Configuration + 0x20 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX1 + XDMA MUX1 Configuration + 0x24 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX2 + XDMA MUX2 Configuration + 0x28 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX3 + XDMA MUX3 Configuration + 0x2c + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX4 + XDMA MUX4 Configuration + 0x30 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX5 + XDMA MUX5 Configuration + 0x34 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX6 + XDMA MUX6 Configuration + 0x38 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX7 + XDMA MUX7 Configuration + 0x3c + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + + + HDMA + HDMA + DMA + 0xf00c4000 + + 0x10 + 0x15c + registers + + + + DMACFG + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACTRL + DMAC Control Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + CHABORT + Channel Abort Register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + INTSTATUS + Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0x00FFFFFF + + + TC + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 16 + 8 + read-write + + + ABORT + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 8 + 8 + read-write + + + ERROR + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 8 + read-write + + + + + CHEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + CHCTRL_CH0_CTRL + Channel n Control Register + 0x40 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH0_TRANSIZE + Channel n Transfer Size Register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH0_SRCADDR + Channel n Source Address Low Part Register + 0x48 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH0_SRCADDRH + Channel n Source Address High Part Register + 0x4c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH0_DSTADDR + Channel n Destination Address Low Part Register + 0x50 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH0_DSTADDRH + Channel n Destination Address High Part Register + 0x54 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH0_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x58 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH0_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH1_CTRL + Channel n Control Register + 0x60 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH1_TRANSIZE + Channel n Transfer Size Register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH1_SRCADDR + Channel n Source Address Low Part Register + 0x68 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH1_SRCADDRH + Channel n Source Address High Part Register + 0x6c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH1_DSTADDR + Channel n Destination Address Low Part Register + 0x70 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH1_DSTADDRH + Channel n Destination Address High Part Register + 0x74 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH1_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x78 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH1_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH2_CTRL + Channel n Control Register + 0x80 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH2_TRANSIZE + Channel n Transfer Size Register + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH2_SRCADDR + Channel n Source Address Low Part Register + 0x88 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH2_SRCADDRH + Channel n Source Address High Part Register + 0x8c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH2_DSTADDR + Channel n Destination Address Low Part Register + 0x90 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH2_DSTADDRH + Channel n Destination Address High Part Register + 0x94 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH2_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x98 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH2_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH3_CTRL + Channel n Control Register + 0xa0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH3_TRANSIZE + Channel n Transfer Size Register + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH3_SRCADDR + Channel n Source Address Low Part Register + 0xa8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH3_SRCADDRH + Channel n Source Address High Part Register + 0xac + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH3_DSTADDR + Channel n Destination Address Low Part Register + 0xb0 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH3_DSTADDRH + Channel n Destination Address High Part Register + 0xb4 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH3_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0xb8 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH3_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH4_CTRL + Channel n Control Register + 0xc0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH4_TRANSIZE + Channel n Transfer Size Register + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH4_SRCADDR + Channel n Source Address Low Part Register + 0xc8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH4_SRCADDRH + Channel n Source Address High Part Register + 0xcc + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH4_DSTADDR + Channel n Destination Address Low Part Register + 0xd0 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH4_DSTADDRH + Channel n Destination Address High Part Register + 0xd4 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH4_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0xd8 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH4_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH5_CTRL + Channel n Control Register + 0xe0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH5_TRANSIZE + Channel n Transfer Size Register + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH5_SRCADDR + Channel n Source Address Low Part Register + 0xe8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH5_SRCADDRH + Channel n Source Address High Part Register + 0xec + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH5_DSTADDR + Channel n Destination Address Low Part Register + 0xf0 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH5_DSTADDRH + Channel n Destination Address High Part Register + 0xf4 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH5_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0xf8 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH5_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH6_CTRL + Channel n Control Register + 0x100 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH6_TRANSIZE + Channel n Transfer Size Register + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH6_SRCADDR + Channel n Source Address Low Part Register + 0x108 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH6_SRCADDRH + Channel n Source Address High Part Register + 0x10c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH6_DSTADDR + Channel n Destination Address Low Part Register + 0x110 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH6_DSTADDRH + Channel n Destination Address High Part Register + 0x114 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH6_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x118 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH6_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH7_CTRL + Channel n Control Register + 0x120 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH7_TRANSIZE + Channel n Transfer Size Register + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH7_SRCADDR + Channel n Source Address Low Part Register + 0x128 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH7_SRCADDRH + Channel n Source Address High Part Register + 0x12c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH7_DSTADDR + Channel n Destination Address Low Part Register + 0x130 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH7_DSTADDRH + Channel n Destination Address High Part Register + 0x134 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH7_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x138 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH7_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + + + XDMA + XDMA + DMA + 0xf3048000 + + + RNG + RNG + RNG + 0xf00c8000 + + 0x0 + 0x40 + registers + + + + CMD + Command Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 7 + 25 + read-write + + + SFTRST + Soft Reset, Perform a software reset of the RNG This bit is self-clearing. +0 Do not perform a software reset. +1 Software reset + 6 + 1 + read-write + + + CLRERR + Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. +0 Do not clear the errors and the interrupt. +1 Clear the errors and the interrupt. + 5 + 1 + read-write + + + CLRINT + Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. +0 Do not clear the interrupt. +1 Clear the interrupt + 4 + 1 + read-write + + + RESERVED + Not used + 2 + 2 + read-only + + + GENSD + Generate Seed, when both ST and GS triggered, ST first and GS next. + 1 + 1 + read-write + + + SLFCHK + Self Test, when both ST and GS triggered, ST first and GS next. + 0 + 1 + read-write + + + + + CTRL + Control Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 7 + 25 + read-only + + + MIRQERR + Mask Interrupt Request for Error + 6 + 1 + read-write + + + MIRQDN + Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: +• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). +• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + 5 + 1 + read-write + + + AUTRSD + Auto Reseed + 4 + 1 + read-write + + + RESERVED + Not used + 2 + 2 + read-only + + + FUFMOD + FIFO underflow response mode +00 Return all zeros and set the ESR[FUFE]. +01 Return all zeros and set the ESR[FUFE]. +10 Generate the bus transfer error +11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + 0 + 2 + read-write + + + + + STA + Status Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 24 + 8 + read-only + + + SCPF + Self Check Pass Fail + 21 + 3 + read-only + + + RESERVED + Not used + 17 + 4 + read-only + + + FUNCERR + Error was detected, check ESR register for details + 16 + 1 + read-only + + + FSIZE + Fifo Size, it is 5 in this design. + 12 + 4 + read-only + + + FRNNU + Fifo Level, Indicates the number of random words currently in the output FIFO + 8 + 4 + read-only + + + RESERVED + Not used + 7 + 1 + read-only + + + NSDDN + New seed done. + 6 + 1 + read-only + + + FSDDN + 1st Seed done +When "1", Indicates that the RNG generated the first seed. + 5 + 1 + read-only + + + SCDN + Self Check Done +Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is +initiated by setting the CMD[ST]. +0 Self test not completed +1 Completed a self test since the last reset. + 4 + 1 + read-only + + + RSDREQ + Reseed needed +Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or +automatically if the CTRL[ARS] is set. + 3 + 1 + read-only + + + IDLE + Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + 2 + 1 + read-only + + + BUSY + when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + 1 + 1 + read-only + + + RESERVED + Not used + 0 + 1 + read-only + + + + + ERR + Error Registers + 0xc + 32 + 0x00000000 + 0xFFFFFF3F + + + RESERVED + OSC1 Satistics test pass failed. +Indicates the pass or fail status of the various statistics tests on the last seed generated. +0 Pass +1 Fail + 24 + 8 + read-only + + + RESERVED + OSC0 Satistics test pass failed. +Indicates the pass or fail status of the various statistics tests on the last seed generated. +0 Pass +1 Fail + 16 + 8 + read-only + + + RESERVED + Not used + 8 + 8 + read-only + + + FUFE + FIFO access error(underflow) + 5 + 1 + read-only + + + RESERVED + Statistical test error +Indicates whether the statistical tests for the last generated seed was failed or not. This bit is sticky and is +cleared by a hardware or software reset or by writing 1 to the CMD[CE]. +0 No fail for the statistical tests. +1 Failed the statistical tests during the initialization + 4 + 1 + read-only + + + SCKERR + Self-test error +Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a +hardware reset or by writing 1 to the CMD[CE] + 3 + 1 + read-only + + + RESERVED + Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a +software or hardware reset. + 2 + 1 + read-only + + + RESERVED + Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a +software or hardware reset. + 1 + 1 + read-only + + + RESERVED + Linear feedback shift register (LFSR) error +When this bit is set, the interrupt generated was caused by a failure of one of the LFSRs in any of the RNG LFSR ciruit. + 0 + 1 + read-only + + + + + FO2B + FIFO out to bus/cpu + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2B + SW read the FIFO output. + 0 + 32 + read-only + + + + + R2SK_FO2S0 + FIFO out to SDP as AES engine key + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S1 + FIFO out to SDP as AES engine key + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S2 + FIFO out to SDP as AES engine key + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S3 + FIFO out to SDP as AES engine key + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S4 + FIFO out to SDP as AES engine key + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S5 + FIFO out to SDP as AES engine key + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S6 + FIFO out to SDP as AES engine key + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S7 + FIFO out to SDP as AES engine key + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + + + KEYM + KEYM + KEYM + 0xf00cc000 + + 0x0 + 0x50 + registers + + + + SOFTMKEY_SFK0 + software set symmetric key + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK1 + software set symmetric key + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK2 + software set symmetric key + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK3 + software set symmetric key + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK4 + software set symmetric key + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK5 + software set symmetric key + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK6 + software set symmetric key + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK7 + software set symmetric key + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK0 + system asymmetric key + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK1 + system asymmetric key + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK2 + system asymmetric key + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK3 + system asymmetric key + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK4 + system asymmetric key + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK5 + system asymmetric key + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK6 + system asymmetric key + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK7 + system asymmetric key + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of followings +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of followings +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + I2S0 + I2S0 + I2S + 0xf0100000 + + 0x0 + 0x80 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 19 + 13 + read-write + + + SFTRST_RX + software reset the RX module if asserted to be 1'b1. Self-clear. + 18 + 1 + read-write + + + SFTRST_TX + software reset the TX module if asserted to be 1'b1. Self-clear. + 17 + 1 + read-write + + + SFTRST_CLKGEN + software reset the CLK GEN module if asserted to be 1'b1. Self-clear. + 16 + 1 + read-write + + + TXDNIE + TX buffer data needed interrupt enable +0: TXE interrupt masked +1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 15 + 1 + read-write + + + RXDAIE + RX buffer data available interrupt enable +0: RXNE interrupt masked +1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 14 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 13 + 1 + read-write + + + TX_DMA_EN + Asserted to use DMA, else to use interrupt + 12 + 1 + read-write + + + RX_DMA_EN + Asserted to use DMA, else to use interrupt + 11 + 1 + read-write + + + TXFIFOCLR + Self-clear + 10 + 1 + read-write + + + RXFIFOCLR + Self-clear + 9 + 1 + read-write + + + TX_EN + enable for each TX data pad + 5 + 4 + read-write + + + RX_EN + enable for each RX data pad + 1 + 4 + read-write + + + I2S_EN + enable for the module + 0 + 1 + read-write + + + + + RFIFO_FILLINGS + Rx FIFO Filling Level + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX3 + RX3 fifo fillings + 24 + 8 + read-only + + + RX2 + RX2 fifo fillings + 16 + 8 + read-only + + + RX1 + RX1 fifo fillings + 8 + 8 + read-only + + + RX0 + RX0 fifo fillings + 0 + 8 + read-only + + + + + TFIFO_FILLINGS + Tx FIFO Filling Level + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX3 + TX3 fifo fillings + 24 + 8 + read-only + + + TX2 + TX2 fifo fillings + 16 + 8 + read-only + + + TX1 + TX1 fifo fillings + 8 + 8 + read-only + + + TX0 + TX0 fifo fillings + 0 + 8 + read-only + + + + + FIFO_THRESH + TX/RX FIFO Threshold setting. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 16 + 16 + read-write + + + TX + TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. + 8 + 8 + read-write + + + RX + RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. + 0 + 8 + read-write + + + + + STA + Status Registers + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 17 + 15 + read-only + + + TX_UD + Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. + 13 + 4 + read-write + + + RX_OV + Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. + 9 + 4 + read-write + + + TX_DN + Asserted when tx fifo data are needed. + 5 + 4 + read-only + + + RX_DA + Asserted when rx fifo data are available. + 1 + 4 + read-only + + + RSV + Reserved + 0 + 1 + read-only + + + + + RXD_DATA0 + Rx Data0 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + read-only + + + + + RXD_DATA1 + Rx Data1 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + read-only + + + + + RXD_DATA2 + Rx Data2 + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + read-only + + + + + RXD_DATA3 + Rx Data3 + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + read-only + + + + + TXD_DATA0 + Tx Data0 + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + write-only + + + + + TXD_DATA1 + Tx Data1 + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + write-only + + + + + TXD_DATA2 + Tx Data2 + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + write-only + + + + + TXD_DATA3 + Tx Data3 + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + write-only + + + + + CFGR + Configruation Regsiters + 0x50 + 32 + 0x40000000 + 0xFFFFFFFF + + + RSV + Reserved + 31 + 1 + read-write + + + BCLK_GATEOFF + Gate off the bclk. Asserted to gate-off the BCLK. + 30 + 1 + read-write + + + BCLK_DIV + Linear prescaler to generate BCLK from MCLK. +BCLK_DIV [8:0] = 0: BCLK=No CLK. +BCLK_DIV [8:0] = 1: BCLK=MCLK/1 +BCLK_DIV [8:0] = n: BCLK=MCLK/(n). +Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 21 + 9 + read-write + + + INV_BCLK_OUT + Invert the BCLK before sending it out to pad. Only valid in BCLK master mode + 20 + 1 + read-write + + + INV_BCLK_IN + Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode + 19 + 1 + read-write + + + INV_FCLK_OUT + Invert the FCLK before sending it out to pad. Only valid in FCLK master mode + 18 + 1 + read-write + + + INV_FCLK_IN + Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode + 17 + 1 + read-write + + + INV_MCLK_OUT + Invert the MCLK before sending it out to pad. Only valid in MCLK master mode + 16 + 1 + read-write + + + INV_MCLK_IN + Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode + 15 + 1 + read-write + + + BCLK_SEL_OP + asserted to use external clk source + 14 + 1 + read-write + + + FCLK_SEL_OP + asserted to use external clk source + 13 + 1 + read-write + + + MCK_SEL_OP + asserted to use external clk source + 12 + 1 + read-write + + + FRAME_EDGE + The start edge of a frame +0: Falling edge indicates a new frame (Just like standard I2S Philips standard) +1: Rising edge indicates a new frame + 11 + 1 + read-write + + + CH_MAX + CH_MAX[3:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +4'h2: 2 channels +4'h4: 4 channels +... + 6 + 5 + read-write + + + TDM_EN + TDM mode +0: not TDM mode +1: TDM mode + 5 + 1 + read-write + + + STD + I2S standard selection +00: I2S Philips standard. +01: MSB justified standard (left justified) +10: LSB justified standard (right justified) +11: PCM standard +Note: For correct operation, these bits should be configured when the I2S is disabled. + 3 + 2 + read-write + + + DATSIZ + Data length to be transferred +00: 16-bit data length +01: 24-bit data length +10: 32-bit data length +11: Not allowed +Note: For correct operation, these bits should be configured when the I2S is disabled. + 1 + 2 + read-write + + + CHSIZ + Channel length (number of bits per audio channel) +0: 16-bit wide +1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. + 0 + 1 + read-write + + + + + MISC_CFGR + Misc configuration Registers + 0x58 + 32 + 0x00042000 + 0xFFFFEC01 + + + RSV + Reserved + 14 + 18 + read-write + + + MCLK_GATEOFF + Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. + 13 + 1 + read-write + + + RSV + Reserved + 11 + 1 + read-write + + + RSV + Reserved + 10 + 1 + read-write + + + MCLKOE + Master clock output to pad enable +0: Master clock output is disabled +1: Master clock output is enabled +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 0 + 1 + read-write + + + + + RXDSLOT_DATA0 + Rx Slots Enable for Rx Data0 + 0x60 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + RXDSLOT_DATA1 + Rx Slots Enable for Rx Data1 + 0x64 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + RXDSLOT_DATA2 + Rx Slots Enable for Rx Data2 + 0x68 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + RXDSLOT_DATA3 + Rx Slots Enable for Rx Data3 + 0x6c + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + TXDSLOT_DATA0 + Tx Slots Enable for Tx Data0. + 0x70 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + TXDSLOT_DATA1 + Tx Slots Enable for Tx Data1. + 0x74 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + TXDSLOT_DATA2 + Tx Slots Enable for Tx Data2. + 0x78 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + TXDSLOT_DATA3 + Tx Slots Enable for Tx Data3. + 0x7c + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + + + I2S1 + I2S1 + I2S + 0xf0104000 + + + DAO + DAO + DAO + 0xf0110000 + + 0x0 + 0x1c + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x000300FF + + + HPF_EN + Whether HPF is enabled. This HPF is used to filter out the DC part. + 17 + 1 + read-write + + + SAT_ERR_IE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (saturation) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 16 + 1 + read-write + + + MONO + Asserted to let the left and right channel output the same value. + 7 + 1 + read-write + + + RIGHT_EN + Asserted to enable the right channel + 6 + 1 + read-write + + + LEFT_EN + Asserted to enable the left channel + 5 + 1 + read-write + + + REMAP + 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative +0: Don't use remap pwm version + 4 + 1 + read-write + + + INVERT + all the outputs are inverted before sending to pad + 3 + 1 + read-write + + + FALSE_LEVEL + the pad output in False run mode, or when the module is disabled +0: all low +1: all high +2: P-high, N-low +3. output is not enabled + 1 + 2 + read-write + + + FALSE_RUN + the module continues to comsume data, but all the pads are constant, thus no audio out + 0 + 1 + read-write + + + + + CMD + Command Register + 0x8 + 32 + 0x00000000 + 0x00000003 + + + SFTRST + Self-clear + 1 + 1 + read-write + + + RUN + Enable this module to run. + 0 + 1 + read-write + + + + + RX_CFGR + Configuration Register + 0xc + 32 + 0x00000000 + 0x000007C0 + + + CH_MAX + CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +4'h2: 2 channels +4'h4: 4 channels +etc + 6 + 5 + read-write + + + + + RXSLT + RX Slot Control Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + EN + Slot enable for the channels. + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + PDM + PDM + PDM + 0xf0114000 + + 0x0 + 0x34 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x809FF7FF + + + SFTRST + software reset the module. Self-clear. + 31 + 1 + read-write + + + SOF_FEDGE + asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. + 23 + 1 + read-write + + + USE_COEF_RAM + Asserted to use Coef RAM instead of Coef ROM + 20 + 1 + read-write + + + FILT_CRX_ERR_IE + data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. + 19 + 1 + read-write + + + OFIFO_OVFL_ERR_IE + output fifo overflow error interrupt enable + 18 + 1 + read-write + + + CIC_OVLD_ERR_IE + CIC overload error interrupt enable + 17 + 1 + read-write + + + CIC_SAT_ERR_IE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 16 + 1 + read-write + + + DEC_AFT_CIC + decimation rate after CIC. Now it is forced to be 3. + 12 + 4 + read-write + + + CAPT_DLY + Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + 7 + 4 + read-write + + + PDM_CLK_HFDIV + The clock divider will work at least 4. +0: div-by-2, +1: div-by-4 +. . . +n: div-by-2*(n+1) + 3 + 4 + read-write + + + PDM_CLK_DIV_BYPASS + asserted to bypass the pdm clock divider + 2 + 1 + read-write + + + PDM_CLK_OE + pdm_clk_output_en + 1 + 1 + read-write + + + HPF_EN + pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. + 0 + 1 + read-write + + + + + CH_CTRL + Channel Control Register + 0x4 + 32 + 0x00000000 + 0x00FF03FF + + + CH_POL + Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + 16 + 8 + read-write + + + CH_EN + Asserted to enable the channel. +Ch8 & 9 are refs. +Ch0-7 are pdm mics. + 0 + 10 + read-write + + + + + ST + Status Register + 0x8 + 32 + 0x00000000 + 0x0000000F + + + FILT_CRX_ERR + data accessed out of boundary error + 3 + 1 + read-write + + + OFIFO_OVFL_ERR + output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. + 2 + 1 + read-write + + + CIC_OVLD_ERR + CIC overload error. write 1 clear + 1 + 1 + read-write + + + CIC_SAT_ERR + CIC saturation. Write 1 clear + 0 + 1 + read-write + + + + + CH_CFG + Channel Configuration Register + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + CH9_TYPE + No description avaiable + 18 + 2 + read-write + + + CH8_TYPE + No description avaiable + 16 + 2 + read-write + + + CH7_TYPE + No description avaiable + 14 + 2 + read-write + + + CH6_TYPE + No description avaiable + 12 + 2 + read-write + + + CH5_TYPE + No description avaiable + 10 + 2 + read-write + + + CH4_TYPE + No description avaiable + 8 + 2 + read-write + + + CH3_TYPE + No description avaiable + 6 + 2 + read-write + + + CH2_TYPE + No description avaiable + 4 + 2 + read-write + + + CH1_TYPE + No description avaiable + 2 + 2 + read-write + + + CH0_TYPE + Type of Channel 0 +2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) +2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) + 0 + 2 + read-write + + + + + CIC_CFG + CIC configuration register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + POST_SCALE + the shift value after CIC results. + 10 + 6 + read-write + + + SGD + Sigma_delta_order[1:0] +2'b00: 7 +2'b01: 6 +2'b10: 5 +Others: unused + 8 + 2 + read-write + + + CIC_DEC_RATIO + CIC decimation factor + 0 + 8 + read-write + + + + + CTRL_INBUF + In Buf Control Register + 0x14 + 32 + 0x00000000 + 0x3FFFFFFF + + + MAX_PTR + The buf size-1 for each channel + 22 + 8 + read-write + + + PITCH + The spacing between starting address of adjacent channels + 11 + 11 + read-write + + + START_ADDR + The starting address of channel 0 in filter data buffer + 0 + 11 + read-write + + + + + CTRL_FILT0 + Filter 0 Control Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M0 + Coef length of filter type 2'b00 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b00 in coef memory + 0 + 8 + read-write + + + + + CTRL_FILT1 + Filter 1 Control Register + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M1 + Coef length of filter type 2'b01 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b01 in coef memory + 0 + 8 + read-write + + + + + RUN + Run Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + PDM_EN + Asserted to enable the module + 0 + 1 + read-write + + + + + MEMADDR + Memory Access Address + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + 0--0x0FFFFFFF: COEF_RAM +0x10000000--0x1FFFFFFF: DATA_RAM + 0 + 32 + read-write + + + + + MEMDATA + Memory Access Data + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + The data write-to/read-from buffer + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + PWM0 + PWM0 + PWM + 0xf0200000 + + 0x0 + 0x290 + registers + + + + UNLK + Shadow registers unlock register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHUNLK + write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written. + 0 + 32 + read-write + + + + + STA + Counter start register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + XSTA + pwm timer counter extended start point, should back to this value after reach xrld + 28 + 4 + read-write + + + STA + pwm timer counter start value + sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk + 4 + 24 + read-write + + + RESERVED + reserved + 0 + 4 + read-write + + + + + RLD + Counter reload register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + XRLD + timeout counter extended reload point, counter will reload to xsta after reach this point + 28 + 4 + read-write + + + RLD + pwm timer counter reload value + 4 + 24 + read-write + + + RESERVED + reserved + 0 + 4 + read-write + + + + + CMP_0 + Comparator register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_1 + Comparator register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_2 + Comparator register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_3 + Comparator register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_4 + Comparator register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_5 + Comparator register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_6 + Comparator register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_7 + Comparator register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_8 + Comparator register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_9 + Comparator register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_10 + Comparator register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_11 + Comparator register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_12 + Comparator register + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_13 + Comparator register + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_14 + Comparator register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_15 + Comparator register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_16 + Comparator register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_17 + Comparator register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_18 + Comparator register + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_19 + Comparator register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_20 + Comparator register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_21 + Comparator register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_22 + Comparator register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_23 + Comparator register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + FRCMD + Force output mode register + 0x78 + 32 + 0x00000000 + 0x0000FFFF + + + FRCMD + 2bit for each PWM output channel (0~7); +00: force output 0 +01: force output 1 +10: output highz +11: no force + 0 + 16 + read-write + + + + + SHLK + Shadow registers lock register + 0x7c + 32 + 0x00000000 + 0x80000000 + + + SHLK + write 1 to lock all shawdow register, wirte access is not permitted + 31 + 1 + read-write + + + + + CHCFG_0 + Output channel configure register + 0x80 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_1 + Output channel configure register + 0x84 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_2 + Output channel configure register + 0x88 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_3 + Output channel configure register + 0x8c + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_4 + Output channel configure register + 0x90 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_5 + Output channel configure register + 0x94 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_6 + Output channel configure register + 0x98 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_7 + Output channel configure register + 0x9c + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_8 + Output channel configure register + 0xa0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_9 + Output channel configure register + 0xa4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_10 + Output channel configure register + 0xa8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_11 + Output channel configure register + 0xac + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_12 + Output channel configure register + 0xb0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_13 + Output channel configure register + 0xb4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_14 + Output channel configure register + 0xb8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_15 + Output channel configure register + 0xbc + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_16 + Output channel configure register + 0xc0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_17 + Output channel configure register + 0xc4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_18 + Output channel configure register + 0xc8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_19 + Output channel configure register + 0xcc + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_20 + Output channel configure register + 0xd0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_21 + Output channel configure register + 0xd4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_22 + Output channel configure register + 0xd8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_23 + Output channel configure register + 0xdc + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + GCR + Global control register + 0xf0 + 32 + 0x00000000 + 0xFDFFFFE7 + + + FAULTI3EN + 1- enable the internal fault input 3 + 31 + 1 + read-write + + + FAULTI2EN + 1- enable the internal fault input 2 + 30 + 1 + read-write + + + FAULTI1EN + 1- enable the internal fault input 1 + 29 + 1 + read-write + + + FAULTI0EN + 1- enable the internal fault input 0 + 28 + 1 + read-write + + + DEBUGFAULT + 1- enable debug mode output protection + 27 + 1 + read-write + + + FRCPOL + polarity of input pwm_force, +1- active low +0- active high + 26 + 1 + read-write + + + HWSHDWEDG + When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as shadow register hardware load event. +1- Falling edge +0- Rising edge + 24 + 1 + read-write + + + CMPSHDWSEL + This bitfield select one of the comparators as hardware event time to load comparator shadow registers + 19 + 5 + read-write + + + FAULTRECEDG + When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. +1- Falling edge +0- Rising edge + 18 + 1 + read-write + + + FAULTRECHWSEL + Selec one of the 24 comparators as fault output recover trigger. + 13 + 5 + read-write + + + FAULTE1EN + 1- enable the external fault input 1 + 12 + 1 + read-write + + + FAULTE0EN + 1- enable the external fault input 0 + 11 + 1 + read-write + + + FAULTEXPOL + external fault polarity +1-active low +0-active high + 9 + 2 + read-write + + + RLDSYNCEN + 1- pwm timer counter reset to reload value (rld) by synci is enabled + 8 + 1 + read-write + + + CEN + 1- enable the pwm timer counter +0- stop the pwm timer counter + 7 + 1 + read-write + + + FAULTCLR + 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + 6 + 1 + read-write + + + XRLDSYNCEN + 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled + 5 + 1 + read-write + + + FRCTIME + This bit field select the force effective time +00: force immediately +01: force at main counter reload time +10: force at FRCSYNCI +11: no force + 1 + 2 + read-write + + + SWFRC + 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect + 0 + 1 + read-write + + + + + SHCR + Shadow register control register + 0xf4 + 32 + 0x00000000 + 0x00001FFF + + + FRCSHDWSEL + This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers + 8 + 5 + read-write + + + CNTSHDWSEL + This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) + 3 + 5 + read-write + + + CNTSHDWUPT + This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 1 + 2 + read-write + + + SHLKEN + 1- enable shadow registers lock feature, +0- disable shadow registers lock, shlk bit will always be 0 + 0 + 1 + read-write + + + + + CAPPOS_0 + Capture rising edge register + 0x100 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_1 + Capture rising edge register + 0x104 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_2 + Capture rising edge register + 0x108 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_3 + Capture rising edge register + 0x10c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_4 + Capture rising edge register + 0x110 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_5 + Capture rising edge register + 0x114 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_6 + Capture rising edge register + 0x118 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_7 + Capture rising edge register + 0x11c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_8 + Capture rising edge register + 0x120 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_9 + Capture rising edge register + 0x124 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_10 + Capture rising edge register + 0x128 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_11 + Capture rising edge register + 0x12c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_12 + Capture rising edge register + 0x130 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_13 + Capture rising edge register + 0x134 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_14 + Capture rising edge register + 0x138 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_15 + Capture rising edge register + 0x13c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_16 + Capture rising edge register + 0x140 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_17 + Capture rising edge register + 0x144 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_18 + Capture rising edge register + 0x148 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_19 + Capture rising edge register + 0x14c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_20 + Capture rising edge register + 0x150 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_21 + Capture rising edge register + 0x154 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_22 + Capture rising edge register + 0x158 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_23 + Capture rising edge register + 0x15c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CNT + Counter + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + RESERVED + read-only as 0 + 0 + 4 + read-only + + + + + CAPNEG_0 + Capture falling edge register + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_1 + Capture falling edge register + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_2 + Capture falling edge register + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_3 + Capture falling edge register + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_4 + Capture falling edge register + 0x190 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_5 + Capture falling edge register + 0x194 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_6 + Capture falling edge register + 0x198 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_7 + Capture falling edge register + 0x19c + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_8 + Capture falling edge register + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_9 + Capture falling edge register + 0x1a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_10 + Capture falling edge register + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_11 + Capture falling edge register + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_12 + Capture falling edge register + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_13 + Capture falling edge register + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_14 + Capture falling edge register + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_15 + Capture falling edge register + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_16 + Capture falling edge register + 0x1c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_17 + Capture falling edge register + 0x1c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_18 + Capture falling edge register + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_19 + Capture falling edge register + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_20 + Capture falling edge register + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_21 + Capture falling edge register + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_22 + Capture falling edge register + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_23 + Capture falling edge register + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CNTCOPY + Counter copy + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + RESERVED + read-only as 0 + 0 + 4 + read-only + + + + + PWMCFG_0 + PWM channel configure register + 0x200 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_1 + PWM channel configure register + 0x204 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_2 + PWM channel configure register + 0x208 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_3 + PWM channel configure register + 0x20c + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_4 + PWM channel configure register + 0x210 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_5 + PWM channel configure register + 0x214 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_6 + PWM channel configure register + 0x218 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_7 + PWM channel configure register + 0x21c + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + SR + Status register + 0x220 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTF + fault condition flag + 27 + 1 + read-write + + + XRLDF + extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + 26 + 1 + read-write + + + HALFRLDF + half reload flag, this flag set when cnt count to rld/2 + 25 + 1 + read-write + + + RLDF + reload flag, this flag set when cnt count to rld value or when SYNCI assert + 24 + 1 + read-write + + + CMPFX + comparator output compare or input capture flag + 0 + 24 + read-write + + + + + IRQEN + Interrupt request enable register + 0x224 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTIRQE + fault condition interrupt enable + 27 + 1 + read-write + + + XRLDIRQE + extended reload flag interrupt enable + 26 + 1 + read-write + + + HALFRLDIRQE + half reload flag interrupt enable + 25 + 1 + read-write + + + RLDIRQE + reload flag interrupt enable + 24 + 1 + read-write + + + CMPIRQEX + comparator output compare or input capture flag interrupt enable + 0 + 24 + read-write + + + + + DMAEN + DMA request enable register + 0x22c + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTEN + fault condition DMA request enable + 27 + 1 + read-write + + + XRLDEN + extended reload flag DMA request enable + 26 + 1 + read-write + + + HALFRLDEN + half reload flag DMA request enable + 25 + 1 + read-write + + + RLDEN + reload flag DMA request enable + 24 + 1 + read-write + + + CMPENX + comparator output compare or input capture flag DMA request enable + 0 + 24 + read-write + + + + + CMPCFG_CMPCFG0 + Comparator configure register + 0x230 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_1 + Comparator configure register + 0x234 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_2 + Comparator configure register + 0x238 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_3 + Comparator configure register + 0x23c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_4 + Comparator configure register + 0x240 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_5 + Comparator configure register + 0x244 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_6 + Comparator configure register + 0x248 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_7 + Comparator configure register + 0x24c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_8 + Comparator configure register + 0x250 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_9 + Comparator configure register + 0x254 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_10 + Comparator configure register + 0x258 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_11 + Comparator configure register + 0x25c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_12 + Comparator configure register + 0x260 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_13 + Comparator configure register + 0x264 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_14 + Comparator configure register + 0x268 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_15 + Comparator configure register + 0x26c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_16 + Comparator configure register + 0x270 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_17 + Comparator configure register + 0x274 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_18 + Comparator configure register + 0x278 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_19 + Comparator configure register + 0x27c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_20 + Comparator configure register + 0x280 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_21 + Comparator configure register + 0x284 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_22 + Comparator configure register + 0x288 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_23 + Comparator configure register + 0x28c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + + + PWM1 + PWM1 + PWM + 0xf0210000 + + + HALL0 + HALL0 + HALL + 0xf0204000 + + 0x0 + 0x8c + registers + + + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0x8001083F + + + READ + 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + RESERVED + reserved + 16 + 1 + read-write + + + SNAPEN + 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert + 11 + 1 + read-write + + + RESERVED + reserved + 5 + 1 + read-write + + + RSTCNT + set to reset all counter and related snapshots + 4 + 1 + read-write + + + RESERVED + reserved + 2 + 2 + read-write + + + RESERVED + reserved + 0 + 2 + read-write + + + + + PHCFG + Phase configure register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DLYSEL + This bit select delay start time: +1- start counting delay after pre-trigger +0- start counting delay after u,v,w toggle + 31 + 1 + read-write + + + RESERVED + reserved + 24 + 7 + read-write + + + DLYCNT + delay clock cycles number + 0 + 24 + read-write + + + + + WDGCFG + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + UVWCFG + U,V,W configure register + 0xc + 32 + 0x00000000 + 0x07FFFFFF + + + RESERVED + reserved + 24 + 3 + read-write + + + PRECNT + the clock cycle number which the pre flag will set before the next uvw transition + 0 + 24 + read-write + + + + + TRGOEN + Trigger output enable register + 0x10 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- enable trigger output when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- enable trigger output when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- enable trigger output when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFEN + 1- enable trigger output when u flag set + 23 + 1 + read-write + + + VFEN + 1- enable trigger output when v flag set + 22 + 1 + read-write + + + WFEN + 1- enable trigger output when w flag set + 21 + 1 + read-write + + + + + READEN + Read event enable register + 0x14 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- load counters to their read registers when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- load counters to their read registers when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- load counters to their read registers when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFEN + 1- load counters to their read registers when u flag set + 23 + 1 + read-write + + + VFEN + 1- load counters to their read registers when v flag set + 22 + 1 + read-write + + + WFEN + 1- load counters to their read registers when w flag set + 21 + 1 + read-write + + + + + DMAEN + DMA enable register + 0x24 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- generate dma request when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- generate dma request when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- generate dma request when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFEN + 1- generate dma request when u flag set + 23 + 1 + read-write + + + VFEN + 1- generate dma request when v flag set + 22 + 1 + read-write + + + WFEN + 1- generate dma request when w flag set + 21 + 1 + read-write + + + + + SR + Status register + 0x28 + 32 + 0x00000000 + 0xFFE00000 + + + WDGF + watchdog count timeout flag + 31 + 1 + read-write + + + PHUPTF + phase update flag, will set when any of u, v, w signal toggle + 30 + 1 + read-write + + + PHPREF + phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle + 29 + 1 + read-write + + + PHDLYF + phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UF + u flag, will set when u signal toggle + 23 + 1 + read-write + + + VF + v flag, will set when v signal toggle + 22 + 1 + read-write + + + WF + w flag, will set when w signal toggle + 21 + 1 + read-write + + + + + IRQEN + Interrupt request enable register + 0x2c + 32 + 0x00000000 + 0xFFE00000 + + + WDGIE + 1- generate interrupt request when wdg flag set + 31 + 1 + read-write + + + PHUPTIE + 1- generate interrupt request when phupt flag set + 30 + 1 + read-write + + + PHPREIE + 1- generate interrupt request when phpre flag set + 29 + 1 + read-write + + + PHDLYIE + 1- generate interrupt request when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFIE + 1- generate interrupt request when u flag set + 23 + 1 + read-write + + + VFIE + 1- generate interrupt request when v flag set + 22 + 1 + read-write + + + WFIE + 1- generate interrupt request when w flag set + 21 + 1 + read-write + + + + + COUNT_CURRENT_W + W counter + 0x30 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_CURRENT_V + V counter + 0x34 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_CURRENT_U + U counter + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_CURRENT_TMR + Timer counter + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_READ_W + W read register + 0x40 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_READ_V + V read register + 0x44 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_READ_U + U read register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_READ_TMR + Timer read register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP0_W + W snap register 0 + 0x50 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP0_V + V snap register 0 + 0x54 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP0_U + Usnap register 0 + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP0_TMR + Timer snap register 0 + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP1_W + W snap register 1 + 0x60 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP1_V + V snap register 1 + 0x64 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP1_U + U snap register 1 + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP1_TMR + Timer snap register 1 + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + HIS_U_HIS0 + history register 0 + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + HIS_U_HIS1 + history register 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + HIS_V_HIS0 + V histroy register 0 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + HIS_V_HIS1 + V histroy register 1 + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + HIS_W_HIS0 + W histroy register 0 + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + HIS_W_HIS1 + W histroy register 1 + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + + + HALL1 + HALL1 + HALL + 0xf0214000 + + + QEI0 + QEI0 + QEI + 0xf0208000 + + 0x0 + 0x80 + registers + + + + CR + Control register + 0x0 + 32 + 0x00000000 + 0x80077F3F + + + READ + 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + HRSTSPD + 1- reset spdcnt when H assert + 18 + 1 + read-write + + + HRSTPH + 1- reset phcnt when H assert + 17 + 1 + read-write + + + HRSTZ + 1- reset zcnt when H assert + 16 + 1 + read-write + + + PAUSESPD + 1- pause spdcnt when PAUSE assert + 14 + 1 + read-write + + + PAUSEPH + 1- pause phcnt when PAUSE assert + 13 + 1 + read-write + + + PAUSEZ + 1- pause zcnt when PAUSE assert + 12 + 1 + read-write + + + HRDIR1 + 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + 11 + 1 + read-write + + + HRDIR0 + 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + 10 + 1 + read-write + + + HFDIR1 + 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + 9 + 1 + read-write + + + HFDIR0 + 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + 8 + 1 + read-write + + + SNAPEN + 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + 5 + 1 + read-write + + + RSTCNT + 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + 4 + 1 + read-write + + + RESERVED + 00-x1, phase_cnt will increase at each A posedge +01-x2, phase_cnt will increase at each A/B posedge +10-x4, phase_cnt will increase at each edge(A/B, pos/neg) + 2 + 2 + read-write + + + ENCTYP + 00-abz; 01-pd; 10-ud; 11-reserved + 0 + 2 + read-write + + + + + PHCFG + Phase configure register + 0x4 + 32 + 0x00000000 + 0x007FFFFF + + + ZCNTCFG + 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 +0- zcnt will increment or decrement when Z input assert + 22 + 1 + read-write + + + PHCALIZ + 1- phcnt will set to phidx when Z input assert + 21 + 1 + read-write + + + PHMAX + maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + 0 + 21 + read-write + + + + + WDGCFG + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + PHIDX + Phase index register + 0xc + 32 + 0x00000000 + 0x001FFFFF + + + PHIDX + phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + 0 + 21 + read-write + + + + + TRGOEN + Tigger output enable register + 0x10 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- enable trigger output when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- enable trigger output when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- enable trigger output when zphf flag set + 28 + 1 + read-write + + + + + READEN + Read event enable register + 0x14 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- load counters to their read registers when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- load counters to their read registers when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- load counters to their read registers when zphf flag set + 28 + 1 + read-write + + + + + ZCMP + Z comparator + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCMP + zcnt postion compare value + 0 + 32 + read-write + + + + + PHCMP + Phase comparator + 0x1c + 32 + 0x00000000 + 0xE01FFFFF + + + ZCMPDIS + 1- postion compare not include zcnt + 31 + 1 + read-write + + + DIRCMPDIS + 1- postion compare not include rotation direction + 30 + 1 + read-write + + + DIRCMP + 0- position compare need positive rotation +1- position compare need negative rotation + 29 + 1 + read-write + + + PHCMP + phcnt position compare value + 0 + 21 + read-write + + + + + SPDCMP + Speed comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDCMP + spdcnt position compare value + 0 + 32 + read-write + + + + + DMAEN + DMA request enable register + 0x24 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- generate dma request when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- generate dma request when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- generate dma request when zphf flag set + 28 + 1 + read-write + + + + + SR + Status register + 0x28 + 32 + 0x00000000 + 0xF0000000 + + + WDGF + watchdog flag + 31 + 1 + read-write + + + HOMEF + home flag + 30 + 1 + read-write + + + POSCMPF + postion compare match flag + 29 + 1 + read-write + + + ZPHF + z input flag + 28 + 1 + read-write + + + + + IRQEN + Interrupt request register + 0x2c + 32 + 0x00000000 + 0xF0000000 + + + WDGIE + 1- generate interrupt when wdg flag set + 31 + 1 + read-write + + + HOMEIE + 1- generate interrupt when homef flag set + 30 + 1 + read-write + + + POSCMPIE + 1- generate interrupt when poscmpf flag set + 29 + 1 + read-write + + + ZPHIE + 1- generate interrupt when zphf flag set + 28 + 1 + read-write + + + + + COUNT_CURRENT_Z + Z counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_CURRENT_PH + Phase counter + 0x34 + 32 + 0x00000000 + 0xC61FFFFF + + + RESERVE + reversed + 31 + 1 + read-only + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_CURRENT_SPD + Speed counter + 0x38 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_CURRENT_TMR + Timer counter + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_READ_Z + Z counter + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_READ_PH + Phase counter + 0x44 + 32 + 0x00000000 + 0xC61FFFFF + + + RESERVE + reversed + 31 + 1 + read-only + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_READ_SPD + Speed counter + 0x48 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_READ_TMR + Timer counter + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP0_Z + Z snap register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_SNAP0_PH + Phase snap register + 0x54 + 32 + 0x00000000 + 0xC61FFFFF + + + RESERVE + reversed + 31 + 1 + read-only + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_SNAP0_SPD + Speed snap register + 0x58 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_SNAP0_TMR + Timer snap register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP1_Z + Z snap register 1 + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_SNAP1_PH + Phase snap register 1 + 0x64 + 32 + 0x00000000 + 0xC61FFFFF + + + RESERVE + reversed + 31 + 1 + read-only + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_SNAP1_SPD + Speed snap register 1 + 0x68 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_SNAP1_TMR + Timer snap register 1 + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS0 + Speed history + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS1 + Speed history 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS2 + Speed history 2 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS3 + Speed history 3 + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + + + QEI1 + QEI1 + QEI + 0xf0218000 + + + TRGM0 + TRGM0 + TRGM + 0xf020c000 + + 0x0 + 0x404 + registers + + + + FILTCFG_PWM_IN0 + Filter configure register + 0x0 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN1 + Filter configure register + 0x4 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN2 + Filter configure register + 0x8 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN3 + Filter configure register + 0xc + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN4 + Filter configure register + 0x10 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN5 + Filter configure register + 0x14 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN6 + Filter configure register + 0x18 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN7 + Filter configure register + 0x1c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN0 + Filter configure register + 0x20 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN1 + Filter configure register + 0x24 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN2 + Filter configure register + 0x28 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN3 + Filter configure register + 0x2c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN4 + Filter configure register + 0x30 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN5 + Filter configure register + 0x34 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN6 + Filter configure register + 0x38 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN7 + Filter configure register + 0x3c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN8 + Filter configure register + 0x40 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN9 + Filter configure register + 0x44 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN10 + Filter configure register + 0x48 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN11 + Filter configure register + 0x4c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + TRGOCFG_TRGM_OUT0 + Trigger manager output configure register + 0x100 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT1 + Trigger manager output configure register + 0x104 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT2 + Trigger manager output configure register + 0x108 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT3 + Trigger manager output configure register + 0x10c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT4 + Trigger manager output configure register + 0x110 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT5 + Trigger manager output configure register + 0x114 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT6 + Trigger manager output configure register + 0x118 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT7 + Trigger manager output configure register + 0x11c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT8 + Trigger manager output configure register + 0x120 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT9 + Trigger manager output configure register + 0x124 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT10 + Trigger manager output configure register + 0x128 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT11 + Trigger manager output configure register + 0x12c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUTX0 + Trigger manager output configure register + 0x130 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUTX1 + Trigger manager output configure register + 0x134 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_SYNCI + Trigger manager output configure register + 0x138 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FRCI + Trigger manager output configure register + 0x13c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FRCSYNCI + Trigger manager output configure register + 0x140 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_SHRLDSYNCI + Trigger manager output configure register + 0x144 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FAULTI0 + Trigger manager output configure register + 0x148 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FAULTI1 + Trigger manager output configure register + 0x14c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FAULTI2 + Trigger manager output configure register + 0x150 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FAULTI3 + Trigger manager output configure register + 0x154 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN8 + Trigger manager output configure register + 0x158 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN9 + Trigger manager output configure register + 0x15c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN10 + Trigger manager output configure register + 0x160 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN11 + Trigger manager output configure register + 0x164 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN12 + Trigger manager output configure register + 0x168 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN13 + Trigger manager output configure register + 0x16c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN14 + Trigger manager output configure register + 0x170 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN15 + Trigger manager output configure register + 0x174 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN16 + Trigger manager output configure register + 0x178 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN17 + Trigger manager output configure register + 0x17c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN18 + Trigger manager output configure register + 0x180 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN19 + Trigger manager output configure register + 0x184 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN20 + Trigger manager output configure register + 0x188 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN21 + Trigger manager output configure register + 0x18c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN22 + Trigger manager output configure register + 0x190 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN23 + Trigger manager output configure register + 0x194 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_A + Trigger manager output configure register + 0x198 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_B + Trigger manager output configure register + 0x19c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_Z + Trigger manager output configure register + 0x1a0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_H + Trigger manager output configure register + 0x1a4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_PAUSE + Trigger manager output configure register + 0x1a8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_SNAPI + Trigger manager output configure register + 0x1ac + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_HALL_U + Trigger manager output configure register + 0x1b0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_HALL_V + Trigger manager output configure register + 0x1b4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_HALL_W + Trigger manager output configure register + 0x1b8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_HALL_SNAPI + Trigger manager output configure register + 0x1bc + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADC0_STRGI + Trigger manager output configure register + 0x1c0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADC1_STRGI + Trigger manager output configure register + 0x1c4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADC2_STRGI + Trigger manager output configure register + 0x1c8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADC3_STRGI + Trigger manager output configure register + 0x1cc + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADCX_PTRGI0A + Trigger manager output configure register + 0x1d0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADCX_PTRGI0B + Trigger manager output configure register + 0x1d4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADCX_PTRGI0C + Trigger manager output configure register + 0x1d8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRA_SYNCI + Trigger manager output configure register + 0x1dc + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRA_IN2 + Trigger manager output configure register + 0x1e0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRA_IN3 + Trigger manager output configure register + 0x1e4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRB_SYNCI + Trigger manager output configure register + 0x1e8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRB_IN2 + Trigger manager output configure register + 0x1ec + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRB_IN3 + Trigger manager output configure register + 0x1f0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_CMPX_WIN + Trigger manager output configure register + 0x1f4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_CAN_PTPC0_CAP + Trigger manager output configure register + 0x1f8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_CAN_PTPC1_CAP + Trigger manager output configure register + 0x1fc + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + DMACFG_0 + DMA request configure register + 0x200 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + DMACFG_1 + DMA request configure register + 0x204 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + DMACFG_2 + DMA request configure register + 0x208 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + DMACFG_3 + DMA request configure register + 0x20c + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + GCR + General Control Register + 0x400 + 32 + 0x00000000 + 0x00000FFF + + + TRGOPEN + The bitfield enable the TRGM outputs. + 0 + 12 + read-write + + + + + + + TRGM1 + TRGM1 + TRGM + 0xf021c000 + + + SYNT + SYNT + SYNT + 0xf0240000 + + 0x0 + 0x30 + registers + + + + GCR + Global control register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + CRST + 1- Reset counter + 1 + 1 + read-write + + + CEN + 1- Enable counter + 0 + 1 + read-write + + + + + RLD + Counter reload register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + counter reload value + 0 + 32 + read-write + + + + + CNT + Counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT + counter + 0 + 32 + read-only + + + + + CMP_0 + Comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + CMP_1 + Comparator + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + CMP_2 + Comparator + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + CMP_3 + Comparator + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + + + ENET0 + ENET0 + ENET + 0xf2000000 + + 0x0 + 0x3028 + registers + + + + MACCFG + MAC Configuration Register + 0x0 + 32 + 0x00000000 + 0x7FFFFFFF + + + SARC + Source Address Insertion or Replacement Control + This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: +- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. +- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. +- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. Note: - Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. + 28 + 3 + read-write + + + TWOKPE + IEEE 802.3as Support for 2K Packets + When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status. + 27 + 1 + read-write + + + SFTERR + SMII Force Transmit Error + When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. + 26 + 1 + read-write + + + CST + CRC Stripping for Type Frames + When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. + 25 + 1 + read-write + + + TC + Transmit Configuration in RGMII, SGMII, or SMII + When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. + 24 + 1 + read-write + + + WD + Watchdog Disable + When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. + 23 + 1 + read-write + + + JD + Jabber Disable + When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. + 22 + 1 + read-write + + + BE + Frame Burst Enable + When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. + 21 + 1 + read-write + + + JE + Jumbo Frame Enable + When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. + 20 + 1 + read-write + + + IFG + Inter-Frame Gap + These bits control the minimum IFG between frames during transmission. +- 000: 96 bit times +- 001: 88 bit times +- 010: 80 bit times - ... +- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. + 17 + 3 + read-write + + + DCRS + Disable Carrier Sense During Transmission + When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. + 16 + 1 + read-write + + + PS + Port Select + This bit selects the Ethernet line speed. +- 0: For 1000 Mbps operations +- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. + 15 + 1 + read-write + + + FES + Speed + This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: +- 0: 10 Mbps +- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. + 14 + 1 + read-write + + + DO + Disable Receive Own + When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. + 13 + 1 + read-write + + + LM + Loopback Mode + When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. + 12 + 1 + read-write + + + DM + Duplex Mode + When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configuration. + 11 + 1 + read-write + + + IPC + Checksum Offload +When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. + 10 + 1 + read-write + + + DR + Disable Retry +When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). + 9 + 1 + read-write + + + LUD + Link Up or Down + This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: +- 0: Link Down +- 1: Link Up + 8 + 1 + read-write + + + ACS + Automatic Pad or CRC Stripping + When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. + 7 + 1 + read-write + + + BL + Back-Off Limit + The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. +- 00: k= min (n, 10) +- 01: k = min (n, 8) +- 10: k = min (n, 4) +- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k + 5 + 2 + read-write + + + DC + Deferral Check + When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. + 4 + 1 + read-write + + + TE + Transmitter Enable + When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. + 3 + 1 + read-write + + + RE + Receiver Enable + When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. + 2 + 1 + read-write + + + PRELEN + Preamble Length for Transmit frames + These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. +- 2'b00: 7 bytes of preamble +- 2'b01: 5 bytes of preamble +- 2'b10: 3 bytes of preamble +- 2'b11: Reserved + 0 + 2 + read-write + + + + + MACFF + MAC Frame Filter + 0x4 + 32 + 0x00000000 + 0x803087FF + + + RA + Receive All + When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. + 31 + 1 + read-write + + + DNTU + Drop non-TCP/UDP over IP Frames + When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. + 21 + 1 + read-write + + + IPFE + Layer 3 and Layer 4 Filter Enable + When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. + 20 + 1 + read-write + + + VTFE + VLAN Tag Filter Enable + When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. + 15 + 1 + read-write + + + HPF + Hash or Perfect Filter + When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. + 10 + 1 + read-write + + + SAF + Source Address Filter Enable + When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. + 9 + 1 + read-write + + + SAIF + SA Inverse Filtering +When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. + 8 + 1 + read-write + + + PCF + Pass Control Frames + These bits control the forwarding of all control frames (including unicast and multicast Pause frames). +- 00: MAC filters all control frames from reaching the application. +- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. +- 10: MAC forwards all control frames to application even if they fail the Address Filter. +- 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing: - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). + 6 + 2 + read-write + + + DBF + Disable Broadcast Frames + When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. + 5 + 1 + read-write + + + PM + Pass All Multicast +When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. + 4 + 1 + read-write + + + DAIF + DA Inverse Filtering + When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. + 3 + 1 + read-write + + + HMC + Hash Multicast +When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. + 2 + 1 + read-write + + + HUC + Hash Unicast + When set, the MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. + 1 + 1 + read-write + + + PR + Promiscuous Mode +When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. + 0 + 1 + read-write + + + + + HASH_H + Hash Table High Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HTH + Hash Table High + This field contains the upper 32 bits of the Hash table. + 0 + 32 + read-write + + + + + HASH_L + Hash Table Low Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + HTL + Hash Table Low + This field contains the lower 32 bits of the Hash table. + 0 + 32 + read-write + + + + + GMII_ADDR + GMII Address Register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + PA + Physical Layer Address + This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. + 11 + 5 + read-write + + + GR + GMII Register + These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. + 6 + 5 + read-write + + + CR + CSR Clock Range + The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. +- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. +- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. +- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. +- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. +- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. +- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. +- 0110, 0111: Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. +- 1000: CSR clock/4 +- 1001: CSR clock/6 +- 1010: CSR clock/8 +- 1011: CSR clock/10 +- 1100: CSR clock/12 +- 1101: CSR clock/14 +- 1110: CSR clock/16 +- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. + 2 + 4 + read-write + + + GW + GMII Write + When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. + 1 + 1 + read-write + + + GB + GMII Busy + This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. + 0 + 1 + read-write + + + + + GMII_DATA + GMII Data Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + GD + GMII Data + This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. + 0 + 16 + read-write + + + + + FLOWCTRL + Flow Control Register + 0x18 + 32 + 0x00000000 + 0xFFFF00BF + + + PT + Pause Time + This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. + 16 + 16 + read-write + + + DZPQ + Disable Zero-Quanta Pause + When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. + 7 + 1 + read-write + + + PLT + Pause Low Threshold + This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: +- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). +- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). +- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). +- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. + 4 + 2 + read-write + + + UP + Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. + 3 + 1 + read-write + + + RFE + Receive Flow Control Enable + When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. + 2 + 1 + read-write + + + TFE + Transmit Flow Control Enable +In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. + 1 + 1 + read-write + + + FCB_BPA + Flow Control Busy or Backpressure Activate + This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. + 0 + 1 + read-write + + + + + VLAN_TAG + VLAN Tag Register + 0x1c + 32 + 0x00000000 + 0x000FFFFF + + + VTHM + VLAN Tag Hash Table Match Enable + When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. + 19 + 1 + read-write + + + ESVL + Enable S-VLAN + When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. + 18 + 1 + read-write + + + VTIM + VLAN Tag Inverse Match Enable +When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. + 17 + 1 + read-write + + + ETV + Enable 12-Bit VLAN Tag Comparison + When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. + 16 + 1 + read-write + + + VL + VLAN Tag Identifier for Receive Frames + This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: - Bits [15:13]: User Priority - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. + 0 + 16 + read-write + + + + + VERSION + Version Register + 0x20 + 32 + 0x00000000 + 0x0000FFFF + + + USERVER + User-defined Version + 8 + 8 + read-only + + + SNPSVER + Synopsys-defined Version (3.7) + 0 + 8 + read-only + + + + + DEBUGGING + Debug Register + 0x24 + 32 + 0x00000000 + 0x037F0377 + + + TXSTSFSTS + MTL TxStatus FIFO Full Status + When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. + 25 + 1 + read-only + + + TXFSTS + MTL Tx FIFO Not Empty Status +When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. + 24 + 1 + read-only + + + TWCSTS + MTL Tx FIFO Write Controller Status +When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. + 22 + 1 + read-only + + + TRCSTS + MTL Tx FIFO Read Controller Status +This field indicates the state of the Tx FIFO Read Controller: +- 00: IDLE state +- 01: READ state (transferring data to the MAC transmitter) +- 10: Waiting for TxStatus from the MAC transmitter +- 11: Writing the received TxStatus or flushing the Tx FIFO + 20 + 2 + read-only + + + TXPAUSED + MAC Transmitter in Pause +When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-only mode) and hence does not schedule any frame for transmission. + 19 + 1 + read-only + + + TFCSTS + MAC Transmit Frame Controller Status +This field indicates the state of the MAC Transmit Frame Controller module: +- 00: IDLE state +- 01: Waiting for status of previous frame or IFG or backoff period to be over +- 10: Generating and transmitting a Pause frame (in the full-duplex mode) +- 11: Transferring input frame for transmission + 17 + 2 + read-only + + + TPESTS + MAC GMII or MII Transmit Protocol Engine Status + When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. + 16 + 1 + read-only + + + RXFSTS + MTL RxFIFO Fill-Level Status +This field gives the status of the fill-level of the Rx FIFO: +- 00: Rx FIFO Empty +- 01: Rx FIFO fill-level below flow-control deactivate threshold +- 10: Rx FIFO fill-level above flow-control activate threshold +- 11: Rx FIFO Full + 8 + 2 + read-only + + + RRCSTS + MTL RxFIFO Read Controller State +This field gives the state of the Rx FIFO read Controller: +- 00: IDLE state +- 01: Reading frame data +- 10: Reading frame status (or timestamp) +- 11: Flushing the frame data and status + 5 + 2 + read-only + + + RWCSTS + MTL Rx FIFO Write Controller Active Status + When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. + 4 + 1 + read-only + + + RFCFCSTS + MAC Receive Frame FIFO Controller Status + When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. - RFCFCSTS[1] represents the status of small FIFO Read controller. - RFCFCSTS[0] represents the status of small FIFO Write controller. + 1 + 2 + read-only + + + RPESTS + MAC GMII or MII Receive Protocol Engine Status +When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. + 0 + 1 + read-only + + + + + RWKFRMFILT + Remote Wake-Up Frame Filter Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + WKUPFRMFILT + This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers + 0 + 32 + read-write + + + + + PMT_CSR + PMT Control and Status Register + 0x2c + 32 + 0x00000000 + 0x9F000267 + + + RWKFILTRST + Remote Wake-Up Frame Filter Register Pointer Reset +When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. + 31 + 1 + read-write + + + RWKPTR + Remote Wake-up FIFO Pointer +This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. + 24 + 5 + read-write + + + GLBLUCAST + Global Unicast +When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. + 9 + 1 + read-write + + + RWKPRCVD + Remote Wake-Up Frame Received +When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. + 6 + 1 + read-write + + + MGKPRCVD + Magic Packet Received +When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. + 5 + 1 + read-write + + + RWKPKTEN + Remote Wake-Up Frame Enable +When set, enables generation of a power management event because of remote wake-up frame reception. + 2 + 1 + read-write + + + MGKPKTEN + Magic Packet Enable +When set, enables generation of a power management event because of magic packet reception. + 1 + 1 + read-write + + + PWRDWN + Power Down +When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. The frames, received by the MAC after this bit is cleared, are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. + 0 + 1 + read-write + + + + + LPI_CSR + LPI Control and Status Regsiter + 0x30 + 32 + 0x00000000 + 0x000F030F + + + LPITXA + LPI TX Automate +This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + 19 + 1 + read-write + + + PLSEN + PHY Link Status Enable +This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. + 18 + 1 + read-write + + + PLS + PHY Link Status +This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. + 17 + 1 + read-write + + + LPIEN + LPI Enable +When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + 16 + 1 + read-write + + + RLPIST + Receive LPI State +When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. + 9 + 1 + read-write + + + TLPIST + Transmit LPI State +When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. + 8 + 1 + read-write + + + RLPIEX + Receive LPI Exit +When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 3 + 1 + read-write + + + RLPIEN + Receive LPI Entry +When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 2 + 1 + read-write + + + TLPIEX + Transmit LPI Exit +When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. + 1 + 1 + read-write + + + TLPIEN + Transmit LPI Entry + When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. + 0 + 1 + read-write + + + + + LPI_TCR + LPI Timers Control Register + 0x34 + 32 + 0x00000000 + 0x03FFFFFF + + + LST + LPI LS TIMER +This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. + 16 + 10 + read-write + + + TWT + LPI TW TIMER +This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. + 0 + 16 + read-write + + + + + INTR_STATUS + Interrupt Status Register + 0x38 + 32 + 0x00000000 + 0x00000EFF + + + GPIIS + GPI Interrupt Status +When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved. + 11 + 1 + read-only + + + LPIIS + LPI Interrupt Status +When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. + 10 + 1 + read-only + + + TSIS + Timestamp Interrupt Status +When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - There is an overflow in the seconds register. - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). + 9 + 1 + read-only + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 7 + 1 + read-only + + + MMCTXIS + MMC Transmit Interrupt Status +This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 6 + 1 + read-only + + + MMCRXIS + MMC Receive Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 5 + 1 + read-only + + + MMCIS + MMC Interrupt Status +This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. + 4 + 1 + read-only + + + PMTIS + PMT Interrupt Status +This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. + 3 + 1 + read-only + + + PCSANCIS + PCS Auto-Negotiation Complete +This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. + 2 + 1 + read-only + + + PCSLCHGIS + PCS Link Status Changed +This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. + 1 + 1 + read-only + + + RGSMIIIS + RGMII or SMII Interrupt Status +This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. + 0 + 1 + read-only + + + + + INTR_MASK + Interrupt Mask Register + 0x3c + 32 + 0x00000000 + 0x0000060F + + + LPIIM + LPI Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). + 10 + 1 + read-write + + + TSIM + Timestamp Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). + 9 + 1 + read-write + + + PMTIM + PMT Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). + 3 + 1 + read-write + + + PCSANCIM + PCS AN Completion Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). + 2 + 1 + read-write + + + PCSLCHGIM + PCS Link Status Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). + 1 + 1 + read-write + + + RGSMIIIM + RGMII or SMII Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). + 0 + 1 + read-write + + + + + MAC_ADDR_0_HIGH + MAC Address 0 High Register + 0x40 + 32 + 0x00000000 + 0x8000FFFF + + + AE + Address Enable + This bit is always set to 1. + 31 + 1 + read-only + + + ADDRHI + MAC Address0 [47:32] + This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 16 + read-write + + + + + MAC_ADDR_0_LOW + MAC Address 0 Low Register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address0 [31:0] + This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 32 + read-write + + + + + MAC_ADDR_1_HIGH + MAC Address High Register + 0x48 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + MAC_ADDR_1_LOW + MAC Address Low Register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + MAC_ADDR_2_HIGH + MAC Address2 High Register + 0x50 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + MAC_ADDR_2_LOW + MAC Address2 Low Register + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + MAC_ADDR_3_HIGH + MAC Address3 High Register + 0x58 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + MAC_ADDR_3_LOW + MAC Address3 Low Register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + MAC_ADDR_4_HIGH + MAC Address4 High Register + 0x60 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + MAC_ADDR_4_LOW + MAC Address4 Low Register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + XMII_CSR + SGMII/RGMII/SMII Control and Status Register + 0xd8 + 32 + 0x00000000 + 0x0001003F + + + SMIDRXS + Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal. If the SMII PHY Interface with source synchronous mode is selected during core configuration, this bit is reserved (RO with default value). + 16 + 1 + read-only + + + FALSCARDET + False Carrier Detected + This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 5 + 1 + read-write + + + JABTO + Jabber Timeout + This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 4 + 1 + read-write + + + LNKSTS + Link Status + This bit indicates whether the link between the local PHY and the remote PHY is up or down. It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. + 3 + 1 + read-write + + + LNKSPEED + Link Speed + This bit indicates the current speed of the link: +- 00: 2.5 MHz +- 01: 25 MHz +- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. + 1 + 2 + read-write + + + LNKMOD + Link Mode + This bit indicates the current mode of operation of the link: +- 1’b0: Half-duplex mode +- 1’b1: Full-duplex mode + 0 + 1 + read-write + + + + + WDOG_WTO + Watchdog Timeout Register + 0xdc + 32 + 0x00000000 + 0x00013FFF + + + PWE + Programmable Watchdog Enable + When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). + 16 + 1 + read-write + + + WTO + Watchdog Timeout +When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. + 0 + 14 + read-write + + + + + GPIO + General Purpose IO Register + 0xe0 + 32 + 0x00000000 + 0x0F0F0F0F + + + GPIT + No description avaiable + 24 + 4 + read-write + + + GPIE + No description avaiable + 16 + 4 + read-write + + + GPO + No description avaiable + 8 + 4 + read-write + + + GPIS + No description avaiable + 0 + 4 + read-write + + + + + MMC_CNTRL + MMC Control establishes the operating mode of MMC. + 0x100 + 32 + 0x00000000 + 0x0000013F + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames +When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). When reset, the MMC Counters are not updated for dropped Broadcast frames. + 8 + 1 + read-write + + + CNTPRSTLVL + Full-Half Preset +When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half +- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half +- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full +- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full +- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. + 5 + 1 + read-write + + + CNTPRST + Counters Preset +When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. + 4 + 1 + read-write + + + CNTFREEZ + MMC Counter Freeze +When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. + 3 + 1 + read-write + + + RSTONRD + Reset on Read +When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. + 2 + 1 + read-write + + + CNTSTOPRO + Counter Stop Rollover +When this bit is set, the counter does not roll over to zero after reaching the maximum value. + 1 + 1 + read-write + + + CNTRST + Counters Reset +When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle + 0 + 1 + read-write + + + + + MMC_INTR_RX + MMC Receive Interrupt maintains the interrupt generated from all +of the receive statistic counters. + 0x104 + 32 + 0x00000000 + 0x03FFFFFF + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status +This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status +This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status +This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status +This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status +This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status +This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status. +This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status +This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status +This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. +This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status +This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status +This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status +This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status +This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status +This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status +This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status +This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status +This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status +This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status +This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status +This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + MMC_INTR_TX + MMC Transmit Interrupt maintains the interrupt generated from all +of the transmit statistic counters + 0x108 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status +This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status +This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status +This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status +This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status +This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status +This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status +This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status +This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status +This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status +This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status +This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status +This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status +This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status +The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status +This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status +This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status +This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status +This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + MMC_INTR_MASK_RX + MMC Receive Interrupt mask maintains the mask for the interrupt +generated from all of the receive statistic counters + 0x10c + 32 + 0x00000000 + 0x03FFFFFE + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. +Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask. +Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + + + MMC_INTR_MASK_TX + MMC Transmit Interrupt Mask + 0x110 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIM + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + TXOCTETCOUNT_GB + Number of bytes transmitted, exclusive of preamble and retried +bytes, in good and bad frames. + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. + 0 + 32 + read-write + + + + + TXFRAMECOUNT_GB + Number of good and bad frames transmitted, exclusive of retried +frames. + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted, exclusive of retried frames. + 0 + 32 + read-write + + + + + TXBROADCASTFRAMES_G + Number of good broadcast frames transmitted + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good broadcast frames transmitted. + 0 + 32 + read-write + + + + + TXMLTICASTFRAMES_G + Number of good multicast frames transmitted + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good multicast frames transmitted. + 0 + 32 + read-write + + + + + TX64OCTETS_GB + Number of good and bad frames transmitted with length 64 bytes, +exclusive of preamble and retried frames. + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX65TO127OCTETS_GB + Number of good and bad frames transmitted with length between +65 and 127 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX128TO255OCTETS_GB + Number of good and bad frames transmitted with length between +128 and 255 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX256TO511OCTETS_GB + Number of good and bad frames transmitted with length between +256 and 511 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX512TO1023OCTETS_GB + Number of good and bad frames transmitted with length between +512 and 1,023 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX1024TOMAXOCTETS_GB + Number of good and bad frames transmitted with length between +1,024 and maxsize (inclusive) bytes, exclusive of preamble and +retried frames. + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TXUNICASTFRAMES_GB + Number of good and bad unicast frames transmitted. + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad unicast frames transmitted. + 0 + 32 + read-write + + + + + TXMULTICASTFRAMES_GB + Number of good and bad multicast frames transmitted. + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad multicast frames transmitted. + 0 + 32 + read-write + + + + + TXBROADCASTFRAMES_GB + Number of good and bad broadcast frames transmitted. + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad broadcast frames transmitted. + 0 + 32 + read-write + + + + + TXUNDERFLOWERROR + Number of frames aborted because of frame underflow error. + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of frame underflow error. + 0 + 32 + read-write + + + + + TXSINGLECOL_G + Number of successfully transmitted frames after a single collision +in the half-duplex mode. + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of successfully transmitted frames after a single collision in the half-duplex mode. + 0 + 32 + read-write + + + + + TXMULTICOL_G + Number of successfully transmitted frames after multiple collisions +in the half-duplex mode. + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of successfully transmitted frames after multiple collisions in the half-duplex mode. + 0 + 32 + read-write + + + + + TXDEFERRED + Number of successfully transmitted frames after a deferral in the +half-duplex mode. + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of successfully transmitted frames after a deferral in the half-duplex mode. + 0 + 32 + read-write + + + + + TXLATECOL + Number of frames aborted because of late collision error + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of late collision error. + 0 + 32 + read-write + + + + + TXEXESSCOL + Number of frames aborted because of excessive (16) collision +errors + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of excessive (16) collision errors. + 0 + 32 + read-write + + + + + TXCARRIERERROR + Number of frames aborted because of carrier sense error (no +carrier or loss of carrier). + 0x160 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of carrier sense error (no carrier or loss of carrier). + 0 + 32 + read-write + + + + + TXOCTETCOUNT_G + Number of bytes transmitted, exclusive of preamble, only in good +frames. + 0x164 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes transmitted, exclusive of preamble, only in good frames. + 0 + 32 + read-write + + + + + TXFRAMECOUNT_G + Number of good frames transmitted + 0x168 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good frames transmitted. + 0 + 32 + read-write + + + + + TXEXCESSDEF + Number of frames aborted because of excessive deferral error +(deferred for more than two max-sized frame times). + 0x16c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of excessive deferral error (deferred for more than two max-sized frame times). + 0 + 32 + read-write + + + + + TXPAUSEFRAMES + Number of good Pause frames transmitted + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good Pause frames transmitted. + 0 + 32 + read-write + + + + + TXVLANFRAMES_G + Number of good VLAN frames transmitted, exclusive of retried +frames. + 0x174 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good VLAN frames transmitted, exclusive of retried frames. + 0 + 32 + read-write + + + + + TXOVERSIZE_G + Number of frames transmitted without errors and with length +greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged +frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC +Configuration Register)). + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). + 0 + 32 + read-write + + + + + RXFRAMECOUNT_GB + Number of good and bad frames received + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received. + 0 + 32 + read-write + + + + + RXOCTETCOUNT_G + Number of bytes received, exclusive of preamble, only in good +frames. + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received, exclusive of preamble, in good and bad frames. + 0 + 32 + read-write + + + + + RXOCTETCOUNT_GB + Number of bytes received, exclusive of preamble, in good and bad +frames. + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received, exclusive of preamble, only in good frames. + 0 + 32 + read-write + + + + + RXBROADCASTFRAMES_G + Number of good broadcast frames received + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good broadcast frames received. + 0 + 32 + read-write + + + + + RXMULTICASTFRAMES_G + Number of good multicast frames received + 0x190 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good multicast frames received. + 0 + 32 + read-write + + + + + RXCRCERROR + Number of frames received with CRC error + 0x194 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with CRC error. + 0 + 32 + read-write + + + + + RXALIGNMENTERROR + Number of frames received with alignment (dribble) error. Valid +only in 10/100 mode + 0x198 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. + 0 + 32 + read-write + + + + + RXRUNTERROR + Number of frames received with runt (<64 bytes and CRC error) +error. + 0x19c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with runt (<64 bytes and CRC error) error. + 0 + 32 + read-write + + + + + RXJABBERERROR + Number of giant frames received with length (including CRC) +greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with +CRC error. If Jumbo Frame mode is enabled, then frames of +length greater than 9,018 bytes (9,022 for VLAN tagged) are +considered as giant frames. + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. + 0 + 32 + read-write + + + + + RXUNDERSIZE_G + Number of frames received with length less than 64 bytes, without +any errors. + 0x1a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with length less than 64 bytes, without any errors. + 0 + 32 + read-write + + + + + RXOVERSIZE_G + Number of frames received without errors, with length greater +than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 +bytes if enabled in Bit 27 of Register 0 (MAC Configuration +Register)) + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). + 0 + 32 + read-write + + + + + RX64OCTETS_GB + Number of good and bad frames received with length 64 bytes, +exclusive of preamble. + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length 64 bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX65TO127OCTETS_GB + No description avaiable + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX128TO255OCTETS_GB + No description avaiable + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX256TO511OCTETS_GB + Number of good and bad frames received with length between +256 and 511 (inclusive) bytes, exclusive of preamble. + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX512TO1023OCTETS_GB + Number of good and bad frames received with length between +512 and 1023 (inclusive) bytes, exclusive of preamble. + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX1024TOMAXOCTETS_GB + Number of good and bad frames received with length between +1024 and maxsize (inclusive) bytes, exclusive of preamble. + 0x1c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + RXUNICASTFRAMES_G + Number of received good unicast frames. + 0x1c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of received good unicast frames. + 0 + 32 + read-write + + + + + RXLENGTHERROR + Number of frames received with length error (Length type field ≠ +frame size), for all frames with valid length field. + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with length error (Length type field ≠ frame size), for all frames with valid length field. + 0 + 32 + read-write + + + + + RXOUTOFRANGETYPE + Number of frames received with length field not equal to the valid +frame size (greater than 1,500 but less than 1,536). + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). + 0 + 32 + read-write + + + + + RXPAUSEFRAMES + Number of good and valid Pause frames received. + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and valid Pause frames received. + 0 + 32 + read-write + + + + + RXFIFOOVERFLOW + Number of missed received frames because of FIFO overflow. +This counter is not present in the GMAC-CORE configuration. + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of missed received frames because of FIFO overflow. This counter is not present in the GMAC-CORE configuration. + 0 + 32 + read-write + + + + + RXVLANFRAMES_GB + Number of good and bad VLAN frames received. + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad VLAN frames received. + 0 + 32 + read-write + + + + + RXWATCHDOGERROR + Number of frames received with error because of watchdog +timeout error (frames with a data load larger than 2,048 bytes or +the value programmed in Register 55 (Watchdog Timeout +Register)). + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with error because of watchdog timeout error (frames with a data load larger than 2,048 bytes or the value programmed in Register 55 (Watchdog Timeout Register)). + 0 + 32 + read-write + + + + + RXRCVERROR + Number of frames received with Receive error or Frame Extension +error on the GMII or MII interface. + 0x1e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. + 0 + 32 + read-write + + + + + RXCTRLFRAMES_G + Number of received good control frames + 0x1e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of received good control frames. + 0 + 32 + read-write + + + + + MMC_IPC_INTR_MASK_RX + MMC IPC Receive Checksum Offload Interrupt Mask maintains +the mask for the interrupt generated from the receive IPC statistic +counters. + 0x200 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIM + MMC Receive ICMP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIM + MMC Receive ICMP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIM + MMC Receive TCP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIM + MMC Receive TCP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + 26 + 1 + read-write + + + RXUDPEROIM + MMC Receive UDP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIM + MMC Receive IPV6 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIM + MMC Receive IPV6 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIM + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIM + MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIM + MMC Receive IPV4 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIM + MMC Receive IPV4 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIM + MMC Receive IPV4 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIM + MMC Receive ICMP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIM + MMC Receive ICMP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIM + MMC Receive TCP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIM + MMC Receive TCP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIM + MMC Receive UDP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIM + MMC Receive UDP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIM + MMC Receive IPV6 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIM + MMC Receive IPV6 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIM + MMC Receive IPV6 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIM + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIM + MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIM + MMC Receive IPV4 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIM + MMC Receive IPV4 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIM + MMC Receive IPV4 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + MMC_IPC_INTR_RX + MMC Receive Checksum Offload Interrupt maintains the interrupt +that the receive IPC statistic counters generate. See Table 4-25 +for further detail. + 0x208 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIS + MMC Receive ICMP Error Octet Counter Interrupt Status +This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIS + MMC Receive ICMP Good Octet Counter Interrupt Status +This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIS + MMC Receive TCP Error Octet Counter Interrupt Status +This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIS + MMC Receive TCP Good Octet Counter Interrupt Status +This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value + 26 + 1 + read-write + + + RXUDPEROIS + MMC Receive UDP Error Octet Counter Interrupt Status +This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIS + MMC Receive UDP Good Octet Counter Interrupt Status +This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIS + MMC Receive IPV6 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIS + MMC Receive IPV6 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIS + MMC Receive IPV6 Good Octet Counter Interrupt Status +This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIS + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status +This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIS + MMC Receive IPV4 Fragmented Octet Counter Interrupt Status +This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIS + MMC Receive IPV4 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIS + MMC Receive IPV4 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIS + MMC Receive IPV4 Good Octet Counter Interrupt Status +This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIS + MMC Receive ICMP Error Frame Counter Interrupt Status +This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIS + MMC Receive ICMP Good Frame Counter Interrupt Status +This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIS + MMC Receive TCP Error Frame Counter Interrupt Status +This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIS + MMC Receive TCP Good Frame Counter Interrupt Status +This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIS + MMC Receive UDP Error Frame Counter Interrupt Status +This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIS + MMC Receive UDP Good Frame Counter Interrupt Status +This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIS + MMC Receive IPV6 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIS + MMC Receive IPV6 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIS + MMC Receive IPV6 Good Frame Counter Interrupt Status +This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIS + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status +This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIS + MMC Receive IPV4 Fragmented Frame Counter Interrupt Status +This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIS + MMC Receive IPV4 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIS + MMC Receive IPV4 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIS + MMC Receive IPV4 Good Frame Counter Interrupt Status +This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + RXIPV4_GD_FMS + Number of good IPv4 datagrams received with the TCP, UDP, or +ICMP payload + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload + 0 + 32 + read-write + + + + + RXIPV4_HDRERR_FRMS + Number of IPv4 datagrams received with header (checksum, +length, or version mismatch) errors + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors + 0 + 32 + read-write + + + + + RXIPV4_NOPAY_FRMS + Number of IPv4 datagram frames received that did not have a +TCP, UDP, or ICMP payload processed by the Checksum engine + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine + 0 + 32 + read-write + + + + + RXIPV4_FRAG_FRMS + Number of good IPv4 datagrams with fragmentation + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv4 datagrams with fragmentation + 0 + 32 + read-write + + + + + RXIPV4_UDSBL_FRMS + Number of good IPv4 datagrams received that had a UDP +payload with checksum disabled + 0x220 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv4 datagrams received that had a UDP payload with checksum disabled + 0 + 32 + read-write + + + + + RXIPV6_GD_FRMS + Number of good IPv6 datagrams received with TCP, UDP, or +ICMP payloads + 0x224 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads + 0 + 32 + read-write + + + + + RXIPV6_HDRERR_FRMS + Number of IPv6 datagrams received with header errors (length or +version mismatch) + 0x228 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of IPv6 datagrams received with header errors (length or version mismatch) + 0 + 32 + read-write + + + + + RXIPV6_NOPAY_FRMS + Number of IPv6 datagram frames received that did not have a +TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with +fragmentation or security extension headers + 0x22c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers + 0 + 32 + read-write + + + + + RXUDP_GD_FRMS + Number of good IP datagrams with a good UDP payload. This +counter is not updated when the rxipv4_udsbl_frms counter is +incremented. + 0x230 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. + 0 + 32 + read-write + + + + + RXUDP_ERR_FRMS + Number of good IP datagrams whose UDP payload has a +checksum error + 0x234 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams whose UDP payload has a checksum error + 0 + 32 + read-write + + + + + RXTCP_GD_FRMS + Number of good IP datagrams with a good TCP payload + 0x238 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams with a good TCP payload + 0 + 32 + read-write + + + + + RXTCP_ERR_FRMS + Number of good IP datagrams whose TCP payload has a +checksum error + 0x23c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams whose TCP payload has a checksum error + 0 + 32 + read-write + + + + + RXICMP_GD_FRMS + Number of good IP datagrams with a good ICMP payload + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams with a good ICMP payload + 0 + 32 + read-write + + + + + RXICMP_ERR_FRMS + Number of good IP datagrams whose ICMP payload has a +checksum error + 0x244 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams whose ICMP payload has a checksum error + 0 + 32 + read-write + + + + + RXIPV4_GD_OCTETS + Number of bytes received in good IPv4 datagrams encapsulating +TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad +bytes are not included in this counter or in the octet counters listed +below). + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). + 0 + 32 + read-write + + + + + RXIPV4_HDRERR_OCTETS + Number of bytes received in IPv4 datagrams with header errors +(checksum, length, version mismatch). The value in the Length +field of IPv4 header is used to update this counter. + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. + 0 + 32 + read-write + + + + + RXIPV4_NOPAY_OCTETS + Number of bytes received in IPv4 datagrams that did not have a +TCP, UDP, or ICMP payload. The value in the IPv4 header’s +Length field is used to update this counter. + 0x258 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header’s Length field is used to update this counter. + 0 + 32 + read-write + + + + + RXIPV4_FRAG_OCTETS + Number of bytes received in fragmented IPv4 datagrams. The +value in the IPv4 header’s Length field is used to update this +counter + 0x25c + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header’s Length field is used to update this counter. + 0 + 32 + read-write + + + + + RXIPV4_UDSBL_OCTETS + Number of bytes received in a UDP segment that had the UDP +checksum disabled. This counter does not count IP Header bytes. + 0x260 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. + 0 + 32 + read-write + + + + + RXIPV6_GD_OCTETS + Number of bytes received in good IPv6 datagrams encapsulating +TCP, UDP or ICMPv6 data + 0x264 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data + 0 + 32 + read-write + + + + + RXIPV6_HDRERR_OCTETS + Number of bytes received in IPv6 datagrams with header errors +(length, version mismatch). The value in the IPv6 header’s Length +field is used to update this counter. + 0x268 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header’s Length field is used to update this counter. + 0 + 32 + read-write + + + + + RXIPV6_NOPAY_OCTETS + Number of bytes received in IPv6 datagrams that did not have a +TCP, UDP, or ICMP payload. The value in the IPv6 header’s +Length field is used to update this counter. + 0x26c + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header’s Length field is used to update this counter. + 0 + 32 + read-write + + + + + RXUDP_GD_OCTETS + Number of bytes received in a good UDP segment. This counter +(and the counters below) does not count IP header bytes. + 0x270 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. + 0 + 32 + read-write + + + + + RXUDP_ERR_OCTETS + Number of bytes received in a UDP segment that had checksum +errors + 0x274 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a UDP segment that had checksum errors + 0 + 32 + read-write + + + + + RXTCP_GD_OCTETS + Number of bytes received in a good TCP segment + 0x278 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a good TCP segment + 0 + 32 + read-write + + + + + RXTCP_ERR_OCTETS + Number of bytes received in a TCP segment with checksum +errors + 0x27c + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a TCP segment with checksum errors + 0 + 32 + read-write + + + + + RXICMP_GD_OCTETS + Number of bytes received in a good ICMP segment + 0x280 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a good ICMP segment + 0 + 32 + read-write + + + + + L3_L4_CFG_0_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x400 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L3_L4_CFG_0_L4_ADDR + Layer 4 Address Register + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_L4_CFG_0_L3_ADDR_0 + Layer 3 Address 0 Register + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_0_L3_ADDR_1 + Layer 3 Address 1 Register + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_0_L3_ADDR_2 + Layer 3 Address 2 Register + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_0_L3_ADDR_3 + Layer 3 Address 3 Register + 0x41c + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_1_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x430 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L3_L4_CFG_1_L4_ADDR + Layer 4 Address Register + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_L4_CFG_1_L3_ADDR_0 + Layer 3 Address 0 Register + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_1_L3_ADDR_1 + Layer 3 Address 1 Register + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_1_L3_ADDR_2 + Layer 3 Address 2 Register + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_1_L3_ADDR_3 + Layer 3 Address 3 Register + 0x44c + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_2_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x460 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L3_L4_CFG_2_L4_ADDR + Layer 4 Address Register + 0x464 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_L4_CFG_2_L3_ADDR_0 + Layer 3 Address 0 Register + 0x470 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_2_L3_ADDR_1 + Layer 3 Address 1 Register + 0x474 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_2_L3_ADDR_2 + Layer 3 Address 2 Register + 0x478 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_2_L3_ADDR_3 + Layer 3 Address 3 Register + 0x47c + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_3_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x490 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L3_L4_CFG_3_L4_ADDR + Layer 4 Address Register + 0x494 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_L4_CFG_3_L3_ADDR_0 + Layer 3 Address 0 Register + 0x4a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_3_L3_ADDR_1 + Layer 3 Address 1 Register + 0x4a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_3_L3_ADDR_2 + Layer 3 Address 2 Register + 0x4a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_3_L3_ADDR_3 + Layer 3 Address 3 Register + 0x4ac + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER0 + Hash Table Register 0 + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER1 + Hash Table Register 1 + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER2 + Hash Table Register 2 + 0x508 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER3 + Hash Table Register 3 + 0x50c + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER4 + Hash Table Register 4 + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER5 + Hash Table Register 5 + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER6 + Hash Table Register 6 + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER7 + Hash Table Register 7 + 0x51c + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + VLAN_TAG_INC_RPL + VLAN Tag Inclusion or Replacement Register + 0x584 + 32 + 0x00000000 + 0x000FFFFF + + + CSVL + C-VLAN or S-VLAN + When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. + 19 + 1 + read-write + + + VLP + VLAN Priority Control +When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. + 18 + 1 + read-write + + + VLC + VLAN Tag Control in Transmit Frames +- 2’b00: No VLAN tag deletion, insertion, or replacement +- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. +- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. +- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. + 16 + 2 + read-write + + + VLT + VLAN Tag for Transmit Frames + This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. + 0 + 16 + read-write + + + + + VLAN_HASH + VLAN Hash Table Register + 0x588 + 32 + 0x00000000 + 0x0000FFFF + + + VLHT + VLAN Hash Table + This field contains the 16-bit VLAN Hash Table. + 0 + 16 + read-write + + + + + TS_CTRL + Timestamp Control Register + 0x700 + 32 + 0x00000000 + 0x1F07FF3F + + + ATSEN3 + Auxiliary Snapshot 3 Enable +This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. + 28 + 1 + read-write + + + ATSEN2 + Auxiliary Snapshot 2 Enable +This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. + 27 + 1 + read-write + + + ATSEN1 + Auxiliary Snapshot 1 Enable +This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. + 26 + 1 + read-write + + + ATSEN0 + Auxiliary Snapshot 0 Enable +This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. + 25 + 1 + read-write + + + ATSFC + Auxiliary Snapshot FIFO Clear +When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. + 24 + 1 + read-write + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering +When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. + 18 + 1 + read-write + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. + 16 + 2 + read-write + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master +When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. + 15 + 1 + read-write + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages +When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. + 14 + 1 + read-write + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. + 13 + 1 + read-write + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP +When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. + 12 + 1 + read-write + + + TSIPENA + Enable Processing of PTP over Ethernet Frames +When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets + 11 + 1 + read-write + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format +When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. + 10 + 1 + read-write + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control +When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. + 9 + 1 + read-write + + + TSENALL + Enable Timestamp for All Frames +When set, the timestamp snapshot is enabled for all frames received by the MAC. + 8 + 1 + read-write + + + TSADDREG + Addend Reg Update +When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. + 5 + 1 + read-write + + + TSTRIG + Timestamp Interrupt Trigger Enable +When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. + 4 + 1 + read-write + + + TSUPDT + Timestamp Update +When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. + 3 + 1 + read-write + + + TSINIT + Timestamp Initialize +When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. + 2 + 1 + read-write + + + TSCFUPDT + Timestamp Fine or Coarse Update +When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. + 1 + 1 + read-write + + + TSENA + Timestamp Enable +When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. + 0 + 1 + read-write + + + + + SUB_SEC_INCR + Sub-Second Increment Register + 0x704 + 32 + 0x00000000 + 0x000000FF + + + SSINC + Sub-second Increment Value +The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. + 0 + 8 + read-write + + + + + SYST_SEC + System Time - Seconds Register + 0x708 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the current value in seconds of the System Time maintained by the MAC. + 0 + 32 + read-write + + + + + SYST_NSEC + System Time - Nanoseconds Register + 0x70c + 32 + 0x00000000 + 0x7FFFFFFF + + + TSSS + Timestamp Sub Seconds + The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. + 0 + 31 + read-write + + + + + SYST_SEC_UPD + System Time - Seconds Update Register + 0x710 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the time in seconds to be initialized or added to the system time. + 0 + 32 + read-write + + + + + SYST_NSEC_UPD + System Time - Nanoseconds Update Register + 0x714 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDSUB + Add or Subtract Time + When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. + 31 + 1 + read-write + + + TSSS + Timestamp Sub Seconds +The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. + 0 + 31 + read-write + + + + + TS_ADDEND + Timestamp Addend Register + 0x718 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSAR + Timestamp Addend Register +This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. + 0 + 32 + read-write + + + + + TGTTM_SEC + Target Time Seconds Register + 0x71c + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTR + Target Time Seconds Register + This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + TGTTM_NSEC + Target Time Nanoseconds Register + 0x720 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY + Target Time Register Busy + The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. + 31 + 1 + read-write + + + TTSLO + Target Timestamp Low Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + SYSTM_H_SEC + System Time - Higher Word Seconds Register + 0x724 + 32 + 0x00000000 + 0x0000FFFF + + + TSHWR + Timestamp Higher Word Register +This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. + 0 + 16 + read-write + + + + + TS_STATUS + Timestamp Status Register + 0x728 + 32 + 0x00000000 + 0x3F0F03FF + + + ATSNS + Number of Auxiliary Timestamp Snapshots +This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 25 + 5 + read-only + + + ATSSTM + Auxiliary Timestamp Snapshot Trigger Missed + This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 24 + 1 + read-only + + + ATSSTN + Auxiliary Timestamp Snapshot Trigger Identifier +These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. + 16 + 4 + read-only + + + TSTRGTERR3 + Timestamp Target Time Error +This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. + 9 + 1 + read-only + + + TSTARGT3 + Timestamp Target Time Reached for Target Time PPS3 +When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). + 8 + 1 + read-only + + + TSTRGTERR2 + No description avaiable + 7 + 1 + read-only + + + TSTARGT2 + No description avaiable + 6 + 1 + read-only + + + TSTRGTERR1 + No description avaiable + 5 + 1 + read-only + + + TSTARGT1 + No description avaiable + 4 + 1 + read-only + + + TSTRGTERR + No description avaiable + 3 + 1 + read-only + + + AUXTSTRIG + No description avaiable + 2 + 1 + read-only + + + TSTARGT + No description avaiable + 1 + 1 + read-only + + + TSSOVF + No description avaiable + 0 + 1 + read-only + + + + + PPS_CTRL + PPS Control Register + 0x72c + 32 + 0x00000000 + 0x6767677F + + + TRGTMODSEL3 + Target Time Register Mode for PPS3 Output +This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. + 29 + 2 + read-write + + + PPSCMD3 + Flexible PPS3 Output Control +This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 24 + 3 + read-write + + + TRGTMODSEL2 + Target Time Register Mode for PPS2 Output +This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. + 21 + 2 + read-write + + + PPSCMD2 + Flexible PPS2 Output Control +This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 16 + 3 + read-write + + + TRGTMODSEL1 + Target Time Register Mode for PPS1 Output +This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. + 13 + 2 + read-write + + + PPSCMD1 + Flexible PPS1 Output Control +This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 8 + 3 + read-write + + + TRGTMODSEL0 + Target Time Register Mode for PPS0 Output + This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: +- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. +- 01: Reserved +- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. +- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. + 5 + 2 + read-write + + + PPSEN0 + Flexible PPS Output Mode Enable +When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. + 4 + 1 + read-write + + + PPSCTRL0 + PPSCTRL0: PPS0 Output Frequency Control +This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: +- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. +- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. +- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. +- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... +- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) + 0 + 4 + read-write + + + + + AUX_TS_NSEC + Auxiliary Timestamp - Nanoseconds Register + 0x730 + 32 + 0x00000000 + 0x7FFFFFFF + + + AUXTSLO + Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. + 0 + 31 + read-write + + + + + AUX_TS_SEC + Auxiliary Timestamp - Seconds Register + 0x734 + 32 + 0x00000000 + 0xFFFFFFFF + + + AUXTSHI + Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. + 0 + 32 + read-write + + + + + PPS0_INTERVAL + PPS0 Interval Register + 0x760 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS0 Output Signal Interval +These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS0_WIDTH + PPS0 Width Register + 0x764 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS0 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_1_TGTTM_SEC + PPS Target Time Seconds Register + 0x780 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + PPS_1_TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x784 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + PPS_1_INTERVAL + PPS Interval Register + 0x788 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_1_WIDTH + PPS Width Register + 0x78c + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_2_TGTTM_SEC + PPS2 Target Time Seconds Register + 0x7a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + PPS_2_TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x7a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + PPS_2_INTERVAL + PPS Interval Register + 0x7a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_2_WIDTH + PPS Width Register + 0x7ac + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_3_TGTTM_SEC + PPS3 Target Time Seconds Register + 0x7c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + PPS_3_TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x7c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + PPS_3_INTERVAL + PPS Interval Register + 0x7c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_3_WIDTH + PPS Width Register + 0x7cc + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + DMA_BUS_MODE + Bus Mode Register + 0x1000 + 32 + 0x00000000 + 0xBFFFFFFF + + + RIB + Rebuild INCRx Burst +When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. + 31 + 1 + read-write + + + PRWG + Channel Priority +Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. +- 00: The priority weight is 1. +- 01: The priority weight is 2. +- 10: The priority weight is 3. +- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). + 28 + 2 + read-write + + + TXPR + Transmit Priority +When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). + 27 + 1 + read-write + + + MB + Mixed Burst +When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. + 26 + 1 + read-write + + + AAL + Address-Aligned Beats +When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. + 25 + 1 + read-write + + + PBLX8 + PBLx8 Mode +When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. + 24 + 1 + read-write + + + USP + Use Separate PBL +When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. + 23 + 1 + read-write + + + RPBL + Rx DMA PBL +This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. + 17 + 6 + read-write + + + FB + Fixed Burst + This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. + 16 + 1 + read-write + + + PR + Priority Ratio + These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. +- 00: The Priority Ratio is 1:1. +- 01: The Priority Ratio is 2:1. +- 10: The Priority Ratio is 3:1. +- 11: The Priority Ratio is 4:1. + 14 + 2 + read-write + + + PBL + Programmable Burst Length +These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. + 8 + 6 + read-write + + + ATDS + Alternate Descriptor Size +When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). + 7 + 1 + read-write + + + DSL + Descriptor Skip Length +This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. + 2 + 5 + read-write + + + DA + DMA Arbitration Scheme +This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. +- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). +- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. + 1 + 1 + read-write + + + SWR + Software Reset + When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. + 0 + 1 + read-write + + + + + DMA_TX_POLL_DEMAND + Transmit Poll Demand Register + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPD + Transmit Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. + 0 + 32 + read-write + + + + + DMA_RX_POLL_DEMAND + Receive Poll Demand Register + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPD + Receive Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. + 0 + 32 + read-write + + + + + DMA_RX_DESC_LIST_ADDR + Receive Descriptor List Address Register + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + RDESLA + Start of Receive List +This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_TX_DESC_LIST_ADDR + Transmit Descriptor List Address Register + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDESLA + Start of Transmit List +This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_STATUS + Status Register + 0x1014 + 32 + 0x00000000 + 0x7FFFE7FF + + + GLPII + GLPII: GMAC LPI Interrupt (for Channel 0) +This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. + 30 + 1 + read-write + + + TTI + Timestamp Trigger Interrupt +This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. + 29 + 1 + read-write + + + GPI + GMAC PMT Interrupt +This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. + 28 + 1 + read-write + + + GMI + GMAC MMC Interrupt + This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. + 27 + 1 + read-write + + + GLI + GMAC Line Interface Interrupt +When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. + 26 + 1 + read-write + + + EB + Error Bits +This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. +- 0 0 0: Error during Rx DMA Write Data Transfer +- 0 1 1: Error during Tx DMA Read Data Transfer +- 1 0 0: Error during Rx DMA Descriptor Write Access +- 1 0 1: Error during Tx DMA Descriptor Write Access +- 1 1 0: Error during Rx DMA Descriptor Read Access +- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. + 23 + 3 + read-write + + + TS + Transmit Process State +This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped; Reset or Stop Transmit Command issued +- 3’b001: Running; Fetching Transmit Transfer Descriptor +- 3’b010: Running; Waiting for status +- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) +- 3’b100: TIME_STAMP write state +- 3’b101: Reserved for future use +- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow +- 3’b111: Running; Closing Transmit Descriptor + 20 + 3 + read-write + + + RS + Receive Process State +This field indicates the Receive DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped: Reset or Stop Receive Command issued +- 3’b001: Running: Fetching Receive Transfer Descriptor +- 3’b010: Reserved for future use +- 3’b011: Running: Waiting for receive packet +- 3’b100: Suspended: Receive Descriptor Unavailable +- 3’b101: Running: Closing Receive Descriptor +- 3’b110: TIME_STAMP write state +- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory + 17 + 3 + read-write + + + NIS + Normal Interrupt Summary +Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. + 16 + 1 + read-write + + + AIS + Abnormal Interrupt Summary +Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. + 15 + 1 + read-write + + + ERI + Early Receive Interrupt +This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). + 14 + 1 + read-write + + + FBI + Fatal Bus Error Interrupt +This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. + 13 + 1 + read-write + + + ETI + Early Transmit Interrupt +This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + 10 + 1 + read-write + + + RWT + Receive Watchdog Timeout +When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + 9 + 1 + read-write + + + RPS + Receive Process Stopped +This bit is asserted when the Receive Process enters the Stopped state. + 8 + 1 + read-write + + + RU + Receive Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. + 7 + 1 + read-write + + + RI + Receive Interrupt +This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. + 6 + 1 + read-write + + + UNF + Transmit Underflow +This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + 5 + 1 + read-write + + + OVF + Receive Overflow +This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. + 4 + 1 + read-write + + + TJT + Transmit Jabber Timeout +This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + 3 + 1 + read-write + + + TU + Transmit Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. + 2 + 1 + read-write + + + TPS + Transmit Process Stopped +This bit is set when the transmission is stopped. + 1 + 1 + read-write + + + TI + Transmit Interrupt +This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. + 0 + 1 + read-write + + + + + DMA_OP_MODE + Operation Mode Register + 0x1018 + 32 + 0x00000000 + 0x13F1FFFE + + + DT + Disable Dropping of TCP/IP Checksum Error Frames +When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). + 28 + 1 + read-write + + + RSF + Receive Store and Forward +When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. + 25 + 1 + read-write + + + DFF + Disable Flushing of Received Frames +When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) + 24 + 1 + read-write + + + RFA_2 + MSB of Threshold for Activating Flow Control +If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 23 + 1 + read-write + + + RFD_2 + MSB of Threshold for Deactivating Flow Control +If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 22 + 1 + read-write + + + TSF + Transmit Store and Forward +When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. + 21 + 1 + read-write + + + FTF + Flush Transmit FIFO +When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. + 20 + 1 + read-write + + + TTC + Transmit Threshold Control +These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. +- 000: 64 +- 001: 128 +- 010: 192 +- 011: 256 +- 100: 40 +- 101: 32 +- 110: 24 +- 111: 16 + 14 + 3 + read-write + + + ST + Start or Stop Transmission Command +When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. + 13 + 1 + read-write + + + RFD + Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. +- 00: Full minus 1 KB, that is, FULL — 1 KB +- 01: Full minus 2 KB, that is, FULL — 2 KB +- 10: Full minus 3 KB, that is, FULL — 3 KB +- 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. + 11 + 2 + read-write + + + RFA + Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. +- 00: Full minus 1 KB, that is, FULL—1KB. +- 01: Full minus 2 KB, that is, FULL—2KB. +- 10: Full minus 3 KB, that is, FULL—3KB. +- 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition + 9 + 2 + read-write + + + EFC + Enable HW Flow Control +When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. + 8 + 1 + read-write + + + FEF + Forward Error Frames +When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. + 7 + 1 + read-write + + + FUF + Forward Undersized Good Frames +When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. + 6 + 1 + read-write + + + DGF + Drop Giant Frames +When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). + 5 + 1 + read-write + + + RTC + Receive Threshold Control +These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. +- 00: 64 +- 01: 32 +- 10: 96 +- 11: 128 + 3 + 2 + read-write + + + OSF + Operate on Second Frame +When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + 2 + 1 + read-write + + + SR + Start or Stop Receive +When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. + 1 + 1 + read-write + + + + + DMA_INTR_EN + Interrupt Enable Register + 0x101c + 32 + 0x00000000 + 0x0001E7FF + + + NIE + Normal Interrupt Summary Enable +When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt + 16 + 1 + read-write + + + AIE + Abnormal Interrupt Summary Enable +When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error + 15 + 1 + read-write + + + ERE + Early Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. + 14 + 1 + read-write + + + FBE + Fatal Bus Error Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. + 13 + 1 + read-write + + + ETE + Early Transmit Interrupt Enable +When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. + 10 + 1 + read-write + + + RWE + Receive Watchdog Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. + 9 + 1 + read-write + + + RSE + Receive Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. + 8 + 1 + read-write + + + RUE + Receive Buffer Unavailable Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. + 7 + 1 + read-write + + + RIE + Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. + 6 + 1 + read-write + + + UNE + Underflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. + 5 + 1 + read-write + + + OVE + Overflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. + 4 + 1 + read-write + + + TJE + Transmit Jabber Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. + 3 + 1 + read-write + + + TUE + Transmit Buffer Unavailable Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. + 2 + 1 + read-write + + + TSE + Transmit Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. + 1 + 1 + read-write + + + TIE + Transmit Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. + 0 + 1 + read-write + + + + + DMA_MISS_OVF_CNT + Missed Frame And Buffer Overflow Counter Register + 0x1020 + 32 + 0x00000000 + 0x1FFFFFFF + + + ONFCNTOVF + Overflow Bit for FIFO Overflow Counter +This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 28 + 1 + read-write + + + OVFFRMCNT + Overflow Frame Counter +This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. + 17 + 11 + read-write + + + MISCNTOVF + Overflow Bit for Missed Frame Counter +This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 16 + 1 + read-write + + + MISFRMCNT + Missed Frame Counter +This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. + 0 + 16 + read-write + + + + + DMA_RX_INTR_WDOG + Receive Interrupt Watchdog Timer Register + 0x1024 + 32 + 0x00000000 + 0x000000FF + + + RIWT + RI Watchdog Timer Count +This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + 0 + 8 + read-write + + + + + DMA_AXI_MODE + AXI Bus Mode Register + 0x1028 + 32 + 0x00000000 + 0xC0FF30FF + + + EN_LPI + Enable Low Power Interface (LPI) +When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. + 31 + 1 + read-write + + + LPI_XIT_FRM + Unlock on Magic Packet or Remote Wake-Up Frame +When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. + 30 + 1 + read-write + + + WR_OSR_LMT + AXI Maximum Write Outstanding Request Limit +This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. + 20 + 4 + read-write + + + RD_OSR_LMT + AXI Maximum Read Outstanding Request Limit +This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. + 16 + 4 + read-write + + + ONEKBBE + 1 KB Boundary Crossing Enable for the GMAC-AXI Master +When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. + 13 + 1 + read-write + + + AXI_AAL + Address-Aligned Beats +This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. + 12 + 1 + read-write + + + BLEN256 + AXI Burst Length 256 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). + 7 + 1 + read-write + + + BLEN128 + AXI Burst Length 128 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). + 6 + 1 + read-write + + + BLEN64 + AXI Burst Length 64 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). + 5 + 1 + read-write + + + BLEN32 + AXI Burst Length 32 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). + 4 + 1 + read-write + + + BLEN16 + AXI Burst Length 16 +When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. + 3 + 1 + read-write + + + BLEN8 + AXI Burst Length 8 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 2 + 1 + read-write + + + BLEN4 + AXI Burst Length 4 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 1 + 1 + read-write + + + UNDEF + AXI Undefined Burst Length +This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. + 0 + 1 + read-write + + + + + DMA_BUS_STATUS + AHB or AXI Status Register + 0x102c + 32 + 0x00000000 + 0x00000003 + + + AXIRDSTS + AXI Master Read Channel Status +When high, it indicates that AXI master's read channel is active and transferring data. + 1 + 1 + read-write + + + AXWHSTS + AXI Master Write Channel or AHB Master Status +When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. + 0 + 1 + read-write + + + + + DMA_CURR_HOST_TX_DESC + Current Host Transmit Descriptor Register + 0x1048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTDESAPTR + Host Transmit Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_DESC + Current Host Receive Descriptor Register + 0x104c + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRDESAPTR + Host Receive Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_TX_BUF + Current Host Transmit Buffer Address Register + 0x1050 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTBUFAPTR + Host Transmit Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_BUF + Current Host Receive Buffer Address Register + 0x1054 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRBUFAPTR + Host Receive Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_HW_FEATURE + HW Feature Register + 0x1058 + 32 + 0x00000000 + 0x7FFFFFFF + + + ACTPHYIF + Active or selected PHY interface +When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. +- 000: GMII or MII +- 001: RGMII +- 010: SGMII +- 011: TBI +- 100: RMII +- 101: RTBI +- 110: SMII +- 111: RevMII - All Others: Reserved + 28 + 3 + read-write + + + SAVLANINS + Source Address or VLAN Insertion + 27 + 1 + read-write + + + FLEXIPPSEN + Flexible Pulse-Per-Second Output + 26 + 1 + read-write + + + INTTSEN + Timestamping with Internal System Time + 25 + 1 + read-write + + + ENHDESSEL + Alternate (Enhanced Descriptor) + 24 + 1 + read-write + + + TXCHCNT + Number of additional Tx Channels + 22 + 2 + read-write + + + RXCHCNT + Number of additional Rx Channels + 20 + 2 + read-write + + + RXFIFOSIZE + Rx FIFO > 2,048 Bytes + 19 + 1 + read-write + + + RXTYP2COE + IP Checksum Offload (Type 2) in Rx + 18 + 1 + read-write + + + RXTYP1COE + IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1. + 17 + 1 + read-write + + + TXCOESEL + Checksum Offload in Tx + 16 + 1 + read-write + + + AVSEL + AV feature + 15 + 1 + read-write + + + EEESEL + Energy Efficient Ethernet + 14 + 1 + read-write + + + TSVER2SEL + IEEE 1588-2008 Advanced timestamp + 13 + 1 + read-write + + + TSVER1SEL + Only IEEE 1588-2002 timestamp + 12 + 1 + read-write + + + MMCSEL + RMON module + 11 + 1 + read-write + + + MGKSEL + PMT magic packet + 10 + 1 + read-write + + + RWKSEL + PMT remote wake-up frame + 9 + 1 + read-write + + + SMASEL + SMA (MDIO) Interface + 8 + 1 + read-write + + + L3L4FLTREN + Layer 3 and Layer 4 feature + 7 + 1 + read-write + + + PCSSEL + PCS registers (TBI, SGMII, or RTBI PHY interface) + 6 + 1 + read-write + + + ADDMACADRSEL + Multiple MAC Address registers + 5 + 1 + read-write + + + HASHSEL + HASH filter + 4 + 1 + read-write + + + EXTHASHEN + Expanded DA Hash filter + 3 + 1 + read-write + + + HDSEL + Half-duplex support + 2 + 1 + read-write + + + GMIISEL + 1000 Mbps support + 1 + 1 + read-write + + + MIISEL + 10 or 100 Mbps support + 0 + 1 + read-write + + + + + CTRL0 + Control Register 0 + 0x3000 + 32 + 0x00000000 + 0x000003FF + + + ENET0_RXCLK_DLY_SEL + No description avaiable + 5 + 5 + read-write + + + ENET0_TXCLK_DLY_SEL + No description avaiable + 0 + 5 + read-write + + + + + CTRL2 + Control Register 1 + 0x3008 + 32 + 0x00000000 + 0xF808F400 + + + ENET0_IRQ_EN + No description avaiable + 27 + 5 + read-write + + + ENET0_REFCLK_OE + No description avaiable + 19 + 1 + read-write + + + ENET0_PHY_INF_SEL + No description avaiable + 13 + 3 + read-write + + + ENET0_FLOWCTRL + No description avaiable + 12 + 1 + read-write + + + ENET0_RMII_TXCLK_SEL + No description avaiable + 10 + 1 + read-write + + + + + + + NTMR0 + NTMR0 + TMR + 0xf2010000 + + 0x0 + 0x20c + registers + + + + CHANNEL_CH0_CR + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 15 + 16 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- RLD flag, counter reload; +01- Input signal toggle captured +10- CMP0 flag +11- CMP1 flag + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH0_CMP0 + Comparator register 0 + 0x4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH0_CMP1 + Comparator register 1 + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH0_RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH0_CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH0_CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH0_CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH0_CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH0_CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH0_CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + CHANNEL_CH1_CR + Control Register + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 15 + 16 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- RLD flag, counter reload; +01- Input signal toggle captured +10- CMP0 flag +11- CMP1 flag + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH1_CMP0 + Comparator register 0 + 0x44 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH1_CMP1 + Comparator register 1 + 0x48 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH1_RLD + Reload register + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH1_CNTUPTVAL + Counter update value register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH1_CAPPOS + Capture rising edge register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH1_CAPNEG + Capture falling edge register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH1_CAPPRD + PWM period measure register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH1_CAPDTY + PWM duty cycle measure register + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH1_CNT + Counter + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + CHANNEL_CH2_CR + Control Register + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 15 + 16 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- RLD flag, counter reload; +01- Input signal toggle captured +10- CMP0 flag +11- CMP1 flag + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH2_CMP0 + Comparator register 0 + 0x84 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH2_CMP1 + Comparator register 1 + 0x88 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH2_RLD + Reload register + 0x8c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH2_CNTUPTVAL + Counter update value register + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH2_CAPPOS + Capture rising edge register + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH2_CAPNEG + Capture falling edge register + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH2_CAPPRD + PWM period measure register + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH2_CAPDTY + PWM duty cycle measure register + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH2_CNT + Counter + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + CHANNEL_CH3_CR + Control Register + 0xc0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 15 + 16 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- RLD flag, counter reload; +01- Input signal toggle captured +10- CMP0 flag +11- CMP1 flag + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH3_CMP0 + Comparator register 0 + 0xc4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH3_CMP1 + Comparator register 1 + 0xc8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH3_RLD + Reload register + 0xcc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH3_CNTUPTVAL + Counter update value register + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH3_CAPPOS + Capture rising edge register + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH3_CAPNEG + Capture falling edge register + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH3_CAPPRD + PWM period measure register + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH3_CAPDTY + PWM duty cycle measure register + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH3_CNT + Counter + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + read-write + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + read-write + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + read-write + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + read-write + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + read-write + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + read-write + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + read-write + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + read-write + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + read-write + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + read-write + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + read-write + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + read-write + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + read-write + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + read-write + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + read-write + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + read-write + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software coutner sync event + 0 + 4 + read-write + + + + + + + GPTMR0 + GPTMR0 + TMR + 0xf3000000 + + + GPTMR1 + GPTMR1 + TMR + 0xf3004000 + + + GPTMR2 + GPTMR2 + TMR + 0xf3008000 + + + GPTMR3 + GPTMR3 + TMR + 0xf300c000 + + + PTMR + PTMR + TMR + 0xf40e0000 + + + USB0 + USB0 + USB + 0xf2020000 + + 0x80 + 0x1a8 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00000000 + 0x00FFEB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0x00FF00FF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0x00FF00FF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 8 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x000000FF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 8 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0x00FF00FF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0x00FF00FF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0x00FF00FF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0x00FF00FF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTCTRL_ENDPTCTRL0 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL1 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c4 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL2 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c8 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL3 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1cc + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL4 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL5 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d4 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL6 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d8 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL7 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1dc + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description avaiable + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description avaiable + 25 + 1 + read-write + + + AUTORESUME_EN + No description avaiable + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description avaiable + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description avaiable + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description avaiable + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description avaiable + 10 + 1 + read-write + + + OTG_POWER_MASK + No description avaiable + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description avaiable + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description avaiable + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description avaiable + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description avaiable + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description avaiable + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description avaiable + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description avaiable + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description avaiable + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description avaiable + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description avaiable + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description avaiable + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description avaiable + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description avaiable + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description avaiable + 31 + 1 + read-write + + + + + PHY_STATUS + No description avaiable + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description avaiable + 31 + 1 + read-write + + + LINE_STATE + No description avaiable + 6 + 2 + read-write + + + HOST_DISCONNECT + No description avaiable + 5 + 1 + read-write + + + ID_DIG + No description avaiable + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description avaiable + 2 + 1 + read-write + + + VBUS_VALID + No description avaiable + 0 + 1 + read-write + + + + + + + SDXC0 + SDXC0 + SDXC + 0xf2030000 + + 0x0 + 0x3008 + registers + + + + SDMASA + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + BLOCKCNT_SDMASA + 32-bit Block Count (SDMA System Address) +- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. +When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. +It can be accessed only if no transaction is executing. Reading this register during data transfers may +return an invalid value. +- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. +The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. +This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. +Following are the values for BLOCKCNT_SDMASA: +- 0xFFFF_FFFF: 4G - 1 Block +- +- 0x0000_0002: 2 Blocks +- 0x0000_0001: 1 Block +- 0x0000_0000: Stop Count +Note: +- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. +The system address must be programmed in the ADMA System Address register. +- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. +Auto CMD23 cannot be used with SDMA. +- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. + 0 + 32 + read-write + + + + + BLK_ATTR + No description avaiable + 0x4 + 32 + 0x00020210 + 0xFFFF7FFF + + + BLOCK_CNT + 16-bit Block Count +- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. +- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. +Following are the values for BLOCK_CNT: +- 0x0: Stop Count +- 0x1: 1 Block +- 0x2: 2 Blocks +- . +- 0xFFFF: 65535 Blocks +Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. + 16 + 16 + read-write + + + SDMA_BUF_BDARY + SDMA Buffer Boundary +These bits specify the size of contiguous buffer in system memory. +The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. +Values: +- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary +- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary +- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary +- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary +- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary +- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary +- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary +- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + 12 + 3 + read-write + + + XFER_BLOCK_SIZE + Transfer Block Size +These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. +Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: +- 0x1: 1 byte +- 0x2: 2 bytes +- 0x3: 3 bytes +- . +- 0x1FF: 511 byte +- 0x200: 512 byt es +- . +- 0x800: 2048 bytes +Note: This register must be programmed with a non-zero value for data transfer. + 0 + 12 + read-write + + + + + CMD_ARG + No description avaiable + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGUMNET + Command Argument +These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. + 0 + 32 + read-write + + + + + CMD_XFER + No description avaiable + 0xc + 32 + 0x00000000 + 0x3FFF01FF + + + CMD_INDEX + Command Index +These bits are set to the command number that is specified in bits 45-40 of the Command Format. + 24 + 6 + read-write + + + CMD_TYPE + Command Type +These bits indicate the command type. +Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. +Values: +0x3 (ABORT_CMD): Abort +0x2 (RESUME_CMD): Resume +0x1 (SUSPEND_CMD): Suspend +0x0 (NORMAL_CMD): Normal + 22 + 2 + read-write + + + DATA_PRESENT_SEL + Data Present Select +This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: +Command using the CMD line +Command with no data transfer but using busy signal on the DAT[0] line +Resume Command +Values: +0x0 (NO_DATA): No Data Present +0x1 (DATA): Data Present + 21 + 1 + read-write + + + CMD_IDX_CHK_ENABLE + Command Index Check Enable +This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. +If the value is not the same, it is reported as a Command Index error. +Note: +Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. +For the tuning command, this bit must always be set to enable the index check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 20 + 1 + read-write + + + CMD_CRC_CHK_ENABLE + Command CRC Check Enable +This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. +Note: +CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. +For the tuning command, this bit must always be set to 1 to enable the CRC check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 19 + 1 + read-write + + + SUB_CMD_FLAG + Sub Command Flag +This bit distinguishes between a main command and a sub command. +Values: +0x0 (MAIN): Main Command +0x1 (SUB): Sub Command + 18 + 1 + read-write + + + RESP_TYPE_SELECT + Response Type Select +This bit indicates the type of response expected from the card. +Values: +0x0 (NO_RESP): No Response +0x1 (RESP_LEN_136): Response Length 136 +0x2 (RESP_LEN_48): Response Length 48 +0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response + 16 + 2 + read-write + + + RESP_INT_DISABLE + Response Interrupt Disable +The Host Controller supports response check function to avoid overhead of response error check by the Host driver. +Response types of only R1 and R5 can be checked by the Controller. +If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. +If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. +The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. +Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. +Values: +- 0x0 (ENABLED): Response Interrupt is enabled +- 0x1 (DISABLED): Response Interrupt is disabled + 8 + 1 + read-write + + + RESP_ERR_CHK_ENABLE + Response Error Check Enable +The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. +Note: +- Response error check must not be enabled for any response type other than R1 and R5. +- Response check must not be enabled for the tuning command. +Values: +- 0x0 (DISABLED): Response Error Check is disabled +- 0x1 (ENABLED): Response Error Check is enabled + 7 + 1 + read-write + + + RESP_TYPE + Response Type R1/R5 +This bit selects either R1 or R5 as a response type when the Response Error Check is selected. +Error statuses checked in R1: +OUT_OF_RANGE +ADDRESS_ERROR +BLOCK_LEN_ERROR +WP_VIOLATION +CARD_IS_LOCKED +COM_CRC_ERROR +CARD_ECC_FAILED +CC_ERROR +ERROR +Response Flags checked in R5: +COM_CRC_ERROR +ERROR +FUNCTION_NUMBER +OUT_OF_RANGE +Values: +0x0 (RESP_R1): R1 (Memory) +0x1 (RESP_R5): R5 (SDIO) + 6 + 1 + read-write + + + MULTI_BLK_SEL + Multi/Single Block Select +This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. +Values: +0x0 (SINGLE): Single Block +0x1 (MULTI): Multiple Block + 5 + 1 + read-write + + + DATA_XFER_DIR + Data Transfer Direction Select +This bit defines the direction of DAT line data transfers. +This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. +Values: +0x1 (READ): Read (Card to Host) +0x0 (WRITE): Write (Host to Card) + 4 + 1 + read-write + + + AUTO_CMD_ENABLE + Auto Command Enable +This field determines use of Auto Command functions. +Note: In SDIO, this field must be set as 00b (Auto Command Disabled). +Values: +0x0 (AUTO_CMD_DISABLED): Auto Command Disabled +0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable +0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable +0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel + 2 + 2 + read-write + + + BLOCK_COUNT_ENABLE + Block Count Enable +This bit is used to enable the Block Count register, which is relevant for multiple block transfers. +If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. +The Host Driver must set this bit to 0 when ADMA is used. +Values: +0x1 (ENABLED): Enable +0x0 (DISABLED): Disable + 1 + 1 + read-write + + + DMA_ENABLE + DMA Enable +This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. +You can select one of the DMA modes by using DMA Select in the Host Control 1 register. +Values: +0x1 (ENABLED): DMA Data transfer +0x0 (DISABLED): No data transfer or Non-DMA data transfer + 0 + 1 + read-write + + + + + RESP_RESP01 + No description avaiable + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + + RESP_RESP23 + No description avaiable + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + + RESP_RESP45 + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + + RESP_RESP67 + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + + BUF_DATA + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF_DATA + Buffer Data +These bits enable access to the Host Controller packet buffer. + 0 + 32 + read-write + + + + + PSTATE + No description avaiable + 0x24 + 32 + 0x00000000 + 0x19FF0FFF + + + SUB_CMD_STAT + Sub Command Status +This bit is used to distinguish between a main command and a sub command status. +Values: +0x0 (FALSE): Main Command Status +0x1 (TRUE): Sub Command Status + 28 + 1 + read-only + + + CMD_ISSUE_ERR + Command Not Issued by Error +This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. +Values: +0x0 (FALSE): No error for issuing a command +0x1 (TRUE): Command cannot be issued + 27 + 1 + read-only + + + CMD_LINE_LVL + Command-Line Signal Level +This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. + 24 + 1 + read-only + + + DAT_3_0 + DAT[3:0] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. + 20 + 4 + read-only + + + WR_PROTECT_SW_LVL + Write Protect Switch Pin Level +This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. +Values: +0x0 (FALSE): Write protected +0x1 (TRUE): Write enabled + 19 + 1 + read-only + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level +This bit reflects the inverse synchronized value of the card_detect_n signal. +Values: +0x0 (FALSE): No card present +0x1 (TRUE): Card Present + 18 + 1 + read-only + + + CARD_STABLE + Card Stable +This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. +Values: +0x0 (FALSE): Reset or Debouncing +0x1 (TRUE): No Card or Inserted + 17 + 1 + read-only + + + CARD_INSERTED + Card Inserted +This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. +Values: +0x0 (FALSE): Reset, Debouncing, or No card +0x1 (TRUE): Card Inserted + 16 + 1 + read-only + + + BUF_RD_ENABLE + Buffer Read Enable +This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. +Values: +0x0 (DISABLED): Read disable +0x1 (ENABLED): Read enable + 11 + 1 + read-only + + + BUF_WR_ENABLE + Buffer Write Enable +This bit is used for non-DMA transfers. This bit is set if space is available for writing data. +Values: +0x0 (DISABLED): Write disable +0x1 (ENABLED): Write enable + 10 + 1 + read-only + + + RD_XFER_ACTIVE + Read Transfer Active +This bit indicates whether a read transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 9 + 1 + read-only + + + WR_XFER_ACTIVE + Write Transfer Active +This status indicates whether a write transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 8 + 1 + read-only + + + DAT_7_4 + DAT[7:4] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. + 4 + 4 + read-only + + + RE_TUNE_REQ + Re-Tuning Request +SDXC does not generate retuning request. The software must maintain the Retuning timer. + 3 + 1 + read-only + + + DAT_LINE_ACTIVE + DAT Line Active ( +This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. +In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. +In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. +For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. +Values: +0x0 (INACTIVE): DAT Line Inactive +0x1 (ACTIVE): DAT Line Active + 2 + 1 + read-only + + + DAT_INHIBIT + Command Inhibit (DAT) +This bit is generated if either DAT line active or Read transfer active is set to 1. +If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. +Values: +0x0 (READY): Can issue command which used DAT line +0x1 (NOT_READY): Cannot issue command which used DAT line + 1 + 1 + read-only + + + CMD_INHIBIT + Command Inhibit (CMD) +This bit indicates the following : +If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. +This bit is set when the command register is written. This bit is cleared when the command response is received. +This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. +Values: +0x0 (READY): Host Controller is ready to issue a command +0x1 (NOT_READY): Host Controller is not ready to issue a command + 0 + 1 + read-only + + + + + PROT_CTRL + No description avaiable + 0x28 + 32 + 0x00000000 + 0x070F0E3E + + + CARD_REMOVAL + Wakeup Event Enable on SD Card Removal +This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. +For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 26 + 1 + read-write + + + CARD_INSERT + Wakeup Event Enable on SD Card Insertion +This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. +FN_WUS (Wake Up Support) in CIS does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 25 + 1 + read-write + + + CARD_INT + Wakeup Event Enable on Card Interrupt +This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. +This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 24 + 1 + read-write + + + INT_AT_BGAP + Interrupt At Block Gap +This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. +Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. +Values: +0x0 (DISABLE): Disabled +0x1 (ENABLE): Enabled + 19 + 1 + read-write + + + RD_WAIT_CTRL + Read Wait Control +This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. +Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. +Values: +0x0 (DISABLE): Disable Read Wait Control +0x1 (ENABLE): Enable Read Wait Control + 18 + 1 + read-write + + + CONTINUE_REQ + Continue Request +This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. +The Host Controller automatically clears this bit when the transaction restarts. +If stop at block gap request is set to 1, any write to this bit is ignored. +Values: +0x0 (NO_AFFECT): No Affect +0x1 (RESTART): Restart + 17 + 1 + read-write + + + STOP_BG_REQ + Stop At Block Gap Request +This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. +Values: +0x0 (XFER): Transfer +0x1 (STOP): Stop + 16 + 1 + read-write + + + SD_BUS_VOL_VDD1 + SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD +These bits enable the Host Driver to select the voltage level for an SD/eMMC card. +Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. +If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. +The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. +SD Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 3.0V(Typical) +0x5 : 1.8V(Typical) for Embedded +0x4 : 0x0 - Reserved +eMMC Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 1.8V(Typical) +0x5 : 1.2V(Typical) +0x4 : 0x0 - Reserved +Values: +0x7 (V_3_3): 3.3V (Typ.) +0x6 (V_3_0): 3.0V (Typ.) +0x5 (V_1_8): 1.8V (Typ.) for Embedded +0x4 (RSVD4): Reserved +0x3 (RSVD3): Reserved +0x2 (RSVD2): Reserved +0x1 (RSVD1): Reserved +0x0 (RSVD0): Reserved + 9 + 3 + read-write + + + EXT_DAT_XFER + Extended Data Transfer Width +This bit controls 8-bit bus width mode of embedded device. +Values: +0x1 (EIGHT_BIT): 8-bit Bus Width +0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width + 5 + 1 + read-write + + + DMA_SEL + DMA Select +This field is used to select the DMA type. +When Host Version 4 Enable is 1 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : ADMA2 is selected +0x3 : ADMA2 or ADMA3 is selected +When Host Version 4 Enable is 0 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : 32-bit Address ADMA2 is selected +0x3 : 64-bit Address ADMA2 is selected +Values: +0x0 (SDMA): SDMA is selected +0x1 (RSVD_BIT): Reserved +0x2 (ADMA2): ADMA2 is selected +0x3 (ADMA2_3): ADMA2 or ADMA3 is selected + 3 + 2 + read-write + + + HIGH_SPEED_EN + High Speed Enable +this bit is used to determine the selection of preset value for High Speed mode. +Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. +Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. +Values: +0x1 (HIGH_SPEED): High Speed mode +0x0 (NORMAL_SPEED): Normal Speed mode + 2 + 1 + read-write + + + DAT_XFER_WIDTH + Data Transfer Width +For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. +The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. +Values: +0x1 (FOUR_BIT): 4-bit mode +0x0 (ONE_BIT): 1-bit mode + 1 + 1 + read-write + + + + + SYS_CTRL + No description avaiable + 0x2c + 32 + 0x00000000 + 0x070FFFEF + + + SW_RST_DAT + Software Reset For DAT line +This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. +The following registers and bits are cleared by this bit: +Buffer Data Port register +-Buffer is cleared and initialized. +Present state register +-Buffer Read Enable +-Buffer Write Enable +-Read Transfer Active +-Write Transfer Active +-DAT Line Active +-Command Inhibit (DAT) +Block Gap Control register +-Continue Request +-Stop At Block Gap Request +Normal Interrupt status register +-Buffer Read Ready +-Buffer Write Ready +-DMA Interrupt +-Block Gap Event +-Transfer Complete +In UHS-II mode, this bit shall be set to 0 +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 26 + 1 + read-write + + + SW_RST_CMD + Software Reset For CMD line +This bit resets only a part of the command circuit to be able to issue a command. +It bit is also used to initialize a UHS-II command circuit. +This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. +Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. +The following registers and bits are cleared by this bit: +Present State register : Command Inhibit (CMD) bit +Normal Interrupt Status register : Command Complete bit +Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 25 + 1 + read-write + + + SW_RST_ALL + Software Reset For All +This reset affects the entire Host Controller except for the card detection circuit. +During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. +All registers are reset except the capabilities register. +If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 24 + 1 + read-write + + + TOUT_CNT + Data Timeout Counter Value. +This value determines the interval by which DAT line timeouts are detected. +The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. +When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). +The values for these bits are: +0xF : Reserved +0xE : TMCLK x 2^27 +......... +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 +Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. + 16 + 4 + read-write + + + FREQ_SEL + SDCLK/RCLK Frequency Select +These bits are used to select the frequency of the SDCLK signal. +These bits depend on setting of Preset Value Enable in the Host Control 2 register. +If Preset Value Enable = 0, these bits are set by the Host Driver. +If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. +The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. +10-bit Divided Clock Mode: +0x3FF : 1/2046 Divided clock +.......... +N : 1/2N Divided Clock +.......... +0x002 : 1/4 Divided Clock +0x001 : 1/2 Divided Clock +0x000 : Base clock (10MHz - 255 MHz) +Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: +0x3FF : Base clock * M /1024 +.......... +N-1 : Base clock * M /N +.......... +0x002 : Base clock * M /3 +0x001 : Base clock * M /2 +0x000 : Base clock * M + 8 + 8 + read-write + + + UPPER_FREQ_SEL + These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. +The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. + 6 + 2 + read-write + + + CLK_GEN_SELECT + Clock Generator Select +This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. +If Preset Value Enable = 0, this bit is set by the Host Driver. +If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. +The value is reflected on the card_clk_gen_sel signal. +Values: +0x0 (FALSE): Divided Clock Mode +0x1 (TRUE): Programmable Clock Mode + 5 + 1 + read-write + + + PLL_ENABLE + PLL Enable +This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). +When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. +Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): PLL is in low power mode +0x1 (TRUE): PLL is enabled + 3 + 1 + read-write + + + SD_CLK_EN + SD/eMMC Clock Enable +This bit stops the SDCLK or RCLK when set to 0. +The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. +The value is reflected on the clk2card_on pin. +Values: +0x0 (FALSE): Disable providing SDCLK/RCLK +0x1 (TRUE): Enable providing SDCLK/RCLK + 2 + 1 + read-write + + + INTERNAL_CLK_STABLE + Internal Clock Stable +This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. +This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, +and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. +Values: +0x0 (FALSE): Not Ready +0x1 (TRUE): Ready + 1 + 1 + read-write + + + INTERNAL_CLK_EN + Internal Clock Enable +This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. +The Host Controller must stop its internal clock to enter a very low power state. +However, registers can still be read and written to. The value is reflected on the intclk_en signal. +Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): Stop +0x1 (TRUE): Oscillate + 0 + 1 + read-write + + + + + INT_STAT + No description avaiable + 0x30 + 32 + 0x00000000 + 0x1FFFF1FF + + + BOOT_ACK_ERR + Boot Acknowledgement Error +This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. +In SD/UHS-II mode, this bit is irrelevant. + 28 + 1 + read-write + + + RESP_ERR + Response Error +Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 27 + 1 + read-write + + + TUNING_ERR + Tuning Error +This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure +(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). +By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. +To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. +The Tuning Error is higher priority than the other error interrupts generated during data transfer. +By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. +This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 26 + 1 + read-write + + + ADMA_ERR + ADMA Error +This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: +Error response received from System bus (Master I/F) +ADMA3,ADMA2 Descriptors invalid +CQE Task or Transfer descriptors invalid +When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. +In eMMC CQE mode: +The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. +ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. +The Host Driver may find that Valid bit is not set at the error descriptor. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 25 + 1 + read-write + + + AUTO_CMD_ERR + Auto CMD Error +This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. +This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. +D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 24 + 1 + read-write + + + CUR_LMT_ERR + Current Limit Error +By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. +If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. +A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. +A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. +The Host Controller may require some sampling time to detect the current limit. +SDXC Host Controller does not support this function, this bit is always set to 0. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Power Fail + 23 + 1 + read-write + + + DATA_END_BIT_ERR + Data End Bit Error +This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 22 + 1 + read-write + + + DATA_CRC_ERR + Data CRC Error +This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, +when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 21 + 1 + read-write + + + DATA_TOUT_ERR + Data Timeout Error +This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: +Busy timeout for R1b, R5b type +Busy timeout after Write CRC status +Write CRC Status timeout +Read Data timeout +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 20 + 1 + read-write + + + CMD_IDX_ERR + Command Index Error +This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR + Command End Bit Error +This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): End Bit error generated + 18 + 1 + read-write + + + CMD_CRC_ERR + Command CRC Error +Command CRC Error is generated in SD/eMMC mode for following two cases. +If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. +The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. +If the Host Controller drives the CMD line to 1 level, +but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. +The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. +Values: +0x0 (FALSE): No error +0x1 (TRUE): CRC error generated + 17 + 1 + read-write + + + CMD_TOUT_ERR + Command Timeout Error +In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. +If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 16 + 1 + read-write + + + ERR_INTERRUPT + Error Interrupt +If any of the bits in the Error Interrupt Status register are set, then this bit is set. +Values: +0x0 (FALSE): No Error +0x1 (TRUE): Error + 15 + 1 + read-only + + + CQE_EVENT + Command Queuing Event +This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): Command Queuing Event is detected + 14 + 1 + read-write + + + FX_EVENT + FX Event +This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): FX Event is detected + 13 + 1 + read-only + + + RE_TUNE_EVENT + Re-tuning Event +This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. + 12 + 1 + read-only + + + CARD_INTERRUPT + Card Interrupt +This bit reflects the synchronized value of: +DAT[1] Interrupt Input for SD Mode +DAT[2] Interrupt Input for UHS-II Mode +Values: +0x0 (FALSE): No Card Interrupt +0x1 (TRUE): Generate Card Interrupt + 8 + 1 + read-only + + + CARD_REMOVAL + Card Removal +This bit is set if the Card Inserted in the Present State register changes from 1 to 0. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Removed + 7 + 1 + read-write + + + CARD_INSERTION + Card Insertion +This bit is set if the Card Inserted in the Present State register changes from 0 to 1. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Inserted + 6 + 1 + read-write + + + BUF_RD_READY + Buffer Read Ready +This bit is set if the Buffer Read Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to read buffer +0x1 (TRUE): Ready to read buffer + 5 + 1 + read-write + + + BUF_WR_READY + Buffer Write Ready +This bit is set if the Buffer Write Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to write buffer +0x1 (TRUE): Ready to write buffer + 4 + 1 + read-write + + + DMA_INTERRUPT + DMA Interrupt +This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. +In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. +This interrupt is not generated after a Transfer Complete. +Values: +0x0 (FALSE): No DMA Interrupt +0x1 (TRUE): DMA Interrupt is generated + 3 + 1 + read-write + + + BGAP_EVENT + Block Gap Event +This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. +Values: +0x0 (FALSE): No Block Gap Event +0x1 (TRUE): Transaction stopped at block gap + 2 + 1 + read-write + + + XFER_COMPLETE + Transfer Complete +This bit is set when a read/write transfer and a command with status busy is completed. +Values: +0x0 (FALSE): Not complete +0x1 (TRUE): Command execution is completed + 1 + 1 + read-write + + + CMD_COMPLETE + Command Complete +In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. +This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. +Values: +0x0 (FALSE): No command complete +0x1 (TRUE): Command Complete + 0 + 1 + read-write + + + + + INT_STAT_EN + No description avaiable + 0x34 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_STAT_EN + Boot Acknowledgment Error (eMMC Mode only) +Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_STAT_EN + Response Error Status Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_STAT_EN + Tuning Error Status Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_STAT_EN + ADMA Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_STAT_EN + Auto CMD Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_STAT_EN + Current Limit Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_STAT_EN + Data End Bit Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_STAT_EN + Data CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_STAT_EN + Data Timeout Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_STAT_EN + Command Index Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 19 + 1 + read-write + + + CMD_END_BIT_ERR_STAT_EN + Command End Bit Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_STAT_EN + Command CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_STAT_EN + Command Timeout Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_STAT_EN + CQE Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_STAT_EN + FX Event Status Enable +This bit is added from Version 4.10. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_STAT_EN + Re-Tuning Event (UHS-I only) Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_STAT_EN + Card Interrupt Status Enable +If this bit is set to 0, the Host Controller clears the interrupt request to the System. +The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. +The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. +By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_STAT_EN + Card Removal Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_STAT_EN + Card Insertion Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_STAT_EN + Buffer Read Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_STAT_EN + Buffer Write Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_STAT_EN + DMA Interrupt Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_STAT_EN + Block Gap Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_STAT_EN + Transfer Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_STAT_EN + Command Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + INT_SIGNAL_EN + No description avaiable + 0x38 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_SIGNAL_EN + Boot Acknowledgment Error (eMMC Mode only). +Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgement Error in Error Interrupt Status register is set. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_SIGNAL_EN + Response Error Signal Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_SIGNAL_EN + Tuning Error Signal Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_SIGNAL_EN + ADMA Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_SIGNAL_EN + Auto CMD Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_SIGNAL_EN + Current Limit Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_SIGNAL_EN + Data End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_SIGNAL_EN + Data CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_SIGNAL_EN + Data Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_SIGNAL_EN + Command Index Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR_SIGNAL_EN + Command End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_SIGNAL_EN + Command CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_SIGNAL_EN + Command Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_SIGNAL_EN + Command Queuing Engine Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_SIGNAL_EN + FX Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_SIGNAL_EN + Re-Tuning Event (UHS-I only) Signal Enable. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_SIGNAL_EN + Card Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_SIGNAL_EN + Card Removal Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_SIGNAL_EN + Card Insertion Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_SIGNAL_EN + Buffer Read Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_SIGNAL_EN + Buffer Write Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_SIGNAL_EN + DMA Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_SIGNAL_EN + Block Gap Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_SIGNAL_EN + Transfer Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_SIGNAL_EN + Command Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + AC_HOST_CTRL + No description avaiable + 0x3c + 32 + 0x00000000 + 0xDCCF00BF + + + PRESET_VAL_ENABLE + Preset Value Enable +This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. +When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. +These values are selected from set of Preset Value registers based on selected speed mode. +Values: +0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver +0x1 (TRUE): Automatic Selection by Preset Value are Enabled + 31 + 1 + read-write + + + ASYNC_INT_ENABLE + Asynchronous Interrupt Enable +This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. +Values: +0x0 (FALSE): Disabled +0x1 (TRUE): Enabled + 30 + 1 + read-write + + + HOST_VER4_ENABLE + Host Version 4 Enable +This bit selects either Version 3.00 compatible mode or Version 4 mode. +Functions of following fields are modified for Host Version 4 mode: +SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) +ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register +64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 +Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register +32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register +Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, +UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). +Values: +0x0 (FALSE): Version 3.00 compatible mode +0x1 (TRUE): Version 4 mode + 28 + 1 + read-write + + + CMD23_ENABLE + CMD23 Enable +If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. +Values: +0x0 (FALSE): Auto CMD23 is disabled +0x1 (TRUE): Auto CMD23 is enabled + 27 + 1 + read-write + + + ADMA2_LEN_MODE + ADMA2 Length Mode +This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. +Values: +0x0 (FALSE): 16-bit Data Length Mode +0x1 (TRUE): 26-bit Data Length Mode + 26 + 1 + read-write + + + SAMPLE_CLK_SEL + Sampling Clock Select +This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. +This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). +Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. +The value is reflected on the sample_cclk_sel pin. +Values: +0x0 (FALSE): Fixed clock is used to sample data +0x1 (TRUE): Tuned clock is used to sample data + 23 + 1 + read-write + + + EXEC_TUNING + Execute Tuning +This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. +Values: +0x0 (FALSE): Not Tuned or Tuning completed +0x1 (TRUE): Execute Tuning + 22 + 1 + read-write + + + SIGNALING_EN + 1.8V Signaling Enable +This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. +Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. +Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. +Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). +Values: +0x0 (V_3_3): 3.3V Signalling +0x1 (V_1_8): 1.8V Signalling + 19 + 1 + read-write + + + UHS_MODE_SEL + UHS Mode/eMMC Speed Mode Select +These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. +UHS Mode (SD/UHS-II mode only): +0x0 (SDR12): SDR12/Legacy +0x1 (SDR25): SDR25/High Speed SDR +0x2 (SDR50): SDR50 +0x3 (SDR104): SDR104/HS200 +0x4 (DDR50): DDR50/High Speed DDR +0x5 (RSVD5): Reserved +0x6 (RSVD6): Reserved +0x7 (UHS2): UHS-II/HS400 +eMMC Speed Mode (eMMC mode only): +0x0: Legacy +0x1: High Speed SDR +0x2: Reserved +0x3: HS200 +0x4: High Speed DDR +0x5: Reserved +0x6: Reserved +0x7: HS400 + 16 + 3 + read-write + + + CMD_NOT_ISSUED_AUTO_CMD12 + Command Not Issued By Auto CMD12 Error +If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Issued +0x0 (FALSE): No Error + 7 + 1 + read-only + + + AUTO_CMD_RESP_ERR + Auto CMD Response Error +This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. +This status is ignored if any bit between D00 to D04 is set to 1. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 5 + 1 + read-only + + + AUTO_CMD_IDX_ERR + Auto CMD Index Error +This bit is set if the command index error occurs in response to a command. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 4 + 1 + read-only + + + AUTO_CMD_EBIT_ERR + Auto CMD End Bit Error +This bit is set when detecting that the end bit of command response is 0. +Values: +0x1 (TRUE): End Bit Error Generated +0x0 (FALSE): No Error + 3 + 1 + read-only + + + AUTO_CMD_CRC_ERR + Auto CMD CRC Error +This bit is set when detecting a CRC error in the command response. +Values: +0x1 (TRUE): CRC Error Generated +0x0 (FALSE): No Error + 2 + 1 + read-only + + + AUTO_CMD_TOUT_ERR + Auto CMD Timeout Error +This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. +If this bit is set to 1, error status bits (D04-D01) are meaningless. +Values: +0x1 (TRUE): Time out +0x0 (FALSE): No Error + 1 + 1 + read-only + + + AUTO_CMD12_NOT_EXEC + Auto CMD12 Not Executed +If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. +Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. + If this bit is set to 1, error status bits (D04-D01) is meaningless. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Executed +0x0 (FALSE): Executed + 0 + 1 + read-only + + + + + CAPABILITIES1 + No description avaiable + 0x40 + 32 + 0x00000000 + 0xE7EFFFBF + + + SLOT_TYPE_R + Slot Type +These bits indicate usage of a slot by a specific Host System. +Values: +0x0 (REMOVABLE_SLOT): Removable Card Slot +0x1 (EMBEDDED_SLOT): Embedded Slot for one Device +0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) +0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices + 30 + 2 + read-only + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support (SD Mode only) +Values: +0x0 (FALSE): Asynchronous Interrupt Not Supported +0x1 (TRUE): Asynchronous Interrupt Supported + 29 + 1 + read-only + + + VOLT_18 + Voltage Support for 1.8V +Values: +0x0 (FALSE): 1.8V Not Supported +0x1 (TRUE): 1.8V Supported + 26 + 1 + read-only + + + VOLT_30 + Voltage Support for SD 3.0V or Embedded 1.2V +Values: +0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported +0x1 (TRUE): SD 3.0V or Embedded Supported + 25 + 1 + read-only + + + VOLT_33 + Voltage Support for 3.3V +Values: +0x0 (FALSE): 3.3V Not Supported +0x1 (TRUE): 3.3V Supported + 24 + 1 + read-only + + + SUS_RES_SUPPORT + Suspense/Resume Support +This bit indicates whether the Host Controller supports Suspend/Resume functionality. +If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. +Values: +0x0 (FALSE): Not Supported +0x1 (TRUE): Supported + 23 + 1 + read-only + + + SDMA_SUPPORT + SDMA Support +This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. +Values: +0x0 (FALSE): SDMA not Supported +0x1 (TRUE): SDMA Supported + 22 + 1 + read-only + + + HIGH_SPEED_SUPPORT + High Speed Support +This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. +Values: +0x0 (FALSE): High Speed not Supported +0x1 (TRUE): High Speed Supported + 21 + 1 + read-only + + + ADMA2_SUPPORT + ADMA2 Support +This bit indicates whether the Host Controller is capable of using ADMA2. +Values: +0x0 (FALSE): ADMA2 not Supported +0x1 (TRUE): ADMA2 Supported + 19 + 1 + read-only + + + EMBEDDED_8_BIT + 8-bit Support for Embedded Device +This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. +Values: +0x0 (FALSE): 8-bit Bus Width not Supported +0x1 (TRUE): 8-bit Bus Width Supported + 18 + 1 + read-only + + + MAX_BLK_LEN + Maximum Block Length +This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. +The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit +Values: +0x0 (ZERO): 512 Byte +0x1 (ONE): 1024 Byte +0x2 (TWO): 2048 Byte +0x3 (THREE): Reserved + 16 + 2 + read-only + + + BASE_CLK_FREQ + Base Clock Frequency for SD clock +These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. +6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. +The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............. +-0x3F : 63 MHz +-0x40-0xFF : Not Supported +8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............ +-0xFF : 255 MHz +If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. +If these bits are all 0, the Host system has to get information using a different method. + 8 + 8 + read-only + + + TOUT_CLK_UNIT + Timeout Clock Unit +This bit shows the unit of base clock frequency used to detect Data TImeout Error. +Values: +0x0 (KHZ): KHz +0x1 (MHZ): MHz + 7 + 1 + read-only + + + TOUT_CLK_FREQ + Timeout Clock Frequency +This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. +0x00 : Get information through another method +0x01 : 1KHz / 1MHz +0x02 : 2KHz / 2MHz +0x03 : 3KHz / 3MHz + ........... +0x3F : 63KHz / 63MHz + 0 + 6 + read-only + + + + + CAPABILITIES2 + No description avaiable + 0x44 + 32 + 0x00000000 + 0x18FFEF7F + + + VDD2_18V_SUPPORT + 1.8V VDD2 Support +This bit indicates support of VDD2 for the Host System. +0x0 (FALSE): 1.8V VDD2 is not Supported +0x1 (TRUE): 1.8V VDD2 is Supported + 28 + 1 + read-only + + + ADMA3_SUPPORT + ADMA3 Support +This bit indicates whether the Host Controller is capable of using ADMA3. +Values: +0x0 (FALSE): ADMA3 not Supported +0x1 (TRUE): ADMA3 Supported + 27 + 1 + read-only + + + CLK_MUL + Clock Multiplier +These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. +0x0: Clock Multiplier is not Supported +0x1: Clock Multiplier M = 2 +0x2: Clock Multiplier M = 3 + ......... +0xFF: Clock Multiplier M = 256 + 16 + 8 + read-only + + + RE_TUNING_MODES + Re-Tuning Modes (UHS-I only) +These bits select the re-tuning method and limit the maximum data length. +Values: +0x0 (MODE1): Timer +0x1 (MODE2): Timer and Re-Tuning Request (Not supported) +0x2 (MODE3): Auto Re-Tuning (for transfer) +0x3 (RSVD_MODE): Reserved + 14 + 2 + read-only + + + USE_TUNING_SDR50 + Use Tuning for SDR50 (UHS-I only) +Values: +0x0 (ZERO): SDR50 does not require tuning +0x1 (ONE): SDR50 requires tuning + 13 + 1 + read-only + + + RETUNE_CNT + Timer Count for Re-Tuning (UHS-I only) +0x0: Re-Tuning Timer disabled +0x1: 1 seconds +0x2: 2 seconds +0x3: 4 seconds + ........ +0xB: 1024 seconds +0xC: Reserved +0xD: Reserved +0xE: Reserved +0xF: Get information from other source + 8 + 4 + read-only + + + DRV_TYPED + Driver Type D Support (UHS-I only) +This bit indicates support of Driver Type D for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type D is not supported +0x1 (TRUE): Driver Type D is supported + 6 + 1 + read-only + + + DRV_TYPEC + Driver Type C Support (UHS-I only) +This bit indicates support of Driver Type C for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type C is not supported +0x1 (TRUE): Driver Type C is supported + 5 + 1 + read-only + + + DRV_TYPEA + Driver Type A Support (UHS-I only) +This bit indicates support of Driver Type A for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type A is not supported +0x1 (TRUE): Driver Type A is supported + 4 + 1 + read-only + + + UHS2_SUPPORT + UHS-II Support (UHS-II only) +This bit indicates whether Host Controller supports UHS-II. +Values: +0x0 (FALSE): UHS-II is not supported +0x1 (TRUE): UHS-II is supported + 3 + 1 + read-only + + + DDR50_SUPPORT + DDR50 Support (UHS-I only) +Values: +0x0 (FALSE): DDR50 is not supported +0x1 (TRUE): DDR50 is supported + 2 + 1 + read-only + + + SDR104_SUPPORT + SDR104 Support (UHS-I only) +This bit mentions that SDR104 requires tuning. +Values: +0x0 (FALSE): SDR104 is not supported +0x1 (TRUE): SDR104 is supported + 1 + 1 + read-only + + + SDR50_SUPPORT + SDR50 Support (UHS-I only) +This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. +Values: +0x0 (FALSE): SDR50 is not supported +0x1 (TRUE): SDR50 is supported + 0 + 1 + read-only + + + + + CURR_CAPABILITIES1 + No description avaiable + 0x48 + 32 + 0x00000000 + 0x00FFFFFF + + + MAX_CUR_18V + Maximum Current for 1.8V +This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 16 + 8 + read-only + + + MAX_CUR_30V + Maximum Current for 3.0V +This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 8 + 8 + read-only + + + MAX_CUR_33V + Maximum Current for 3.3V +This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + CURR_CAPABILITIES2 + No description avaiable + 0x4c + 32 + 0x00000000 + 0x000000FF + + + MAX_CUR_VDD2_18V + Maximum Current for 1.8V VDD2 +This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + FORCE_EVENT + No description avaiable + 0x50 + 32 + 0x00000000 + 0x1FFF00BF + + + FORCE_BOOT_ACK_ERR + Force Event for Boot Ack error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Boot ack Error Status is set + 28 + 1 + write-only + + + FORCE_RESP_ERR + Force Event for Response Error (SD Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Response Error Status is set + 27 + 1 + write-only + + + FORCE_TUNING_ERR + Force Event for Tuning Error (UHS-I Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Tuning Error Status is set + 26 + 1 + write-only + + + FORCE_ADMA_ERR + Force Event for ADMA Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): ADMA Error Status is set + 25 + 1 + write-only + + + FORCE_AUTO_CMD_ERR + Force Event for Auto CMD Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Auto CMD Error Status is set + 24 + 1 + write-only + + + FORCE_CUR_LMT_ERR + Force Event for Current Limit Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Current Limit Error Status is set + 23 + 1 + write-only + + + FORCE_DATA_END_BIT_ERR + Force Event for Data End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data End Bit Error Status is set + 22 + 1 + write-only + + + FORCE_DATA_CRC_ERR + Force Event for Data CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data CRC Error Status is set + 21 + 1 + write-only + + + FORCE_DATA_TOUT_ERR + Force Event for Data Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data Timeout Error Status is set + 20 + 1 + write-only + + + FORCE_CMD_IDX_ERR + Force Event for Command Index Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Index Error Status is set + 19 + 1 + write-only + + + FORCE_CMD_END_BIT_ERR + Force Event for Command End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command End Bit Error Status is set + 18 + 1 + write-only + + + FORCE_CMD_CRC_ERR + Force Event for Command CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command CRC Error Status is set + 17 + 1 + write-only + + + FORCE_CMD_TOUT_ERR + Force Event for Command Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Timeout Error Status is set + 16 + 1 + write-only + + + FORCE_CMD_NOT_ISSUED_AUTO_CMD12 + Force Event for Command Not Issued By Auto CMD12 Error +Values: +0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set +0x0 (FALSE): Not Affected + 7 + 1 + write-only + + + FORCE_AUTO_CMD_RESP_ERR + Force Event for Auto CMD Response Error +Values: +0x1 (TRUE): Auto CMD Response Error Status is set +0x0 (FALSE): Not Affected + 5 + 1 + write-only + + + FORCE_AUTO_CMD_IDX_ERR + Force Event for Auto CMD Index Error +Values: +0x1 (TRUE): Auto CMD Index Error Status is set +0x0 (FALSE): Not Affected + 4 + 1 + write-only + + + FORCE_AUTO_CMD_EBIT_ERR + Force Event for Auto CMD End Bit Error +Values: +0x1 (TRUE): Auto CMD End Bit Error Status is set +0x0 (FALSE): Not Affected + 3 + 1 + write-only + + + FORCE_AUTO_CMD_CRC_ERR + Force Event for Auto CMD CRC Error +Values: +0x1 (TRUE): Auto CMD CRC Error Status is set +0x0 (FALSE): Not Affected + 2 + 1 + write-only + + + FORCE_AUTO_CMD_TOUT_ERR + Force Event for Auto CMD Timeout Error +Values: +0x1 (TRUE): Auto CMD Timeout Error Status is set +0x0 (FALSE): Not Affected + 1 + 1 + write-only + + + FORCE_AUTO_CMD12_NOT_EXEC + Force Event for Auto CMD12 Not Executed +Values: +0x1 (TRUE): Auto CMD12 Not Executed Status is set +0x0 (FALSE): Not Affected + 0 + 1 + write-only + + + + + ADMA_ERR_STAT + No description avaiable + 0x54 + 32 + 0x00000000 + 0x00000007 + + + ADMA_LEN_ERR + ADMA Length Mismatch Error States +This error occurs in the following instances: +While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length +When the total data length cannot be divided by the block length +Values: +0x0 (NO_ERR): No Error +0x1 (ERROR): Error + 2 + 1 + read-only + + + ADMA_ERR_STATES + ADMA Error States +These bits indicate the state of ADMA when an error occurs during ADMA data transfer. +Values: +0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor +0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor +0x2 (UNUSED): Never set this state +0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor + 0 + 2 + read-only + + + + + ADMA_SYS_ADDR + No description avaiable + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_SA + ADMA System Address +These bits indicate the lower 32 bits of the ADMA system address. +SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location +ADMA2: This register stores the byte address of the executing command of the descriptor table +ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. + 0 + 32 + read-write + + + + + PRESET_INIT + No description avaiable + 0x60 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_DS + No description avaiable + 0x62 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_HS + No description avaiable + 0x64 + 16 + 0x0001 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_SDR12 + No description avaiable + 0x66 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_SDR25 + No description avaiable + 0x68 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_SDR50 + No description avaiable + 0x6a + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_SDR104 + No description avaiable + 0x6c + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_DDR50 + No description avaiable + 0x6e + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_UHS2 + No description avaiable + 0x74 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + ADMA_ID_ADDR + No description avaiable + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_ID_ADDR + ADMA Integrated Descriptor Address +These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. +The start address of Integrated Descriptor is set to these register bits. +The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. + 0 + 32 + read-write + + + + + P_EMBEDDED_CNTRL + No description avaiable + 0xe6 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Offset Address of Embedded Control register. + 0 + 12 + read-only + + + + + P_VENDOR_SPECIFIC_AREA + No description avaiable + 0xe8 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Base offset Address for Vendor-Specific registers. + 0 + 12 + read-only + + + + + P_VENDOR2_SPECIFIC_AREA + No description avaiable + 0xea + 16 + 0x0000 + 0xFFFF + + + REG_OFFSET_ADDR + Base offset Address for Command Queuing registers. + 0 + 16 + read-only + + + + + SLOT_INTR_STATUS + No description avaiable + 0xfc + 16 + 0x0000 + 0x00FF + + + INTR_SLOT + Interrupt signal for each Slot +These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. +A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. + By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. +Bit 00: Slot 1 +Bit 01: Slot 2 +Bit 02: Slot 3 +.......... +.......... +Bit 07: Slot 8 +Note: MSHC Host Controller support single card slot. This register shall always return 0. + 0 + 8 + read-only + + + + + CQVER + No description avaiable + 0x180 + 32 + 0x00000000 + 0x00000FFF + + + EMMC_VER_MAHOR + This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. + 8 + 4 + read-only + + + EMMC_VER_MINOR + This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. + 4 + 4 + read-only + + + EMMC_VER_SUFFIX + This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. + 0 + 4 + read-only + + + + + CQCAP + No description avaiable + 0x184 + 32 + 0x00000000 + 0x1000F3FF + + + CRYPTO_SUPPORT + Crypto Support +This bit indicates whether the Host Controller supports cryptographic operations. +Values: +0x0 (FALSE): Crypto not Supported +0x1 (TRUE): Crypto Supported + 28 + 1 + read-only + + + ITCFMUL + Internal Timer Clock Frequency Multiplier (ITCFMUL) +This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS +polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. +Values: +0x0 (CLK_1KHz): 1KHz clock +0x1 (CLK_10KHz): 10KHz clock +0x2 (CLK_100KHz): 100KHz clock +0x3 (CLK_1MHz): 1MHz clock +0x4 (CLK_10MHz): 10MHz clock + 12 + 4 + read-only + + + ITCFVAL + Internal Timer Clock Frequency Value (ITCFVAL) +This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. + 0 + 10 + read-only + + + + + CQCFG + No description avaiable + 0x188 + 32 + 0x00000000 + 0x00001101 + + + DCMD_EN + This bit indicates to the hardware whether the Task +Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. +Values: +0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor +0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor + 12 + 1 + read-write + + + TASK_DESC_SIZE + Bit Value Description +This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). +Values: +0x1 (TASK_DESC_128b): Task descriptor size is 128 bits +0x0 (TASK_DESC_64b): Task descriptor size is 64 bit + 8 + 1 + read-write + + + CQ_EN + No description avaiable + 0 + 1 + read-write + + + + + CQCTL + No description avaiable + 0x18c + 32 + 0x00000000 + 0x00000101 + + + CLR_ALL_TASKS + Clear all tasks +This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. +Values: +0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller +0x0 (NO_EFFECT): Programming 0 has no effect + 8 + 1 + read-write + + + HALT + Halt request and resume +Values: +0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. +For example, issuing a Discard Task command (CMDQ_TASK_MGMT). +When the software writes 1, CQE completes the ongoing task (if any in progress). +After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. +The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. +0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity + 0 + 1 + read-write + + + + + CQIS + No description avaiable + 0x190 + 32 + 0x00000000 + 0x0000000F + + + TCL + Task cleared interrupt +This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. +The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). +A value of 1 clears this status bit. +Values: +0x1 (SET): TCL Interrupt is set +0x0 (NOTSET): TCL Interrupt is not set + 3 + 1 + read-write + + + RED + Response error detected interrupt +This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status +field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. +A value of 1 clears this status bit. +Values: +0x1 (SET): RED Interrupt is set +0x0 (NOTSET): RED Interrupt is not set + 2 + 1 + read-write + + + TCC + Task complete interrupt +This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: +A task is completed and the INT bit is set in its Task Descriptor +Interrupt caused by Interrupt Coalescing logic due to timeout +Interrupt Coalescing logic reached the configured threshold +A value of 1 clears this status bit + 1 + 1 + read-write + + + HAC + Halt complete interrupt +This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. +A value of 1 clears this status bit. +Values: +0x1 (SET): HAC Interrupt is set +0x0 (NOTSET): HAC Interrupt is not set + 0 + 1 + read-write + + + + + CQISE + No description avaiable + 0x194 + 32 + 0x00000000 + 0x0000000F + + + TCL_STE + Task cleared interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + 3 + 1 + read-write + + + RED_STE + Response error detected interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.RED is disabled + 2 + 1 + read-write + + + TCC_STE + Task complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + 1 + 1 + read-write + + + HAC_STE + Halt complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.HAC is disabled + 0 + 1 + read-write + + + + + CQISGE + No description avaiable + 0x198 + 32 + 0x00000000 + 0x0000000F + + + TCL_SGE + Task cleared interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled + 3 + 1 + read-write + + + RED_SGE + Response error detected interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled + 2 + 1 + read-write + + + TCC_SGE + Task complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled + 1 + 1 + read-write + + + HAC_SGE + Halt complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled + 0 + 1 + read-write + + + + + CQIC + No description avaiable + 0x19c + 32 + 0x00000000 + 0x80119FFF + + + INTC_EN + Interrupt Coalescing Enable Bit +Values: +0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated +0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) + 31 + 1 + read-write + + + INTC_STAT + Interrupt Coalescing Status Bit +This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt +coalescing (that is, this is set if and only if INTC counter > 0). +Values: +0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) +0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) + 20 + 1 + read-only + + + INTC_RST + Counter and Timer Reset +When host driver writes 1, the interrupt coalescing timer and counter are reset. +Values: +0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset +0x0 (NO_EFFECT): No Effect + 16 + 1 + write-only + + + INTC_TH_WEN + Interrupt Coalescing Counter Threshold Write Enable +When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets INTC_TH_WEN +0x0 (WEN_CLR): Clears INTC_TH_WEN + 15 + 1 + write-only + + + INTC_TH + Interrupt Coalescing Counter Threshold filed +Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. +Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. +The counter is reset by software during the interrupt service routine. +The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. +0x0: Interrupt coalescing feature disabled +0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes +0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes +........ +0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes +To write to this field, the INTC_TH_WEN bit must be set during the same write operation. + 8 + 5 + write-only + + + TOUT_VAL_WEN + When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets TOUT_VAL_WEN +0x0 (WEN_CLR): clears TOUT_VAL_WEN + 7 + 1 + write-only + + + TOUT_VAL + Interrupt Coalescing Timeout Value +Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. +Timer Operation: The timer is reset by software during the interrupt service routine. +It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. +When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. +The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +0x0: Timer is disabled. Timeout-based interrupt is not generated +0x1: Timeout on 01x1024 cycles of timer clock frequency +0x2: Timeout on 02x1024 cycles of timer clock frequency +........ +0x7f: Timeout on 127x1024 cycles of timer clock frequency +In order to write to this field, the TOUT_VAL_WEN bit must +be set at the same write operation. + 0 + 7 + read-write + + + + + CQTDLBA + No description avaiable + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDLBA + This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. +The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. +This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE + 0 + 32 + read-write + + + + + CQTDBR + No description avaiable + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DBR + The software configures TDLBA and TDLBAU, and enable +CQE in CQCFG before using this register. +Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. +Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. +CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. +CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to +the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. +The corresponding bit is cleared to 0 by CQE in one of the following events: +A task execution is completed (with success or error). +The task is cleared using CQTCLR register. +All tasks are cleared using CQCTL register. +CQE is disabled using CQCFG register. +Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. +In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. +If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. + 0 + 32 + read-write + + + + + CQTCN + No description avaiable + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + TCN + Task Completion Notification +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has completed execution (with success or errors) +Bit-N(0): Task-N has not completed, could be pending or not submitted. +On task completion, software may read this register to know tasks that have completed. After reading this register, +software may clear the relevant bit fields by writing 1 to the corresponding bits. + 0 + 32 + read-write + + + + + CQDQS + No description avaiable + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DQS + Device Queue Status +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Device has marked task N as ready for execution +Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. +Host controller updates this register with response of the Device Queue Status command. + 0 + 32 + read-write + + + + + CQDPT + No description avaiable + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DPT + Device-Pending Tasks +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution +Bit-N(0): Task-N is not yet queued. +Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. +The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. +Software reads this register in the task-discard procedure to determine if the task is queued in the device + 0 + 32 + read-write + + + + + CQTCLR + No description avaiable + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TCLR + Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. +This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. +When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. +CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. +Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. + 0 + 32 + read-write + + + + + CQSSC1 + No description avaiable + 0x1c0 + 32 + 0x00000000 + 0x000FFFFF + + + SQSCMD_BLK_CNT + This field indicates when SQS CMD is sent while data transfer is in progress. +A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. +0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. +0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. +0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. +0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. +........ +0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. +Should be programmed only when CQCFG.CQ_EN is 0 + 16 + 4 + read-write + + + SQSCMD_IDLE_TMR + This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. +Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. +When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. +Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). +For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). +If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. +Should be programmed only when CQCFG.CQ_EN is '0' + 0 + 16 + read-write + + + + + CQSSC2 + No description avaiable + 0x1c4 + 32 + 0x00000000 + 0x0000FFFF + + + SQSCMD_RCA + This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. +CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. + 0 + 16 + read-write + + + + + CQCRDCT + No description avaiable + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DCMD_RESP + This register contains the response of the command generated by the last direct command (DCMD) task that was sent. +Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. + 0 + 32 + read-only + + + + + CQRMEM + No description avaiable + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP_ERR_MASK + The bits of this field are bit mapped to the device response. +This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. +1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. +0: When a R1/R1b response is received, bit i in the device status is ignored. +The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. +Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. + 0 + 32 + read-write + + + + + CQTERRI + No description avaiable + 0x1d4 + 32 + 0x00000000 + 0x1F3F9F3F + + + TRANS_ERR_TASKID + This field captures the ID of the task that was executed and whose data transfer has errors. + 24 + 5 + read-only + + + TRANS_ERR_CMD_INDX + This field captures the index of the command that was executed and whose data transfer has errors. + 16 + 6 + read-only + + + RESP_ERR_FIELDS_VALID + This bit is updated when an error is detected while a command transaction was in progress. +Values: +0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields +0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX + 15 + 1 + read-only + + + RESP_ERR_TASKID + This field captures the ID of the task which was executed on the command line when the error occurred. + 8 + 5 + read-only + + + RESP_ERR_CMD_INDX + This field captures the index of the command that was executed on the command line when the error occurred + 0 + 6 + read-only + + + + + CQCRI + No description avaiable + 0x1d8 + 32 + 0x00000000 + 0x0000003F + + + CMD_RESP_INDX + Last Command Response index +This field stores the index of the last received command response. Controller updates the value every time a command response is received + 0 + 6 + read-only + + + + + CQCRA + No description avaiable + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_RESP_ARG + Last Command Response argument +This field stores the argument of the last received command response. Controller updates the value every time a command response is received. + 0 + 32 + read-only + + + + + MSHC_VER_ID + No description avaiable + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_ID + No description avaiable + 0 + 32 + read-only + + + + + MSHC_VER_TYPE + No description avaiable + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_TYPE + No description avaiable + 0 + 32 + read-only + + + + + MBIU_CTRL + Y + 0x510 + 32 + 0x00000000 + 0x0000000F + + + BURST_INCR16_EN + No description avaiable + 3 + 1 + read-write + + + BURST_INCR8_EN + No description avaiable + 2 + 1 + read-write + + + BUSRT_INCR4_EN + No description avaiable + 1 + 1 + read-write + + + UNDEFL_INCR_EN + No description avaiable + 0 + 1 + read-write + + + + + EMMC_BOOT_CTRL + No description avaiable + 0x52c + 32 + 0x00000000 + 0xF181070F + + + BOOT_TOUT_CNT + Boot Ack Timeout Counter Value. +This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. +0xF : Reserved +0xE : TMCLK x 2^27 + ............ +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 + 28 + 4 + read-write + + + BOOT_ACK_ENABLE + Boot Acknowledge Enable +When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. +Values: +0x1 (TRUE): Boot Ack enable +0x0 (FALSE): Boot Ack disable + 24 + 1 + read-write + + + VALIDATE_BOOT + Validate Mandatory Boot Enable bit +This bit is used to validate the MAN_BOOT_EN bit. +Values: +0x1 (TRUE): Validate Mandatory boot enable bit +0x0 (FALSE): Ignore Mandatory boot Enable bit + 23 + 1 + write-only + + + MAN_BOOT_EN + Mandatory Boot Enable +This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. +Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. +Values: +0x1 (MAN_BOOT_EN): Mandatory boot enable +0x0 (MAN_BOOT_DIS): Mandatory boot disable + 16 + 1 + read-write + + + CQE_PREFETCH_DISABLE + Enable or Disable CQE's PREFETCH feature +This field allows Software to disable CQE's data prefetch feature when set to 1. +Values: +0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers +0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled + 10 + 1 + read-write + + + CQE_ALGO_SEL + Scheduler algorithm selected for execution +This bit selects the Algorithm used for selecting one of the many ready tasks for execution. +Values: +0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks +0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings + 9 + 1 + read-write + + + ENH_STROBE_ENABLE + Enhanced Strobe Enable +This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. +Values: +0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode +0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode + 8 + 1 + read-write + + + EMMC_RST_N_OE + Output Enable control for EMMC Device Reset signal PAD +control. +This field drived sd_rst_n_oe output of SDXC +Values: +0x1 (ENABLE): sd_rst_n_oe is 1 +0x0 (DISABLE): sd_rst_n_oe is 0 + 3 + 1 + read-write + + + EMMC_RST_N + EMMC Device Reset signal control. +This register field controls the sd_rst_n output of SDXC +Values: +0x1 (RST_DEASSERT): Reset to eMMC device is deasserted +0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) + 2 + 1 + read-write + + + DISABLE_DATA_CRC_CHK + Disable Data CRC Check +This bit controls masking of CRC16 error for Card Write in eMMC mode. +This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, +which may generate CRC error. This CRC error can be masked using this bit during bus testing. +Values: +0x1 (DISABLE): DATA CRC check is disabled +0x0 (ENABLE): DATA CRC check is enabled + 1 + 1 + read-write + + + CARD_IS_EMMC + eMMC Card present +This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. +Values: +0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card +0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card + 0 + 1 + read-write + + + + + AUTO_TUNING_CTRL + No description avaiable + 0x540 + 32 + 0x00000000 + 0x7F1F0F1F + + + SWIN_TH_VAL + Sampling window threshold value setting +The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps +can use values from 0x0 to 0x1F. +This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' +0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. +0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. +0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. +........ +0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. + 24 + 7 + read-write + + + POST_CHANGE_DLY + Time taken for phase switching and stable clock output. +Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 19 + 2 + read-write + + + PRE_CHANGE_DLY + Maximum Latency specification between cclk_tx and cclk_rx. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 17 + 2 + read-write + + + TUNE_CLK_STOP_EN + Clock stopping control for Tuning and auto-tuning circuit. +When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. +This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. + Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. +Values: +0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change +0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching + 16 + 1 + read-write + + + WIN_EDGE_SEL + This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. +0x0: User selection disabled. Tuning calculated edges are used. +0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. +0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess +... +0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. + 8 + 4 + read-write + + + SW_TUNE_EN + This fields enables software-managed tuning flow. +Values: +0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable. +0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled + 4 + 1 + read-write + + + RPT_TUNE_ERR + Framing errors are not generated when executing tuning. +This debug bit allows users to report these errors. +Values: +0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors +0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. + 3 + 1 + read-write + + + SWIN_TH_EN + Sampling window Threshold enable +Selects the tuning mode +Field should be programmed only when SAMPLE_CLK_SEL is '0' +Values: +0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold +set by SWIN_TH_VAL field +0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window + 2 + 1 + read-write + + + CI_SEL + Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. +Values: +0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval +0x1 (WHEN_IN_IDLE): Driven at the end of the transfer + 1 + 1 + read-write + + + AT_EN + Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. +Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. +This field should be programmed only when CLK_CTRL_R.SD_CLK_EN is 0. +Values: +0x1 (AT_ENABLE): AutoTuning is enabled +0x0 (AT_DISABLE): AutoTuning is disabled + 0 + 1 + read-write + + + + + AUTO_TUNING_STAT + No description avaiable + 0x544 + 32 + 0x00000000 + 0x00FFFFFF + + + L_EDGE_PH_CODE + Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. + 16 + 8 + read-only + + + R_EDGE_PH_CODE + Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. + 8 + 8 + read-only + + + CENTER_PH_CODE + Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel + 0 + 8 + read-write + + + + + MISC_CTRL0 + No description avaiable + 0x3000 + 32 + 0x00000000 + 0xD0021FFF + + + IRQ_EN + No description avaiable + 30 + 2 + read-write + + + CARDCLK_INV_EN + No description avaiable + 28 + 1 + read-write + + + PAD_CLK_SEL_B + No description avaiable + 17 + 1 + read-write + + + CARDCLK_EN_SW + No description avaiable + 12 + 1 + read-write + + + FREQ_SEL_SW_EN + No description avaiable + 11 + 1 + read-write + + + TMCLK_EN + No description avaiable + 10 + 1 + read-write + + + FREQ_SEL_SW + No description avaiable + 0 + 10 + read-write + + + + + MISC_CTRL1 + No description avaiable + 0x3004 + 32 + 0x00000000 + 0xB0000000 + + + CARD_ACTIVE + No description avaiable + 31 + 1 + read-write + + + CARD_ACTIVE_PERIOD_SEL + No description avaiable + 28 + 2 + read-write + + + + + + + I2C0 + I2C0 + I2C + 0xf3020000 + + 0x4 + 0x30 + registers + + + + CFG + Configuration Register + 0x10 + 32 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 2 + 30 + read-write + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + INTEN + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 10 + 22 + read-write + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + STATUS + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 15 + 17 + read-write + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + read-write + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + read-write + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + read-write + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + read-write + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + read-write + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + read-write + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + read-write + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + ADDR + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 10 + 22 + read-write + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + DATA + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 8 + 24 + read-write + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + CTRL + Control Register + 0x24 + 32 + 0x00001E00 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 13 + 19 + read-write + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means 256 bytes. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + CMD + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 3 + 29 + read-write + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + SETUP + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 29 + 3 + read-write + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + RESERVED + No description avaiable + 14 + 2 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 5 + 27 + read-write + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf3024000 + + + I2C2 + I2C2 + I2C + 0xf3028000 + + + I2C3 + I2C3 + I2C + 0xf302c000 + + + SDP + SDP + SDP + 0xf304c000 + + 0x0 + 0x60 + registers + + + + SDPCR + SDP control register + 0x0 + 32 + 0x30000000 + 0xFFFE0101 + + + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. + 31 + 1 + read-write + + + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + 30 + 1 + read-write + + + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 + 1 + read-only + + + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 + 1 + read-only + + + RESERVED + Not used + 24 + 4 + read-only + + + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 + 1 + read-write + + + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 + 1 + read-write + + + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 + read-write + + + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 + 1 + read-write + + + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 + 1 + read-write + + + RESERVED + Reserved + 18 + 1 + read-write + + + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 + 1 + read-write + + + RDSCEN + when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) +when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + 8 + 1 + read-write + + + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. + 0 + 1 + read-write + + + + + MODCTRL + Mod control register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +Others, reserved. + 28 + 4 + read-write + + + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write + + + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 + read-write + + + RESERVED + Not used + 17 + 1 + read-only + + + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 + 1 + read-write + + + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 + read-write + + + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 + 1 + read-write + + + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 + 1 + read-write + + + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 + read-write + + + RESERVED + Not used + 8 + 1 + read-only + + + RESERVED + Not used + 6 + 2 + read-only + + + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format + 0 + 2 + read-write + + + + + PKTCNT + packet counter registers. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 31 + 1 + read-write + + + RESERVED + Not used + 30 + 1 + read-write + + + RESERVED + Not used + 24 + 6 + read-only + + + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 + read-only + + + RESERVED + Not used + 8 + 8 + read-only + + + CNTINCR + The value written to this field is added to the spacket count. + 0 + 8 + read-write + + + + + STA + Status Registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TAG + packet tag. + 24 + 8 + read-only + + + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 + 1 + read-write + + + RESERVED + Not used + 21 + 2 + read-only + + + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + read-write + + + AESBSY + AES Busy + 19 + 1 + read-only + + + HASBSY + Hashing Busy + 18 + 1 + read-only + + + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + read-write + + + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 + 1 + read-write + + + RESERVED + Not used + 6 + 10 + read-only + + + ERRSET + Working mode setup error. + 5 + 1 + read-write + + + ERRPKT + Packet head access error, or status update error. + 4 + 1 + read-write + + + ERRSRC + Source Buffer Access Error + 3 + 1 + read-write + + + ERRDST + Destination Buffer Error + 2 + 1 + read-write + + + ERRHAS + Hashing Check Error + 1 + 1 + read-write + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + 0 + 1 + read-write + + + + + KEYADDR + Key Address + 0x10 + 32 + 0x00000040 + 0xFFFFFFFF + + + RESERVED + Not used + 24 + 8 + read-only + + + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + RESERVED + Not used + 2 + 14 + read-only + + + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. + 0 + 2 + read-write + + + + + KEYDAT + Key Data + 0x14 + 32 + 0x00000030 + 0xFFFFFFFF + + + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV0 + Cipher Initializtion Vector 0 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV1 + Cipher Initializtion Vector 1 + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV2 + Cipher Initializtion Vector 2 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV3 + Cipher Initializtion Vector 3 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + HASWRD_HASWRD0 + Hash Data Word 0 + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD1 + Hash Data Word 1 + 0x2c + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD2 + Hash Data Word 2 + 0x30 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD3 + Hash Data Word 3 + 0x34 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD4 + Hash Data Word 4 + 0x38 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD5 + Hash Data Word 5 + 0x3c + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD6 + Hash Data Word 6 + 0x40 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD7 + Hash Data Word 7 + 0x44 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + CMDPTR + Command Pointer + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) + 0 + 32 + read-write + + + + + NPKTPTR + Next Packet Address Pointer + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + NPKTPTR + Next Packet Address Pointer + 0 + 32 + read-write + + + + + PKTCTL + Packet Control Registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTTAG + packet tag + 24 + 8 + read-write + + + RESERVED + Not used + 7 + 17 + read-write + + + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 + read-write + + + HASFNL + Hash Termination packet + 5 + 1 + read-write + + + HASINI + Hash Initialization packat + 4 + 1 + read-write + + + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 + read-write + + + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 + 1 + read-write + + + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 + 1 + read-write + + + RESERVED + Not used + 0 + 1 + read-write + + + + + PKTSRC + Packet Memory Source Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTSRC + Packet Memory Source Address + 0 + 32 + read-write + + + + + PKTDST + Packet Memory Destination Address + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTDST + Packet Memory Destination Address + 0 + 32 + read-write + + + + + PKTBUF + Packet buffer size. + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTBUF + No description avaiable + 0 + 32 + read-write + + + + + + + DRAM + DRAM + DRAM + 0xf3050000 + + 0x0 + 0x154 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x1FFF0007 + + + BTO + Bus timeout cycles +AXI Bus timeout cycle is as following (255*(2^BTO)): +00000b - 255*1 +00001-11110b - 255*2 - 255*2^30 +11111b - 255*2^31 + 24 + 5 + read-write + + + CTO + Command Execution timeout cycles +When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is +generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is +CTO*1024 cycle. + 16 + 8 + read-write + + + DQS + DQS (read strobe) mode +0b - Dummy read strobe loopbacked internally +1b - Dummy read strobe loopbacked from DQS pad + 2 + 1 + read-write + + + DIS + Module Disable +0b - Module enabled +1b - Module disabled + 1 + 1 + read-write + + + RST + Software Reset +Reset all internal logic in SEMC except configuration register + 0 + 1 + read-write + + + + + BMW0 + Bus (AXI) Weight Control Register 0 + 0x8 + 32 + 0x00000000 + 0x00FFFFFF + + + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 + read-write + + + SH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write + + + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + + + BMW1 + Bus (AXI) Weight Control Register 1 + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + BR + Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current +executing command. + 24 + 8 + read-write + + + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 + read-write + + + PH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write + + + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + + + BR_BASE0 + Base Register 0 (for SDRAM CS0 device) + 0x10 + 32 + 0x00000000 + 0xFFFFF03F + + + BASE + Base Address +This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low +position 12 bits are all zero. + 12 + 20 + read-write + + + SIZE + Memory size +00000b - 4KB +00001b - 8KB +00010b - 16KB +00011b - 32KB +00100b - 64KB +00101b - 128KB +00110b - 256KB +00111b - 512KB +01000b - 1MB +01001b - 2MB +01010b - 4MB +01011b - 8MB +01100b - 16MB +01101b - 32MB +01110b - 64MB +01111b - 128MB +10000b - 256MB +10001b - 512MB +10010b - 1GB +10011b - 2GB +10100-11111b - 4GB + 1 + 5 + read-write + + + VLD + Valid + 0 + 1 + read-write + + + + + BR_BASE1 + Base Register 1 (for SDRAM CS1 device) + 0x14 + 32 + 0x00000000 + 0xFFFFF03F + + + BASE + Base Address +This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low +position 12 bits are all zero. + 12 + 20 + read-write + + + SIZE + Memory size +00000b - 4KB +00001b - 8KB +00010b - 16KB +00011b - 32KB +00100b - 64KB +00101b - 128KB +00110b - 256KB +00111b - 512KB +01000b - 1MB +01001b - 2MB +01010b - 4MB +01011b - 8MB +01100b - 16MB +01101b - 32MB +01110b - 64MB +01111b - 128MB +10000b - 256MB +10001b - 512MB +10010b - 1GB +10011b - 2GB +10100-11111b - 4GB + 1 + 5 + read-write + + + VLD + Valid + 0 + 1 + read-write + + + + + INTEN + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000000F + + + AXIBUSERR + AXI BUS error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 3 + 1 + read-write + + + AXICMDERR + AXI command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 2 + 1 + read-write + + + IPCMDERR + IP command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 1 + 1 + read-write + + + IPCMDDONE + IP command done interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 0 + 1 + read-write + + + + + INTR + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000000F + + + AXIBUSERR + AXI bus error interrupt +AXI Bus error interrupt is generated in following cases: +• AXI address is invalid +• AXI 8-bit or 16-bit WRAP write/read + 3 + 1 + read-write + + + AXICMDERR + AXI command error interrupt +AXI command error interrupt is generated when AXI command execution timeout. + 2 + 1 + read-write + + + IPCMDERR + IP command error done interrupt +IP command error interrupt is generated in following case: +• IP Command Address target invalid device space +• IP Command Code unsupported +• IP Command triggered when previous command + 1 + 1 + read-write + + + IPCMDDONE + IP command normal done interrupt + 0 + 1 + read-write + + + + + SDRCTRL0 + SDRAM Control Register 0 + 0x40 + 32 + 0x00000000 + 0x00004FFB + + + BANK2 + 2 Bank selection bit +0b - SDRAM device has 4 banks. +1b - SDRAM device has 2 banks. + 14 + 1 + read-write + + + CAS + CAS Latency +00b - 1 +01b - 1 +10b - 2 +11b - 3 + 10 + 2 + read-write + + + COL + Column address bit number +00b - 12 bit +01b - 11 bit +10b - 10 bit +11b - 9 bit + 8 + 2 + read-write + + + COL8 + Column 8 selection bit +0b - Column address bit number is decided by COL field. +1b - Column address bit number is 8. COL field is ignored. + 7 + 1 + read-write + + + BURSTLEN + Burst Length +000b - 1 +001b - 2 +010b - 4 +011b - 8 +100b - 8 +101b - 8 +110b - 8 +111b - 8 + 4 + 3 + read-write + + + HIGHBAND + high band select +0: use data[15:0] for 16bit SDRAM; +1: use data[31:16] for 16bit SDRAM; +only used when Port Size is 16bit(PORTSZ=01b) + 3 + 1 + read-write + + + PORTSZ + Port Size +00b - 8bit +01b - 16bit +10b - 32bit + 0 + 2 + read-write + + + + + SDRCTRL1 + SDRAM Control Register 1 + 0x44 + 32 + 0x00000000 + 0x00FFFFFF + + + ACT2PRE + ACT to Precharge minimum time +It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. + 20 + 4 + read-write + + + CKEOFF + CKE OFF minimum time +It is promised clock suspend last at leat CKEOFF+1 clock cycles. + 16 + 4 + read-write + + + WRC + Write recovery time +It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. + 13 + 3 + read-write + + + RFRC + Refresh recovery time +It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. + 8 + 5 + read-write + + + ACT2RW + ACT to Read/Write wait time +It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. + 4 + 4 + read-write + + + PRE2ACT + PRECHARGE to ACT/Refresh wait time +It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. + 0 + 4 + read-write + + + + + SDRCTRL2 + SDRAM Control Register 2 + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + ITO + SDRAM Idle timeout +It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is +considered idle when there is no AXI Bus transfer and no SDRAM command pending. +00000000b - IDLE timeout period is 256*Prescale period. +00000001-11111111b - IDLE timeout period is ITO*Prescale period. + 24 + 8 + read-write + + + ACT2ACT + ACT to ACT wait time +It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This +could help to meet tRRD timing requirement by SDRAM device. + 16 + 8 + read-write + + + REF2REF + Refresh to Refresh wait time +It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. +This could help to meet tRFC timing requirement by SDRAM device. + 8 + 8 + read-write + + + SRRC + Self Refresh Recovery time +It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. + 0 + 8 + read-write + + + + + SDRCTRL3 + SDRAM Control Register 3 + 0x4c + 32 + 0x00000000 + 0xFFFFFF0F + + + UT + Refresh urgent threshold +Internal refresh request is generated on every Refresh period. Before internal request timer count up to +urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh +request is handled in lower priority than any pending AXI command or IP command to SDRAM device. +When internal request timer count up to this urgent threshold, refresh request is considered as urgent +refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP +command to SDRAM device. +NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as +urgent refresh request. +Refresh urgent threshold is as follwoing: +00000000b - 256*Prescaler period +00000001-11111111b - UT*Prescaler period + 24 + 8 + read-write + + + RT + Refresh timer period +Refresh timer period is as following: +00000000b - 256*Prescaler period +00000001-11111111b - RT*Prescaler period + 16 + 8 + read-write + + + PRESCALE + Prescaler timer period +Prescaler timer period is as following: +00000000b - 256*16 clock cycles +00000001-11111111b - PRESCALE*16 clock cycles + 8 + 8 + read-write + + + REBL + Refresh burst length +It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The +number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. +000b - 1 +001b - 2 +010b - 3 +011b - 4 +100b - 5 +101b - 6 +110b - 7 +111b - 8 + 1 + 3 + read-write + + + REN + Refresh enable + 0 + 1 + read-write + + + + + SADDR + IP Command Control Register 0 + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + SA + Slave address + 0 + 32 + read-write + + + + + DATSZ + IP Command Control Register 1 + 0x94 + 32 + 0x00000000 + 0x00000007 + + + DATSZ + Data Size in Byte +When IP command is not a write/read operation, DATSZ field would be ignored. +000b - 4 +001b - 1 +010b - 2 +011b - 3 +100b - 4 +101b - 4 +110b - 4 +111b - 4 + 0 + 3 + read-write + + + + + BYTEMSK + IP Command Control Register 2 + 0x98 + 32 + 0x00000000 + 0x0000000F + + + BM3 + Byte Mask for Byte 3 (IPTXD bit 31:24) +0b - Byte Unmasked +1b - Byte Masked + 3 + 1 + read-write + + + BM2 + Byte Mask for Byte 2 (IPTXD bit 23:16) +0b - Byte Unmasked +1b - Byte Masked + 2 + 1 + read-write + + + BM1 + Byte Mask for Byte 1 (IPTXD bit 15:8) +0b - Byte Unmasked +1b - Byte Masked + 1 + 1 + read-write + + + BM0 + Byte Mask for Byte 0 (IPTXD bit 7:0) +0b - Byte Unmasked +1b - Byte Masked + 0 + 1 + read-write + + + + + IPCMD + IP Command Register + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory +device is selected by BRx settings and IPCR0 registers. + 16 + 16 + write-only + + + CMD + SDRAM Commands: +• 0x8: READ +• 0x9: WRITE +• 0xA: MODESET +• 0xB: ACTIVE +• 0xC: AUTO REFRESH +• 0xD: SELF REFRESH +• 0xE: PRECHARGE +• 0xF: PRECHARGE ALL +• Others: RSVD +NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. + 0 + 16 + read-write + + + + + IPTX + TX DATA Register + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + Data + 0 + 32 + read-write + + + + + IPRX + RX DATA Register + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + Data + 0 + 32 + read-write + + + + + STAT0 + Status Register 0 + 0xc0 + 32 + 0x00000000 + 0x00000001 + + + IDLE + Indicating whether it is in IDLE state. +When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no +pending device access. + 0 + 1 + read-only + + + + + DLYCFG + Delay Line Config Register + 0x150 + 32 + 0x00000000 + 0x0000203F + + + OE + delay clock output enable, should be set after setting DLYEN and DLYSEL + 13 + 1 + read-write + + + DLYSEL + delay line select, 0 for 1 cell, 31 for all 32 cells + 1 + 5 + read-write + + + DLYEN + delay line enable + 0 + 1 + read-write + + + + + + + FFA + FFA + FFA + 0xf3058000 + + 0x0 + 0x48 + registers + + + + CTRL + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFFFFFE01 + + + SFTRST + software reset the module if asserted to be 1. +EN is only active after this bit is zero. + 31 + 1 + read-write + + + RSV + Reserved + 9 + 22 + read-write + + + EN + Asserted to enable the module + 0 + 1 + read-write + + + + + STATUS + No description avaiable + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 8 + 24 + read-only + + + FIR_OV + FIR Overflow err + 7 + 1 + read-only + + + FFT_OV + FFT Overflow Err + 6 + 1 + read-only + + + WR_ERR + AXI Data Write Error + 5 + 1 + read-only + + + RD_NXT_ERR + AXI Read Bus Error for NXT DATA + 4 + 1 + read-only + + + RD_ERR + AXI Data Read Error + 3 + 1 + read-only + + + RSV + Reserved + 2 + 1 + read-only + + + NXT_CMD_RD_DONE + Indicate that next command sequence is already read into the module. + 1 + 1 + read-only + + + OP_CMD_DONE + Indicate that operation cmd is done, and data are available in system memory. + 0 + 1 + read-only + + + + + INT_EN + No description avaiable + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WRSV1 + Reserved + 8 + 24 + read-write + + + FIR_OV + FIR Overflow err + 7 + 1 + read-write + + + FFT_OV + FFT Overflow Err + 6 + 1 + read-write + + + WR_ERR + Enable Data Write Error interrupt + 5 + 1 + read-write + + + RD_NXT_ERR + Enable Read Bus Error for NXT DATA interrupt + 4 + 1 + read-write + + + RD_ERR + Enable Data Read Error interrupt + 3 + 1 + read-write + + + RSV + Write as zero + 2 + 1 + read-write + + + NXT_CMD_RD_DONE + Indicate that next command sequence is already read into the module. + 1 + 1 + read-write + + + OP_CMD_DONE + Indicate that operation cmd is done, and data are available in system memory. + 0 + 1 + read-write + + + + + OP_CTRL + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + NXT_ADDR + The address for the next command. +It will be processed after CUR_CMD is executed and done.. + 2 + 30 + read-write + + + NXT_EN + Whether NXT_CMD is enabled. +Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. + 1 + 1 + read-write + + + EN + Whether CUR_CMD is enabled. +Asserted to enable the CUR_CMD + 0 + 1 + read-write + + + + + OP_CMD + No description avaiable + 0x24 + 32 + 0x00000000 + 0x01FFFEFF + + + CONJ_C + asserted to have conjuate value for coefs in computation + 24 + 1 + read-write + + + CMD + The Command Used: +0: FIR +2: FFT +Others: Reserved + 18 + 6 + read-write + + + OUTD_TYPE + Output data type: +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 + 15 + 3 + read-write + + + COEF_TYPE + Coef data type (used for FIR): +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 + 12 + 3 + read-write + + + IND_TYPE + Input data type: +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 + 9 + 3 + read-write + + + NXT_CMD_LEN + The length of nxt commands in 32-bit words + 0 + 8 + read-write + + + + + OP_REG0 + No description avaiable + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_MISC + No description avaiable + 0x28 + 32 + 0x00000000 + 0x00003FFF + + + FIR_COEF_TAPS + Length of FIR coefs + 0 + 14 + read-write + + + + + OP_FFT_MISC + No description avaiable + 0x28 + 32 + 0x00000000 + 0x000007FF + + + FFT_LEN + FFT length +0:8, +..., +n:2^(3+n) + 7 + 4 + read-write + + + IFFT + Asserted to indicate IFFT + 6 + 1 + read-write + + + RSV + Reserved. Should be written as zero + 4 + 2 + read-write + + + TMP_BLK + Memory block for indata. Should be assigned as 1 + 2 + 2 + read-write + + + IND_BLK + Memory block for indata. Should be assigned as 0 + 0 + 2 + read-write + + + + + OP_REG1 + No description avaiable + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_MISC1 + No description avaiable + 0x2c + 32 + 0x00000000 + 0x003FFFFF + + + OUTD_MEM_BLK + Should be assigned as 0 + 20 + 2 + read-write + + + COEF_MEM_BLK + Should be assigned as 1 + 18 + 2 + read-write + + + IND_MEM_BLK + Should be assigned as 2 + 16 + 2 + read-write + + + FIR_DATA_TAPS + The input data data length + 0 + 16 + read-write + + + + + OP_REG2 + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FFT_INRBUF + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The input (real) data buffer pointer + 0 + 32 + read-write + + + + + OP_REG3 + No description avaiable + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_INBUF + No description avaiable + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The input data buffer pointer + 0 + 32 + read-write + + + + + OP_REG4 + No description avaiable + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_COEFBUF + No description avaiable + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The coef buf pointer + 0 + 32 + read-write + + + + + OP_FFT_OUTRBUF + No description avaiable + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The output (real) data buffer pointer + 0 + 32 + read-write + + + + + OP_REG5 + No description avaiable + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_FIR_OUTBUF + No description avaiable + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOC + The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） + 0 + 32 + read-write + + + + + OP_REG6 + No description avaiable + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + OP_REG7 + No description avaiable + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CT + Contents + 0 + 32 + read-write + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x2ffc + registers + + + + RESOURCE_CPU0 + Resource control register for cpu0_core + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CPX0 + Resource control register for cpu0_subsys + 0x4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_POW_CPU0 + Resource control register for pow_cpu0 + 0x54 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_SOC + Resource control register for rst_soc + 0x58 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_CPU0 + Resource control register for rst_cpu0 + 0x5c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_XTAL + Resource control register for xtal + 0x80 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL0 + Resource control register for pll0 + 0x84 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK0_PLL0 + Resource control register for clk0_pll0 + 0x88 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK1_PLL0 + Resource control register for clk1_pll0 + 0x8c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK2_PLL0 + Resource control register for clk2_pll0 + 0x90 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL1 + Resource control register for pll1 + 0x94 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK0_PLL1 + Resource control register for clk0_pll1 + 0x98 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK1_PLL1 + Resource control register for clk1_pll1 + 0x9c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL2 + Resource control register for pll2 + 0xa0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK0_PLL2 + Resource control register for clk0_pll2 + 0xa4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK1_PLL2 + Resource control register for clk1_pll2 + 0xa8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL0_REF + Resource control register for pll0 ref clock + 0xac + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL1_REF + Resource control register for pll1 ref clock + 0xb0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL2_REF + Resource control register for pll2 ref clock + 0xb4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CPU0 + Resource control register for clk_top_cpu0 + 0x100 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_MCT0 + Resource control register for clk_top_mct0 + 0x104 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_DRAM + Resource control register for clk_top_dram + 0x108 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_XPI0 + Resource control register for clk_top_xpi0 + 0x10c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_XPI1 + Resource control register for clk_top_xpi1 + 0x110 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_TMR0 + Resource control register for clk_top_tmr0 + 0x114 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_TMR1 + Resource control register for clk_top_tmr1 + 0x118 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_TMR2 + Resource control register for clk_top_tmr2 + 0x11c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_TMR3 + Resource control register for clk_top_tmr3 + 0x120 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT0 + Resource control register for clk_top_urt0 + 0x124 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT1 + Resource control register for clk_top_urt1 + 0x128 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT2 + Resource control register for clk_top_urt2 + 0x12c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT3 + Resource control register for clk_top_urt3 + 0x130 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT4 + Resource control register for clk_top_urt4 + 0x134 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT5 + Resource control register for clk_top_urt5 + 0x138 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT6 + Resource control register for clk_top_urt6 + 0x13c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT7 + Resource control register for clk_top_urt7 + 0x140 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C0 + Resource control register for clk_top_i2c0 + 0x144 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C1 + Resource control register for clk_top_i2c1 + 0x148 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C2 + Resource control register for clk_top_i2c2 + 0x14c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C3 + Resource control register for clk_top_i2c3 + 0x150 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI0 + Resource control register for clk_top_spi0 + 0x154 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI1 + Resource control register for clk_top_spi1 + 0x158 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI2 + Resource control register for clk_top_spi2 + 0x15c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI3 + Resource control register for clk_top_spi3 + 0x160 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN0 + Resource control register for clk_top_can0 + 0x164 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN1 + Resource control register for clk_top_can1 + 0x168 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_PTPC + Resource control register for clk_top_ptpc + 0x16c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA0 + Resource control register for clk_top_ana0 + 0x170 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA1 + Resource control register for clk_top_ana1 + 0x174 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA2 + Resource control register for clk_top_ana2 + 0x178 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA3 + Resource control register for clk_top_ana3 + 0x17c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_AUD0 + Resource control register for clk_top_aud0 + 0x180 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_AUD1 + Resource control register for clk_top_aud1 + 0x184 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ETH0 + Resource control register for clk_top_eth0 + 0x188 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_PTP0 + Resource control register for clk_top_ptp0 + 0x18c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_REF0 + Resource control register for clk_top_ref0 + 0x190 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_REF1 + Resource control register for clk_top_ref1 + 0x194 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_NTM0 + Resource control register for clk_top_ntm0 + 0x198 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SDC0 + Resource control register for clk_top_sdc0 + 0x19c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC0 + Resource control register for clk_top_adc0 + 0x200 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC1 + Resource control register for clk_top_adc1 + 0x204 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC2 + Resource control register for clk_top_adc2 + 0x208 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_DAC0 + Resource control register for clk_top_dac0 + 0x20c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2S0 + Resource control register for clk_top_i2s0 + 0x210 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2S1 + Resource control register for clk_top_i2s1 + 0x214 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AHBP + Resource control register for ahbapb_bus + 0x400 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AXIS + Resource control register for soc_bus + 0x404 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AXIC + Resource control register for conn_bus + 0x408 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_DRAM + Resource control register for dram + 0x40c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ROM0 + Resource control register for rom + 0x410 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LMM0 + Resource control register for lmm0 + 0x414 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RAM0 + Resource control register for axi_sram + 0x418 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MCT0 + Resource control register for mchtmr0 + 0x41c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_XPI0 + Resource control register for xpi0 + 0x420 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_XPI1 + Resource control register for xpi1 + 0x424 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SDP0 + Resource control register for sdp + 0x428 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RNG0 + Resource control register for rng + 0x42c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_KMAN + Resource control register for keym + 0x430 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_DMA0 + Resource control register for hdma + 0x434 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_DMA1 + Resource control register for xdma + 0x438 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_FFA0 + Resource control register for ffa + 0x43c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPIO + Resource control register for gpio + 0x440 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MBX0 + Resource control register for mbx + 0x444 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_WDG0 + Resource control register for wdg0 + 0x448 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_WDG1 + Resource control register for wdg1 + 0x44c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TSNS + Resource control register for tsns + 0x450 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TMR0 + Resource control register for tmr0 + 0x454 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TMR1 + Resource control register for tmr1 + 0x458 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TMR2 + Resource control register for tmr2 + 0x45c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TMR3 + Resource control register for tmr3 + 0x460 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT0 + Resource control register for uart0 + 0x464 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT1 + Resource control register for uart1 + 0x468 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT2 + Resource control register for uart2 + 0x46c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT3 + Resource control register for uart3 + 0x470 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT4 + Resource control register for uart4 + 0x474 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT5 + Resource control register for uart5 + 0x478 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT6 + Resource control register for uart6 + 0x47c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT7 + Resource control register for uart7 + 0x480 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C0 + Resource control register for i2c0 + 0x484 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C1 + Resource control register for i2c1 + 0x488 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C2 + Resource control register for i2c2 + 0x48c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C3 + Resource control register for i2c3 + 0x490 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI0 + Resource control register for spi0 + 0x494 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI1 + Resource control register for spi1 + 0x498 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI2 + Resource control register for spi2 + 0x49c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI3 + Resource control register for spi3 + 0x4a0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN0 + Resource control register for can0 + 0x4a4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN1 + Resource control register for can1 + 0x4a8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_PTPC + Resource control register for ptpc + 0x4ac + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC0 + Resource control register for adc0 + 0x4b0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC1 + Resource control register for adc1 + 0x4b4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC2 + Resource control register for adc2 + 0x4b8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_DAC0 + Resource control register for dac + 0x4bc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ACMP + Resource control register for acmp + 0x4c0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2S0 + Resource control register for i2s0 + 0x4c4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2S1 + Resource control register for i2s1 + 0x4c8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_PDM0 + Resource control register for pdm + 0x4cc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_DAO + Resource control register for dao + 0x4d0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MSYN + Resource control register for msyn + 0x4d4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT0 + Resource control register for mot0 + 0x4d8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT1 + Resource control register for mot1 + 0x4dc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ETH0 + Resource control register for enet + 0x4e0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_NTM0 + Resource control register for ntmr + 0x4e4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SDC0 + Resource control register for sdxc + 0x4e8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_USB0 + Resource control register for usb + 0x4ec + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_REF0 + Resource control register for ref0 + 0x4f0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_REF1 + Resource control register for ref1 + 0x4f4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + GROUP0_LINK0_VALUE + Group setting + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK0_SET + Group setting + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK0_CLEAR + Group setting + 0x808 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + GROUP0_LINK0_TOGGLE + Group setting + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + GROUP0_LINK1_VALUE + Group setting + 0x810 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK1_SET + Group setting + 0x814 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK1_CLEAR + Group setting + 0x818 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + GROUP0_LINK1_TOGGLE + Group setting + 0x81c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + AFFILIATE_CPU0_VALUE + Affiliate of Group + 0x900 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU0_SET + Affiliate of Group + 0x904 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 + read-write + + + + + AFFILIATE_CPU0_CLEAR + Affiliate of Group + 0x908 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 + read-write + + + + + AFFILIATE_CPU0_TOGGLE + Affiliate of Group + 0x90c + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 + read-write + + + + + RETENTION_CPU0_VALUE + Retention Contol + 0x920 + 32 + 0x00000000 + 0x000000FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu stop, +bit01: soc_ctx is kept on while cpu stop, +bit02: cpu0_mem is kept on while cpu stop, +bit03: cpu0_ctx is kept on while cpu stop, +bit04: xtal_hold is kept on while cpu stop, +bit05: pll0_hold is kept on while cpu stop, +bit06: pll1_hold is kept on while cpu stop, +bit07: pll2_hold is kept on while cpu stop, + 0 + 8 + read-write + + + + + RETENTION_CPU0_SET + Retention Contol + 0x924 + 32 + 0x00000000 + 0x000000FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 8 + read-write + + + + + RETENTION_CPU0_CLEAR + Retention Contol + 0x928 + 32 + 0x00000000 + 0x000000FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 8 + read-write + + + + + RETENTION_CPU0_TOGGLE + Retention Contol + 0x92c + 32 + 0x00000000 + 0x000000FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before + 0 + 8 + read-write + + + + + POWER_CPU0_STATUS + Power Setting + 0x1000 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + POWER_CPU0_LF_WAIT + Power Setting + 0x1004 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_CPU0_OFF_WAIT + Power Setting + 0x100c + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + RESET_SOC_CONTROL + Reset Setting + 0x1400 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_SOC_CONFIG + Reset Setting + 0x1404 + 32 + 0x00643203 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_SOC_COUNTER + Reset Setting + 0x140c + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + RESET_CPU0_CONTROL + Reset Setting + 0x1410 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_CPU0_CONFIG + Reset Setting + 0x1414 + 32 + 0x00643203 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_CPU0_COUNTER + Reset Setting + 0x141c + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + CLOCK_CPU_CLK_TOP_CPU0 + Clock setting + 0x1800 + 32 + 0x00000000 + 0xD0FF0FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + SUB1_DIV + ahb bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 20 + 4 + read-write + + + SUB0_DIV + axi bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 16 + 4 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_MCT0 + Clock setting + 0x1804 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_DRAM + Clock setting + 0x1808 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_XPI0 + Clock setting + 0x180c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_XPI1 + Clock setting + 0x1810 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_TMR0 + Clock setting + 0x1814 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_TMR1 + Clock setting + 0x1818 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_TMR2 + Clock setting + 0x181c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_TMR3 + Clock setting + 0x1820 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT0 + Clock setting + 0x1824 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT1 + Clock setting + 0x1828 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT2 + Clock setting + 0x182c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT3 + Clock setting + 0x1830 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT4 + Clock setting + 0x1834 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT5 + Clock setting + 0x1838 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT6 + Clock setting + 0x183c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT7 + Clock setting + 0x1840 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C0 + Clock setting + 0x1844 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C1 + Clock setting + 0x1848 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C2 + Clock setting + 0x184c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C3 + Clock setting + 0x1850 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI0 + Clock setting + 0x1854 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI1 + Clock setting + 0x1858 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI2 + Clock setting + 0x185c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI3 + Clock setting + 0x1860 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN0 + Clock setting + 0x1864 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN1 + Clock setting + 0x1868 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_PTPC + Clock setting + 0x186c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA0 + Clock setting + 0x1870 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA1 + Clock setting + 0x1874 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA2 + Clock setting + 0x1878 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA3 + Clock setting + 0x187c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_AUD0 + Clock setting + 0x1880 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_AUD1 + Clock setting + 0x1884 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ETH0 + Clock setting + 0x1888 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_PTP0 + Clock setting + 0x188c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_REF0 + Clock setting + 0x1890 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_REF1 + Clock setting + 0x1894 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_NTM0 + Clock setting + 0x1898 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SDC0 + Clock setting + 0x189c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + ADCCLK_CLK_TOP_ADC0 + Clock setting + 0x1c00 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + ADCCLK_CLK_TOP_ADC1 + Clock setting + 0x1c04 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + ADCCLK_CLK_TOP_ADC2 + Clock setting + 0x1c08 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + DACCLK_CLK_TOP_DAC0 + Clock setting + 0x1c0c + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + I2SCLK_CLK_TOP_I2S0 + Clock setting + 0x1c10 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: aud clock 0 +1: aud clock 1 + 8 + 1 + read-write + + + + + I2SCLK_CLK_TOP_I2S1 + Clock setting + 0x1c14 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: aud clock 0 +1: aud clock 1 + 8 + 1 + read-write + + + + + GLOBAL00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + MUX + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 + 0 + 4 + read-write + + + + + MONITOR_SLICE0_CONTROL + Clock measure and monitor control + 0x2400 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + MONITOR_SLICE0_CURRENT + Clock measure result + 0x2404 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE0_LOW_LIMIT + Clock lower limit + 0x2408 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE0_HIGH_LIMIT + Clock upper limit + 0x240c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE1_CONTROL + Clock measure and monitor control + 0x2420 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + MONITOR_SLICE1_CURRENT + Clock measure result + 0x2424 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE1_LOW_LIMIT + Clock lower limit + 0x2428 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE1_HIGH_LIMIT + Clock upper limit + 0x242c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE2_CONTROL + Clock measure and monitor control + 0x2440 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + MONITOR_SLICE2_CURRENT + Clock measure result + 0x2444 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE2_LOW_LIMIT + Clock lower limit + 0x2448 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE2_HIGH_LIMIT + Clock upper limit + 0x244c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE3_CONTROL + Clock measure and monitor control + 0x2460 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + MONITOR_SLICE3_CURRENT + Clock measure result + 0x2464 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE3_LOW_LIMIT + Clock lower limit + 0x2468 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE3_HIGH_LIMIT + Clock upper limit + 0x246c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + CPU_CPU0_LP + CPU0 LP control + 0x2800 + 32 + 0x00001000 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + CPU_CPU0_LOCK + CPU0 Lock GPR + 0x2804 + 32 + 0x00000002 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + CPU_CPU0_GPR0 + CPU0 GPR0 + 0x2808 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR1 + CPU0 GPR1 + 0x280c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR2 + CPU0 GPR2 + 0x2810 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR3 + CPU0 GPR3 + 0x2814 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR4 + CPU0 GPR4 + 0x2818 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR5 + CPU0 GPR5 + 0x281c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR6 + CPU0 GPR6 + 0x2820 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR7 + CPU0 GPR7 + 0x2824 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR8 + CPU0 GPR8 + 0x2828 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR9 + CPU0 GPR9 + 0x282c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR10 + CPU0 GPR10 + 0x2830 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR11 + CPU0 GPR11 + 0x2834 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR12 + CPU0 GPR12 + 0x2838 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR13 + CPU0 GPR13 + 0x283c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_STATUS0 + CPU0 wakeup IRQ status + 0x2840 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS1 + CPU0 wakeup IRQ status + 0x2844 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS2 + CPU0 wakeup IRQ status + 0x2848 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS3 + CPU0 wakeup IRQ status + 0x284c + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_ENABLE0 + CPU0 wakeup IRQ enable + 0x2880 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE1 + CPU0 wakeup IRQ enable + 0x2884 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE2 + CPU0 wakeup IRQ enable + 0x2888 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE3 + CPU0 wakeup IRQ enable + 0x288c + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xf64 + registers + + + + PAD_PA00_FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA00_PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA01_FUNC_CTL + ALT SELECT + 0x8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA01_PAD_CTL + PAD SETTINGS + 0xc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA02_FUNC_CTL + ALT SELECT + 0x10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA02_PAD_CTL + PAD SETTINGS + 0x14 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA03_FUNC_CTL + ALT SELECT + 0x18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA03_PAD_CTL + PAD SETTINGS + 0x1c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA04_FUNC_CTL + ALT SELECT + 0x20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA04_PAD_CTL + PAD SETTINGS + 0x24 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA05_FUNC_CTL + ALT SELECT + 0x28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA05_PAD_CTL + PAD SETTINGS + 0x2c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA06_FUNC_CTL + ALT SELECT + 0x30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA06_PAD_CTL + PAD SETTINGS + 0x34 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA07_FUNC_CTL + ALT SELECT + 0x38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA07_PAD_CTL + PAD SETTINGS + 0x3c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA08_FUNC_CTL + ALT SELECT + 0x40 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA08_PAD_CTL + PAD SETTINGS + 0x44 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA09_FUNC_CTL + ALT SELECT + 0x48 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA09_PAD_CTL + PAD SETTINGS + 0x4c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA10_FUNC_CTL + ALT SELECT + 0x50 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA10_PAD_CTL + PAD SETTINGS + 0x54 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA11_FUNC_CTL + ALT SELECT + 0x58 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA11_PAD_CTL + PAD SETTINGS + 0x5c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA12_FUNC_CTL + ALT SELECT + 0x60 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA12_PAD_CTL + PAD SETTINGS + 0x64 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA13_FUNC_CTL + ALT SELECT + 0x68 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA13_PAD_CTL + PAD SETTINGS + 0x6c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA14_FUNC_CTL + ALT SELECT + 0x70 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA14_PAD_CTL + PAD SETTINGS + 0x74 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA15_FUNC_CTL + ALT SELECT + 0x78 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA15_PAD_CTL + PAD SETTINGS + 0x7c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA16_FUNC_CTL + ALT SELECT + 0x80 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA16_PAD_CTL + PAD SETTINGS + 0x84 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA17_FUNC_CTL + ALT SELECT + 0x88 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA17_PAD_CTL + PAD SETTINGS + 0x8c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA18_FUNC_CTL + ALT SELECT + 0x90 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA18_PAD_CTL + PAD SETTINGS + 0x94 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA19_FUNC_CTL + ALT SELECT + 0x98 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA19_PAD_CTL + PAD SETTINGS + 0x9c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA20_FUNC_CTL + ALT SELECT + 0xa0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA20_PAD_CTL + PAD SETTINGS + 0xa4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA21_FUNC_CTL + ALT SELECT + 0xa8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA21_PAD_CTL + PAD SETTINGS + 0xac + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA22_FUNC_CTL + ALT SELECT + 0xb0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA22_PAD_CTL + PAD SETTINGS + 0xb4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA23_FUNC_CTL + ALT SELECT + 0xb8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA23_PAD_CTL + PAD SETTINGS + 0xbc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA24_FUNC_CTL + ALT SELECT + 0xc0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA24_PAD_CTL + PAD SETTINGS + 0xc4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA25_FUNC_CTL + ALT SELECT + 0xc8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA25_PAD_CTL + PAD SETTINGS + 0xcc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA26_FUNC_CTL + ALT SELECT + 0xd0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA26_PAD_CTL + PAD SETTINGS + 0xd4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA27_FUNC_CTL + ALT SELECT + 0xd8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA27_PAD_CTL + PAD SETTINGS + 0xdc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA28_FUNC_CTL + ALT SELECT + 0xe0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA28_PAD_CTL + PAD SETTINGS + 0xe4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA29_FUNC_CTL + ALT SELECT + 0xe8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA29_PAD_CTL + PAD SETTINGS + 0xec + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA30_FUNC_CTL + ALT SELECT + 0xf0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA30_PAD_CTL + PAD SETTINGS + 0xf4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA31_FUNC_CTL + ALT SELECT + 0xf8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA31_PAD_CTL + PAD SETTINGS + 0xfc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB00_FUNC_CTL + ALT SELECT + 0x100 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB00_PAD_CTL + PAD SETTINGS + 0x104 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB01_FUNC_CTL + ALT SELECT + 0x108 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB01_PAD_CTL + PAD SETTINGS + 0x10c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB02_FUNC_CTL + ALT SELECT + 0x110 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB02_PAD_CTL + PAD SETTINGS + 0x114 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB03_FUNC_CTL + ALT SELECT + 0x118 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB03_PAD_CTL + PAD SETTINGS + 0x11c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB04_FUNC_CTL + ALT SELECT + 0x120 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB04_PAD_CTL + PAD SETTINGS + 0x124 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB05_FUNC_CTL + ALT SELECT + 0x128 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB05_PAD_CTL + PAD SETTINGS + 0x12c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB06_FUNC_CTL + ALT SELECT + 0x130 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB06_PAD_CTL + PAD SETTINGS + 0x134 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB07_FUNC_CTL + ALT SELECT + 0x138 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB07_PAD_CTL + PAD SETTINGS + 0x13c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB08_FUNC_CTL + ALT SELECT + 0x140 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB08_PAD_CTL + PAD SETTINGS + 0x144 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB09_FUNC_CTL + ALT SELECT + 0x148 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB09_PAD_CTL + PAD SETTINGS + 0x14c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB10_FUNC_CTL + ALT SELECT + 0x150 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB10_PAD_CTL + PAD SETTINGS + 0x154 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB11_FUNC_CTL + ALT SELECT + 0x158 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB11_PAD_CTL + PAD SETTINGS + 0x15c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB12_FUNC_CTL + ALT SELECT + 0x160 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB12_PAD_CTL + PAD SETTINGS + 0x164 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB13_FUNC_CTL + ALT SELECT + 0x168 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB13_PAD_CTL + PAD SETTINGS + 0x16c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB14_FUNC_CTL + ALT SELECT + 0x170 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB14_PAD_CTL + PAD SETTINGS + 0x174 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB15_FUNC_CTL + ALT SELECT + 0x178 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB15_PAD_CTL + PAD SETTINGS + 0x17c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB16_FUNC_CTL + ALT SELECT + 0x180 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB16_PAD_CTL + PAD SETTINGS + 0x184 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB17_FUNC_CTL + ALT SELECT + 0x188 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB17_PAD_CTL + PAD SETTINGS + 0x18c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB18_FUNC_CTL + ALT SELECT + 0x190 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB18_PAD_CTL + PAD SETTINGS + 0x194 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB19_FUNC_CTL + ALT SELECT + 0x198 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB19_PAD_CTL + PAD SETTINGS + 0x19c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB20_FUNC_CTL + ALT SELECT + 0x1a0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB20_PAD_CTL + PAD SETTINGS + 0x1a4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB21_FUNC_CTL + ALT SELECT + 0x1a8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB21_PAD_CTL + PAD SETTINGS + 0x1ac + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB22_FUNC_CTL + ALT SELECT + 0x1b0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB22_PAD_CTL + PAD SETTINGS + 0x1b4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB23_FUNC_CTL + ALT SELECT + 0x1b8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB23_PAD_CTL + PAD SETTINGS + 0x1bc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB24_FUNC_CTL + ALT SELECT + 0x1c0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB24_PAD_CTL + PAD SETTINGS + 0x1c4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB25_FUNC_CTL + ALT SELECT + 0x1c8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB25_PAD_CTL + PAD SETTINGS + 0x1cc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB26_FUNC_CTL + ALT SELECT + 0x1d0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB26_PAD_CTL + PAD SETTINGS + 0x1d4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB27_FUNC_CTL + ALT SELECT + 0x1d8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB27_PAD_CTL + PAD SETTINGS + 0x1dc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB28_FUNC_CTL + ALT SELECT + 0x1e0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB28_PAD_CTL + PAD SETTINGS + 0x1e4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB29_FUNC_CTL + ALT SELECT + 0x1e8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB29_PAD_CTL + PAD SETTINGS + 0x1ec + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB30_FUNC_CTL + ALT SELECT + 0x1f0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB30_PAD_CTL + PAD SETTINGS + 0x1f4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB31_FUNC_CTL + ALT SELECT + 0x1f8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB31_PAD_CTL + PAD SETTINGS + 0x1fc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC00_FUNC_CTL + ALT SELECT + 0x200 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC00_PAD_CTL + PAD SETTINGS + 0x204 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC01_FUNC_CTL + ALT SELECT + 0x208 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC01_PAD_CTL + PAD SETTINGS + 0x20c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC02_FUNC_CTL + ALT SELECT + 0x210 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC02_PAD_CTL + PAD SETTINGS + 0x214 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC03_FUNC_CTL + ALT SELECT + 0x218 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC03_PAD_CTL + PAD SETTINGS + 0x21c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC04_FUNC_CTL + ALT SELECT + 0x220 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC04_PAD_CTL + PAD SETTINGS + 0x224 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC05_FUNC_CTL + ALT SELECT + 0x228 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC05_PAD_CTL + PAD SETTINGS + 0x22c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC06_FUNC_CTL + ALT SELECT + 0x230 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC06_PAD_CTL + PAD SETTINGS + 0x234 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC07_FUNC_CTL + ALT SELECT + 0x238 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC07_PAD_CTL + PAD SETTINGS + 0x23c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC08_FUNC_CTL + ALT SELECT + 0x240 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC08_PAD_CTL + PAD SETTINGS + 0x244 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC09_FUNC_CTL + ALT SELECT + 0x248 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC09_PAD_CTL + PAD SETTINGS + 0x24c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC10_FUNC_CTL + ALT SELECT + 0x250 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC10_PAD_CTL + PAD SETTINGS + 0x254 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC11_FUNC_CTL + ALT SELECT + 0x258 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC11_PAD_CTL + PAD SETTINGS + 0x25c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC12_FUNC_CTL + ALT SELECT + 0x260 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC12_PAD_CTL + PAD SETTINGS + 0x264 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC13_FUNC_CTL + ALT SELECT + 0x268 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC13_PAD_CTL + PAD SETTINGS + 0x26c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC14_FUNC_CTL + ALT SELECT + 0x270 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC14_PAD_CTL + PAD SETTINGS + 0x274 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC15_FUNC_CTL + ALT SELECT + 0x278 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC15_PAD_CTL + PAD SETTINGS + 0x27c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC16_FUNC_CTL + ALT SELECT + 0x280 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC16_PAD_CTL + PAD SETTINGS + 0x284 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC17_FUNC_CTL + ALT SELECT + 0x288 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC17_PAD_CTL + PAD SETTINGS + 0x28c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC18_FUNC_CTL + ALT SELECT + 0x290 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC18_PAD_CTL + PAD SETTINGS + 0x294 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC19_FUNC_CTL + ALT SELECT + 0x298 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC19_PAD_CTL + PAD SETTINGS + 0x29c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC20_FUNC_CTL + ALT SELECT + 0x2a0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC20_PAD_CTL + PAD SETTINGS + 0x2a4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC21_FUNC_CTL + ALT SELECT + 0x2a8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC21_PAD_CTL + PAD SETTINGS + 0x2ac + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC22_FUNC_CTL + ALT SELECT + 0x2b0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC22_PAD_CTL + PAD SETTINGS + 0x2b4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC23_FUNC_CTL + ALT SELECT + 0x2b8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC23_PAD_CTL + PAD SETTINGS + 0x2bc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC24_FUNC_CTL + ALT SELECT + 0x2c0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC24_PAD_CTL + PAD SETTINGS + 0x2c4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC25_FUNC_CTL + ALT SELECT + 0x2c8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC25_PAD_CTL + PAD SETTINGS + 0x2cc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC26_FUNC_CTL + ALT SELECT + 0x2d0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC26_PAD_CTL + PAD SETTINGS + 0x2d4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC27_FUNC_CTL + ALT SELECT + 0x2d8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC27_PAD_CTL + PAD SETTINGS + 0x2dc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC28_FUNC_CTL + ALT SELECT + 0x2e0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC28_PAD_CTL + PAD SETTINGS + 0x2e4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC29_FUNC_CTL + ALT SELECT + 0x2e8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC29_PAD_CTL + PAD SETTINGS + 0x2ec + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC30_FUNC_CTL + ALT SELECT + 0x2f0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC30_PAD_CTL + PAD SETTINGS + 0x2f4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC31_FUNC_CTL + ALT SELECT + 0x2f8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC31_PAD_CTL + PAD SETTINGS + 0x2fc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD00_FUNC_CTL + ALT SELECT + 0x300 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD00_PAD_CTL + PAD SETTINGS + 0x304 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD01_FUNC_CTL + ALT SELECT + 0x308 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD01_PAD_CTL + PAD SETTINGS + 0x30c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD02_FUNC_CTL + ALT SELECT + 0x310 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD02_PAD_CTL + PAD SETTINGS + 0x314 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD03_FUNC_CTL + ALT SELECT + 0x318 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD03_PAD_CTL + PAD SETTINGS + 0x31c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD04_FUNC_CTL + ALT SELECT + 0x320 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD04_PAD_CTL + PAD SETTINGS + 0x324 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD05_FUNC_CTL + ALT SELECT + 0x328 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD05_PAD_CTL + PAD SETTINGS + 0x32c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD06_FUNC_CTL + ALT SELECT + 0x330 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD06_PAD_CTL + PAD SETTINGS + 0x334 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD07_FUNC_CTL + ALT SELECT + 0x338 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD07_PAD_CTL + PAD SETTINGS + 0x33c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD08_FUNC_CTL + ALT SELECT + 0x340 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD08_PAD_CTL + PAD SETTINGS + 0x344 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD09_FUNC_CTL + ALT SELECT + 0x348 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD09_PAD_CTL + PAD SETTINGS + 0x34c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD10_FUNC_CTL + ALT SELECT + 0x350 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD10_PAD_CTL + PAD SETTINGS + 0x354 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD11_FUNC_CTL + ALT SELECT + 0x358 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD11_PAD_CTL + PAD SETTINGS + 0x35c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD12_FUNC_CTL + ALT SELECT + 0x360 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD12_PAD_CTL + PAD SETTINGS + 0x364 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD13_FUNC_CTL + ALT SELECT + 0x368 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD13_PAD_CTL + PAD SETTINGS + 0x36c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD14_FUNC_CTL + ALT SELECT + 0x370 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD14_PAD_CTL + PAD SETTINGS + 0x374 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD15_FUNC_CTL + ALT SELECT + 0x378 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD15_PAD_CTL + PAD SETTINGS + 0x37c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD16_FUNC_CTL + ALT SELECT + 0x380 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD16_PAD_CTL + PAD SETTINGS + 0x384 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD17_FUNC_CTL + ALT SELECT + 0x388 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD17_PAD_CTL + PAD SETTINGS + 0x38c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD18_FUNC_CTL + ALT SELECT + 0x390 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD18_PAD_CTL + PAD SETTINGS + 0x394 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD19_FUNC_CTL + ALT SELECT + 0x398 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD19_PAD_CTL + PAD SETTINGS + 0x39c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD20_FUNC_CTL + ALT SELECT + 0x3a0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD20_PAD_CTL + PAD SETTINGS + 0x3a4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD21_FUNC_CTL + ALT SELECT + 0x3a8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD21_PAD_CTL + PAD SETTINGS + 0x3ac + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD22_FUNC_CTL + ALT SELECT + 0x3b0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD22_PAD_CTL + PAD SETTINGS + 0x3b4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PD23_FUNC_CTL + ALT SELECT + 0x3b8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD23_PAD_CTL + PAD SETTINGS + 0x3bc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX00_FUNC_CTL + ALT SELECT + 0xd00 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX00_PAD_CTL + PAD SETTINGS + 0xd04 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX01_FUNC_CTL + ALT SELECT + 0xd08 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX01_PAD_CTL + PAD SETTINGS + 0xd0c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX02_FUNC_CTL + ALT SELECT + 0xd10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX02_PAD_CTL + PAD SETTINGS + 0xd14 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX03_FUNC_CTL + ALT SELECT + 0xd18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX03_PAD_CTL + PAD SETTINGS + 0xd1c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX04_FUNC_CTL + ALT SELECT + 0xd20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX04_PAD_CTL + PAD SETTINGS + 0xd24 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX05_FUNC_CTL + ALT SELECT + 0xd28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX05_PAD_CTL + PAD SETTINGS + 0xd2c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX06_FUNC_CTL + ALT SELECT + 0xd30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX06_PAD_CTL + PAD SETTINGS + 0xd34 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX07_FUNC_CTL + ALT SELECT + 0xd38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX07_PAD_CTL + PAD SETTINGS + 0xd3c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY00_FUNC_CTL + ALT SELECT + 0xe00 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY00_PAD_CTL + PAD SETTINGS + 0xe04 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY01_FUNC_CTL + ALT SELECT + 0xe08 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY01_PAD_CTL + PAD SETTINGS + 0xe0c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY02_FUNC_CTL + ALT SELECT + 0xe10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY02_PAD_CTL + PAD SETTINGS + 0xe14 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY03_FUNC_CTL + ALT SELECT + 0xe18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY03_PAD_CTL + PAD SETTINGS + 0xe1c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY04_FUNC_CTL + ALT SELECT + 0xe20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY04_PAD_CTL + PAD SETTINGS + 0xe24 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY05_FUNC_CTL + ALT SELECT + 0xe28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY05_PAD_CTL + PAD SETTINGS + 0xe2c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY06_FUNC_CTL + ALT SELECT + 0xe30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY06_PAD_CTL + PAD SETTINGS + 0xe34 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY07_FUNC_CTL + ALT SELECT + 0xe38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY07_PAD_CTL + PAD SETTINGS + 0xe3c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY08_FUNC_CTL + ALT SELECT + 0xe40 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY08_PAD_CTL + PAD SETTINGS + 0xe44 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY09_FUNC_CTL + ALT SELECT + 0xe48 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY09_PAD_CTL + PAD SETTINGS + 0xe4c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY10_FUNC_CTL + ALT SELECT + 0xe50 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY10_PAD_CTL + PAD SETTINGS + 0xe54 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY11_FUNC_CTL + ALT SELECT + 0xe58 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY11_PAD_CTL + PAD SETTINGS + 0xe5c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ00_FUNC_CTL + ALT SELECT + 0xf00 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ00_PAD_CTL + PAD SETTINGS + 0xf04 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ01_FUNC_CTL + ALT SELECT + 0xf08 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ01_PAD_CTL + PAD SETTINGS + 0xf0c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ02_FUNC_CTL + ALT SELECT + 0xf10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ02_PAD_CTL + PAD SETTINGS + 0xf14 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ03_FUNC_CTL + ALT SELECT + 0xf18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ03_PAD_CTL + PAD SETTINGS + 0xf1c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ04_FUNC_CTL + ALT SELECT + 0xf20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ04_PAD_CTL + PAD SETTINGS + 0xf24 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ05_FUNC_CTL + ALT SELECT + 0xf28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ05_PAD_CTL + PAD SETTINGS + 0xf2c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ06_FUNC_CTL + ALT SELECT + 0xf30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ06_PAD_CTL + PAD SETTINGS + 0xf34 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ07_FUNC_CTL + ALT SELECT + 0xf38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ07_PAD_CTL + PAD SETTINGS + 0xf3c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ08_FUNC_CTL + ALT SELECT + 0xf40 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ08_PAD_CTL + PAD SETTINGS + 0xf44 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ09_FUNC_CTL + ALT SELECT + 0xf48 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ09_PAD_CTL + PAD SETTINGS + 0xf4c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ10_FUNC_CTL + ALT SELECT + 0xf50 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ10_PAD_CTL + PAD SETTINGS + 0xf54 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ11_FUNC_CTL + ALT SELECT + 0xf58 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ11_PAD_CTL + PAD SETTINGS + 0xf5c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + + + PIOC + PIOC + IOC + 0xf40d8000 + + + BIOC + BIOC + IOC + 0xf5010000 + + + OTPSHW + OTPSHW + OTP + 0xf4080000 + + 0x0 + 0xc08 + registers + + + + SHADOW_SHADOW000 + Fuse shadow registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW001 + Fuse shadow registers + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW002 + Fuse shadow registers + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW003 + Fuse shadow registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW004 + Fuse shadow registers + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW005 + Fuse shadow registers + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW006 + Fuse shadow registers + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW007 + Fuse shadow registers + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW008 + Fuse shadow registers + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW009 + Fuse shadow registers + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW010 + Fuse shadow registers + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW011 + Fuse shadow registers + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW012 + Fuse shadow registers + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW013 + Fuse shadow registers + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW014 + Fuse shadow registers + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW015 + Fuse shadow registers + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW016 + Fuse shadow registers + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW017 + Fuse shadow registers + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW018 + Fuse shadow registers + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW019 + Fuse shadow registers + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW020 + Fuse shadow registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW021 + Fuse shadow registers + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW022 + Fuse shadow registers + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW023 + Fuse shadow registers + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW024 + Fuse shadow registers + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW025 + Fuse shadow registers + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW026 + Fuse shadow registers + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW027 + Fuse shadow registers + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW028 + Fuse shadow registers + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW029 + Fuse shadow registers + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW030 + Fuse shadow registers + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW031 + Fuse shadow registers + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW032 + Fuse shadow registers + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW033 + Fuse shadow registers + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW034 + Fuse shadow registers + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW035 + Fuse shadow registers + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW036 + Fuse shadow registers + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW037 + Fuse shadow registers + 0x94 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW038 + Fuse shadow registers + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW039 + Fuse shadow registers + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW040 + Fuse shadow registers + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW041 + Fuse shadow registers + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW042 + Fuse shadow registers + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW043 + Fuse shadow registers + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW044 + Fuse shadow registers + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW045 + Fuse shadow registers + 0xb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW046 + Fuse shadow registers + 0xb8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW047 + Fuse shadow registers + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW048 + Fuse shadow registers + 0xc0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW049 + Fuse shadow registers + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW050 + Fuse shadow registers + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW051 + Fuse shadow registers + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW052 + Fuse shadow registers + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW053 + Fuse shadow registers + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW054 + Fuse shadow registers + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW055 + Fuse shadow registers + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW056 + Fuse shadow registers + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW057 + Fuse shadow registers + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW058 + Fuse shadow registers + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW059 + Fuse shadow registers + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW060 + Fuse shadow registers + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW061 + Fuse shadow registers + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW062 + Fuse shadow registers + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW063 + Fuse shadow registers + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW064 + Fuse shadow registers + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW065 + Fuse shadow registers + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW066 + Fuse shadow registers + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW067 + Fuse shadow registers + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW068 + Fuse shadow registers + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW069 + Fuse shadow registers + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW070 + Fuse shadow registers + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW071 + Fuse shadow registers + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW072 + Fuse shadow registers + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW073 + Fuse shadow registers + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW074 + Fuse shadow registers + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW075 + Fuse shadow registers + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW076 + Fuse shadow registers + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW077 + Fuse shadow registers + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW078 + Fuse shadow registers + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW079 + Fuse shadow registers + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW080 + Fuse shadow registers + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW081 + Fuse shadow registers + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW082 + Fuse shadow registers + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW083 + Fuse shadow registers + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW084 + Fuse shadow registers + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW085 + Fuse shadow registers + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW086 + Fuse shadow registers + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW087 + Fuse shadow registers + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW088 + Fuse shadow registers + 0x160 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW089 + Fuse shadow registers + 0x164 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW090 + Fuse shadow registers + 0x168 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW091 + Fuse shadow registers + 0x16c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW092 + Fuse shadow registers + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW093 + Fuse shadow registers + 0x174 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW094 + Fuse shadow registers + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW095 + Fuse shadow registers + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW096 + Fuse shadow registers + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW097 + Fuse shadow registers + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW098 + Fuse shadow registers + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW099 + Fuse shadow registers + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW100 + Fuse shadow registers + 0x190 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW101 + Fuse shadow registers + 0x194 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW102 + Fuse shadow registers + 0x198 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW103 + Fuse shadow registers + 0x19c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW104 + Fuse shadow registers + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW105 + Fuse shadow registers + 0x1a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW106 + Fuse shadow registers + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW107 + Fuse shadow registers + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW108 + Fuse shadow registers + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW109 + Fuse shadow registers + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW110 + Fuse shadow registers + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW111 + Fuse shadow registers + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW112 + Fuse shadow registers + 0x1c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW113 + Fuse shadow registers + 0x1c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW114 + Fuse shadow registers + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW115 + Fuse shadow registers + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW116 + Fuse shadow registers + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW117 + Fuse shadow registers + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW118 + Fuse shadow registers + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW119 + Fuse shadow registers + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW120 + Fuse shadow registers + 0x1e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW121 + Fuse shadow registers + 0x1e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW122 + Fuse shadow registers + 0x1e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW123 + Fuse shadow registers + 0x1ec + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW124 + Fuse shadow registers + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW125 + Fuse shadow registers + 0x1f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW126 + Fuse shadow registers + 0x1f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW127 + Fuse shadow registers + 0x1fc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK00 + Fuse shadow lock + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK01 + Fuse shadow lock + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK02 + Fuse shadow lock + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK03 + Fuse shadow lock + 0x20c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK04 + Fuse shadow lock + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK05 + Fuse shadow lock + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK06 + Fuse shadow lock + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK07 + Fuse shadow lock + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_FUSE000 + Fuse Array + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE001 + Fuse Array + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE002 + Fuse Array + 0x408 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE003 + Fuse Array + 0x40c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE004 + Fuse Array + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE005 + Fuse Array + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE006 + Fuse Array + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE007 + Fuse Array + 0x41c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE008 + Fuse Array + 0x420 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE009 + Fuse Array + 0x424 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE010 + Fuse Array + 0x428 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE011 + Fuse Array + 0x42c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE012 + Fuse Array + 0x430 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE013 + Fuse Array + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE014 + Fuse Array + 0x438 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE015 + Fuse Array + 0x43c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE016 + Fuse Array + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE017 + Fuse Array + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE018 + Fuse Array + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE019 + Fuse Array + 0x44c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE020 + Fuse Array + 0x450 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE021 + Fuse Array + 0x454 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE022 + Fuse Array + 0x458 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE023 + Fuse Array + 0x45c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE024 + Fuse Array + 0x460 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE025 + Fuse Array + 0x464 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE026 + Fuse Array + 0x468 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE027 + Fuse Array + 0x46c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE028 + Fuse Array + 0x470 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE029 + Fuse Array + 0x474 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE030 + Fuse Array + 0x478 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE031 + Fuse Array + 0x47c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE032 + Fuse Array + 0x480 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE033 + Fuse Array + 0x484 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE034 + Fuse Array + 0x488 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE035 + Fuse Array + 0x48c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE036 + Fuse Array + 0x490 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE037 + Fuse Array + 0x494 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE038 + Fuse Array + 0x498 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE039 + Fuse Array + 0x49c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE040 + Fuse Array + 0x4a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE041 + Fuse Array + 0x4a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE042 + Fuse Array + 0x4a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE043 + Fuse Array + 0x4ac + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE044 + Fuse Array + 0x4b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE045 + Fuse Array + 0x4b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE046 + Fuse Array + 0x4b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE047 + Fuse Array + 0x4bc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE048 + Fuse Array + 0x4c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE049 + Fuse Array + 0x4c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE050 + Fuse Array + 0x4c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE051 + Fuse Array + 0x4cc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE052 + Fuse Array + 0x4d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE053 + Fuse Array + 0x4d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE054 + Fuse Array + 0x4d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE055 + Fuse Array + 0x4dc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE056 + Fuse Array + 0x4e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE057 + Fuse Array + 0x4e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE058 + Fuse Array + 0x4e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE059 + Fuse Array + 0x4ec + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE060 + Fuse Array + 0x4f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE061 + Fuse Array + 0x4f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE062 + Fuse Array + 0x4f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE063 + Fuse Array + 0x4fc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE064 + Fuse Array + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE065 + Fuse Array + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE066 + Fuse Array + 0x508 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE067 + Fuse Array + 0x50c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE068 + Fuse Array + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE069 + Fuse Array + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE070 + Fuse Array + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE071 + Fuse Array + 0x51c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE072 + Fuse Array + 0x520 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE073 + Fuse Array + 0x524 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE074 + Fuse Array + 0x528 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE075 + Fuse Array + 0x52c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE076 + Fuse Array + 0x530 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE077 + Fuse Array + 0x534 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE078 + Fuse Array + 0x538 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE079 + Fuse Array + 0x53c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE080 + Fuse Array + 0x540 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE081 + Fuse Array + 0x544 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE082 + Fuse Array + 0x548 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE083 + Fuse Array + 0x54c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE084 + Fuse Array + 0x550 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE085 + Fuse Array + 0x554 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE086 + Fuse Array + 0x558 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE087 + Fuse Array + 0x55c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE088 + Fuse Array + 0x560 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE089 + Fuse Array + 0x564 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE090 + Fuse Array + 0x568 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE091 + Fuse Array + 0x56c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE092 + Fuse Array + 0x570 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE093 + Fuse Array + 0x574 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE094 + Fuse Array + 0x578 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE095 + Fuse Array + 0x57c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE096 + Fuse Array + 0x580 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE097 + Fuse Array + 0x584 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE098 + Fuse Array + 0x588 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE099 + Fuse Array + 0x58c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE100 + Fuse Array + 0x590 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE101 + Fuse Array + 0x594 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE102 + Fuse Array + 0x598 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE103 + Fuse Array + 0x59c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE104 + Fuse Array + 0x5a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE105 + Fuse Array + 0x5a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE106 + Fuse Array + 0x5a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE107 + Fuse Array + 0x5ac + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE108 + Fuse Array + 0x5b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE109 + Fuse Array + 0x5b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE110 + Fuse Array + 0x5b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE111 + Fuse Array + 0x5bc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE112 + Fuse Array + 0x5c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE113 + Fuse Array + 0x5c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE114 + Fuse Array + 0x5c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE115 + Fuse Array + 0x5cc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE116 + Fuse Array + 0x5d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE117 + Fuse Array + 0x5d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE118 + Fuse Array + 0x5d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE119 + Fuse Array + 0x5dc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE120 + Fuse Array + 0x5e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE121 + Fuse Array + 0x5e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE122 + Fuse Array + 0x5e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE123 + Fuse Array + 0x5ec + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE124 + Fuse Array + 0x5f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE125 + Fuse Array + 0x5f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE126 + Fuse Array + 0x5f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE127 + Fuse Array + 0x5fc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK00 + Fuse lock + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK01 + Fuse lock + 0x604 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK02 + Fuse lock + 0x608 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK03 + Fuse lock + 0x60c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK04 + Fuse lock + 0x610 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK05 + Fuse lock + 0x614 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK06 + Fuse lock + 0x618 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK07 + Fuse lock + 0x61c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + REGION_LOAD_REGION0 + LOAD region + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + REGION_LOAD_REGION1 + LOAD region + 0xa24 + 32 + 0x00001008 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + REGION_LOAD_REGION2 + LOAD region + 0xa28 + 32 + 0x00000010 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + REGION_LOAD_REGION3 + LOAD region + 0xa2c + 32 + 0x00000000 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + OTP + OTP + OTP + 0xf40c8000 + + + PPOR + PPOR + PPOR + 0xf40c0000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOT + reset type triggered by reset + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TYPE + reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_COLD + reset type attribute + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf40c4000 + + 0x0 + 0x70 + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LOWPOWER_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 24 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0001044C + 0x00010FFF + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x00B010B0 + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: trun off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00B010B0 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000000 + 0x11818191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-write + + + DISABLE_POWER_LOSS + disable power loss protection +0: power loss protection enabled, DCDC shuts down when power loss +1: power loss protection disabled, DCDC try working after power voltage drop + 23 + 1 + read-write + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + ouput over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x00EF1C6E + 0x073F007F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_AUTOLP + enable auto enter low power mode +0: do not enter low power mode +1: enter low power mode if current is detected low + 4 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00EF1C6E + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + SOC power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: clock gated according to low power flow +10: clock is always off +11: clock is always on +bit0-1: fuse +bit2-3: sram +bit4-5: vad +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart +bit16-17:debug + 0 + 32 + read-write + + + + + DEBUG_STOP + Debug stop config + 0x50 + 32 + 0x00000001 + 0x00000003 + + + CPU1 + Stop peripheral when CPU1 enter debug mode +0: peripheral keep running when CPU1 in debug mode +1: peripheral enter debug mode when CPU1 enter debug + 1 + 1 + read-write + + + CPU0 + Stop peripheral when CPU0 enter debug mode +0: peripheral keep running when CPU0 in debug mode +1: peripheral enter debug mode when CPU0 enter debug + 0 + 1 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000316 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + + + PSEC + PSEC + PSEC + 0xf40cc000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + PMON + PMON + PMON + 0xf40d0000 + + 0x0 + 0x48 + registers + + + + MONITOR_GLITCH0_CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_GLITCH0_STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_GLITCH1_CONTROL + Glitch and clock monitor control + 0x8 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_GLITCH1_STATUS + Glitch and clock monitor status + 0xc + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_CONTROL + Glitch and clock monitor control + 0x10 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_STATUS + Glitch and clock monitor status + 0x14 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_CLOCK1_CONTROL + Glitch and clock monitor control + 0x18 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_CLOCK1_STATUS + Glitch and clock monitor status + 0x1c + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + IRQ_FLAG + No description avaiable + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description avaiable + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + PGPR + PGPR + PGPR + 0xf40d4000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + PLLCTLV2 + PLLCTLV2 + PLLCTLV2 + 0xf4100000 + + 0x0 + 0x244 + registers + + + + XTAL + OSC configuration + 0x0 + 32 + 0x0001FFFF + 0xB00FFFFF + + + BUSY + Busy flag +0: Oscillator is working or shutdown +1: Oscillator is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of RC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + PLL_PLL0_MFI + PLL0 multiple register + 0x80 + 32 + 0x00000010 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + PLL_PLL0_MFN + PLL0 fraction numerator register + 0x84 + 32 + 0x09896800 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + PLL_PLL0_MFD + PLL0 fraction demoninator register + 0x88 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + PLL_PLL0_SS_STEP + PLL0 spread spectrum step register + 0x8c + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL0_SS_STOP + PLL0 spread spectrum stop register + 0x90 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL0_CONFIG + PLL0 confguration register + 0x94 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + PLL_PLL0_LOCKTIME + PLL0 lock time register + 0x98 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + PLL_PLL0_STEPTIME + PLL0 step time register + 0x9c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + PLL_PLL0_ADVANCED + PLL0 advance configuration register + 0xa0 + 32 + 0x00000000 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + PLL_PLL0_DIV0 + PLL0 divider output 0 configuration register + 0xc0 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL0_DIV1 + PLL0 divider output 1 configuration register + 0xc4 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL0_DIV2 + PLL0 divider output 2 configuration register + 0xc8 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL1_MFI + PLL1 multiple register + 0x100 + 32 + 0x00000018 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + PLL_PLL1_MFN + PLL1 fraction numerator register + 0x104 + 32 + 0x00000000 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + PLL_PLL1_MFD + PLL1 fraction demoninator register + 0x108 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + PLL_PLL1_SS_STEP + PLL1 spread spectrum step register + 0x10c + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL1_SS_STOP + PLL1 spread spectrum stop register + 0x110 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL1_CONFIG + PLL1 confguration register + 0x114 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + PLL_PLL1_LOCKTIME + PLL1 lock time register + 0x118 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + PLL_PLL1_STEPTIME + PLL1 step time register + 0x11c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + PLL_PLL1_ADVANCED + PLL1 advance configuration register + 0x120 + 32 + 0x000009C4 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + PLL_PLL1_DIV0 + PLL1 divider output 0 configuration register + 0x140 + 32 + 0x00000001 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL1_DIV1 + PLL1 divider output 1 configuration register + 0x144 + 32 + 0x00000004 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL1_DIV2 + PLL1 divider output 0 configuration register + 0x148 + 32 + 0x00000001 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL2_MFI + PLL2 multiple register + 0x180 + 32 + 0x0000001E + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + PLL_PLL2_MFN + PLL2 fraction numerator register + 0x184 + 32 + 0x00182B80 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + PLL_PLL2_MFD + PLL2 fraction demoninator register + 0x188 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + PLL_PLL2_SS_STEP + PLL2 spread spectrum step register + 0x18c + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL2_SS_STOP + PLL2 spread spectrum stop register + 0x190 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL2_CONFIG + PLL2 confguration register + 0x194 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + PLL_PLL2_LOCKTIME + PLL2 lock time register + 0x198 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + PLL_PLL2_STEPTIME + PLL2 step time register + 0x19c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + PLL_PLL2_ADVANCED + PLL2 advance configuration register + 0x1a0 + 32 + 0x000009C4 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + PLL_PLL2_DIV0 + PLL2 divider output 0 configuration register + 0x1c0 + 32 + 0x00000002 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL2_DIV1 + PLL2 divider output 1 configuration register + 0x1c4 + 32 + 0x00000003 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL2_DIV2 + PLL2 divider output 0 configuration register + 0x1c8 + 32 + 0x00000002 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + + + TSNS + TSNS + TSNS + 0xf4104000 + + 0x0 + 0x3c + registers + + + + T + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Signed number of temperature in 256 x celsius degree + 0 + 32 + read-only + + + + + TMAX + No description avaiable + 0x4 + 32 + 0x007FFFFF + 0xFFFFFFFF + + + T + maximum temperature ever found + 0 + 32 + read-only + + + + + TMIN + No description avaiable + 0x8 + 32 + 0xFF800000 + 0xFFFFFFFF + + + T + minimum temperature ever found + 0 + 32 + read-only + + + + + AGE + No description avaiable + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + AGE + age of T register in 24MHz clock cycles + 0 + 32 + read-only + + + + + STATUS + No description avaiable + 0x10 + 32 + 0x00000000 + 0x80000001 + + + VALID + indicate value in T is valid or not +0: not valid +1:valid + 31 + 1 + read-only + + + TRIGGER + Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode + 0 + 1 + read-write + + + + + CONFIG + No description avaiable + 0x14 + 32 + 0x00300300 + 0xC3FF0713 + + + IRQ_EN + Enable interrupt + 31 + 1 + read-write + + + RST_EN + Enable reset + 30 + 1 + read-write + + + COMPARE_MIN_EN + Enable compare for minimum temperature + 25 + 1 + read-write + + + COMPARE_MAX_EN + Enable compare for maximum temperature + 24 + 1 + read-write + + + SPEED + cycles of a progressive step in 24M clock, valide from 24-255, default 63 +24: 24 cycle for a step +25: 25 cycle for a step +26: 26 cycle for a step +... +255: 255 cycle for a step + 16 + 8 + read-write + + + AVERAGE + Average time, defaul tin 2 +0: measure and return +1: twice and average +2: 4 times and average(default) +. . . +7: 128 times and average + 8 + 3 + read-write + + + CONTINUOUS + continuous mode that keep sampling temperature peridically +0: trigger mode +1: continuous mode + 4 + 1 + read-write + + + ASYNC + Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value +0: active mode +1: Async mode + 1 + 1 + read-write + + + ENABLE + Enable temperature +0: disable, temperature sensor is shut down +1: enable. Temperature sensor enabled + 0 + 1 + read-write + + + + + VALIDITY + No description avaiable + 0x18 + 32 + 0x016E3600 + 0xFFFFFFFF + + + VALIDITY + time for temperature values to expire in 24M clock cycles + 0 + 32 + read-write + + + + + FLAG + No description avaiable + 0x1c + 32 + 0x00000000 + 0x00330001 + + + RECORD_MIN_CLR + Clear minimum recorder of temerature, write 1 to clear + 21 + 1 + read-write + + + RECORD_MAX_CLR + Clear maximum recorder of temerature, write 1 to clear + 20 + 1 + read-write + + + UNDER_TEMP + Clear under temperature status, write 1 to clear + 17 + 1 + read-write + + + OVER_TEMP + Clear over temperature status, write 1 to clear + 16 + 1 + read-write + + + IRQ + IRQ flag, write 1 to clear + 0 + 1 + read-write + + + + + UPPER_LIM_IRQ + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_IRQ + No description avaiable + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + UPPER_LIM_RST + No description avaiable + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_RST + No description avaiable + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + ASYNC + No description avaiable + 0x30 + 32 + 0x00000000 + 0x010107FF + + + ASYNC_TYPE + Compare hotter than or colder than in asynchoronous mode +0: hotter than +1: colder than + 24 + 1 + read-write + + + POLARITY + No description avaiable + 16 + 1 + read-write + + + VALUE + Value of async mode to compare + 0 + 11 + read-write + + + + + ADVAN + No description avaiable + 0x38 + 32 + 0x00000000 + 0x03010003 + + + ASYNC_IRQ + interrupt status of asynchronous mode + 25 + 1 + read-only + + + ACTIVE_IRQ + interrupt status of active mode + 24 + 1 + read-only + + + SAMPLING + temperature sampling is working + 16 + 1 + read-only + + + NEG_ONLY + use negative compare polarity only + 1 + 1 + read-write + + + POS_ONLY + use positive compare polarity only + 0 + 1 + read-write + + + + + + + BPOR + BPOR + BPOR + 0xf5004000 + + 0x0 + 0x10 + registers + + + + POR_CAUSE + Power on cause + 0x0 + 32 + 0x00000000 + 0x0000001F + + + CAUSE + Power on cause, each bit represnts one cause, write 1 to clear each bit +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_SELECT + Power on select + 0x4 + 32 + 0x00000000 + 0x0000001F + + + SELECT + Power on cause select, each bit represnts one cause, value 1 enables corresponding cause +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_CONFIG + Power on reset config + 0x8 + 32 + 0x00000000 + 0x00000001 + + + RETENTION + retention battery domain setting +0: battery reset on reset pin reset happen +1: battery domain retention when reset pin reset happen + 0 + 1 + read-write + + + + + POR_CONTROL + Power down control + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + COUNTER + Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + 0 + 16 + read-write + + + + + + + BCFG + BCFG + TRIM + 0xf5008000 + + 0x0 + 0x14 + registers + + + + VBG_CFG + Bandgap config + 0x0 + 32 + 0x00000000 + 0x811F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + POWER_SAVE + Bandgap works in power save mode +0: not in power save mode +1: bandgap work in power save mode + 24 + 1 + read-write + + + VBG_1P0 + Bandgap 1.0V output trim + 16 + 5 + read-write + + + VBG_P65 + Bandgap 0.65V output trim + 8 + 5 + read-write + + + VBG_P50 + Bandgap 0.50V output trim + 0 + 5 + read-write + + + + + IRC32K_CFG + On-chip 32k oscillator config + 0x8 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + XTAL32K_CFG + XTAL 32K config + 0xc + 32 + 0x00000000 + 0x00001313 + + + HYST_EN + crystal 32k hysteres enable + 12 + 1 + read-write + + + GMSEL + crystal 32k gm selection + 8 + 2 + read-write + + + CFG + crystal 32k config + 4 + 1 + read-write + + + AMP + crystal 32k amplifier + 0 + 2 + read-write + + + + + CLK_CFG + Clock config + 0x10 + 32 + 0x00000000 + 0x10010010 + + + XTAL_SEL + crystal selected + 28 + 1 + read-only + + + KEEP_IRC + force irc32k run + 16 + 1 + read-write + + + FORCE_XTAL + force switch to crystal + 4 + 1 + read-write + + + + + + + BUTN + BUTN + BUTN + 0xf500c000 + + 0x0 + 0xc + registers + + + + BTN_STATUS + Button status + 0x0 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + BTN_IRQ_MASK + Button interrupt mask + 0x4 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + LED_INTENSE + Debounce setting + 0x8 + 32 + 0x00000000 + 0x000F000F + + + RLED + Rbutton brightness 0 + 16 + 4 + read-write + + + PLED + Pbutton brightness 0 + 0 + 4 + read-write + + + + + + + BGPR + BGPR + BGPR + 0xf5018000 + + 0x0 + 0x20 + registers + + + + BATT_GPR0 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR1 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR2 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR3 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR4 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR5 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR6 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR7 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + BSEC + BSEC + BSEC + 0xf5040000 + + 0x0 + 0x14 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x0003000F + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + BATT_FAIL + BATT secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 3 + 1 + read-write + + + BATT_NSC + BATT secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 2 + 1 + read-write + + + BATT_SEC + BATT secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 1 + 1 + read-write + + + BATT_INS + BATT secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 0 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF0003 + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + BATT_ESC_NSC + BATT is escalating non-secure event + 1 + 1 + read-only + + + BATT_ESC_SEC + BATT is escalting ssecure event + 0 + 1 + read-only + + + + + + + RTC + RTC + RTC + 0xf5044000 + + 0x0 + 0x28 + registers + + + + SECOND + Second counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SECOND + second counter + 0 + 32 + read-write + + + + + SUBSEC + Sub-second counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SUBSEC + sub second counter + 0 + 32 + read-only + + + + + SEC_SNAP + Second counter snap shot + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_SNAP + second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + SUB_SNAP + Sub-second counter snap shot + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SUB_SNAP + sub second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + ALARM0 + RTC alarm0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM0_INC + Alarm0 incremental + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM1 + RTC alarm1 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM1_INC + Alarm1 incremental + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM_FLAG + RTC alarm flag + 0x20 + 32 + 0x00000000 + 0x00000003 + + + ALARM1 + alarm1 happen + 1 + 1 + read-write + + + ALARM0 + alarm0 happen + 0 + 1 + read-write + + + + + ALARM_EN + RTC alarm enable + 0x24 + 32 + 0x00000000 + 0x00000003 + + + ENABLE1 + alarm1 mask +0: alarm1 disabled +1: alarm1 enabled + 1 + 1 + read-write + + + ENABLE0 + alarm0 mask +0: alarm0 disabled +1: alarm0 enabled + 0 + 1 + read-write + + + + + + + BKEY + BKEY + BKEY + 0xf5048000 + + 0x0 + 0x4c + registers + + + + KEY_0_DATA_0 + Key data + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_1 + Key data + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_2 + Key data + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_3 + Key data + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_4 + Key data + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_5 + Key data + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_6 + Key data + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_7 + Key data + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_0 + Key data + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_1 + Key data + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_2 + Key data + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_3 + Key data + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_4 + Key data + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_5 + Key data + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_6 + Key data + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_7 + Key data + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + ECC_KEY0 + Key ECC and access control + 0x40 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + ECC_KEY1 + Key 1 ECC and access control + 0x44 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + SELECT + Key selection + 0x48 + 32 + 0x00000000 + 0x00000001 + + + SELECT + select key, key0 treated as secure key, in non-scure mode, only key1 can be selected +0: select key0 in secure mode, key1 in non-secure mode +1: select key1 in secure or nonsecure mode + 0 + 1 + read-write + + + + + + + BMON + BMON + BMON + 0xf504c000 + + 0x0 + 0x1c + registers + + + + MONITOR_GLITCH0_CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_GLITCH0_STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_CONTROL + Glitch and clock monitor control + 0x10 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_STATUS + Glitch and clock monitor status + 0x14 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + + TAMP + TAMP + TAMP + 0xf5050000 + + 0x0 + 0x88 + registers + + + + TAMP_TAMP0_CONTROL + Tamper n control + 0x0 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP0_POLY + Tamper n Polynomial of LFSR + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP0_LFSR + Tamper n LFSR shift register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP1_CONTROL + Tamper1 control + 0x10 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP1_POLY + Tamper1 Polynomial of LFSR + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP1_LFSR + Tamper1 LFSR shift register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP2_CONTROL + Tamper2 control + 0x20 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP2_POLY + Tamper2 Polynomial of LFSR + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP2_LFSR + Tamper2 LFSR shift register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP3_CONTROL + Tamper3 control + 0x30 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP3_POLY + Tamper3 Polynomial of LFSR + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP3_LFSR + Tamper3 LFSR shift register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_FLAG + Tamper flag + 0x80 + 32 + 0x00000000 + 0x00000FFF + + + FLAG + tamper flag, each bit represents one tamper pin, write 1 to clear the flag +Note, clear can only be cleared when tamper disapeared + 0 + 12 + read-write + + + + + IRQ_EN + Tamper interrupt enable + 0x84 + 32 + 0x00000000 + 0x80000FFF + + + LOCK + lock bit for IRQ enable +0: enable bits can be changed +1: enable bits hold until next battery domain power cycle + 31 + 1 + read-write + + + IRQ_EN + interrupt enable, each bit represents one tamper pin +0: interrupt disabled +1: interrupt enabled + 0 + 12 + read-write + + + + + + + MONO + MONO + MONO + 0xf5054000 + + 0x0 + 0x8 + registers + + + + MONOL + Low part of monotonic counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + low part of monotonica counter, write to this counter will cause counter increase by 1 + 0 + 32 + read-write + + + + + MONOH + High part of monotonic counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPOCH + Fuse value for high part of monotonica + 16 + 16 + read-write + + + COUNTER + high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow + 0 + 16 + read-write + + + + + + + \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/SConscript new file mode 100644 index 0000000000..985fd5d7e6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/SConscript @@ -0,0 +1,24 @@ +import os +import sys +Import('rtconfig') +from building import * + +#get current directory +cwd = GetCurrentDir() + +# Update include path +path = [ cwd, cwd + '/boot' ] + +# The set of source files associated with this SConscript file. +src = Split(''' + system.c + hpm_l1c_drv.c + hpm_sysctl_drv.c + hpm_clock_drv.c + boot/hpm_bootheader.c +''') + + +group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) + +Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.c new file mode 100644 index 0000000000..30c2edc202 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_bootheader.h" + +/* symbol exported from startup.S */ +extern uint32_t _start[]; + +/* following symbols exported from linker script */ +extern uint32_t __app_load_addr__[]; +extern uint32_t __app_offset__[]; +extern uint32_t __fw_size__[]; + +#define FW_SIZE (32768) +__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { + (uint32_t)__app_offset__, /* offset */ + (uint32_t)__fw_size__, /* size */ + 0, /* flags */ + 0, /* reserved0 */ + (uint32_t) &__app_load_addr__, /* load_addr */ + 0, /* reserved1 */ + (uint32_t) _start, /* entry_point */ + 0, /* reserved2 */ + {0}, /* hash */ + {0}, /* iv */ +}; + +__attribute__ ((section(".boot_header"))) const boot_header_t header = { + HPM_BOOTHEADER_TAG, /* tag */ + 0x10, /* version*/ + sizeof(header) + sizeof(fw_info), + 0, /* flags */ + 0, /* sw_version */ + 0, /* fuse_version */ + 1, /* fw_count */ + 0, + 0, /* sig_block_offset */ +}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.h new file mode 100644 index 0000000000..c2bf30d0b0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/boot/hpm_bootheader.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BOOT_HEADER_H +#define HPM_BOOT_HEADER_H + +#include "hpm_common.h" + +#define HPM_BOOTHEADER_TAG (0xBFU) +#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) + +#ifndef HPM_BOOT_FW_COUNT +#define HPM_BOOT_FW_COUNT 1 +#endif + +#if HPM_BOOT_FW_COUNT < 1 +#error "HPM_BOOT_FW_COUNT can't be less than 1" +#endif + +typedef struct { + uint32_t offset; /* 0x0: offset to boot_header start */ + uint32_t size; /* 0x4: size in bytes */ + uint32_t flags; /* 0x8: [3:0] fw type: */ + /* 0 - executable */ + /* 1 - cmd container */ + /* [11:8] - hash type */ + /* 0 - none */ + /* 1 - sha256 */ + /* 2 - sm3 */ + uint32_t reserved0; /* 0xC */ + uint32_t load_addr; /* 0x10: load address */ + uint32_t reserved1; /* 0x14 */ + uint32_t entry_point; /* 0x18: application entry */ + uint32_t reserved2; /* 0x1C */ + uint8_t hash[64]; /* 0x20: hash value */ + uint8_t iv[32]; /* 0x60: initial vector */ +} fw_info_table_t; + +typedef struct { + uint8_t tag; /* 0x0: must be '0xbf' */ + uint8_t version; /* 0x1: header version */ + uint16_t length; /* 0x2: header length, max 8KB */ + uint32_t flags; /* 0x4: [3:0] SRK set */ + /* [7:4] SRK index */ + /* [15:8] SRK_REVOKE_MASK */ + /* [19:16] Signature Type */ + /* 1: ECDSA */ + /* 2: SM2 */ + uint16_t sw_version; /* 0x8: software version */ + uint8_t fuse_version; /* 0xA: fuse version */ + uint8_t fw_count; /* 0xB: number of fw */ + uint16_t dc_block_offset; /* 0xC: device config block offset*/ + uint16_t sig_block_offset; /* 0xE: signature block offset */ + /* + * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] + * uint32_t dc_info[]; [> <] + */ +} boot_header_t; + +#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h new file mode 100644 index 0000000000..8d6e337a35 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BATT_IOMUX_H +#define HPM_BATT_IOMUX_H + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ08_FUNC_CTL function mux definitions */ +#define IOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ08_FUNC_CTL_TAMP_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ09_FUNC_CTL function mux definitions */ +#define IOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ09_FUNC_CTL_TAMP_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ10_FUNC_CTL function mux definitions */ +#define IOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ10_FUNC_CTL_HIBERNATE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ10_FUNC_CTL_TAMP_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ11_FUNC_CTL function mux definitions */ +#define IOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ11_FUNC_CTL_STANDBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ11_FUNC_CTL_TAMP_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_BATT_IOMUX_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c new file mode 100644 index 0000000000..51e3b793c8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_soc.h" +#include "hpm_common.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_csr_regs.h" +#include "riscv/riscv_core.h" +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define FREQ_1MHz (1000000UL) + +/* Clock preset values */ +#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) +#define FREQ_PRESET1_PLL0_CLK0 (400000000UL) +#define FREQ_PRESET1_PLL0_CLK1 (333333333UL) +#define FREQ_PRESET1_PLL1_CLK2 (250000000UL) +#define FREQ_PRESET1_PLL1_CLK0 (480000000UL) +#define FREQ_PRESET1_PLL1_CLK1 (320000000UL) +#define FREQ_PRESET1_PLL2_CLK0 (5160960000UL) +#define FREQ_PRESET1_PLL2_CLK1 (4515840000UL) +#define FREQ_32KHz (32768UL) +#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) +#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) +#define I2S_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->I2SCLK) +#define WDG_INSTANCE_NUM (4U) +#define BUS_FREQ_MAX (166000000UL) + +/* Clock On/Off definitions */ +#define CLOCK_ON (true) +#define CLOCK_OFF (false) + + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ + + + +/** + * @brief Get Clock frequency for IP in common group + */ +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); + +/** + * @brief Get Clock frequency for I2S or ADC + */ +static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t instance); + +/** + * @brief Get Clock frequency for DAC + */ +static uint32_t get_frequency_for_dac(uint32_t instance); + +/** + * @brief Get Clock frequency for WDG + */ +static uint32_t get_frequency_for_wdg(uint32_t instance); + +/** + * @brief Turn on/off the IP clock + */ +static void switch_ip_clock(clock_name_t clock_name, bool on); + +static uint32_t get_frequency_for_cpu(void); +static uint32_t get_frequency_for_axi(void); +static uint32_t get_frequency_for_ahb(void); + + +/*********************************************************************************************************************** + * Variables + **********************************************************************************************************************/ +static const clock_node_t s_adc_clk_mux_node[] = { + clock_node_ana0, + clock_node_ahb, +}; + +static const clock_node_t s_dac_clk_mux_node[] = { + clock_node_ana3, + clock_node_ahb +}; + +static const clock_node_t s_i2s_clk_mux_node[] = { + clock_node_aud0, + clock_node_aud1, +}; + +static WDG_Type *const s_wdgs[] = { HPM_WDG0, HPM_WDG1}; + +uint32_t hpm_core_clock; + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +uint32_t clock_get_frequency(clock_name_t clock_name) +{ + uint32_t clk_freq = 0UL; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); + break; + case CLK_SRC_GROUP_ADC: + clk_freq = get_frequency_for_i2s_or_adc(CLK_SRC_GROUP_ADC, node_or_instance); + break; + case CLK_SRC_GROUP_DAC: + clk_freq = get_frequency_for_dac(node_or_instance); + break; + case CLK_SRC_GROUP_I2S: + clk_freq = get_frequency_for_i2s_or_adc(CLK_SRC_GROUP_I2S, node_or_instance); + break; + case CLK_SRC_GROUP_WDG: + clk_freq = get_frequency_for_wdg(node_or_instance); + break; + case CLK_SRC_GROUP_PMIC: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case CLK_SRC_GROUP_CPU0: + clk_freq = get_frequency_for_cpu(); + break; + case CLK_SRC_GROUP_AHB: + clk_freq = get_frequency_for_ahb(); + break; + case CLK_SRC_GROUP_AXI: + clk_freq = get_frequency_for_axi(); + break; + case CLK_SRC_GROUP_SRC: + clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); + break; + default: + clk_freq = 0UL; + break; + } + return clk_freq; +} + +uint32_t get_frequency_for_source(clock_source_t source) +{ + uint32_t clk_freq = 0UL; + switch (source) { + case clock_source_osc0_clk0: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case clock_source_pll0_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); + break; + case clock_source_pll0_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); + break; + case clock_source_pll0_clk2: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); + break; + case clock_source_pll1_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); + break; + case clock_source_pll1_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); + break; + case clock_source_pll2_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 0U); + break; + case clock_source_pll2_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 1U); + break; + default: + clk_freq = 0UL; + break; + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) +{ + uint32_t clk_freq = 0UL; + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); + + if (node_or_instance < clock_node_end) { + uint32_t clk_node = (uint32_t) node_or_instance; + + uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); + clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); + clk_freq = get_frequency_for_source(clk_mux) / clk_div; + } + return clk_freq; +} + +static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + if (clk_src_type == CLK_SRC_GROUP_ADC) { + uint32_t adc_index = instance; + if (adc_index < ADC_INSTANCE_NUM) { + is_mux_valid = true; + uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); + if (mux_in_reg == 1) { + node = s_adc_clk_mux_node[1]; + } else { + node = s_adc_clk_mux_node[0] + adc_index; + } + } + } else { + uint32_t i2s_index = instance; + if (i2s_index < I2S_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[i2s_index]); + if (mux_in_reg < ARRAY_SIZE(s_i2s_clk_mux_node)) { + node = s_i2s_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + } + + if (is_mux_valid) { + clk_freq = get_frequency_for_ip_in_common_group(node); + } + return clk_freq; +} + +static uint32_t get_frequency_for_dac(uint32_t instance) +{ + uint32_t clk_freq = 0UL; + clock_node_t node = clock_node_end; + if (instance < DAC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[instance]); + if (mux_in_reg == 1) { + node = s_dac_clk_mux_node[1]; + } else { + node = s_dac_clk_mux_node[0] + instance; + } + + if (node == clock_node_ahb) { + clk_freq = get_frequency_for_ahb(); + } else { + clk_freq = get_frequency_for_ip_in_common_group(node); + } + } + + return clk_freq; +} + +static uint32_t get_frequency_for_wdg(uint32_t instance) +{ + uint32_t freq_in_hz; + /* EXT clock is chosen */ + if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { + freq_in_hz = get_frequency_for_cpu(); + } + /* PCLK is chosen */ + else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_cpu(void) +{ + uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_source(mux) / div); +} + +static uint32_t get_frequency_for_axi(void) +{ + uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_cpu() / div); +} + +static uint32_t get_frequency_for_ahb(void) +{ + uint32_t div = SYSCTL_CLOCK_CPU_SUB1_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_cpu() / div); +} + +clk_src_t clock_get_source(clock_name_t clock_name) +{ + uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; + uint8_t clk_src_index = 0xFU; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_ADC: + if (node_or_instance < ADC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_ADC; + clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_I2S: + if (node_or_instance < I2S_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_I2S; + clk_src_index = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_WDG; + clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); + } + break; + case CLK_SRC_GROUP_PMIC: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = clock_source_osc0_clk0; + break; + case CLK_SRC_GROUP_CPU0: + case CLK_SRC_GROUP_AHB: + case CLK_SRC_GROUP_AXI: + clk_src_group = CLK_SRC_GROUP_CPU0; + clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_SRC: + clk_src_index = (clk_src_t) node_or_instance; + break; + default: + clk_src_group = CLK_SRC_GROUP_INVALID; + break; + } + + clk_src_t clk_src; + if (clk_src_group != CLK_SRC_GROUP_INVALID) { + clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); + } else { + clk_src = clk_src_invalid; + } + + return clk_src; +} + +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src != clk_adc_src_ahb) && (src != clk_adc_src_ana)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->ADCCLK[node_or_instance] = + (HPM_SYSCTL->ADCCLK[node_or_instance] & SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_DAC) || (node_or_instance >= DAC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src != clk_dac_src_ana) || (src != clk_dac_src_ahb)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->DACCLK[node_or_instance] = + (HPM_SYSCTL->DACCLK[node_or_instance] & SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_I2S) || (node_or_instance >= I2S_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src != clk_i2s_src_aud0) || (src != clk_i2s_src_aud1)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->I2SCLK[node_or_instance] = + (HPM_SYSCTL->I2SCLK[node_or_instance] & SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) +{ + hpm_stat_t status = status_success; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + if ((div < 1U) || (div > 256U)) { + status = status_clk_div_invalid; + } else { + clock_source_t source = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); + sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, source, div); + } + break; + case CLK_SRC_GROUP_ADC: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_I2S: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + if (src == clk_wdg_src_ahb0) { + s_wdgs[node_or_instance]->CTRL &= ~WDG_CTRL_CLKSEL_MASK; + } else if (src == clk_wdg_src_osc32k) { + s_wdgs[node_or_instance]->CTRL |= WDG_CTRL_CLKSEL_MASK; + } else { + status = status_clk_src_invalid; + } + } + break; + case CLK_SRC_GROUP_PMIC: + status = status_clk_fixed; + break; + case CLK_SRC_GROUP_AHB: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_AXI: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_CPU0: + if (node_or_instance == clock_node_cpu0) { + /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency + * changes, the AXI and AHB clock changes accordingly, here the driver ensures the + * AXI and AHB bus clock frequency is in valid range. + */ + uint32_t expected_freq = get_frequency_for_source(src) / div; + uint32_t axi_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; + uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, src, div, axi_sub_div, ahb_sub_div); + } else { + status = status_clk_shared_cpu0; + } + break; + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; + break; + default: + status = status_clk_src_invalid; + break; + } + + return status; +} + +void switch_ip_clock(clock_name_t clock_name, bool on) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + uint32_t mode = on ? 1UL : 2UL; + HPM_SYSCTL->RESOURCE[resource] = + (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + } +} + + +void clock_enable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_ON); +} + +void clock_disable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_OFF); +} + +void clock_add_to_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); + } else if (resource == RESOURCE_SHARED_PTPC) { + sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, true); + } +} + +void clock_remove_from_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); + } else if (resource == RESOURCE_SHARED_PTPC) { + sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, false); + } +} + +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 2U) { + HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); + } +} + +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 2U) { + HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); + } +} + + +static uint64_t get_core_mcycle(void) +{ + uint64_t result; + uint32_t resultl_first = read_csr(CSR_CYCLE); + uint32_t resulth = read_csr(CSR_CYCLEH); + uint32_t resultl_second = read_csr(CSR_CYCLE); + if (resultl_first < resultl_second) { + result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ + } else { + resulth = read_csr(CSR_MCYCLEH); + result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ + } + return result; + } + +void clock_cpu_delay_us(uint32_t us) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = get_core_mcycle() + ticks_per_us * us; + while (get_core_mcycle() < expected_ticks) { + } +} + +void clock_cpu_delay_ms(uint32_t ms) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (get_core_mcycle() < expected_ticks) { + } +} + +void clock_update_core_clock(void) +{ + hpm_core_clock = clock_get_frequency(clock_cpu0); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h new file mode 100644 index 0000000000..9841dac595 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CLOCK_DRV_H +#define HPM_CLOCK_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_drv.h" + + +/** + * @brief Error codes for clock driver + */ +enum { + status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), + status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), + status_clk_invalid = MAKE_STATUS(status_group_clk, 2), + status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), + status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), + status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), + status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), + status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), + status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), + status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), + status_clk_fixed = MAKE_STATUS(status_group_clk, 10), + +}; + + + +/** + * @brief Clock source group definitions + */ +#define CLK_SRC_GROUP_COMMON (0U) +#define CLK_SRC_GROUP_ADC (1U) +#define CLK_SRC_GROUP_I2S (2U) +#define CLK_SRC_GROUP_WDG (3U) +#define CLK_SRC_GROUP_PMIC (4U) +#define CLK_SRC_GROUP_AHB (5U) +#define CLK_SRC_GROUP_AXI (6U) +#define CLK_SRC_GROUP_DAC (7U) +#define CLK_SRC_GROUP_CPU0 (9U) +#define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_INVALID (15U) + +#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) +#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) +#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) + +/** + * @brief Clock source definitions + */ +typedef enum _clock_sources { + clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), + clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), + clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), + clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), + clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), + clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), + clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), + clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), + clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), + + clk_adc_src_ana = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ahb = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + + clk_dac_src_ana = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), + clk_dac_src_ahb = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), + + clk_i2s_src_aud0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), + clk_i2s_src_aud1 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 1), + + clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), + clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), +} clk_src_t; + + +#define RESOURCE_INVALID (0xFFFFU) +#define RESOURCE_SHARED_PTPC (0xFFFEU) +#define RESOURCE_SHARED_CPU0 (0xFFFDU) + +#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) + +/* Clock NAME related Macros */ +#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)node)) +#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) +#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) +#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) + +/** + * @brief Peripheral Clock Type Description + */ +typedef enum _clock_name { + clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), + clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), + clock_dram = MAKE_CLOCK_NAME(sysctl_resource_dram, CLK_SRC_GROUP_COMMON, clock_node_dram), + clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), + clock_xpi1 = MAKE_CLOCK_NAME(sysctl_resource_xpi1, CLK_SRC_GROUP_COMMON, clock_node_xpi1), + clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), + clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), + clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), + clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), + clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), + clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), + clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), + clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), + clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), + clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), + clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), + clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), + clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), + clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), + clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), + clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), + clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), + clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), + clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), + clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), + clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), + clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), + clock_sdxc0 = MAKE_CLOCK_NAME(sysctl_resource_sdxc0, CLK_SRC_GROUP_COMMON, clock_node_sdxc0), + clock_ntmr0 = MAKE_CLOCK_NAME(sysctl_resource_ntmr0, CLK_SRC_GROUP_COMMON, clock_node_ntmr0), + clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), + clock_axi = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AXI, clock_node_axi), + clock_axic = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_AXI, clock_node_axi), + clock_axis = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_AXI, clock_node_axi), + clock_ahbp = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_AHB, clock_node_ahb), + + clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), + clock_ptp0 = MAKE_CLOCK_NAME(RESOURCE_SHARED_PTPC, CLK_SRC_GROUP_COMMON, clock_node_ptp0), + clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), + clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), + clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), + clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), + clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), + clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI, 2), + clock_ram0 = MAKE_CLOCK_NAME(sysctl_resource_ram0, CLK_SRC_GROUP_AXI, 3), + clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI, 4), + clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 0), + clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 1), + clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 2), + clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AHB, 4), + clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 5), + clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 6), + clock_mot1 = MAKE_CLOCK_NAME(sysctl_resource_mot1, CLK_SRC_GROUP_AHB, 7), + clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), + clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_i2spdm0, CLK_SRC_GROUP_AHB, 11), + clock_dao = MAKE_CLOCK_NAME(sysctl_resource_i2sdao, CLK_SRC_GROUP_AHB, 12), + clock_msyn = MAKE_CLOCK_NAME(sysctl_resource_msyn, CLK_SRC_GROUP_AHB, 13), + clock_ffa0 = MAKE_CLOCK_NAME(sysctl_resource_ffa0, CLK_SRC_GROUP_AHB, 14), + clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), + clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_CPU0, 0), + + + /* For ADC, there are 2-stage clock source and divider configurations */ + clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), + clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), + clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), + clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), + clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), + clock_adc2 = MAKE_CLOCK_NAME(sysctl_resource_adc2, CLK_SRC_GROUP_ADC, 2), + + /* For DAC, there are 2-stage clock source and divider configurations */ + clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), + clock_dac0 = MAKE_CLOCK_NAME(sysctl_resource_dac0, CLK_SRC_GROUP_DAC, 0), + + /* For I2S, there are 2-stage clock source and divider configurations */ + clock_aud0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud0), + clock_aud1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud1), + clock_i2s0 = MAKE_CLOCK_NAME(sysctl_resource_i2s0, CLK_SRC_GROUP_I2S, 0), + clock_i2s1 = MAKE_CLOCK_NAME(sysctl_resource_i2s1, CLK_SRC_GROUP_I2S, 1), + + /* Clock sources */ + clk_osc0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 1), + clk_pll0clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 2), + clk_pll0clk2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 3), + clk_pll1clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 4), + clk_pll1clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 5), + clk_pll2clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 6), + clk_pll2clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 7), +} clock_name_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get specified IP frequency + * @param[in] clock_name IP clock name + * + * @return IP clock frequency in Hz + */ +uint32_t clock_get_frequency(clock_name_t clock_name); + + +/** + * @brief Get Clock frequency for selected clock source + * @param [in] source clock source + * @return clock frequency for selected clock source + */ +uint32_t get_frequency_for_source(clock_source_t source); + +/** + * @brief Get the IP clock source + * Note: This API return the direct clock source + * @param [in] clock_name clock name + * @return IP clock source + */ +clk_src_t clock_get_source(clock_name_t clock_name); + +/** + * @brief Set ADC clock source + * @param[in] clock_name ADC clock name + * @param[in] src ADC clock source + * + * @return #status_success Setting ADC clock source is successful + * #status_clk_invalid Invalid ADC clock + * #status_clk_src_invalid Invalid ADC clock source + */ +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set DAC clock source + * @param[in] clock_name DAC clock name + * @param[in] src DAC clock source + * + * @return #status_success Setting DAC clock source is successful + * #status_clk_invalid Invalid DAC clock + * #status_clk_src_invalid Invalid DAC clock source + */ +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set I2S clock source + * @param[in] clock_name I2S clock name + * @param[in] src I2S clock source + * + * @return #status_success Setting I2S clock source is successful + * #status_clk_invalid Invalid I2S clock + * #status_clk_src_invalid Invalid I2S clock source + */ +hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set the IP clock source and divider + * @param[in] clock_name clock name + * @param[in] src clock source + * @param[in] div clock divider, valid range (1 - 256) + * + * @return #status_success Setting Clock source and divider is successful. + * #status_clk_src_invalid clock source is invalid. + * #status_clk_fixed clock source and divider is a fixed value + * #status_clk_shared_ahb Clock is shared with the AHB clock + * #status_clk_shared_axi0 Clock is shared with the AXI0 clock + * #status_clk_shared_axi1 CLock is shared with the AXI1 clock + * #status_clk_shared_axi2 Clock is shared with the AXI2 clock + * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock + * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock + */ +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); + +/** + * @brief Enable IP clock + * @param[in] clock_name IP clock name + */ +void clock_enable(clock_name_t clock_name); + +/** + * @brief Disable IP clock + * @param[in] clock_name IP clock name + */ +void clock_disable(clock_name_t clock_name); + +/** + * @brief Add IP to specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_add_to_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Remove IP from specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ +void clock_cpu_delay_us(uint32_t us); + +/** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ +void clock_cpu_delay_ms(uint32_t ms); + +/** + * @brief Update the Core clock frequency + */ +void clock_update_core_clock(void); + +/** + * @brief HPM Core clock variable + */ +extern uint32_t hpm_core_clock; + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h new file mode 100644 index 0000000000..72f6fb746f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h @@ -0,0 +1,6512 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CSR_H +#define HPM_CSR_H + +/* STANDARD CRS address definition */ +#define CSR_USTATUS (0x0) +#define CSR_UIE (0x4) +#define CSR_UTVEC (0x5) +#define CSR_USCRATCH (0x40) +#define CSR_UEPC (0x41) +#define CSR_UCAUSE (0x42) +#define CSR_UTVAL (0x43) +#define CSR_UIP (0x44) +#define CSR_SSTATUS (0x100) +#define CSR_SEDELEG (0x102) +#define CSR_SIDELEG (0x103) +#define CSR_SIE (0x104) +#define CSR_STVEC (0x105) +#define CSR_SSCRATCH (0x140) +#define CSR_SEPC (0x141) +#define CSR_SCAUSE (0x142) +#define CSR_STVAL (0x143) +#define CSR_SIP (0x144) +#define CSR_SATP (0x180) +#define CSR_MSTATUS (0x300) +#define CSR_MISA (0x301) +#define CSR_MEDELEG (0x302) +#define CSR_MIDELEG (0x303) +#define CSR_MIE (0x304) +#define CSR_MTVEC (0x305) +#define CSR_MCOUNTEREN (0x306) +#define CSR_MHPMEVENT3 (0x323) +#define CSR_MHPMEVENT4 (0x324) +#define CSR_MHPMEVENT5 (0x325) +#define CSR_MHPMEVENT6 (0x326) +#define CSR_MSCRATCH (0x340) +#define CSR_MEPC (0x341) +#define CSR_MCAUSE (0x342) +#define CSR_MTVAL (0x343) +#define CSR_MIP (0x344) +#define CSR_PMPCFG0 (0x3A0) +#define CSR_PMPCFG1 (0x3A1) +#define CSR_PMPCFG2 (0x3A2) +#define CSR_PMPCFG3 (0x3A3) +#define CSR_PMPADDR0 (0x3B0) +#define CSR_PMPADDR1 (0x3B1) +#define CSR_PMPADDR2 (0x3B2) +#define CSR_PMPADDR3 (0x3B3) +#define CSR_PMPADDR4 (0x3B4) +#define CSR_PMPADDR5 (0x3B5) +#define CSR_PMPADDR6 (0x3B6) +#define CSR_PMPADDR7 (0x3B7) +#define CSR_PMPADDR8 (0x3B8) +#define CSR_PMPADDR9 (0x3B9) +#define CSR_PMPADDR10 (0x3BA) +#define CSR_PMPADDR11 (0x3BB) +#define CSR_PMPADDR12 (0x3BC) +#define CSR_PMPADDR13 (0x3BD) +#define CSR_PMPADDR14 (0x3BE) +#define CSR_PMPADDR15 (0x3BF) +#define CSR_TSELECT (0x7A0) +#define CSR_TDATA1 (0x7A1) +#define CSR_MCONTROL (0x7A1) +#define CSR_ICOUNT (0x7A1) +#define CSR_ITRIGGER (0x7A1) +#define CSR_ETRIGGER (0x7A1) +#define CSR_TDATA2 (0x7A2) +#define CSR_TDATA3 (0x7A3) +#define CSR_TEXTRA (0x7A3) +#define CSR_TINFO (0x7A4) +#define CSR_TCONTROL (0x7A5) +#define CSR_MCONTEXT (0x7A8) +#define CSR_SCONTEXT (0x7AA) +#define CSR_DCSR (0x7B0) +#define CSR_DPC (0x7B1) +#define CSR_DSCRATCH0 (0x7B2) +#define CSR_DSCRATCH1 (0x7B3) +#define CSR_MCYCLE (0xB00) +#define CSR_MINSTRET (0xB02) +#define CSR_MHPMCOUNTER3 (0xB03) +#define CSR_MHPMCOUNTER4 (0xB04) +#define CSR_MHPMCOUNTER5 (0xB05) +#define CSR_MHPMCOUNTER6 (0xB06) +#define CSR_MCYCLEH (0xB80) +#define CSR_MINSTRETH (0xB82) +#define CSR_MHPMCOUNTER3H (0xB83) +#define CSR_MHPMCOUNTER4H (0xB84) +#define CSR_MHPMCOUNTER5H (0xB85) +#define CSR_MHPMCOUNTER6H (0xB86) +#define CSR_PMACFG0 (0xBC0) +#define CSR_PMACFG1 (0xBC1) +#define CSR_PMACFG2 (0xBC2) +#define CSR_PMACFG3 (0xBC3) +#define CSR_PMAADDR0 (0xBD0) +#define CSR_PMAADDR1 (0xBD1) +#define CSR_PMAADDR2 (0xBD2) +#define CSR_PMAADDR3 (0xBD3) +#define CSR_PMAADDR4 (0xBD4) +#define CSR_PMAADDR5 (0xBD5) +#define CSR_PMAADDR6 (0xBD6) +#define CSR_PMAADDR7 (0xBD7) +#define CSR_PMAADDR8 (0xBD8) +#define CSR_PMAADDR9 (0xBD9) +#define CSR_PMAADDR10 (0xBDA) +#define CSR_PMAADDR11 (0xBDB) +#define CSR_PMAADDR12 (0xBDC) +#define CSR_PMAADDR13 (0xBDD) +#define CSR_PMAADDR14 (0xBDE) +#define CSR_PMAADDR15 (0xBDF) +#define CSR_CYCLE (0xC00) +#define CSR_CYCLEH (0xC80) +#define CSR_MVENDORID (0xF11) +#define CSR_MARCHID (0xF12) +#define CSR_MIMPID (0xF13) +#define CSR_MHARTID (0xF14) + +/* NON-STANDARD CRS address definition */ +#define CSR_SCOUNTEREN (0x106) +#define CSR_MCOUNTINHIBIT (0x320) +#define CSR_MILMB (0x7C0) +#define CSR_MDLMB (0x7C1) +#define CSR_MECC_CODE (0x7C2) +#define CSR_MNVEC (0x7C3) +#define CSR_MXSTATUS (0x7C4) +#define CSR_MPFT_CTL (0x7C5) +#define CSR_MHSP_CTL (0x7C6) +#define CSR_MSP_BOUND (0x7C7) +#define CSR_MSP_BASE (0x7C8) +#define CSR_MDCAUSE (0x7C9) +#define CSR_MCACHE_CTL (0x7CA) +#define CSR_MCCTLBEGINADDR (0x7CB) +#define CSR_MCCTLCOMMAND (0x7CC) +#define CSR_MCCTLDATA (0x7CD) +#define CSR_MCOUNTERWEN (0x7CE) +#define CSR_MCOUNTERINTEN (0x7CF) +#define CSR_MMISC_CTL (0x7D0) +#define CSR_MCOUNTERMASK_M (0x7D1) +#define CSR_MCOUNTERMASK_S (0x7D2) +#define CSR_MCOUNTERMASK_U (0x7D3) +#define CSR_MCOUNTEROVF (0x7D4) +#define CSR_MSLIDELEG (0x7D5) +#define CSR_MCLK_CTL (0x7DF) +#define CSR_DEXC2DBG (0x7E0) +#define CSR_DDCAUSE (0x7E1) +#define CSR_UITB (0x800) +#define CSR_UCODE (0x801) +#define CSR_UDCAUSE (0x809) +#define CSR_UCCTLBEGINADDR (0x80B) +#define CSR_UCCTLCOMMAND (0x80C) +#define CSR_SLIE (0x9C4) +#define CSR_SLIP (0x9C5) +#define CSR_SDCAUSE (0x9C9) +#define CSR_SCCTLDATA (0x9CD) +#define CSR_SCOUNTERINTEN (0x9CF) +#define CSR_SCOUNTERMASK_M (0x9D1) +#define CSR_SCOUNTERMASK_S (0x9D2) +#define CSR_SCOUNTERMASK_U (0x9D3) +#define CSR_SCOUNTEROVF (0x9D4) +#define CSR_SCOUNTINHIBIT (0x9E0) +#define CSR_SHPMEVENT3 (0x9E3) +#define CSR_SHPMEVENT4 (0x9E4) +#define CSR_SHPMEVENT5 (0x9E5) +#define CSR_SHPMEVENT6 (0x9E6) +#define CSR_MICM_CFG (0xFC0) +#define CSR_MDCM_CFG (0xFC1) +#define CSR_MMSC_CFG (0xFC2) +#define CSR_MMSC_CFG2 (0xFC3) + +/* STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: USTATUS */ +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_USTATUS_UPIE_MASK (0x10U) +#define CSR_USTATUS_UPIE_SHIFT (4U) +#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) +#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_USTATUS_UIE_MASK (0x1U) +#define CSR_USTATUS_UIE_SHIFT (0U) +#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) +#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) + +/* Bitfield definition for register: UIE */ +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UEIE_MASK (0x100U) +#define CSR_UIE_UEIE_SHIFT (8U) +#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) +#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UTIE_MASK (0x10U) +#define CSR_UIE_UTIE_SHIFT (4U) +#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) +#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_USIE_MASK (0x1U) +#define CSR_UIE_USIE_SHIFT (0U) +#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) +#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) + +/* Bitfield definition for register: UTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_UTVEC_BASE_31_2_SHIFT (2U) +#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) +#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: USCRATCH */ +/* + * USCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_USCRATCH_USCRATCH_SHIFT (0U) +#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) +#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) + +/* Bitfield definition for register: UEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_UEPC_EPC_SHIFT (1U) +#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) +#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) + +/* Bitfield definition for register: UCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) +#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 4:User timer interrupt + * 8:User external interrupt + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9-11:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32：Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) +#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: UTVAL */ +/* + * UTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) +#define CSR_UTVAL_UTVAL_SHIFT (0U) +#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) +#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) + +/* Bitfield definition for register: UIP */ +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UEIP_MASK (0x100U) +#define CSR_UIP_UEIP_SHIFT (8U) +#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) +#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UTIP_MASK (0x10U) +#define CSR_UIP_UTIP_SHIFT (4U) +#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) +#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_USIP_MASK (0x1U) +#define CSR_UIP_USIP_SHIFT (0U) +#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) +#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) + +/* Bitfield definition for register: SSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_SSTATUS_SD_MASK (0x80000000UL) +#define CSR_SSTATUS_SD_SHIFT (31U) +#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_SSTATUS_MXR_MASK (0x80000UL) +#define CSR_SSTATUS_MXR_SHIFT (19U) +#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) +#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_SSTATUS_SUM_MASK (0x40000UL) +#define CSR_SSTATUS_SUM_SHIFT (18U) +#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) +#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggeredwhen XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. + * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_XS_MASK (0x18000UL) +#define CSR_SSTATUS_XS_SHIFT (15U) +#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. + * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_FS_MASK (0x6000U) +#define CSR_SSTATUS_FS_SHIFT (13U) +#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) +#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_SSTATUS_SPP_MASK (0x100U) +#define CSR_SSTATUS_SPP_SHIFT (8U) +#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) +#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_SSTATUS_SPIE_MASK (0x20U) +#define CSR_SSTATUS_SPIE_SHIFT (5U) +#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) +#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_SSTATUS_UPIE_MASK (0x10U) +#define CSR_SSTATUS_UPIE_SHIFT (4U) +#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) +#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_SIE_MASK (0x2U) +#define CSR_SSTATUS_SIE_SHIFT (1U) +#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) +#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_UIE_MASK (0x1U) +#define CSR_SSTATUS_UIE_SHIFT (0U) +#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) +#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: SEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SPF_MASK (0x8000U) +#define CSR_SEDELEG_SPF_SHIFT (15U) +#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) +#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LPF_MASK (0x2000U) +#define CSR_SEDELEG_LPF_SHIFT (13U) +#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) +#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IPF_MASK (0x1000U) +#define CSR_SEDELEG_IPF_SHIFT (12U) +#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) +#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_UEC_MASK (0x100U) +#define CSR_SEDELEG_UEC_SHIFT (8U) +#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) +#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAF_MASK (0x80U) +#define CSR_SEDELEG_SAF_SHIFT (7U) +#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) +#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAM_MASK (0x40U) +#define CSR_SEDELEG_SAM_SHIFT (6U) +#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) +#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAF_MASK (0x20U) +#define CSR_SEDELEG_LAF_SHIFT (5U) +#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) +#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAM_MASK (0x10U) +#define CSR_SEDELEG_LAM_SHIFT (4U) +#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) +#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) + +/* + * B (RW) + * + * B indicates whether an exception triggered by breakpoint will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_B_MASK (0x8U) +#define CSR_SEDELEG_B_SHIFT (3U) +#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) +#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_II_MASK (0x4U) +#define CSR_SEDELEG_II_SHIFT (2U) +#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) +#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAF_MASK (0x2U) +#define CSR_SEDELEG_IAF_SHIFT (1U) +#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) +#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAM_MASK (0x1U) +#define CSR_SEDELEG_IAM_SHIFT (0U) +#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) +#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: SIDELEG */ +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UEI_MASK (0x100U) +#define CSR_SIDELEG_UEI_SHIFT (8U) +#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) +#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UTI_MASK (0x10U) +#define CSR_SIDELEG_UTI_SHIFT (4U) +#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) +#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_USI_MASK (0x1U) +#define CSR_SIDELEG_USI_SHIFT (0U) +#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) +#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) + +/* Bitfield definition for register: SIE */ +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SEIE_MASK (0x200U) +#define CSR_SIE_SEIE_SHIFT (9U) +#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) +#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UEIE_MASK (0x100U) +#define CSR_SIE_UEIE_SHIFT (8U) +#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) +#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_STIE_MASK (0x20U) +#define CSR_SIE_STIE_SHIFT (5U) +#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) +#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UTIE_MASK (0x10U) +#define CSR_SIE_UTIE_SHIFT (4U) +#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) +#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SSIE_MASK (0x2U) +#define CSR_SIE_SSIE_SHIFT (1U) +#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) +#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_USIE_MASK (0x1U) +#define CSR_SIE_USIE_SHIFT (0U) +#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) +#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) + +/* Bitfield definition for register: STVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_STVEC_BASE_31_2_SHIFT (2U) +#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) +#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: SSCRATCH */ +/* + * SSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) +#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) +#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) + +/* Bitfield definition for register: SEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_SEPC_EPC_SHIFT (1U) +#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) +#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) + +/* Bitfield definition for register: SCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) +#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 256+16:Slave port ECC error interrupt (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt(S-mode) + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:10:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) +#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: STVAL */ +/* + * STVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) +#define CSR_STVAL_STVAL_SHIFT (0U) +#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) +#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) + +/* Bitfield definition for register: SIP */ +/* + * SEIP (RO) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SEIP_MASK (0x200U) +#define CSR_SIP_SEIP_SHIFT (9U) +#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UEIP_MASK (0x100U) +#define CSR_SIP_UEIP_SHIFT (8U) +#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) +#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) + +/* + * STIP (RO) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_STIP_MASK (0x20U) +#define CSR_SIP_STIP_SHIFT (5U) +#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) + +/* + * UTIP (RO) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UTIP_MASK (0x10U) +#define CSR_SIP_UTIP_SHIFT (4U) +#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SSIP_MASK (0x2U) +#define CSR_SIP_SSIP_SHIFT (1U) +#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) +#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_USIP_MASK (0x1U) +#define CSR_SIP_USIP_SHIFT (0U) +#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) +#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) + +/* Bitfield definition for register: SATP */ +/* + * MODE (RW) + * + * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is + * not supported in the product, this CSR will be + * hardwired to 0. + * 0:No page translation + * 1:Page-based 32-bit virtual addressing + */ +#define CSR_SATP_MODE_MASK (0x80000000UL) +#define CSR_SATP_MODE_SHIFT (31U) +#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) +#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) + +/* + * ASID (RW) + * + * ASID holds the address space identifier. + */ +#define CSR_SATP_ASID_MASK (0x7FC00000UL) +#define CSR_SATP_ASID_SHIFT (22U) +#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) +#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) + +/* + * PPN (RW) + * + * PPN holds the physical page number of the root page table. + */ +#define CSR_SATP_PPN_MASK (0x3FFFFFUL) +#define CSR_SATP_PPN_SHIFT (0U) +#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) +#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) + +/* Bitfield definition for register: MSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_MSTATUS_SD_MASK (0x80000000UL) +#define CSR_MSTATUS_SD_SHIFT (31U) +#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) + +/* + * TSR (RW) + * + * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TSR_MASK (0x400000UL) +#define CSR_MSTATUS_TSR_SHIFT (22U) +#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) +#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) + +/* + * TW (RW) + * + * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TW_MASK (0x200000UL) +#define CSR_MSTATUS_TW_SHIFT (21U) +#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) +#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) + +/* + * TVM (RW) + * + * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. + * 0:Normal execution + * 1:Raising exceptions + */ +#define CSR_MSTATUS_TVM_MASK (0x100000UL) +#define CSR_MSTATUS_TVM_SHIFT (20U) +#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) +#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_MSTATUS_MXR_MASK (0x80000UL) +#define CSR_MSTATUS_MXR_SHIFT (19U) +#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) +#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_MSTATUS_SUM_MASK (0x40000UL) +#define CSR_MSTATUS_SUM_SHIFT (18U) +#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) +#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) + +/* + * MPRV (RW) + * + * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. + */ +#define CSR_MSTATUS_MPRV_MASK (0x20000UL) +#define CSR_MSTATUS_MPRV_SHIFT (17U) +#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) +#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggered when XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_XS_MASK (0x18000UL) +#define CSR_MSTATUS_XS_SHIFT (15U) +#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state + * managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_FS_MASK (0x6000U) +#define CSR_MSTATUS_FS_SHIFT (13U) +#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) +#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) + +/* + * MPP (RW) + * + * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. + */ +#define CSR_MSTATUS_MPP_MASK (0x1800U) +#define CSR_MSTATUS_MPP_SHIFT (11U) +#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) +#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_MSTATUS_SPP_MASK (0x100U) +#define CSR_MSTATUS_SPP_SHIFT (8U) +#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) +#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) + +/* + * MPIE (RW) + * + * MPIE holds the value of the MIE bit prior to a trap. + */ +#define CSR_MSTATUS_MPIE_MASK (0x80U) +#define CSR_MSTATUS_MPIE_SHIFT (7U) +#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) +#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_MSTATUS_SPIE_MASK (0x20U) +#define CSR_MSTATUS_SPIE_SHIFT (5U) +#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) +#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_MSTATUS_UPIE_MASK (0x10U) +#define CSR_MSTATUS_UPIE_SHIFT (4U) +#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) +#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) + +/* + * MIE (RW) + * + * M mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_MIE_MASK (0x8U) +#define CSR_MSTATUS_MIE_SHIFT (3U) +#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) +#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_SIE_MASK (0x2U) +#define CSR_MSTATUS_SIE_SHIFT (1U) +#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) +#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_UIE_MASK (0x1U) +#define CSR_MSTATUS_UIE_SHIFT (0U) +#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) +#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: MISA */ +/* + * BASE (RO) + * + * The general-purpose register width of the native base integer ISA. + * 0:Reserved + * 1:32 + * 2:64 + * 3:128 + */ +#define CSR_MISA_BASE_MASK (0xC0000000UL) +#define CSR_MISA_BASE_SHIFT (30U) +#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) + +/* + * Z (RO) + * + * Reserved + */ +#define CSR_MISA_Z_MASK (0x2000000UL) +#define CSR_MISA_Z_SHIFT (25U) +#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) + +/* + * Y (RO) + * + * Reserved + */ +#define CSR_MISA_Y_MASK (0x1000000UL) +#define CSR_MISA_Y_SHIFT (24U) +#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) + +/* + * X (RO) + * + * Non-standard extensions present + */ +#define CSR_MISA_X_MASK (0x800000UL) +#define CSR_MISA_X_SHIFT (23U) +#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) + +/* + * W (RO) + * + * Reserved + */ +#define CSR_MISA_W_MASK (0x400000UL) +#define CSR_MISA_W_SHIFT (22U) +#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) + +/* + * V (RO) + * + * Tentatively reserved for Vector extension + */ +#define CSR_MISA_V_MASK (0x200000UL) +#define CSR_MISA_V_SHIFT (21U) +#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) + +/* + * U (RO) + * + * User mode implemented + * 0:Machine + * 1:Machine + User / Machine + Supervisor + User + */ +#define CSR_MISA_U_MASK (0x100000UL) +#define CSR_MISA_U_SHIFT (20U) +#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) + +/* + * T (RO) + * + * Tentatively reserved for Transactional Memory extension + */ +#define CSR_MISA_T_MASK (0x80000UL) +#define CSR_MISA_T_SHIFT (19U) +#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) + +/* + * S (RO) + * + * Supervisor mode implemented + * 0:Machine / Machine + User + * 1:Machine + Supervisor + User + */ +#define CSR_MISA_S_MASK (0x40000UL) +#define CSR_MISA_S_SHIFT (18U) +#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) + +/* + * R (RO) + * + * Reserved + */ +#define CSR_MISA_R_MASK (0x20000UL) +#define CSR_MISA_R_SHIFT (17U) +#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) + +/* + * Q (RO) + * + * Quad-precision floating-point extension + */ +#define CSR_MISA_Q_MASK (0x10000UL) +#define CSR_MISA_Q_SHIFT (16U) +#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) + +/* + * P (RO) + * + * Tentatively reserved for Packed-SIMD extension + */ +#define CSR_MISA_P_MASK (0x8000U) +#define CSR_MISA_P_SHIFT (15U) +#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) + +/* + * O (RO) + * + * Reserved + */ +#define CSR_MISA_O_MASK (0x4000U) +#define CSR_MISA_O_SHIFT (14U) +#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) + +/* + * N (RO) + * + * User-level interrupts supported + * 0:no + * 1:yes + */ +#define CSR_MISA_N_MASK (0x2000U) +#define CSR_MISA_N_SHIFT (13U) +#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) + +/* + * M (RO) + * + * Integer Multiply/Divide extension + */ +#define CSR_MISA_M_MASK (0x1000U) +#define CSR_MISA_M_SHIFT (12U) +#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) + +/* + * L (RO) + * + * Tentatively reserved for Decimal Floating-Point extension + */ +#define CSR_MISA_L_MASK (0x800U) +#define CSR_MISA_L_SHIFT (11U) +#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) + +/* + * K (RO) + * + * Reserved + */ +#define CSR_MISA_K_MASK (0x400U) +#define CSR_MISA_K_SHIFT (10U) +#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) + +/* + * J (RO) + * + * Tentatively reserved for Dynamically Translated Languages extension + */ +#define CSR_MISA_J_MASK (0x200U) +#define CSR_MISA_J_SHIFT (9U) +#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) + +/* + * I (RO) + * + * RV32I/64I/128I base ISA + */ +#define CSR_MISA_I_MASK (0x100U) +#define CSR_MISA_I_SHIFT (8U) +#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) + +/* + * H (RO) + * + * Reserved + */ +#define CSR_MISA_H_MASK (0x80U) +#define CSR_MISA_H_SHIFT (7U) +#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) + +/* + * G (RO) + * + * Additional standard extensions present + */ +#define CSR_MISA_G_MASK (0x40U) +#define CSR_MISA_G_SHIFT (6U) +#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) + +/* + * F (RO) + * + * Single-precision floating-point extension + * 0:none + * 1:double+single precision / single precision + */ +#define CSR_MISA_F_MASK (0x20U) +#define CSR_MISA_F_SHIFT (5U) +#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) + +/* + * E (RO) + * + * RV32E base ISA + */ +#define CSR_MISA_E_MASK (0x10U) +#define CSR_MISA_E_SHIFT (4U) +#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) + +/* + * D (RO) + * + * Double-precision floating-point extension + * 0:single precision / none + * 1:double+single precision + */ +#define CSR_MISA_D_MASK (0x8U) +#define CSR_MISA_D_SHIFT (3U) +#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) + +/* + * C (RO) + * + * Compressed extension + */ +#define CSR_MISA_C_MASK (0x4U) +#define CSR_MISA_C_SHIFT (2U) +#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) + +/* + * B (RO) + * + * Tentatively reserved for Bit operations extension + */ +#define CSR_MISA_B_MASK (0x2U) +#define CSR_MISA_B_SHIFT (1U) +#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) + +/* + * A (RO) + * + * Atomic extension + * 0:no + * 1:yes + */ +#define CSR_MISA_A_MASK (0x1U) +#define CSR_MISA_A_SHIFT (0U) +#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) + +/* Bitfield definition for register: MEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SPF_MASK (0x8000U) +#define CSR_MEDELEG_SPF_SHIFT (15U) +#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) +#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LPF_MASK (0x2000U) +#define CSR_MEDELEG_LPF_SHIFT (13U) +#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) +#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IPF_MASK (0x1000U) +#define CSR_MEDELEG_IPF_SHIFT (12U) +#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) +#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) + +/* + * SEC (RW) + * + * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SEC_MASK (0x200U) +#define CSR_MEDELEG_SEC_SHIFT (9U) +#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) +#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_UEC_MASK (0x100U) +#define CSR_MEDELEG_UEC_SHIFT (8U) +#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) +#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAF_MASK (0x80U) +#define CSR_MEDELEG_SAF_SHIFT (7U) +#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) +#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAM_MASK (0x40U) +#define CSR_MEDELEG_SAM_SHIFT (6U) +#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) +#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAF_MASK (0x20U) +#define CSR_MEDELEG_LAF_SHIFT (5U) +#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) +#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAM_MASK (0x10U) +#define CSR_MEDELEG_LAM_SHIFT (4U) +#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) +#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_II_MASK (0x4U) +#define CSR_MEDELEG_II_SHIFT (2U) +#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) +#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAF_MASK (0x2U) +#define CSR_MEDELEG_IAF_SHIFT (1U) +#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) +#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAM_MASK (0x1U) +#define CSR_MEDELEG_IAM_SHIFT (0U) +#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) +#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: MIDELEG */ +/* + * SEI (RW) + * + * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SEI_MASK (0x200U) +#define CSR_MIDELEG_SEI_SHIFT (9U) +#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) +#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) + +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UEI_MASK (0x100U) +#define CSR_MIDELEG_UEI_SHIFT (8U) +#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) +#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) + +/* + * STI (RW) + * + * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_STI_MASK (0x20U) +#define CSR_MIDELEG_STI_SHIFT (5U) +#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) +#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UTI_MASK (0x10U) +#define CSR_MIDELEG_UTI_SHIFT (4U) +#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) +#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) + +/* + * SSI (RW) + * + * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SSI_MASK (0x2U) +#define CSR_MIDELEG_SSI_SHIFT (1U) +#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) +#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_USI_MASK (0x1U) +#define CSR_MIDELEG_USI_SHIFT (0U) +#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) +#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) + +/* Bitfield definition for register: MIE */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_PMOVI_MASK (0x40000UL) +#define CSR_MIE_PMOVI_SHIFT (18U) +#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) +#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_BWEI_MASK (0x20000UL) +#define CSR_MIE_BWEI_SHIFT (17U) +#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) +#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_IMECCI_MASK (0x10000UL) +#define CSR_MIE_IMECCI_SHIFT (16U) +#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) +#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) + +/* + * MEIE (RW) + * + * M mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MEIE_MASK (0x800U) +#define CSR_MIE_MEIE_SHIFT (11U) +#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) +#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) + +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SEIE_MASK (0x200U) +#define CSR_MIE_SEIE_SHIFT (9U) +#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) +#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UEIE_MASK (0x100U) +#define CSR_MIE_UEIE_SHIFT (8U) +#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) +#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) + +/* + * MTIE (RW) + * + * M mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MTIE_MASK (0x80U) +#define CSR_MIE_MTIE_SHIFT (7U) +#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) +#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_STIE_MASK (0x20U) +#define CSR_MIE_STIE_SHIFT (5U) +#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) +#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UTIE_MASK (0x10U) +#define CSR_MIE_UTIE_SHIFT (4U) +#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) +#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) + +/* + * MSIE (RW) + * + * M mode software interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MSIE_MASK (0x8U) +#define CSR_MIE_MSIE_SHIFT (3U) +#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) +#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SSIE_MASK (0x2U) +#define CSR_MIE_SSIE_SHIFT (1U) +#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) +#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_USIE_MASK (0x1U) +#define CSR_MIE_USIE_SHIFT (0U) +#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) +#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) + +/* Bitfield definition for register: MTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode + */ +#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_MTVEC_BASE_31_2_SHIFT (2U) +#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) +#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: MCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) +#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) +#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) +#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) +#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_IR_MASK (0x4U) +#define CSR_MCOUNTEREN_IR_SHIFT (2U) +#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) +#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_TM_MASK (0x2U) +#define CSR_MCOUNTEREN_TM_SHIFT (1U) +#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) +#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_CY_MASK (0x1U) +#define CSR_MCOUNTEREN_CY_SHIFT (0U) +#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) +#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT3_SEL_SHIFT (4U) +#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) +#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) +#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT4_SEL_SHIFT (4U) +#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) +#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) +#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT5_SEL_SHIFT (4U) +#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) +#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) +#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT6_SEL_SHIFT (4U) +#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) +#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) +#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MSCRATCH */ +/* + * MSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) +#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) +#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) + +/* Bitfield definition for register: MEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_MEPC_EPC_SHIFT (1U) +#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) +#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) + +/* Bitfield definition for register: MCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt + */ +#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) +#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception code + * When interrupt is 1, the value means: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 3:Machine software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 7:Machine timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 11:Machine external interrupt + * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) + * 17:Bus read/write transaction error interrupt (M-mode) + * 18:Performance monitor overflow interrupt (M-mode) + * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt (S-mode) + * When interrupt bit is 0, the value means: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:Environment call from M-mode + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) +#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) +#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: MTVAL */ +/* + * MTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) +#define CSR_MTVAL_MTVAL_SHIFT (0U) +#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) +#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) + +/* Bitfield definition for register: MIP */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_PMOVI_MASK (0x40000UL) +#define CSR_MIP_PMOVI_SHIFT (18U) +#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) +#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_BWEI_MASK (0x20000UL) +#define CSR_MIP_BWEI_SHIFT (17U) +#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) +#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_IMECCI_MASK (0x10000UL) +#define CSR_MIP_IMECCI_SHIFT (16U) +#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) +#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) + +/* + * MEIP (RW) + * + * M mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MEIP_MASK (0x800U) +#define CSR_MIP_MEIP_SHIFT (11U) +#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) +#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) + +/* + * SEIP (RW) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SEIP_MASK (0x200U) +#define CSR_MIP_SEIP_SHIFT (9U) +#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) +#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UEIP_MASK (0x100U) +#define CSR_MIP_UEIP_SHIFT (8U) +#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) +#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) + +/* + * MTIP (RW) + * + * M mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MTIP_MASK (0x80U) +#define CSR_MIP_MTIP_SHIFT (7U) +#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) +#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) + +/* + * STIP (RW) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_STIP_MASK (0x20U) +#define CSR_MIP_STIP_SHIFT (5U) +#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) +#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UTIP_MASK (0x10U) +#define CSR_MIP_UTIP_SHIFT (4U) +#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) +#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) + +/* + * MSIP (RW) + * + * M mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MSIP_MASK (0x8U) +#define CSR_MIP_MSIP_SHIFT (3U) +#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) +#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SSIP_MASK (0x2U) +#define CSR_MIP_SSIP_SHIFT (1U) +#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) +#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_USIP_MASK (0x1U) +#define CSR_MIP_USIP_SHIFT (0U) +#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) +#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) + +/* Bitfield definition for register: PMPCFG0 */ +/* + * PMP3CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) +#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) +#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) + +/* + * PMP2CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) +#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) +#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) + +/* + * PMP1CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) +#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) +#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) +#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) + +/* + * PMP0CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) +#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) +#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) +#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG1 */ +/* + * PMP7CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) +#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) +#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) + +/* + * PMP6CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) +#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) +#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) + +/* + * PMP5CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) +#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) +#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) +#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) + +/* + * PMP4CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) +#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) +#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) +#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG2 */ +/* + * PMP11CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) +#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) +#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) + +/* + * PMP10CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) +#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) +#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) + +/* + * PMP9CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) +#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) +#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) +#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) + +/* + * PMP8CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) +#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) +#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) +#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG3 */ +/* + * PMP15CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) +#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) +#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) + +/* + * PMP14CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) +#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) +#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) + +/* + * PMP13CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) +#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) +#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) +#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) + +/* + * PMP12CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) +#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) +#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) +#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaa0 8 + * aaaa. . . aa01 16 + * aaaa. . . a011 32 + * . . . . . . + * aa01. . . 1111 2^{XLEN} + * a011. . . 1111 2^{XLEN+1} + * 0111. . . 1111 2^{XLEN+2} + * 1111. . . 1111 2^{XLEN+3*1} + */ +#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) +#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) +#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) +#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) +#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) +#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) +#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) +#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) +#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) +#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) +#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) +#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) +#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) +#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) +#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) +#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) +#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register: TSELECT */ +/* + * TRIGGER_INDEX (RW) + * + * This register determines which trigger is accessible through other trigger registers. + */ +#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) +#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) +#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) +#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) + +/* Bitfield definition for register: TDATA1 */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + * 3:The selected trigger is an instruction count trigger + * 4:The selected trigger is an interrupt trigger. + * 5:The selected trigger is an exception trigger. + */ +#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) +#define CSR_TDATA1_TYPE_SHIFT (28U) +#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) +#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_TDATA1_DMODE_MASK (0x8000000UL) +#define CSR_TDATA1_DMODE_SHIFT (27U) +#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) +#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) + +/* + * DATA (RW) + * + * Trigger-specific data + */ +#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) +#define CSR_TDATA1_DATA_SHIFT (0U) +#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) +#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) + +/* Bitfield definition for register: MCONTROL */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + */ +#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) +#define CSR_MCONTROL_TYPE_SHIFT (28U) +#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) +#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) +#define CSR_MCONTROL_DMODE_SHIFT (27U) +#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) +#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) + +/* + * MASKMAX (RO) + * + * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. + */ +#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) +#define CSR_MCONTROL_MASKMAX_SHIFT (21U) +#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_MCONTROL_ACTION_MASK (0xF000U) +#define CSR_MCONTROL_ACTION_SHIFT (12U) +#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) +#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) + +/* + * CHAIN (RW) + * + * Setting this field to enable trigger chain. + * 0:When this trigger matches, the configured action is taken. + * 1:While this trigger does not match, it prevents the trigger with the next index from matching. + * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). + * If Number of Triggers is 4, this field is hardwired + * to 0 on trigger 3 (tselect = 3). + * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). + */ +#define CSR_MCONTROL_CHAIN_MASK (0x800U) +#define CSR_MCONTROL_CHAIN_SHIFT (11U) +#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) +#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) + +/* + * MATCH (RW) + * + * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. + * 2:Matches when the value is greater than (unsigned) or equal to tdata2. + * 3:Matches when the value is less than (unsigned) tdata2 + */ +#define CSR_MCONTROL_MATCH_MASK (0x780U) +#define CSR_MCONTROL_MATCH_SHIFT (7U) +#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) +#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_MCONTROL_M_MASK (0x40U) +#define CSR_MCONTROL_M_SHIFT (6U) +#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) +#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_MCONTROL_S_MASK (0x10U) +#define CSR_MCONTROL_S_SHIFT (4U) +#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) +#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_MCONTROL_U_MASK (0x8U) +#define CSR_MCONTROL_U_SHIFT (3U) +#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) +#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) + +/* + * EXECUTE (RW) + * + * Setting this field to enable this trigger to compare virtual address of an instruction. + */ +#define CSR_MCONTROL_EXECUTE_MASK (0x4U) +#define CSR_MCONTROL_EXECUTE_SHIFT (2U) +#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) +#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) + +/* + * STORE (RW) + * + * Setting this field to enable this trigger to compare virtual address of a store. + */ +#define CSR_MCONTROL_STORE_MASK (0x2U) +#define CSR_MCONTROL_STORE_SHIFT (1U) +#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) +#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) + +/* + * LOAD (RW) + * + * Setting this field to enable this trigger to compare virtual address of a load. + */ +#define CSR_MCONTROL_LOAD_MASK (0x1U) +#define CSR_MCONTROL_LOAD_SHIFT (0U) +#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) +#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) + +/* Bitfield definition for register: ICOUNT */ +/* + * TYPE (RW) + * + * The selected trigger is an instruction count trigger. + */ +#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) +#define CSR_ICOUNT_TYPE_SHIFT (28U) +#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) +#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) +#define CSR_ICOUNT_DMODE_SHIFT (27U) +#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) +#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) + +/* + * COUNT (RO) + * + * This field is hardwired to 1 for single-stepping support + */ +#define CSR_ICOUNT_COUNT_MASK (0x400U) +#define CSR_ICOUNT_COUNT_SHIFT (10U) +#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ICOUNT_M_MASK (0x200U) +#define CSR_ICOUNT_M_SHIFT (9U) +#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) +#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ICOUNT_S_MASK (0x80U) +#define CSR_ICOUNT_S_SHIFT (7U) +#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) +#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ICOUNT_U_MASK (0x40U) +#define CSR_ICOUNT_U_SHIFT (6U) +#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) +#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ICOUNT_ACTION_MASK (0x3FU) +#define CSR_ICOUNT_ACTION_SHIFT (0U) +#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) +#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) + +/* Bitfield definition for register: ITRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an interrupt trigger. + */ +#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ITRIGGER_TYPE_SHIFT (28U) +#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) +#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ITRIGGER_DMODE_SHIFT (27U) +#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) +#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ITRIGGER_M_MASK (0x200U) +#define CSR_ITRIGGER_M_SHIFT (9U) +#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) +#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ITRIGGER_S_MASK (0x80U) +#define CSR_ITRIGGER_S_SHIFT (7U) +#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) +#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ITRIGGER_U_MASK (0x40U) +#define CSR_ITRIGGER_U_SHIFT (6U) +#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) +#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception. + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ITRIGGER_ACTION_MASK (0x3FU) +#define CSR_ITRIGGER_ACTION_SHIFT (0U) +#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) +#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: ETRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an exception trigger. + */ +#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ETRIGGER_TYPE_SHIFT (28U) +#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) +#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ETRIGGER_DMODE_SHIFT (27U) +#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) +#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) + +/* + * NMI (RW) + * + * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. + */ +#define CSR_ETRIGGER_NMI_MASK (0x400U) +#define CSR_ETRIGGER_NMI_SHIFT (10U) +#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) +#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ETRIGGER_M_MASK (0x200U) +#define CSR_ETRIGGER_M_SHIFT (9U) +#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) +#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ETRIGGER_S_MASK (0x80U) +#define CSR_ETRIGGER_S_SHIFT (7U) +#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) +#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ETRIGGER_U_MASK (0x40U) +#define CSR_ETRIGGER_U_SHIFT (6U) +#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) +#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ETRIGGER_ACTION_MASK (0x3FU) +#define CSR_ETRIGGER_ACTION_SHIFT (0U) +#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) +#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: TDATA2 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA2_DATA_SHIFT (0U) +#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) +#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) + +/* Bitfield definition for register: TDATA3 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA3_DATA_SHIFT (0U) +#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) +#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) + +/* Bitfield definition for register: TEXTRA */ +/* + * MVALUE (RW) + * + * Data used together with MSELECT. + */ +#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) +#define CSR_TEXTRA_MVALUE_SHIFT (26U) +#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) +#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) + +/* + * MSELECT (RW) + * + * 0:Ignore MVALUE. + * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. + */ +#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) +#define CSR_TEXTRA_MSELECT_SHIFT (25U) +#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) +#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) + +/* + * SVALUE (RW) + * + * Data used together with SSELECT. + */ +#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) +#define CSR_TEXTRA_SVALUE_SHIFT (2U) +#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) +#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) + +/* + * SSELECT (RW) + * + * 0:Ignore MVALUE + * 1:This trigger will only match if the lower bits of scontext equal SVALUE + * 2This trigger will only match if satp.ASID equals SVALUE. + */ +#define CSR_TEXTRA_SSELECT_MASK (0x3U) +#define CSR_TEXTRA_SSELECT_SHIFT (0U) +#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) +#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) + +/* Bitfield definition for register: TINFO */ +/* + * INFO (RO) + * + * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that + * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. + * 0:When this bit is set, there is no trigger at this tselect + * 1:Reserved and hardwired to 0. + * 2：When this bit is set, the selected trigger supports type of address/data match trigger + * 3:When this bit is set, the selected trigger supports type of instruction count trigger. + * 4:When this bit is set, the selected trigger supports type of interrupt trigger + * 5:When this bit is set, the selected trigger supports type of exception trigger + * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. + * Others:Reserved for future use. + */ +#define CSR_TINFO_INFO_MASK (0xFFFFU) +#define CSR_TINFO_INFO_SHIFT (0U) +#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) + +/* Bitfield definition for register: TCONTROL */ +/* + * MPTE (RW) + * + * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. + */ +#define CSR_TCONTROL_MPTE_MASK (0x80U) +#define CSR_TCONTROL_MPTE_SHIFT (7U) +#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) +#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) + +/* + * MTE (RW) + * + * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. + * 0:Triggers do not match/fire while the hart is in M-mode. + * 1:Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_MASK (0x8U) +#define CSR_TCONTROL_MTE_SHIFT (3U) +#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) +#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) + +/* Bitfield definition for register: MCONTEXT */ +/* + * MCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) +#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) +#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) +#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) + +/* Bitfield definition for register: SCONTEXT */ +/* + * SCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) +#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) +#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) +#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) + +/* Bitfield definition for register: DCSR */ +/* + * XDEBUGVER (RO) + * + * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 + */ +#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) +#define CSR_DCSR_XDEBUGVER_SHIFT (28U) +#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) + +/* + * EBREAKM (RW) + * + * This bit controls the behavior of EBREAK instructions in Machine Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKM_MASK (0x8000U) +#define CSR_DCSR_EBREAKM_SHIFT (15U) +#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) +#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) + +/* + * EBREAKS (RW) + * + * This bit controls the behavior of EBREAK instructions in Supervisor Mode. + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKS_MASK (0x2000U) +#define CSR_DCSR_EBREAKS_SHIFT (13U) +#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) +#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) + +/* + * EBREAKU (RW) + * + * This bit controls the behavior of EBREAK instructions in User/Application Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKU_MASK (0x1000U) +#define CSR_DCSR_EBREAKU_SHIFT (12U) +#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) +#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) + +/* + * STEPIE (RW) + * + * This bit controls whether interrupts are enabled during single stepping + * 0:Disable interrupts during single stepping + * 1:Allow interrupts in single stepping + */ +#define CSR_DCSR_STEPIE_MASK (0x800U) +#define CSR_DCSR_STEPIE_SHIFT (11U) +#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) +#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) + +/* + * STOPCOUNT (RW) + * + * This bit controls whether performance counters are stopped in Debug Mode. + * 0:Do not stop counters in Debug Mode + * 1:Stop counters in Debug Mode + */ +#define CSR_DCSR_STOPCOUNT_MASK (0x400U) +#define CSR_DCSR_STOPCOUNT_SHIFT (10U) +#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) +#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) + +/* + * STOPTIME (RW) + * + * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. + * 0:Do not stop timers in Debug Mode + * 1:Stop timers in Debug Mode + */ +#define CSR_DCSR_STOPTIME_MASK (0x200U) +#define CSR_DCSR_STOPTIME_SHIFT (9U) +#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) +#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) + +/* + * CAUSE (RO) + * + * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger + * 0:Reserved + * 1:EBREAK + * 2:Trigger module + * 3:Halt request + * 4:Single step + * 5:Halt-on-reset + * 6-7:Reserved + */ +#define CSR_DCSR_CAUSE_MASK (0x1C0U) +#define CSR_DCSR_CAUSE_SHIFT (6U) +#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) + +/* + * MPRVEN (RW) + * + * This bit controls whether mstatus.MPRV takes effect in Debug Mode. + * 0:MPRV in mstatus is ignored in Debug Mode. + * 1:MPRV in mstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_MASK (0x10U) +#define CSR_DCSR_MPRVEN_SHIFT (4U) +#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) +#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) + +/* + * NMIP (RO) + * + * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. + */ +#define CSR_DCSR_NMIP_MASK (0x8U) +#define CSR_DCSR_NMIP_SHIFT (3U) +#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) + +/* + * STEP (RW) + * + * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. + * 0:Single Step Mode is off + * 1:Single Step Mode is on + */ +#define CSR_DCSR_STEP_MASK (0x4U) +#define CSR_DCSR_STEP_SHIFT (2U) +#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) +#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) + +/* + * PRV (RW) + * + * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. + * 0:User/Application + * 1:Supervisor + * 2:Reserved + * 3:Machine + */ +#define CSR_DCSR_PRV_MASK (0x3U) +#define CSR_DCSR_PRV_SHIFT (0U) +#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) +#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) + +/* Bitfield definition for register: DPC */ +/* + * DPC (RW) + * + * Debug Program Counter. Bit 0 is hardwired to 0. + */ +#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) +#define CSR_DPC_DPC_SHIFT (0U) +#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) +#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) + +/* Bitfield definition for register: DSCRATCH0 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) + +/* Bitfield definition for register: DSCRATCH1 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) + +/* Bitfield definition for register: MCYCLE */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLE_COUNTER_SHIFT (0U) +#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) +#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRET */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRET_COUNTER_SHIFT (0U) +#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) +#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) +#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) +#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) +#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) +#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) + +/* Bitfield definition for register: MCYCLEH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLEH_COUNTER_SHIFT (0U) +#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) +#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRETH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRETH_COUNTER_SHIFT (0U) +#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) +#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) +#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) +#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) +#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) +#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) + +/* Bitfield definition for register: PMACFG0 */ +/* + * PMA3CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) +#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) +#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) +#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) + +/* + * PMA2CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) +#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) +#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) +#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) + +/* + * PMA1CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) +#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) +#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) +#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) + +/* + * PMA0CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) +#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) +#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) +#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) + +/* Bitfield definition for register: PMACFG1 */ +/* + * PMA7CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) +#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) +#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) +#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) + +/* + * PMA6CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) +#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) +#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) +#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) + +/* + * PMA5CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) +#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) +#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) +#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) + +/* + * PMA4CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) +#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) +#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) +#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) + +/* Bitfield definition for register: PMACFG2 */ +/* + * PMA11CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) +#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) +#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) +#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) + +/* + * PMA10CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) +#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) +#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) +#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) + +/* + * PMA9CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) +#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) +#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) +#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) + +/* + * PMA8CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) +#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) +#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) +#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) + +/* Bitfield definition for register: PMACFG3 */ +/* + * PMA15CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) +#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) +#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) +#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) + +/* + * PMA14CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) +#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) +#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) +#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) + +/* + * PMA13CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) +#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) +#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) +#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) + +/* + * PMA12CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) +#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) +#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) +#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaaaaaaaaaa Reserved + * . . . . . . + * aaaa. . . aa011111111 Reserved + * aaaa. . . a0111111111 2^{12} + * aaaa. . . 01111111111 2^{13} + * . . . . . . + * aa01. . . 11111111111 2^{XLEN} + * a011. . . 11111111111 2^{XLEN+1} + * 0111. . . 11111111111 2^{XLEN+2} + * 1111. . . 11111111111 Reserved + */ +#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) +#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) +#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) +#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) +#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) +#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) +#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) +#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) +#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) +#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) +#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) +#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) +#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) +#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) +#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) +#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) +#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register: CYCLE */ +/* + * CYCLE (RW) + * + * Cycle Counter + */ +#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) +#define CSR_CYCLE_CYCLE_SHIFT (0U) +#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) +#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) + +/* Bitfield definition for register: CYCLEH */ +/* + * CYCLEH (RW) + * + * Cycle Counter Higher 32-bit + */ +#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) +#define CSR_CYCLEH_CYCLEH_SHIFT (0U) +#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) +#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) + +/* Bitfield definition for register: MVENDORID */ +/* + * MVENDORID (RO) + * + * The manufacturer ID + */ +#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) +#define CSR_MVENDORID_MVENDORID_SHIFT (0U) +#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) + +/* Bitfield definition for register: MARCHID */ +/* + * CPU_ID (RO) + * + * CPU ID + */ +#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) +#define CSR_MARCHID_CPU_ID_SHIFT (0U) +#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) + +/* Bitfield definition for register: MIMPID */ +/* + * MAJOR (RO) + * + * Revision major + */ +#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) +#define CSR_MIMPID_MAJOR_SHIFT (8U) +#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) + +/* + * MINOR (RO) + * + * Revision minor + */ +#define CSR_MIMPID_MINOR_MASK (0xF0U) +#define CSR_MIMPID_MINOR_SHIFT (4U) +#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) + +/* + * EXTENSION (RO) + * + * Revision extension + */ +#define CSR_MIMPID_EXTENSION_MASK (0xFU) +#define CSR_MIMPID_EXTENSION_SHIFT (0U) +#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) + +/* Bitfield definition for register: MHARTID */ +/* + * MHARTID (RO) + * + * Hart ID + */ +#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) +#define CSR_MHARTID_MHARTID_SHIFT (0U) +#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) + +/* NON-STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: SCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) +#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) +#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) +#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) +#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_IR_MASK (0x4U) +#define CSR_SCOUNTEREN_IR_SHIFT (2U) +#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) +#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_CY_MASK (0x1U) +#define CSR_SCOUNTEREN_CY_SHIFT (0U) +#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) +#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) +#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) +#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) +#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) +#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) +#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) +#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) +#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: MILMB */ +/* + * IBPA (RO) + * + * The base physical address of ILM. It has to be an integer multiple of the ILM size + */ +#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) +#define CSR_MILMB_IBPA_SHIFT (10U) +#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MILMB_RWECC_MASK (0x8U) +#define CSR_MILMB_RWECC_SHIFT (3U) +#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) +#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MILMB_ECCEN_MASK (0x6U) +#define CSR_MILMB_ECCEN_SHIFT (1U) +#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) +#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) + +/* + * IEN (RO) + * + * ILM enable control: + * 0:ILM is disabled + * 1:ILM is enabled + */ +#define CSR_MILMB_IEN_MASK (0x1U) +#define CSR_MILMB_IEN_SHIFT (0U) +#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) + +/* Bitfield definition for register: MDLMB */ +/* + * DBPA (RO) + * + * The base physical address of DLM. It has to be an integer multiple of the DLM size + */ +#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) +#define CSR_MDLMB_DBPA_SHIFT (10U) +#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MDLMB_RWECC_MASK (0x8U) +#define CSR_MDLMB_RWECC_SHIFT (3U) +#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) +#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MDLMB_ECCEN_MASK (0x6U) +#define CSR_MDLMB_ECCEN_SHIFT (1U) +#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) +#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) + +/* + * DEN (RO) + * + * DLM enable control: + * 0:DLM is disabled + * 1:DLM is enabled + */ +#define CSR_MDLMB_DEN_MASK (0x1U) +#define CSR_MDLMB_DEN_SHIFT (0U) +#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) + +/* Bitfield definition for register: MECC_CODE */ +/* + * INSN (RO) + * + * Indicates if the parity/ECC error is caused by instruction fetch or data access. + * 0:Data access + * 1:Instruction fetch + */ +#define CSR_MECC_CODE_INSN_MASK (0x400000UL) +#define CSR_MECC_CODE_INSN_SHIFT (22U) +#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) + +/* + * RAMID (RO) + * + * The ID of RAM that caused parity/ECC errors. + * This bit is updated on parity/ECC error exceptions. + * 0–1:Reserved + * 2:Tag RAM of I-Cache + * 3:Data RAM of I-Cache + * 4:Tag RAM of D-Cache + * 5:Data RAM of D-Cache + * 6:Tag RAM of TLB + * 7:Data RAM of TLB + * 8:ILM + * 9:DLM + * 10–15:Reserved + */ +#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) +#define CSR_MECC_CODE_RAMID_SHIFT (18U) +#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) + +/* + * P (RO) + * + * Precise error. This bit is updated on parity/ECC error exceptions. + * 0:Imprecise error + * 1:Precise error + */ +#define CSR_MECC_CODE_P_MASK (0x20000UL) +#define CSR_MECC_CODE_P_SHIFT (17U) +#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) + +/* + * C (RO) + * + * Correctable error. This bit is updated on parity/ECC error exceptions. + * 0:Uncorrectable error + * 1:Correctable error + */ +#define CSR_MECC_CODE_C_MASK (0x10000UL) +#define CSR_MECC_CODE_C_SHIFT (16U) +#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) + +/* + * CODE (RW) + * + * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). + */ +#define CSR_MECC_CODE_CODE_MASK (0x7FU) +#define CSR_MECC_CODE_CODE_SHIFT (0U) +#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) +#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) + +/* Bitfield definition for register: MNVEC */ +/* + * MNVEC (RO) + * + * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. + */ +#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) +#define CSR_MNVEC_MNVEC_SHIFT (0U) +#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) + +/* Bitfield definition for register: MXSTATUS */ +/* + * PDME (RW) + * + * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. + */ +#define CSR_MXSTATUS_PDME_MASK (0x20U) +#define CSR_MXSTATUS_PDME_SHIFT (5U) +#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) +#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) + +/* + * DME (RW) + * + * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. + */ +#define CSR_MXSTATUS_DME_MASK (0x10U) +#define CSR_MXSTATUS_DME_SHIFT (4U) +#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) +#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) + +/* + * PPFT_EN (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) +#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) +#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) +#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) + +/* + * PFT_EN (RW) + * + * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: + * PPFT_EN <= PFT_EN; + * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; + * On executing an MRET instruction: + * PFT_EN <= PPFT_EN; + * This field is hardwired to 0 if the PowerBrake feature is not supported. + */ +#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) +#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) +#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) +#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) + +/* Bitfield definition for register: MPFT_CTL */ +/* + * FAST_INT (RW) + * + * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. + */ +#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) +#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) +#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) +#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) + +/* + * T_LEVEL (RW) + * + * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest + * performance at throttling level 15. + * 0:Level 0 (the highest performance) + * 1-14:Level 1-14 + * 15:Level 15 (the lowest performance) + */ +#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) +#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) +#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) +#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) + +/* Bitfield definition for register: MHSP_CTL */ +/* + * M (RW) + * + * Enables the SP protection and recording mechanism in Machine mode + * 0:The mechanism is disabled in Machine mode. + * 1: The mechanism is enabled in Machine mode. + */ +#define CSR_MHSP_CTL_M_MASK (0x20U) +#define CSR_MHSP_CTL_M_SHIFT (5U) +#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) +#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) + +/* + * S (RW) + * + * Enables the SP protection and recording mechanism in Supervisor mode + * 0:The mechanism is disabled in Supervisor mode + * 1:The mechanism is enabled in Supervisor mode + */ +#define CSR_MHSP_CTL_S_MASK (0x10U) +#define CSR_MHSP_CTL_S_SHIFT (4U) +#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) +#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) + +/* + * U (RW) + * + * Enables the SP protection and recording mechanism in User mode + * 0:The mechanism is disabled in User mode + * 1:The mechanism is enabled in User mode. + */ +#define CSR_MHSP_CTL_U_MASK (0x8U) +#define CSR_MHSP_CTL_U_SHIFT (3U) +#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) +#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) + +/* + * SCHM (RW) + * + * Selects the operating scheme of the stack protection and recording mechanism + * 0:Stack overflow/underflow detection + * 1:Top-of-stack recording + */ +#define CSR_MHSP_CTL_SCHM_MASK (0x4U) +#define CSR_MHSP_CTL_SCHM_SHIFT (2U) +#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) +#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) + +/* + * UDF_EN (RW) + * + * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack underflow protection is disabled + * 1:The stack underflow protection is enabled. + */ +#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) +#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) +#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) +#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) + +/* + * OVF_EN (RW) + * + * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack overflow protection and recording mechanism are disabled. + * 1:The stack overflow protection and recording mechanism are enabled. + */ +#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) +#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) +#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) +#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) + +/* Bitfield definition for register: MSP_BOUND */ +/* + * MSP_BOUND (RW) + * + * Machine SP Bound + */ +#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) +#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) +#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) + +/* Bitfield definition for register: MSP_BASE */ +/* + * SP_BASE (RW) + * + * Machine SP base + */ +#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) +#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) +#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) + +/* Bitfield definition for register: MDCAUSE */ +/* + * PM (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MDCAUSE_PM_MASK (0x60U) +#define CSR_MDCAUSE_PM_SHIFT (5U) +#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) +#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) + +/* + * MDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the mcause register. + * The value of MDCAUSE for precise exception: + * When mcause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When mcause == 2 (Illegal instruction): + * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When mcause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When mcause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of MDCAUSE for imprecise exception: + * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) +#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) +#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) +#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) + +/* Bitfield definition for register: MCACHE_CTL */ +/* + * DC_WAROUND (RW) + * + * Cache Write-Around threshold + * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. + * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. + * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. + * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. + */ +#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) +#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) +#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) +#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) + +/* + * DC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) + +/* + * IC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) + +/* + * DPREF_EN (RW) + * + * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 + * 0:Disable hardware prefetch on load/store memory accesses + * 1:Enable hardware prefetch on load/store memory accesses + */ +#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) +#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) +#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) +#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) + +/* + * IPREF_EN (RW) + * + * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 + * 0:Disable hardware prefetch on instruction fetches + * 1:Enable hardware prefetch on instruction fetches + */ +#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) +#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) +#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) +#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) + +/* + * CCTL_SUEN (RW) + * + * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs + * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) +#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) + +/* + * DC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) +#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) +#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) +#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) + +/* + * IC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) +#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) +#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) +#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) + +/* + * DC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * data cache. + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) +#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) +#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) +#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) + +/* + * IC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * instruction cache + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) +#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) +#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) +#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) + +/* + * DC_EN (RW) + * + * Controls if the data cache is enabled or not. + * 0:D-Cache is disabled + * 1:D-Cache is enabled + */ +#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) +#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) +#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) +#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) + +/* + * IC_EN (RW) + * + * Controls if the instruction cache is enabled or not. + * 0:I-Cache is disabled + * 1:I-Cache is enabled + */ +#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) +#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) +#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) +#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) + +/* Bitfield definition for register: MCCTLBEGINADDR */ +/* + * VA (RW) + * + * This register holds the address information required by CCTL operations + */ +#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) +#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: MCCTLCOMMAND */ +/* + * VA (RW) + * + * See CCTL Command Definition Table + */ +#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) +#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_MCCTLDATA_VA_MASK (0x1FU) +#define CSR_MCCTLDATA_VA_SHIFT (0U) +#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) +#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: MCOUNTERWEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) +#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) +#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) +#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) +#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_IR_MASK (0x4U) +#define CSR_MCOUNTERWEN_IR_SHIFT (2U) +#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) +#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_CY_MASK (0x1U) +#define CSR_MCOUNTERWEN_CY_SHIFT (0U) +#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) +#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) +#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) +#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) +#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) +#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) +#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) +#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: MMISC_CTL */ +/* + * NBLD_EN (RW) + * + * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. + * 0:Load to memory regions are blocking. + * 1:Load to memory regions are non-blocking. + */ +#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) +#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) +#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) +#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) + +/* + * MSA_UNA (RW) + * + * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. + * Supported instructions: LW/LH/LHU/SW/SH + * 0:Misaligned accesses generate Address Misaligned exceptions. + * 1:Misaligned accesses generate Address Misaligned exceptions. + */ +#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) +#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) +#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) +#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) + +/* + * BRPE (RW) + * + * Branch prediction enable bit. This bit controls all branch prediction structures. + * 0:Disabled + * 1:Enabled + * This bit is hardwired to 0 if branch prediction structure is not supported. + */ +#define CSR_MMISC_CTL_BRPE_MASK (0x8U) +#define CSR_MMISC_CTL_BRPE_SHIFT (3U) +#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) +#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) + +/* + * RVCOMPM (RW) + * + * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions + * 0:Disabled + * 1:Enabled + */ +#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) +#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) +#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) +#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) + +/* + * VEC_PLIC (RW) + * + * Selects the operation mode of PLIC: + * 0:Regular mode + * 1:Vector mode + * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. + */ +#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) +#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) +#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) +#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) +#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) +#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) +#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) +#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) +#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) +#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) +#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) +#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) +#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) +#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) +#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) +#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) +#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) +#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) +#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) +#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) +#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) +#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) +#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) +#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) +#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) +#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_IR_MASK (0x4U) +#define CSR_MCOUNTEROVF_IR_SHIFT (2U) +#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) +#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_CY_MASK (0x1U) +#define CSR_MCOUNTEROVF_CY_SHIFT (0U) +#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) +#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: MSLIDELEG */ +/* + * PMOVI (RW) + * + * Delegate S-mode performance monitor overflow local interrupt to S-mode. + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) +#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) +#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) +#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Delegate S-mode bus read/write transaction error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) +#define CSR_MSLIDELEG_BWEI_SHIFT (17U) +#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) +#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Delegate S-mode slave-port ECC error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) +#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) +#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) +#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) + +/* Bitfield definition for register: MCLK_CTL */ +/* + * FUNIT (RW) + * + * Level 2 clock gating enable for function units listed in the following table. + * 16:integer arithmetic unit + * 17:integer permutation unit + * 18:integer mask unit + * 19:integer division unit + * 20:integer multiply and add unit + * 21:floating-point multiply and add + * unit + * 22:floating-point miscellaneous unit + * 23:floating-point division unit + * 24:load/store unit + * 31:25:Reserved + */ +#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) +#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) +#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) +#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) + +/* + * VI (RW) + * + * Level 1 clock gating enable for the vector/floating-point issue queues. + */ +#define CSR_MCLK_CTL_VI_MASK (0x8000U) +#define CSR_MCLK_CTL_VI_SHIFT (15U) +#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) +#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) + +/* + * VR (RW) + * + * Level 1 clock gating enable for the vector/floating-point register file. + */ +#define CSR_MCLK_CTL_VR_MASK (0x4000U) +#define CSR_MCLK_CTL_VR_SHIFT (14U) +#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) +#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) + +/* + * AQ (RW) + * + * Level 1 clock gating enable for ACE load/store queues. + */ +#define CSR_MCLK_CTL_AQ_MASK (0x2000U) +#define CSR_MCLK_CTL_AQ_SHIFT (13U) +#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) +#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) + +/* + * DQ (RW) + * + * Level 1 clock gating enable for data cache load/store queues. + */ +#define CSR_MCLK_CTL_DQ_MASK (0x1000U) +#define CSR_MCLK_CTL_DQ_SHIFT (12U) +#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) +#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) + +/* + * UQ (RW) + * + * Level 1 clock gating enable for uncached queues + */ +#define CSR_MCLK_CTL_UQ_MASK (0x800U) +#define CSR_MCLK_CTL_UQ_SHIFT (11U) +#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) +#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) + +/* + * FP (RW) + * + * Level 1 clock gating enable for scalar floating point issue unit and queues. + */ +#define CSR_MCLK_CTL_FP_MASK (0x400U) +#define CSR_MCLK_CTL_FP_SHIFT (10U) +#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) +#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) + +/* + * CLKGATE (RW) + * + * One-hot clock gating levels. + * 0:Level 1 clock gating in module level + * 1:Level 2 clock gating in unit level + * 2:Level 3 clock gating in VPU level + * 7:3:Reserved + */ +#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) +#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) +#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) +#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) + +/* Bitfield definition for register: DEXC2DBG */ +/* + * PMOV (RW) + * + * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) +#define CSR_DEXC2DBG_PMOV_SHIFT (19U) +#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) +#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) + +/* + * SPF (RW) + * + * Indicates whether store page fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) +#define CSR_DEXC2DBG_SPF_SHIFT (18U) +#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) +#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) + +/* + * LPF (RW) + * + * Indicates whether load fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) +#define CSR_DEXC2DBG_LPF_SHIFT (17U) +#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) +#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) + +/* + * IPF (RW) + * + * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) +#define CSR_DEXC2DBG_IPF_SHIFT (16U) +#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) +#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) + +/* + * BWE (RW) + * + * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_BWE_MASK (0x8000U) +#define CSR_DEXC2DBG_BWE_SHIFT (15U) +#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) +#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) + +/* + * SLPECC (RW) + * + * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) +#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) +#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) +#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) + +/* + * ACE (RW) + * + * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_ACE_MASK (0x2000U) +#define CSR_DEXC2DBG_ACE_SHIFT (13U) +#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) +#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) + +/* + * HSP (RW) + * + * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_HSP_MASK (0x1000U) +#define CSR_DEXC2DBG_HSP_SHIFT (12U) +#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) +#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) + +/* + * MEC (RW) + * + * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_MEC_MASK (0x800U) +#define CSR_DEXC2DBG_MEC_SHIFT (11U) +#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) +#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) + +/* + * SEC (RW) + * + * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SEC_MASK (0x200U) +#define CSR_DEXC2DBG_SEC_SHIFT (9U) +#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) +#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) + +/* + * UEC (RW) + * + * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_UEC_MASK (0x100U) +#define CSR_DEXC2DBG_UEC_SHIFT (8U) +#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) +#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) + +/* + * SAF (RW) + * + * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAF_MASK (0x80U) +#define CSR_DEXC2DBG_SAF_SHIFT (7U) +#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) +#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) + +/* + * SAM (RW) + * + * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAM_MASK (0x40U) +#define CSR_DEXC2DBG_SAM_SHIFT (6U) +#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) +#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) + +/* + * LAF (RW) + * + * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAF_MASK (0x20U) +#define CSR_DEXC2DBG_LAF_SHIFT (5U) +#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) +#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) + +/* + * LAM (RW) + * + * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAM_MASK (0x10U) +#define CSR_DEXC2DBG_LAM_SHIFT (4U) +#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) +#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) + +/* + * NMI (RW) + * + * Indicates whether Non-Maskable Interrupt + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_NMI_MASK (0x8U) +#define CSR_DEXC2DBG_NMI_SHIFT (3U) +#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) +#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) + +/* + * II (RW) + * + * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_II_MASK (0x4U) +#define CSR_DEXC2DBG_II_SHIFT (2U) +#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) +#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) + +/* + * IAF (RW) + * + * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAF_MASK (0x2U) +#define CSR_DEXC2DBG_IAF_SHIFT (1U) +#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) +#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) + +/* + * IAM (RW) + * + * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAM_MASK (0x1U) +#define CSR_DEXC2DBG_IAM_SHIFT (0U) +#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) +#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) + +/* Bitfield definition for register: DDCAUSE */ +/* + * SUBTYPE (RO) + * + * Subtypes for main type. + * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. + * 0:Illegal instruction + * 1:Privileged instruction + * 2:Non-existent CSR + * 3:Privilege CSR access + * 4:Read-only CSR update + */ +#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) +#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) +#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) + +/* + * MAINTYPE (RO) + * + * Cause for redirection to Debug Mode. + * 0:Software Breakpoint (EBREAK) + * 1:Instruction Access Misaligned (IAM) + * 2:Instruction Access Fault (IAF) + * 3:Illegal Instruction (II) + * 4:Non-Maskable Interrupt (NMI) + * 5:Load Access Misaligned (LAM) + * 6:Load Access Fault (LAF) + * 7:Store Access Misaligned (SAM) + * 8:Store Access Fault (SAF) + * 9:U-mode Environment Call (UEC) + * 10:S-mode Environment Call (SEC) + * 11:Instruction page fault + * 12:M-mode Environment Call (MEC) + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 16:Imprecise ECC error + * 17;Bus write transaction error + * 18:Performance Counter overflow + * 19–31:Reserved + * 32:Stack overflow exception + * 33:Stack underflow exception + * 34:ACE disabled exception + * 35–39:Reserved + * 40–47:ACE exception + * ≥48:Reserved + */ +#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) +#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) +#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) + +/* Bitfield definition for register: UITB */ +/* + * ADDR (RW) + * + * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. + */ +#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) +#define CSR_UITB_ADDR_SHIFT (2U) +#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) +#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) + +/* + * HW (RO) + * + * This bit specifies if the CoDense instruction table is hardwired. + * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. + * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. + */ +#define CSR_UITB_HW_MASK (0x1U) +#define CSR_UITB_HW_SHIFT (0U) +#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) + +/* Bitfield definition for register: UCODE */ +/* + * OV (RW) + * + * Overflow flag. It will be set by DSP instructions with a saturated result. + * 0:A saturated result is not generated + * 1:A saturated result is generated + */ +#define CSR_UCODE_OV_MASK (0x1U) +#define CSR_UCODE_OV_SHIFT (0U) +#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) +#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) + +/* Bitfield definition for register: UDCAUSE */ +/* + * UDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. + * The value of UDCAUSE for precise exception: + * When ucause == 1 (Instruction access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP instruction access violation + * 3:Bus error + * 4:PMA empty hole access + * When ucause == 2 (Illegal instruction) + * 0:Please parse the utval CSR + * 1:FP disabled exception + * 2:ACE disabled exception + * When ucause == 5 (Load access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP load access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + * When ucause == 7 (Store access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP store access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + */ +#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) +#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) +#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) +#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) + +/* Bitfield definition for register: UCCTLBEGINADDR */ +/* + * VA (RW) + * + * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. + */ +#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) +#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: UCCTLCOMMAND */ +/* + * VA (RW) + * + * See User CCTL Command Definition Table + */ +#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) +#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: SLIE */ +/* + * PMOVI (RW) + * + * Enable S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_PMOVI_MASK (0x40000UL) +#define CSR_SLIE_PMOVI_SHIFT (18U) +#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) +#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_BWEI_MASK (0x20000UL) +#define CSR_SLIE_BWEI_SHIFT (17U) +#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) +#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Enable S-mode slave-port ECC error local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_IMECCI_MASK (0x10000UL) +#define CSR_SLIE_IMECCI_SHIFT (16U) +#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) +#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) + +/* Bitfield definition for register: SLIP */ +/* + * PMOVI (RW) + * + * Pending control and status of S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_PMOVI_MASK (0x40000UL) +#define CSR_SLIP_PMOVI_SHIFT (18U) +#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) +#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_BWEI_MASK (0x20000UL) +#define CSR_SLIP_BWEI_SHIFT (17U) +#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) +#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Pending control and status of S-mode slave-port ECC error local interrupt.. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_IMECCI_MASK (0x10000UL) +#define CSR_SLIP_IMECCI_SHIFT (16U) +#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) +#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) + +/* Bitfield definition for register: SDCAUSE */ +/* + * PM (RW) + * + * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0:User mode + * 1:Supervisor mode + * 2:Reserved + * 3:Machine mode + */ +#define CSR_SDCAUSE_PM_MASK (0x60U) +#define CSR_SDCAUSE_PM_SHIFT (5U) +#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) +#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) + +/* + * SDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. + * The value of SDCAUSE for precise exception: + * When scause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When scause == 2 (Illegal instruction): + * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When scause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When scause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of SDCAUSE for imprecise exception: + * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) +#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) +#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) +#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) + +/* Bitfield definition for register: SCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_SCCTLDATA_VA_MASK (0x1FU) +#define CSR_SCCTLDATA_VA_SHIFT (0U) +#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) +#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: SCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) +#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) +#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) +#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) +#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) +#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) +#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) +#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) +#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) +#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) +#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) +#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) +#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) +#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) +#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) +#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) +#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) +#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) +#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) +#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) +#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) +#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) +#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) +#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) +#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) +#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) +#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) +#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) +#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_IR_MASK (0x4U) +#define CSR_SCOUNTEROVF_IR_SHIFT (2U) +#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) +#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_CY_MASK (0x1U) +#define CSR_SCOUNTEROVF_CY_SHIFT (0U) +#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) +#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) +#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) +#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) +#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) +#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) +#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) +#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) +#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: SHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT3_SEL_SHIFT (4U) +#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) +#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) +#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT4_SEL_SHIFT (4U) +#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) +#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) +#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT5_SEL_SHIFT (4U) +#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) +#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) +#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT6_SEL_SHIFT (4U) +#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) +#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) +#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MICM_CFG */ +/* + * SETH (RO) + * + * This bit extends the ISET field. + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MICM_CFG_SETH_SHIFT (24U) +#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) + +/* + * ILM_ECC (RO) + * + * ILM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) +#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) +#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) + +/* + * ILMSZ (RO) + * + * ILM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) +#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) +#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) + +/* + * ILMB (RW) + * + * Number of ILM base registers present + * 0:No ILM base register present + * 1:One ILM base register present + * 2-7:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMB_MASK (0x7000U) +#define CSR_MICM_CFG_ILMB_SHIFT (12U) +#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) +#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) + +/* + * IC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) +#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) +#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) + +/* + * ILCK (RO) + * + * I-Cache locking support + * 0:No locking support + * 1:With locking support + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILCK_MASK (0x200U) +#define CSR_MICM_CFG_ILCK_SHIFT (9U) +#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) + +/* + * ISZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) +#define CSR_MICM_CFG_ISZ_SHIFT (6U) +#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) + +/* + * IWAY (RO) + * + * Associativity of I-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IWAY_MASK (0x38U) +#define CSR_MICM_CFG_IWAY_SHIFT (3U) +#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) + +/* + * ISET (RO) + * + * I-Cache sets (# of cache lines per way): + * When micm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When micm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + */ +#define CSR_MICM_CFG_ISET_MASK (0x7U) +#define CSR_MICM_CFG_ISET_SHIFT (0U) +#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) + +/* Bitfield definition for register: MDCM_CFG */ +/* + * SETH (RO) + * + * This bit extends the DSET field. + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MDCM_CFG_SETH_SHIFT (24U) +#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) + +/* + * DLM_ECC (RO) + * + * DLM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When DLM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) +#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) +#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) + +/* + * DLMSZ (RO) + * + * DLM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) +#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) +#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) + +/* + * DLMB (RO) + * + * Number of DLM base registers present + * 0:No DLM base register present + * 1:One DLM base register present + * 2-7:Reserved + * When DLM is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) +#define CSR_MDCM_CFG_DLMB_SHIFT (12U) +#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) + +/* + * DC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC support + * 1:Has parity support + * 2:Has ECC support + * 3:Reserved + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) +#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) +#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) + +/* + * DLCK (RO) + * + * D-Cache locking support + * 0:No locking support + * 1:With locking support + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLCK_MASK (0x200U) +#define CSR_MDCM_CFG_DLCK_SHIFT (9U) +#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) + +/* + * DSZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) +#define CSR_MDCM_CFG_DSZ_SHIFT (6U) +#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) + +/* + * DWAY (RO) + * + * Associativity of D-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DWAY_MASK (0x38U) +#define CSR_MDCM_CFG_DWAY_SHIFT (3U) +#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) + +/* + * DSET (RO) + * + * D-Cache sets (# of cache lines per way): + * When mdcm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When mdcm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DSET_MASK (0x7U) +#define CSR_MDCM_CFG_DSET_SHIFT (0U) +#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) + +/* Bitfield definition for register: MMSC_CFG */ +/* + * MSC_EXT (RO) + * + * Indicates if the mmsc_cfg2 CSR is present or not. + * 0:The mmsc_cfg2 CSR is not present. + * 1:The mmsc_cfg2 CSR is present + */ +#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) +#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) +#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) + +/* + * PPMA (RO) + * + * Indicates if programmable PMA setup with PMA region CSRs is supported or not + * 0:Programmable PMA setup is not supported. + * 1:Programmable PMA setup is supported. + */ +#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) +#define CSR_MMSC_CFG_PPMA_SHIFT (30U) +#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) + +/* + * EDSP (RO) + * + * Indicates if the DSP extension is supported or not + * 0:The DSP extension is not supported. + * 1:The DSP extension is supported. + */ +#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) +#define CSR_MMSC_CFG_EDSP_SHIFT (29U) +#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) + +/* + * VCCTL (RO) + * + * Indicates the version number of CCTL command operation scheme supported by an implementation + * 0:instruction cache and data cache are not configured. + * 1:instruction cache or data cache is configured. + */ +#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) +#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) +#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) + +/* + * EFHW (RO) + * + * Indicates the support of FLHW and FSHW instructions + * 0:FLHW and FSHW instructions are not supported + * 1:FLHW and FSHW instructions are supported. + */ +#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) +#define CSR_MMSC_CFG_EFHW_SHIFT (17U) +#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) + +/* + * CCTLCSR (RO) + * + * Indicates the presence of CSRs for CCTL operations. + * 0:Feature of CSRs for CCTL operations is not supported. + * 1:Feature of CSRs for CCTL operations is supported. + */ +#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) +#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) +#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) + +/* + * PMNDS (RO) + * + * Indicates if Andes-enhanced performance monitoring feature is present or no. + * 0:Andes-enhanced performance monitoring feature is not supported. + * 1:Andes-enhanced performance monitoring feature is supported. + */ +#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) +#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) +#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) + +/* + * LMSLVP (RO) + * + * Indicates if local memory slave port is present or not. + * 0:Local memory slave port is not present. + * 1:Local memory slave port is implemented. + */ +#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) +#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) +#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) + +/* + * EV5PE (RO) + * + * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) +#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) +#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) + +/* + * VPLIC (RO) + * + * Indicates whether the Andes Vectored PLIC Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) +#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) +#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) + +/* + * ACE (RO) + * + * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ACE_MASK (0x40U) +#define CSR_MMSC_CFG_ACE_SHIFT (6U) +#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) + +/* + * HSP (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_HSP_MASK (0x20U) +#define CSR_MMSC_CFG_HSP_SHIFT (5U) +#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) + +/* + * PFT (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_PFT_MASK (0x10U) +#define CSR_MMSC_CFG_PFT_SHIFT (4U) +#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) + +/* + * ECD (RO) + * + * Indicates whether the Andes CoDense Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ECD_MASK (0x8U) +#define CSR_MMSC_CFG_ECD_SHIFT (3U) +#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) + +/* + * TLB_ECC (RO) + * + * TLB parity/ECC support configuration. + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + */ +#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) +#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) +#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) + +/* + * ECC (RO) + * + * Indicates whether the parity/ECC soft-error protection is implemented or not. + * 0:Not implemented. + * 1:Implemented. + * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. + * micm_cfg.IC_ECC + * micm_cfg.ILM_ECC + * mdcm_cfg.DC_ECC + * mdcm_cfg.DLM_ECC + * mmsc_cfg.TLB_ECC + */ +#define CSR_MMSC_CFG_ECC_MASK (0x1U) +#define CSR_MMSC_CFG_ECC_SHIFT (0U) +#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) + +/* Bitfield definition for register: MMSC_CFG2 */ +/* + * FINV (RO) + * + * Indicates if scalar FPU is implemented in VPU + * 0:Scalar FPU is not implemented in VPU + * 1:Scalar FPU is implemented in VPU + */ +#define CSR_MMSC_CFG2_FINV_MASK (0x20U) +#define CSR_MMSC_CFG2_FINV_SHIFT (5U) +#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) + +/* + * ZFH (RO) + * + * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. + * 0:The FP16 extension is not supported. + * 1:The FP16 extension is supported + */ +#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) +#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) +#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) + +/* + * BF16CVT (RO) + * + * Indicates if the BFLOAT16 conversion extension + * is supported or not. + * 0:The BFLOAT16 conversion extension is not supported + * 1:The BFLOAT16 conversion extension is supported + */ +#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) +#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) +#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) + + +#endif /* HPM_CSR_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h new file mode 100644 index 0000000000..6d595d073f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_SRC_H +#define HPM_DMAMUX_SRC_H + +/* dma mux definitions */ +#define HPM_DMA_SRC_SPI0_RX (0x0UL) +#define HPM_DMA_SRC_SPI0_TX (0x1UL) +#define HPM_DMA_SRC_SPI1_RX (0x2UL) +#define HPM_DMA_SRC_SPI1_TX (0x3UL) +#define HPM_DMA_SRC_SPI2_RX (0x4UL) +#define HPM_DMA_SRC_SPI2_TX (0x5UL) +#define HPM_DMA_SRC_SPI3_RX (0x6UL) +#define HPM_DMA_SRC_SPI3_TX (0x7UL) +#define HPM_DMA_SRC_UART0_RX (0x8UL) +#define HPM_DMA_SRC_UART0_TX (0x9UL) +#define HPM_DMA_SRC_UART1_RX (0xAUL) +#define HPM_DMA_SRC_UART1_TX (0xBUL) +#define HPM_DMA_SRC_UART2_RX (0xCUL) +#define HPM_DMA_SRC_UART2_TX (0xDUL) +#define HPM_DMA_SRC_UART3_RX (0xEUL) +#define HPM_DMA_SRC_UART3_TX (0xFUL) +#define HPM_DMA_SRC_UART4_RX (0x10UL) +#define HPM_DMA_SRC_UART4_TX (0x11UL) +#define HPM_DMA_SRC_UART5_RX (0x12UL) +#define HPM_DMA_SRC_UART5_TX (0x13UL) +#define HPM_DMA_SRC_UART6_RX (0x14UL) +#define HPM_DMA_SRC_UART6_TX (0x15UL) +#define HPM_DMA_SRC_UART7_RX (0x16UL) +#define HPM_DMA_SRC_UART7_TX (0x17UL) +#define HPM_DMA_SRC_I2S0_RX (0x18UL) +#define HPM_DMA_SRC_I2S0_TX (0x19UL) +#define HPM_DMA_SRC_I2S1_RX (0x1AUL) +#define HPM_DMA_SRC_I2S1_TX (0x1BUL) +#define HPM_DMA_SRC_MOT0_0 (0x1CUL) +#define HPM_DMA_SRC_MOT0_1 (0x1DUL) +#define HPM_DMA_SRC_MOT0_2 (0x1EUL) +#define HPM_DMA_SRC_MOT0_3 (0x1FUL) +#define HPM_DMA_SRC_MOT1_0 (0x20UL) +#define HPM_DMA_SRC_MOT1_1 (0x21UL) +#define HPM_DMA_SRC_MOT1_2 (0x22UL) +#define HPM_DMA_SRC_MOT1_3 (0x23UL) +#define HPM_DMA_SRC_NTMR0_0 (0x24UL) +#define HPM_DMA_SRC_NTMR0_1 (0x25UL) +#define HPM_DMA_SRC_NTMR0_2 (0x26UL) +#define HPM_DMA_SRC_NTMR0_3 (0x27UL) +#define HPM_DMA_SRC_GPTMR0_0 (0x28UL) +#define HPM_DMA_SRC_GPTMR0_1 (0x29UL) +#define HPM_DMA_SRC_GPTMR0_2 (0x2AUL) +#define HPM_DMA_SRC_GPTMR0_3 (0x2BUL) +#define HPM_DMA_SRC_GPTMR1_0 (0x2CUL) +#define HPM_DMA_SRC_GPTMR1_1 (0x2DUL) +#define HPM_DMA_SRC_GPTMR1_2 (0x2EUL) +#define HPM_DMA_SRC_GPTMR1_3 (0x2FUL) +#define HPM_DMA_SRC_GPTMR2_0 (0x30UL) +#define HPM_DMA_SRC_GPTMR2_1 (0x31UL) +#define HPM_DMA_SRC_GPTMR2_2 (0x32UL) +#define HPM_DMA_SRC_GPTMR2_3 (0x33UL) +#define HPM_DMA_SRC_GPTMR3_0 (0x34UL) +#define HPM_DMA_SRC_GPTMR3_1 (0x35UL) +#define HPM_DMA_SRC_GPTMR3_2 (0x36UL) +#define HPM_DMA_SRC_GPTMR3_3 (0x37UL) +#define HPM_DMA_SRC_I2C0 (0x38UL) +#define HPM_DMA_SRC_I2C1 (0x39UL) +#define HPM_DMA_SRC_I2C2 (0x3AUL) +#define HPM_DMA_SRC_I2C3 (0x3BUL) +#define HPM_DMA_SRC_XPI0_RX (0x3CUL) +#define HPM_DMA_SRC_XPI0_TX (0x3DUL) +#define HPM_DMA_SRC_XPI1_RX (0x3EUL) +#define HPM_DMA_SRC_XPI1_TX (0x3FUL) +#define HPM_DMA_SRC_DAC (0x40UL) +#define HPM_DMA_SRC_ACMP_0 (0x41UL) +#define HPM_DMA_SRC_ACMP_1 (0x42UL) + + + +#endif /* HPM_DMAMUX_SRC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h new file mode 100644 index 0000000000..449405b137 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_enet_soc_drv.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ENET_SOC_DRV_H +#define HPM_ENET_SOC_DRV_H + +#include "hpm_soc.h" + +#if defined __cplusplus +extern "C" { +#endif + +static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) +{ + hpm_stat_t stat = status_fail; + + return stat; +} + +static inline hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal) +{ + hpm_stat_t stat = status_success; + + /* use an internal PLL clock as reference clock for rmii mode */ + if (ptr == HPM_ENET0) { + if (internal == true) { + /* use a pll clock */ + ptr->CTRL2 |= ENET_CTRL2_ENET0_REFCLK_OE_MASK | ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; + } else { + /* use an external clock as reference clock for rmii mode */ + ptr->CTRL2 |= ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; /* use an external clock */ + } + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + ptr->CTRL2 &= ~ENET_CTRL2_ENET0_PHY_INF_SEL_MASK; + ptr->CTRL2 |= ENET_CTRL2_ENET0_PHY_INF_SEL_SET(inf_type); + } else { + return status_invalid_argument; + } + + return stat; +} + +#if defined __cplusplus +} /* __cplusplus */ +#endif + +#endif /* HPM_ENET_SOC_DRV_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h new file mode 100644 index 0000000000..3ac71c4c38 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPIOM_H +#define HPM_GPIOM_H + +typedef struct { + struct { + __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ + } ASSIGN[16]; +} GPIOM_Type; + + +/* Bitfield definition for register of struct array ASSIGN: PIN00 */ +/* + * LOCK (RW) + * + * lock fields in this register, lock can only be cleared by soc reset + * 0: fields can be changed + * 1: fields locked to current value, not changeable + */ +#define GPIOM_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_PIN_LOCK_SHIFT (31U) +#define GPIOM_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_PIN_LOCK_SHIFT) & GPIOM_PIN_LOCK_MASK) +#define GPIOM_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_PIN_LOCK_MASK) >> GPIOM_PIN_LOCK_SHIFT) + +/* + * HIDE (RW) + * + * pin value visibility to gpios, + * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 + * bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + */ +#define GPIOM_PIN_HIDE_MASK (0x300U) +#define GPIOM_PIN_HIDE_SHIFT (8U) +#define GPIOM_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_PIN_HIDE_SHIFT) & GPIOM_PIN_HIDE_MASK) +#define GPIOM_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_PIN_HIDE_MASK) >> GPIOM_PIN_HIDE_SHIFT) + +/* + * SELECT (RW) + * + * select which gpio controls chip pin, + * 0: soc gpio0; + * 1: cpu0 fastgpio + */ +#define GPIOM_PIN_SELECT_MASK (0x1U) +#define GPIOM_PIN_SELECT_SHIFT (0U) +#define GPIOM_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_PIN_SELECT_SHIFT) & GPIOM_PIN_SELECT_MASK) +#define GPIOM_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_PIN_SELECT_MASK) >> GPIOM_PIN_SELECT_SHIFT) + + + +/* PIN register group index macro definition */ +#define GPIOM_ASSIGN_PIN_PIN00 (0UL) +#define GPIOM_ASSIGN_PIN_PIN01 (1UL) +#define GPIOM_ASSIGN_PIN_PIN02 (2UL) +#define GPIOM_ASSIGN_PIN_PIN03 (3UL) +#define GPIOM_ASSIGN_PIN_PIN04 (4UL) +#define GPIOM_ASSIGN_PIN_PIN05 (5UL) +#define GPIOM_ASSIGN_PIN_PIN06 (6UL) +#define GPIOM_ASSIGN_PIN_PIN07 (7UL) +#define GPIOM_ASSIGN_PIN_PIN08 (8UL) +#define GPIOM_ASSIGN_PIN_PIN09 (9UL) +#define GPIOM_ASSIGN_PIN_PIN10 (10UL) +#define GPIOM_ASSIGN_PIN_PIN11 (11UL) +#define GPIOM_ASSIGN_PIN_PIN12 (12UL) +#define GPIOM_ASSIGN_PIN_PIN13 (13UL) +#define GPIOM_ASSIGN_PIN_PIN14 (14UL) +#define GPIOM_ASSIGN_PIN_PIN15 (15UL) +#define GPIOM_ASSIGN_PIN_PIN16 (16UL) +#define GPIOM_ASSIGN_PIN_PIN17 (17UL) +#define GPIOM_ASSIGN_PIN_PIN18 (18UL) +#define GPIOM_ASSIGN_PIN_PIN19 (19UL) +#define GPIOM_ASSIGN_PIN_PIN20 (20UL) +#define GPIOM_ASSIGN_PIN_PIN21 (21UL) +#define GPIOM_ASSIGN_PIN_PIN22 (22UL) +#define GPIOM_ASSIGN_PIN_PIN23 (23UL) +#define GPIOM_ASSIGN_PIN_PIN24 (24UL) +#define GPIOM_ASSIGN_PIN_PIN25 (25UL) +#define GPIOM_ASSIGN_PIN_PIN26 (26UL) +#define GPIOM_ASSIGN_PIN_PIN27 (27UL) +#define GPIOM_ASSIGN_PIN_PIN28 (28UL) +#define GPIOM_ASSIGN_PIN_PIN29 (29UL) +#define GPIOM_ASSIGN_PIN_PIN30 (30UL) +#define GPIOM_ASSIGN_PIN_PIN31 (31UL) + +/* ASSIGN register group index macro definition */ +#define GPIOM_ASSIGN_GPIOA (0UL) +#define GPIOM_ASSIGN_GPIOB (1UL) +#define GPIOM_ASSIGN_GPIOC (2UL) +#define GPIOM_ASSIGN_GPIOX (13UL) +#define GPIOM_ASSIGN_GPIOY (14UL) +#define GPIOM_ASSIGN_GPIOZ (15UL) + + +#endif /* HPM_GPIOM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h new file mode 100644 index 0000000000..e4b460359a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIOM_SOC_DRV_H +#define HPM_GPIOM_SOC_DRV_H + +/** + * @addtogroup gpiom_interface GPIOM driver APIs + * @{ + */ + +/* @brief gpiom control module */ +typedef enum hpm6300_gpiom_gpio { + gpiom_soc_gpio0 = 0, + gpiom_core0_fast = 1, +} gpiom_gpio_t; + +/** + * @} + */ + +#endif /* HPM_GPIOM_SOC_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h new file mode 100644 index 0000000000..afbf13d54f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h @@ -0,0 +1,947 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_INTERRUPT_H +#define HPM_INTERRUPT_H +#include "riscv/riscv_core.h" +#include "hpm_common.h" +#include "hpm_plic_drv.h" + +/** + * @brief INTERRUPT driver APIs + * @defgroup irq_interface INTERRUPT driver APIs + * @{ + */ + +#define M_MODE 0 /*!< Machine mode */ +#define S_MODE 1 /*!< Supervisor mode */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Machine mode API: these APIs are supposed to be called at machine mode */ + +/** + * @brief Enable global IRQ with mask + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask + * + * @param[in] mask interrupt mask to be disabled + */ +ATTR_ALWAYS_INLINE static inline void disable_global_irq(uint32_t mask) +{ + clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Enable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) +{ + set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Disable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ + */ +ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) +{ + set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Delegate IRQ handling + * + * @param[in] mask interrupt mask to be delegated + */ +ATTR_ALWAYS_INLINE static inline void delegate_irq(uint32_t mask) +{ + set_csr(CSR_MIDELEG, mask); +} + +/** + * @brief Undelegate IRQ handling + * + * @param[in] mask interrupt mask to be undelegated + */ +ATTR_ALWAYS_INLINE static inline void undelegate_irq(uint32_t mask) +{ + clear_csr(CSR_MIDELEG, mask); +} + + +/* Supervisor mode API: these APIs are supposed to be called at supervisor mode */ + +/** + * @brief Enable global IRQ with mask for supervisor mode + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_s_global_irq(uint32_t mask) +{ + set_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask for supervisor mode + * + * @param[in] mask interrupt mask to be disabled + */ +ATTR_ALWAYS_INLINE static inline void disable_s_global_irq(uint32_t mask) +{ + clear_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Disable IRQ from interrupt controller for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void disable_s_irq_from_intc(void) +{ + clear_csr(CSR_SIE, CSR_SIE_SEIE_MASK); +} + +/** + * @brief Enable IRQ from interrupt controller for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void enable_s_irq_from_intc(void) +{ + set_csr(CSR_SIE, CSR_SIE_SEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ for supervisor mode + */ +ATTR_ALWAYS_INLINE static inline void enable_s_mchtmr_irq(void) +{ + set_csr(CSR_SIE, CSR_SIE_STIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_s_mchtmr_irq(void) +{ + clear_csr(CSR_SIE, CSR_SIE_STIE_MASK); +} + + +/* + * CPU Machine SWI control + * + * Machine SWI (MSIP) is connected to PLICSW irq 1. + */ +#define PLICSWI 1 + +/** + * @brief Initialize software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) +{ + __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + + +/** + * @brief Enable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) +{ + set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Disable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Trigger software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) +{ + __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); +} + +/** + * @brief Claim software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) +{ + __plic_claim_irq(HPM_PLICSW_BASE, 0); +} + +/** + * @brief Complete software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) +{ + __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + +/* + * @brief Enable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Disable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +#define intc_m_set_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) + +/* + * @brief Complete IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Claim IRQ for machine mode + * + */ +#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) + +/* + * @brief Enable IRQ for machine mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_m_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_m_enable_irq(irq); \ + } while (0) + + + +/* Supervisor mode */ + +/** + * @brief Enable software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_enable_swi(void) +{ + set_csr(CSR_SIE, CSR_SIE_SSIE_MASK); +} + + +/** + * @brief Disable software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_disable_swi(void) +{ + clear_csr(CSR_SIE, CSR_SIE_SSIE_MASK); +} + + +/** + * @brief Trigger software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_trigger_swi(void) +{ + set_csr(CSR_SIP, CSR_SIP_SSIP_MASK); +} + + +/** + * @brief Complete software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_complete_swi(void) +{ + clear_csr(CSR_SIP, CSR_SIP_SSIP_MASK); +} + +/* + * @brief Enable IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_S_MODE, irq) + +/* + * @brief Disable IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_S_MODE, irq) + +#define intc_set_s_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_S_MODE, threshold) + +/* + * @brief Complete IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_S_MODE, irq) + +/* + * @brief Claim IRQ for supervisor mode + * + */ +#define intc_s_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_S_MODE) + +/* + * @brief Enable IRQ for supervisor mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_s_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_s_enable_irq(irq); \ + } while (0) + + +/* + * @brief Enable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) +{ + __plic_enable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) +{ + __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); +} + +/** + * @brief Disable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) +{ + __plic_disable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt threshold + * + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + */ +ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) +{ + __plic_set_threshold(HPM_PLIC_BASE, target, threshold); +} + +/** + * @brief Claim IRQ + * + * @param[in] target Target to handle specific interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) +{ + return __plic_claim_irq(HPM_PLIC_BASE, target); +} + +/** + * @brief Complete IRQ + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Specific IRQ to be completed + * + */ +ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) +{ + __plic_complete_irq(HPM_PLIC_BASE, target, irq); +} + +/* + * Vectored based irq install and uninstall + */ +/* Machine mode */ +extern int __vector_table[]; +extern void default_irq_entry(void); + +/** + * @brief Install ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) +{ + __vector_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) +{ + __vector_table[irq] = (int) default_irq_entry; +} + +/* Supervisor mode */ +extern int __vector_s_table[]; +extern void default_s_irq_entry(void); +/** + * @brief Install ISR for certain IRQ for ram based vector table for supervisor mode + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_s_isr(uint32_t irq, uint32_t isr) +{ + __vector_s_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table for supervisor mode + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) +{ + __vector_s_table[irq] = (int) default_s_irq_entry; +} + + +/* + * Inline nested irq entry/exit macros + */ +/* + * @brief Save CSR + * @param[in] r Target CSR to be saved + */ +#define SAVE_CSR(r) register long __##r = read_csr(r); + +/* + * @brief Restore macro + * + * @param[in] r Target CSR to be restored + */ +#define RESTORE_CSR(r) write_csr(r, __##r); + +#if SUPPORT_PFT_ARCH +#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) +#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) +#else +#define SAVE_MXSTATUS() +#define RESTORE_MXSTATUS() +#endif + +#ifdef __riscv_flen +#define SAVE_FCSR() register int __fcsr = read_fcsr(); +#define RESTORE_FCSR() write_fcsr(__fcsr); +#else +#define SAVE_FCSR() +#define RESTORE_FCSR() +#endif + +#ifdef __riscv_dsp +#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) +#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) +#else +#define SAVE_UCODE() +#define RESTORE_UCODE() +#endif + +#ifdef __riscv_flen +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP) + 21 FPU caller registers */ +#define CONTEXT_REG_NUM (4*(16 + 4 + 1 + 21)) +#else +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ +#define CONTEXT_REG_NUM (4*(16 + 4 + 1)) +#endif + +#ifdef __riscv_flen +/* + * Save FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack + */ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("fsw ft0, 21*4(sp) \n\ + fsw ft1, 22*4(sp) \n\ + fsw ft2, 23*4(sp) \n\ + fsw ft3, 24*4(sp) \n\ + fsw ft4, 25*4(sp) \n\ + fsw ft5, 26*4(sp) \n\ + fsw ft6, 27*4(sp) \n\ + fsw ft7, 28*4(sp) \n\ + fsw fa0, 29*4(sp) \n\ + fsw fa1, 30*4(sp) \n\ + fsw fa2, 31*4(sp) \n\ + fsw fa3, 32*4(sp) \n\ + fsw fa4, 33*4(sp) \n\ + fsw fa5, 34*4(sp) \n\ + fsw fa6, 35*4(sp) \n\ + fsw fa7, 36*4(sp) \n\ + fsw ft8, 37*4(sp) \n\ + fsw ft9, 38*4(sp) \n\ + fsw ft10, 39*4(sp) \n\ + fsw ft11, 40*4(sp) \n\ + frsr t6 \n\ + sw t6, 41*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("flw ft0, 21*4(sp) \n\ + flw ft1, 22*4(sp) \n\ + flw ft2, 23*4(sp) \n\ + flw ft3, 24*4(sp) \n\ + flw ft4, 25*4(sp) \n\ + flw ft5, 26*4(sp) \n\ + flw ft6, 27*4(sp) \n\ + flw ft7, 28*4(sp) \n\ + flw fa0, 29*4(sp) \n\ + flw fa1, 30*4(sp) \n\ + flw fa2, 31*4(sp) \n\ + flw fa3, 32*4(sp) \n\ + flw fa4, 33*4(sp) \n\ + flw fa5, 34*4(sp) \n\ + flw fa6, 35*4(sp) \n\ + flw fa7, 36*4(sp) \n\ + flw ft8, 37*4(sp) \n\ + flw ft9, 38*4(sp) \n\ + flw ft10, 39*4(sp) \n\ + flw ft11, 40*4(sp) \n\ + lw t6, 41*4(sp) \n\ + fssr t6, t6 \n");\ +} +#else +#define SAVE_FPU_CONTEXT() +#define RESTORE_FPU_CONTEXT() +#endif + +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("sw ra, 0*4(sp) \n\ + sw t0, 1*4(sp) \n\ + sw t1, 2*4(sp) \n\ + sw t2, 3*4(sp) \n\ + sw a0, 4*4(sp) \n\ + sw a1, 5*4(sp) \n\ + sw a2, 6*4(sp) \n\ + sw a3, 7*4(sp) \n\ + sw a4, 8*4(sp) \n\ + sw a5, 9*4(sp) \n\ + sw a6, 10*4(sp) \n\ + sw a7, 11*4(sp) \n\ + sw t3, 12*4(sp) \n\ + sw t4, 13*4(sp) \n\ + sw t5, 14*4(sp) \n\ + sw t6, 15*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("lw ra, 0*4(sp) \n\ + lw t0, 1*4(sp) \n\ + lw t1, 2*4(sp) \n\ + lw t2, 3*4(sp) \n\ + lw a0, 4*4(sp) \n\ + lw a1, 5*4(sp) \n\ + lw a2, 6*4(sp) \n\ + lw a3, 7*4(sp) \n\ + lw a4, 8*4(sp) \n\ + lw a5, 9*4(sp) \n\ + lw a6, 10*4(sp) \n\ + lw a7, 11*4(sp) \n\ + lw t3, 12*4(sp) \n\ + lw t4, 13*4(sp) \n\ + lw t5, 14*4(sp) \n\ + lw t6, 15*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} + +#ifdef __riscv_dsp +/* + * Save DSP context + * NOTE: To simplify the logic, DSP context registers are always stored at word offset 20 in the stack + */ +#define SAVE_DSP_CONTEXT() { \ + __asm volatile("csrr t6, ucode\n\ + sw t6, 20*4(sp)\n"); \ +} +/* + * @brief Restore DSP context + * @note To simplify the logic, DSP context registers are always stored at word offset 20 in the stack + */ +#define RESTORE_DSP_CONTEXT() {\ + __asm volatile("lw t6, 20*4(sp)\n\ + csrw ucode, t6 \n"); \ +} +#else +#define SAVE_DSP_CONTEXT() +#define RESTORE_DSP_CONTEXT() +#endif + +/* + * @brief Enter Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define ENTER_NESTED_IRQ_HANDLING_M() {\ + __asm volatile("csrr t6, mepc \n\ + sw t6, 17*4(sp) \n\ + csrr t6, mstatus \n\ + sw t6, 18*4(sp) \n\ + csrr t6, %0\n\ + sw t6, 19*4(sp) \n\ + " : : "i" CSR_MSTATUS);\ + SAVE_DSP_CONTEXT(); \ + __asm volatile("li t6, %0\n" : : "i" (CSR_MSTATUS_MIE_MASK)); \ + __asm volatile("csrrs t6, mstatus, t6\n"); \ +} +#define COMPLETE_IRQ_HANDLING_M(irq_num) {\ + __asm volatile("li t0, 0xe4000000 \n\ + li t1, 0x200004 \n\ + add t0, t0, t1 \n\ + lui t1, 0 \n\ + slli t2, t1, 0xc \n\ + add t0, t0, t2 \n");\ + __asm volatile("li t1, %0" : : "i" (irq_num) :); \ + __asm volatile("sw t1, 0(t0) \n\ + fence io, io \n\ + li t6, 1\n\ + addi t6, t6, -0x800\n\ + csrrs t6, mie, t6 \n"); \ +} + +#define ENTER_NESTED_IRQ_HANDLING_S() {\ + __asm volatile("csrr t6, sepc \n\ + sw t6, 17*4(sp) \n\ + csrr t6, sstatus \n\ + sw t6, 18*4(sp) \n\ + csrr t6, %0\n\ + sw t6, 19*4(sp) \n\ + " : : "i" CSR_SSTATUS);\ + SAVE_DSP_CONTEXT(); \ + __asm volatile("li t6, %0\n" : : "i" (CSR_SSTATUS_SIE_MASK)); \ + __asm volatile("csrrs t6, sstatus, t6\n"); \ +} +#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ + __asm volatile("li t0, 0xe4000000 \n\ + li t1, 0x201004 \n\ + add t0, t0, t1 \n\ + lui t1, 0 \n\ + slli t2, t1, 0xc \n\ + add t0, t0, t2 \n");\ + __asm volatile("li t1, %0" : : "i" (irq_num) :); \ + __asm volatile("sw t1, 0(t0) \n\ + fence io, io \n\ + li t6, 1\n\ + addi t6, t6, -0x200\n\ + csrrs t6, sie, t6 \n"); \ +} + + +/* + * @brief Exit Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define EXIT_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("csrrci t6, mstatus, 8 \n\ + lw t6, 18*4(sp) \n\ + csrw mstatus, t6 \n\ + lw t6, 17*4(sp) \n\ + csrw mepc, t6 \n\ + lw t6, 19*4(sp) \n\ + csrw %0, t6 \n" : : "i" CSR_MSTATUS);\ + RESTORE_DSP_CONTEXT(); \ +} + +/* + * @brief Exit Nested IRQ Handling at supervisor mode + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * SCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * SSTATUS = word offset 18 + */ +#define EXIT_NESTED_IRQ_HANDLING_S() { \ + __asm volatile("csrrci t6, sstatus, 2 \n\ + lw t6, 18*4(sp) \n\ + csrw sstatus, t6 \n\ + lw t6, 17*4(sp) \n\ + csrw sepc, t6 \n\ + lw t6, 19*4(sp) \n\ + csrw %0, t6 \n" : : "i" CSR_SSTATUS);\ + RESTORE_DSP_CONTEXT(); \ +} + +/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ +#define NESTED_IRQ_ENTER() \ + SAVE_CSR(CSR_MEPC) \ + SAVE_CSR(CSR_MSTATUS) \ + SAVE_MXSTATUS() \ + SAVE_FCSR() \ + SAVE_UCODE() \ + set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +/* @brief Nested IRQ exit macro : Restore CSRs */ +#define NESTED_IRQ_EXIT() \ + clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); \ + RESTORE_CSR(CSR_MSTATUS) \ + RESTORE_CSR(CSR_MEPC) \ + RESTORE_MXSTATUS() \ + RESTORE_FCSR() \ + RESTORE_UCODE() + +/* + * @brief Nested IRQ exit macro : Restore CSRs + * @param[in] irq Target interrupt number + */ +#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ +do { \ + clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ + __asm volatile("fence io, io"); \ + set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ +} while (0) + +#ifdef __cplusplus +#define EXTERN_C extern "C" +#else +#define EXTERN_C +#endif + +#define ISR_NAME_M(irq_num) default_isr_##irq_num +#define ISR_NAME_S(irq_num) default_isr_s_##irq_num +/** + * @brief Declare an external interrupt handler for machine mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#ifndef USE_NONVECTOR_MODE + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) {\ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_M();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + EXIT_NESTED_IRQ_HANDLING_M();\ + COMPLETE_IRQ_HANDLING_M(irq_num);\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("mret\n");\ +} + +/** + * @brief Declare an external interrupt handler for supervisor mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_s_vector")));\ +EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_s_vector")));\ +void ISR_NAME_S(irq_num)(void) {\ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_S();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + EXIT_NESTED_IRQ_HANDLING_S();\ + COMPLETE_IRQ_HANDLING_S(irq_num);\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("sret\n");\ +} + +#else + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) { \ + isr(); \ +} + +#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_S(irq_num)(void) { \ + isr(); \ +} + +#endif + + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_isr(void) {\ + isr();\ +} + +/* Supervisor mode */ + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR_S(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void mchtmr_s_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_s_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR_S(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void swi_s_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_s_isr(void) {\ + isr();\ +} + +#define CSR_MSTATUS_MPP_S_MODE (0x1) +#define MODE_SWITCH_FROM_M(mstatus, mepc, label, mode) \ +do { \ + if (label) { \ + write_csr(mepc, label); \ + } \ + clear_csr(mstatus, CSR_MSTATUS_MPP_MASK); \ + set_csr(mstatus, CSR_MSTATUS_MPP_SET(mode)); \ +} while(0) + +typedef void (*s_mode_entry)(void); + +/** + * @brief Switch mode to supervisor from machine + * + * @param[in] entry - entry point after mode is switched + */ +static inline void switch_to_s_mode(s_mode_entry entry) +{ + write_csr(CSR_SEPC, entry); + MODE_SWITCH_FROM_M(CSR_MSTATUS, CSR_MEPC, entry, CSR_MSTATUS_MPP_S_MODE); + if (entry) { + __asm("mret"); + } +} +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h new file mode 100644 index 0000000000..c38a47cea2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOC_H +#define HPM_IOC_H + +typedef struct { + struct { + __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ + __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ + } PAD[492]; +} IOC_Type; + + +/* Bitfield definition for register of struct array PAD: FUNC_CTL */ +/* + * LOOP_BACK (RW) + * + * force input on + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) + +/* + * ANALOG (RW) + * + * select analog pin in pad + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) +#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) +#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) +#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) + +/* + * ALT_SELECT (RW) + * + * alt select + * 0: ALT0 + * 1: ALT1 + * … + * 31:ALT31 + */ +#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) + +/* Bitfield definition for register of struct array PAD: PAD_CTL */ +/* + * HYS (RW) + * + * schmitt trigger enable + * 0: disable + * 1: enable + */ +#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) +#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) +#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) +#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) + +/* + * PRS (RW) + * + * select pull up/down internal resistance strength: + * For pull down, only have 100 Kohm resistance + * For pull up: + * 00: 100 KOhm + * 01: 47 KOhm + * 10: 22 KOhm + * 11: 22 KOhm + */ +#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) +#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) +#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) +#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) + +/* + * PS (RW) + * + * pull select + * 0: pull down + * 1: pull up + */ +#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) +#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) +#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) +#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) + +/* + * PE (RW) + * + * pull enable + * 0: pull disable + * 1: pull enable + */ +#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) +#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) +#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) +#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) + +/* + * KE (RW) + * + * keeper capability enable + * 0: keeper disable + * 1: keeper enable + */ +#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) +#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) +#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) +#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) + +/* + * OD (RW) + * + * open drain + * 0: open drain disable + * 1: open drain enable + */ +#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) +#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) +#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) +#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) + +/* + * SR (RW) + * + * slew rate + * 0: Slow slew rate + * 1: Fast slew rate + */ +#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) +#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) +#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) +#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) + +/* + * SPD (RW) + * + * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise + * 00: Slow frequency slew rate(50Mhz) + * 01: Medium frequency slew rate(100 Mhz) + * 10: Fast frequency slew rate(150 Mhz) + * 11: Max frequency slew rate(200Mhz) + */ +#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) +#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) +#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) +#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) + +/* + * DS (RW) + * + * drive strength + * 1.8V Mode: + * 000: 260 Ohm + * 001: 260 Ohm + * 010: 130 Ohm + * 011: 88 Ohm + * 100: 65 Ohm + * 101: 52 Ohm + * 110: 43 Ohm + * 111: 37 Ohm + * 3.3V Mode: + * 000: 157 Ohm + * 001: 157 Ohm + * 010: 78 Ohm + * 011: 53 Ohm + * 100: 39 Ohm + * 101: 32 Ohm + * 110: 26 Ohm + * 111: 23 Ohm + */ +#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) +#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) +#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) +#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) + + + +/* PAD register group index macro definition */ +#define IOC_PAD_PA00 (0UL) +#define IOC_PAD_PA01 (1UL) +#define IOC_PAD_PA02 (2UL) +#define IOC_PAD_PA03 (3UL) +#define IOC_PAD_PA04 (4UL) +#define IOC_PAD_PA05 (5UL) +#define IOC_PAD_PA06 (6UL) +#define IOC_PAD_PA07 (7UL) +#define IOC_PAD_PA08 (8UL) +#define IOC_PAD_PA09 (9UL) +#define IOC_PAD_PA10 (10UL) +#define IOC_PAD_PA11 (11UL) +#define IOC_PAD_PA12 (12UL) +#define IOC_PAD_PA13 (13UL) +#define IOC_PAD_PA14 (14UL) +#define IOC_PAD_PA15 (15UL) +#define IOC_PAD_PA16 (16UL) +#define IOC_PAD_PA17 (17UL) +#define IOC_PAD_PA18 (18UL) +#define IOC_PAD_PA19 (19UL) +#define IOC_PAD_PA20 (20UL) +#define IOC_PAD_PA21 (21UL) +#define IOC_PAD_PA22 (22UL) +#define IOC_PAD_PA23 (23UL) +#define IOC_PAD_PA24 (24UL) +#define IOC_PAD_PA25 (25UL) +#define IOC_PAD_PA26 (26UL) +#define IOC_PAD_PA27 (27UL) +#define IOC_PAD_PA28 (28UL) +#define IOC_PAD_PA29 (29UL) +#define IOC_PAD_PA30 (30UL) +#define IOC_PAD_PA31 (31UL) +#define IOC_PAD_PB00 (32UL) +#define IOC_PAD_PB01 (33UL) +#define IOC_PAD_PB02 (34UL) +#define IOC_PAD_PB03 (35UL) +#define IOC_PAD_PB04 (36UL) +#define IOC_PAD_PB05 (37UL) +#define IOC_PAD_PB06 (38UL) +#define IOC_PAD_PB07 (39UL) +#define IOC_PAD_PB08 (40UL) +#define IOC_PAD_PB09 (41UL) +#define IOC_PAD_PB10 (42UL) +#define IOC_PAD_PB11 (43UL) +#define IOC_PAD_PB12 (44UL) +#define IOC_PAD_PB13 (45UL) +#define IOC_PAD_PB14 (46UL) +#define IOC_PAD_PB15 (47UL) +#define IOC_PAD_PB16 (48UL) +#define IOC_PAD_PB17 (49UL) +#define IOC_PAD_PB18 (50UL) +#define IOC_PAD_PB19 (51UL) +#define IOC_PAD_PB20 (52UL) +#define IOC_PAD_PB21 (53UL) +#define IOC_PAD_PB22 (54UL) +#define IOC_PAD_PB23 (55UL) +#define IOC_PAD_PB24 (56UL) +#define IOC_PAD_PB25 (57UL) +#define IOC_PAD_PB26 (58UL) +#define IOC_PAD_PB27 (59UL) +#define IOC_PAD_PB28 (60UL) +#define IOC_PAD_PB29 (61UL) +#define IOC_PAD_PB30 (62UL) +#define IOC_PAD_PB31 (63UL) +#define IOC_PAD_PC00 (64UL) +#define IOC_PAD_PC01 (65UL) +#define IOC_PAD_PC02 (66UL) +#define IOC_PAD_PC03 (67UL) +#define IOC_PAD_PC04 (68UL) +#define IOC_PAD_PC05 (69UL) +#define IOC_PAD_PC06 (70UL) +#define IOC_PAD_PC07 (71UL) +#define IOC_PAD_PC08 (72UL) +#define IOC_PAD_PC09 (73UL) +#define IOC_PAD_PC10 (74UL) +#define IOC_PAD_PC11 (75UL) +#define IOC_PAD_PC12 (76UL) +#define IOC_PAD_PC13 (77UL) +#define IOC_PAD_PC14 (78UL) +#define IOC_PAD_PC15 (79UL) +#define IOC_PAD_PC16 (80UL) +#define IOC_PAD_PC17 (81UL) +#define IOC_PAD_PC18 (82UL) +#define IOC_PAD_PC19 (83UL) +#define IOC_PAD_PC20 (84UL) +#define IOC_PAD_PC21 (85UL) +#define IOC_PAD_PC22 (86UL) +#define IOC_PAD_PC23 (87UL) +#define IOC_PAD_PC24 (88UL) +#define IOC_PAD_PC25 (89UL) +#define IOC_PAD_PC26 (90UL) +#define IOC_PAD_PC27 (91UL) +#define IOC_PAD_PC28 (92UL) +#define IOC_PAD_PC29 (93UL) +#define IOC_PAD_PC30 (94UL) +#define IOC_PAD_PC31 (95UL) +#define IOC_PAD_PD00 (96UL) +#define IOC_PAD_PD01 (97UL) +#define IOC_PAD_PD02 (98UL) +#define IOC_PAD_PD03 (99UL) +#define IOC_PAD_PD04 (100UL) +#define IOC_PAD_PD05 (101UL) +#define IOC_PAD_PD06 (102UL) +#define IOC_PAD_PD07 (103UL) +#define IOC_PAD_PD08 (104UL) +#define IOC_PAD_PD09 (105UL) +#define IOC_PAD_PD10 (106UL) +#define IOC_PAD_PD11 (107UL) +#define IOC_PAD_PD12 (108UL) +#define IOC_PAD_PD13 (109UL) +#define IOC_PAD_PD14 (110UL) +#define IOC_PAD_PD15 (111UL) +#define IOC_PAD_PD16 (112UL) +#define IOC_PAD_PD17 (113UL) +#define IOC_PAD_PD18 (114UL) +#define IOC_PAD_PD19 (115UL) +#define IOC_PAD_PD20 (116UL) +#define IOC_PAD_PD21 (117UL) +#define IOC_PAD_PD22 (118UL) +#define IOC_PAD_PD23 (119UL) +#define IOC_PAD_PX00 (416UL) +#define IOC_PAD_PX01 (417UL) +#define IOC_PAD_PX02 (418UL) +#define IOC_PAD_PX03 (419UL) +#define IOC_PAD_PX04 (420UL) +#define IOC_PAD_PX05 (421UL) +#define IOC_PAD_PX06 (422UL) +#define IOC_PAD_PX07 (423UL) +#define IOC_PAD_PY00 (448UL) +#define IOC_PAD_PY01 (449UL) +#define IOC_PAD_PY02 (450UL) +#define IOC_PAD_PY03 (451UL) +#define IOC_PAD_PY04 (452UL) +#define IOC_PAD_PY05 (453UL) +#define IOC_PAD_PY06 (454UL) +#define IOC_PAD_PY07 (455UL) +#define IOC_PAD_PY08 (456UL) +#define IOC_PAD_PY09 (457UL) +#define IOC_PAD_PY10 (458UL) +#define IOC_PAD_PY11 (459UL) +#define IOC_PAD_PZ00 (480UL) +#define IOC_PAD_PZ01 (481UL) +#define IOC_PAD_PZ02 (482UL) +#define IOC_PAD_PZ03 (483UL) +#define IOC_PAD_PZ04 (484UL) +#define IOC_PAD_PZ05 (485UL) +#define IOC_PAD_PZ06 (486UL) +#define IOC_PAD_PZ07 (487UL) +#define IOC_PAD_PZ08 (488UL) +#define IOC_PAD_PZ09 (489UL) +#define IOC_PAD_PZ10 (490UL) +#define IOC_PAD_PZ11 (491UL) + + +#endif /* HPM_IOC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h new file mode 100644 index 0000000000..5b1a771099 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h @@ -0,0 +1,1256 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOMUX_H +#define HPM_IOMUX_H + +/* IOC_PA00_FUNC_CTL function mux definitions */ +#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA00_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA00_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA00_FUNC_CTL_XPI_SLV_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA01_FUNC_CTL function mux definitions */ +#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA01_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA01_FUNC_CTL_XPI_SLV_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA02_FUNC_CTL function mux definitions */ +#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA02_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA02_FUNC_CTL_XPI_SLV_ADQ_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA03_FUNC_CTL function mux definitions */ +#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA03_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA03_FUNC_CTL_XPI_SLV_ADQ_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA04_FUNC_CTL function mux definitions */ +#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA04_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA04_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA04_FUNC_CTL_XPI_SLV_ADQ_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA05_FUNC_CTL function mux definitions */ +#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA05_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA05_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA05_FUNC_CTL_ADC2_DBG IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA05_FUNC_CTL_XPI_SLV_ADQ_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA06_FUNC_CTL function mux definitions */ +#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA06_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA06_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA06_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA06_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA06_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA06_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA06_FUNC_CTL_ADC1_DBG IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA06_FUNC_CTL_XPI_SLV_ADQ_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA07_FUNC_CTL function mux definitions */ +#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA07_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA07_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA07_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA07_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA07_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA07_FUNC_CTL_ADC0_DBG IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA07_FUNC_CTL_XPI_SLV_ADQ_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA08_FUNC_CTL function mux definitions */ +#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA08_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA08_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA08_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA08_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA08_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA08_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA08_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA08_FUNC_CTL_XPI_SLV_ADQ_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA09_FUNC_CTL function mux definitions */ +#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA09_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA09_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA09_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA09_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA09_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA09_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA09_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA09_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA09_FUNC_CTL_XPI_SLV_ADQ_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA10_FUNC_CTL function mux definitions */ +#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA10_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA10_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA10_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA10_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA10_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA10_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA10_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA10_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA11_FUNC_CTL function mux definitions */ +#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA11_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA11_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA11_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA11_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA11_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA11_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA11_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA12_FUNC_CTL function mux definitions */ +#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA12_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA12_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA12_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA12_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA12_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA12_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA12_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA13_FUNC_CTL function mux definitions */ +#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA13_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA13_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA13_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA13_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA13_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA13_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA13_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA14_FUNC_CTL function mux definitions */ +#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA14_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA14_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA14_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA14_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA14_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA14_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA14_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA14_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA14_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA15_FUNC_CTL function mux definitions */ +#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA15_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA15_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA15_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA15_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA15_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA15_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA15_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA15_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA15_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA16_FUNC_CTL function mux definitions */ +#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA16_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA16_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA16_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA16_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA16_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA16_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA16_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA16_FUNC_CTL_XPI_SLV_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA17_FUNC_CTL function mux definitions */ +#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA17_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA17_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA17_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA17_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA17_FUNC_CTL_XPI_SLV_RDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA18_FUNC_CTL function mux definitions */ +#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA18_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA18_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA18_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA18_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA18_FUNC_CTL_XPI_SLV_ERR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PA19_FUNC_CTL function mux definitions */ +#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA19_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA19_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA19_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA19_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA19_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA20_FUNC_CTL function mux definitions */ +#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA20_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA20_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA20_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA20_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA20_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA20_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA21_FUNC_CTL function mux definitions */ +#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA21_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA21_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA21_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA21_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA21_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA21_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA21_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA22_FUNC_CTL function mux definitions */ +#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA22_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA22_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA22_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA22_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA22_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA22_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA22_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA23_FUNC_CTL function mux definitions */ +#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA23_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA23_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA23_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA23_FUNC_CTL_DRAM_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA23_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA23_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA24_FUNC_CTL function mux definitions */ +#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA24_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA24_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA24_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA24_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA24_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA24_FUNC_CTL_DRAM_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA24_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA24_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA25_FUNC_CTL function mux definitions */ +#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA25_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA25_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA25_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA25_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA25_FUNC_CTL_DRAM_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA25_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA25_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA25_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PA26_FUNC_CTL function mux definitions */ +#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA26_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA26_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA26_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA26_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA26_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA26_FUNC_CTL_DRAM_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA26_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA26_FUNC_CTL_ETH0_CRS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA26_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PA27_FUNC_CTL function mux definitions */ +#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA27_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA27_FUNC_CTL_DRAM_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA27_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA27_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PA28_FUNC_CTL function mux definitions */ +#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA28_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA28_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA28_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA28_FUNC_CTL_DRAM_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA28_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PA29_FUNC_CTL function mux definitions */ +#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA29_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA29_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA29_FUNC_CTL_DRAM_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA29_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PA30_FUNC_CTL function mux definitions */ +#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA30_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA30_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA30_FUNC_CTL_DRAM_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA30_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PA31_FUNC_CTL function mux definitions */ +#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA31_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA31_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA31_FUNC_CTL_DRAM_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PA31_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB00_FUNC_CTL function mux definitions */ +#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB00_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB00_FUNC_CTL_DRAM_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB01_FUNC_CTL function mux definitions */ +#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB01_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB01_FUNC_CTL_DRAM_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB02_FUNC_CTL function mux definitions */ +#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB02_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB02_FUNC_CTL_DRAM_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB03_FUNC_CTL function mux definitions */ +#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB03_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB03_FUNC_CTL_DRAM_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB03_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB04_FUNC_CTL function mux definitions */ +#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB04_FUNC_CTL_DRAM_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB04_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB05_FUNC_CTL function mux definitions */ +#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB05_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB05_FUNC_CTL_DRAM_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB05_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB06_FUNC_CTL function mux definitions */ +#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB06_FUNC_CTL_DRAM_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB07_FUNC_CTL function mux definitions */ +#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB07_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB07_FUNC_CTL_DRAM_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB07_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB08_FUNC_CTL function mux definitions */ +#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB08_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB08_FUNC_CTL_DRAM_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB08_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB08_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB09_FUNC_CTL function mux definitions */ +#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB09_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB09_FUNC_CTL_DRAM_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB09_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB09_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB10_FUNC_CTL function mux definitions */ +#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB10_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB10_FUNC_CTL_DRAM_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB10_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB10_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB11_FUNC_CTL function mux definitions */ +#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB11_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB11_FUNC_CTL_DRAM_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB11_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB11_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB12_FUNC_CTL function mux definitions */ +#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB12_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB12_FUNC_CTL_DRAM_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB12_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB13_FUNC_CTL function mux definitions */ +#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB13_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB13_FUNC_CTL_DRAM_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB13_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB14_FUNC_CTL function mux definitions */ +#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB14_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB14_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB14_FUNC_CTL_DRAM_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB14_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB15_FUNC_CTL function mux definitions */ +#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB15_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB15_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB15_FUNC_CTL_DRAM_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB15_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB16_FUNC_CTL function mux definitions */ +#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB16_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB16_FUNC_CTL_DRAM_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB16_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB17_FUNC_CTL function mux definitions */ +#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB17_FUNC_CTL_DRAM_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB17_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PB17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB18_FUNC_CTL function mux definitions */ +#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB18_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB18_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB18_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB18_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB18_FUNC_CTL_DRAM_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB19_FUNC_CTL function mux definitions */ +#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB19_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB19_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB19_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB19_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB19_FUNC_CTL_DRAM_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB20_FUNC_CTL function mux definitions */ +#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB20_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB20_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB20_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB20_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB20_FUNC_CTL_DRAM_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB21_FUNC_CTL function mux definitions */ +#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB21_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB21_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB21_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB21_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB21_FUNC_CTL_DRAM_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB22_FUNC_CTL function mux definitions */ +#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB22_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB22_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB22_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB22_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB22_FUNC_CTL_DRAM_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB22_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB23_FUNC_CTL function mux definitions */ +#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB23_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB23_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB23_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB23_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB23_FUNC_CTL_DRAM_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB23_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB24_FUNC_CTL function mux definitions */ +#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB24_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB24_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB24_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB24_FUNC_CTL_DRAM_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB24_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB25_FUNC_CTL function mux definitions */ +#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB25_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB25_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB25_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB25_FUNC_CTL_DRAM_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB25_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB26_FUNC_CTL function mux definitions */ +#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB26_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB26_FUNC_CTL_DRAM_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB26_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB27_FUNC_CTL function mux definitions */ +#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB27_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB27_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB27_FUNC_CTL_DRAM_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB27_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB28_FUNC_CTL function mux definitions */ +#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB28_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB28_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB28_FUNC_CTL_DRAM_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB28_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB29_FUNC_CTL function mux definitions */ +#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB29_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB29_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB29_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB29_FUNC_CTL_DRAM_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB29_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB30_FUNC_CTL function mux definitions */ +#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB30_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB30_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB30_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB30_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB30_FUNC_CTL_DRAM_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB30_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB31_FUNC_CTL function mux definitions */ +#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB31_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB31_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB31_FUNC_CTL_DRAM_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB31_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC00_FUNC_CTL function mux definitions */ +#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC00_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC00_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC00_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC00_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC00_FUNC_CTL_DRAM_SRDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC01_FUNC_CTL function mux definitions */ +#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC01_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC01_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC01_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC01_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC01_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC02_FUNC_CTL function mux definitions */ +#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC02_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC02_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC02_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC03_FUNC_CTL function mux definitions */ +#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC03_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC03_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC03_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC03_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC04_FUNC_CTL function mux definitions */ +#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC04_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC04_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC04_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC04_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC04_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC04_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC05_FUNC_CTL function mux definitions */ +#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC05_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC05_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC05_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC05_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC05_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC06_FUNC_CTL function mux definitions */ +#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC06_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC06_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC06_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC07_FUNC_CTL function mux definitions */ +#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC07_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC07_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PC07_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC07_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC07_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC07_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC08_FUNC_CTL function mux definitions */ +#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC08_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC08_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC08_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC08_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC08_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC08_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC09_FUNC_CTL function mux definitions */ +#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC09_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC09_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC09_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC09_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC09_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PC10_FUNC_CTL function mux definitions */ +#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC10_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC10_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC10_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC10_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC10_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PC11_FUNC_CTL function mux definitions */ +#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC11_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC11_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC11_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC11_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC11_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PC12_FUNC_CTL function mux definitions */ +#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC12_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC12_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC12_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC12_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PC13_FUNC_CTL function mux definitions */ +#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC13_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC13_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC13_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC13_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) + +/* IOC_PC14_FUNC_CTL function mux definitions */ +#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC14_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC14_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC15_FUNC_CTL function mux definitions */ +#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC15_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC16_FUNC_CTL function mux definitions */ +#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC16_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC16_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) + +/* IOC_PC17_FUNC_CTL function mux definitions */ +#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC17_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC17_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PC18_FUNC_CTL function mux definitions */ +#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC18_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC18_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC18_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC18_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC19_FUNC_CTL function mux definitions */ +#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC19_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC19_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC19_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC19_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC20_FUNC_CTL function mux definitions */ +#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC20_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC20_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC20_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC20_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC20_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC21_FUNC_CTL function mux definitions */ +#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC21_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC21_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC21_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC21_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC21_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC22_FUNC_CTL function mux definitions */ +#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC22_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC22_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC22_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PC22_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC22_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC23_FUNC_CTL function mux definitions */ +#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC23_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC23_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC23_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC24_FUNC_CTL function mux definitions */ +#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC24_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC24_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC24_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC24_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC25_FUNC_CTL function mux definitions */ +#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC25_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC25_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC25_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC25_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC26_FUNC_CTL function mux definitions */ +#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC26_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC26_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC26_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC26_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC27_FUNC_CTL function mux definitions */ +#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC27_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC27_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PC27_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC27_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC28_FUNC_CTL function mux definitions */ +#define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC28_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC28_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC28_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC28_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC29_FUNC_CTL function mux definitions */ +#define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC29_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC29_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC29_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC29_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC30_FUNC_CTL function mux definitions */ +#define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC30_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC30_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC30_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PC31_FUNC_CTL function mux definitions */ +#define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC31_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC31_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC31_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD00_FUNC_CTL function mux definitions */ +#define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD00_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD00_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD00_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD00_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD00_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD00_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD00_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD00_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PD01_FUNC_CTL function mux definitions */ +#define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD01_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD01_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD01_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD01_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD01_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD01_FUNC_CTL_XPI1_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD01_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PD02_FUNC_CTL function mux definitions */ +#define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD02_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD02_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD02_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD02_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD02_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD02_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD02_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD02_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD03_FUNC_CTL function mux definitions */ +#define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD03_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD03_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD03_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD03_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD03_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD03_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD03_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD03_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD03_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD04_FUNC_CTL function mux definitions */ +#define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD04_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD04_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD04_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD04_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD04_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD04_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD04_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD05_FUNC_CTL function mux definitions */ +#define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD05_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD05_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD05_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD05_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD05_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD05_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD05_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD06_FUNC_CTL function mux definitions */ +#define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD06_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD06_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD06_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD06_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD06_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD06_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD06_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PD07_FUNC_CTL function mux definitions */ +#define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD07_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD07_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD07_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD07_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD07_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD07_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PD08_FUNC_CTL function mux definitions */ +#define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD08_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD08_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD08_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD08_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD08_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD08_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PD09_FUNC_CTL function mux definitions */ +#define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD09_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD09_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD09_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD09_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PD10_FUNC_CTL function mux definitions */ +#define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD10_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD10_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD10_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD10_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD10_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PD11_FUNC_CTL function mux definitions */ +#define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD11_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD11_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD11_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD11_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD11_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD11_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PD12_FUNC_CTL function mux definitions */ +#define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD12_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD12_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD12_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD12_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD12_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD13_FUNC_CTL function mux definitions */ +#define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD13_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD13_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD13_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD13_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD13_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD14_FUNC_CTL function mux definitions */ +#define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD14_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD14_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD14_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD14_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD14_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD14_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD14_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD15_FUNC_CTL function mux definitions */ +#define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD15_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD15_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD15_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD15_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD15_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD15_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD15_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PD16_FUNC_CTL function mux definitions */ +#define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD16_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD16_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD16_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD16_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD16_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD16_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PD17_FUNC_CTL function mux definitions */ +#define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD17_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD17_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD17_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD17_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD17_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PD18_FUNC_CTL function mux definitions */ +#define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD18_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD18_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD18_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD18_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD18_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PD19_FUNC_CTL function mux definitions */ +#define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD19_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD19_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD19_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD19_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PD20_FUNC_CTL function mux definitions */ +#define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD20_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD20_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD20_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD20_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PD20_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD20_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PD21_FUNC_CTL function mux definitions */ +#define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD21_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PD21_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD21_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD21_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PD21_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD21_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PD22_FUNC_CTL function mux definitions */ +#define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD22_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) + +/* IOC_PD23_FUNC_CTL function mux definitions */ +#define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD23_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) + +/* IOC_PX00_FUNC_CTL function mux definitions */ +#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX01_FUNC_CTL function mux definitions */ +#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX02_FUNC_CTL function mux definitions */ +#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX03_FUNC_CTL function mux definitions */ +#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX04_FUNC_CTL function mux definitions */ +#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX05_FUNC_CTL function mux definitions */ +#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX06_FUNC_CTL function mux definitions */ +#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX06_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX07_FUNC_CTL function mux definitions */ +#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX07_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PX07_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY01_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY04_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PY04_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY05_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY05_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PY05_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY06_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY07_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PY08_FUNC_CTL function mux definitions */ +#define IOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + +/* IOC_PY09_FUNC_CTL function mux definitions */ +#define IOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + +/* IOC_PY10_FUNC_CTL function mux definitions */ +#define IOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + +/* IOC_PY11_FUNC_CTL function mux definitions */ +#define IOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ02_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ03_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) + +/* IOC_PZ08_FUNC_CTL function mux definitions */ +#define IOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + +/* IOC_PZ09_FUNC_CTL function mux definitions */ +#define IOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + +/* IOC_PZ10_FUNC_CTL function mux definitions */ +#define IOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + +/* IOC_PZ11_FUNC_CTL function mux definitions */ +#define IOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) + + +#endif /* HPM_IOMUX_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.c new file mode 100644 index 0000000000..418f3eb409 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.c @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + + +#define ASSERT_ADDR_SIZE(addr, size) do { \ + assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ + assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ + } while (0) + +static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) +{ + register uint32_t i; + register uint32_t next_address = 0; + register uint32_t tmp; + +#define CCTL_VERSION (3U << 18) + + if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { + l1c_cctl_address(address); + while (next_address < (address + size)) { + l1c_cctl_cmd(opcode); + next_address = l1c_cctl_get_address(); + } + } else { + for (i = 0, tmp = 0; tmp < size; i++) { + l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); + tmp += HPM_L1C_CACHELINE_SIZE; + } + } +} + +void l1c_dc_enable(void) +{ + if (!l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); + set_csr(CSR_MCACHE_CTL, +#ifdef L1C_DC_WAROUND_VALUE + HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | +#endif + HPM_MCACHE_CTL_DPREF_EN_MASK + | HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_dc_disable(void) +{ + if (l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_ic_enable(void) +{ + if (!l1c_ic_is_enabled()) { + set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK + | HPM_MCACHE_CTL_CCTL_SUEN_MASK + | HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_ic_disable(void) +{ + if (l1c_ic_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_fence_i(void) +{ + __asm("fence.i"); +} + +void l1c_dc_invalidate_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); +} + +void l1c_dc_writeback_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); +} + +void l1c_dc_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); +} + +void l1c_dc_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); +} + +void l1c_dc_writeback(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); +} + +void l1c_dc_flush(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); +} + +void l1c_ic_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); +} + +void l1c_ic_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h new file mode 100644 index 0000000000..d64cd4791f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h @@ -0,0 +1,479 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_L1_CACHE_H +#define _HPM_L1_CACHE_H +#include "riscv/riscv_core.h" +#include "hpm_common.h" + +/** + * + * @brief L1CACHE driver APIs + * @defgroup l1cache_interface L1CACHE driver APIs + * @{ + */ + +/* cache size is 32KB */ +#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) +#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) +#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) +/* cache line size is 64B */ +#define HPM_L1C_CACHELINE_SIZE (64) +/* cache way is 128 */ +#define HPM_L1C_CACHELINES_PER_WAY (128) + +/* mcache_ctl register */ +/* + * Controls if the instruction cache is enabled or not. + * + * 0 I-Cache is disabled + * 1 I-Cache is enabled + */ +#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) +#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) +#define HPM_MCACHE_CTL_IC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) + +/* + * Controls if the data cache is enabled or not. + * + * 0 D-Cache is disabled + * 1 D-Cache is enabled + */ +#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) +#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) +#define HPM_MCACHE_CTL_DC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) + +/* + * Parity/ECC error checking enable control for the instruction cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) +#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_IC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) + +/* + * + * Parity/ECC error checking enable control for the data cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) +#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_DC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. + * It is set to enable CCTL operations to access the ECC codes. This bit + * can be set for injecting ECC errors to test the ECC handler. + * + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) +#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_IC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is + * set to enable CCTL operations to access the ECC codes. This bit can be + * set for injecting + * + * ECC errors to test the ECC handler. + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) +#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_DC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) + +/* + * Enable bit for Superuser-mode and User-mode software to access + * ucctlbeginaddr and ucctlcommand CSRs. + * + * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) +#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) +#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) + +/* + * This bit controls hardware prefetch for instruction fetches to cacheable + * memory regions when I-Cache size is not 0. + * + * 0 Disable hardware prefetch on instruction fetches + * 1 Enable hardware prefetch on instruction fetches + */ +#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) +#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_IPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) + +/* + * This bit controls hardware prefetch for load/store accesses to cacheable + * memory regions when D-Cache size is not 0. + * + * 0 Disable hardware prefetch on load/store memory accesses. + * 1 Enable hardware prefetch on load/store memory accesses. + */ +#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) +#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_DPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) + +/* + * I-Cache miss allocation filling policy Value Meaning + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) +#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) + +/* + * D-Cache miss allocation filling policy + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) +#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) + +/* + * D-Cache Write-Around threshold + * + * 0 Disables streaming. All cacheable write misses allocate a cache line + * according to PMA settings. + * 1 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 4 cache lines. + * 2 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 64 cache lines. + * 3 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 128 cache lines. + */ +#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) +#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) +#define HPM_MCACHE_CTL_DC_WAROUND(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) + +/* CCTL command list */ +#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) +#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) +#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) + +#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) + +#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) + +#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) + +#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) +#define HPM_L1C_CCTL_CMD_FAIL (0UL) + +#ifdef __cplusplus +extern "C" { +#endif +/* get cache control register value */ +__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) +{ + return read_csr(CSR_MCACHE_CTL); +} + +__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; +} + +__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; +} + +/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ +#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) +#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) +#define HPM_MCCTLBEGINADDR_OFFSET(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) +#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) +#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) +#define HPM_MCCTLBEGINADDR_INDEX(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) +#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) +#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) +#define HPM_MCCTLBEGINADDR_WAY(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) + +/* send IX command */ +__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); +} + +/* send command */ +__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) +{ + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) +{ + return read_csr(CSR_MCCTLBEGINADDR); +} + +/* send IX command */ +__attribute__((always_inline)) static inline + void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) +#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) +#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) +#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) +#define HPM_MCCTLDATA_I_TAG_VALID(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) + +#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) +#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) +#define HPM_MCCTLDATA_D_TAG_MESI(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) + +#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) +#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) +#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_TAG(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) + +/* + * @brief Cache control command read address + * + * Send IX read tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] ecc_data ECC value + * @return data read + */ +ATTR_ALWAYS_INLINE static inline + uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + *ecc_data = read_csr(CSR_MECC_CODE); + return read_csr(CSR_MCCTLDATA); +} + +/* + * @brief Cache control command write address + * + * Send IX write tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] data Data to be written + * @param[in] ecc_data ECC of data + */ +ATTR_ALWAYS_INLINE static inline + void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + write_csr(CSR_MCCTLDATA, data); + write_csr(CSR_MECC_CODE, ecc_data); +} + +#define HPM_L1C_CFG_SET_SHIFT (0UL) +#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) +#define HPM_L1C_CFG_WAY_SHIFT (3UL) +#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) +#define HPM_L1C_CFG_SIZE_SHIFT (6UL) +#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) +#define HPM_L1C_CFG_LOCK_SHIFT (9UL) +#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) +#define HPM_L1C_CFG_ECC_SHIFT (10UL) +#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) +#define HPM_L1C_CFG_LMB_SHIFT (12UL) +#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) +#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) +#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) +#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) +#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) +#define HPM_L1C_CFG_SETH_SHIFT (24UL) +#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) + +/** + * @brief Align down based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) + +/** + * @brief Align up based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) + +/** + * @brief Get I-cache configuration + * + * @return I-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) +{ + return read_csr(CSR_MICM_CFG); +} + +/** + * @brief Get D-cache configuration + * + * @return D-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) +{ + return read_csr(CSR_MDCM_CFG); +} + +/* + * @brief D-cache disable + */ +void l1c_dc_disable(void); + +/* + * @brief D-cache enable + */ +void l1c_dc_enable(void); + +/* + * @brief D-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_dc_invalidate(uint32_t address, uint32_t size); + +/* + * @brief D-cache writeback by address + * @param[in] address Start address to be writtenback + * @param[in] size Size of memory to be writtenback + */ +void l1c_dc_writeback(uint32_t address, uint32_t size); + +/* + * @brief D-cache invalidate and writeback by address + * @param[in] address Start address to be invalidated and writtenback + * @param[in] size Size of memory to be invalidted and writtenback + */ +void l1c_dc_flush(uint32_t address, uint32_t size); + +/* + * @brief D-cache fill and lock by address + * @param[in] address Start address to be filled and locked + * @param[in] size Size of memory to be filled and locked + */ +void l1c_dc_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief I-cache disable + */ +void l1c_ic_disable(void); + +/* + * @brief I-cache enable + */ +void l1c_ic_enable(void); + +/* + * @brief I-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_ic_invalidate(uint32_t address, uint32_t size); + +/* + * @brief I-cache fill and lock by address + * @param[in] address Start address to be locked + * @param[in] size Size of memory to be locked + */ +void l1c_ic_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief Invalidate all icache and writeback all dcache + */ +void l1c_fence_i(void); + +/* + * @brief Invalidate all d-cache + */ +void l1c_dc_invalidate_all(void); + +/* + * @brief Writeback all d-cache + */ +void l1c_dc_writeback_all(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h new file mode 100644 index 0000000000..3ad12ad240 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_misc.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MISC_H +#define HPM_MISC_H + +#define ILM_LOCAL_BASE (0x0U) +#define ILM_SIZE_IN_BYTE (0x40000U) +#define DLM_LOCAL_BASE (0x80000U) +#define DLM_SIZE_IN_BYTE (0x40000U) +#define CORE0_ILM_SYSTEM_BASE (0x1040000U) +#define CORE0_DLM_SYSTEM_BASE (0x1060000U) +#define CORE1_ILM_SYSTEM_BASE (0x1180000U) +#define CORE1_DLM_SYSTEM_BASE (0x11C0000U) + +#define ADDRESS_IN_ILM(address) \ + ((ILM_LOCAL_BASE) <= (address)) && \ + ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_DLM(address) \ + ((DLM_LOCAL_BASE) <= (address)) && \ + ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ + ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + +#define DLM_TO_SYSTEM(address) \ + (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) +#define ILM_TO_SYSTEM(address) \ + (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) +#define SYSTEM_TO_DLM(address) \ + ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) + +#define HPM_CORE0 (0U) +#define HPM_CORE1 (1U) + +/* map core local memory(DLM/ILM) to system address */ +static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) +{ + return addr; +} + +/* map system address to core local memory(DLM/ILM) */ +static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) +{ + return addr; +} +#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.c new file mode 100644 index 0000000000..ef0fa1cfc4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_otp_drv.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) +#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ +#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) +#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ +#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +void otp_init(void) +{ + +} + +void otp_deinit(void) +{ + +} + +uint32_t otp_read_from_shadow(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP->SHADOW[addr] : HPM_OTPSHW->SHADOW[addr]; + } + + return ret_val; +} + +uint32_t otp_read_from_ip(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->FUSE[addr]; + } + return ret_val; +} + +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); + + /* Enable 2.5V LDO for FUSE programming */ + uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); + HPM_PCFG->LDO2P5 = reg_val; + /* Wait until LDO is ready */ + while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { + } + HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; + for (uint32_t i = 0; i < num_of_words; i++) { + HPM_OTP->FUSE[addr++] = *src++; + } + HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; + /* Disable 2.5V LDO after FUSE programming for saving power */ + HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_reload(otp_region_t region) +{ + hpm_stat_t status = status_invalid_argument; + if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { + HPM_OTP->LOAD_REQ = (uint32_t)region; + HPM_OTP->LOAD_COMP = (uint32_t)region; + while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { + + } + status = status_success; + } + + return status; +} + +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); + + HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) + | OTP_REGION_STOP_SET(start + num_of_words); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + uint32_t lock_mask = 3U << lock_reg_offset; + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) + >> lock_reg_offset); + + if (lock_opt != otp_no_lock) { + status = otp_write_disallowed; + break; + } + + otp_base->SHADOW[addr] = val; + + status = status_success; + } while (false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h new file mode 100644 index 0000000000..09f62879ec --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_otp_drv.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_OTP_DRV_H +#define HPM_OTP_DRV_H + +/** + * @brief OTP APIs + * @defgroup otp_interface OTP driver APIs + * @{ + */ + +#include "hpm_common.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * @brief OTP region definitions + */ +typedef enum { + otp_region0_mask = 1U, /*!< Address range: [0, 7] */ + otp_region1_mask = 2U, /*!< Address range: [8, 15] */ + otp_region2_mask = 4U, /*!< Address range: [16, 127] */ + otp_region3_mask = 8U, /*!< Address range: user defined */ +} otp_region_t; + +/** + * @brief OTP lock options + */ +typedef enum { + otp_no_lock = 0, + otp_read_only = 1, + otp_permanent_no_lock = 2, + otp_disable_access = 3, + otp_lock_option_max = otp_disable_access, +} otp_lock_option_t; + +enum { + otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), +}; + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +#ifdef __cpluscplus +extern "C" { +#endif + +/** + * @brief Initialize OTP controller + */ +void otp_init(void); + +/** + * @brief De-initialize OTP controller + */ +void otp_deinit(void); + +/** + * @brief Read the OTP word from shadow register + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_shadow(uint32_t addr); + +/** + * @brief Read the specified OTP word from OTP IP bus + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_ip(uint32_t addr); + +/** + * @brief Program a word to specified OTP field + * @param [in] addr OTP word index + * @param [in] src Pointer to the data to be programmed + * @param [in] num_of_words Number of words to be programmed, only 1 is allowed + * @return API execution status + */ +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + +/** + * @brief Reload a OTP region + * @param [in] region OTP region option + * @return API execution status + */ +hpm_stat_t otp_reload(otp_region_t region); + +/** + * @brief Change the Software lock permission + * @param [in] addr OTP word index + * @param [in] lock_option OTP lcok option + * @return API execution status + */ +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief OTP lock shadow + * @param [in] addr OTP word index + * @param [in] lock_option OTP lock option + * @return API execution status + */ +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief Set the configurable region range + * @param [in] start OTP word start index + * @param [in] num_of_words Number of words in configuration region + * @retval status_out_of_range Invalid range + * @retval status_success Operation is successful + */ +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); + +/** + * @return Write data to OTP shadow register + * @param [in] addr OTP word index + * @param [val] val Data to be written + * @return API execution status + */ +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); + + +#ifdef __cpluscplus +} +#endif +/** + * @} + */ + + + + +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_plic_drv.h new file mode 100644 index 0000000000..dc0b95e00e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_plic_drv.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLIC_DRV_H +#define HPM_PLIC_DRV_H + +/** + * @brief PLIC driver APIs + * @defgroup plic_interface PLIC driver APIs + * @{ + */ + +#define HPM_PLIC_TARGET_M_MODE 0 +#define HPM_PLIC_TARGET_S_MODE 1 + +/* Feature Register */ +#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) +#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) +#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) + +/* Priority Register - 32 bits per irq */ +#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) +#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per source */ +#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) +#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 + +/* Enable Register - 0x80 per target */ +#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) +#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + +/* Claim Register - 0x1000 per target */ +#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) +#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if !defined(__ASSEMBLER__) + +/** + * @brief Set plic feature + * + * @param[in] base PLIC base address + * @param[in] feature Specific feature to be set + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) +{ + *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; +} + +/** + * @brief Set plic threshold + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, + uint32_t target, + uint32_t threshold) +{ + volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + + HPM_PLIC_THRESHOLD_OFFSET + + (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +/** + * @brief Set interrupt priority + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * @param[in] priority Priority to be assigned + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, + uint32_t irq, + uint32_t priority) +{ + volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +/** + * @brief Set interrupt pending bit + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); + *current_ptr = (1 << (irq & 0x1F)); +} + +/** + * @brief Enable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be enabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current | (1 << (irq & 0x1F)); + *current_ptr = current; +} + +/** + * @brief Disable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be disabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current & ~((1 << (irq & 0x1F))); + *current_ptr = current; +} + +/** + * @brief Claim interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to claim interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +/** + * @brief Complete interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = irq; +} +#endif /* __ASSEMBLER__ */ +/** + * @} + */ +#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h new file mode 100644 index 0000000000..197dcb8c4f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PMIC_IOMUX_H +#define HPM_PMIC_IOMUX_H + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY08_FUNC_CTL function mux definitions */ +#define IOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY08_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY09_FUNC_CTL function mux definitions */ +#define IOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY09_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY10_FUNC_CTL function mux definitions */ +#define IOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY10_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY11_FUNC_CTL function mux definitions */ +#define IOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY11_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_PMIC_IOMUX_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h new file mode 100644 index 0000000000..5797f26e0d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h @@ -0,0 +1,725 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_H +#define HPM_ROMAPI_H + +/** + * @brief ROM APIs + * @defgroup romapi_interface ROM APIs + * @{ + */ + +#include "hpm_common.h" +#include "hpm_otp_drv.h" +#include "hpm_romapi_xpi_def.h" +#include "hpm_romapi_xpi_soc_def.h" +#include "hpm_romapi_xpi_nor_def.h" +#include "hpm_romapi_xpi_ram_def.h" +#include "hpm_sdp_drv.h" + +/* XPI0 base address */ +#define HPM_XPI0_BASE (0xF3040000UL) /**< XPI0 Base address */ +/* XPI0 base pointer */ +#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ +/* XPI1 base address */ +#define HPM_XPI1_BASE (0xF3044000UL) /**< XPI1 Base address */ +/* XPI1 base pointer */ +#define HPM_XPI1 ((XPI_Type *) HPM_XPI1_BASE) /**< XPI1 Base pointer */ + + +/*********************************************************************************************************************** + * + * + * Definitions + * + * + **********************************************************************************************************************/ +/** + * @brief Enter Bootloader API argument + */ +typedef union { + uint32_t U; + struct { + uint32_t index: 8; /**< Image index */ + uint32_t peripheral: 8; /**< Boot peripheral */ + uint32_t src: 8; /**< Boot source */ + uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ + }; +} api_boot_arg_t; + +#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ +#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ +#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ +#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ +#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ +#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ +#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ +#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ + +/** + * @brief OTP driver interface + */ +typedef struct { + /**< OTP driver interface version */ + uint32_t version; + /**< OTP driver interface: init */ + void (*init)(void); + /**< OTP driver interface: deinit */ + void (*deinit)(void); + /**< OTP driver interface: read from shadow */ + uint32_t (*read_from_shadow)(uint32_t addr); + /**< OTP driver interface: read from ip */ + uint32_t (*read_from_ip)(uint32_t addr); + /**< OTP driver interface: program */ + hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + /**< OTP driver interface: reload */ + hpm_stat_t (*reload)(otp_region_t region); + /**< OTP driver interface: lock */ + hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: lock_shadow */ + hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: set_configurable_region */ + hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); + /**< OTP driver interface: write_shadow_register */ + hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); +} otp_driver_interface_t; + +/** + * @brief XPI driver interface + */ +typedef struct { + /**< XPI driver interface: version */ + uint32_t version; + /**< XPI driver interface: get default configuration */ + hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); + /**< XPI driver interface: get default device configuration */ + hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); + /**< XPI driver interface: initialize the XPI using xpi_config */ + hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); + /**< XPI driver interface: configure the AHB buffer */ + hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); + /**< XPI driver interface: configure the device */ + hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); + /**< XPI driver interface: update instruction talbe */ + hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); + /**< XPI driver interface: transfer command/data using block interface */ + hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); + /**< Software reset the XPI controller */ + void (*software_reset)(XPI_Type *base); + /**< XPI driver interface: Check whether IP is idle */ + bool (*is_idle)(XPI_Type *base); + /**< XPI driver interface: update delay line setting */ + void (*update_dllcr)(XPI_Type *base, + uint32_t serial_root_clk_freq, + uint32_t data_valid_time, + xpi_channel_t channel, + uint32_t dly_target); + /**< XPI driver interface: Get absolute address for APB transfer */ + hpm_stat_t + (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); +} xpi_driver_interface_t; + +/** + * @brief XPI NOR driver interface + */ +typedef struct { + /**< XPI NOR driver interface: API version */ + uint32_t version; + /**< XPI NOR driver interface: Get FLASH configuration */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + /**< XPI NOR driver interface: initialize FLASH */ + hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Enable write access to FLASH */ + hpm_stat_t + (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Get FLASH status register */ + hpm_stat_t (*get_status)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status); + /**< XPI NOR driver interface: Wait when FLASH is still busy */ + hpm_stat_t + (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: erase a specified FLASH region */ + hpm_stat_t (*erase)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: Erase the whole FLASH */ + hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Erase specified FLASH sector */ + hpm_stat_t + (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Erase specified FLASH block */ + hpm_stat_t + (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Program data to specified FLASH address */ + hpm_stat_t (*program)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: read data from specified FLASH address */ + hpm_stat_t (*read)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ + hpm_stat_t + (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + + uint32_t reserved0[3]; + + /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ + hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + + /**< XPI NOR driver interface: Get FLASH properties */ + hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); + +} xpi_nor_driver_interface_t; + +/** + * @brief XPI RAM driver interface + */ +typedef struct { + /**< XPI RAM driver interface: API version */ + uint32_t version; + + /**< Get XPI RAM configuration based on cfg_option */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); + + /**< XPI RAM driver interface: Initialize XPI RAM */ + hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); +} xpi_ram_driver_interface_t; + +/** + * @brief SDP API interface + */ +typedef struct { + /**< SDP API interface: API version */ + uint32_t version; + /**< SDP API interface: Initialize IP */ + hpm_stat_t (*sdp_ip_init)(void); + /**< SDP API interface: Deinitialize IP */ + hpm_stat_t (*sdp_ip_deinit)(void); + /**< SDP API interface: Set AES key */ + hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: AES ECB crypto operation */ + hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API interface: AES CBC crypto operation */ + hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API interface: AES CTR crypto operation */ + hpm_stat_t + (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API interface: AES CCM encryption */ + hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: AES CCM Decrypt and verify */ + hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: memcpy */ + hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); + /**< SDP API interface: memset */ + hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); + /**< SDP API interface: HASH initialization */ + hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + /**< SDP API interface: HASH update */ + hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + /**< SDP API interface: HASH finish */ + hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); +} sdp_driver_interface_t; + +/** + * @brief Bootloader API table + */ +typedef struct { + /**< Bootloader API table: version */ + const uint32_t version; + /**< Bootloader API table: copyright string address */ + const char *copyright; + /**< Bootloader API table: run_bootloader API */ + const hpm_stat_t (*run_bootloader)(void *arg); + /**< Bootloader API table: otp driver interface address */ + const otp_driver_interface_t *otp_driver_if; + /**< Bootloader API table: xpi driver interface address */ + const xpi_driver_interface_t *xpi_driver_if; + /**< Bootloader API table: xpi nor driver interface address */ + const xpi_nor_driver_interface_t *xpi_nor_driver_if; + /**< Bootloader API table: xpi ram driver interface address */ + const xpi_ram_driver_interface_t *xpi_ram_driver_if; + /**< Bootloader API table: sdp driver interface address */ + const sdp_driver_interface_t *sdp_driver_if; +} bootloader_api_table_t; + +/**< Bootloader API table Root */ +#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t*)0x2001FF00U) + + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * + * + * Enter bootloader Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Eneter specified Boot mode + * @param [in] ctx Enter bootloader context + * @retval status_invalid Invalid parameters were deteced + */ +static inline hpm_stat_t rom_enter_bootloader(void *ctx) +{ + return ROM_API_TABLE_ROOT->run_bootloader(ctx); +} + +/*********************************************************************************************************************** + * + * + * XPI NOR Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Get XPI NOR configuration via cfg_option + * @param [in] base XPI base address + * @param [out] nor_cfg XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_get_config(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); +} + +/** + * @brief Initialize XPI NOR based on nor_config + * @param [in] base XPI base address + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); +} + +/** + * @brief Erase specified FLASH region + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI nOR configuration + * @param[in] start Erase address start address + * @param[in] length Region size to be erased + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); +} + +/** + * @brief Erase specified FLASH sector in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_erase_sector(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH sector in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_erase_block(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase the whole FLASH in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_erase_chip(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); +} + +/** + * @brief Erase the whole FLASH in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); +} + +/** + * @brief Program data to specified FLASH address in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Page-Program data to specified FLASH address in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if + ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Read data from specified FLASH address + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] dst Memory start address to store the data read out from FLASH + * @param [in] start FLASH address for data read + * @param [in] length length of data to be read out + * @return API exection address + */ +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); +} + +/** + * @brief Automatically configure XPI NOR based on cfg_option + * @param [in] base XPI base address + * @param [out] config XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_auto_config(XPI_Type *base, xpi_nor_config_t *config, xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); +} + +/** + * @brief Get XPI NOR properties + * @param [in] base XPI base address + * @param [in] nor_cfg XPI NOR configuration structure + * @param [in] property_id + * @param [out] value property value retrieved by this API + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_get_property(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); +} + + +/*********************************************************************************************************************** + * + * + * XPI RAM Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Get XPI RAM configuration based on cfg_option + * @param [in] base XPI base address + * @param [out] ram_cfg XPI RAM configuration structure + * @param [in] cfg_option XPI RAM configuration option + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_ram_get_config(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); +} + +/** + * @brief Initialize XPI RAM + * @param [in] base XPI base address + * @param [in] ram_cfg XPI ram configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); +} + +/*********************************************************************************************************************** + * + * + * SDP Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Initialize SDP IP + */ +static inline void rom_sdp_init(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); +} + +/** + * @brief De-initialize SDP IP + */ +static inline void rom_sdp_deinit(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); +} + +/** + * @brief Set AES key to SDP + * @param [in] aes_ctx AES context + * @param [in] key AES key buffer + * @param [in] key_bits AES key-bit option + * @param[in] key_idx AES key index + * @return API execution status + */ +static inline hpm_stat_t +rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t key_bits, uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] len Data length for AES encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t +rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); +} + +/** + * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] length Data length for AES encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); +} + +/** + * @brief HASH initialization + * @param [in] hash_ctx HASH context + * @param [in] alg HASH algorithm + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); +} + +/** + * @brief HASH Update + * @param [in] hash_ctx HASH context + * @param [in] data Data for HASH operation + * @param [in] length of the data for HASH operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); +} + +/** + * @brief HASH finialize + * @param [in] hash_ctx HASH context + * @param [out] digest the output digest + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); +} + +/** + * @brief SDP memcpy operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memcpy + * @param [in] src Source address for memcpy + * @param [in] length Size of data for memcpy operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); +} + +/** + * @brief SDP memset operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memset + * @param [in] pattern pattern for memset + * @param [in] length Size of data for memset operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi_xpi_soc_def.h new file mode 100644 index 0000000000..13edd92e2c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_romapi_xpi_soc_def.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_XPI_SOC_DEF_H +#define HPM_ROMAPI_XPI_SOC_DEF_H + +#include "hpm_common.h" +#include "hpm_romapi_xpi_def.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) +#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) +#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) +#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) +#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) +#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) +#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) +#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) +#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) + +typedef struct { + struct { + uint8_t priority; /* Offset: 0x00 */ + uint8_t master_idx; /* Offset: 0x01 */ + uint8_t buf_size_in_dword; /* Offset: 0x02 */ + bool enable_prefetch; /* Offset: 0x03 */ + } entry[8]; +} xpi_ahb_buffer_cfg_t; + +typedef struct { + uint8_t data_pads; + xpi_channel_t channel; + xpi_io_group_t io_group; + uint8_t drive_strength; + bool enable_dqs; + bool enable_diff_clk; +} xpi_io_config_t; + +typedef enum { + xpi_freq_type_typical, + xpi_freq_type_mhz, +} clk_freq_type_t; + +typedef enum { + xpi_clk_src_auto, + xpi_clk_src_osc, + xpi_clk_src_pll0clk0, + xpi_clk_src_pll1clk0, + xpi_clk_src_pll1clk1, + xpi_clk_src_pll2clk0, + xpi_clk_src_pll2clk1, + xpi_clk_src_pll3clk0, + xpi_clk_src_pll4clk0, +} xpi_clk_src_t; + + +typedef union +{ + struct { + uint8_t freq; + bool enable_ddr; + xpi_clk_src_t clk_src; + clk_freq_type_t freq_type; + }; + uint32_t freq_opt; +} xpi_clk_config_t; + +typedef enum { + xpi_clock_bus, + xpi_clock_serial_root, + xpi_clock_serial, +} xpi_clock_t; + +#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h new file mode 100644 index 0000000000..9f39f2ef07 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sdxc_soc_drv.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SDXC_SOC_DRV_H +#define HPM_SDXC_SOC_DRV_H + +#include "hpm_soc.h" +#include "hpm_sdxc_regs.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +static inline void sdxc_enable_tm_clock(SDXC_Type *base) +{ + base->MISC_CTRL0 |= SDXC_MISC_CTRL0_TMCLK_EN_MASK; +} + +static inline void sdxc_enable_freq_selection(SDXC_Type *base) +{ + base->MISC_CTRL0 |= SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; +} + +static inline void sdxc_disable_freq_selection(SDXC_Type *base) +{ + base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; +} + +static inline void sdxc_set_clock_divider(SDXC_Type *base, uint32_t div) +{ + base->MISC_CTRL0 = (base->MISC_CTRL0 & ~SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) | SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(div) | SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; +} + +static inline uint32_t sdxc_get_clock_divider(SDXC_Type *base) +{ + return SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(base->MISC_CTRL0); +} + +/** + * @brief Wait at least 74 clocks until card is ready to receive the first command + */ +static inline void sdxc_wait_card_active(SDXC_Type *base) +{ + base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; + + base->MISC_CTRL1 |= SDXC_MISC_CTRL1_CARD_ACTIVE_MASK; + + while (!IS_HPM_BITMASK_SET(base->MISC_CTRL1, SDXC_MISC_CTRL1_CARD_ACTIVE_MASK)) { + } +} + +static inline void sdxc_enable_inverse_clock(SDXC_Type *base, bool enable) +{ + if (enable) { + base->MISC_CTRL0 |= SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK; + } else { + base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK; + } +} + + +#if defined(__cplusplus) +} +#endif + + +#endif /* HPM_SDXC_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml new file mode 100644 index 0000000000..3d3d1e7c66 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml @@ -0,0 +1,27252 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h new file mode 100644 index 0000000000..bdde731cb1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h @@ -0,0 +1,647 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SOC_H +#define HPM_SOC_H + + +/* List of external IRQs */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ +#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ +#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */ +#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */ +#define IRQn_ADC0 8 /* ADC0 IRQ */ +#define IRQn_ADC1 9 /* ADC1 IRQ */ +#define IRQn_ADC2 10 /* ADC2 IRQ */ +#define IRQn_DAC 11 /* DAC IRQ */ +#define IRQn_ACMP_0 12 /* ACMP[0] IRQ */ +#define IRQn_ACMP_1 13 /* ACMP[1] IRQ */ +#define IRQn_SPI0 14 /* SPI0 IRQ */ +#define IRQn_SPI1 15 /* SPI1 IRQ */ +#define IRQn_SPI2 16 /* SPI2 IRQ */ +#define IRQn_SPI3 17 /* SPI3 IRQ */ +#define IRQn_UART0 18 /* UART0 IRQ */ +#define IRQn_UART1 19 /* UART1 IRQ */ +#define IRQn_UART2 20 /* UART2 IRQ */ +#define IRQn_UART3 21 /* UART3 IRQ */ +#define IRQn_UART4 22 /* UART4 IRQ */ +#define IRQn_UART5 23 /* UART5 IRQ */ +#define IRQn_UART6 24 /* UART6 IRQ */ +#define IRQn_UART7 25 /* UART7 IRQ */ +#define IRQn_CAN0 26 /* CAN0 IRQ */ +#define IRQn_CAN1 27 /* CAN1 IRQ */ +#define IRQn_PTPC 28 /* PTPC IRQ */ +#define IRQn_WDG0 29 /* WDG0 IRQ */ +#define IRQn_WDG1 30 /* WDG1 IRQ */ +#define IRQn_TSNS 31 /* TSNS IRQ */ +#define IRQn_MBX0A 32 /* MBX0A IRQ */ +#define IRQn_MBX0B 33 /* MBX0B IRQ */ +#define IRQn_GPTMR0 34 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 35 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 36 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 37 /* GPTMR3 IRQ */ +#define IRQn_I2C0 38 /* I2C0 IRQ */ +#define IRQn_I2C1 39 /* I2C1 IRQ */ +#define IRQn_I2C2 40 /* I2C2 IRQ */ +#define IRQn_I2C3 41 /* I2C3 IRQ */ +#define IRQn_PWM0 42 /* PWM0 IRQ */ +#define IRQn_HALL0 43 /* HALL0 IRQ */ +#define IRQn_QEI0 44 /* QEI0 IRQ */ +#define IRQn_PWM1 45 /* PWM1 IRQ */ +#define IRQn_HALL1 46 /* HALL1 IRQ */ +#define IRQn_QEI1 47 /* QEI1 IRQ */ +#define IRQn_SDP 48 /* SDP IRQ */ +#define IRQn_XPI0 49 /* XPI0 IRQ */ +#define IRQn_XPI1 50 /* XPI1 IRQ */ +#define IRQn_XDMA 51 /* XDMA IRQ */ +#define IRQn_HDMA 52 /* HDMA IRQ */ +#define IRQn_DRAM 53 /* DRAM IRQ */ +#define IRQn_RNG 54 /* RNG IRQ */ +#define IRQn_I2S0 55 /* I2S0 IRQ */ +#define IRQn_I2S1 56 /* I2S1 IRQ */ +#define IRQn_DAO 57 /* DAO IRQ */ +#define IRQn_PDM 58 /* PDM IRQ */ +#define IRQn_FFA 59 /* FFA IRQ */ +#define IRQn_NTMR0 60 /* NTMR0 IRQ */ +#define IRQn_USB0 61 /* USB0 IRQ */ +#define IRQn_ENET0 62 /* ENET0 IRQ */ +#define IRQn_SDXC0 63 /* SDXC0 IRQ */ +#define IRQn_PSEC 64 /* PSEC IRQ */ +#define IRQn_PGPIO 65 /* PGPIO IRQ */ +#define IRQn_PWDG 66 /* PWDG IRQ */ +#define IRQn_PTMR 67 /* PTMR IRQ */ +#define IRQn_PUART 68 /* PUART IRQ */ +#define IRQn_FUSE 69 /* FUSE IRQ */ +#define IRQn_SECMON 70 /* SECMON IRQ */ +#define IRQn_RTC 71 /* RTC IRQ */ +#define IRQn_BUTN 72 /* BUTN IRQ */ +#define IRQn_BGPIO 73 /* BGPIO IRQ */ +#define IRQn_BVIO 74 /* BVIO IRQ */ +#define IRQn_BROWNOUT 75 /* BROWNOUT IRQ */ +#define IRQn_SYSCTL 76 /* SYSCTL IRQ */ +#define IRQn_DEBUG_0 77 /* DEBUG[0] IRQ */ +#define IRQn_DEBUG_1 78 /* DEBUG[1] IRQ */ + +#include "hpm_common.h" + +#include "hpm_gpio_regs.h" +/* Address of GPIO instances */ +/* FGPIO base address */ +#define HPM_FGPIO_BASE (0xC0000UL) +/* FGPIO base pointer */ +#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) +/* GPIO0 base address */ +#define HPM_GPIO0_BASE (0xF0000000UL) +/* GPIO0 base pointer */ +#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) +/* PGPIO base address */ +#define HPM_PGPIO_BASE (0xF40DC000UL) +/* PGPIO base pointer */ +#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) +/* BGPIO base address */ +#define HPM_BGPIO_BASE (0xF5014000UL) +/* BGPIO base pointer */ +#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) + +/* Address of DM instances */ +/* DM base address */ +#define HPM_DM_BASE (0x30000000UL) + +#include "hpm_plic_regs.h" +/* Address of PLIC instances */ +/* PLIC base address */ +#define HPM_PLIC_BASE (0xE4000000UL) +/* PLIC base pointer */ +#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) + +#include "hpm_mchtmr_regs.h" +/* Address of MCHTMR instances */ +/* MCHTMR base address */ +#define HPM_MCHTMR_BASE (0xE6000000UL) +/* MCHTMR base pointer */ +#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) + +#include "hpm_plic_sw_regs.h" +/* Address of PLICSW instances */ +/* PLICSW base address */ +#define HPM_PLICSW_BASE (0xE6400000UL) +/* PLICSW base pointer */ +#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) + +#include "hpm_gpiom_regs.h" +/* Address of GPIOM instances */ +/* GPIOM base address */ +#define HPM_GPIOM_BASE (0xF0008000UL) +/* GPIOM base pointer */ +#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) + +#include "hpm_adc16_regs.h" +/* Address of ADC16 instances */ +/* ADC0 base address */ +#define HPM_ADC0_BASE (0xF0010000UL) +/* ADC0 base pointer */ +#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) +/* ADC1 base address */ +#define HPM_ADC1_BASE (0xF0014000UL) +/* ADC1 base pointer */ +#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) +/* ADC2 base address */ +#define HPM_ADC2_BASE (0xF0018000UL) +/* ADC2 base pointer */ +#define HPM_ADC2 ((ADC16_Type *) HPM_ADC2_BASE) + +#include "hpm_acmp_regs.h" +/* Address of ACMP instances */ +/* ACMP base address */ +#define HPM_ACMP_BASE (0xF0020000UL) +/* ACMP base pointer */ +#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) + +#include "hpm_dac_regs.h" +/* Address of DAC instances */ +/* DAC base address */ +#define HPM_DAC_BASE (0xF0024000UL) +/* DAC base pointer */ +#define HPM_DAC ((DAC_Type *) HPM_DAC_BASE) + +#include "hpm_spi_regs.h" +/* Address of SPI instances */ +/* SPI0 base address */ +#define HPM_SPI0_BASE (0xF0030000UL) +/* SPI0 base pointer */ +#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) +/* SPI1 base address */ +#define HPM_SPI1_BASE (0xF0034000UL) +/* SPI1 base pointer */ +#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) +/* SPI2 base address */ +#define HPM_SPI2_BASE (0xF0038000UL) +/* SPI2 base pointer */ +#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) +/* SPI3 base address */ +#define HPM_SPI3_BASE (0xF003C000UL) +/* SPI3 base pointer */ +#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) + +#include "hpm_uart_regs.h" +/* Address of UART instances */ +/* UART0 base address */ +#define HPM_UART0_BASE (0xF0040000UL) +/* UART0 base pointer */ +#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) +/* UART1 base address */ +#define HPM_UART1_BASE (0xF0044000UL) +/* UART1 base pointer */ +#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) +/* UART2 base address */ +#define HPM_UART2_BASE (0xF0048000UL) +/* UART2 base pointer */ +#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) +/* UART3 base address */ +#define HPM_UART3_BASE (0xF004C000UL) +/* UART3 base pointer */ +#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) +/* UART4 base address */ +#define HPM_UART4_BASE (0xF0050000UL) +/* UART4 base pointer */ +#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) +/* UART5 base address */ +#define HPM_UART5_BASE (0xF0054000UL) +/* UART5 base pointer */ +#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) +/* UART6 base address */ +#define HPM_UART6_BASE (0xF0058000UL) +/* UART6 base pointer */ +#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) +/* UART7 base address */ +#define HPM_UART7_BASE (0xF005C000UL) +/* UART7 base pointer */ +#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) +/* PUART base address */ +#define HPM_PUART_BASE (0xF40E4000UL) +/* PUART base pointer */ +#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) + +#include "hpm_can_regs.h" +/* Address of CAN instances */ +/* CAN0 base address */ +#define HPM_CAN0_BASE (0xF0080000UL) +/* CAN0 base pointer */ +#define HPM_CAN0 ((CAN_Type *) HPM_CAN0_BASE) +/* CAN1 base address */ +#define HPM_CAN1_BASE (0xF0084000UL) +/* CAN1 base pointer */ +#define HPM_CAN1 ((CAN_Type *) HPM_CAN1_BASE) + +#include "hpm_wdg_regs.h" +/* Address of WDOG instances */ +/* WDG0 base address */ +#define HPM_WDG0_BASE (0xF0090000UL) +/* WDG0 base pointer */ +#define HPM_WDG0 ((WDG_Type *) HPM_WDG0_BASE) +/* WDG1 base address */ +#define HPM_WDG1_BASE (0xF0094000UL) +/* WDG1 base pointer */ +#define HPM_WDG1 ((WDG_Type *) HPM_WDG1_BASE) +/* PWDG base address */ +#define HPM_PWDG_BASE (0xF40E8000UL) +/* PWDG base pointer */ +#define HPM_PWDG ((WDG_Type *) HPM_PWDG_BASE) + +#include "hpm_mbx_regs.h" +/* Address of MBX instances */ +/* MBX0A base address */ +#define HPM_MBX0A_BASE (0xF00A0000UL) +/* MBX0A base pointer */ +#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) +/* MBX0B base address */ +#define HPM_MBX0B_BASE (0xF00A4000UL) +/* MBX0B base pointer */ +#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) + +#include "hpm_ptpc_regs.h" +/* Address of PTPC instances */ +/* PTPC base address */ +#define HPM_PTPC_BASE (0xF00B0000UL) +/* PTPC base pointer */ +#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) + +#include "hpm_dmamux_regs.h" +/* Address of DMAMUX instances */ +/* DMAMUX base address */ +#define HPM_DMAMUX_BASE (0xF00C0000UL) +/* DMAMUX base pointer */ +#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) + +#include "hpm_dma_regs.h" +/* Address of DMA instances */ +/* HDMA base address */ +#define HPM_HDMA_BASE (0xF00C4000UL) +/* HDMA base pointer */ +#define HPM_HDMA ((DMA_Type *) HPM_HDMA_BASE) +/* XDMA base address */ +#define HPM_XDMA_BASE (0xF3048000UL) +/* XDMA base pointer */ +#define HPM_XDMA ((DMA_Type *) HPM_XDMA_BASE) + +#include "hpm_rng_regs.h" +/* Address of RNG instances */ +/* RNG base address */ +#define HPM_RNG_BASE (0xF00C8000UL) +/* RNG base pointer */ +#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) + +#include "hpm_keym_regs.h" +/* Address of KEYM instances */ +/* KEYM base address */ +#define HPM_KEYM_BASE (0xF00CC000UL) +/* KEYM base pointer */ +#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) + +#include "hpm_i2s_regs.h" +/* Address of I2S instances */ +/* I2S0 base address */ +#define HPM_I2S0_BASE (0xF0100000UL) +/* I2S0 base pointer */ +#define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE) +/* I2S1 base address */ +#define HPM_I2S1_BASE (0xF0104000UL) +/* I2S1 base pointer */ +#define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE) + +#include "hpm_dao_regs.h" +/* Address of DAO instances */ +/* DAO base address */ +#define HPM_DAO_BASE (0xF0110000UL) +/* DAO base pointer */ +#define HPM_DAO ((DAO_Type *) HPM_DAO_BASE) + +#include "hpm_pdm_regs.h" +/* Address of PDM instances */ +/* PDM base address */ +#define HPM_PDM_BASE (0xF0114000UL) +/* PDM base pointer */ +#define HPM_PDM ((PDM_Type *) HPM_PDM_BASE) + +#include "hpm_pwm_regs.h" +/* Address of PWM instances */ +/* PWM0 base address */ +#define HPM_PWM0_BASE (0xF0200000UL) +/* PWM0 base pointer */ +#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) +/* PWM1 base address */ +#define HPM_PWM1_BASE (0xF0210000UL) +/* PWM1 base pointer */ +#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) + +#include "hpm_hall_regs.h" +/* Address of HALL instances */ +/* HALL0 base address */ +#define HPM_HALL0_BASE (0xF0204000UL) +/* HALL0 base pointer */ +#define HPM_HALL0 ((HALL_Type *) HPM_HALL0_BASE) +/* HALL1 base address */ +#define HPM_HALL1_BASE (0xF0214000UL) +/* HALL1 base pointer */ +#define HPM_HALL1 ((HALL_Type *) HPM_HALL1_BASE) + +#include "hpm_qei_regs.h" +/* Address of QEI instances */ +/* QEI0 base address */ +#define HPM_QEI0_BASE (0xF0208000UL) +/* QEI0 base pointer */ +#define HPM_QEI0 ((QEI_Type *) HPM_QEI0_BASE) +/* QEI1 base address */ +#define HPM_QEI1_BASE (0xF0218000UL) +/* QEI1 base pointer */ +#define HPM_QEI1 ((QEI_Type *) HPM_QEI1_BASE) + +#include "hpm_trgm_regs.h" +/* Address of TRGM instances */ +/* TRGM0 base address */ +#define HPM_TRGM0_BASE (0xF020C000UL) +/* TRGM0 base pointer */ +#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) +/* TRGM1 base address */ +#define HPM_TRGM1_BASE (0xF021C000UL) +/* TRGM1 base pointer */ +#define HPM_TRGM1 ((TRGM_Type *) HPM_TRGM1_BASE) + +#include "hpm_synt_regs.h" +/* Address of SYNT instances */ +/* SYNT base address */ +#define HPM_SYNT_BASE (0xF0240000UL) +/* SYNT base pointer */ +#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) + +#include "hpm_enet_regs.h" +/* Address of ENET instances */ +/* ENET0 base address */ +#define HPM_ENET0_BASE (0xF2000000UL) +/* ENET0 base pointer */ +#define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE) + +#include "hpm_gptmr_regs.h" +/* Address of TMR instances */ +/* NTMR0 base address */ +#define HPM_NTMR0_BASE (0xF2010000UL) +/* NTMR0 base pointer */ +#define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE) +/* GPTMR0 base address */ +#define HPM_GPTMR0_BASE (0xF3000000UL) +/* GPTMR0 base pointer */ +#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) +/* GPTMR1 base address */ +#define HPM_GPTMR1_BASE (0xF3004000UL) +/* GPTMR1 base pointer */ +#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) +/* GPTMR2 base address */ +#define HPM_GPTMR2_BASE (0xF3008000UL) +/* GPTMR2 base pointer */ +#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) +/* GPTMR3 base address */ +#define HPM_GPTMR3_BASE (0xF300C000UL) +/* GPTMR3 base pointer */ +#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) +/* PTMR base address */ +#define HPM_PTMR_BASE (0xF40E0000UL) +/* PTMR base pointer */ +#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) + +#include "hpm_usb_regs.h" +/* Address of USB instances */ +/* USB0 base address */ +#define HPM_USB0_BASE (0xF2020000UL) +/* USB0 base pointer */ +#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) + +#include "hpm_sdxc_regs.h" +/* Address of SDXC instances */ +/* SDXC0 base address */ +#define HPM_SDXC0_BASE (0xF2030000UL) +/* SDXC0 base pointer */ +#define HPM_SDXC0 ((SDXC_Type *) HPM_SDXC0_BASE) + +#include "hpm_i2c_regs.h" +/* Address of I2C instances */ +/* I2C0 base address */ +#define HPM_I2C0_BASE (0xF3020000UL) +/* I2C0 base pointer */ +#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) +/* I2C1 base address */ +#define HPM_I2C1_BASE (0xF3024000UL) +/* I2C1 base pointer */ +#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) +/* I2C2 base address */ +#define HPM_I2C2_BASE (0xF3028000UL) +/* I2C2 base pointer */ +#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) +/* I2C3 base address */ +#define HPM_I2C3_BASE (0xF302C000UL) +/* I2C3 base pointer */ +#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) + +#include "hpm_sdp_regs.h" +/* Address of SDP instances */ +/* SDP base address */ +#define HPM_SDP_BASE (0xF304C000UL) +/* SDP base pointer */ +#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) + +#include "hpm_dram_regs.h" +/* Address of DRAM instances */ +/* DRAM base address */ +#define HPM_DRAM_BASE (0xF3050000UL) +/* DRAM base pointer */ +#define HPM_DRAM ((DRAM_Type *) HPM_DRAM_BASE) + +/* Address of ROMC instances */ +/* ROMC base address */ +#define HPM_ROMC_BASE (0xF3054000UL) + +#include "hpm_ffa_regs.h" +/* Address of FFA instances */ +/* FFA base address */ +#define HPM_FFA_BASE (0xF3058000UL) +/* FFA base pointer */ +#define HPM_FFA ((FFA_Type *) HPM_FFA_BASE) + +#include "hpm_sysctl_regs.h" +/* Address of SYSCTL instances */ +/* SYSCTL base address */ +#define HPM_SYSCTL_BASE (0xF4000000UL) +/* SYSCTL base pointer */ +#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) + +#include "hpm_ioc_regs.h" +/* Address of IOC instances */ +/* IOC base address */ +#define HPM_IOC_BASE (0xF4040000UL) +/* IOC base pointer */ +#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) +/* PIOC base address */ +#define HPM_PIOC_BASE (0xF40D8000UL) +/* PIOC base pointer */ +#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) +/* BIOC base address */ +#define HPM_BIOC_BASE (0xF5010000UL) +/* BIOC base pointer */ +#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) + +#include "hpm_otp_regs.h" +/* Address of OTP instances */ +/* OTPSHW base address */ +#define HPM_OTPSHW_BASE (0xF4080000UL) +/* OTPSHW base pointer */ +#define HPM_OTPSHW ((OTP_Type *) HPM_OTPSHW_BASE) +/* OTP base address */ +#define HPM_OTP_BASE (0xF40C8000UL) +/* OTP base pointer */ +#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) + +#include "hpm_ppor_regs.h" +/* Address of PPOR instances */ +/* PPOR base address */ +#define HPM_PPOR_BASE (0xF40C0000UL) +/* PPOR base pointer */ +#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) + +#include "hpm_pcfg_regs.h" +/* Address of PCFG instances */ +/* PCFG base address */ +#define HPM_PCFG_BASE (0xF40C4000UL) +/* PCFG base pointer */ +#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) + +#include "hpm_psec_regs.h" +/* Address of PSEC instances */ +/* PSEC base address */ +#define HPM_PSEC_BASE (0xF40CC000UL) +/* PSEC base pointer */ +#define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE) + +#include "hpm_pmon_regs.h" +/* Address of PMON instances */ +/* PMON base address */ +#define HPM_PMON_BASE (0xF40D0000UL) +/* PMON base pointer */ +#define HPM_PMON ((PMON_Type *) HPM_PMON_BASE) + +#include "hpm_pgpr_regs.h" +/* Address of PGPR instances */ +/* PGPR base address */ +#define HPM_PGPR_BASE (0xF40D4000UL) +/* PGPR base pointer */ +#define HPM_PGPR ((PGPR_Type *) HPM_PGPR_BASE) + +#include "hpm_pllctlv2_regs.h" +/* Address of PLLCTLV2 instances */ +/* PLLCTLV2 base address */ +#define HPM_PLLCTLV2_BASE (0xF4100000UL) +/* PLLCTLV2 base pointer */ +#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) + +#include "hpm_tsns_regs.h" +/* Address of TSNS instances */ +/* TSNS base address */ +#define HPM_TSNS_BASE (0xF4104000UL) +/* TSNS base pointer */ +#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) + +/* Address of BACC instances */ +/* BACC base address */ +#define HPM_BACC_BASE (0xF5000000UL) + +#include "hpm_bpor_regs.h" +/* Address of BPOR instances */ +/* BPOR base address */ +#define HPM_BPOR_BASE (0xF5004000UL) +/* BPOR base pointer */ +#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) + +#include "hpm_bcfg_regs.h" +/* Address of BCFG instances */ +/* BCFG base address */ +#define HPM_BCFG_BASE (0xF5008000UL) +/* BCFG base pointer */ +#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) + +#include "hpm_butn_regs.h" +/* Address of BUTN instances */ +/* BUTN base address */ +#define HPM_BUTN_BASE (0xF500C000UL) +/* BUTN base pointer */ +#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE) + +#include "hpm_bgpr_regs.h" +/* Address of BGPR instances */ +/* BGPR base address */ +#define HPM_BGPR_BASE (0xF5018000UL) +/* BGPR base pointer */ +#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) + +#include "hpm_bsec_regs.h" +/* Address of BSEC instances */ +/* BSEC base address */ +#define HPM_BSEC_BASE (0xF5040000UL) +/* BSEC base pointer */ +#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) + +#include "hpm_rtc_regs.h" +/* Address of RTC instances */ +/* RTC base address */ +#define HPM_RTC_BASE (0xF5044000UL) +/* RTC base pointer */ +#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) + +#include "hpm_bkey_regs.h" +/* Address of BKEY instances */ +/* BKEY base address */ +#define HPM_BKEY_BASE (0xF5048000UL) +/* BKEY base pointer */ +#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) + +#include "hpm_bmon_regs.h" +/* Address of BMON instances */ +/* BMON base address */ +#define HPM_BMON_BASE (0xF504C000UL) +/* BMON base pointer */ +#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) + +#include "hpm_tamp_regs.h" +/* Address of TAMP instances */ +/* TAMP base address */ +#define HPM_TAMP_BASE (0xF5050000UL) +/* TAMP base pointer */ +#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) + +#include "hpm_mono_regs.h" +/* Address of MONO instances */ +/* MONO base address */ +#define HPM_MONO_BASE (0xF5054000UL) +/* MONO base pointer */ +#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) + + +#include "riscv/riscv_core.h" +#include "hpm_csr_regs.h" +#include "hpm_interrupt.h" +#include "hpm_misc.h" +#include "hpm_dmamux_src.h" +#include "hpm_trgmmux_src.h" +#include "hpm_iomux.h" +#include "hpm_pmic_iomux.h" +#include "hpm_batt_iomux.h" +#include "hpm_ioc_regs.h" +#include "hpm_gpiom_regs.h" +#include "hpm_sysctl_regs.h" +#include "hpm_trgm_regs.h" +#endif /* HPM_SOC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h new file mode 100644 index 0000000000..d4cb0fd4c3 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SOC_FEATURE_H +#define HPM_SOC_FEATURE_H + +#include "hpm_soc.h" + +/* + * I2C Section + */ +#define I2C_SOC_FIFO_SIZE (4U) + +/* + * PMIC Section + */ +#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) +#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) +#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) +#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) +#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) +#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) + +/* + * I2S Section + */ +#define I2S_SOC_MAX_CHANNEL_NUM (16U) +#define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) +#define PDM_I2S HPM_I2S0 +#define DAO_I2S HPM_I2S1 +#define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) +#define VAD_SOC_SAMPLE_RATE_IN_HZ (16000U) +#define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U) +#define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U) +#define DAO_SOC_VAD_SAMPLE_RATE_RATIO (3U) + +/* + * PLLCTL Section + */ +#define PLLCTL_SOC_PLL_MAX_COUNT (3U) +/* PLL reference clock in hz */ +#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) +/* only PLL1 and PLL2 have DIV0, DIV1 */ +#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) +#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) + + +/* + * PWM Section + */ +#define PWM_SOC_PWM_MAX_COUNT (8U) +#define PWM_SOC_CMP_MAX_COUNT (24U) +#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) +#define PWM_SOC_OUTPUT_MAX_COUNT (24U) + +/* + * DMA Section + */ +#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) +#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) +#define DMA_SOC_BUS_NUM (1U) +#define DMA_SOC_CHANNEL_NUM (8U) +#define DMA_SOC_MAX_COUNT (2U) +#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) + +/* + * PDMA Section + */ +#define PDMA_SOC_PS_MAX_COUNT (0U) + +/* + * LCDC Section + */ +#define LCDC_SOC_MAX_LAYER_COUNT (0U) +#define LCDC_SOC_MAX_CSC_LAYER_COUNT (0U) +#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) +#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) + +/* +* USB Section +*/ +#define USB_SOC_MAX_COUNT (1U) + +#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) +#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) +#define USB_SOC_DCD_QTD_ALIGNMENT (32U) +#define USB_SOC_DCD_QHD_ALIGNMENT (64U) +#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) + +#define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) +#define USB_SOC_HCD_QTD_ALIGNMENT (32U) +#define USB_SOC_HCD_QHD_ALIGNMENT (32U) +#define USB_SOC_HCD_MAX_ENDPOINT_COUNT (8U) +#define USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT (USB_SOC_HCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) +#define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) + +/* +* ENET Section +*/ +#define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) +#define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) +#define ENET_SOC_ADDR_MAX_COUNT (5U) +#define ENET_SOC_ADVANCED_TIMESTAMP_EN (1U) +#define ENET_SOC_IPC_FULL_CHKSUM_OFFLOAD_ENGINE (0U) +#define ENET_SOC_ALT_EHD_DES_LEN (ENET_SOC_ADVANCED_TIMESTAMP_EN || ENET_SOC_IPC_FULL_CHKSUM_OFFLOAD_ENGINE) ? (8U) : (4U) +/* +* ADC Section +*/ +#define ADC_SOC_SEQ_MAX_LEN (16U) +#define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) +#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) +#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (1024U) +#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) + +#define ADC16_SOC_PARAMS_LEN (34U) +#define ADC16_SOC_MAX_CH_NUM (15U) +#define ADC16_SOC_TEMP_CH_NUM (16U) +#define ADC16_SOC_MAX_TRIG_CH_NUM (11U) + +/* + * SYSCTL Section + */ +#define SYSCTL_SOC_CPU_GPR_COUNT (14U) +#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) + +/* + * PTPC Section + */ +#define PTPC_SOC_TIMER_MAX_COUNT (2U) + +/* + * CAN Section + */ +#define CAN_SOC_MAX_COUNT (2U) + +/* + * SDP Section + */ +#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) + +/* + * SOC Privilege mdoe + */ +#define SOC_HAS_S_MODE (1U) + +/* + * DAC Section + */ +#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) +#define DAC_SOC_MAX_DATA (4095U) +#define DAC_SOC_MAX_BUFF_COUNT (65536U) +#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) + + +/* + * SDXC Section + */ +#define SDXC_SOC_HAS_MISC_CTRL0 (1) +#define SDXC_SOC_HAS_MISC_CTRL1 (1) + +/* + * UART Section + */ +#define UART_SOC_FIFO_SIZE (16U) + +/* + * SPI Section + */ +#define SPI_SOC_TRANSFER_COUNT_MAX (512U) + +/* + * SDXC Section + */ +#define SDXC_SOC_MAX_COUNT (1) + +#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c new file mode 100644 index 0000000000..ece6d90972 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sysctl_drv.h" +#include "hpm_soc_feature.h" + +#define SYSCTL_RESOURCE_GROUP0 0 +#define SYSCTL_RESOURCE_GROUP1 1 + +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24 )) + +static inline bool sysctl_valid_cpu_index(uint8_t cpu) +{ + if (cpu != SYSCTL_CPU_CPU0) { + return false; + } + return true; +} + +hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) +{ + uint32_t i; + if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { + return status_invalid_argument; + } + for (i = 0; i < size; i++) { + *(data + i) = ptr->CPU[cpu].GPR[i]; + } + return status_success; +} + +static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + *(data + i) = ptr->CPU[cpu].GPR[start + i]; + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); +} + +hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); +} + +static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + ptr->CPU[cpu].GPR[start + i] = *(data + i); + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) +{ + config->mode = monitor_work_mode_record; + config->accuracy = monitor_accuracy_1khz; + config->reference = monitor_reference_24mhz; + config->divide_by = 1; + config->high_limit = 0; + config->low_limit = 0; + config->start_measure = true; + config->enable_output = false; + config->target = monitor_target_clk_top_cpu0; +} + +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t slice, monitor_config_t *config) +{ + ptr->MONITOR[slice].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + + if (config->mode == monitor_work_mode_compare) { + ptr->MONITOR[slice].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[slice].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + } + + ptr->MONITOR[slice].CONTROL = (ptr->MONITOR[slice].CONTROL & + ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | + SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | + (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | + SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | + SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | + SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | + SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | + SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); +} + +uint32_t +sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_target_t target, bool enable_output) +{ + uint32_t frequency = 0; + monitor_config_t monitor = { 0 }; + sysctl_monitor_get_default_config(ptr, &monitor); + monitor.target = target; + monitor.enable_output = enable_output; + sysctl_monitor_init(ptr, monitor_index, &monitor); + if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { + frequency = sysctl_monitor_get_current_result(ptr, monitor_index); + } + return frequency; +} + +static hpm_stat_t _sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) +{ + if (!sysctl_valid_cpu_index(cpu)) { + return status_invalid_argument; + } + ptr->CPU[cpu].GPR[0] = entry; + ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); + return status_success; +} + +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return _sysctl_set_cpu_entry(ptr, 0, entry); +} + +hpm_stat_t sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu, cpu_lp_mode_t mode) +{ + if (!sysctl_valid_cpu_index(cpu)) { + return status_invalid_argument; + } + ptr->CPU[cpu].LP = (ptr->CPU[cpu].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); + return status_success; +} + +hpm_stat_t +sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource, bool enable) +{ + uint32_t index, offset; + if (linkable_resource < sysctl_resource_linkable_start) { + return status_invalid_argument; + } + + index = (linkable_resource - sysctl_resource_linkable_start) / 32; + offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); +} + +hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_i2s_t source) +{ + uint32_t index; + if ((node < clock_node_adc_i2s_start) || (source >= clock_source_adc_i2s_clk_end)) { + return status_invalid_argument; + } + + switch (node) { + case clock_node_adc2: + case clock_node_adc1: + case clock_node_adc0: + index = node - clock_node_adc0; + ptr->ADCCLK[index] = (ptr->ADCCLK[index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); + break; + case clock_node_i2s1: + case clock_node_i2s0: + index = node - clock_node_i2s0; + ptr->I2SCLK[index] = (ptr->I2SCLK[index] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(source); + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_i2s_start) { + return status_invalid_argument; + } + + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); + while (sysctl_clock_target_is_busy(ptr, node)) { } + return status_success; +} + +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, clock_source_t source, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_i2s_start) { + return status_invalid_argument; + } + + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | + (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); + while (sysctl_clock_target_is_busy(ptr, node)) { } + return status_success; +} + +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, + clock_source_t source, + uint32_t cpu_div, + uint32_t axi_sub_div, + uint32_t ahb_sub_div) +{ + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + + uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; + if (origin_cpu_div == cpu_div) { + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | + SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + } + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | + SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); + + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h new file mode 100644 index 0000000000..cb10353254 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h @@ -0,0 +1,1016 @@ +/** + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SYSCTL_DRV_H +#define HPM_SYSCTL_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_regs.h" + +/** + * + * @brief SYSCTL driver APIs + * @defgroup sysctl_interface SYSCTL driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Retention domains + */ +typedef enum { + sysctl_retention_domain_sys = 0, + sysctl_retention_domain_cpu0 = 2, + sysctl_retention_domain_cpu1 = 4, + sysctl_retention_domain_conn = 6, + sysctl_retention_domain_vis = 8, + sysctl_retention_domain_xtal24m = 10, + sysctl_retention_domain_pll0 = 11, + sysctl_retention_domain_pll1 = 12, + sysctl_retention_domain_pll2 = 13, + sysctl_retention_domain_pll3 = 14, + sysctl_retention_domain_pll4 = 15, +} sysctl_retention_domain_t; + +/** + * @brief Clock presets + */ +typedef enum { + sysctl_preset_0 = 1 << 0, sysctl_preset_1 = 1 << 1, sysctl_preset_2 = 1 << 2, sysctl_preset_3 = 1 << 3, +} sysctl_preset_t; + +/** + * @brief Reset domains + */ +typedef enum { + sysctl_reset_domain_soc = 0, + sysctl_reset_domain_con, + sysctl_reset_domain_vis, + sysctl_reset_domain_cpu0, + sysctl_reset_domain_cpu1, +} sysctl_reset_domain_t; + +/** + * @brief Resource + */ +typedef enum { + sysctl_resource_cpu0 = 0, + sysctl_resource_cpx0 = 1, + sysctl_resource_exe0 = 2, + sysctl_resource_wak0 = 3, + sysctl_resource_cpu0_per = 4, + sysctl_resource_logic0 = 16, + sysctl_resource_logic1 = 17, + sysctl_resource_logic2 = 18, + sysctl_resource_logic3 = 19, + sysctl_resource_pmic = 20, + sysctl_resource_pow_cpu0 = 21, + sysctl_resource_rst_soc = 22, + sysctl_resource_rst_cpu0 = 23, + sysctl_resource_xtal = 32, + sysctl_resource_pll0 = 33, + sysctl_resource_clk0_pll0 = 34, + sysctl_resource_clk1_pll0 = 35, + sysctl_resource_clk2_pll0 = 36, + sysctl_resource_pll1 = 37, + sysctl_resource_clk0_pll1 = 38, + sysctl_resource_clk1_pll1 = 39, + sysctl_resource_pll2 = 40, + sysctl_resource_clk0_pll2 = 41, + sysctl_resource_clk1_pll2 = 42, + sysctl_resource_pll0_ref = 43, + sysctl_resource_pll1_ref = 44, + sysctl_resource_pll2_ref = 45, + sysctl_resource_mbist_soc = 48, + sysctl_resource_mbist_cpu = 49, + sysctl_resource_mbist_con = 50, + sysctl_resource_dft_start_bus = 51, + sysctl_resource_clk_top_cpu0 = 64, + sysctl_resource_clk_top_mchtmr0 = 65, + sysctl_resource_clk_top_dram = 66, + sysctl_resource_clk_top_xpi0 = 67, + sysctl_resource_clk_top_xpi1 = 68, + sysctl_resource_clk_top_gptmr0 = 69, + sysctl_resource_clk_top_gptmr1 = 70, + sysctl_resource_clk_top_gptmr2 = 71, + sysctl_resource_clk_top_gptmr3 = 72, + sysctl_resource_clk_top_uart0 = 73, + sysctl_resource_clk_top_uart1 = 74, + sysctl_resource_clk_top_uart2 = 75, + sysctl_resource_clk_top_uart3 = 76, + sysctl_resource_clk_top_uart4 = 77, + sysctl_resource_clk_top_uart5 = 78, + sysctl_resource_clk_top_uart6 = 79, + sysctl_resource_clk_top_uart7 = 80, + sysctl_resource_clk_top_i2c0 = 81, + sysctl_resource_clk_top_i2c1 = 82, + sysctl_resource_clk_top_i2c2 = 83, + sysctl_resource_clk_top_i2c3 = 84, + sysctl_resource_clk_top_spi0 = 85, + sysctl_resource_clk_top_spi1 = 86, + sysctl_resource_clk_top_spi2 = 87, + sysctl_resource_clk_top_spi3 = 88, + sysctl_resource_clk_top_can0 = 89, + sysctl_resource_clk_top_can1 = 90, + sysctl_resource_clk_top_ptpc = 91, + sysctl_resource_clk_top_ana0 = 92, + sysctl_resource_clk_top_ana1 = 93, + sysctl_resource_clk_top_ana2 = 94, + sysctl_resource_clk_top_ana3 = 95, + sysctl_resource_clk_top_aud0 = 96, + sysctl_resource_clk_top_aud1 = 97, + sysctl_resource_clk_top_eth0 = 98, + sysctl_resource_clk_top_ptp0 = 99, + sysctl_resource_clk_top_ref0 = 100, + sysctl_resource_clk_top_ref1 = 101, + sysctl_resource_clk_top_ntmr0 = 102, + sysctl_resource_clk_top_sdxc0 = 103, + sysctl_resource_clk_top_adc0 = 128, + sysctl_resource_clk_top_adc1 = 129, + sysctl_resource_clk_top_adc2 = 130, + sysctl_resource_clk_top_dac0 = 131, + sysctl_resource_clk_top_i2s0 = 132, + sysctl_resource_clk_top_i2s1 = 133, + + sysctl_resource_eth0_mem = 192, + sysctl_resource_sdxc0_mem = 193, + sysctl_resource_usb0_mem = 194, + sysctl_resource_ram0_mem = 195, + sysctl_resource_ahbp_mem = 196, + sysctl_resource_dram_mem = 197, + sysctl_resource_rom0_mem = 198, + sysctl_resource_xpi0_mem = 199, + sysctl_resource_xpi1_mem = 200, + sysctl_resource_can0_mem = 201, + sysctl_resource_can1_mem = 202, + sysctl_resource_i2s0_mem = 203, + sysctl_resource_i2s1_mem = 204, + sysctl_resource_pdm0_mem = 205, + sysctl_resource_sdp0_mem = 206, + sysctl_resource_ffa0_mem = 207, + sysctl_resource_cpx_mem = 208, + sysctl_resource_core_mem = 209, + sysctl_resource_lmm0_mem = 210, + + + sysctl_resource_linkable_start = 256, + sysctl_resource_ahbp = 256, + sysctl_resource_axis = 257, + sysctl_resource_axic = 258, + sysctl_resource_dram = 259, + sysctl_resource_rom0 = 260, + sysctl_resource_lmm0 = 261, + sysctl_resource_ram0 = 262, + sysctl_resource_mchtmr0 = 263, + sysctl_resource_xpi0 = 264, + sysctl_resource_xpi1 = 265, + sysctl_resource_sdp0 = 266, + sysctl_resource_rng0 = 267, + sysctl_resource_kman = 268, + sysctl_resource_dma0 = 269, + sysctl_resource_dma1 = 270, + sysctl_resource_ffa0 = 271, + sysctl_resource_gpio = 272, + sysctl_resource_mbx0 = 273, + sysctl_resource_wdg0 = 274, + sysctl_resource_wdg1 = 275, + sysctl_resource_tsns = 276, + sysctl_resource_gptmr0 = 277, + sysctl_resource_gptmr1 = 278, + sysctl_resource_gptmr2 = 279, + sysctl_resource_gptmr3 = 280, + sysctl_resource_uart0 = 281, + sysctl_resource_uart1 = 282, + sysctl_resource_uart2 = 283, + sysctl_resource_uart3 = 284, + sysctl_resource_uart4 = 285, + sysctl_resource_uart5 = 286, + sysctl_resource_uart6 = 287, + sysctl_resource_uart7 = 288, + sysctl_resource_i2c0 = 289, + sysctl_resource_i2c1 = 290, + sysctl_resource_i2c2 = 291, + sysctl_resource_i2c3 = 292, + sysctl_resource_spi0 = 293, + sysctl_resource_spi1 = 294, + sysctl_resource_spi2 = 295, + sysctl_resource_spi3 = 296, + sysctl_resource_can0 = 297, + sysctl_resource_can1 = 298, + sysctl_resource_ptpc = 299, + sysctl_resource_adc0 = 300, + sysctl_resource_adc1 = 301, + sysctl_resource_adc2 = 302, + sysctl_resource_dac0 = 303, + sysctl_resource_acmp = 304, + sysctl_resource_i2s0 = 305, + sysctl_resource_i2s1 = 306, + sysctl_resource_i2spdm0 = 307, + sysctl_resource_i2sdao = 308, + sysctl_resource_msyn = 309, + sysctl_resource_mot0 = 310, + sysctl_resource_mot1 = 311, + sysctl_resource_eth0 = 312, + sysctl_resource_ntmr0 = 313, + sysctl_resource_sdxc0 = 314, + sysctl_resource_usb0 = 315, + sysctl_resource_ref0 = 316, + sysctl_resource_ref1 = 317, + sysctl_resource_linkable_end, + sysctl_resource_end = sysctl_resource_linkable_end, +} sysctl_resource_t; + +/** + * @brief Resource modes + */ +typedef enum { + sysctl_resource_mode_auto = 0, + sysctl_resource_mode_force_on, + sysctl_resource_mode_force_off, +} sysctl_resource_mode_t; + +/** + * @brief Clock nodes + */ +typedef enum { + clock_node_mchtmr0 = 0, + clock_node_dram = 1, + clock_node_xpi0 = 2, + clock_node_xpi1 = 3, + clock_node_gptmr0 = 4, + clock_node_gptmr1 = 5, + clock_node_gptmr2 = 6, + clock_node_gptmr3 = 7, + clock_node_uart0 = 8, + clock_node_uart1 = 9, + clock_node_uart2 = 10, + clock_node_uart3 = 11, + clock_node_uart4 = 12, + clock_node_uart5 = 13, + clock_node_uart6 = 14, + clock_node_uart7 = 15, + clock_node_i2c0 = 16, + clock_node_i2c1 = 17, + clock_node_i2c2 = 18, + clock_node_i2c3 = 19, + clock_node_spi0 = 20, + clock_node_spi1 = 21, + clock_node_spi2 = 22, + clock_node_spi3 = 23, + clock_node_can0 = 24, + clock_node_can1 = 25, + clock_node_ptpc = 26, + clock_node_ana0 = 27, + clock_node_ana1 = 28, + clock_node_ana2 = 29, + clock_node_ana3 = 30, + clock_node_aud0 = 31, + clock_node_aud1 = 32, + clock_node_eth0 = 33, + clock_node_ptp0 = 34, + clock_node_ref0 = 35, + clock_node_ref1 = 36, + clock_node_ntmr0 = 37, + clock_node_sdxc0 = 38, + + clock_node_adc_i2s_start, + clock_node_adc0 = clock_node_adc_i2s_start, + clock_node_adc1, + clock_node_adc2, + + clock_node_i2s0, + clock_node_i2s1, + + clock_node_end, + + clock_node_core_start = 0xfc, + clock_node_cpu0 = clock_node_core_start, + clock_node_axi, + clock_node_ahb, +} clock_node_t; + +/** + * @brief General clock sources + */ +typedef enum { + clock_source_osc0_clk0 = 0, + clock_source_pll0_clk0 = 1, + clock_source_pll0_clk1 = 2, + clock_source_pll0_clk2 = 3, + clock_source_pll1_clk0 = 4, + clock_source_pll1_clk1 = 5, + clock_source_pll2_clk0 = 6, + clock_source_pll2_clk1 = 7, + clock_source_general_source_end, +} clock_source_t; + +/** + * @brief ADC/I2S clock sources + */ +typedef enum { + clock_source_adc_ana_clk = 0, + clock_source_adc_ahb_clk = 1, + clock_source_i2s_aud0_clk = 0, + clock_source_i2s_aud1_clk = 1, + clock_source_adc_i2s_clk_end, +} clock_source_adc_i2s_t; + +/** + * @brief CPU low power mode + */ +typedef enum { + cpu_lp_mode_gate_cpu_clock = 0, + cpu_lp_mode_trigger_system_lp = 0x1, + cpu_lp_mode_ungate_cpu_clock = 0x2, +} cpu_lp_mode_t; + +/** + * @brief Monitor targets + */ +typedef enum { + monitor_target_clk_32k = 0, + monitor_target_clk_irc24m = 1, + monitor_target_clk_xtal_24m = 2, + monitor_target_clk_usb0_phy = 3, + monitor_target_clk_usb1_phy = 4, + monitor_target_clk0_osc0 = 8, + monitor_target_clk0_pll0 = 9, + monitor_target_clk0_pll1 = 10, + monitor_target_clk1_pll1 = 11, + monitor_target_clk0_pll2 = 12, + monitor_target_clk1_pll2 = 13, + monitor_target_clk0_pll3 = 14, + monitor_target_clk0_pll4 = 15, + monitor_target_clk_top_cpu0 = 128, + monitor_target_clk_top_mchtmr0 = 129, + monitor_target_clk_top_cpu1 = 130, + monitor_target_clk_top_mchtmr1 = 131, + monitor_target_clk_top_axi0 = 132, + monitor_target_clk_top_axi1 = 133, + monitor_target_clk_top_axi2 = 134, + monitor_target_clk_top_ahb0 = 135, + monitor_target_clk_top_dram = 136, + monitor_target_clk_top_xpi0 = 137, + monitor_target_clk_top_xpi1 = 138, + monitor_target_clk_top_gptmr0 = 139, + monitor_target_clk_top_gptmr1 = 140, + monitor_target_clk_top_gptmr2 = 141, + monitor_target_clk_top_gptmr3 = 142, + monitor_target_clk_top_gptmr4 = 143, + monitor_target_clk_top_gptmr5 = 144, + monitor_target_clk_top_gptmr6 = 145, + monitor_target_clk_top_gptmr7 = 146, + monitor_target_clk_top_uart0 = 147, + monitor_target_clk_top_uart1 = 148, + monitor_target_clk_top_uart2 = 149, + monitor_target_clk_top_uart3 = 150, + monitor_target_clk_top_uart4 = 151, + monitor_target_clk_top_uart5 = 152, + monitor_target_clk_top_uart6 = 153, + monitor_target_clk_top_uart7 = 154, + monitor_target_clk_top_uart8 = 155, + monitor_target_clk_top_uart9 = 156, + monitor_target_clk_top_uarta = 157, + monitor_target_clk_top_uartb = 158, + monitor_target_clk_top_uartc = 159, + monitor_target_clk_top_uartd = 160, + monitor_target_clk_top_uarte = 161, + monitor_target_clk_top_uartf = 162, + monitor_target_clk_top_i2c0 = 163, + monitor_target_clk_top_i2c1 = 164, + monitor_target_clk_top_i2c2 = 165, + monitor_target_clk_top_i2c3 = 166, + monitor_target_clk_top_spi0 = 167, + monitor_target_clk_top_spi1 = 168, + monitor_target_clk_top_spi2 = 169, + monitor_target_clk_top_spi3 = 170, + monitor_target_clk_top_can0 = 171, + monitor_target_clk_top_can1 = 172, + monitor_target_clk_top_can2 = 173, + monitor_target_clk_top_can3 = 174, + monitor_target_clk_top_ptpc = 175, + monitor_target_clk_top_ana0 = 176, + monitor_target_clk_top_ana1 = 177, + monitor_target_clk_top_ana2 = 178, + monitor_target_clk_top_aud0 = 179, + monitor_target_clk_top_aud1 = 180, + monitor_target_clk_top_aud2 = 181, + monitor_target_clk_top_dis0 = 182, + monitor_target_clk_top_cam0 = 183, + monitor_target_clk_top_cam1 = 184, + monitor_target_clk_top_eth0 = 185, + monitor_target_clk_top_eth1 = 186, + monitor_target_clk_top_ptp0 = 187, + monitor_target_clk_top_ptp1 = 188, + monitor_target_clk_top_ref0 = 189, + monitor_target_clk_top_ref1 = 190, + monitor_target_clk_top_ntmr0 = 191, + monitor_target_clk_top_ntmr1 = 192, + monitor_target_clk_top_sdxc0 = 193, + monitor_target_clk_top_sdxc1 = 194, +} monitor_target_t; + +/** + * @brief Monitor work mode + */ +typedef enum { + monitor_work_mode_compare = 0, monitor_work_mode_record = 1, +} monitor_work_mode_t; + +/** + * @brief Monitor accuracy + */ +typedef enum { + monitor_accuracy_1khz = 0, monitor_accuracy_1hz = 1, +} monitor_accuracy_t; + +/** + * @brief Monitor reference clock source + */ +typedef enum { + monitor_reference_32khz = 0, monitor_reference_24mhz = 1, +} monitor_reference_t; + +/** + * @brief Monitor config + */ +typedef struct monitor_config { + uint8_t divide_by; /**< Divider to be used for OBS output to pads */ + monitor_work_mode_t mode; /**< Monitor work mode */ + monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ + monitor_reference_t reference; /**< Monitor reference clock source */ + monitor_target_t target; /**< Monitor target */ + bool start_measure; /**< Start flag */ + bool enable_output; /**< Enable output to pads if true */ + uint32_t high_limit; /**< Maximum frequency at compare mode */ + uint32_t low_limit; /**< Minimum frequency at compare mode */ +} monitor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if monitor result is valid + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * + * @return true if it is valid + */ +static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); +} + +/** + * @brief Get target monitor instance result + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return value of monitor result measured + */ +static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { + } + return ptr->MONITOR[monitor_index].CURRENT; +} + +/** + * @brief Set work mode for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record + */ +static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) +{ + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | + (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); +} + +/** + * @brief Set minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement high limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set frequency limit for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit_high measurement high limit + * @param[in] limit_low measurement low limit + */ +static inline hpm_stat_t +sysctl_monitor_set_limit(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit_high, uint32_t limit_low) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); + return status_success; +} + +/** + * @brief Get maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current high limit value + */ +static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); +} + +/** + * @brief Get minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current low limit value + */ +static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); +} + +/** + * @brief Measure specific target frequency + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] target monitor target to be measured + * @param[in] enable_output enable clock obs output + * @return frequency of monitor target measured + */ +uint32_t +sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_target_t target, bool enable_output); + +/** + * @brief Link current CPU core its own group + * + * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; +} + +/** + * @brief Unlink current CPU core with its own group + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; +} + +/** + * @brief Check if any resource is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any resource is busy + */ +static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; +} + +/** + * @brief Check if specific target is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return true if target resource is busy + */ +static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; +} + +/** + * @brief Set target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @param[in] mode target resource mode + */ +static inline void +sysctl_resource_target_set_mode(SYSCTL_Type *ptr, sysctl_resource_t resource, sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Disable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to clear + */ +static inline void sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].CLEAR = mask; +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to set + */ +static inline void sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].SET = mask; +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void +sysctl_cpu_lp_retain_domain(SYSCTL_Type *ptr, uint8_t cpu_index, sysctl_retention_domain_t domain, bool retain_mem) +{ + uint8_t set_mask = 0x1; + if (domain < sysctl_retention_domain_xtal24m) { + set_mask = retain_mem ? 0x3 : 0x1; + } + ptr->RETENTION[cpu_index].SET = (set_mask << domain); +} + +/** + * @brief Check if cpu clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; +} + +/** + * @brief Check if any clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; +} + +/** + * @brief Check if target clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + * @return true if target clock is busy + */ +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock) +{ + return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; +} + +/** + * @brief Set clock preset + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] preset preset + */ +static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) +{ + ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); +} + +/** + * @brief Check if target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken wakeup reset + */ +static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken reset + */ +static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain for all reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Get target CPU wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; +} + +/** + * @brief Check wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t +sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index, uint32_t mask) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; +} + +/** + * @brief Enable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void +sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t enable_index, uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Disable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void +sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t enable_index, uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; +} + +/** + * @brief Disable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); +} + +/** + * @brief Enable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num % 32); +} + +/** + * @brief Lock CPU0 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +{ + ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + +/** + * @brief Lock CPU0 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) +{ + ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; +} + +/** + * @brief Config lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @param[in] divide_by clock frequency divider + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); + +/** + * @brief Configure CPU domain clock + * @param ptr SYSCTL base address + * @param source clock source to be used + * @param cpu_div CPU divider + * @param axi_sub_div AXI BUS divider based on divided CPU clock + * @param ahb_sub_div AHB BUS divider based on divided CPU clock + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, clock_source_t source, uint32_t cpu_div, + uint32_t axi_sub_div, uint32_t ahb_sub_div); + +/** + * @brief Set ADC/I2S clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_i2s_t source); + +/** + * @brief Set CPU low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mode target mode to set + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode); + +/** + * @brief Enable group resource + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be modified + * @param[in] resource target resource to be added/removed from group + * @param[in] enable set true to add resource, remove otherwise + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); +/** + * @brief Add resource to CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource resource to be added to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Get default monitor config + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); + +/** + * @brief Initialize Monitor + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index Monitor instance to be initialized + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); + +/** + * @brief Save data to GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); + +/** + * @brief Get data saved from GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set entry point on CPU0 wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU0 on its wakeup + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h new file mode 100644 index 0000000000..ffe34cb8c9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h @@ -0,0 +1,1324 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SYSCTL_H +#define HPM_SYSCTL_H + +typedef struct { + __RW uint32_t RESOURCE[318]; /* 0x0 - 0x4F4: Resource control register for cpu0_core */ + __R uint8_t RESERVED0[776]; /* 0x4F8 - 0x7FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x800: Group setting */ + __RW uint32_t SET; /* 0x804: Group setting */ + __RW uint32_t CLEAR; /* 0x808: Group setting */ + __RW uint32_t TOGGLE; /* 0x80C: Group setting */ + } GROUP0[2]; + __R uint8_t RESERVED1[224]; /* 0x820 - 0x8FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ + __RW uint32_t SET; /* 0x904: Affiliate of Group */ + __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ + __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ + } AFFILIATE[1]; + __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x920: Retention Contol */ + __RW uint32_t SET; /* 0x924: Retention Contol */ + __RW uint32_t CLEAR; /* 0x928: Retention Contol */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ + } RETENTION[1]; + __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ + struct { + __RW uint32_t STATUS; /* 0x1000: Power Setting */ + __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ + __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ + __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ + } POWER[1]; + __R uint8_t RESERVED4[1008]; /* 0x1010 - 0x13FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ + __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ + __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ + __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ + } RESET[2]; + __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */ + __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ + __RW uint32_t CLOCK[39]; /* 0x1804 - 0x189C: Clock setting */ + __R uint8_t RESERVED6[864]; /* 0x18A0 - 0x1BFF: Reserved */ + __RW uint32_t ADCCLK[3]; /* 0x1C00 - 0x1C08: Clock setting */ + __RW uint32_t DACCLK[1]; /* 0x1C0C: Clock setting */ + __RW uint32_t I2SCLK[2]; /* 0x1C10 - 0x1C14: Clock setting */ + __R uint8_t RESERVED7[1000]; /* 0x1C18 - 0x1FFF: Reserved */ + __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ + __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ + __R uint32_t CURRENT; /* 0x2404: Clock measure result */ + __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ + __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ + __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ + } MONITOR[4]; + __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ + struct { + __RW uint32_t LP; /* 0x2800: CPU0 LP control */ + __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ + __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ + __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ + __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ + __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ + __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ + } CPU[1]; +} SYSCTL_Type; + + +/* Bitfield definition for register array: RESOURCE */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any nodes + * 1: any of nodes is changing status + */ +#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) +#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: no change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) +#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) + +/* + * MODE (RW) + * + * resource work mode + * 0:auto turn on and off as system required(recommended) + * 1:always on + * 2:always off + * 3:reserved + */ +#define SYSCTL_RESOURCE_MODE_MASK (0x3U) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) +#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) +#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: add periphera into this group，periphera is needed + */ +#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) +#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: delete periphera in this group，periphera is not needed + */ +#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) +#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: toggle the result that whether periphera is needed before + */ +#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: VALUE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * bit0: cpu0 depends on group0 + * bit1: cpu0 depends on group1 + * bit2: cpu0 depends on group2 + * bit3: cpu0 depends on group3 + */ +#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) +#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: SET */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0，each bit represents a group + * 0: no effect + * 1: the group is assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) +#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: the group is not assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) +#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: toggle the result that whether the group is assigned to CPU0 before + */ +#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: VALUE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * bit00: soc_mem is kept on while cpu stop, + * bit01: soc_ctx is kept on while cpu stop, + * bit02: cpu0_mem is kept on while cpu stop, + * bit03: cpu0_ctx is kept on while cpu stop, + * bit04: xtal_hold is kept on while cpu stop, + * bit05: pll0_hold is kept on while cpu stop, + * bit06: pll1_hold is kept on while cpu stop, + * bit07: pll2_hold is kept on while cpu stop, + */ +#define SYSCTL_RETENTION_VALUE_LINK_MASK (0xFFU) +#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) +#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: SET */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: keep + */ +#define SYSCTL_RETENTION_SET_LINK_MASK (0xFFU) +#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) +#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: CLEAR */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: no keep + */ +#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0xFFU) +#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) +#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: TOGGLE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: toggle the result that whether the resource is kept on while CPU0 stop before + */ +#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0xFFU) +#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) +#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array POWER: STATUS */ +/* + * FLAG (RW) + * + * flag represents power cycle happened from last clear of this bit + * 0: power domain did not edurance power cycle since last clear of this bit + * 1: power domain enduranced power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) +#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) +#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) +#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup power cycle happened from last clear of this bit + * 0: power domain did not edurance wakeup power cycle since last clear of this bit + * 1: power domain enduranced wakeup power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) + +/* + * LF_DISABLE (RO) + * + * low fanout power switch disable + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) + +/* + * LF_ACK (RO) + * + * low fanout power switch feedback + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) +#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) +#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) + +/* Bitfield definition for register of struct array POWER: LF_WAIT */ +/* + * WAIT (RW) + * + * wait time for low fan out power switch turn on, default value is 255 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: OFF_WAIT */ +/* + * WAIT (RW) + * + * wait time for power switch turn off, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONTROL */ +/* + * FLAG (RW) + * + * flag represents reset happened from last clear of this bit + * 0: domain did not edurance reset cycle since last clear of this bit + * 1: domain enduranced reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) +#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup reset happened from last clear of this bit + * 0: domain did not edurance wakeup reset cycle since last clear of this bit + * 1: domain enduranced wakeup reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) + +/* + * HOLD (RW) + * + * perform reset and hold in reset, until ths bit cleared by software + * 0: reset is released for function + * 1: reset is assert and hold + */ +#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) +#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) +#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) +#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) + +/* + * RESET (RW) + * + * perform reset and release imediately + * 0: reset is released + * 1 reset is asserted and will release automaticly + */ +#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) +#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) +#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) +#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONFIG */ +/* + * PRE_WAIT (RW) + * + * wait cycle numbers before assert reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) + +/* + * RSTCLK_NUM (RW) + * + * reset clock number(must be even number) + * 0: 0 cycle + * 1: 0 cycles + * 2: 2 cycles + * 3: 2 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) + +/* + * POST_WAIT (RW) + * + * time guard band for reset release + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: COUNTER */ +/* + * COUNTER (RW) + * + * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) +#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) +#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +/* Bitfield definition for register array: CLOCK_CPU */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) +#define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) + +/* + * SUB1_DIV (RW) + * + * ahb bus divider, the bus clock is generated by cpu_clock/div + * 0: divider by 1 + * 1: divider by 2 + * … + */ +#define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xF00000UL) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20U) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) + +/* + * SUB0_DIV (RW) + * + * axi bus divider, the bus clock is generated by cpu_clock/div + * 0: divider by 1 + * 1: divider by 2 + * … + */ +#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll2_clk0 + * 7:pll2_clk1 + */ +#define SYSCTL_CLOCK_CPU_MUX_MASK (0xF00U) +#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) +#define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) +#define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) + +/* Bitfield definition for register array: CLOCK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) +#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll2_clk0 + * 7:pll2_clk1 + */ +#define SYSCTL_CLOCK_MUX_MASK (0xF00U) +#define SYSCTL_CLOCK_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) +#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) +#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) + +/* Bitfield definition for register array: ADCCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) +#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ana clock + * 1: ahb clock + */ +#define SYSCTL_ADCCLK_MUX_MASK (0x100U) +#define SYSCTL_ADCCLK_MUX_SHIFT (8U) +#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) +#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) + +/* Bitfield definition for register array: DACCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) +#define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ana clock + * 1: ahb clock + */ +#define SYSCTL_DACCLK_MUX_MASK (0x100U) +#define SYSCTL_DACCLK_MUX_SHIFT (8U) +#define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) +#define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) + +/* Bitfield definition for register array: I2SCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_I2SCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_I2SCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_I2SCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_PRESERVE_SHIFT) & SYSCTL_I2SCLK_PRESERVE_MASK) +#define SYSCTL_I2SCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_PRESERVE_MASK) >> SYSCTL_I2SCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: aud clock 0 + * 1: aud clock 1 + */ +#define SYSCTL_I2SCLK_MUX_MASK (0x100U) +#define SYSCTL_I2SCLK_MUX_SHIFT (8U) +#define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK) +#define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT) + +/* Bitfield definition for register: GLOBAL00 */ +/* + * MUX (RW) + * + * global clock override request + * bit0: override to preset0 + * bit1: override to preset1 + * bit2: override to preset2 + * bit3: override to preset3 + */ +#define SYSCTL_GLOBAL00_MUX_MASK (0xFU) +#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) +#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) +#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * VALID (RW) + * + * result is ready for read + * 0: not ready + * 1: result is ready + */ +#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) +#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) +#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) +#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) + +/* + * DIV_BUSY (RO) + * + * divider is applying new setting + */ +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) + +/* + * OUTEN (RW) + * + * enable clock output + */ +#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) +#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) + +/* + * DIV (RW) + * + * output divider + */ +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) +#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) +#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) + +/* + * HIGH (RW) + * + * clock frequency higher than upper limit + */ +#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) +#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) + +/* + * LOW (RW) + * + * clock frequency lower than lower limit + */ +#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) +#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) +#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) +#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) + +/* + * START (RW) + * + * start measurement + */ +#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) +#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) +#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) +#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) + +/* + * MODE (RW) + * + * work mode, + * 0: register value will be compared to measurement + * 1: upper and lower value will be recordered in register + */ +#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) +#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) +#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) +#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) + +/* + * ACCURACY (RW) + * + * measurement accuracy, + * 0: resolution is 1kHz + * 1: resolution is 1Hz + */ +#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) + +/* + * REFERENCE (RW) + * + * refrence clock selection, + * 0: 32k + * 1: 24M + */ +#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) + +/* + * SELECTION (RW) + * + * clock measurement selection + */ +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) +#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CURRENT */ +/* + * FREQUENCY (RO) + * + * self updating measure result + */ +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ +/* + * FREQUENCY (RW) + * + * lower frequency + */ +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ +/* + * FREQUENCY (RW) + * + * upper frequency + */ +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array CPU: LP */ +/* + * WAKE_CNT (RW) + * + * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + */ +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) +#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) +#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) + +/* + * HALT (RW) + * + * halt request for CPU0, + * 0: CPU0 will start to execute after reset or receive wakeup request + * 1: CPU0 will not start after reset, or wakeup after WFI + */ +#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) +#define SYSCTL_CPU_LP_HALT_SHIFT (16U) +#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) +#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) + +/* + * WAKE (RO) + * + * CPU0 is waking up + * 0: CPU0 wake up not asserted + * 1: CPU0 wake up asserted + */ +#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) +#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) +#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) + +/* + * EXEC (RO) + * + * CPU0 is executing + * 0: CPU0 is not executing + * 1: CPU0 is executing + */ +#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) +#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) +#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) + +/* + * WAKE_FLAG (RW) + * + * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit + * 0: CPU0 wakeup not happened + * 1: CPU0 wake up happened + */ +#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) +#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) + +/* + * SLEEP_FLAG (RW) + * + * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit + * 0: CPU0 sleep not happened + * 1: CPU0 sleep happened + */ +#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) +#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) + +/* + * RESET_FLAG (RW) + * + * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit + * 0: CPU0 reset not happened + * 1: CPU0 reset happened + */ +#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) +#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) +#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) +#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) + +/* + * MODE (RW) + * + * Low power mode, system behavior after WFI + * 00: CPU clock stop after WFI + * 01: System enter low power mode after WFI + * 10: Keep running after WFI + * 11: reserved + */ +#define SYSCTL_CPU_LP_MODE_MASK (0x3U) +#define SYSCTL_CPU_LP_MODE_SHIFT (0U) +#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) +#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) + +/* Bitfield definition for register of struct array CPU: LOCK */ +/* + * GPR (RW) + * + * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + */ +#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) +#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) +#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) + +/* + * LOCK (RW) + * + * Lock bit for CPU_LOCK + */ +#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) +#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) +#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) +#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register of struct array CPU: GPR0 */ +/* + * GPR (RW) + * + * register for software to handle resume, can save resume address or status + */ +#define SYSCTL_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_GPR_GPR_SHIFT (0U) +#define SYSCTL_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_GPR_GPR_SHIFT) & SYSCTL_GPR_GPR_MASK) +#define SYSCTL_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_GPR_GPR_MASK) >> SYSCTL_GPR_GPR_SHIFT) + +/* Bitfield definition for register of struct array CPU: STATUS0 */ +/* + * STATUS (RO) + * + * IRQ values + */ +#define SYSCTL_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_WAKEUP_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register of struct array CPU: ENABLE0 */ +/* + * ENABLE (RW) + * + * IRQ wakeup enable + */ +#define SYSCTL_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT) + + + +/* RESOURCE register group index macro definition */ +#define SYSCTL_RESOURCE_CPU0 (0UL) +#define SYSCTL_RESOURCE_CPX0 (1UL) +#define SYSCTL_RESOURCE_POW_CPU0 (21UL) +#define SYSCTL_RESOURCE_RST_SOC (22UL) +#define SYSCTL_RESOURCE_RST_CPU0 (23UL) +#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) +#define SYSCTL_RESOURCE_CLK_TOP_DRAM (66UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI1 (68UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (69UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (70UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (71UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (72UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT0 (73UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT1 (74UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT2 (75UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT3 (76UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT4 (77UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT5 (78UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT6 (79UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT7 (80UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (81UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (82UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (83UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (84UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (85UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (86UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (87UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (88UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (89UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (90UL) +#define SYSCTL_RESOURCE_CLK_TOP_PTPC (91UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (92UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (93UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (94UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (95UL) +#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (96UL) +#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (97UL) +#define SYSCTL_RESOURCE_CLK_TOP_ETH0 (98UL) +#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (99UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (100UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (101UL) +#define SYSCTL_RESOURCE_CLK_TOP_NTM0 (102UL) +#define SYSCTL_RESOURCE_CLK_TOP_SDC0 (103UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (132UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (133UL) +#define SYSCTL_RESOURCE_AHBP (256UL) +#define SYSCTL_RESOURCE_AXIS (257UL) +#define SYSCTL_RESOURCE_AXIC (258UL) +#define SYSCTL_RESOURCE_DRAM (259UL) +#define SYSCTL_RESOURCE_ROM0 (260UL) +#define SYSCTL_RESOURCE_LMM0 (261UL) +#define SYSCTL_RESOURCE_RAM0 (262UL) +#define SYSCTL_RESOURCE_MCT0 (263UL) +#define SYSCTL_RESOURCE_XPI0 (264UL) +#define SYSCTL_RESOURCE_XPI1 (265UL) +#define SYSCTL_RESOURCE_SDP0 (266UL) +#define SYSCTL_RESOURCE_RNG0 (267UL) +#define SYSCTL_RESOURCE_KMAN (268UL) +#define SYSCTL_RESOURCE_DMA0 (269UL) +#define SYSCTL_RESOURCE_DMA1 (270UL) +#define SYSCTL_RESOURCE_FFA0 (271UL) +#define SYSCTL_RESOURCE_GPIO (272UL) +#define SYSCTL_RESOURCE_MBX0 (273UL) +#define SYSCTL_RESOURCE_WDG0 (274UL) +#define SYSCTL_RESOURCE_WDG1 (275UL) +#define SYSCTL_RESOURCE_TSNS (276UL) +#define SYSCTL_RESOURCE_TMR0 (277UL) +#define SYSCTL_RESOURCE_TMR1 (278UL) +#define SYSCTL_RESOURCE_TMR2 (279UL) +#define SYSCTL_RESOURCE_TMR3 (280UL) +#define SYSCTL_RESOURCE_URT0 (281UL) +#define SYSCTL_RESOURCE_URT1 (282UL) +#define SYSCTL_RESOURCE_URT2 (283UL) +#define SYSCTL_RESOURCE_URT3 (284UL) +#define SYSCTL_RESOURCE_URT4 (285UL) +#define SYSCTL_RESOURCE_URT5 (286UL) +#define SYSCTL_RESOURCE_URT6 (287UL) +#define SYSCTL_RESOURCE_URT7 (288UL) +#define SYSCTL_RESOURCE_I2C0 (289UL) +#define SYSCTL_RESOURCE_I2C1 (290UL) +#define SYSCTL_RESOURCE_I2C2 (291UL) +#define SYSCTL_RESOURCE_I2C3 (292UL) +#define SYSCTL_RESOURCE_SPI0 (293UL) +#define SYSCTL_RESOURCE_SPI1 (294UL) +#define SYSCTL_RESOURCE_SPI2 (295UL) +#define SYSCTL_RESOURCE_SPI3 (296UL) +#define SYSCTL_RESOURCE_CAN0 (297UL) +#define SYSCTL_RESOURCE_CAN1 (298UL) +#define SYSCTL_RESOURCE_PTPC (299UL) +#define SYSCTL_RESOURCE_ADC0 (300UL) +#define SYSCTL_RESOURCE_ADC1 (301UL) +#define SYSCTL_RESOURCE_ADC2 (302UL) +#define SYSCTL_RESOURCE_DAC0 (303UL) +#define SYSCTL_RESOURCE_ACMP (304UL) +#define SYSCTL_RESOURCE_I2S0 (305UL) +#define SYSCTL_RESOURCE_I2S1 (306UL) +#define SYSCTL_RESOURCE_PDM0 (307UL) +#define SYSCTL_RESOURCE_DAO (308UL) +#define SYSCTL_RESOURCE_MSYN (309UL) +#define SYSCTL_RESOURCE_MOT0 (310UL) +#define SYSCTL_RESOURCE_MOT1 (311UL) +#define SYSCTL_RESOURCE_ETH0 (312UL) +#define SYSCTL_RESOURCE_NTM0 (313UL) +#define SYSCTL_RESOURCE_SDC0 (314UL) +#define SYSCTL_RESOURCE_USB0 (315UL) +#define SYSCTL_RESOURCE_REF0 (316UL) +#define SYSCTL_RESOURCE_REF1 (317UL) + +/* GROUP0 register group index macro definition */ +#define SYSCTL_GROUP0_LINK0 (0UL) +#define SYSCTL_GROUP0_LINK1 (1UL) + +/* AFFILIATE register group index macro definition */ +#define SYSCTL_AFFILIATE_CPU0 (0UL) + +/* RETENTION register group index macro definition */ +#define SYSCTL_RETENTION_CPU0 (0UL) + +/* POWER register group index macro definition */ +#define SYSCTL_POWER_CPU0 (0UL) + +/* RESET register group index macro definition */ +#define SYSCTL_RESET_SOC (0UL) +#define SYSCTL_RESET_CPU0 (1UL) + +/* CLOCK_CPU register group index macro definition */ +#define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) + +/* CLOCK register group index macro definition */ +#define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) +#define SYSCTL_CLOCK_CLK_TOP_DRAM (1UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI0 (2UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI1 (3UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR0 (4UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR1 (5UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR2 (6UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR3 (7UL) +#define SYSCTL_CLOCK_CLK_TOP_URT0 (8UL) +#define SYSCTL_CLOCK_CLK_TOP_URT1 (9UL) +#define SYSCTL_CLOCK_CLK_TOP_URT2 (10UL) +#define SYSCTL_CLOCK_CLK_TOP_URT3 (11UL) +#define SYSCTL_CLOCK_CLK_TOP_URT4 (12UL) +#define SYSCTL_CLOCK_CLK_TOP_URT5 (13UL) +#define SYSCTL_CLOCK_CLK_TOP_URT6 (14UL) +#define SYSCTL_CLOCK_CLK_TOP_URT7 (15UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C0 (16UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C1 (17UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C2 (18UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C3 (19UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI0 (20UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI1 (21UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI2 (22UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI3 (23UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN0 (24UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN1 (25UL) +#define SYSCTL_CLOCK_CLK_TOP_PTPC (26UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA0 (27UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA1 (28UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA2 (29UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA3 (30UL) +#define SYSCTL_CLOCK_CLK_TOP_AUD0 (31UL) +#define SYSCTL_CLOCK_CLK_TOP_AUD1 (32UL) +#define SYSCTL_CLOCK_CLK_TOP_ETH0 (33UL) +#define SYSCTL_CLOCK_CLK_TOP_PTP0 (34UL) +#define SYSCTL_CLOCK_CLK_TOP_REF0 (35UL) +#define SYSCTL_CLOCK_CLK_TOP_REF1 (36UL) +#define SYSCTL_CLOCK_CLK_TOP_NTM0 (37UL) +#define SYSCTL_CLOCK_CLK_TOP_SDC0 (38UL) + +/* ADCCLK register group index macro definition */ +#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL) + +/* DACCLK register group index macro definition */ +#define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) + +/* I2SCLK register group index macro definition */ +#define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL) +#define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL) + +/* MONITOR register group index macro definition */ +#define SYSCTL_MONITOR_SLICE0 (0UL) +#define SYSCTL_MONITOR_SLICE1 (1UL) +#define SYSCTL_MONITOR_SLICE2 (2UL) +#define SYSCTL_MONITOR_SLICE3 (3UL) + +/* GPR register group index macro definition */ +#define SYSCTL_CPU_GPR_GPR0 (0UL) +#define SYSCTL_CPU_GPR_GPR1 (1UL) +#define SYSCTL_CPU_GPR_GPR2 (2UL) +#define SYSCTL_CPU_GPR_GPR3 (3UL) +#define SYSCTL_CPU_GPR_GPR4 (4UL) +#define SYSCTL_CPU_GPR_GPR5 (5UL) +#define SYSCTL_CPU_GPR_GPR6 (6UL) +#define SYSCTL_CPU_GPR_GPR7 (7UL) +#define SYSCTL_CPU_GPR_GPR8 (8UL) +#define SYSCTL_CPU_GPR_GPR9 (9UL) +#define SYSCTL_CPU_GPR_GPR10 (10UL) +#define SYSCTL_CPU_GPR_GPR11 (11UL) +#define SYSCTL_CPU_GPR_GPR12 (12UL) +#define SYSCTL_CPU_GPR_GPR13 (13UL) + +/* WAKEUP_STATUS register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) + +/* WAKEUP_ENABLE register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) + +/* CPU register group index macro definition */ +#define SYSCTL_CPU_CPU0 (0UL) + + +#endif /* HPM_SYSCTL_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h new file mode 100644 index 0000000000..e34cb1bd5e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGM_H +#define HPM_TRGM_H + +typedef struct { + __RW uint32_t FILTCFG[20]; /* 0x0 - 0x4C: Filter configure register */ + __R uint8_t RESERVED0[176]; /* 0x50 - 0xFF: Reserved */ + __RW uint32_t TRGOCFG[64]; /* 0x100 - 0x1FC: Trigger manager output configure register */ + __RW uint32_t DMACFG[4]; /* 0x200 - 0x20C: DMA request configure register */ + __R uint8_t RESERVED1[496]; /* 0x210 - 0x3FF: Reserved */ + __RW uint32_t GCR; /* 0x400: General Control Register */ +} TRGM_Type; + + +/* Bitfield definition for register array: FILTCFG */ +/* + * OUTINV (RW) + * + * 1- Filter will invert the output + * 0- Filter will not invert the output + */ +#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) +#define TRGM_FILTCFG_OUTINV_SHIFT (16U) +#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) +#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) + +/* + * MODE (RW) + * + * This bitfields defines the filter mode + * 000-bypass; + * 100-rapid change mode; + * 101-delay filter mode; + * 110-stalbe low mode; + * 111-stable high mode + */ +#define TRGM_FILTCFG_MODE_MASK (0xE000U) +#define TRGM_FILTCFG_MODE_SHIFT (13U) +#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) +#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) + +/* + * SYNCEN (RW) + * + * set to enable sychronization input signal with TRGM clock + */ +#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) +#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) +#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) +#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) + +/* + * FILTLEN (RW) + * + * This bitfields defines the filter counter length. + */ +#define TRGM_FILTCFG_FILTLEN_MASK (0xFFFU) +#define TRGM_FILTCFG_FILTLEN_SHIFT (0U) +#define TRGM_FILTCFG_FILTLEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT) & TRGM_FILTCFG_FILTLEN_MASK) +#define TRGM_FILTCFG_FILTLEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT) + +/* Bitfield definition for register array: TRGOCFG */ +/* + * OUTINV (RW) + * + * 1- Invert the output + */ +#define TRGM_TRGOCFG_OUTINV_MASK (0x100U) +#define TRGM_TRGOCFG_OUTINV_SHIFT (8U) +#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) +#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) + +/* + * FEDG2PEN (RW) + * + * 1- The selected input signal falling edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x80U) +#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (7U) +#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) +#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) + +/* + * REDG2PEN (RW) + * + * 1- The selected input signal rising edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_REDG2PEN_MASK (0x40U) +#define TRGM_TRGOCFG_REDG2PEN_SHIFT (6U) +#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) +#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) + +/* + * TRIGOSEL (RW) + * + * This bitfield selects one of the TRGM inputs as output. + */ +#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x3FU) +#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) +#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) +#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) + +/* Bitfield definition for register array: DMACFG */ +/* + * DMASRCSEL (RW) + * + * This field selects one of the DMA requests as the DMA request output. + */ +#define TRGM_DMACFG_DMASRCSEL_MASK (0x1FU) +#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) +#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) +#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) + +/* Bitfield definition for register: GCR */ +/* + * TRGOPEN (RW) + * + * The bitfield enable the TRGM outputs. + */ +#define TRGM_GCR_TRGOPEN_MASK (0xFFFU) +#define TRGM_GCR_TRGOPEN_SHIFT (0U) +#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) +#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) + + + +/* FILTCFG register group index macro definition */ +#define TRGM_FILTCFG_PWM_IN0 (0UL) +#define TRGM_FILTCFG_PWM_IN1 (1UL) +#define TRGM_FILTCFG_PWM_IN2 (2UL) +#define TRGM_FILTCFG_PWM_IN3 (3UL) +#define TRGM_FILTCFG_PWM_IN4 (4UL) +#define TRGM_FILTCFG_PWM_IN5 (5UL) +#define TRGM_FILTCFG_PWM_IN6 (6UL) +#define TRGM_FILTCFG_PWM_IN7 (7UL) +#define TRGM_FILTCFG_TRGM_IN0 (8UL) +#define TRGM_FILTCFG_TRGM_IN1 (9UL) +#define TRGM_FILTCFG_TRGM_IN2 (10UL) +#define TRGM_FILTCFG_TRGM_IN3 (11UL) +#define TRGM_FILTCFG_TRGM_IN4 (12UL) +#define TRGM_FILTCFG_TRGM_IN5 (13UL) +#define TRGM_FILTCFG_TRGM_IN6 (14UL) +#define TRGM_FILTCFG_TRGM_IN7 (15UL) +#define TRGM_FILTCFG_TRGM_IN8 (16UL) +#define TRGM_FILTCFG_TRGM_IN9 (17UL) +#define TRGM_FILTCFG_TRGM_IN10 (18UL) +#define TRGM_FILTCFG_TRGM_IN11 (19UL) + +/* TRGOCFG register group index macro definition */ +#define TRGM_TRGOCFG_TRGM_OUT0 (0UL) +#define TRGM_TRGOCFG_TRGM_OUT1 (1UL) +#define TRGM_TRGOCFG_TRGM_OUT2 (2UL) +#define TRGM_TRGOCFG_TRGM_OUT3 (3UL) +#define TRGM_TRGOCFG_TRGM_OUT4 (4UL) +#define TRGM_TRGOCFG_TRGM_OUT5 (5UL) +#define TRGM_TRGOCFG_TRGM_OUT6 (6UL) +#define TRGM_TRGOCFG_TRGM_OUT7 (7UL) +#define TRGM_TRGOCFG_TRGM_OUT8 (8UL) +#define TRGM_TRGOCFG_TRGM_OUT9 (9UL) +#define TRGM_TRGOCFG_TRGM_OUT10 (10UL) +#define TRGM_TRGOCFG_TRGM_OUT11 (11UL) +#define TRGM_TRGOCFG_TRGM_OUTX0 (12UL) +#define TRGM_TRGOCFG_TRGM_OUTX1 (13UL) +#define TRGM_TRGOCFG_PWM_SYNCI (14UL) +#define TRGM_TRGOCFG_PWM_FRCI (15UL) +#define TRGM_TRGOCFG_PWM_FRCSYNCI (16UL) +#define TRGM_TRGOCFG_PWM_SHRLDSYNCI (17UL) +#define TRGM_TRGOCFG_PWM_FAULTI0 (18UL) +#define TRGM_TRGOCFG_PWM_FAULTI1 (19UL) +#define TRGM_TRGOCFG_PWM_FAULTI2 (20UL) +#define TRGM_TRGOCFG_PWM_FAULTI3 (21UL) +#define TRGM_TRGOCFG_PWM_IN8 (22UL) +#define TRGM_TRGOCFG_PWM_IN9 (23UL) +#define TRGM_TRGOCFG_PWM_IN10 (24UL) +#define TRGM_TRGOCFG_PWM_IN11 (25UL) +#define TRGM_TRGOCFG_PWM_IN12 (26UL) +#define TRGM_TRGOCFG_PWM_IN13 (27UL) +#define TRGM_TRGOCFG_PWM_IN14 (28UL) +#define TRGM_TRGOCFG_PWM_IN15 (29UL) +#define TRGM_TRGOCFG_PWM_IN16 (30UL) +#define TRGM_TRGOCFG_PWM_IN17 (31UL) +#define TRGM_TRGOCFG_PWM_IN18 (32UL) +#define TRGM_TRGOCFG_PWM_IN19 (33UL) +#define TRGM_TRGOCFG_PWM_IN20 (34UL) +#define TRGM_TRGOCFG_PWM_IN21 (35UL) +#define TRGM_TRGOCFG_PWM_IN22 (36UL) +#define TRGM_TRGOCFG_PWM_IN23 (37UL) +#define TRGM_TRGOCFG_QEI_A (38UL) +#define TRGM_TRGOCFG_QEI_B (39UL) +#define TRGM_TRGOCFG_QEI_Z (40UL) +#define TRGM_TRGOCFG_QEI_H (41UL) +#define TRGM_TRGOCFG_QEI_PAUSE (42UL) +#define TRGM_TRGOCFG_QEI_SNAPI (43UL) +#define TRGM_TRGOCFG_HALL_U (44UL) +#define TRGM_TRGOCFG_HALL_V (45UL) +#define TRGM_TRGOCFG_HALL_W (46UL) +#define TRGM_TRGOCFG_HALL_SNAPI (47UL) +#define TRGM_TRGOCFG_ADC0_STRGI (48UL) +#define TRGM_TRGOCFG_ADC1_STRGI (49UL) +#define TRGM_TRGOCFG_ADC2_STRGI (50UL) +#define TRGM_TRGOCFG_ADC3_STRGI (51UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL) +#define TRGM_TRGOCFG_GPTMRA_SYNCI (55UL) +#define TRGM_TRGOCFG_GPTMRA_IN2 (56UL) +#define TRGM_TRGOCFG_GPTMRA_IN3 (57UL) +#define TRGM_TRGOCFG_GPTMRB_SYNCI (58UL) +#define TRGM_TRGOCFG_GPTMRB_IN2 (59UL) +#define TRGM_TRGOCFG_GPTMRB_IN3 (60UL) +#define TRGM_TRGOCFG_CMPX_WIN (61UL) +#define TRGM_TRGOCFG_CAN_PTPC0_CAP (62UL) +#define TRGM_TRGOCFG_CAN_PTPC1_CAP (63UL) + +/* DMACFG register group index macro definition */ +#define TRGM_DMACFG_0 (0UL) +#define TRGM_DMACFG_1 (1UL) +#define TRGM_DMACFG_2 (2UL) +#define TRGM_DMACFG_3 (3UL) + + +#endif /* HPM_TRGM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h new file mode 100644 index 0000000000..8fcaecc9d1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGMMUX_SRC_H +#define HPM_TRGMMUX_SRC_H + +/* trgm0_input mux definitions */ +#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN0 (0x2UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN1 (0x3UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN2 (0x4UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN3 (0x5UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN4 (0x6UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN5 (0x7UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN6 (0x8UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN7 (0x9UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN8 (0xAUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN9 (0xBUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN10 (0xCUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN11 (0xDUL) +#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) +#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH16REF (0x1CUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH17REF (0x1DUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH18REF (0x1EUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH19REF (0x1FUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH20REF (0x20UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH21REF (0x21UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH22REF (0x22UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH23REF (0x23UL) +#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x24UL) +#define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x25UL) +#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x26UL) +#define HPM_TRGM0_INPUT_SRC_NTMR0_CH1_OUT (0x27UL) +#define HPM_TRGM0_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) +#define HPM_TRGM0_INPUT_SRC_NTMR0_CH0_OUT (0x29UL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x2AUL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x2BUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x2CUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x2DUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x2EUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x2FUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x30UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x31UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x32UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) +#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) + +/* trgm1_input mux definitions */ +#define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) +#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH16REF (0x1CUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH17REF (0x1DUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH18REF (0x1EUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH19REF (0x1FUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH20REF (0x20UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH21REF (0x21UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH22REF (0x22UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH23REF (0x23UL) +#define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x24UL) +#define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x25UL) +#define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x26UL) +#define HPM_TRGM1_INPUT_SRC_NTMR0_CH1_OUT (0x27UL) +#define HPM_TRGM1_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) +#define HPM_TRGM1_INPUT_SRC_NTMR0_CH0_OUT (0x29UL) +#define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x2AUL) +#define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x2BUL) +#define HPM_TRGM1_INPUT_SRC_SYNT0_CH0 (0x2CUL) +#define HPM_TRGM1_INPUT_SRC_SYNT0_CH1 (0x2DUL) +#define HPM_TRGM1_INPUT_SRC_SYNT0_CH2 (0x2EUL) +#define HPM_TRGM1_INPUT_SRC_SYNT0_CH3 (0x2FUL) +#define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2 (0x30UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT3 (0x31UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT2 (0x32UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) +#define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) + +/* trgm0_output mux definitions */ +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN16 (0x1EUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN17 (0x1FUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN18 (0x20UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN19 (0x21UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN20 (0x22UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN21 (0x23UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN22 (0x24UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN23 (0x25UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) +#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI_ADCX_PTRGI2A (0x30UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI_ADCX_PTRGI2B (0x31UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI_ADCX_PTRGI2C (0x32UL) +#define HPM_TRGM0_OUTPUT_SRC_DAC_BUFF_TRIGGER (0x33UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x3AUL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x3BUL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x3CUL) +#define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) +#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN0 (0x40UL) +#define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN1 (0x41UL) +#define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN2 (0x42UL) +#define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN3 (0x43UL) + +/* trgm1_output mux definitions */ +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN16 (0x1EUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN17 (0x1FUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN18 (0x20UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN19 (0x21UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN20 (0x22UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN21 (0x23UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN22 (0x24UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN23 (0x25UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) +#define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI_ADCX_PTRGI3A (0x30UL) +#define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI_ADCX_PTRGI3B (0x31UL) +#define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI_ADCX_PTRGI3C (0x32UL) +#define HPM_TRGM1_OUTPUT_SRC_DAC_BUFF_TRIGGER (0x33UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_SYNCI (0x3AUL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN2 (0x3BUL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN3 (0x3CUL) +#define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) +#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN0 (0x40UL) +#define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN1 (0x41UL) +#define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN2 (0x42UL) +#define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN3 (0x43UL) + +/* trgm0_filter mux definitions */ +#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) + +/* trgm1_filter mux definitions */ +#define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) + +/* trgm0_dma mux definitions */ +#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) +#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) +#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) +#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) +#define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) +#define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) + +/* trgm1_dma mux definitions */ +#define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) +#define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) +#define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) +#define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) +#define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) +#define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) + + + +#endif /* HPM_TRGMMUX_SRC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list new file mode 100644 index 0000000000..99fa6f61a8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/soc_modules.list @@ -0,0 +1,36 @@ +# Copyright 2022 hpmicro +# SPDX-License-Identifier: BSD-3-Clause +# +# In this file, all modules available on this part are listed + +CONFIG_HAS_HPMSDK_UART=y +CONFIG_HAS_HPMSDK_DRAM=y +CONFIG_HAS_HPMSDK_SDP=y +CONFIG_HAS_HPMSDK_I2C=y +CONFIG_HAS_HPMSDK_PMP=y +CONFIG_HAS_HPMSDK_RNG=y +CONFIG_HAS_HPMSDK_GPIO=y +CONFIG_HAS_HPMSDK_SPI=y +CONFIG_HAS_HPMSDK_WDG=y +CONFIG_HAS_HPMSDK_DMA=y +CONFIG_HAS_HPMSDK_GPTMR=y +CONFIG_HAS_HPMSDK_PWM=y +CONFIG_HAS_HPMSDK_PLLCTLV2=y +CONFIG_HAS_HPMSDK_USB=y +CONFIG_HAS_HPMSDK_RTC=y +CONFIG_HAS_HPMSDK_ACMP=y +CONFIG_HAS_HPMSDK_I2S=y +CONFIG_HAS_HPMSDK_DAO=y +CONFIG_HAS_HPMSDK_PDM=y +CONFIG_HAS_HPMSDK_VAD=y +CONFIG_HAS_HPMSDK_CAN=y +CONFIG_HAS_HPMSDK_ENET=y +CONFIG_HAS_HPMSDK_SDXC=y +CONFIG_HAS_HPMSDK_ADC16=y +CONFIG_HAS_HPMSDK_PCFG=y +CONFIG_HAS_HPMSDK_PTPC=y +CONFIG_HAS_HPMSDK_MCHTMR=y +CONFIG_HAS_HPMSDK_FFA=y +CONFIG_HAS_HPMSDK_TSNS=y +CONFIG_HAS_HPMSDK_DAC=y + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c new file mode 100644 index 0000000000..d6396d9d6f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/system.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" + +void enable_plic_feature(void) +{ + uint32_t plic_feature = 0; +#ifndef USE_NONVECTOR_MODE + /* enabled vector mode and preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; +#endif +#ifndef DISABLE_IRQ_PREEMPTIVE + /* enabled preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; +#endif + __plic_set_feature(HPM_PLIC_BASE, plic_feature); +} + +__attribute__((weak)) void system_init(void) +{ +#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ +#endif + +#ifdef USE_S_MODE_IRQ + disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#else + disable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + + disable_irq_from_intc(); +#ifdef USE_S_MODE_IRQ + disable_s_irq_from_intc(); +#endif + + enable_plic_feature(); + enable_irq_from_intc(); + +#ifdef USE_S_MODE_IRQ + delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); + enable_s_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#else + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + l1c_dc_invalidate_all(); +#endif +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld new file mode 100644 index 0000000000..1bf808a0e4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld @@ -0,0 +1,180 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (wx) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 256K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .vectors ORIGIN(ILM) : AT(etext) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld new file mode 100644 index 0000000000..ffe3ebf65d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld @@ -0,0 +1,186 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM : ORIGIN = 0x0, LENGTH = 128K + DLM : ORIGIN = 0x80000, LENGTH = 128K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) + SDRAM_NONCACHABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + } > DLM + + __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld new file mode 100644 index 0000000000..314ed67616 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld @@ -0,0 +1,204 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM : ORIGIN = 0, LENGTH = 128K + DLM : ORIGIN = 0x80000, LENGTH = 128K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) + SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld new file mode 100644 index 0000000000..9badc91602 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld @@ -0,0 +1,184 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (wx) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 256K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld new file mode 100644 index 0000000000..1807e0eef0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld @@ -0,0 +1,202 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (wx) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 256K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld new file mode 100644 index 0000000000..5c082c283d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld @@ -0,0 +1,187 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + /* It's alias address of core0 ILM+DLM, but accessing via system bus */ + CORE0_LM_SLV (wx) : ORIGIN = 0x1040000, LENGTH = 256K + + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 256K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + KEEP(*(.isr_s_vector)) + KEEP(*(.vector_s_table)) + . = ALIGN(8); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > AXI_SRAM + + .dual_core_share (NOLOAD) : { + KEEP(*(.dual_core_share)) + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > DLM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + ASSERT(__stack_base__ >= __heap_end__, "stack overlapped with heap") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S new file mode 100644 index 0000000000..71fd2638c2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_csr_regs.h" + + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + + /* reset mstatus to 0*/ + csrrw x0, mstatus, x0 + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_safe + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifndef CONFIG_FREERTOS + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#else + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler +#endif + +#ifndef USE_NONVECTOR_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidentally */ +1: j 1b + + .weak exit +exit: +1: j 1b + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c new file mode 100644 index 0000000000..f25b2e75b9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c @@ -0,0 +1,131 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include "hpm_interrupt.h" + +#ifdef __cplusplus +extern "C" { +#endif +extern void system_init(void); +extern void __libc_init_array(void); +extern void __libc_fini_array(void); +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) void _clean_up(void) +{ + /* clean up plic, it will help while debugging */ + disable_irq_from_intc(); + intc_m_set_threshold(0); + for (uint32_t irq = 0; irq < 128; irq++) { + intc_m_complete_irq(irq); + } + /* clear any bits left in plic enable register */ + for (uint32_t i = 0; i < 4; i++) { + *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; + } +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#if defined(FLASH_XIP) || defined(FLASH_UF2) + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while (1) { + ; + } +} + +__attribute__((weak)) void reset_handler(void) +{ + l1c_dc_disable(); + l1c_dc_invalidate_all(); +#if !defined(__SEGGER_RTL_VERSION) || defined(__GNU_LINKER) + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); +#endif + + /* Call platform specific hardware initialization */ + system_init(); + +#ifdef __cplusplus + /* Do global constructors */ + __libc_init_array(); +#endif + + /* Entry function */ + main(); +} + +/* + * When compiling C++ code with static objects, the compiler inserts + * a call to __cxa_atexit() with __dso_handle as one of the arguments. + * The dummy versions of these symbols should be provided. + */ +void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +{ +} + +#ifndef __SEGGER_RTL_VERSION +void* __dso_handle = (void *) &__dso_handle; +#endif + +__attribute__((weak)) void _init(void) +{ +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf new file mode 100644 index 0000000000..1e87e297e2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf @@ -0,0 +1,89 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ +define region ILM = [from 0x0 size 128k]; /* ILM */ +define region DLM = [from 0x80000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 256k]; +define region SDRAM = [from 0x40000000 size _extram_size]; +define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM_SLV with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack }; // Stack reserved block at the end +place at end of DLM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf new file mode 100644 index 0000000000..75b1221ad9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf @@ -0,0 +1,85 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH ]; +define region AXI_SRAM = [from 0x1040000 size 768K]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order {symbol _start}; +keep { section .uf2_signature }; + +place at start of AXI_SRAM with fixed order { block vectors, block vectors_s }; +initialize by copy { block vectors, block vectors_s }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in SDRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SDRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf new file mode 100644 index 0000000000..3f5bc4fb56 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf @@ -0,0 +1,98 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM = [from 0x0 size 256K]; +define region DLM = [from 0x80000 size 256K]; +define region AXI_SRAM = [from 0x1080000 size 512K]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM with fixed order { block vectors, block vectors_s }; +initialize by copy { block vectors, block vectors_s }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in AXI_SRAM with auto order { block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in SDRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SDRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack, block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf new file mode 100644 index 0000000000..87188c823c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf @@ -0,0 +1,87 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM = [from 0 size 128k]; /* ILM slave */ +define region DLM = [from 0x80000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order {symbol _start}; +keep { section .uf2_signature }; + +place at start of ILM with fixed order { block vectors, block vectors_s }; +initialize by copy { block vectors, block vectors_s }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf new file mode 100644 index 0000000000..eee3e8a6c2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf @@ -0,0 +1,98 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM = [from 0 size 128k]; /* ILM */ +define region DLM = [from 0x80000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x10C0000 size 256k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM with fixed order { block vectors, block vectors_s }; +initialize by copy { block vectors, block vectors_s }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section + +place in DLM with auto order { block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of DLM { block stack, block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf new file mode 100644 index 0000000000..94e0dae066 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf @@ -0,0 +1,78 @@ +/* + * Copyright 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0 size 128k]; /* ILM */ +define region RAM = [from 0x80000 size 128k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 256k]; +define region NONCACHEABLE_RAM = [from 0x10C0000 size 256K]; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack = end of block stack + 1; +define block safe_stack with size = 512, readwrite access {}; +define exported symbol _stack_safe = end of block safe_stack + 1; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block framebuffer { section .framebuffer }; + + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of ILM { symbol _start }; +place in ILM { block vectors, block vectors_s }; // Vector table section +place in ILM with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +/* Explicit placement in AXI_SRAM */ +place in AXI_SRAM { block framebuffer }; + +place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in RAM { block heap }; // Heap reserved block +place at end of RAM { block stack, block safe_stack }; // Stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s new file mode 100644 index 0000000000..d5607703d5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s @@ -0,0 +1,383 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_RISCV_crt0.s +Purpose : Generic runtime init startup code for RISC-V CPUs. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then + calls SEGGER_SEMIHOST_Exit(). + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and + halts in a loop. +*/ + +#include "hpm_csr_regs.h" + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT reset_handler +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ +// +// Declare a label as function symbol (without switching sections) +// +.macro MARK_FUNC Name + .global \Name + .type \Name, function +\Name: +.endm + +// +// Declare a regular function. +// Functions from the startup are placed in the init section. +// +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Declare a weak function +// +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .global \Name + .weak \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Mark the end of a function and calculate its size +// +.macro END_FUNC name + .size \name,.-\name +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized +* - by hardware (such as on Cortex-M), +* - by the device-specific reset handler, +* - or by the debugger (such as for RAM Code). +*/ +#undef L +#define L(label) .L_start_##label + +START_FUNC _start + .option push + .option norelax + lui gp, %hi(__global_pointer$) + addi gp, gp, %lo(__global_pointer$) + lui tp, %hi(__thread_pointer$) + addi tp, tp, %lo(__thread_pointer$) + .option pop + + csrw mstatus, zero + csrw mcause, zero + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_safe + mv sp, t0 + call _init_ext_ram +#endif + + lui t0, %hi(__stack_end__) + addi sp, t0, %lo(__stack_end__) + +#ifndef __NO_SYSTEM_INIT + // + // Call _init + // + call _init +#endif + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table +L(RunInit): + lw a0, (s0) // Get next initialization function from table + add s0, s0, 4 // Increment table pointer to point to function arguments + jalr a0 // Call initialization function + j L(RunInit) + // +MARK_FUNC __SEGGER_init_done + // + // Time to call main(), the application entry point. + // + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifndef CONFIG_FREERTOS + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#else + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler +#endif + +#if !defined(USE_NONVECTOR_MODE) + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + +MARK_FUNC start +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init a0 and a1. + // + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + // + // end of _start + // Fall-through to exit if main ever returns. + // +MARK_FUNC exit + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + j . + .size exit,.-exit +#else + // + // In a hosted environment, + // we need to load a0 and a1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args + + call APP_ENTRY_POINT // Call to application entry point (usually main()) + call exit // Call exit function + j . // If we unexpectedly return from exit, hang. +END_FUNC _start +#endif + +#ifdef FULL_LIBRARY + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args +#else + li a0, 0 + li a1, 0 +#endif + + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + + // +#ifdef FULL_LIBRARY +/********************************************************************* +* +* exit +* +* Function description +* Exit of the system. +* Called on return from application entry point or explicit call +* to exit. +* +* Additional information +* In a hosted environment exit gracefully, by +* saving the return value, +* calling destructurs of global objects, +* calling registered atexit functions, +* and notifying the host/debugger. +*/ +#undef L +#define L(label) .L_exit_##label + +WEAK_FUNC exit + mv s1, a0 // Save the exit parameter/return result + // + // Call destructors + // + la s0, __dtors_start__ +L(Loop): + la t0, __dtors_end__ + beq s0, t0, L(End) + lw t1, 0(s0) + addi s0, s0, 4 + jalr t1 + j L(Loop) +L(End): + // + // Call atexit functions + // + call _execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mv a0, s1 + call debug_exit + // + // If execution is not terminated, loop forever + // +L(ExitLoop): + j L(ExitLoop) // Loop forever. +END_FUNC exit +#endif + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE + .size args, .-args + .type args, %object +#endif + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" + +/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c new file mode 100644 index 0000000000..7e26b87c93 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" + +/********************** MCAUSE exception types **************************************/ +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ +#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ +#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ +#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ +#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ +#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ +#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ +#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +__attribute__((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void swi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) +{ +} + +__attribute__((weak)) long exception_handler(long cause, long epc) +{ + switch (cause) { + case MCAUSE_INSTR_ADDR_MISALIGNED: + break; + case MCAUSE_INSTR_ACCESS_FAULT: + break; + case MCAUSE_ILLEGAL_INSTR: + break; + case MCAUSE_BREAKPOINT: + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + break; + case MCAUSE_LOAD_ACCESS_FAULT: + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + break; + case MCAUSE_ECALL_FROM_USER_MODE: + break; + case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: + break; + case MCAUSE_ECALL_FROM_MACHINE_MODE: + break; + case MCAUSE_INSTR_PAGE_FAULT: + break; + case MCAUSE_LOAD_PAGE_FAULT: + break; + case MCAUSE_STORE_AMO_PAGE_FAULT: + break; + default: + break; + } + /* Unhandled Trap */ + return epc; +} + +__attribute__((weak)) long exception_s_handler(long cause, long epc) +{ + return epc; +} + +__attribute__((weak)) void swi_s_isr(void) +{ +} + +__attribute__((weak)) void mchtmr_s_isr(void) +{ +} + +#ifndef CONFIG_FREERTOS +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#else +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); +#endif +void irq_handler_trap(void) +{ + long mcause = read_csr(CSR_MCAUSE); + long mepc = read_csr(CSR_MEPC); + long mstatus = read_csr(CSR_MSTATUS); +#if SUPPORT_PFT_ARCH + long mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { + /* Machine timer interrupt */ + mchtmr_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + if (irq_index) { + /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ +#ifndef DISABLE_IRQ_PREEMPTIVE + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + ((isr_func_t)__vector_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + } +#endif + + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { + /* Machine SWI interrupt */ + swi_isr(); + intc_m_complete_swi(); + } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + mepc += 4; + } else { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +#ifndef CONFIG_FREERTOS +void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"), interrupt("supervisor"), aligned(4))); +#else +void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); +#endif +void irq_handler_s_trap(void) +{ + long scause = read_csr(CSR_SCAUSE); + long sepc = read_csr(CSR_SEPC); + long sstatus = read_csr(CSR_SSTATUS); + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_TIMER)) { + /* Machine timer interrupt */ + mchtmr_s_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); +#ifndef DISABLE_IRQ_PREEMPTIVE + enable_s_global_irq(CSR_SSTATUS_SIE_MASK); +#endif + ((isr_func_t)__vector_s_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE, irq_index); + + } +#endif + + else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_SOFT)) { + /* Machine SWI interrupt */ + intc_m_claim_swi(); + swi_s_isr(); + intc_s_complete_swi(); + } else if (!(scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_SUPERVISOR_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + sepc += 4; + } else { + sepc = exception_s_handler(scause, sepc); + } + + /* Restore CSR */ + write_csr(CSR_SSTATUS, sstatus); + write_csr(CSR_SEPC, sepc); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h new file mode 100644 index 0000000000..ebfb6b9596 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +.global default_irq_handler +.weak default_irq_handler +.align 2 +default_irq_handler: +1: j 1b + +.macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq +.endm + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* ADC0 IRQ handler */ + IRQ_HANDLER 9 /* ADC1 IRQ handler */ + IRQ_HANDLER 10 /* ADC2 IRQ handler */ + IRQ_HANDLER 11 /* DAC IRQ handler */ + IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 14 /* SPI0 IRQ handler */ + IRQ_HANDLER 15 /* SPI1 IRQ handler */ + IRQ_HANDLER 16 /* SPI2 IRQ handler */ + IRQ_HANDLER 17 /* SPI3 IRQ handler */ + IRQ_HANDLER 18 /* UART0 IRQ handler */ + IRQ_HANDLER 19 /* UART1 IRQ handler */ + IRQ_HANDLER 20 /* UART2 IRQ handler */ + IRQ_HANDLER 21 /* UART3 IRQ handler */ + IRQ_HANDLER 22 /* UART4 IRQ handler */ + IRQ_HANDLER 23 /* UART5 IRQ handler */ + IRQ_HANDLER 24 /* UART6 IRQ handler */ + IRQ_HANDLER 25 /* UART7 IRQ handler */ + IRQ_HANDLER 26 /* CAN0 IRQ handler */ + IRQ_HANDLER 27 /* CAN1 IRQ handler */ + IRQ_HANDLER 28 /* PTPC IRQ handler */ + IRQ_HANDLER 29 /* WDG0 IRQ handler */ + IRQ_HANDLER 30 /* WDG1 IRQ handler */ + IRQ_HANDLER 31 /* TSNS IRQ handler */ + IRQ_HANDLER 32 /* MBX0A IRQ handler */ + IRQ_HANDLER 33 /* MBX0B IRQ handler */ + IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 38 /* I2C0 IRQ handler */ + IRQ_HANDLER 39 /* I2C1 IRQ handler */ + IRQ_HANDLER 40 /* I2C2 IRQ handler */ + IRQ_HANDLER 41 /* I2C3 IRQ handler */ + IRQ_HANDLER 42 /* PWM0 IRQ handler */ + IRQ_HANDLER 43 /* HALL0 IRQ handler */ + IRQ_HANDLER 44 /* QEI0 IRQ handler */ + IRQ_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_HANDLER 46 /* HALL1 IRQ handler */ + IRQ_HANDLER 47 /* QEI1 IRQ handler */ + IRQ_HANDLER 48 /* SDP IRQ handler */ + IRQ_HANDLER 49 /* XPI0 IRQ handler */ + IRQ_HANDLER 50 /* XPI1 IRQ handler */ + IRQ_HANDLER 51 /* XDMA IRQ handler */ + IRQ_HANDLER 52 /* HDMA IRQ handler */ + IRQ_HANDLER 53 /* DRAM IRQ handler */ + IRQ_HANDLER 54 /* RNG IRQ handler */ + IRQ_HANDLER 55 /* I2S0 IRQ handler */ + IRQ_HANDLER 56 /* I2S1 IRQ handler */ + IRQ_HANDLER 57 /* DAO IRQ handler */ + IRQ_HANDLER 58 /* PDM IRQ handler */ + IRQ_HANDLER 59 /* FFA IRQ handler */ + IRQ_HANDLER 60 /* NTMR0 IRQ handler */ + IRQ_HANDLER 61 /* USB0 IRQ handler */ + IRQ_HANDLER 62 /* ENET0 IRQ handler */ + IRQ_HANDLER 63 /* SDXC0 IRQ handler */ + IRQ_HANDLER 64 /* PSEC IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PWDG IRQ handler */ + IRQ_HANDLER 67 /* PTMR IRQ handler */ + IRQ_HANDLER 68 /* PUART IRQ handler */ + IRQ_HANDLER 69 /* FUSE IRQ handler */ + IRQ_HANDLER 70 /* SECMON IRQ handler */ + IRQ_HANDLER 71 /* RTC IRQ handler */ + IRQ_HANDLER 72 /* BUTN IRQ handler */ + IRQ_HANDLER 73 /* BGPIO IRQ handler */ + IRQ_HANDLER 74 /* BVIO IRQ handler */ + IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ + + +.global default_irq_s_handler +.weak default_irq_s_handler +.align 2 +default_irq_s_handler: +1: j 1b + +.macro IRQ_S_HANDLER irq + .weak default_isr_s_\irq + .set default_isr_s_\irq, default_irq_s_handler + .long default_isr_s_\irq +.endm + +.section .vector_s_table, "a" +.global __vector_s_table +.align 9 + +__vector_s_table: + .weak default_isr_s_trap + .set default_isr_s_trap, irq_handler_s_trap + .long default_isr_s_trap + IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_S_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_S_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_S_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_S_HANDLER 8 /* ADC0 IRQ handler */ + IRQ_S_HANDLER 9 /* ADC1 IRQ handler */ + IRQ_S_HANDLER 10 /* ADC2 IRQ handler */ + IRQ_S_HANDLER 11 /* DAC IRQ handler */ + IRQ_S_HANDLER 12 /* ACMP[0] IRQ handler */ + IRQ_S_HANDLER 13 /* ACMP[1] IRQ handler */ + IRQ_S_HANDLER 14 /* SPI0 IRQ handler */ + IRQ_S_HANDLER 15 /* SPI1 IRQ handler */ + IRQ_S_HANDLER 16 /* SPI2 IRQ handler */ + IRQ_S_HANDLER 17 /* SPI3 IRQ handler */ + IRQ_S_HANDLER 18 /* UART0 IRQ handler */ + IRQ_S_HANDLER 19 /* UART1 IRQ handler */ + IRQ_S_HANDLER 20 /* UART2 IRQ handler */ + IRQ_S_HANDLER 21 /* UART3 IRQ handler */ + IRQ_S_HANDLER 22 /* UART4 IRQ handler */ + IRQ_S_HANDLER 23 /* UART5 IRQ handler */ + IRQ_S_HANDLER 24 /* UART6 IRQ handler */ + IRQ_S_HANDLER 25 /* UART7 IRQ handler */ + IRQ_S_HANDLER 26 /* CAN0 IRQ handler */ + IRQ_S_HANDLER 27 /* CAN1 IRQ handler */ + IRQ_S_HANDLER 28 /* PTPC IRQ handler */ + IRQ_S_HANDLER 29 /* WDG0 IRQ handler */ + IRQ_S_HANDLER 30 /* WDG1 IRQ handler */ + IRQ_S_HANDLER 31 /* TSNS IRQ handler */ + IRQ_S_HANDLER 32 /* MBX0A IRQ handler */ + IRQ_S_HANDLER 33 /* MBX0B IRQ handler */ + IRQ_S_HANDLER 34 /* GPTMR0 IRQ handler */ + IRQ_S_HANDLER 35 /* GPTMR1 IRQ handler */ + IRQ_S_HANDLER 36 /* GPTMR2 IRQ handler */ + IRQ_S_HANDLER 37 /* GPTMR3 IRQ handler */ + IRQ_S_HANDLER 38 /* I2C0 IRQ handler */ + IRQ_S_HANDLER 39 /* I2C1 IRQ handler */ + IRQ_S_HANDLER 40 /* I2C2 IRQ handler */ + IRQ_S_HANDLER 41 /* I2C3 IRQ handler */ + IRQ_S_HANDLER 42 /* PWM0 IRQ handler */ + IRQ_S_HANDLER 43 /* HALL0 IRQ handler */ + IRQ_S_HANDLER 44 /* QEI0 IRQ handler */ + IRQ_S_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_S_HANDLER 46 /* HALL1 IRQ handler */ + IRQ_S_HANDLER 47 /* QEI1 IRQ handler */ + IRQ_S_HANDLER 48 /* SDP IRQ handler */ + IRQ_S_HANDLER 49 /* XPI0 IRQ handler */ + IRQ_S_HANDLER 50 /* XPI1 IRQ handler */ + IRQ_S_HANDLER 51 /* XDMA IRQ handler */ + IRQ_S_HANDLER 52 /* HDMA IRQ handler */ + IRQ_S_HANDLER 53 /* DRAM IRQ handler */ + IRQ_S_HANDLER 54 /* RNG IRQ handler */ + IRQ_S_HANDLER 55 /* I2S0 IRQ handler */ + IRQ_S_HANDLER 56 /* I2S1 IRQ handler */ + IRQ_S_HANDLER 57 /* DAO IRQ handler */ + IRQ_S_HANDLER 58 /* PDM IRQ handler */ + IRQ_S_HANDLER 59 /* FFA IRQ handler */ + IRQ_S_HANDLER 60 /* NTMR0 IRQ handler */ + IRQ_S_HANDLER 61 /* USB0 IRQ handler */ + IRQ_S_HANDLER 62 /* ENET0 IRQ handler */ + IRQ_S_HANDLER 63 /* SDXC0 IRQ handler */ + IRQ_S_HANDLER 64 /* PSEC IRQ handler */ + IRQ_S_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_S_HANDLER 66 /* PWDG IRQ handler */ + IRQ_S_HANDLER 67 /* PTMR IRQ handler */ + IRQ_S_HANDLER 68 /* PUART IRQ handler */ + IRQ_S_HANDLER 69 /* FUSE IRQ handler */ + IRQ_S_HANDLER 70 /* SECMON IRQ handler */ + IRQ_S_HANDLER 71 /* RTC IRQ handler */ + IRQ_S_HANDLER 72 /* BUTN IRQ handler */ + IRQ_S_HANDLER 73 /* BGPIO IRQ handler */ + IRQ_S_HANDLER 74 /* BVIO IRQ handler */ + IRQ_S_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_S_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_S_HANDLER 77 /* DEBUG[0] IRQ handler */ + IRQ_S_HANDLER 78 /* DEBUG[1] IRQ handler */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml new file mode 100644 index 0000000000..e6b4f7cb4d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml @@ -0,0 +1,133497 @@ + + + HPMICRO + HPM6750 + HPM6700/HPM6400 + 1.0 + HPM6700/HPM6400 device + + /* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + 8 + 32 + + 32 + 0x0 + 0xFFFFFFFF + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x800 + registers + + + + DI_GPIOA_VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOA_SET + GPIO input set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOA_CLEAR + GPIO input clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOA_TOGGLE + GPIO input toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_VALUE + GPIOB input + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_SET + GPIO input set + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_CLEAR + GPIO input clear + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_TOGGLE + GPIO input toggle + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_VALUE + GPIOC input + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_SET + GPIO input set + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_CLEAR + GPIO input clear + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_TOGGLE + GPIO input toggle + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOD_VALUE + GPIOD input + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOD_SET + GPIO input set + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOD_CLEAR + GPIO input clear + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOD_TOGGLE + GPIO input toggle + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOE_VALUE + GPIOE input + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOE_SET + GPIO input set + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOE_CLEAR + GPIO input clear + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOE_TOGGLE + GPIO input toggle + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOF_VALUE + GPIOF input + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOF_SET + GPIO input set + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOF_CLEAR + GPIO input clear + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOF_TOGGLE + GPIO input toggle + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_VALUE + GPIOX input + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_SET + GPIO input set + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_CLEAR + GPIO input clear + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_TOGGLE + GPIO input toggle + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_VALUE + GPIOY input + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_SET + GPIO input set + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_CLEAR + GPIO input clear + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_TOGGLE + GPIO input toggle + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_VALUE + GPIOZ input + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_SET + GPIO input set + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_CLEAR + GPIO input clear + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_TOGGLE + GPIO input toggle + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DO_GPIOA_VALUE + GPIO output value + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOA_SET + GPIO output set + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOA_CLEAR + GPIO output clear + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOA_TOGGLE + GPIO output toggle + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_VALUE + GPIOB output + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_SET + GPIO output set + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_CLEAR + GPIO output clear + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_TOGGLE + GPIO output toggle + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_VALUE + GPIOC output + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_SET + GPIO output set + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_CLEAR + GPIO output clear + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_TOGGLE + GPIO output toggle + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOD_VALUE + GPIOD output + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOD_SET + GPIO output set + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOD_CLEAR + GPIO output clear + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOD_TOGGLE + GPIO output toggle + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOE_VALUE + GPIOE output + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOE_SET + GPIO output set + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOE_CLEAR + GPIO output clear + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOE_TOGGLE + GPIO output toggle + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOF_VALUE + GPIOF output + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOF_SET + GPIO output set + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOF_CLEAR + GPIO output clear + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOF_TOGGLE + GPIO output toggle + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_VALUE + GPIOX output + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_SET + GPIO output set + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_CLEAR + GPIO output clear + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_TOGGLE + GPIO output toggle + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_VALUE + GPIOY output + 0x1e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_SET + GPIO output set + 0x1e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_CLEAR + GPIO output clear + 0x1e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_TOGGLE + GPIO output toggle + 0x1ec + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_VALUE + GPIOZ output + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_SET + GPIO output set + 0x1f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_CLEAR + GPIO output clear + 0x1f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_TOGGLE + GPIO output toggle + 0x1fc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + OE_GPIOA_VALUE + GPIO direction value + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOA_SET + GPIO direction set + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOA_CLEAR + GPIO direction clear + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOA_TOGGLE + GPIO direction toggle + 0x20c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_VALUE + GPIOB direction + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_SET + GPIO direction set + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_CLEAR + GPIO direction clear + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_TOGGLE + GPIO direction toggle + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_VALUE + GPIOC direction + 0x220 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_SET + GPIO direction set + 0x224 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_CLEAR + GPIO direction clear + 0x228 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_TOGGLE + GPIO direction toggle + 0x22c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOD_VALUE + GPIOD direction + 0x230 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOD_SET + GPIO direction set + 0x234 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOD_CLEAR + GPIO direction clear + 0x238 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOD_TOGGLE + GPIO direction toggle + 0x23c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOE_VALUE + GPIOE direction + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOE_SET + GPIO direction set + 0x244 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOE_CLEAR + GPIO direction clear + 0x248 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOE_TOGGLE + GPIO direction toggle + 0x24c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOF_VALUE + GPIOF direction + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOF_SET + GPIO direction set + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOF_CLEAR + GPIO direction clear + 0x258 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOF_TOGGLE + GPIO direction toggle + 0x25c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_VALUE + GPIOX direction + 0x2d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_SET + GPIO direction set + 0x2d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_CLEAR + GPIO direction clear + 0x2d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_TOGGLE + GPIO direction toggle + 0x2dc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_VALUE + GPIOY direction + 0x2e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_SET + GPIO direction set + 0x2e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_CLEAR + GPIO direction clear + 0x2e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_TOGGLE + GPIO direction toggle + 0x2ec + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_VALUE + GPIOZ direction + 0x2f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_SET + GPIO direction set + 0x2f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_CLEAR + GPIO direction clear + 0x2f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_TOGGLE + GPIO direction toggle + 0x2fc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + IF_GPIOA_VALUE + GPIO interrupt flag value + 0x300 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOA_SET + GPIO interrupt flag set + 0x304 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOA_CLEAR + GPIO interrupt flag clear + 0x308 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOA_TOGGLE + GPIO interrupt flag toggle + 0x30c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_VALUE + GPIOB interrupt flag + 0x310 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_SET + GPIO interrupt flag set + 0x314 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_CLEAR + GPIO interrupt flag clear + 0x318 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_TOGGLE + GPIO interrupt flag toggle + 0x31c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_VALUE + GPIOC interrupt flag + 0x320 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_SET + GPIO interrupt flag set + 0x324 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_CLEAR + GPIO interrupt flag clear + 0x328 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_TOGGLE + GPIO interrupt flag toggle + 0x32c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOD_VALUE + GPIOD interrupt flag + 0x330 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOD_SET + GPIO interrupt flag set + 0x334 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOD_CLEAR + GPIO interrupt flag clear + 0x338 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOD_TOGGLE + GPIO interrupt flag toggle + 0x33c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOE_VALUE + GPIOE interrupt flag + 0x340 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOE_SET + GPIO interrupt flag set + 0x344 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOE_CLEAR + GPIO interrupt flag clear + 0x348 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOE_TOGGLE + GPIO interrupt flag toggle + 0x34c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOF_VALUE + GPIOF interrupt flag + 0x350 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOF_SET + GPIO interrupt flag set + 0x354 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOF_CLEAR + GPIO interrupt flag clear + 0x358 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOF_TOGGLE + GPIO interrupt flag toggle + 0x35c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_VALUE + GPIOX interrupt flag + 0x3d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_SET + GPIO interrupt flag set + 0x3d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_CLEAR + GPIO interrupt flag clear + 0x3d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_TOGGLE + GPIO interrupt flag toggle + 0x3dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_VALUE + GPIOY interrupt flag + 0x3e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_SET + GPIO interrupt flag set + 0x3e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_CLEAR + GPIO interrupt flag clear + 0x3e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_TOGGLE + GPIO interrupt flag toggle + 0x3ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_VALUE + GPIOZ interrupt flag + 0x3f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_SET + GPIO interrupt flag set + 0x3f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_CLEAR + GPIO interrupt flag clear + 0x3f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_TOGGLE + GPIO interrupt flag toggle + 0x3fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IE_GPIOA_VALUE + GPIO interrupt enable value + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOA_SET + GPIO interrupt enable set + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOA_CLEAR + GPIO interrupt enable clear + 0x408 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOA_TOGGLE + GPIO interrupt enable toggle + 0x40c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_VALUE + GPIOB interrupt enable + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_SET + GPIO interrupt enable set + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_CLEAR + GPIO interrupt enable clear + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_TOGGLE + GPIO interrupt enable toggle + 0x41c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_VALUE + GPIOC interrupt enable + 0x420 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_SET + GPIO interrupt enable set + 0x424 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_CLEAR + GPIO interrupt enable clear + 0x428 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_TOGGLE + GPIO interrupt enable toggle + 0x42c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOD_VALUE + GPIOD interrupt enable + 0x430 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOD_SET + GPIO interrupt enable set + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOD_CLEAR + GPIO interrupt enable clear + 0x438 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOD_TOGGLE + GPIO interrupt enable toggle + 0x43c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOE_VALUE + GPIOE interrupt enable + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOE_SET + GPIO interrupt enable set + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOE_CLEAR + GPIO interrupt enable clear + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOE_TOGGLE + GPIO interrupt enable toggle + 0x44c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOF_VALUE + GPIOF interrupt enable + 0x450 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOF_SET + GPIO interrupt enable set + 0x454 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOF_CLEAR + GPIO interrupt enable clear + 0x458 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOF_TOGGLE + GPIO interrupt enable toggle + 0x45c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_VALUE + GPIOX interrupt enable + 0x4d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_SET + GPIO interrupt enable set + 0x4d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_CLEAR + GPIO interrupt enable clear + 0x4d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_TOGGLE + GPIO interrupt enable toggle + 0x4dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_VALUE + GPIOY interrupt enable + 0x4e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_SET + GPIO interrupt enable set + 0x4e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_CLEAR + GPIO interrupt enable clear + 0x4e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_TOGGLE + GPIO interrupt enable toggle + 0x4ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_VALUE + GPIOZ interrupt enable + 0x4f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_SET + GPIO interrupt enable set + 0x4f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_CLEAR + GPIO interrupt enable clear + 0x4f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_TOGGLE + GPIO interrupt enable toggle + 0x4fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + PL_GPIOA_VALUE + GPIO interrupt polarity value + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOA_SET + GPIO interrupt polarity set + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOA_CLEAR + GPIO interrupt polarity clear + 0x508 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOA_TOGGLE + GPIO interrupt polarity toggle + 0x50c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_VALUE + GPIOB interrupt polarity + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_SET + GPIO interrupt polarity set + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_CLEAR + GPIO interrupt polarity clear + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_TOGGLE + GPIO interrupt polarity toggle + 0x51c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_VALUE + GPIOC interrupt polarity + 0x520 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_SET + GPIO interrupt polarity set + 0x524 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_CLEAR + GPIO interrupt polarity clear + 0x528 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_TOGGLE + GPIO interrupt polarity toggle + 0x52c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOD_VALUE + GPIOD interrupt polarity + 0x530 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOD_SET + GPIO interrupt polarity set + 0x534 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOD_CLEAR + GPIO interrupt polarity clear + 0x538 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOD_TOGGLE + GPIO interrupt polarity toggle + 0x53c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOE_VALUE + GPIOE interrupt polarity + 0x540 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOE_SET + GPIO interrupt polarity set + 0x544 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOE_CLEAR + GPIO interrupt polarity clear + 0x548 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOE_TOGGLE + GPIO interrupt polarity toggle + 0x54c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOF_VALUE + GPIOF interrupt polarity + 0x550 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOF_SET + GPIO interrupt polarity set + 0x554 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOF_CLEAR + GPIO interrupt polarity clear + 0x558 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOF_TOGGLE + GPIO interrupt polarity toggle + 0x55c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_VALUE + GPIOX interrupt polarity + 0x5d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_SET + GPIO interrupt polarity set + 0x5d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_CLEAR + GPIO interrupt polarity clear + 0x5d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_TOGGLE + GPIO interrupt polarity toggle + 0x5dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_VALUE + GPIOY interrupt polarity + 0x5e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_SET + GPIO interrupt polarity set + 0x5e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_CLEAR + GPIO interrupt polarity clear + 0x5e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_TOGGLE + GPIO interrupt polarity toggle + 0x5ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_VALUE + GPIOZ interrupt polarity + 0x5f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_SET + GPIO interrupt polarity set + 0x5f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_CLEAR + GPIO interrupt polarity clear + 0x5f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_TOGGLE + GPIO interrupt polarity toggle + 0x5fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TP_GPIOA_VALUE + GPIO interrupt type value + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOA_SET + GPIO interrupt type set + 0x604 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOA_CLEAR + GPIO interrupt type clear + 0x608 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOA_TOGGLE + GPIO interrupt type toggle + 0x60c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_VALUE + GPIOB interrupt type + 0x610 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_SET + GPIO interrupt type set + 0x614 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_CLEAR + GPIO interrupt type clear + 0x618 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_TOGGLE + GPIO interrupt type toggle + 0x61c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_VALUE + GPIOC interrupt type + 0x620 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_SET + GPIO interrupt type set + 0x624 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_CLEAR + GPIO interrupt type clear + 0x628 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_TOGGLE + GPIO interrupt type toggle + 0x62c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOD_VALUE + GPIOD interrupt type + 0x630 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOD_SET + GPIO interrupt type set + 0x634 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOD_CLEAR + GPIO interrupt type clear + 0x638 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOD_TOGGLE + GPIO interrupt type toggle + 0x63c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOE_VALUE + GPIOE interrupt type + 0x640 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOE_SET + GPIO interrupt type set + 0x644 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOE_CLEAR + GPIO interrupt type clear + 0x648 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOE_TOGGLE + GPIO interrupt type toggle + 0x64c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOF_VALUE + GPIOF interrupt type + 0x650 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOF_SET + GPIO interrupt type set + 0x654 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOF_CLEAR + GPIO interrupt type clear + 0x658 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOF_TOGGLE + GPIO interrupt type toggle + 0x65c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_VALUE + GPIOX interrupt type + 0x6d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_SET + GPIO interrupt type set + 0x6d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_CLEAR + GPIO interrupt type clear + 0x6d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_TOGGLE + GPIO interrupt type toggle + 0x6dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_VALUE + GPIOY interrupt type + 0x6e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_SET + GPIO interrupt type set + 0x6e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_CLEAR + GPIO interrupt type clear + 0x6e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_TOGGLE + GPIO interrupt type toggle + 0x6ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_VALUE + GPIOZ interrupt type + 0x6f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_SET + GPIO interrupt type set + 0x6f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_CLEAR + GPIO interrupt type clear + 0x6f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_TOGGLE + GPIO interrupt type toggle + 0x6fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + AS_GPIOA_VALUE + GPIO interrupt asynchronous value + 0x700 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOA_SET + GPIO interrupt asynchronous set + 0x704 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOA_CLEAR + GPIO interrupt asynchronous clear + 0x708 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOA_TOGGLE + GPIO interrupt asynchronous toggle + 0x70c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_VALUE + GPIOB interrupt asynchronous + 0x710 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_SET + GPIO interrupt asynchronous set + 0x714 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_CLEAR + GPIO interrupt asynchronous clear + 0x718 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_TOGGLE + GPIO interrupt asynchronous toggle + 0x71c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_VALUE + GPIOC interrupt asynchronous + 0x720 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_SET + GPIO interrupt asynchronous set + 0x724 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_CLEAR + GPIO interrupt asynchronous clear + 0x728 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_TOGGLE + GPIO interrupt asynchronous toggle + 0x72c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOD_VALUE + GPIOD interrupt asynchronous + 0x730 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOD_SET + GPIO interrupt asynchronous set + 0x734 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOD_CLEAR + GPIO interrupt asynchronous clear + 0x738 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOD_TOGGLE + GPIO interrupt asynchronous toggle + 0x73c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOE_VALUE + GPIOE interrupt asynchronous + 0x740 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOE_SET + GPIO interrupt asynchronous set + 0x744 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOE_CLEAR + GPIO interrupt asynchronous clear + 0x748 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOE_TOGGLE + GPIO interrupt asynchronous toggle + 0x74c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOF_VALUE + GPIOF interrupt asynchronous + 0x750 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOF_SET + GPIO interrupt asynchronous set + 0x754 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOF_CLEAR + GPIO interrupt asynchronous clear + 0x758 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOF_TOGGLE + GPIO interrupt asynchronous toggle + 0x75c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_VALUE + GPIOX interrupt asynchronous + 0x7d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_SET + GPIO interrupt asynchronous set + 0x7d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_CLEAR + GPIO interrupt asynchronous clear + 0x7d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_TOGGLE + GPIO interrupt asynchronous toggle + 0x7dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_VALUE + GPIOY interrupt asynchronous + 0x7e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_SET + GPIO interrupt asynchronous set + 0x7e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_CLEAR + GPIO interrupt asynchronous clear + 0x7e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_TOGGLE + GPIO interrupt asynchronous toggle + 0x7ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_VALUE + GPIOZ interrupt asynchronous + 0x7f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_SET + GPIO interrupt asynchronous set + 0x7f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_CLEAR + GPIO interrupt asynchronous clear + 0x7f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_TOGGLE + GPIO interrupt asynchronous toggle + 0x7fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf0000000 + + + GPIO1 + GPIO1 + GPIO + 0xf0004000 + + + PGPIO + PGPIO + GPIO + 0xf40dc000 + + + BGPIO + BGPIO + GPIO + 0xf5014000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x202000 + registers + + + + FEATURE + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + PRIORITY_PRIORITY1 + Source priority + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY2 + Source priority + 0x8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY3 + Source priority + 0xc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY4 + Source priority + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY5 + Source priority + 0x14 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY6 + Source priority + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY7 + Source priority + 0x1c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY8 + Source priority + 0x20 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY9 + Source priority + 0x24 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY10 + Source priority + 0x28 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY11 + Source priority + 0x2c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY12 + Source priority + 0x30 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY13 + Source priority + 0x34 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY14 + Source priority + 0x38 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY15 + Source priority + 0x3c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY16 + Source priority + 0x40 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY17 + Source priority + 0x44 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY18 + Source priority + 0x48 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY19 + Source priority + 0x4c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY20 + Source priority + 0x50 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY21 + Source priority + 0x54 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY22 + Source priority + 0x58 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY23 + Source priority + 0x5c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY24 + Source priority + 0x60 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY25 + Source priority + 0x64 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY26 + Source priority + 0x68 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY27 + Source priority + 0x6c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY28 + Source priority + 0x70 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY29 + Source priority + 0x74 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY30 + Source priority + 0x78 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY31 + Source priority + 0x7c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY32 + Source priority + 0x80 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY33 + Source priority + 0x84 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY34 + Source priority + 0x88 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY35 + Source priority + 0x8c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY36 + Source priority + 0x90 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY37 + Source priority + 0x94 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY38 + Source priority + 0x98 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY39 + Source priority + 0x9c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY40 + Source priority + 0xa0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY41 + Source priority + 0xa4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY42 + Source priority + 0xa8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY43 + Source priority + 0xac + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY44 + Source priority + 0xb0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY45 + Source priority + 0xb4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY46 + Source priority + 0xb8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY47 + Source priority + 0xbc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY48 + Source priority + 0xc0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY49 + Source priority + 0xc4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY50 + Source priority + 0xc8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY51 + Source priority + 0xcc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY52 + Source priority + 0xd0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY53 + Source priority + 0xd4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY54 + Source priority + 0xd8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY55 + Source priority + 0xdc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY56 + Source priority + 0xe0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY57 + Source priority + 0xe4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY58 + Source priority + 0xe8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY59 + Source priority + 0xec + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY60 + Source priority + 0xf0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY61 + Source priority + 0xf4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY62 + Source priority + 0xf8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY63 + Source priority + 0xfc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY64 + Source priority + 0x100 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY65 + Source priority + 0x104 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY66 + Source priority + 0x108 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY67 + Source priority + 0x10c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY68 + Source priority + 0x110 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY69 + Source priority + 0x114 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY70 + Source priority + 0x118 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY71 + Source priority + 0x11c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY72 + Source priority + 0x120 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY73 + Source priority + 0x124 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY74 + Source priority + 0x128 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY75 + Source priority + 0x12c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY76 + Source priority + 0x130 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY77 + Source priority + 0x134 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY78 + Source priority + 0x138 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY79 + Source priority + 0x13c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY80 + Source priority + 0x140 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY81 + Source priority + 0x144 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY82 + Source priority + 0x148 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY83 + Source priority + 0x14c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY84 + Source priority + 0x150 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY85 + Source priority + 0x154 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY86 + Source priority + 0x158 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY87 + Source priority + 0x15c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY88 + Source priority + 0x160 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY89 + Source priority + 0x164 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY90 + Source priority + 0x168 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY91 + Source priority + 0x16c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY92 + Source priority + 0x170 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY93 + Source priority + 0x174 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY94 + Source priority + 0x178 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY95 + Source priority + 0x17c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY96 + Source priority + 0x180 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY97 + Source priority + 0x184 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY98 + Source priority + 0x188 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY99 + Source priority + 0x18c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY100 + Source priority + 0x190 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY101 + Source priority + 0x194 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY102 + Source priority + 0x198 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY103 + Source priority + 0x19c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY104 + Source priority + 0x1a0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY105 + Source priority + 0x1a4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY106 + Source priority + 0x1a8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY107 + Source priority + 0x1ac + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY108 + Source priority + 0x1b0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY109 + Source priority + 0x1b4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY110 + Source priority + 0x1b8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY111 + Source priority + 0x1bc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY112 + Source priority + 0x1c0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY113 + Source priority + 0x1c4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY114 + Source priority + 0x1c8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY115 + Source priority + 0x1cc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY116 + Source priority + 0x1d0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY117 + Source priority + 0x1d4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY118 + Source priority + 0x1d8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY119 + Source priority + 0x1dc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY120 + Source priority + 0x1e0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY121 + Source priority + 0x1e4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY122 + Source priority + 0x1e8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY123 + Source priority + 0x1ec + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY124 + Source priority + 0x1f0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY125 + Source priority + 0x1f4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY126 + Source priority + 0x1f8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY127 + Source priority + 0x1fc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PENDING_PENDING0 + Pending status + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + PENDING_PENDING1 + Pending status + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + PENDING_PENDING2 + Pending status + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + PENDING_PENDING3 + Pending status + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TRIGGER_TRIGGER0 + Trigger type + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + TRIGGER_TRIGGER1 + Trigger type + 0x1084 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + TRIGGER_TRIGGER2 + Trigger type + 0x1088 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + TRIGGER_TRIGGER3 + Trigger type + 0x108c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + TARGETINT_TARGET0_INTEN0 + machine interrupt enable + 0x2000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET0_INTEN1 + machine interrupt enable + 0x2004 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET0_INTEN2 + machine interrupt enable + 0x2008 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET0_INTEN3 + machine interrupt enable + 0x200c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN0 + supervisor interrupt enable + 0x2080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN1 + supervisor interrupt enable + 0x2084 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN2 + supervisor interrupt enable + 0x2088 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN3 + supervisor interrupt enable + 0x208c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET0_THRESHOLD + Target0 priority threshold + 0x200000 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET0_CLAIM + Target claim and complete + 0x200004 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + TARGETCONFIG_TARGET0_PPS + Preempted priority stack + 0x200400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET1_THRESHOLD + Target1 priority threshold + 0x201000 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET1_CLAIM + Target claim and complete + 0x201004 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + TARGETCONFIG_TARGET1_PPS + Preempted priority stack + 0x201400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + GPIOM + GPIOM + GPIOM + 0xf0008000 + + 0x0 + 0x800 + registers + + + + ASSIGN_GPIOA_PIN_PIN00 + GPIO mananger + 0x0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN01 + GPIO mananger + 0x4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN02 + GPIO mananger + 0x8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN03 + GPIO mananger + 0xc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN04 + GPIO mananger + 0x10 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN05 + GPIO mananger + 0x14 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN06 + GPIO mananger + 0x18 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN07 + GPIO mananger + 0x1c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN08 + GPIO mananger + 0x20 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN09 + GPIO mananger + 0x24 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN10 + GPIO mananger + 0x28 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN11 + GPIO mananger + 0x2c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN12 + GPIO mananger + 0x30 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN13 + GPIO mananger + 0x34 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN14 + GPIO mananger + 0x38 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN15 + GPIO mananger + 0x3c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN16 + GPIO mananger + 0x40 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN17 + GPIO mananger + 0x44 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN18 + GPIO mananger + 0x48 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN19 + GPIO mananger + 0x4c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN20 + GPIO mananger + 0x50 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN21 + GPIO mananger + 0x54 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN22 + GPIO mananger + 0x58 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN23 + GPIO mananger + 0x5c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN24 + GPIO mananger + 0x60 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN25 + GPIO mananger + 0x64 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN26 + GPIO mananger + 0x68 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN27 + GPIO mananger + 0x6c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN28 + GPIO mananger + 0x70 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN29 + GPIO mananger + 0x74 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN30 + GPIO mananger + 0x78 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN31 + GPIO mananger + 0x7c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN00 + GPIO mananger + 0x80 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN01 + GPIO mananger + 0x84 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN02 + GPIO mananger + 0x88 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN03 + GPIO mananger + 0x8c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN04 + GPIO mananger + 0x90 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN05 + GPIO mananger + 0x94 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN06 + GPIO mananger + 0x98 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN07 + GPIO mananger + 0x9c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN08 + GPIO mananger + 0xa0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN09 + GPIO mananger + 0xa4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN10 + GPIO mananger + 0xa8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN11 + GPIO mananger + 0xac + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN12 + GPIO mananger + 0xb0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN13 + GPIO mananger + 0xb4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN14 + GPIO mananger + 0xb8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN15 + GPIO mananger + 0xbc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN16 + GPIO mananger + 0xc0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN17 + GPIO mananger + 0xc4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN18 + GPIO mananger + 0xc8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN19 + GPIO mananger + 0xcc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN20 + GPIO mananger + 0xd0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN21 + GPIO mananger + 0xd4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN22 + GPIO mananger + 0xd8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN23 + GPIO mananger + 0xdc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN24 + GPIO mananger + 0xe0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN25 + GPIO mananger + 0xe4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN26 + GPIO mananger + 0xe8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN27 + GPIO mananger + 0xec + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN28 + GPIO mananger + 0xf0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN29 + GPIO mananger + 0xf4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN30 + GPIO mananger + 0xf8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN31 + GPIO mananger + 0xfc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN00 + GPIO mananger + 0x100 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN01 + GPIO mananger + 0x104 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN02 + GPIO mananger + 0x108 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN03 + GPIO mananger + 0x10c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN04 + GPIO mananger + 0x110 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN05 + GPIO mananger + 0x114 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN06 + GPIO mananger + 0x118 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN07 + GPIO mananger + 0x11c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN08 + GPIO mananger + 0x120 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN09 + GPIO mananger + 0x124 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN10 + GPIO mananger + 0x128 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN11 + GPIO mananger + 0x12c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN12 + GPIO mananger + 0x130 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN13 + GPIO mananger + 0x134 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN14 + GPIO mananger + 0x138 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN15 + GPIO mananger + 0x13c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN16 + GPIO mananger + 0x140 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN17 + GPIO mananger + 0x144 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN18 + GPIO mananger + 0x148 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN19 + GPIO mananger + 0x14c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN20 + GPIO mananger + 0x150 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN21 + GPIO mananger + 0x154 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN22 + GPIO mananger + 0x158 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN23 + GPIO mananger + 0x15c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN24 + GPIO mananger + 0x160 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN25 + GPIO mananger + 0x164 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN26 + GPIO mananger + 0x168 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN27 + GPIO mananger + 0x16c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN28 + GPIO mananger + 0x170 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN29 + GPIO mananger + 0x174 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN30 + GPIO mananger + 0x178 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN31 + GPIO mananger + 0x17c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN00 + GPIO mananger + 0x180 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN01 + GPIO mananger + 0x184 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN02 + GPIO mananger + 0x188 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN03 + GPIO mananger + 0x18c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN04 + GPIO mananger + 0x190 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN05 + GPIO mananger + 0x194 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN06 + GPIO mananger + 0x198 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN07 + GPIO mananger + 0x19c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN08 + GPIO mananger + 0x1a0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN09 + GPIO mananger + 0x1a4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN10 + GPIO mananger + 0x1a8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN11 + GPIO mananger + 0x1ac + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN12 + GPIO mananger + 0x1b0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN13 + GPIO mananger + 0x1b4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN14 + GPIO mananger + 0x1b8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN15 + GPIO mananger + 0x1bc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN16 + GPIO mananger + 0x1c0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN17 + GPIO mananger + 0x1c4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN18 + GPIO mananger + 0x1c8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN19 + GPIO mananger + 0x1cc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN20 + GPIO mananger + 0x1d0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN21 + GPIO mananger + 0x1d4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN22 + GPIO mananger + 0x1d8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN23 + GPIO mananger + 0x1dc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN24 + GPIO mananger + 0x1e0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN25 + GPIO mananger + 0x1e4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN26 + GPIO mananger + 0x1e8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN27 + GPIO mananger + 0x1ec + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN28 + GPIO mananger + 0x1f0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN29 + GPIO mananger + 0x1f4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN30 + GPIO mananger + 0x1f8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOD_PIN_PIN31 + GPIO mananger + 0x1fc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN00 + GPIO mananger + 0x200 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN01 + GPIO mananger + 0x204 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN02 + GPIO mananger + 0x208 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN03 + GPIO mananger + 0x20c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN04 + GPIO mananger + 0x210 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN05 + GPIO mananger + 0x214 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN06 + GPIO mananger + 0x218 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN07 + GPIO mananger + 0x21c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN08 + GPIO mananger + 0x220 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN09 + GPIO mananger + 0x224 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN10 + GPIO mananger + 0x228 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN11 + GPIO mananger + 0x22c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN12 + GPIO mananger + 0x230 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN13 + GPIO mananger + 0x234 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN14 + GPIO mananger + 0x238 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN15 + GPIO mananger + 0x23c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN16 + GPIO mananger + 0x240 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN17 + GPIO mananger + 0x244 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN18 + GPIO mananger + 0x248 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN19 + GPIO mananger + 0x24c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN20 + GPIO mananger + 0x250 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN21 + GPIO mananger + 0x254 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN22 + GPIO mananger + 0x258 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN23 + GPIO mananger + 0x25c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN24 + GPIO mananger + 0x260 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN25 + GPIO mananger + 0x264 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN26 + GPIO mananger + 0x268 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN27 + GPIO mananger + 0x26c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN28 + GPIO mananger + 0x270 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN29 + GPIO mananger + 0x274 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN30 + GPIO mananger + 0x278 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOE_PIN_PIN31 + GPIO mananger + 0x27c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN00 + GPIO mananger + 0x280 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN01 + GPIO mananger + 0x284 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN02 + GPIO mananger + 0x288 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN03 + GPIO mananger + 0x28c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN04 + GPIO mananger + 0x290 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN05 + GPIO mananger + 0x294 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN06 + GPIO mananger + 0x298 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN07 + GPIO mananger + 0x29c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN08 + GPIO mananger + 0x2a0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN09 + GPIO mananger + 0x2a4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN10 + GPIO mananger + 0x2a8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN11 + GPIO mananger + 0x2ac + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN12 + GPIO mananger + 0x2b0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN13 + GPIO mananger + 0x2b4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN14 + GPIO mananger + 0x2b8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN15 + GPIO mananger + 0x2bc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN16 + GPIO mananger + 0x2c0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN17 + GPIO mananger + 0x2c4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN18 + GPIO mananger + 0x2c8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN19 + GPIO mananger + 0x2cc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN20 + GPIO mananger + 0x2d0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN21 + GPIO mananger + 0x2d4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN22 + GPIO mananger + 0x2d8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN23 + GPIO mananger + 0x2dc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN24 + GPIO mananger + 0x2e0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN25 + GPIO mananger + 0x2e4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN26 + GPIO mananger + 0x2e8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN27 + GPIO mananger + 0x2ec + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN28 + GPIO mananger + 0x2f0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN29 + GPIO mananger + 0x2f4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN30 + GPIO mananger + 0x2f8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOF_PIN_PIN31 + GPIO mananger + 0x2fc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN00 + GPIO mananger + 0x680 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN01 + GPIO mananger + 0x684 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN02 + GPIO mananger + 0x688 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN03 + GPIO mananger + 0x68c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN04 + GPIO mananger + 0x690 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN05 + GPIO mananger + 0x694 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN06 + GPIO mananger + 0x698 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN07 + GPIO mananger + 0x69c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN08 + GPIO mananger + 0x6a0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN09 + GPIO mananger + 0x6a4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN10 + GPIO mananger + 0x6a8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN11 + GPIO mananger + 0x6ac + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN12 + GPIO mananger + 0x6b0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN13 + GPIO mananger + 0x6b4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN14 + GPIO mananger + 0x6b8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN15 + GPIO mananger + 0x6bc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN16 + GPIO mananger + 0x6c0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN17 + GPIO mananger + 0x6c4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN18 + GPIO mananger + 0x6c8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN19 + GPIO mananger + 0x6cc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN20 + GPIO mananger + 0x6d0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN21 + GPIO mananger + 0x6d4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN22 + GPIO mananger + 0x6d8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN23 + GPIO mananger + 0x6dc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN24 + GPIO mananger + 0x6e0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN25 + GPIO mananger + 0x6e4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN26 + GPIO mananger + 0x6e8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN27 + GPIO mananger + 0x6ec + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN28 + GPIO mananger + 0x6f0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN29 + GPIO mananger + 0x6f4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN30 + GPIO mananger + 0x6f8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN31 + GPIO mananger + 0x6fc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN00 + GPIO mananger + 0x700 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN01 + GPIO mananger + 0x704 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN02 + GPIO mananger + 0x708 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN03 + GPIO mananger + 0x70c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN04 + GPIO mananger + 0x710 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN05 + GPIO mananger + 0x714 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN06 + GPIO mananger + 0x718 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN07 + GPIO mananger + 0x71c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN08 + GPIO mananger + 0x720 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN09 + GPIO mananger + 0x724 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN10 + GPIO mananger + 0x728 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN11 + GPIO mananger + 0x72c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN12 + GPIO mananger + 0x730 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN13 + GPIO mananger + 0x734 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN14 + GPIO mananger + 0x738 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN15 + GPIO mananger + 0x73c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN16 + GPIO mananger + 0x740 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN17 + GPIO mananger + 0x744 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN18 + GPIO mananger + 0x748 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN19 + GPIO mananger + 0x74c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN20 + GPIO mananger + 0x750 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN21 + GPIO mananger + 0x754 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN22 + GPIO mananger + 0x758 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN23 + GPIO mananger + 0x75c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN24 + GPIO mananger + 0x760 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN25 + GPIO mananger + 0x764 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN26 + GPIO mananger + 0x768 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN27 + GPIO mananger + 0x76c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN28 + GPIO mananger + 0x770 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN29 + GPIO mananger + 0x774 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN30 + GPIO mananger + 0x778 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN31 + GPIO mananger + 0x77c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN00 + GPIO mananger + 0x780 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN01 + GPIO mananger + 0x784 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN02 + GPIO mananger + 0x788 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN03 + GPIO mananger + 0x78c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN04 + GPIO mananger + 0x790 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN05 + GPIO mananger + 0x794 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN06 + GPIO mananger + 0x798 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN07 + GPIO mananger + 0x79c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN08 + GPIO mananger + 0x7a0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN09 + GPIO mananger + 0x7a4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN10 + GPIO mananger + 0x7a8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN11 + GPIO mananger + 0x7ac + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN12 + GPIO mananger + 0x7b0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN13 + GPIO mananger + 0x7b4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN14 + GPIO mananger + 0x7b8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN15 + GPIO mananger + 0x7bc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN16 + GPIO mananger + 0x7c0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN17 + GPIO mananger + 0x7c4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN18 + GPIO mananger + 0x7c8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN19 + GPIO mananger + 0x7cc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN20 + GPIO mananger + 0x7d0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN21 + GPIO mananger + 0x7d4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN22 + GPIO mananger + 0x7d8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN23 + GPIO mananger + 0x7dc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN24 + GPIO mananger + 0x7e0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN25 + GPIO mananger + 0x7e4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN26 + GPIO mananger + 0x7e8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN27 + GPIO mananger + 0x7ec + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN28 + GPIO mananger + 0x7f0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN29 + GPIO mananger + 0x7f4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN30 + GPIO mananger + 0x7f8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN31 + GPIO mananger + 0x7fc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + + + ADC0 + ADC0 + ADC12 + 0xf0010000 + + 0x0 + 0x1214 + registers + + + + CONFIG_TRG0A + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG0B + No description avaiable + 0x4 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG0C + No description avaiable + 0x8 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1A + No description avaiable + 0xc + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1B + No description avaiable + 0x10 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1C + No description avaiable + 0x14 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2A + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2B + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2C + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3A + No description avaiable + 0x24 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3B + No description avaiable + 0x28 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3C + No description avaiable + 0x2c + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + TRG_DMA_ADDR + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + BUS_RESULT_CHN0 + No description avaiable + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN1 + No description avaiable + 0x404 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN2 + No description avaiable + 0x408 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN3 + No description avaiable + 0x40c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN4 + No description avaiable + 0x410 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN5 + No description avaiable + 0x414 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN6 + No description avaiable + 0x418 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN7 + No description avaiable + 0x41c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN8 + No description avaiable + 0x420 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN9 + No description avaiable + 0x424 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN10 + No description avaiable + 0x428 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN11 + No description avaiable + 0x42c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN12 + No description avaiable + 0x430 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN13 + No description avaiable + 0x434 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN14 + No description avaiable + 0x438 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN15 + No description avaiable + 0x43c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN16 + No description avaiable + 0x440 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN17 + No description avaiable + 0x444 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN18 + No description avaiable + 0x448 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUF_CFG0 + No description avaiable + 0x500 + 32 + 0x00000000 + 0x00000001 + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + SEQ_CFG0 + No description avaiable + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + SEQ_DMA_ADDR + No description avaiable + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + SEQ_WR_ADDR + No description avaiable + 0x808 + 32 + 0x00000000 + 0x00000FFF + + + SEQ_WR_POINTER + HW update this field after each dma write, it indicate the next dma write pointer. +dma write address is (tar_addr+seq_wr_pointer)*4 + 0 + 12 + read-only + + + + + SEQ_DMA_CFG + No description avaiable + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + SEQ_QUE_CFG0 + No description avaiable + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG1 + No description avaiable + 0x814 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG2 + No description avaiable + 0x818 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG3 + No description avaiable + 0x81c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG4 + No description avaiable + 0x820 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG5 + No description avaiable + 0x824 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG6 + No description avaiable + 0x828 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG7 + No description avaiable + 0x82c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG8 + No description avaiable + 0x830 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG9 + No description avaiable + 0x834 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG10 + No description avaiable + 0x838 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG11 + No description avaiable + 0x83c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG12 + No description avaiable + 0x840 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG13 + No description avaiable + 0x844 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG14 + No description avaiable + 0x848 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG15 + No description avaiable + 0x84c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + PRD_CFG_CHN0_PRD_CFG + No description avaiable + 0xc00 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN0_PRD_THSHD_CFG + No description avaiable + 0xc04 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN0_PRD_RESULT + No description avaiable + 0xc08 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN1_PRD_CFG + No description avaiable + 0xc10 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN1_PRD_THSHD_CFG + No description avaiable + 0xc14 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN1_PRD_RESULT + No description avaiable + 0xc18 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN2_PRD_CFG + No description avaiable + 0xc20 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN2_PRD_THSHD_CFG + No description avaiable + 0xc24 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN2_PRD_RESULT + No description avaiable + 0xc28 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN3_PRD_CFG + No description avaiable + 0xc30 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN3_PRD_THSHD_CFG + No description avaiable + 0xc34 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN3_PRD_RESULT + No description avaiable + 0xc38 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN4_PRD_CFG + No description avaiable + 0xc40 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN4_PRD_THSHD_CFG + No description avaiable + 0xc44 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN4_PRD_RESULT + No description avaiable + 0xc48 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN5_PRD_CFG + No description avaiable + 0xc50 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN5_PRD_THSHD_CFG + No description avaiable + 0xc54 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN5_PRD_RESULT + No description avaiable + 0xc58 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN6_PRD_CFG + No description avaiable + 0xc60 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN6_PRD_THSHD_CFG + No description avaiable + 0xc64 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN6_PRD_RESULT + No description avaiable + 0xc68 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN7_PRD_CFG + No description avaiable + 0xc70 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN7_PRD_THSHD_CFG + No description avaiable + 0xc74 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN7_PRD_RESULT + No description avaiable + 0xc78 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN8_PRD_CFG + No description avaiable + 0xc80 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN8_PRD_THSHD_CFG + No description avaiable + 0xc84 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN8_PRD_RESULT + No description avaiable + 0xc88 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN9_PRD_CFG + No description avaiable + 0xc90 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN9_PRD_THSHD_CFG + No description avaiable + 0xc94 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN9_PRD_RESULT + No description avaiable + 0xc98 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN10_PRD_CFG + No description avaiable + 0xca0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN10_PRD_THSHD_CFG + No description avaiable + 0xca4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN10_PRD_RESULT + No description avaiable + 0xca8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN11_PRD_CFG + No description avaiable + 0xcb0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN11_PRD_THSHD_CFG + No description avaiable + 0xcb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN11_PRD_RESULT + No description avaiable + 0xcb8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN12_PRD_CFG + No description avaiable + 0xcc0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN12_PRD_THSHD_CFG + No description avaiable + 0xcc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN12_PRD_RESULT + No description avaiable + 0xcc8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN13_PRD_CFG + No description avaiable + 0xcd0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN13_PRD_THSHD_CFG + No description avaiable + 0xcd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN13_PRD_RESULT + No description avaiable + 0xcd8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN14_PRD_CFG + No description avaiable + 0xce0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN14_PRD_THSHD_CFG + No description avaiable + 0xce4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN14_PRD_RESULT + No description avaiable + 0xce8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN15_PRD_CFG + No description avaiable + 0xcf0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN15_PRD_THSHD_CFG + No description avaiable + 0xcf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN15_PRD_RESULT + No description avaiable + 0xcf8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN16_PRD_CFG + No description avaiable + 0xd00 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN16_PRD_THSHD_CFG + No description avaiable + 0xd04 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN16_PRD_RESULT + No description avaiable + 0xd08 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN17_PRD_CFG + No description avaiable + 0xd10 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN17_PRD_THSHD_CFG + No description avaiable + 0xd14 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN17_PRD_RESULT + No description avaiable + 0xd18 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN18_PRD_CFG + No description avaiable + 0xd20 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN18_PRD_THSHD_CFG + No description avaiable + 0xd24 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN18_PRD_RESULT + No description avaiable + 0xd28 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + SAMPLE_CFG_CHN0 + No description avaiable + 0x1000 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN1 + No description avaiable + 0x1004 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN2 + No description avaiable + 0x1008 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN3 + No description avaiable + 0x100c + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN4 + No description avaiable + 0x1010 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN5 + No description avaiable + 0x1014 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN6 + No description avaiable + 0x1018 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN7 + No description avaiable + 0x101c + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN8 + No description avaiable + 0x1020 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN9 + No description avaiable + 0x1024 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN10 + No description avaiable + 0x1028 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN11 + No description avaiable + 0x102c + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN12 + No description avaiable + 0x1030 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN13 + No description avaiable + 0x1034 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN14 + No description avaiable + 0x1038 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN15 + No description avaiable + 0x103c + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN16 + No description avaiable + 0x1040 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN17 + No description avaiable + 0x1044 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN18 + No description avaiable + 0x1048 + 32 + 0x00000000 + 0x00001FFF + + + DIFF_SEL + set to 1 to select differential channel + 12 + 1 + read-write + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample_clock_number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + CONV_CFG1 + No description avaiable + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 13 (0xD) for 12bit mode, which means convert need 14 adc clock cycles(based on clock after divider); +set to 11 for 10bit mode; set to 9 for 8bit mode; set to 7 or 6bit mode; +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 13 for 12bit mode, clock_divder to 2, then each ADC convertion(plus sample) need 18(14 convert, 4 sample) cycles(66MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. +set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + ADC_CFG0 + No description avaiable + 0x1108 + 32 + 0x00000000 + 0xA0000000 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + + + INT_STS + No description avaiable + 0x1110 + 32 + 0x00000000 + 0xFFE7FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + No description avaiable + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1 + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 19 + read-write + + + + + INT_EN + No description avaiable + 0x1114 + 32 + 0x00000000 + 0xFFE7FFFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 19 + read-write + + + + + ANA_CTRL0 + No description avaiable + 0x1200 + 32 + 0x00000000 + 0x7F7F487E + + + CAL_VAL_DIFF + calibration value for differential mode + 24 + 7 + read-write + + + CAL_VAL_SE + calibration value for single-end mode + 16 + 7 + read-write + + + REARM_EN + set will insert one adc cycle rearm before sample, user need to increase one to sample_clock_number + 14 + 1 + read-write + + + SELRANGE_LDO + Defines the range for the LDO reference (vdd_soc) +selrange_ldo = 0: LDO reference dvdd or vref_ldo in range [0.81;0.99] +selrange_ldo = 1: LDO reference dvdd or vref_ldo in range [0.99;1.21] + 11 + 1 + read-write + + + ENLDO + set to enable adc LDO, need at least 20us for LDO to be stable. + 6 + 1 + read-write + + + ENADC + set to enable adc analog function. user need set it after LDO stable, or wait at least 20us after setting enldo, then set this bit. + 5 + 1 + read-write + + + RESETADC + set to 1 to reset adc analog; default high. + 4 + 1 + read-write + + + RESETCAL + set to 1 to reset calibration logic; default high. + 3 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + LOADCAL + Signal that loads the offset calibration word into the internal registers (Active H) + 1 + 1 + read-write + + + + + ANA_CTRL1 + No description avaiable + 0x1204 + 32 + 0x00000000 + 0x000000C0 + + + SELRES + 11-12bit +10-10bit +01-8bit +00-6bit + 6 + 2 + read-write + + + + + ANA_STATUS + No description avaiable + 0x1210 + 32 + 0x00000000 + 0x000000FF + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + CAL_OUT + No description avaiable + 0 + 7 + read-write + + + + + + + ADC1 + ADC1 + ADC12 + 0xf0014000 + + + ADC2 + ADC2 + ADC12 + 0xf0018000 + + + ADC3 + ADC3 + ADC16 + 0xf001c000 + + 0x0 + 0x1464 + registers + + + + CONFIG_TRG0A + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG0B + No description avaiable + 0x4 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG0C + No description avaiable + 0x8 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1A + No description avaiable + 0xc + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1B + No description avaiable + 0x10 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1C + No description avaiable + 0x14 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2A + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2B + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2C + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3A + No description avaiable + 0x24 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3B + No description avaiable + 0x28 + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3C + No description avaiable + 0x2c + 32 + 0x00000000 + 0xFF3F3F3F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + TRG_DMA_ADDR + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + BUS_RESULT_CHN0 + No description avaiable + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN1 + No description avaiable + 0x404 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN2 + No description avaiable + 0x408 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN3 + No description avaiable + 0x40c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN4 + No description avaiable + 0x410 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN5 + No description avaiable + 0x414 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN6 + No description avaiable + 0x418 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN7 + No description avaiable + 0x41c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUF_CFG0 + No description avaiable + 0x500 + 32 + 0x00000000 + 0x00000001 + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + SEQ_CFG0 + No description avaiable + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + SEQ_DMA_ADDR + No description avaiable + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + SEQ_WR_ADDR + No description avaiable + 0x808 + 32 + 0x00000000 + 0x00000FFF + + + SEQ_WR_POINTER + HW update this field after each dma write, it indicate the next dma write pointer. +dma write address is (tar_addr+seq_wr_pointer)*4 + 0 + 12 + read-only + + + + + SEQ_DMA_CFG + No description avaiable + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + SEQ_QUE_CFG0 + No description avaiable + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG1 + No description avaiable + 0x814 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG2 + No description avaiable + 0x818 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG3 + No description avaiable + 0x81c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG4 + No description avaiable + 0x820 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG5 + No description avaiable + 0x824 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG6 + No description avaiable + 0x828 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG7 + No description avaiable + 0x82c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG8 + No description avaiable + 0x830 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG9 + No description avaiable + 0x834 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG10 + No description avaiable + 0x838 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG11 + No description avaiable + 0x83c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG12 + No description avaiable + 0x840 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG13 + No description avaiable + 0x844 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG14 + No description avaiable + 0x848 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG15 + No description avaiable + 0x84c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + PRD_CFG_CHN0_PRD_CFG + No description avaiable + 0xc00 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN0_PRD_THSHD_CFG + No description avaiable + 0xc04 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN0_PRD_RESULT + No description avaiable + 0xc08 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN1_PRD_CFG + No description avaiable + 0xc10 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN1_PRD_THSHD_CFG + No description avaiable + 0xc14 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN1_PRD_RESULT + No description avaiable + 0xc18 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN2_PRD_CFG + No description avaiable + 0xc20 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN2_PRD_THSHD_CFG + No description avaiable + 0xc24 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN2_PRD_RESULT + No description avaiable + 0xc28 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN3_PRD_CFG + No description avaiable + 0xc30 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN3_PRD_THSHD_CFG + No description avaiable + 0xc34 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN3_PRD_RESULT + No description avaiable + 0xc38 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN4_PRD_CFG + No description avaiable + 0xc40 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN4_PRD_THSHD_CFG + No description avaiable + 0xc44 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN4_PRD_RESULT + No description avaiable + 0xc48 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN5_PRD_CFG + No description avaiable + 0xc50 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN5_PRD_THSHD_CFG + No description avaiable + 0xc54 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN5_PRD_RESULT + No description avaiable + 0xc58 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN6_PRD_CFG + No description avaiable + 0xc60 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN6_PRD_THSHD_CFG + No description avaiable + 0xc64 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN6_PRD_RESULT + No description avaiable + 0xc68 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN7_PRD_CFG + No description avaiable + 0xc70 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN7_PRD_THSHD_CFG + No description avaiable + 0xc74 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN7_PRD_RESULT + No description avaiable + 0xc78 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + SAMPLE_CFG_CHN0 + No description avaiable + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN1 + No description avaiable + 0x1004 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN2 + No description avaiable + 0x1008 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN3 + No description avaiable + 0x100c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN4 + No description avaiable + 0x1010 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN5 + No description avaiable + 0x1014 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN6 + No description avaiable + 0x1018 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN7 + No description avaiable + 0x101c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + CONV_CFG1 + No description avaiable + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); +user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. +set to 3 can genenerate 50MHz adc_clk at 200MHz bus_clk. + 0 + 4 + read-write + + + + + ADC_CFG0 + No description avaiable + 0x1108 + 32 + 0x00000000 + 0xAFFFF001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + CONVERT_DURATION + for trigger queue, from trg_sample_req to trg_convert_req + 12 + 16 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + INT_STS + No description avaiable + 0x1110 + 32 + 0x00000000 + 0xFFE03FFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 14 + read-write + + + + + INT_EN + No description avaiable + 0x1114 + 32 + 0x00000000 + 0xFFE03FFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 14 + read-write + + + + + ANA_CTRL0 + No description avaiable + 0x1200 + 32 + 0x00000000 + 0x00001004 + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ANA_STATUS + No description avaiable + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + ADC16_PARAMS_ADC16_PARA00 + No description avaiable + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA01 + No description avaiable + 0x1402 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA02 + No description avaiable + 0x1404 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA03 + No description avaiable + 0x1406 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA04 + No description avaiable + 0x1408 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA05 + No description avaiable + 0x140a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA06 + No description avaiable + 0x140c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA07 + No description avaiable + 0x140e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA08 + No description avaiable + 0x1410 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA09 + No description avaiable + 0x1412 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA10 + No description avaiable + 0x1414 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA11 + No description avaiable + 0x1416 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA12 + No description avaiable + 0x1418 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA13 + No description avaiable + 0x141a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA14 + No description avaiable + 0x141c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA15 + No description avaiable + 0x141e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA16 + No description avaiable + 0x1420 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA17 + No description avaiable + 0x1422 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA18 + No description avaiable + 0x1424 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA19 + No description avaiable + 0x1426 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA20 + No description avaiable + 0x1428 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA21 + No description avaiable + 0x142a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA22 + No description avaiable + 0x142c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA23 + No description avaiable + 0x142e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA24 + No description avaiable + 0x1430 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA25 + No description avaiable + 0x1432 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA26 + No description avaiable + 0x1434 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA27 + No description avaiable + 0x1436 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA28 + No description avaiable + 0x1438 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA29 + No description avaiable + 0x143a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA30 + No description avaiable + 0x143c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA31 + No description avaiable + 0x143e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA32 + No description avaiable + 0x1440 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA33 + No description avaiable + 0x1442 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_CONFIG0 + No description avaiable + 0x1444 + 32 + 0x00000000 + 0x03F07FFF + + + TEMPSNS_EN + set to enable temp senser + 25 + 1 + read-write + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + convertion parameter + 0 + 14 + read-write + + + + + ADC16_CONFIG1 + No description avaiable + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number). + 8 + 5 + read-write + + + + + + + ACMP + ACMP + ACMP + 0xf0020000 + + 0x0 + 0x80 + registers + + + + CHANNEL_CHN0_CFG + Configure Register + 0x0 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN0_DACCFG + DAC configure register + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN0_SR + Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN0_IRQEN + Interrupt request enable register + 0x14 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN0_DMAEN + DMA request enable register + 0x18 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN1_CFG + Configure Register + 0x20 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN1_DACCFG + DAC configure register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN1_SR + Status register + 0x30 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN1_IRQEN + Interrupt request enable register + 0x34 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN1_DMAEN + DMA request enable register + 0x38 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN2_CFG + Configure Register + 0x40 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN2_DACCFG + DAC configure register + 0x44 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN2_SR + Status register + 0x50 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN2_IRQEN + Interrupt request enable register + 0x54 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN2_DMAEN + DMA request enable register + 0x58 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN3_CFG + Configure Register + 0x60 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN3_DACCFG + DAC configure register + 0x64 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN3_SR + Status register + 0x70 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN3_IRQEN + Interrupt request enable register + 0x74 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN3_DMAEN + DMA request enable register + 0x78 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + + + SPI0 + SPI0 + SPI + 0xf0030000 + + 0x10 + 0x70 + registers + + + + TRANSFMT + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + RESERVED + No description avaiable + 18 + 14 + read-write + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + DIRECTIO + Direct IO Control Register + 0x14 + 32 + 0x00003100 + 0x013F3F3F + + + DIRECTIOEN + Enable Direct IO +0x0: Disable +0x1: Enable + 24 + 1 + read-write + + + HOLD_OE + Output enable for the SPI Flash hold signal + 21 + 1 + read-write + + + WP_OE + Output enable for the SPI Flash write protect signal + 20 + 1 + read-write + + + MISO_OE + Output enable fo the SPI MISO signal + 19 + 1 + read-write + + + MOSI_OE + Output enable for the SPI MOSI signal + 18 + 1 + read-write + + + SCLK_OE + Output enable for the SPI SCLK signal + 17 + 1 + read-write + + + CS_OE + Output enable for SPI CS (chip select) signal + 16 + 1 + read-write + + + HOLD_O + Output value for the SPI Flash hold signal + 13 + 1 + read-write + + + WP_O + Output value for the SPI Flash write protect signal + 12 + 1 + read-write + + + MISO_O + Output value for the SPI MISO signal + 11 + 1 + read-write + + + MOSI_O + Output value for the SPI MOSI signal + 10 + 1 + read-write + + + SCLK_O + Output value for the SPI SCLK signal + 9 + 1 + read-write + + + CS_O + Output value for the SPI CS (chip select) signal + 8 + 1 + read-write + + + HOLD_I + Status of the SPI Flash hold signal + 5 + 1 + read-only + + + WP_I + Status of the SPI Flash write protect signal + 4 + 1 + read-only + + + MISO_I + Status of the SPI MISO signal + 3 + 1 + read-only + + + MOSI_I + Status of the SPI MOSI signal + 2 + 1 + read-only + + + SCLK_I + Status of the SPI SCLK signal + 1 + 1 + read-only + + + CS_I + Status of the SPI CS (chip select) signal + 0 + 1 + read-only + + + + + TRANSCTRL + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + CMD + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + ADDR + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + DATA + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + CTRL + Control Register + 0x30 + 32 + 0x00000000 + 0x00FFFF1F + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + STATUS + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + INTREN + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + INTRST + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + read-write + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + read-write + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + read-write + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + read-write + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + read-write + + + + + TIMING + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SLVST + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + read-write + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SLVDATACNT + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + CONFIG + Configuration Register + 0x7c + 32 + 0x00004311 + 0x00004BFF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + DIRECTIO + Support for Direct SPI IO + 11 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0034000 + + + SPI2 + SPI2 + SPI + 0xf0038000 + + + SPI3 + SPI3 + SPI + 0xf003c000 + + + UART0 + UART0 + UART + 0xf0040000 + + 0x10 + 0x2c + registers + + + + CFG + Configuration Register + 0x10 + 32 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 2 + 30 + read-write + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: The over-sample ratio is 32 +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + 0x24 + 32 + 0x00000000 + 0x0000000F + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + 0x28 + 32 + 0x00000001 + 0x000000CF + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0x000000FF + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-write + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + UART4 + UART4 + UART + 0xf0050000 + + + UART5 + UART5 + UART + 0xf0054000 + + + UART6 + UART6 + UART + 0xf0058000 + + + UART7 + UART7 + UART + 0xf005c000 + + + UART8 + UART8 + UART + 0xf0060000 + + + UART9 + UART9 + UART + 0xf0064000 + + + UART10 + UART10 + UART + 0xf0068000 + + + UART11 + UART11 + UART + 0xf006c000 + + + UART12 + UART12 + UART + 0xf0070000 + + + UART13 + UART13 + UART + 0xf0074000 + + + UART14 + UART14 + UART + 0xf0078000 + + + UART15 + UART15 + UART + 0xf007c000 + + + PUART + PUART + UART + 0xf40e4000 + + + CAN0 + CAN0 + CAN + 0xf0080000 + + 0x0 + 0xca + registers + + + + RBUF_BUF0 + receive buffer registers and reception time stamp + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF1 + receive buffer registers and reception time stamp + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF2 + receive buffer registers and reception time stamp + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF3 + receive buffer registers and reception time stamp + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF4 + receive buffer registers and reception time stamp + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF5 + receive buffer registers and reception time stamp + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF6 + receive buffer registers and reception time stamp + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF7 + receive buffer registers and reception time stamp + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF8 + receive buffer registers and reception time stamp + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF9 + receive buffer registers and reception time stamp + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF10 + receive buffer registers and reception time stamp + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF11 + receive buffer registers and reception time stamp + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF12 + receive buffer registers and reception time stamp + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF13 + receive buffer registers and reception time stamp + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF14 + receive buffer registers and reception time stamp + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF15 + receive buffer registers and reception time stamp + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF16 + receive buffer registers and reception time stamp + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF17 + receive buffer registers and reception time stamp + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF18 + receive buffer registers and reception time stamp + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + RBUF_BUF19 + receive buffer registers and reception time stamp + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + RBUF + receive buffer + 0 + 32 + read-write + + + + + TBUF_BUF0 + transmit buffer register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF1 + transmit buffer register + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF2 + transmit buffer register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF3 + transmit buffer register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF4 + transmit buffer register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF5 + transmit buffer register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF6 + transmit buffer register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF7 + transmit buffer register + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF8 + transmit buffer register + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF9 + transmit buffer register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF10 + transmit buffer register + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF11 + transmit buffer register + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF12 + transmit buffer register + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF13 + transmit buffer register + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF14 + transmit buffer register + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF15 + transmit buffer register + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF16 + transmit buffer register + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TBUF_BUF17 + transmit buffer register + 0x94 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBUF + transmit buffer + 0 + 32 + read-write + + + + + TTS_WRD0 + transmission time stamp, LSB 32bit + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + TTS_WRD0 + transmission time stamp, word 0, LSB 32bit + 0 + 32 + read-only + + + + + TTS_WRD1 + transmission time stamp, MSB 32bit + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + TTS_WRD0 + transmission time stamp, word 0, LSB 32bit + 0 + 32 + read-only + + + + + CMD_STA_CMD_CTRL + config, status, command and control bits + 0xa0 + 32 + 0x00900080 + 0xFBF3FFFF + + + SACK + Self-ACKnowledge +0 – no self-ACK +1 – self-ACK when LBME=1 + 31 + 1 + read-write + + + ROM + Receive buffer Overflow Mode +In case of a full RBUF when a new message is received, then ROM selects the following: +1 – The new message will not be stored. +0 – The oldest message will be overwritten. + 30 + 1 + read-write + + + ROV + Receive buffer OVerflow +1 – Overflow. At least one message is lost. +0 – No Overflow. +ROV is cleared by setting RREL=1. + 29 + 1 + read-only + + + RREL + Receive buffer RELease +The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL +core points to the next RB slot. RSTAT gets updated. +1 – Release: The host has read the RB. +0 – No release + 28 + 1 + read-write + + + RBALL + Receive Buffer stores ALL data frames +0 – normal operation +1 – RB stores correct data frames as well as data frames with error + 27 + 1 + read-write + + + RSTAT + Receive buffer STATus +00 - empty +01 - > empty and < almost full (AFWL) +10 -  almost full (programmable threshold by AFWL) but not full and no overflow +11 - full (stays set in case of overflow – for overflow signaling see ROV) + 24 + 2 + read-only + + + FD_ISO + CAN FD ISO mode +0 - Bosch CAN FD (non-ISO) mode +1 - ISO CAN FD mode (ISO 11898-1:2015) +ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. +Both modes are incompatible and must not be mixed in one CAN network. +This bit has no impact to CAN 2.0B. +This bit is only writeable if RESET=1. + 23 + 1 + read-write + + + TSNEXT + Transmit buffer Secondary NEXT +0 - no action +1 - STB slot filled, select next slot. +After all frame bytes are written to the TBUF registers, the host controller has to set +TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF +registers to the next slot. Once a slot is marked as filled a transmission can be started +using TSONE or TSALL. +It is possible to set TSNEXT and TSONE or TSALL together in one write access. +TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL +core immediately after it was set. +Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and +automatically cleared. It does not do any harm. +If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. +TSNEXT has no meaning in TTCAN mode and is fixed to 0. + 22 + 1 + read-write + + + TSMODE + Transmit buffer Secondary operation MODE +0 - FIFO mode +1 - priority decision mode +In FIFO mode frames are transmitted in the order in that they are written into the STB. +In priority decision mode the frame with the highest priority in the STB is automatically +transmitted first. The ID of a frame is used for the priority decision. A lower ID means a +higher priority of a frame. A frame in the PTB has always the highest priority regardless of +the ID. +TSMODE shall be switched only if the STB if empty + 21 + 1 + read-write + + + TTTBM + TTCAN Transmit Buffer Mode +If TTEN=0 then TTTBM is ignored, otherwise the following is valid: +0 - separate PTB and STB, behavior defined by TSMODE +1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR +For event-driven CAN communication (TTEN=0), the system provides PTB and STB and +the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. +For time-triggered CAN communication (TTEN=1) with full support of all features including +time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are +addressable using TTPTR and TBPTR. +For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode +and the behavior can be selected by TSMODE. +TTTBM shall be switched only if the TBUF is empty. + 20 + 1 + read-write + + + TSSTAT + Transmission Secondary STATus bits +If TTEN=0 or TTTBM=0: +00 – STB is empty +01 – STB is less than or equal to half full +10 – STB is more than half full +11 – STB is full +If the STB is disabled using STB_DISABLE, then TSSTAT=00. +If TTEN=1 and TTTBM=1: +00 – PTB and STB are empty +01 – PTB and STB are not empty and not full +11 – PTB and STB are full + 16 + 2 + read-only + + + TBSEL + Transmit Buffer Select +Selects the transmit buffer to be loaded with a message. Use the TBUF registers for +access. TBSEL needs to be stable all the time the TBUF registers are written and when +TSNEXT is set. +0 - PTB (high-priority buffer) +1 - STB +The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) + 15 + 1 + read-write + + + LOM + Listen Only Mode +0 - Disabled +1 - Enabled +LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM +is enabled and LBME is disabled. +LOM=1 and LBME=0 disables all transmissions. +LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables +the transmission of own frames. + 14 + 1 + read-write + + + STBY + Transceiver Standby Mode +0 - Disabled +1 - Enabled +This register bit is connected to the output signal stby which can be used to control a +standby mode of a transceiver. +STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. +If the host sets STBY to 0 then the host needs to wait for the time required by the +transceiver to start up before the host requests a new transmission. + 13 + 1 + read-write + + + TPE + Transmit Primary Enable +1 - Transmission enable for the message in the high-priority PTB +0 - No transmission for the PTB +If TPE is set, the message from the PTB will be transmitted at the next possible transmit +position. A started transmission from the STB will be completed before, but pending new +messages are delayed until the PTB message has been transmitted. +TPE stays set until the message has been transmitted successfully or it is aborted using +TPA. +The host controller can set TPE to 1 but can not reset it to 0. This would only be possible +using TPA and aborting the message. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). + 12 + 1 + read-write + + + TPA + Transmit Primary Abort +1 – Aborts a transmission from PTB which has been requested by TPE=1 but not +started yet. (The data bytes of the message remains in the PTB.) +0 – no abort +The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA +automatically de-asserts TPE. +The host controller can set TPA to 1 but can not reset it to 0. +During the short time while the CAN-CTRL core resets the bit, it cannot be set by the +host. +The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). +TPA should not be set simultaneously with TPE. + 11 + 1 + read-write + + + TSONE + Transmit Secondary ONE frame +1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message +and in priority mode this is the one with the highest priority. +TSONE in priority mode is difficult to handle, because it is not always clear which +message will be transmitted if new messages are written to the STB meanwhile. +The controller starts the transmission as soon as the bus becomes vacant and +no request of the PTB (bit TPE) is pending. +0 – No transmission for the STB. +TSONE stays set until the message has been transmitted successfully or it is aborted +using TSA. +The host controller can set TSONE to 1 but can not reset it to 0. This would only be +possible using TSA and aborting the message. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). + 10 + 1 + read-write + + + TSALL + Transmit Secondary ALL frames +1 – Transmission enable of all messages in the STB. +The controller starts the transmission as soon as the bus becomes vacant and +no request of the PTB (bit TPE) is pending. +0 – No transmission for the STB. +TSALL stays set until all messages have been transmitted successfully or they are aborted +using TSA. +The host controller can set TSALL to 1 but can not reset it to 0. This would only be +possible using TSA and aborting the messages. +The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and +LBME=0) or (TTEN=1 and TTTBM=1). +If during a transmission the STB is loaded with a new frame then the new frame will be +transmitted too. In other words: a transmission initiated by TSALL is finished when the +STB becomes empty. + 9 + 1 + read-write + + + TSA + Transmit Secondary Abort +1 – Aborts a transmission from STB which has been requested but not started yet. +For a TSONE transmission, only one frame is aborted while for a TSALL +Transmission, all frames are aborted. +One or all message slots will be released which updates TSSTAT. +All aborted messages are lost because they are not accessible any more. +If in priority mode a TSONE transmission is aborted, then it is not clear which +frame will be aborted if new frames are written to the STB meanwhile. +0 – no abort +The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. +The host controller can set TSA to 1 but can not reset it to 0. +The bit will be reset to the hardware reset value if RESET=1. +TSA should not be set simultaneously with TSONE or TSALL. + 8 + 1 + read-write + + + RESET + RESET request bit +1 - The host controller performs a local reset of CAN-CTRL. +0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. +Bit RESET forces several components to a reset state. +RESET is automatically set if the node enters “bus off” state. +Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. +This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. +The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. + 7 + 1 + read-write + + + LBME + Loop Back Mode, External +0 - Disabled +1 - EnabledLBME should not be enabled while a transmission is active + 6 + 1 + read-write + + + LBMI + Loop Back Mode, Internal +0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. + 5 + 1 + read-write + + + TPSS + Transmission Primary Single Shot mode for PTB +0 - Disabled +1 - Enabled + 4 + 1 + read-write + + + TSSS + Transmission Secondary Single Shot mode for STB +0 - Disabled +1 - Enabled + 3 + 1 + read-write + + + RACTIVE + Reception ACTIVE (Receive Status bit) +1 - The controller is currently receiving a frame. +0 - No receive activity. + 2 + 1 + read-only + + + TACTIVE + Transmission ACTIVE (Transmit Status bit) +1 - The controller is currently transmitting a frame. +0 - No transmit activity. + 1 + 1 + read-only + + + BUSOFF + Bus Off (Bus Status bit) +1 - The controller status is “bus off”. +0 - The controller status is “bus on”. +Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. +See Chapter 3.9.10.6 for details. + 0 + 1 + read-write + + + + + RTIE + Receive and Transmit Interrupt Enable Register RTIE + 0xa4 + 8 + 0xFE + 0xFF + + + RIE + Receive Interrupt Enable +0 – Disabled, 1 – Enabled + 7 + 1 + read-write + + + ROIE + RB Overrun Interrupt Enable +0 – Disabled, 1 – Enabled + 6 + 1 + read-write + + + RFIE + RB Full Interrupt Enable +0 – Disabled, 1 – Enabled + 5 + 1 + read-write + + + RAFIE + RB Almost Full Interrupt Enable +0 – Disabled, 1 – Enabled + 4 + 1 + read-write + + + TPIE + Transmission Primary Interrupt Enable +0 – Disabled, 1 – Enabled + 3 + 1 + read-write + + + TSIE + Transmission Secondary Interrupt Enable +0 – Disabled, 1 – Enabled + 2 + 1 + read-write + + + EIE + Error Interrupt Enable +0 – Disabled, 1 – Enabled + 1 + 1 + read-write + + + TSFF + If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag +1 - The STB is filled with the maximal number of messages. +0 - The STB is not filled with the maximal number of messages. +If the STB is disabled using STB_DISABLE, then TSFF=0. +If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag +1 - The buffer slot selected by TBPTR is filled. +0 - The buffer slot selected by TBPTR is empty. + 0 + 1 + read-only + + + + + RTIF + Receive and Transmit Interrupt Flag Register RTIF (0xa5) + 0xa5 + 8 + 0x00 + 0xFF + + + RIF + Receive Interrupt Flag +1 - Data or a remote frame has been received and is available in the receive buffer. +0 - No frame has been received. + 7 + 1 + read-write + + + ROIF + RB Overrun Interrupt Flag +1 - At least one received message has been overwritten in the RB. +0 - No RB overwritten. +In case of an overrun both ROIF and RFIF will be set. + 6 + 1 + read-write + + + RFIF + RB Full Interrupt Flag +1 - All RBs are full. If no RB will be released until the next valid message is received, +the oldest message will be lost. +0 - The RB FIFO is not full. + 5 + 1 + read-write + + + RAFIF + RB Almost Full Interrupt Flag +1 - number of filled RB slots >= AFWL_i +0 - number of filled RB slots < AFWL_i + 4 + 1 + read-write + + + TPIF + Transmission Primary Interrupt Flag +1 - The requested transmission of the PTB has been successfully completed. +0 - No transmission of the PTB has been completed. +In TTCAN mode, TPIF will never be set. Then only TSIF is valid. + 3 + 1 + read-write + + + TSIF + Transmission Secondary Interrupt Flag +1 - The requested transmission of the STB has been successfully completed. +0 - No transmission of the STB has been completed successfully. +In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of +the message. + 2 + 1 + read-write + + + EIF + Error Interrupt Flag +1 - The border of the error warning limit has been crossed in either direction, +or the BUSOFF bit has been changed in either direction. +0 - There has been no change. + 1 + 1 + read-write + + + AIF + Abort Interrupt Flag +1 - After setting TPA or TSA the appropriated message(s) have been aborted. +It is recommended to not set both TPA and TSA simultaneously because both +source AIF. +0 - No abort has been executed. +The AIF does not have an associated enable register. + 0 + 1 + read-write + + + + + ERRINT + ERRor INTerrupt Enable and Flag Register ERRINT + 0xa6 + 8 + 0x00 + 0xFF + + + EWARN + Error WARNing limit reached +1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. + 7 + 1 + read-only + + + EPASS + Error Passive mode active +0 - not active (node is error active) +1 - active (node is error passive) + 6 + 1 + read-only + + + EPIE + Error Passive Interrupt Enable + 5 + 1 + read-write + + + EPIF + Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error +active to error passive or vice versa and if this interrupt is enabled. + 4 + 1 + read-write + + + ALIE + Arbitration Lost Interrupt Enable + 3 + 1 + read-write + + + ALIF + Arbitration Lost Interrupt Flag + 2 + 1 + read-write + + + BEIE + Bus Error Interrupt Enable + 1 + 1 + read-write + + + BEIF + Bus Error Interrupt Flag + 0 + 1 + read-write + + + + + LIMIT + Warning Limits Register LIMIT + 0xa7 + 8 + 0x1B + 0xFF + + + AFWL + receive buffer Almost Full Warning Limit +AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. +AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . +AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) +AFWL_i > nRB is meaningless and automatically treated as nRB. +AFWL_i = nRB is a valid value, but note that RFIF also exists. + 4 + 4 + read-write + + + EWL + Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. +The value of EWL controls EIF. + 0 + 4 + read-write + + + + + S_PRESC + Bit Timing Register(Slow Speed) + 0xa8 + 32 + 0x01020203 + 0xFF7F7FFF + + + S_PRESC + Prescaler (slow speed) +The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + 24 + 8 + read-write + + + S_SJW + Synchronization Jump Width (slow speed) +The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + 16 + 7 + read-write + + + S_SEG_2 + Bit Timing Segment 2 (slow speed) +Time after the sample point. + 8 + 7 + read-write + + + S_SEG_1 + Bit Timing Segment 1 (slow speed) +The sample point will be set to after start of bit time. + 0 + 8 + read-write + + + + + F_PRESC + Bit Timing Register(Fast Speed) + 0xac + 32 + 0x01020203 + 0xFF0F0F0F + + + F_PRESC + Prescaler (fast speed) +The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + 24 + 8 + read-write + + + F_SJW + Synchronization Jump Width (fast speed) +The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + 16 + 4 + read-write + + + F_SEG_2 + Bit Timing Segment 2 (fast speed) +Time after the sample point + 8 + 4 + read-write + + + F_SEG_1 + Bit Timing Segment 1 (fast speed) +The sample point will be set to after start of bit time. + 0 + 4 + read-write + + + + + EALCAP + Error and Arbitration Lost Capture Register EALCAP + 0xb0 + 8 + 0x00 + 0xFF + + + KOER + Kind Of ERror (Error code) +000 - no error +001 - BIT ERROR +010 - FORM ERROR +011 - STUFF ERROR +100 - ACKNOWLEDGEMENT ERROR +101 - CRC ERROR +110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) +111 - not used +KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. + 5 + 3 + read-only + + + ALC + Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) + 0 + 5 + read-only + + + + + TDC + Transmitter Delay Compensation Register TDC + 0xb1 + 8 + 0x00 + 0xFF + + + TDCEN + Transmitter Delay Compensation ENable +TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. + 7 + 1 + read-write + + + SSPOFF + Secondary Sample Point OFFset +The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. +SSPOFF is given as a number of TQ. + 0 + 7 + read-write + + + + + RECNT + Error Counter Registers RECNT + 0xb2 + 8 + 0x00 + 0xFF + + + RECNT + Receive Error CouNT (number of errors during reception) +RECNT is incremented and decremented as defined in the CAN specification. +RECNT does not overflow. +If TXB=1, then the error counters are frozen. + 0 + 8 + read-only + + + + + TECNT + Error Counter Registers TECNT + 0xb3 + 8 + 0x00 + 0xFF + + + TECNT + Transmit Error CouNT (number of errors during transmission) +TECNT is incremented and decremented as defined in the CAN specification. +In case of the “bus off state” TECNT may overflow. +If TXB=1, then the error counters are frozen. + 0 + 8 + read-only + + + + + ACFCTRL + Acceptance Filter Control Register ACFCTRL + 0xb4 + 8 + 0x00 + 0x2F + + + SELMASK + SELect acceptance MASK +0 - Registers ACF_x point to acceptance code +1 - Registers ACF_x point to acceptance mask. +ACFADR selects one specific acceptance filter. + 5 + 1 + read-write + + + ACFADR + acceptance filter address +ACFADR points to a specific acceptance filter. +The selected filter is accessible using theregisters ACF_x. +Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. +A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. +ACF_NUMBER = 16. + 0 + 4 + read-write + + + + + TIMECFG + CiA 603 Time-Stamping TIMECFG + 0xb5 + 8 + 0x00 + 0x03 + + + TIMEPOS + TIME-stamping POSition +0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. + 1 + 1 + read-write + + + TIMEEN + TIME-stamping ENable +0 – disabled +1 – enabled + 0 + 1 + read-write + + + + + ACF_EN + Acceptance Filter Enable ACF_EN + 0xb6 + 16 + 0x0000 + 0xFFFF + + + ACF_EN + Acceptance filter Enable +1 - acceptance filter enabled +0 - acceptance filter disable +Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. +Disabled filters reject a message. Only enabled filters can accept a message if the +appropriate AMASK / ACODE configuration matches. + 0 + 16 + read-write + + + + + ACF + Acceptance CODE ACODE or ACMASK + 0xb8 + 32 + 0x00000000 + 0x7FFFFFFF + + + AIDEE + Acceptance mask IDE bit check enable +1 - acceptance filter accepts either standard or extended as defined by AIDE +0 - acceptance filter accepts both standard or extended frames +Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + 30 + 1 + read-write + + + AIDE + Acceptance mask IDE bit value +If AIDEE=1 then: +1 - acceptance filter accepts only extended frames +0 - acceptance filter accepts only standard frames +Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + 29 + 1 + read-write + + + CODE_MASK + Acceptance CODE +1 - ACC bit value to compare with ID bit of the received message +0 - ACC bit value to compare with ID bit of the received message +ACODE_x(10:0) will be used for extended frames. +ACODE_x(28:0) will be used for extended frames. +Only filter 0 is affected by the power-on reset. +Acceptance MASK(if SELMASK ==1 ) +1 - acceptance check for these bits of receive identifier disabled +0 - acceptance check for these bits of receive identifier enable +AMASK_x(10:0) will be used for extended frames. +AMASK_x(28:0) will be used for extended frames. +Disabled bits result in accepting the message. Therefore the default configuration after +reset for filter 0 accepts all messages. +Only filter 0 is affected by the power-on reset. + 0 + 29 + read-write + + + + + VER + Version Information VER + 0xbc + 16 + 0x0000 + 0xFFFF + + + VERSION + Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and +VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 + 0 + 16 + read-write + + + + + TBSLOT + TTCAN: TB Slot Pointer TBSLOT + 0xbe + 8 + 0x00 + 0xFF + + + TBE + set TB slot to “Empty” +1 - slot selected by TBPTR shall be marked as “empty” +0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. +If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the + transmissionis not active any more. +If both TBF and TBE are set, then TBE wins + 7 + 1 + read-write + + + TBF + set TB slot to “Filled” +1 - slot selected by TBPTR shall be marked as “filled” +0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. +If both TBF and TBE are set, then TBE wins. + 6 + 1 + read-write + + + TBPTR + Pointer to a TB message slot. +0x00 - Pointer to the PTB +others - Pointer to a slot in the STB +The message slot pointed to by TBPTR is readable / writable using the TBUF registers. +Write access is only possible if TSFF=0. +Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. +TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. +TBPTR can only point to buffer slots, that exist in the hardware. +Unusable bits ofTBPTR are fixed to 0. +TBPTR is limited to the PTB and 63 STB slots. + More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. + 0 + 6 + read-write + + + + + TTCFG + TTCAN: Time Trigger Configuration TTCFG + 0xbf + 8 + 0x00 + 0xFF + + + WTIE + Watch Trigger Interrupt Enable + 7 + 1 + read-write + + + WTIF + Watch Trigger Interrupt Flag +WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. + 6 + 1 + read-write + + + TEIF + Trigger Error Interrupt Flag +The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF + 5 + 1 + read-write + + + TTIE + Time Trigger Interrupt Enable +If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. + 4 + 1 + read-write + + + TTIF + Time Trigger Interrupt Flag +TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. +Writing an one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. +If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. + 3 + 1 + read-write + + + T_PRESC + TTCAN Timer PRESCaler +00b - 1 +01b - 2 +10b - 4 +11b - 8 +The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. +T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. + 1 + 2 + read-write + + + TTEN + Time Trigger Enable +1 - TTCAN enabled, timer is running0 - disabled + 0 + 1 + read-write + + + + + REF_MSG + TTCAN: Reference Message REF_MSG + 0xc0 + 32 + 0x00000000 + 0x9FFFFFFF + + + REF_IDE + REFerence message IDE bit. + 31 + 1 + read-write + + + REF_MSG + REFerence message IDentifier. +If REF_IDE is +1 - REF_ID(28:0) is valid (extended ID) +0 - REF_ID(10:0) is valid (standard ID) +REF_ID is used in TTCAN mode to detect a reference message. This holds for time +slaves (reception) as well as for the time master (transmission). If the reference +message is detected and there are no errors, then the Sync_Mark of this frame will +become the Ref_Mark. +REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. +These bits are used for up to 8 potential time masters. +CAN-CTRL recognizes the reference message only by ID. The payload is not tested. +Additional note: A time master will transmit a reference message in the same way as a +normal frame. REF_ID is intended for detection of a successful transmission of a +reference message. + 0 + 29 + read-write + + + + + TRIG_CFG + TTCAN: Trigger Configuration TRIG_CFG + 0xc4 + 16 + 0x0000 + 0xF73F + + + TEW + Transmit Enable Window +For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time +where the frame is allowed to start. TWE+1 defines the number of ticks. +TEW=0 is a valid setting and shortens the transmit enable window to 1 tick + 12 + 4 + read-write + + + TTYPE + Trigger Type +000b - Immediate Trigger for immediate transmission +001b - Time Trigger for receive triggers +010b - Single Shot Transmit Trigger for exclusive time windows +011b - Transmit Start Trigger for merged arbitrating time windows +100b - Transmit Stop Trigger for merged arbitrating time windows +others - no action +The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the +transmit triggers. See Chapter 6.4 for more details. + 8 + 3 + read-write + + + TTPTR + Transmit Trigger TB slot Pointer +If TTPTR is too big and points to a slot that is not available, then TEIF is set and no +new trigger can be activated after a write access to TT_TRIG_1. +If TTPTR points to an empty slot, then TEIF will be set at the moment, when the +trigger time is reached. + 0 + 6 + read-write + + + + + TT_TRIG + TTCAN: Trigger Time TT_TRIG + 0xc6 + 16 + 0x0000 + 0xFFFF + + + TT_TRIG + Trigger Time +TT_TRIG(15:0) defines the cycle time for a trigger. +For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. + 0 + 16 + read-write + + + + + TT_WTRIG + TTCAN: Watch Trigger Time TT_WTRIG + 0xc8 + 16 + 0x0000 + 0xFFFF + + + TT_WTRIG + Watch Trigger Time +TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. + 0 + 16 + read-write + + + + + + + CAN1 + CAN1 + CAN + 0xf0084000 + + + CAN2 + CAN2 + CAN + 0xf0088000 + + + CAN3 + CAN3 + CAN + 0xf008c000 + + + WDG0 + WDG0 + WDOG + 0xf0090000 + + 0x10 + 0x10 + registers + + + + CTRL + Control Register + 0x10 + 32 + 0x00000000 + 0x000007FF + + + RSTTIME + The time interval of the reset stage: +0: Clock period x 2^7 +1: Clock period x 2^8 +2: Clock period x 2^9 +3: Clock period x 2^10 +4: Clock period x 2^11 +5: Clock period x 2^12 +6: Clock period x 2^13 +7: Clock period x 2^14 + 8 + 3 + read-write + + + INTTIME + The timer interval of the interrupt stage: +0: Clock period x 2^6 +1: Clock period x 2^8 +2: Clock period x 2^10 +3: Clock period x 2^11 +4: Clock period x 2^12 +5: Clock period x 2^13 +6: Clock period x 2^14 +7: Clock period x 2^15 +8: Clock period x 2^17 +9: Clock period x 2^19 +10: Clock period x 2^21 +11: Clock period x 2^23 +12: Clock period x 2^25 +13: Clock period x 2^27 +14: Clock period x 2^29 +15: Clock period x 2^31 + 4 + 4 + read-write + + + RSTEN + Enable or disable the watchdog reset +0: Disable +1: Enable + 3 + 1 + read-write + + + INTEN + Enable or disable the watchdog interrupt +0: Disable +1: Enable + 2 + 1 + read-write + + + CLKSEL + Clock source of timer: +0: EXTCLK +1: PCLK + 1 + 1 + read-write + + + EN + Enable or disable the watchdog timer +0: Disable +1: Enable + 0 + 1 + read-write + + + + + RESTART + Restart Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + RESTART + Write the magic number +ATCWDT200_RESTART_NUM to restart the +watchdog timer. + 0 + 16 + write-only + + + + + WREN + Write Protection Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + WEN + Write the magic code to disable the write +protection of the Control Register and the +Restart Register. + 0 + 16 + write-only + + + + + ST + Status Register + 0x1c + 32 + 0x00000000 + 0x00000001 + + + INTEXPIRED + The status of the watchdog interrupt timer +0: timer is not expired yet +1: timer is expired + 0 + 1 + read-write + + + + + + + WDG1 + WDG1 + WDOG + 0xf0094000 + + + WDG2 + WDG2 + WDOG + 0xf0098000 + + + WDG3 + WDG3 + WDOG + 0xf009c000 + + + PWDG + PWDG + WDOG + 0xf40e8000 + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x24 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + RESERVED + Reserved + 16 + 15 + read-only + + + BARCTL + Bus Acccess Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + RESERVED + Reserved + 9 + 5 + read-only + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + RESERVED + Reserved + 2 + 2 + read-only + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RESERVED + Not used + 24 + 8 + read-only + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + read-write + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + read-write + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + read-write + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + read-write + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + read-write + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + read-write + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + RESERVED + Not used + 2 + 2 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + TXWRD_TXFIFO0 + TXFIFO for sending message to other core + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + RXWRD_RXFIFO0 + RXFIFO for receiving message from other core + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + MBX1A + MBX1A + MBX + 0xf00a8000 + + + MBX1B + MBX1B + MBX + 0xf00ac000 + + + PTPC + PTPC + PTPC + 0xf00b0000 + + 0x0 + 0x200c + registers + + + + PTPC_0_CTRL0 + Control Register 0 + 0x0 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description avaiable + 6 + 1 + read-write + + + RESERVED + No description avaiable + 5 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow +1: coarse update, ns counter add ss_incr[7:0] each clk + 1 + 1 + read-write + + + TIMER_ENABLE + No description avaiable + 0 + 1 + read-write + + + + + PTPC_0_CTRL1 + Control Register 1 + 0x4 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + PTPC_0_TIMEH + timestamp high + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description avaiable + 0 + 32 + read-only + + + + + PTPC_0_TIMEL + timestamp low + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description avaiable + 0 + 32 + read-only + + + + + PTPC_0_TS_UPDTH + timestamp update high + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + PTPC_0_TS_UPDTL + timestamp update low + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description avaiable + 0 + 31 + read-write + + + + + PTPC_0_ADDEND + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + PTPC_0_TARH + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + PTPC_0_TARL + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description avaiable + 0 + 32 + read-write + + + + + PTPC_0_PPS_CTRL + No description avaiable + 0x2c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description avaiable + 0 + 4 + read-write + + + + + PTPC_0_CAPT_SNAPH + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + PTPC_0_CAPT_SNAPL + No description avaiable + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description avaiable + 0 + 32 + read-write + + + + + PTPC_1_CTRL0 + Control Register 0 + 0x1000 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description avaiable + 6 + 1 + read-write + + + RESERVED + No description avaiable + 5 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow +1: coarse update, ns counter add ss_incr[7:0] each clk + 1 + 1 + read-write + + + TIMER_ENABLE + No description avaiable + 0 + 1 + read-write + + + + + PTPC_1_CTRL1 + Control Register 1 + 0x1004 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + PTPC_1_TIMEH + timestamp high + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description avaiable + 0 + 32 + read-only + + + + + PTPC_1_TIMEL + timestamp low + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description avaiable + 0 + 32 + read-only + + + + + PTPC_1_TS_UPDTH + timestamp update high + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + PTPC_1_TS_UPDTL + timestamp update low + 0x1014 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description avaiable + 0 + 31 + read-write + + + + + PTPC_1_ADDEND + No description avaiable + 0x1018 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + PTPC_1_TARH + No description avaiable + 0x101c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + PTPC_1_TARL + No description avaiable + 0x1020 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description avaiable + 0 + 32 + read-write + + + + + PTPC_1_PPS_CTRL + No description avaiable + 0x102c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description avaiable + 0 + 4 + read-write + + + + + PTPC_1_CAPT_SNAPH + No description avaiable + 0x1030 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + PTPC_1_CAPT_SNAPL + No description avaiable + 0x1034 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description avaiable + 0 + 32 + read-write + + + + + TIME_SEL + No description avaiable + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + CAN3_TIME_SEL + No description avaiable + 3 + 1 + read-write + + + CAN2_TIME_SEL + No description avaiable + 2 + 1 + read-write + + + CAN1_TIME_SEL + No description avaiable + 1 + 1 + read-write + + + CAN0_TIME_SEL + set to use ptpc1 for canx +clr to use ptpc0 for canx + 0 + 1 + read-write + + + + + INT_STS + No description avaiable + 0x2004 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description avaiable + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description avaiable + 17 + 1 + read-write + + + PPS_INT_STS1 + No description avaiable + 16 + 1 + read-write + + + COMP_INT_STS0 + No description avaiable + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description avaiable + 1 + 1 + read-write + + + PPS_INT_STS0 + No description avaiable + 0 + 1 + read-write + + + + + INT_EN + No description avaiable + 0x2008 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description avaiable + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description avaiable + 17 + 1 + read-write + + + PPS_INT_STS1 + No description avaiable + 16 + 1 + read-write + + + COMP_INT_STS0 + No description avaiable + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description avaiable + 1 + 1 + read-write + + + PPS_INT_STS0 + No description avaiable + 0 + 1 + read-write + + + + + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c0000 + + 0x0 + 0x40 + registers + + + + MUXCFG_HDMA_MUX0 + HDMA MUX0 Configuration + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX1 + HDMA MUX1 Configuration + 0x4 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX2 + HDMA MUX2 Configuration + 0x8 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX3 + HDMA MUX3 Configuration + 0xc + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX4 + HDMA MUX4 Configuration + 0x10 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX5 + HDMA MUX5 Configuration + 0x14 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX6 + HDMA MUX6 Configuration + 0x18 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX7 + HDMA MUX7 Configuration + 0x1c + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX0 + XDMA MUX0 Configuration + 0x20 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX1 + XDMA MUX1 Configuration + 0x24 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX2 + XDMA MUX2 Configuration + 0x28 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX3 + XDMA MUX3 Configuration + 0x2c + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX4 + XDMA MUX4 Configuration + 0x30 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX5 + XDMA MUX5 Configuration + 0x34 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX6 + XDMA MUX6 Configuration + 0x38 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX7 + XDMA MUX7 Configuration + 0x3c + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + + + HDMA + HDMA + DMA + 0xf00c4000 + + 0x10 + 0x15c + registers + + + + DMACFG + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACTRL + DMAC Control Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + CHABORT + Channel Abort Register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + INTSTATUS + Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0x00FFFFFF + + + TC + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 16 + 8 + read-write + + + ABORT + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 8 + 8 + read-write + + + ERROR + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 8 + read-write + + + + + CHEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + CHCTRL_CH0_CTRL + Channel n Control Register + 0x40 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH0_TRANSIZE + Channel n Transfer Size Register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH0_SRCADDR + Channel n Source Address Low Part Register + 0x48 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH0_SRCADDRH + Channel n Source Address High Part Register + 0x4c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH0_DSTADDR + Channel n Destination Address Low Part Register + 0x50 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH0_DSTADDRH + Channel n Destination Address High Part Register + 0x54 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH0_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x58 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH0_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH1_CTRL + Channel n Control Register + 0x60 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH1_TRANSIZE + Channel n Transfer Size Register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH1_SRCADDR + Channel n Source Address Low Part Register + 0x68 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH1_SRCADDRH + Channel n Source Address High Part Register + 0x6c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH1_DSTADDR + Channel n Destination Address Low Part Register + 0x70 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH1_DSTADDRH + Channel n Destination Address High Part Register + 0x74 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH1_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x78 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH1_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH2_CTRL + Channel n Control Register + 0x80 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH2_TRANSIZE + Channel n Transfer Size Register + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH2_SRCADDR + Channel n Source Address Low Part Register + 0x88 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH2_SRCADDRH + Channel n Source Address High Part Register + 0x8c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH2_DSTADDR + Channel n Destination Address Low Part Register + 0x90 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH2_DSTADDRH + Channel n Destination Address High Part Register + 0x94 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH2_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x98 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH2_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH3_CTRL + Channel n Control Register + 0xa0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH3_TRANSIZE + Channel n Transfer Size Register + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH3_SRCADDR + Channel n Source Address Low Part Register + 0xa8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH3_SRCADDRH + Channel n Source Address High Part Register + 0xac + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH3_DSTADDR + Channel n Destination Address Low Part Register + 0xb0 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH3_DSTADDRH + Channel n Destination Address High Part Register + 0xb4 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH3_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0xb8 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH3_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH4_CTRL + Channel n Control Register + 0xc0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH4_TRANSIZE + Channel n Transfer Size Register + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH4_SRCADDR + Channel n Source Address Low Part Register + 0xc8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH4_SRCADDRH + Channel n Source Address High Part Register + 0xcc + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH4_DSTADDR + Channel n Destination Address Low Part Register + 0xd0 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH4_DSTADDRH + Channel n Destination Address High Part Register + 0xd4 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH4_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0xd8 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH4_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH5_CTRL + Channel n Control Register + 0xe0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH5_TRANSIZE + Channel n Transfer Size Register + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH5_SRCADDR + Channel n Source Address Low Part Register + 0xe8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH5_SRCADDRH + Channel n Source Address High Part Register + 0xec + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH5_DSTADDR + Channel n Destination Address Low Part Register + 0xf0 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH5_DSTADDRH + Channel n Destination Address High Part Register + 0xf4 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH5_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0xf8 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH5_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH6_CTRL + Channel n Control Register + 0x100 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH6_TRANSIZE + Channel n Transfer Size Register + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH6_SRCADDR + Channel n Source Address Low Part Register + 0x108 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH6_SRCADDRH + Channel n Source Address High Part Register + 0x10c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH6_DSTADDR + Channel n Destination Address Low Part Register + 0x110 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH6_DSTADDRH + Channel n Destination Address High Part Register + 0x114 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH6_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x118 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH6_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH7_CTRL + Channel n Control Register + 0x120 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH7_TRANSIZE + Channel n Transfer Size Register + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH7_SRCADDR + Channel n Source Address Low Part Register + 0x128 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH7_SRCADDRH + Channel n Source Address High Part Register + 0x12c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH7_DSTADDR + Channel n Destination Address Low Part Register + 0x130 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH7_DSTADDRH + Channel n Destination Address High Part Register + 0x134 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH7_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x138 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH7_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + + + XDMA + XDMA + DMA + 0xf3048000 + + + RNG + RNG + RNG + 0xf00c8000 + + 0x0 + 0x40 + registers + + + + CMD + Command Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 7 + 25 + read-write + + + SFTRST + Soft Reset, Perform a software reset of the RNG This bit is self-clearing. +0 Do not perform a software reset. +1 Software reset + 6 + 1 + read-write + + + CLRERR + Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. +0 Do not clear the errors and the interrupt. +1 Clear the errors and the interrupt. + 5 + 1 + read-write + + + CLRINT + Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. +0 Do not clear the interrupt. +1 Clear the interrupt + 4 + 1 + read-write + + + RESERVED + Not used + 2 + 2 + read-only + + + GENSD + Generate Seed, when both ST and GS triggered, ST first and GS next. + 1 + 1 + read-write + + + SLFCHK + Self Test, when both ST and GS triggered, ST first and GS next. + 0 + 1 + read-write + + + + + CTRL + Control Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 7 + 25 + read-only + + + MIRQERR + Mask Interrupt Request for Error + 6 + 1 + read-write + + + MIRQDN + Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: +• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). +• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + 5 + 1 + read-write + + + AUTRSD + Auto Reseed + 4 + 1 + read-write + + + RESERVED + Not used + 2 + 2 + read-only + + + FUFMOD + FIFO underflow response mode +00 Return all zeros and set the ESR[FUFE]. +01 Return all zeros and set the ESR[FUFE]. +10 Generate the bus transfer error +11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + 0 + 2 + read-write + + + + + STA + Status Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 24 + 8 + read-only + + + SCPF + Self Check Pass Fail + 21 + 3 + read-only + + + RESERVED + Not used + 17 + 4 + read-only + + + FUNCERR + Error was detected, check ESR register for details + 16 + 1 + read-only + + + FSIZE + Fifo Size, it is 5 in this design. + 12 + 4 + read-only + + + FRNNU + Fifo Level, Indicates the number of random words currently in the output FIFO + 8 + 4 + read-only + + + RESERVED + Not used + 7 + 1 + read-only + + + NSDDN + New seed done. + 6 + 1 + read-only + + + FSDDN + 1st Seed done +When "1", Indicates that the RNG generated the first seed. + 5 + 1 + read-only + + + SCDN + Self Check Done +Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is +initiated by setting the CMD[ST]. +0 Self test not completed +1 Completed a self test since the last reset. + 4 + 1 + read-only + + + RSDREQ + Reseed needed +Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or +automatically if the CTRL[ARS] is set. + 3 + 1 + read-only + + + IDLE + Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + 2 + 1 + read-only + + + BUSY + when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + 1 + 1 + read-only + + + RESERVED + Not used + 0 + 1 + read-only + + + + + ERR + Error Registers + 0xc + 32 + 0x00000000 + 0xFFFFFF3F + + + RESERVED + OSC1 Satistics test pass failed. +Indicates the pass or fail status of the various statistics tests on the last seed generated. +0 Pass +1 Fail + 24 + 8 + read-only + + + RESERVED + OSC0 Satistics test pass failed. +Indicates the pass or fail status of the various statistics tests on the last seed generated. +0 Pass +1 Fail + 16 + 8 + read-only + + + RESERVED + Not used + 8 + 8 + read-only + + + FUFE + FIFO access error(underflow) + 5 + 1 + read-only + + + RESERVED + Statistical test error +Indicates whether the statistical tests for the last generated seed was failed or not. This bit is sticky and is +cleared by a hardware or software reset or by writing 1 to the CMD[CE]. +0 No fail for the statistical tests. +1 Failed the statistical tests during the initialization + 4 + 1 + read-only + + + SCKERR + Self-test error +Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a +hardware reset or by writing 1 to the CMD[CE] + 3 + 1 + read-only + + + RESERVED + Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a +software or hardware reset. + 2 + 1 + read-only + + + RESERVED + Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a +software or hardware reset. + 1 + 1 + read-only + + + RESERVED + Linear feedback shift register (LFSR) error +When this bit is set, the interrupt generated was caused by a failure of one of the LFSRs in any of the RNG LFSR ciruit. + 0 + 1 + read-only + + + + + FO2B + FIFO out to bus/cpu + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2B + SW read the FIFO output. + 0 + 32 + read-only + + + + + R2SK_FO2S0 + FIFO out to SDP as AES engine key + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S1 + FIFO out to SDP as AES engine key + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S2 + FIFO out to SDP as AES engine key + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S3 + FIFO out to SDP as AES engine key + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S4 + FIFO out to SDP as AES engine key + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S5 + FIFO out to SDP as AES engine key + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S6 + FIFO out to SDP as AES engine key + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S7 + FIFO out to SDP as AES engine key + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + + + KEYM + KEYM + KEYM + 0xf00cc000 + + 0x0 + 0x50 + registers + + + + SOFTMKEY_SFK0 + software set symmetric key + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK1 + software set symmetric key + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK2 + software set symmetric key + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK3 + software set symmetric key + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK4 + software set symmetric key + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK5 + software set symmetric key + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK6 + software set symmetric key + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK7 + software set symmetric key + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK0 + system asymmetric key + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK1 + system asymmetric key + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK2 + system asymmetric key + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK3 + system asymmetric key + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK4 + system asymmetric key + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK5 + system asymmetric key + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK6 + system asymmetric key + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK7 + system asymmetric key + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of followings +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of followings +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + I2S0 + I2S0 + I2S + 0xf0100000 + + 0x0 + 0x80 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 19 + 13 + read-write + + + SFTRST_RX + software reset the RX module if asserted to be 1'b1. Self-clear. + 18 + 1 + read-write + + + SFTRST_TX + software reset the TX module if asserted to be 1'b1. Self-clear. + 17 + 1 + read-write + + + SFTRST_CLKGEN + software reset the CLK GEN module if asserted to be 1'b1. Self-clear. + 16 + 1 + read-write + + + TXDNIE + TX buffer data needed interrupt enable +0: TXE interrupt masked +1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 15 + 1 + read-write + + + RXDAIE + RX buffer data available interrupt enable +0: RXNE interrupt masked +1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 14 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 13 + 1 + read-write + + + TX_DMA_EN + Asserted to use DMA, else to use interrupt + 12 + 1 + read-write + + + RX_DMA_EN + Asserted to use DMA, else to use interrupt + 11 + 1 + read-write + + + TXFIFOCLR + Self-clear + 10 + 1 + read-write + + + RXFIFOCLR + Self-clear + 9 + 1 + read-write + + + TX_EN + enable for each TX data pad + 5 + 4 + read-write + + + RX_EN + enable for each RX data pad + 1 + 4 + read-write + + + I2S_EN + enable for the module + 0 + 1 + read-write + + + + + RFIFO_FILLINGS + Rx FIFO Filling Level + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RX3 + RX3 fifo fillings + 24 + 8 + read-only + + + RX2 + RX2 fifo fillings + 16 + 8 + read-only + + + RX1 + RX1 fifo fillings + 8 + 8 + read-only + + + RX0 + RX0 fifo fillings + 0 + 8 + read-only + + + + + TFIFO_FILLINGS + Tx FIFO Filling Level + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TX3 + TX3 fifo fillings + 24 + 8 + read-only + + + TX2 + TX2 fifo fillings + 16 + 8 + read-only + + + TX1 + TX1 fifo fillings + 8 + 8 + read-only + + + TX0 + TX0 fifo fillings + 0 + 8 + read-only + + + + + FIFO_THRESH + TX/RX FIFO Threshold setting. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 16 + 16 + read-write + + + TX + TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. + 8 + 8 + read-write + + + RX + RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. + 0 + 8 + read-write + + + + + STA + Status Registers + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 17 + 15 + read-only + + + TX_UD + Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. + 13 + 4 + read-write + + + RX_OV + Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. + 9 + 4 + read-write + + + TX_DN + Asserted when tx fifo data are needed. + 5 + 4 + read-only + + + RX_DA + Asserted when rx fifo data are available. + 1 + 4 + read-only + + + RSV + Reserved + 0 + 1 + read-only + + + + + RXD_DATA0 + Rx Data0 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + read-only + + + + + RXD_DATA1 + Rx Data1 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + read-only + + + + + RXD_DATA2 + Rx Data2 + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + read-only + + + + + RXD_DATA3 + Rx Data3 + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + read-only + + + + + TXD_DATA0 + Tx Data0 + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + write-only + + + + + TXD_DATA1 + Tx Data1 + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + write-only + + + + + TXD_DATA2 + Tx Data2 + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + write-only + + + + + TXD_DATA3 + Tx Data3 + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + D + No description avaiable + 0 + 32 + write-only + + + + + CFGR + Configruation Regsiters + 0x50 + 32 + 0x40000000 + 0xFFFFFFFF + + + RSV + Reserved + 31 + 1 + read-write + + + BCLK_GATEOFF + Gate off the bclk. Asserted to gate-off the BCLK. + 30 + 1 + read-write + + + BCLK_DIV + Linear prescaler to generate BCLK from MCLK. +BCLK_DIV [8:0] = 0: BCLK=No CLK. +BCLK_DIV [8:0] = 1: BCLK=MCLK/1 +BCLK_DIV [8:0] = n: BCLK=MCLK/(n). +Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 21 + 9 + read-write + + + INV_BCLK_OUT + Invert the BCLK before sending it out to pad. Only valid in BCLK master mode + 20 + 1 + read-write + + + INV_BCLK_IN + Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode + 19 + 1 + read-write + + + INV_FCLK_OUT + Invert the FCLK before sending it out to pad. Only valid in FCLK master mode + 18 + 1 + read-write + + + INV_FCLK_IN + Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode + 17 + 1 + read-write + + + INV_MCLK_OUT + Invert the MCLK before sending it out to pad. Only valid in MCLK master mode + 16 + 1 + read-write + + + INV_MCLK_IN + Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode + 15 + 1 + read-write + + + BCLK_SEL_OP + asserted to use external clk source + 14 + 1 + read-write + + + FCLK_SEL_OP + asserted to use external clk source + 13 + 1 + read-write + + + MCK_SEL_OP + asserted to use external clk source + 12 + 1 + read-write + + + FRAME_EDGE + The start edge of a frame +0: Falling edge indicates a new frame (Just like standard I2S Philips standard) +1: Rising edge indicates a new frame + 11 + 1 + read-write + + + CH_MAX + CH_MAX[3:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +4'h2: 2 channels +4'h4: 4 channels +... + 6 + 5 + read-write + + + TDM_EN + TDM mode +0: not TDM mode +1: TDM mode + 5 + 1 + read-write + + + STD + I2S standard selection +00: I2S Philips standard. +01: MSB justified standard (left justified) +10: LSB justified standard (right justified) +11: PCM standard +Note: For correct operation, these bits should be configured when the I2S is disabled. + 3 + 2 + read-write + + + DATSIZ + Data length to be transferred +00: 16-bit data length +01: 24-bit data length +10: 32-bit data length +11: Not allowed +Note: For correct operation, these bits should be configured when the I2S is disabled. + 1 + 2 + read-write + + + CHSIZ + Channel length (number of bits per audio channel) +0: 16-bit wide +1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. +Note: For correct operation, this bit should be configured when the I2S is disabled. + 0 + 1 + read-write + + + + + MISC_CFGR + Misc configuration Registers + 0x58 + 32 + 0x00042000 + 0xFFFFEC01 + + + RSV + Reserved + 14 + 18 + read-write + + + MCLK_GATEOFF + Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. + 13 + 1 + read-write + + + RSV + Reserved + 11 + 1 + read-write + + + RSV + Reserved + 10 + 1 + read-write + + + MCLKOE + Master clock output to pad enable +0: Master clock output is disabled +1: Master clock output is enabled +Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + 0 + 1 + read-write + + + + + RXDSLOT_DATA0 + Rx Slots Enable for Rx Data0 + 0x60 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + RXDSLOT_DATA1 + Rx Slots Enable for Rx Data1 + 0x64 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + RXDSLOT_DATA2 + Rx Slots Enable for Rx Data2 + 0x68 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + RXDSLOT_DATA3 + Rx Slots Enable for Rx Data3 + 0x6c + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + TXDSLOT_DATA0 + Tx Slots Enable for Tx Data0. + 0x70 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + TXDSLOT_DATA1 + Tx Slots Enable for Tx Data1. + 0x74 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + TXDSLOT_DATA2 + Tx Slots Enable for Tx Data2. + 0x78 + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + TXDSLOT_DATA3 + Tx Slots Enable for Tx Data3. + 0x7c + 32 + 0x0000FFFF + 0xFFFFFFFF + + + EN + No description avaiable + 0 + 32 + read-write + + + + + + + I2S1 + I2S1 + I2S + 0xf0104000 + + + I2S2 + I2S2 + I2S + 0xf0108000 + + + I2S3 + I2S3 + I2S + 0xf010c000 + + + DAO + DAO + DAO + 0xf0110000 + + 0x0 + 0x1c + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x000300FF + + + HPF_EN + Whether HPF is enabled. This HPF is used to filter out the DC part. + 17 + 1 + read-write + + + SAT_ERR_IE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (saturation) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 16 + 1 + read-write + + + MONO + Asserted to let the left and right channel output the same value. + 7 + 1 + read-write + + + RIGHT_EN + Asserted to enable the right channel + 6 + 1 + read-write + + + LEFT_EN + Asserted to enable the left channel + 5 + 1 + read-write + + + REMAP + 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative +0: Don't use remap pwm version + 4 + 1 + read-write + + + INVERT + all the outputs are inverted before sending to pad + 3 + 1 + read-write + + + FALSE_LEVEL + the pad output in False run mode, or when the module is disabled +0: all low +1: all high +2: P-high, N-low +3. output is not enabled + 1 + 2 + read-write + + + FALSE_RUN + the module continues to comsume data, but all the pads are constant, thus no audio out + 0 + 1 + read-write + + + + + CMD + Command Register + 0x8 + 32 + 0x00000000 + 0x00000003 + + + SFTRST + Self-clear + 1 + 1 + read-write + + + RUN + Enable this module to run. + 0 + 1 + read-write + + + + + RX_CFGR + Configuration Register + 0xc + 32 + 0x00000000 + 0x000007C0 + + + CH_MAX + CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. +It must be an even number, so CH_MAX[0] is always 0. +4'h2: 2 channels +4'h4: 4 channels +etc + 6 + 5 + read-write + + + + + RXSLT + RX Slot Control Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + EN + Slot enable for the channels. + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + PDM + PDM + PDM + 0xf0114000 + + 0x0 + 0x34 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x809FF7FF + + + SFTRST + software reset the module. Self-clear. + 31 + 1 + read-write + + + SOF_FEDGE + asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. + 23 + 1 + read-write + + + USE_COEF_RAM + Asserted to use Coef RAM instead of Coef ROM + 20 + 1 + read-write + + + FILT_CRX_ERR_IE + data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. + 19 + 1 + read-write + + + OFIFO_OVFL_ERR_IE + output fifo overflow error interrupt enable + 18 + 1 + read-write + + + CIC_OVLD_ERR_IE + CIC overload error interrupt enable + 17 + 1 + read-write + + + CIC_SAT_ERR_IE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. +0: Error interrupt is masked +1: Error interrupt is enabled + 16 + 1 + read-write + + + DEC_AFT_CIC + decimation rate after CIC. Now it is forced to be 3. + 12 + 4 + read-write + + + CAPT_DLY + Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + 7 + 4 + read-write + + + PDM_CLK_HFDIV + The clock divider will work at least 4. +0: div-by-2, +1: div-by-4 +. . . +n: div-by-2*(n+1) + 3 + 4 + read-write + + + PDM_CLK_DIV_BYPASS + asserted to bypass the pdm clock divider + 2 + 1 + read-write + + + PDM_CLK_OE + pdm_clk_output_en + 1 + 1 + read-write + + + HPF_EN + pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. + 0 + 1 + read-write + + + + + CH_CTRL + Channel Control Register + 0x4 + 32 + 0x00000000 + 0x00FF03FF + + + CH_POL + Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + 16 + 8 + read-write + + + CH_EN + Asserted to enable the channel. +Ch8 & 9 are refs. +Ch0-7 are pdm mics. + 0 + 10 + read-write + + + + + ST + Status Register + 0x8 + 32 + 0x00000000 + 0x0000000F + + + FILT_CRX_ERR + data accessed out of boundary error + 3 + 1 + read-write + + + OFIFO_OVFL_ERR + output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. + 2 + 1 + read-write + + + CIC_OVLD_ERR + CIC overload error. write 1 clear + 1 + 1 + read-write + + + CIC_SAT_ERR + CIC saturation. Write 1 clear + 0 + 1 + read-write + + + + + CH_CFG + Channel Configuration Register + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + CH9_TYPE + No description avaiable + 18 + 2 + read-write + + + CH8_TYPE + No description avaiable + 16 + 2 + read-write + + + CH7_TYPE + No description avaiable + 14 + 2 + read-write + + + CH6_TYPE + No description avaiable + 12 + 2 + read-write + + + CH5_TYPE + No description avaiable + 10 + 2 + read-write + + + CH4_TYPE + No description avaiable + 8 + 2 + read-write + + + CH3_TYPE + No description avaiable + 6 + 2 + read-write + + + CH2_TYPE + No description avaiable + 4 + 2 + read-write + + + CH1_TYPE + No description avaiable + 2 + 2 + read-write + + + CH0_TYPE + Type of Channel 0 +2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) +2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) + 0 + 2 + read-write + + + + + CIC_CFG + CIC configuration register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + POST_SCALE + the shift value after CIC results. + 10 + 6 + read-write + + + SGD + Sigma_delta_order[1:0] +2'b00: 7 +2'b01: 6 +2'b10: 5 +Others: unused + 8 + 2 + read-write + + + CIC_DEC_RATIO + CIC decimation factor + 0 + 8 + read-write + + + + + CTRL_INBUF + In Buf Control Register + 0x14 + 32 + 0x00000000 + 0x3FFFFFFF + + + MAX_PTR + The buf size-1 for each channel + 22 + 8 + read-write + + + PITCH + The spacing between starting address of adjacent channels + 11 + 11 + read-write + + + START_ADDR + The starting address of channel 0 in filter data buffer + 0 + 11 + read-write + + + + + CTRL_FILT0 + Filter 0 Control Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M0 + Coef length of filter type 2'b00 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b00 in coef memory + 0 + 8 + read-write + + + + + CTRL_FILT1 + Filter 1 Control Register + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + COEF_LEN_M1 + Coef length of filter type 2'b01 in coef memory + 8 + 8 + read-write + + + COEF_START_ADDR + Starting address of Coef of filter type 2'b01 in coef memory + 0 + 8 + read-write + + + + + RUN + Run Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + PDM_EN + Asserted to enable the module + 0 + 1 + read-write + + + + + MEMADDR + Memory Access Address + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + 0--0x0FFFFFFF: COEF_RAM +0x10000000--0x1FFFFFFF: DATA_RAM + 0 + 32 + read-write + + + + + MEMDATA + Memory Access Data + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + The data write-to/read-from buffer + 0 + 32 + read-write + + + + + HPF_MA + HPF A Coef Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + Composite value of coef A of the Order-1 HPF + 0 + 32 + read-write + + + + + HPF_B + HPF B Coef Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COEF + coef B of the Order-1 HPF + 0 + 32 + read-write + + + + + + + PWM0 + PWM0 + PWM + 0xf0200000 + + 0x0 + 0x290 + registers + + + + UNLK + Shadow registers unlock register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHUNLK + write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written. + 0 + 32 + read-write + + + + + STA + Counter start register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + XSTA + pwm timer counter extended start point, should back to this value after reach xrld + 28 + 4 + read-write + + + STA + pwm timer counter start value + sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk + 4 + 24 + read-write + + + RESERVED + reserved + 0 + 4 + read-write + + + + + RLD + Counter reload register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + XRLD + timeout counter extended reload point, counter will reload to xsta after reach this point + 28 + 4 + read-write + + + RLD + pwm timer counter reload value + 4 + 24 + read-write + + + RESERVED + reserved + 0 + 4 + read-write + + + + + CMP_0 + Comparator register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_1 + Comparator register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_2 + Comparator register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_3 + Comparator register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_4 + Comparator register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_5 + Comparator register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_6 + Comparator register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_7 + Comparator register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_8 + Comparator register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_9 + Comparator register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_10 + Comparator register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_11 + Comparator register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_12 + Comparator register + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_13 + Comparator register + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_14 + Comparator register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_15 + Comparator register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_16 + Comparator register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_17 + Comparator register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_18 + Comparator register + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_19 + Comparator register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_20 + Comparator register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_21 + Comparator register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_22 + Comparator register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_23 + Comparator register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + FRCMD + Force output mode register + 0x78 + 32 + 0x00000000 + 0x0000FFFF + + + FRCMD + 2bit for each PWM output channel (0~7); +00: force output 0 +01: force output 1 +10: output highz +11: no force + 0 + 16 + read-write + + + + + SHLK + Shadow registers lock register + 0x7c + 32 + 0x00000000 + 0x80000000 + + + SHLK + write 1 to lock all shawdow register, wirte access is not permitted + 31 + 1 + read-write + + + + + CHCFG_0 + Output channel configure register + 0x80 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_1 + Output channel configure register + 0x84 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_2 + Output channel configure register + 0x88 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_3 + Output channel configure register + 0x8c + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_4 + Output channel configure register + 0x90 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_5 + Output channel configure register + 0x94 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_6 + Output channel configure register + 0x98 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_7 + Output channel configure register + 0x9c + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_8 + Output channel configure register + 0xa0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_9 + Output channel configure register + 0xa4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_10 + Output channel configure register + 0xa8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_11 + Output channel configure register + 0xac + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_12 + Output channel configure register + 0xb0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_13 + Output channel configure register + 0xb4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_14 + Output channel configure register + 0xb8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_15 + Output channel configure register + 0xbc + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_16 + Output channel configure register + 0xc0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_17 + Output channel configure register + 0xc4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_18 + Output channel configure register + 0xc8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_19 + Output channel configure register + 0xcc + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_20 + Output channel configure register + 0xd0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_21 + Output channel configure register + 0xd4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_22 + Output channel configure register + 0xd8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_23 + Output channel configure register + 0xdc + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + GCR + Global control register + 0xf0 + 32 + 0x00000000 + 0xFDFFFFE7 + + + FAULTI3EN + 1- enable the internal fault input 3 + 31 + 1 + read-write + + + FAULTI2EN + 1- enable the internal fault input 2 + 30 + 1 + read-write + + + FAULTI1EN + 1- enable the internal fault input 1 + 29 + 1 + read-write + + + FAULTI0EN + 1- enable the internal fault input 0 + 28 + 1 + read-write + + + DEBUGFAULT + 1- enable debug mode output protection + 27 + 1 + read-write + + + FRCPOL + polarity of input pwm_force, +1- active low +0- active high + 26 + 1 + read-write + + + HWSHDWEDG + When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as shadow register hardware load event. +1- Falling edge +0- Rising edge + 24 + 1 + read-write + + + CMPSHDWSEL + This bitfield select one of the comparators as hardware event time to load comparator shadow registers + 19 + 5 + read-write + + + FAULTRECEDG + When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. +1- Falling edge +0- Rising edge + 18 + 1 + read-write + + + FAULTRECHWSEL + Selec one of the 24 comparators as fault output recover trigger. + 13 + 5 + read-write + + + FAULTE1EN + 1- enable the external fault input 1 + 12 + 1 + read-write + + + FAULTE0EN + 1- enable the external fault input 0 + 11 + 1 + read-write + + + FAULTEXPOL + external fault polarity +1-active low +0-active high + 9 + 2 + read-write + + + RLDSYNCEN + 1- pwm timer counter reset to reload value (rld) by synci is enabled + 8 + 1 + read-write + + + CEN + 1- enable the pwm timer counter +0- stop the pwm timer counter + 7 + 1 + read-write + + + FAULTCLR + 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + 6 + 1 + read-write + + + XRLDSYNCEN + 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled + 5 + 1 + read-write + + + FRCTIME + This bit field select the force effective time +00: force immediately +01: force at main counter reload time +10: force at FRCSYNCI +11: no force + 1 + 2 + read-write + + + SWFRC + 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect + 0 + 1 + read-write + + + + + SHCR + Shadow register control register + 0xf4 + 32 + 0x00000000 + 0x00001FFF + + + FRCSHDWSEL + This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers + 8 + 5 + read-write + + + CNTSHDWSEL + This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) + 3 + 5 + read-write + + + CNTSHDWUPT + This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 1 + 2 + read-write + + + SHLKEN + 1- enable shadow registers lock feature, +0- disable shadow registers lock, shlk bit will always be 0 + 0 + 1 + read-write + + + + + CAPPOS_0 + Capture rising edge register + 0x100 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_1 + Capture rising edge register + 0x104 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_2 + Capture rising edge register + 0x108 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_3 + Capture rising edge register + 0x10c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_4 + Capture rising edge register + 0x110 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_5 + Capture rising edge register + 0x114 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_6 + Capture rising edge register + 0x118 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_7 + Capture rising edge register + 0x11c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_8 + Capture rising edge register + 0x120 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_9 + Capture rising edge register + 0x124 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_10 + Capture rising edge register + 0x128 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_11 + Capture rising edge register + 0x12c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_12 + Capture rising edge register + 0x130 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_13 + Capture rising edge register + 0x134 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_14 + Capture rising edge register + 0x138 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_15 + Capture rising edge register + 0x13c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_16 + Capture rising edge register + 0x140 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_17 + Capture rising edge register + 0x144 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_18 + Capture rising edge register + 0x148 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_19 + Capture rising edge register + 0x14c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_20 + Capture rising edge register + 0x150 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_21 + Capture rising edge register + 0x154 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_22 + Capture rising edge register + 0x158 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_23 + Capture rising edge register + 0x15c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CNT + Counter + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + RESERVED + read-only as 0 + 0 + 4 + read-only + + + + + CAPNEG_0 + Capture falling edge register + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_1 + Capture falling edge register + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_2 + Capture falling edge register + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_3 + Capture falling edge register + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_4 + Capture falling edge register + 0x190 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_5 + Capture falling edge register + 0x194 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_6 + Capture falling edge register + 0x198 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_7 + Capture falling edge register + 0x19c + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_8 + Capture falling edge register + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_9 + Capture falling edge register + 0x1a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_10 + Capture falling edge register + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_11 + Capture falling edge register + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_12 + Capture falling edge register + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_13 + Capture falling edge register + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_14 + Capture falling edge register + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_15 + Capture falling edge register + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_16 + Capture falling edge register + 0x1c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_17 + Capture falling edge register + 0x1c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_18 + Capture falling edge register + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_19 + Capture falling edge register + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_20 + Capture falling edge register + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_21 + Capture falling edge register + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_22 + Capture falling edge register + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_23 + Capture falling edge register + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CNTCOPY + Counter copy + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + RESERVED + read-only as 0 + 0 + 4 + read-only + + + + + PWMCFG_0 + PWM channel configure register + 0x200 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_1 + PWM channel configure register + 0x204 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_2 + PWM channel configure register + 0x208 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_3 + PWM channel configure register + 0x20c + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_4 + PWM channel configure register + 0x210 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_5 + PWM channel configure register + 0x214 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_6 + PWM channel configure register + 0x218 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_7 + PWM channel configure register + 0x21c + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + SR + Status register + 0x220 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTF + fault condition flag + 27 + 1 + read-write + + + XRLDF + extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + 26 + 1 + read-write + + + HALFRLDF + half reload flag, this flag set when cnt count to rld/2 + 25 + 1 + read-write + + + RLDF + reload flag, this flag set when cnt count to rld value or when SYNCI assert + 24 + 1 + read-write + + + CMPFX + comparator output compare or input capture flag + 0 + 24 + read-write + + + + + IRQEN + Interrupt request enable register + 0x224 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTIRQE + fault condition interrupt enable + 27 + 1 + read-write + + + XRLDIRQE + extended reload flag interrupt enable + 26 + 1 + read-write + + + HALFRLDIRQE + half reload flag interrupt enable + 25 + 1 + read-write + + + RLDIRQE + reload flag interrupt enable + 24 + 1 + read-write + + + CMPIRQEX + comparator output compare or input capture flag interrupt enable + 0 + 24 + read-write + + + + + DMAEN + DMA request enable register + 0x22c + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTEN + fault condition DMA request enable + 27 + 1 + read-write + + + XRLDEN + extended reload flag DMA request enable + 26 + 1 + read-write + + + HALFRLDEN + half reload flag DMA request enable + 25 + 1 + read-write + + + RLDEN + reload flag DMA request enable + 24 + 1 + read-write + + + CMPENX + comparator output compare or input capture flag DMA request enable + 0 + 24 + read-write + + + + + CMPCFG_CMPCFG0 + Comparator configure register + 0x230 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_1 + Comparator configure register + 0x234 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_2 + Comparator configure register + 0x238 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_3 + Comparator configure register + 0x23c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_4 + Comparator configure register + 0x240 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_5 + Comparator configure register + 0x244 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_6 + Comparator configure register + 0x248 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_7 + Comparator configure register + 0x24c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_8 + Comparator configure register + 0x250 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_9 + Comparator configure register + 0x254 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_10 + Comparator configure register + 0x258 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_11 + Comparator configure register + 0x25c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_12 + Comparator configure register + 0x260 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_13 + Comparator configure register + 0x264 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_14 + Comparator configure register + 0x268 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_15 + Comparator configure register + 0x26c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_16 + Comparator configure register + 0x270 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_17 + Comparator configure register + 0x274 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_18 + Comparator configure register + 0x278 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_19 + Comparator configure register + 0x27c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_20 + Comparator configure register + 0x280 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_21 + Comparator configure register + 0x284 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_22 + Comparator configure register + 0x288 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_23 + Comparator configure register + 0x28c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + + + PWM1 + PWM1 + PWM + 0xf0210000 + + + PWM2 + PWM2 + PWM + 0xf0220000 + + + PWM3 + PWM3 + PWM + 0xf0230000 + + + HALL0 + HALL0 + HALL + 0xf0204000 + + 0x0 + 0x8c + registers + + + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0x8001083F + + + READ + 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + RESERVED + reserved + 16 + 1 + read-write + + + SNAPEN + 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert + 11 + 1 + read-write + + + RESERVED + reserved + 5 + 1 + read-write + + + RSTCNT + set to reset all counter and related snapshots + 4 + 1 + read-write + + + RESERVED + reserved + 2 + 2 + read-write + + + RESERVED + reserved + 0 + 2 + read-write + + + + + PHCFG + Phase configure register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DLYSEL + This bit select delay start time: +1- start counting delay after pre-trigger +0- start counting delay after u,v,w toggle + 31 + 1 + read-write + + + RESERVED + reserved + 24 + 7 + read-write + + + DLYCNT + delay clock cycles number + 0 + 24 + read-write + + + + + WDGCFG + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + UVWCFG + U,V,W configure register + 0xc + 32 + 0x00000000 + 0x07FFFFFF + + + RESERVED + reserved + 24 + 3 + read-write + + + PRECNT + the clock cycle number which the pre flag will set before the next uvw transition + 0 + 24 + read-write + + + + + TRGOEN + Trigger output enable register + 0x10 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- enable trigger output when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- enable trigger output when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- enable trigger output when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFEN + 1- enable trigger output when u flag set + 23 + 1 + read-write + + + VFEN + 1- enable trigger output when v flag set + 22 + 1 + read-write + + + WFEN + 1- enable trigger output when w flag set + 21 + 1 + read-write + + + + + READEN + Read event enable register + 0x14 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- load counters to their read registers when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- load counters to their read registers when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- load counters to their read registers when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFEN + 1- load counters to their read registers when u flag set + 23 + 1 + read-write + + + VFEN + 1- load counters to their read registers when v flag set + 22 + 1 + read-write + + + WFEN + 1- load counters to their read registers when w flag set + 21 + 1 + read-write + + + + + DMAEN + DMA enable register + 0x24 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- generate dma request when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- generate dma request when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- generate dma request when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFEN + 1- generate dma request when u flag set + 23 + 1 + read-write + + + VFEN + 1- generate dma request when v flag set + 22 + 1 + read-write + + + WFEN + 1- generate dma request when w flag set + 21 + 1 + read-write + + + + + SR + Status register + 0x28 + 32 + 0x00000000 + 0xFFE00000 + + + WDGF + watchdog count timeout flag + 31 + 1 + read-write + + + PHUPTF + phase update flag, will set when any of u, v, w signal toggle + 30 + 1 + read-write + + + PHPREF + phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle + 29 + 1 + read-write + + + PHDLYF + phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UF + u flag, will set when u signal toggle + 23 + 1 + read-write + + + VF + v flag, will set when v signal toggle + 22 + 1 + read-write + + + WF + w flag, will set when w signal toggle + 21 + 1 + read-write + + + + + IRQEN + Interrupt request enable register + 0x2c + 32 + 0x00000000 + 0xFFE00000 + + + WDGIE + 1- generate interrupt request when wdg flag set + 31 + 1 + read-write + + + PHUPTIE + 1- generate interrupt request when phupt flag set + 30 + 1 + read-write + + + PHPREIE + 1- generate interrupt request when phpre flag set + 29 + 1 + read-write + + + PHDLYIE + 1- generate interrupt request when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFIE + 1- generate interrupt request when u flag set + 23 + 1 + read-write + + + VFIE + 1- generate interrupt request when v flag set + 22 + 1 + read-write + + + WFIE + 1- generate interrupt request when w flag set + 21 + 1 + read-write + + + + + COUNT_CURRENT_W + W counter + 0x30 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_CURRENT_V + V counter + 0x34 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_CURRENT_U + U counter + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_CURRENT_TMR + Timer counter + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_READ_W + W read register + 0x40 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_READ_V + V read register + 0x44 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_READ_U + U read register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_READ_TMR + Timer read register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP0_W + W snap register 0 + 0x50 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP0_V + V snap register 0 + 0x54 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP0_U + Usnap register 0 + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP0_TMR + Timer snap register 0 + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP1_W + W snap register 1 + 0x60 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP1_V + V snap register 1 + 0x64 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP1_U + U snap register 1 + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP1_TMR + Timer snap register 1 + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + HIS_U_HIS0 + history register 0 + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + HIS_U_HIS1 + history register 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + HIS_V_HIS0 + V histroy register 0 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + HIS_V_HIS1 + V histroy register 1 + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + HIS_W_HIS0 + W histroy register 0 + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + HIS_W_HIS1 + W histroy register 1 + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + + + HALL1 + HALL1 + HALL + 0xf0214000 + + + HALL2 + HALL2 + HALL + 0xf0224000 + + + HALL3 + HALL3 + HALL + 0xf0234000 + + + QEI0 + QEI0 + QEI + 0xf0208000 + + 0x0 + 0x80 + registers + + + + CR + Control register + 0x0 + 32 + 0x00000000 + 0x80077F3F + + + READ + 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + HRSTSPD + 1- reset spdcnt when H assert + 18 + 1 + read-write + + + HRSTPH + 1- reset phcnt when H assert + 17 + 1 + read-write + + + HRSTZ + 1- reset zcnt when H assert + 16 + 1 + read-write + + + PAUSESPD + 1- pause spdcnt when PAUSE assert + 14 + 1 + read-write + + + PAUSEPH + 1- pause phcnt when PAUSE assert + 13 + 1 + read-write + + + PAUSEZ + 1- pause zcnt when PAUSE assert + 12 + 1 + read-write + + + HRDIR1 + 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + 11 + 1 + read-write + + + HRDIR0 + 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + 10 + 1 + read-write + + + HFDIR1 + 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + 9 + 1 + read-write + + + HFDIR0 + 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + 8 + 1 + read-write + + + SNAPEN + 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + 5 + 1 + read-write + + + RSTCNT + 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + 4 + 1 + read-write + + + RESERVED + 00-x1, phase_cnt will increase at each A posedge +01-x2, phase_cnt will increase at each A/B posedge +10-x4, phase_cnt will increase at each edge(A/B, pos/neg) + 2 + 2 + read-write + + + ENCTYP + 00-abz; 01-pd; 10-ud; 11-reserved + 0 + 2 + read-write + + + + + PHCFG + Phase configure register + 0x4 + 32 + 0x00000000 + 0x007FFFFF + + + ZCNTCFG + 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 +0- zcnt will increment or decrement when Z input assert + 22 + 1 + read-write + + + PHCALIZ + 1- phcnt will set to phidx when Z input assert + 21 + 1 + read-write + + + PHMAX + maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + 0 + 21 + read-write + + + + + WDGCFG + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + PHIDX + Phase index register + 0xc + 32 + 0x00000000 + 0x001FFFFF + + + PHIDX + phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + 0 + 21 + read-write + + + + + TRGOEN + Tigger output enable register + 0x10 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- enable trigger output when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- enable trigger output when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- enable trigger output when zphf flag set + 28 + 1 + read-write + + + + + READEN + Read event enable register + 0x14 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- load counters to their read registers when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- load counters to their read registers when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- load counters to their read registers when zphf flag set + 28 + 1 + read-write + + + + + ZCMP + Z comparator + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCMP + zcnt postion compare value + 0 + 32 + read-write + + + + + PHCMP + Phase comparator + 0x1c + 32 + 0x00000000 + 0xE01FFFFF + + + ZCMPDIS + 1- postion compare not include zcnt + 31 + 1 + read-write + + + DIRCMPDIS + 1- postion compare not include rotation direction + 30 + 1 + read-write + + + DIRCMP + 0- position compare need positive rotation +1- position compare need negative rotation + 29 + 1 + read-write + + + PHCMP + phcnt position compare value + 0 + 21 + read-write + + + + + SPDCMP + Speed comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDCMP + spdcnt position compare value + 0 + 32 + read-write + + + + + DMAEN + DMA request enable register + 0x24 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- generate dma request when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- generate dma request when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- generate dma request when zphf flag set + 28 + 1 + read-write + + + + + SR + Status register + 0x28 + 32 + 0x00000000 + 0xF0000000 + + + WDGF + watchdog flag + 31 + 1 + read-write + + + HOMEF + home flag + 30 + 1 + read-write + + + POSCMPF + postion compare match flag + 29 + 1 + read-write + + + ZPHF + z input flag + 28 + 1 + read-write + + + + + IRQEN + Interrupt request register + 0x2c + 32 + 0x00000000 + 0xF0000000 + + + WDGIE + 1- generate interrupt when wdg flag set + 31 + 1 + read-write + + + HOMEIE + 1- generate interrupt when homef flag set + 30 + 1 + read-write + + + POSCMPIE + 1- generate interrupt when poscmpf flag set + 29 + 1 + read-write + + + ZPHIE + 1- generate interrupt when zphf flag set + 28 + 1 + read-write + + + + + COUNT_CURRENT_Z + Z counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_CURRENT_PH + Phase counter + 0x34 + 32 + 0x00000000 + 0xC61FFFFF + + + RESERVE + reversed + 31 + 1 + read-only + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_CURRENT_SPD + Speed counter + 0x38 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_CURRENT_TMR + Timer counter + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_READ_Z + Z counter + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_READ_PH + Phase counter + 0x44 + 32 + 0x00000000 + 0xC61FFFFF + + + RESERVE + reversed + 31 + 1 + read-only + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_READ_SPD + Speed counter + 0x48 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_READ_TMR + Timer counter + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP0_Z + Z snap register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_SNAP0_PH + Phase snap register + 0x54 + 32 + 0x00000000 + 0xC61FFFFF + + + RESERVE + reversed + 31 + 1 + read-only + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_SNAP0_SPD + Speed snap register + 0x58 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_SNAP0_TMR + Timer snap register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP1_Z + Z snap register 1 + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_SNAP1_PH + Phase snap register 1 + 0x64 + 32 + 0x00000000 + 0xC61FFFFF + + + RESERVE + reversed + 31 + 1 + read-only + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_SNAP1_SPD + Speed snap register 1 + 0x68 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_SNAP1_TMR + Timer snap register 1 + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS0 + Speed history + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS1 + Speed history 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS2 + Speed history 2 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS3 + Speed history 3 + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + + + QEI1 + QEI1 + QEI + 0xf0218000 + + + QEI2 + QEI2 + QEI + 0xf0228000 + + + QEI3 + QEI3 + QEI + 0xf0238000 + + + TRGM0 + TRGM0 + TRGM + 0xf020c000 + + 0x0 + 0x404 + registers + + + + FILTCFG_PWM_IN0 + Filter configure register + 0x0 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN1 + Filter configure register + 0x4 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN2 + Filter configure register + 0x8 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN3 + Filter configure register + 0xc + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN4 + Filter configure register + 0x10 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN5 + Filter configure register + 0x14 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN6 + Filter configure register + 0x18 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN7 + Filter configure register + 0x1c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN0 + Filter configure register + 0x20 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN1 + Filter configure register + 0x24 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN2 + Filter configure register + 0x28 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN3 + Filter configure register + 0x2c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN4 + Filter configure register + 0x30 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN5 + Filter configure register + 0x34 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN6 + Filter configure register + 0x38 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN7 + Filter configure register + 0x3c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN8 + Filter configure register + 0x40 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN9 + Filter configure register + 0x44 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN10 + Filter configure register + 0x48 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN11 + Filter configure register + 0x4c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + TRGOCFG_TRGM_OUT0 + Trigger manager output configure register + 0x100 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT1 + Trigger manager output configure register + 0x104 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT2 + Trigger manager output configure register + 0x108 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT3 + Trigger manager output configure register + 0x10c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT4 + Trigger manager output configure register + 0x110 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT5 + Trigger manager output configure register + 0x114 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT6 + Trigger manager output configure register + 0x118 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT7 + Trigger manager output configure register + 0x11c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT8 + Trigger manager output configure register + 0x120 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT9 + Trigger manager output configure register + 0x124 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT10 + Trigger manager output configure register + 0x128 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUT11 + Trigger manager output configure register + 0x12c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUTX0 + Trigger manager output configure register + 0x130 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_TRGM_OUTX1 + Trigger manager output configure register + 0x134 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_SYNCI + Trigger manager output configure register + 0x138 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FRCI + Trigger manager output configure register + 0x13c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FRCSYNCI + Trigger manager output configure register + 0x140 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_SHRLDSYNCI + Trigger manager output configure register + 0x144 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FAULTI0 + Trigger manager output configure register + 0x148 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FAULTI1 + Trigger manager output configure register + 0x14c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FAULTI2 + Trigger manager output configure register + 0x150 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_FAULTI3 + Trigger manager output configure register + 0x154 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN8 + Trigger manager output configure register + 0x158 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN9 + Trigger manager output configure register + 0x15c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN10 + Trigger manager output configure register + 0x160 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN11 + Trigger manager output configure register + 0x164 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN12 + Trigger manager output configure register + 0x168 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN13 + Trigger manager output configure register + 0x16c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN14 + Trigger manager output configure register + 0x170 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN15 + Trigger manager output configure register + 0x174 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN16 + Trigger manager output configure register + 0x178 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN17 + Trigger manager output configure register + 0x17c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN18 + Trigger manager output configure register + 0x180 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN19 + Trigger manager output configure register + 0x184 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN20 + Trigger manager output configure register + 0x188 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN21 + Trigger manager output configure register + 0x18c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN22 + Trigger manager output configure register + 0x190 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_PWM_IN23 + Trigger manager output configure register + 0x194 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_A + Trigger manager output configure register + 0x198 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_B + Trigger manager output configure register + 0x19c + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_Z + Trigger manager output configure register + 0x1a0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_H + Trigger manager output configure register + 0x1a4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_PAUSE + Trigger manager output configure register + 0x1a8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_QEI_SNAPI + Trigger manager output configure register + 0x1ac + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_HALL_U + Trigger manager output configure register + 0x1b0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_HALL_V + Trigger manager output configure register + 0x1b4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_HALL_W + Trigger manager output configure register + 0x1b8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_HALL_SNAPI + Trigger manager output configure register + 0x1bc + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADC0_STRGI + Trigger manager output configure register + 0x1c0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADC1_STRGI + Trigger manager output configure register + 0x1c4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADC2_STRGI + Trigger manager output configure register + 0x1c8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADC3_STRGI + Trigger manager output configure register + 0x1cc + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADCX_PTRGI0A + Trigger manager output configure register + 0x1d0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADCX_PTRGI0B + Trigger manager output configure register + 0x1d4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_ADCX_PTRGI0C + Trigger manager output configure register + 0x1d8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRA_SYNCI + Trigger manager output configure register + 0x1dc + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRA_IN2 + Trigger manager output configure register + 0x1e0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRA_IN3 + Trigger manager output configure register + 0x1e4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRB_SYNCI + Trigger manager output configure register + 0x1e8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRB_IN2 + Trigger manager output configure register + 0x1ec + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_GPTMRB_IN3 + Trigger manager output configure register + 0x1f0 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_CMPX_WIN + Trigger manager output configure register + 0x1f4 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_CAN_PTPC0_CAP + Trigger manager output configure register + 0x1f8 + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + TRGOCFG_CAN_PTPC1_CAP + Trigger manager output configure register + 0x1fc + 32 + 0x00000000 + 0x000001FF + + + OUTINV + 1- Invert the output + 8 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 7 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 6 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 6 + read-write + + + + + DMACFG_0 + DMA request configure register + 0x200 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + DMACFG_1 + DMA request configure register + 0x204 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + DMACFG_2 + DMA request configure register + 0x208 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + DMACFG_3 + DMA request configure register + 0x20c + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + GCR + General Control Register + 0x400 + 32 + 0x00000000 + 0x00000FFF + + + TRGOPEN + The bitfield enable the TRGM outputs. + 0 + 12 + read-write + + + + + + + TRGM1 + TRGM1 + TRGM + 0xf021c000 + + + TRGM2 + TRGM2 + TRGM + 0xf022c000 + + + TRGM3 + TRGM3 + TRGM + 0xf023c000 + + + SYNT + SYNT + SYNT + 0xf0240000 + + 0x0 + 0x30 + registers + + + + GCR + Global control register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + CRST + 1- Reset counter + 1 + 1 + read-write + + + CEN + 1- Enable counter + 0 + 1 + read-write + + + + + RLD + Counter reload register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + counter reload value + 0 + 32 + read-write + + + + + CNT + Counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT + counter + 0 + 32 + read-only + + + + + CMP_0 + Comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + CMP_1 + Comparator + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + CMP_2 + Comparator + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + CMP_3 + Comparator + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + + + LCDC + LCDC + LCDC + 0xf1000000 + + 0x0 + 0x404 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SW_RST + Software reset, high active. When write 1 ,all internal logical will be reset. +0b - No action +1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. + 31 + 1 + read-write + + + DISP_ON + Display panel On/Off mode. +0b - Display Off. +1b - Display On. +Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. +So a good procedure to stop and turn on the display is: +1) clr VS_BLANK status +2) assert software reset +3) de-assert software reset +4) set display off +5) check VS_BLANK status until it is asserted, +6)reset the module, change settings +7) set display on + 30 + 1 + read-write + + + LINE_PATTERN + LCDIF line output order. +000b - RGB. +001b - RBG. +010b - GBR. +011b - GRB. +100b - BRG. +101b - BGR. + 27 + 3 + read-write + + + DISP_MODE + LCDIF operating mode. +00b - Normal mode. Panel content controlled by layer configuration. +01b - Test Mode1.(BGND Color Display) +10b - Test Mode2.(Column Color Bar) +11b - Test Mode3.(Row Color Bar) + 25 + 2 + read-write + + + BGDCL4CLR + background color for clear mode when the alpha channel is 0 + 24 + 1 + read-write + + + ARQOS + ARQOS for bus fabric arbitration + 20 + 4 + read-write + + + RSV + Reserved + 5 + 15 + read-write + + + INV_PXDATA + Indicates if value at the output (pixel data output) needs to be negated. +0b - Output is to remain same as the data inside memory +1b - Output to be negated from the data inside memory + 4 + 1 + read-write + + + INV_PXCLK + Polarity change of Pixel Clock. +0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge +1b - LCDC outputs data on the falling edge, Display samples data on the rising edge + 3 + 1 + read-write + + + INV_HREF + Polarity of HREF +0b - HREF signal active HIGH, indicating active pixel data +1b - HREF signal active LOW + 2 + 1 + read-write + + + INV_VSYNC + Polarity of VSYNC +0b - VSYNC signal active HIGH +1b - VSYNC signal active LOW + 1 + 1 + read-write + + + INV_HSYNC + Polarity of HSYNC +0b - HSYNC signal active HIGH +1b - HSYNC signal active LOW + 0 + 1 + read-write + + + + + BGND_CL + Background Color Register + 0x4 + 32 + 0x00000000 + 0x00FFFFFF + + + R + Red component of the default color displayed in the sectors where no layer is active. + 16 + 8 + read-write + + + G + Green component of the default color displayed in the sectors where no layer is active. + 8 + 8 + read-write + + + B + Blue component of the default color displayed in the sectors where no layer is active. + 0 + 8 + read-write + + + + + DISP_WN_SIZE + Display Window Size Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 28 + 4 + read-write + + + Y + Sets the display size vertical resolution in pixels. + 16 + 12 + read-write + + + RSV + Reserved + 12 + 4 + read-write + + + X + Sets the display size horizontal resolution in pixels. + 0 + 12 + read-write + + + + + HSYNC_PARA + HSYNC Config Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 31 + 1 + read-write + + + FP + HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC + 22 + 9 + read-write + + + RSV + Reserved + 20 + 2 + read-write + + + BP + HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC + 11 + 9 + read-write + + + RSV + Reserved + 9 + 2 + read-write + + + PW + HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. + 0 + 9 + read-write + + + + + VSYNC_PARA + VSYNC Config Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 31 + 1 + read-write + + + FP + VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC + 22 + 9 + read-write + + + RSV + Reserved + 20 + 2 + read-write + + + BP + VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC + 11 + 9 + read-write + + + RSV + Reserved + 9 + 2 + read-write + + + PW + VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. + 0 + 9 + read-write + + + + + DMA_ST + DMA Status Register + 0x14 + 32 + 0x00000000 + 0xFFFFFF00 + + + DMA_ERR + plane n axi error. W1C. + 24 + 8 + read-write + + + DMA1_DONE + Plane n frame 1 dma done. W1C. + 16 + 8 + read-write + + + DMA0_DONE + Plane n frame 0 dma done. W1C. + 8 + 8 + read-write + + + + + ST + Status Register + 0x18 + 32 + 0x00000000 + 0x0000000F + + + URGENT_UNDERRUN + Asserted when the output buffer urgent underrun condition encountered + 3 + 1 + read-write + + + VS_BLANK + Asserted when in vertical blanking period. At the start of VSYNC + 2 + 1 + read-write + + + UNDERRUN + Asserted when the output buffer underrun condition encountered + 1 + 1 + read-write + + + VSYNC + Asserted when in vertical blanking period. At the end of VSYNC + 0 + 1 + read-write + + + + + INT_EN + Interrupt Enable Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + DMA_ERR + Interrupt enable for DMA error + 24 + 8 + read-write + + + DMA_DONE + Interrupt enable for DMA done + 16 + 8 + read-write + + + RSV + Interrupt enable for DMA underflow + 8 + 8 + read-write + + + RSV + Reserved + 4 + 4 + read-write + + + URGENT_UNDERRUN + Asserted when the output buffer urgent underrun condition encountered + 3 + 1 + read-only + + + VS_BLANK + Interrupt enable for start of sof + 2 + 1 + read-write + + + UNDERRUN + Interrupt enable for underrun + 1 + 1 + read-write + + + VSYNC + Interrupt enable for end of sof + 0 + 1 + read-write + + + + + TXFIFO + TX FIFO Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 8 + 24 + read-write + + + THRSH + Threshold to start the lcd raster (0--0x7F) + 0 + 8 + read-write + + + + + LAYER_0_LAYCTRL + Layer Control Register + 0x200 + 32 + 0x00000000 + 0x000FFFFD + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + RSV + Reserved to be asserted. + 18 + 1 + read-write + + + RSV + Asserted when posx and posy are changed + 17 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), byte sequence as B,R +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional blending mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + LAYER_0_ALPHAS + Layer Alpha Register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 16 + 16 + read-write + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYER_0_LAYSIZE + Layer Size Register + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 28 + 4 + read-write + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + RSV + Reserved + 12 + 4 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYER_0_LAYPOS + Layer Position Register + 0x20c + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + LAYER_0_START0 + Layer Buffer Pointer Register + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LAYER_0_LINECFG + Layer Bus Config Register + 0x218 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + RSV + Reserved + 16 + 5 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. + 0 + 16 + read-write + + + + + LAYER_0_BG_CL + Layer Background Color Register + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + LAYER_0_CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x220 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + LAYER_0_CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x224 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + LAYER_0_CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x228 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + LAYER_1_LAYCTRL + Layer Control Register + 0x240 + 32 + 0x00000000 + 0x000FFFFD + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + RSV + Reserved to be asserted. + 18 + 1 + read-write + + + RSV + Asserted when posx and posy are changed + 17 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), byte sequence as B,R +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional blending mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + LAYER_1_ALPHAS + Layer Alpha Register + 0x244 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 16 + 16 + read-write + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYER_1_LAYSIZE + Layer Size Register + 0x248 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 28 + 4 + read-write + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + RSV + Reserved + 12 + 4 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYER_1_LAYPOS + Layer Position Register + 0x24c + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + LAYER_1_START0 + Layer Buffer Pointer Register + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LAYER_1_LINECFG + Layer Bus Config Register + 0x258 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + RSV + Reserved + 16 + 5 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. + 0 + 16 + read-write + + + + + LAYER_1_BG_CL + Layer Background Color Register + 0x25c + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + LAYER_1_CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x260 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + LAYER_1_CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x264 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + LAYER_1_CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x268 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + LAYER_2_LAYCTRL + Layer Control Register + 0x280 + 32 + 0x00000000 + 0x000FFFFD + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + RSV + Reserved to be asserted. + 18 + 1 + read-write + + + RSV + Asserted when posx and posy are changed + 17 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), byte sequence as B,R +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional blending mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + LAYER_2_ALPHAS + Layer Alpha Register + 0x284 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 16 + 16 + read-write + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYER_2_LAYSIZE + Layer Size Register + 0x288 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 28 + 4 + read-write + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + RSV + Reserved + 12 + 4 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYER_2_LAYPOS + Layer Position Register + 0x28c + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + LAYER_2_START0 + Layer Buffer Pointer Register + 0x290 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LAYER_2_LINECFG + Layer Bus Config Register + 0x298 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + RSV + Reserved + 16 + 5 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. + 0 + 16 + read-write + + + + + LAYER_2_BG_CL + Layer Background Color Register + 0x29c + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + LAYER_2_CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x2a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + LAYER_2_CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x2a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + LAYER_2_CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x2a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + LAYER_3_LAYCTRL + Layer Control Register + 0x2c0 + 32 + 0x00000000 + 0x000FFFFD + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + RSV + Reserved to be asserted. + 18 + 1 + read-write + + + RSV + Asserted when posx and posy are changed + 17 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), byte sequence as B,R +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional blending mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + LAYER_3_ALPHAS + Layer Alpha Register + 0x2c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 16 + 16 + read-write + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYER_3_LAYSIZE + Layer Size Register + 0x2c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 28 + 4 + read-write + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + RSV + Reserved + 12 + 4 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYER_3_LAYPOS + Layer Position Register + 0x2cc + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + LAYER_3_START0 + Layer Buffer Pointer Register + 0x2d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LAYER_3_LINECFG + Layer Bus Config Register + 0x2d8 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + RSV + Reserved + 16 + 5 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. + 0 + 16 + read-write + + + + + LAYER_3_BG_CL + Layer Background Color Register + 0x2dc + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + LAYER_3_CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x2e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + LAYER_3_CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x2e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + LAYER_3_CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x2e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + LAYER_4_LAYCTRL + Layer Control Register + 0x300 + 32 + 0x00000000 + 0x000FFFFD + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + RSV + Reserved to be asserted. + 18 + 1 + read-write + + + RSV + Asserted when posx and posy are changed + 17 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), byte sequence as B,R +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional blending mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + LAYER_4_ALPHAS + Layer Alpha Register + 0x304 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 16 + 16 + read-write + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYER_4_LAYSIZE + Layer Size Register + 0x308 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 28 + 4 + read-write + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + RSV + Reserved + 12 + 4 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYER_4_LAYPOS + Layer Position Register + 0x30c + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + LAYER_4_START0 + Layer Buffer Pointer Register + 0x310 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LAYER_4_LINECFG + Layer Bus Config Register + 0x318 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + RSV + Reserved + 16 + 5 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. + 0 + 16 + read-write + + + + + LAYER_4_BG_CL + Layer Background Color Register + 0x31c + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + LAYER_4_CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x320 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + LAYER_4_CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x324 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + LAYER_4_CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x328 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + LAYER_5_LAYCTRL + Layer Control Register + 0x340 + 32 + 0x00000000 + 0x000FFFFD + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + RSV + Reserved to be asserted. + 18 + 1 + read-write + + + RSV + Asserted when posx and posy are changed + 17 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), byte sequence as B,R +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional blending mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + LAYER_5_ALPHAS + Layer Alpha Register + 0x344 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 16 + 16 + read-write + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYER_5_LAYSIZE + Layer Size Register + 0x348 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 28 + 4 + read-write + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + RSV + Reserved + 12 + 4 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYER_5_LAYPOS + Layer Position Register + 0x34c + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + LAYER_5_START0 + Layer Buffer Pointer Register + 0x350 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LAYER_5_LINECFG + Layer Bus Config Register + 0x358 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + RSV + Reserved + 16 + 5 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. + 0 + 16 + read-write + + + + + LAYER_5_BG_CL + Layer Background Color Register + 0x35c + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + LAYER_5_CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x360 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + LAYER_5_CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x364 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + LAYER_5_CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x368 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + LAYER_6_LAYCTRL + Layer Control Register + 0x380 + 32 + 0x00000000 + 0x000FFFFD + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + RSV + Reserved to be asserted. + 18 + 1 + read-write + + + RSV + Asserted when posx and posy are changed + 17 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), byte sequence as B,R +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional blending mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + LAYER_6_ALPHAS + Layer Alpha Register + 0x384 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 16 + 16 + read-write + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYER_6_LAYSIZE + Layer Size Register + 0x388 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 28 + 4 + read-write + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + RSV + Reserved + 12 + 4 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYER_6_LAYPOS + Layer Position Register + 0x38c + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + LAYER_6_START0 + Layer Buffer Pointer Register + 0x390 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LAYER_6_LINECFG + Layer Bus Config Register + 0x398 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + RSV + Reserved + 16 + 5 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. + 0 + 16 + read-write + + + + + LAYER_6_BG_CL + Layer Background Color Register + 0x39c + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + LAYER_6_CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x3a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + LAYER_6_CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x3a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + LAYER_6_CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x3a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + LAYER_7_LAYCTRL + Layer Control Register + 0x3c0 + 32 + 0x00000000 + 0x000FFFFD + + + PACK_DIR + The byte sequence of the 4 bytes in a 32-bit word. +1: {A0, A1, A2, A3} byte re-ordered. +0: {A3, A2, A1, A0} the normal case with no byte re-order + 19 + 1 + read-write + + + RSV + Reserved to be asserted. + 18 + 1 + read-write + + + RSV + Asserted when posx and posy are changed + 17 + 1 + read-write + + + SHADOW_LOAD_EN + Shadow Load Enable +The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + 16 + 1 + read-write + + + YUV_FORMAT + The YUV422 input format selection. +00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 +01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 +10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 +11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 +If not YUV422 mode, +FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) +FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + 14 + 2 + read-write + + + PIXFORMAT + Layer encoding format (bit per pixel) +0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. +0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. +0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. +0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. +0100b - 16 bpp (RGB565), byte sequence as B,R +0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] +1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A +1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + 10 + 4 + read-write + + + LOCALPHA_OP + The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream +1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) +2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream +Others: Reserved + 8 + 2 + read-write + + + INALPHA_OP + The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline +1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) +2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline +Others: Reserved + 6 + 2 + read-write + + + AB_MODE + Alpha Blending Mode +0: SKBlendMode_Clear; +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional blending mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 2 + 4 + read-write + + + EN + Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + 0 + 1 + read-write + + + + + LAYER_7_ALPHAS + Layer Alpha Register + 0x3c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 16 + 16 + read-write + + + LOCD + The system alpha value for the data stream of current layer stream (SRC) + 8 + 8 + read-write + + + IND + The system alpha value for the input stream from previous stage (DST) + 0 + 8 + read-write + + + + + LAYER_7_LAYSIZE + Layer Size Register + 0x3c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 28 + 4 + read-write + + + HEIGHT + Height of the layer in pixels + 16 + 12 + read-write + + + RSV + Reserved + 12 + 4 + read-write + + + WIDTH + Width of the layer in pixels (Note: not actual width-1) +The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + 0 + 12 + read-write + + + + + LAYER_7_LAYPOS + Layer Position Register + 0x3cc + 32 + 0x00000000 + 0xFFFFFFFF + + + Y + The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + 16 + 16 + read-write + + + X + The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + 0 + 16 + read-write + + + + + LAYER_7_START0 + Layer Buffer Pointer Register + 0x3d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR0 + Input buffer Start address 0 + 0 + 32 + read-write + + + + + LAYER_7_LINECFG + Layer Bus Config Register + 0x3d8 + 32 + 0x00000000 + 0xE0FFFFFF + + + MPT_SIZE + Maximal Per Transfer Data Size: +0: 64 bytes +1: 128 bytes +2: 256 bytes +3: 512 bytes +4: 1024 bytes + 29 + 3 + read-write + + + MAX_OT + the number of outstanding axi read transactions. +If zero, it means max 8. + 21 + 3 + read-write + + + RSV + Reserved + 16 + 5 + read-write + + + PITCH + Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. + 0 + 16 + read-write + + + + + LAYER_7_BG_CL + Layer Background Color Register + 0x3dc + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGB + ARGB8888. It is only useful in the last active stage in the pipeline. + 0 + 32 + read-write + + + + + LAYER_7_CSC_COEF0 + Layer Color Space Conversion Config Register 0 + 0x3e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit in the LCDC plane data path. +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data +This bit will be shadowed. + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + LAYER_7_CSC_COEF1 + Layer Color Space Conversion Config Register 1 + 0x3e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + LAYER_7_CSC_COEF2 + Layer Color Space Conversion Config Register 2 + 0x3e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + CLUT_LOAD + Clut Load Control Register + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 7 + 25 + read-write + + + SEL_NUM + Selected CLUT Number +The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. +. 3'h0 - PLANE 0 +. 3'h1 - PLANE 1 +. ------ +. 3'h7 - PLANE 7 +CLUT 8 can be modified via APB even when display is on. +Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. + 4 + 3 + read-write + + + RSV + Reserved + 1 + 3 + read-write + + + UPDATE_EN + CLUT Update Enable +The bit is written to 1 when software want to update the Color Look Up Tables during display. +If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. +If set to 0, software can update CLUT8 directly according to the CLUT memory map. +Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. + 0 + 1 + read-write + + + + + + + CAM0 + CAM0 + CAM + 0xf1008000 + + 0x0 + 0x490 + registers + + + + CR1 + Control Register + 0x0 + 32 + 0x00000000 + 0x3F9A8C7F + + + COLOR_EXT + If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. +The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. + 29 + 1 + read-write + + + INV_PIXCLK + invert pixclk pad input before it is used + 28 + 1 + read-write + + + INV_HSYNC + invert hsync pad input before it is used + 27 + 1 + read-write + + + INV_VSYNC + invert vsync pad input before it is used + 26 + 1 + read-write + + + SWAP16_EN + SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. +NOTE: Example of swapping enabled: +Data input to FIFO = 0x11223344 +Data in RX FIFO = 0x 33441122 +NOTE: Example of swapping disabled: +Data input to FIFO = 0x11223344 +Data in RX FIFO = 0x11223344 +0 Disable swapping +1 Enable swapping + 25 + 1 + read-write + + + PACK_DIR + Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. +0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. +1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. + 24 + 1 + read-write + + + RESTART_BUSPTR + force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer + 23 + 1 + read-write + + + ASYNC_RXFIFO_CLR + ASynchronous Rx FIFO Clear. +When asserted, this bit clears RXFIFO immediately. +It will be auto-cleared. + 20 + 1 + read-write + + + SYNC_RXFIFO_CLR + Synchronous Rx FIFO Clear. +When asserted, this bit clears RXFIFO on every SOF. + 19 + 1 + read-write + + + SOF_INT_POL + SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. +0 SOF interrupt is generated on SOF falling edge +1 SOF interrupt is generated on SOF rising edge + 17 + 1 + read-write + + + INV_DATA + Invert Data Input. This bit enables or disables internal inverters on the data lines. +0 CAM_D data lines are directly applied to internal circuitry +1 CAM_D data lines are inverted before applied to internal circuitry + 15 + 1 + read-write + + + STORAGE_MODE + 00: Normal Mode (one plane mode) +01: Two Plane Mode (Y, UV plane) +10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 +11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 + 10 + 2 + read-write + + + COLOR_FORMATS + input color formats: +0010b: 24bit: RGB888 +0100b: 16bit: RGB565 +0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) +YUV +YCrCb +Note: YUV420 is not supported. +1000b: 24bit: YUV444 + 3 + 4 + read-write + + + SENSOR_BIT_WIDTH + the bit width of the sensor +0: 8 bits +1: 10 bits +Others: Undefined + 0 + 3 + read-write + + + + + INT_EN + Interrupt Enable Register + 0x4 + 32 + 0x00000000 + 0x00003A4D + + + ERR_CL_BWID_CFG_INT_EN + The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable + 13 + 1 + read-write + + + HIST_DONE_INT_EN + Enable hist done int + 12 + 1 + read-write + + + HRESP_ERR_EN + Hresponse Error Enable. This bit enables the hresponse error interrupt. +0 Disable hresponse error interrupt +1 Enable hresponse error interrupt + 11 + 1 + read-write + + + EOF_INT_EN + End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. +0 EOF interrupt is disabled. +1 EOF interrupt is generated when RX count value is reached. + 9 + 1 + read-write + + + RF_OR_INTEN + RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. +0 RxFIFO overrun interrupt is disabled +1 RxFIFO overrun interrupt is enabled + 6 + 1 + read-write + + + FB2_DMA_DONE_INTEN + Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA +transfer done. +0 Frame Buffer2 DMA Transfer Done interrupt disable +1 Frame Buffer2 DMA Transfer Done interrupt enable + 3 + 1 + read-write + + + FB1_DMA_DONE_INTEN + Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA +transfer done. +0 Frame Buffer1 DMA Transfer Done interrupt disable +1 Frame Buffer1 DMA Transfer Done interrupt enable + 2 + 1 + read-write + + + SOF_INT_EN + Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. +0 SOF interrupt disable +1 SOF interrupt enable + 0 + 1 + read-write + + + + + CR2 + Control 2 Register + 0x10 + 32 + 0x00000000 + 0xFFFF8E2F + + + FRMCNT_15_0 + Frame Counter. This is a 16-bit Frame Counter +(Wraps around automatically after reaching the maximum) + 16 + 16 + read-only + + + FRMCNT_RST + Frame Count Reset. Resets the Frame Counter. +0 Do not reset +1 Reset frame counter immediately + 15 + 1 + read-write + + + RXFF_LEVEL + RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. +000 4 Double words +001 8 Double words +010 16 Double words +011 24 Double words +100 32 Double words +101 48 Double words +110 64 Double words +111 96 Double words + 9 + 3 + read-write + + + DMA_REQ_EN_RFF + DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. +0 Disable the dma request +1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. + 5 + 1 + read-write + + + CLRBITFORMAT + Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. + 0 + 4 + read-write + + + + + STA + Status Register + 0x24 + 32 + 0x00000000 + 0x000C26C4 + + + ERR_CL_BWID_CFG + The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found + 19 + 1 + read-write + + + HIST_DONE + hist cal done + 18 + 1 + read-write + + + RF_OR_INT + RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing +1) +0 RXFIFO has not overflowed. +1 RXFIFO has overflowed. + 13 + 1 + read-write + + + DMA_TSF_DONE_FB2 + DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writting 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) +0 DMA transfer is not completed. +1 DMA transfer is completed. + 10 + 1 + read-write + + + DMA_TSF_DONE_FB1 + DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writting 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) +0 DMA transfer is not completed. +1 DMA transfer is completed. + 9 + 1 + read-write + + + EOF_INT + End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) +0 EOF is not detected. +1 EOF is detected. + 7 + 1 + read-write + + + SOF_INT + Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) +0 SOF is not detected. +1 SOF is detected. + 6 + 1 + read-write + + + HRESP_ERR_INT + Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing +1) +0 No hresponse error. +1 Hresponse error is detected. + 2 + 1 + read-write + + + + + DMASA_FB1 + Pixel DMA Frame Buffer 1 Address + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + PTR + DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. +In Two-Plane Mode, Y buffer1 + 2 + 30 + read-write + + + + + DMASA_FB2 + Pixel DMA Frame Buffer 2 Address + 0x34 + 32 + 0x00000000 + 0xFFFFFFFC + + + PTR + DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. +In Two-Plane Mode, Y buffer2 + 2 + 30 + read-write + + + + + BUF_PARA + Buffer Parameters Register + 0x38 + 32 + 0x00000000 + 0x0000FFFF + + + LINEBSP_STRIDE + Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. +The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. + 0 + 16 + read-write + + + + + IDEAL_WN_SIZE + Ideal Image Size Register + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + HEIGHT + Image Height. Indicates how many active pixels in a column of the image from the sensor. + 16 + 16 + read-write + + + WIDTH + Image Width. Indicates how many active pixels in a line of the image from the sensor. +The number of bytes to be transfered is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. +As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. + 0 + 16 + read-write + + + + + CR18 + Control CR18 Register + 0x4c + 32 + 0x00000000 + 0x80000780 + + + CAM_ENABLE + CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. + 31 + 1 + read-write + + + AWQOS + AWQOS for bus fabric arbitration + 7 + 4 + read-write + + + + + DMASA_UV1 + Pixel UV DMA Frame Buffer 1 Address + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + Two Plane UV Buffer Start Address 1 + 2 + 30 + read-write + + + RSV + Reserved + 0 + 2 + read-write + + + + + DMASA_UV2 + Pixel UV DMA Frame Buffer 2 Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR + Two Plane UV Buffer Start Address 2 + 2 + 30 + read-write + + + RSV + Reserved + 0 + 2 + read-write + + + + + CR20 + Control CR20 Register + 0x58 + 32 + 0x00000000 + 0xC00001FF + + + BINARY_EN + binary picture output enable + 31 + 1 + read-write + + + HISTOGRAM_EN + histogarm enable + 30 + 1 + read-write + + + BIG_END + Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. + 8 + 1 + read-write + + + THRESHOLD + Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. + 0 + 8 + read-write + + + + + MAX_WN_CYCLE + Max Window Size Register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + ROW + Max Width-1 + 16 + 16 + read-write + + + COL + Max Height-1 + 0 + 16 + read-write + + + + + CSC_COEF0 + Color Space Conversion Config Register 0 + 0x70 + 32 + 0x00000000 + 0xDFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit +0b - The CSC is bypassed and the input pixels are RGB data already +1b - The CSC is enabled and the pixels will be converted to RGB data + 30 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + CSC_COEF1 + Color Space Conversion Config Register 1 + 0x74 + 32 + 0x00000000 + 0x07FF07FF + + + C1 + Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + CSC_COEF2 + Color Space Conversion Config Register 2 + 0x78 + 32 + 0x00000000 + 0x07FF07FF + + + C2 + Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + CLRKEY_LOW + Low Color Key Register + 0x7c + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + CLRKEY_HIGH + High Color Key Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + HISTOGRAM_FIFO_DATA0 + Histogram Registers + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA1 + Histogram Registers + 0x94 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA2 + Histogram Registers + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA3 + Histogram Registers + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA4 + Histogram Registers + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA5 + Histogram Registers + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA6 + Histogram Registers + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA7 + Histogram Registers + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA8 + Histogram Registers + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA9 + Histogram Registers + 0xb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA10 + Histogram Registers + 0xb8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA11 + Histogram Registers + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA12 + Histogram Registers + 0xc0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA13 + Histogram Registers + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA14 + Histogram Registers + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA15 + Histogram Registers + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA16 + Histogram Registers + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA17 + Histogram Registers + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA18 + Histogram Registers + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA19 + Histogram Registers + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA20 + Histogram Registers + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA21 + Histogram Registers + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA22 + Histogram Registers + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA23 + Histogram Registers + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA24 + Histogram Registers + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA25 + Histogram Registers + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA26 + Histogram Registers + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA27 + Histogram Registers + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA28 + Histogram Registers + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA29 + Histogram Registers + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA30 + Histogram Registers + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA31 + Histogram Registers + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA32 + Histogram Registers + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA33 + Histogram Registers + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA34 + Histogram Registers + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA35 + Histogram Registers + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA36 + Histogram Registers + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA37 + Histogram Registers + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA38 + Histogram Registers + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA39 + Histogram Registers + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA40 + Histogram Registers + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA41 + Histogram Registers + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA42 + Histogram Registers + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA43 + Histogram Registers + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA44 + Histogram Registers + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA45 + Histogram Registers + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 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+ + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA220 + Histogram Registers + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA221 + Histogram Registers + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA222 + Histogram Registers + 0x408 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA223 + Histogram Registers + 0x40c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA224 + Histogram Registers + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA225 + Histogram Registers + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA226 + Histogram Registers + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA227 + Histogram Registers + 0x41c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA228 + Histogram Registers + 0x420 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA229 + Histogram Registers + 0x424 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA230 + Histogram Registers + 0x428 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA231 + Histogram Registers + 0x42c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA232 + Histogram Registers + 0x430 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA233 + Histogram Registers + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA234 + Histogram Registers + 0x438 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA235 + Histogram Registers + 0x43c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA236 + Histogram Registers + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA237 + Histogram Registers + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA238 + Histogram Registers + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA239 + Histogram Registers + 0x44c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA240 + Histogram Registers + 0x450 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA241 + Histogram Registers + 0x454 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA242 + Histogram Registers + 0x458 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA243 + Histogram Registers + 0x45c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA244 + Histogram Registers + 0x460 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA245 + Histogram Registers + 0x464 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA246 + Histogram Registers + 0x468 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA247 + Histogram Registers + 0x46c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA248 + Histogram Registers + 0x470 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA249 + Histogram Registers + 0x474 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA250 + Histogram Registers + 0x478 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA251 + Histogram Registers + 0x47c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA252 + Histogram Registers + 0x480 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA253 + Histogram Registers + 0x484 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA254 + Histogram Registers + 0x488 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + HISTOGRAM_FIFO_DATA255 + Histogram Registers + 0x48c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + reserved + 24 + 8 + read-only + + + HIST_Y + the appearance of bin x (x=(address-DATA0)/4) + 0 + 24 + read-only + + + + + + + CAM1 + CAM1 + CAM + 0xf100c000 + + + PDMA + PDMA + PDMA + 0xf1010000 + + 0x0 + 0xc0 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 23 + 9 + read-write + + + ARQOS + QoS for AXI read bus + 19 + 4 + read-write + + + AWQOS + QoS for AXI write bus + 15 + 4 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 13 + 2 + read-write + + + AXIERR_IRQ_EN + Enable interrupt of AXI bus error + 12 + 1 + read-write + + + PDMA_DONE_IRQ_EN + Enable interrupt of PDMA_DONE + 11 + 1 + read-write + + + RSV + Asserted to re-shadow the registers to enable on-the-fly new display pattern generation. Auto clear to zero. + 10 + 1 + read-write + + + CLKGATE + Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. + 9 + 1 + read-write + + + RSV + Enable handshake with LCD0 controller. When this is set, the PDMA will not process an entire framebuffer, but will instead process rows of NxN blocks in a double-buffer handshake with the LCDIF. This enables the use of the onboard SRAM for a partial frame buffer. + 8 + 1 + read-write + + + RSV + Enable the next irq interrupt + 7 + 1 + read-write + + + IRQ_EN + Enable normal interrupt + 6 + 1 + read-write + + + BS16 + Asserted when the Block Size is 16x16, else 8x8 + 5 + 1 + read-write + + + P1_EN + Plane 1 Enable + 4 + 1 + read-write + + + P0_EN + Plane 0 Enable + 3 + 1 + read-write + + + RSV + Asserted to use repeat mode + 2 + 1 + read-write + + + PDMA_SFTRST + Software Reset. +Write 1 to clear PDMA internal logic. +Write 0 to exit software reset mode. + 1 + 1 + read-write + + + PDMA_EN + 1b - Enabled + 0 + 1 + read-write + + + + + STAT + Status Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + BLOCKY + Y block that is processing + 24 + 8 + read-only + + + BLOCKX + X block that is processing + 16 + 8 + read-only + + + RSV + Reserved + 10 + 6 + read-only + + + PDMA_DONE + PDMA one image done + 9 + 1 + read-only + + + AXI_ERR_ID + AXI error ID + 5 + 4 + read-only + + + AXI_0_WRITE_ERR + AXI0 write err + 4 + 1 + read-write + + + AXI_1_READ_ERR + AXI1 read err + 3 + 1 + read-write + + + AXI_0_READ_ERR + AXI0 read err + 2 + 1 + read-write + + + RSV + Asserted to indicate NEXT_CMD event triggering IRQ + 1 + 1 + read-write + + + IRQ + Asserted to indicate a IRQ event + 0 + 1 + read-write + + + + + OUT_CTRL + Out Layer Control Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSTALPHA + The destination (P1) system ALPHA value. + 24 + 8 + read-write + + + SRCALPHA + The source (P0) system ALPHA value. + 16 + 8 + read-write + + + DSTALPHA_OP + The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream +1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) +2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream +Others: Reserved + 14 + 2 + read-write + + + SRCALPHA_OP + The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) +0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream +1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) +2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream +Others: Reserved + 12 + 2 + read-write + + + ABLEND_MODE + Alpha Blending Mode +0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); +1: SKBlendMode_Src ; +2: SKBlendMode_Dst +3: SKBlendMode_SrcOver +4: SKBlendMode_DstOver +5: SKBlendMode_SrcIn +6: SKBlendMode_DstIn +7: SKBlendMode_SrcOut +8: SKBlendMode_DstOut +9: SKBlendMode_SrcATop +10: SKBlendMode_DstATop +11: SKBlendMode_Xor +12: SKBlendMode_Plus (The conventional belding mode) +13: SKBlendMode_Modulate +14: SRC org +15: DST org +Others: Reserved. + 8 + 4 + read-write + + + RSV + Not suppoted yet + 6 + 2 + read-write + + + FORMAT + Output buffer format. +0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A +0xE RGB565 - 16-bit pixels, byte sequence as B,R +0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) + 0 + 6 + read-write + + + + + OUT_BUF + Output buffer address + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. + 0 + 32 + read-write + + + + + OUT_PITCH + Outlayer Pitch Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + BYTELEN + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + OUT_LRC + Output Lower Right Corner Register + 0x18 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. +The value is the height of the output image size. + 16 + 14 + read-write + + + X + This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. +Should be the width of the output image size. + 0 + 14 + read-write + + + + + OUT_PS_0_ULC + Layer Upper Left Corner Register + 0x1c + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. + 16 + 14 + read-write + + + X + This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. + 0 + 14 + read-write + + + + + OUT_PS_0_LRC + Layer Lower Right Corner Register + 0x20 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. + 16 + 14 + read-write + + + X + This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. + 0 + 14 + read-write + + + + + OUT_PS_1_ULC + Layer Upper Left Corner Register + 0x24 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. + 16 + 14 + read-write + + + X + This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. + 0 + 14 + read-write + + + + + OUT_PS_1_LRC + Layer Lower Right Corner Register + 0x28 + 32 + 0x00000000 + 0x3FFF3FFF + + + Y + This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. + 16 + 14 + read-write + + + X + This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. + 0 + 14 + read-write + + + + + PS_0_CTRL + Layer Control Register + 0x30 + 32 + 0x00000000 + 0x001FFFFF + + + INB13_SWAP + Swap bit[31:24] and bit [15:8] before pack_dir operation. + 20 + 1 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 18 + 2 + read-write + + + BKGCL4CLR + Enable to use background color for clear area + 17 + 1 + read-write + + + YCBCR_MODE + YCbCr mode or YUV mode + 16 + 1 + read-write + + + BYPASS + Asserted to bypass the CSC stage + 15 + 1 + read-write + + + VFLIP + Indicates that the input should be flipped vertically (effect applied before rotation). + 14 + 1 + read-write + + + HFLIP + Indicates that the input should be flipped horizontally (effect applied before rotation). + 13 + 1 + read-write + + + ROTATE + Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring +after the FLIP_X and FLIP_Y permutation. +0x0 ROT_0 +0x1 ROT_90 +0x2 ROT_180 +0x3 ROT_270 + 11 + 2 + read-write + + + DECY + Verticle pre decimation filter control. +0x0 DISABLE - Disable pre-decimation filter. +0x1 DECY2 - Decimate PS by 2. +0x2 DECY4 - Decimate PS by 4. +0x3 DECY8 - Decimate PS by 8. + 9 + 2 + read-write + + + DECX + Horizontal pre decimation filter control. +0x0 DISABLE - Disable pre-decimation filter. +0x1 DECX2 - Decimate PS by 2. +0x2 DECX4 - Decimate PS by 4. +0x3 DECX8 - Decimate PS by 8. + 7 + 2 + read-write + + + HW_BYTE_SWAP + Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. + 6 + 1 + read-write + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. +0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A +0xE RGB565 - 16-bit pixels, byte sequence as B,R +0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) + 0 + 6 + read-write + + + + + PS_0_BUF + Layer data buffer address + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS RGB or Y (luma) input buffer. + 0 + 32 + read-write + + + + + PS_0_PITCH + Layer data pitch register + 0x40 + 32 + 0x00000000 + 0x0000FFFF + + + BYTELEN + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + PS_0_BKGD + Layer background color register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + COLOR + Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. + 0 + 32 + read-write + + + + + PS_0_SCALE + Layer scale register + 0x48 + 32 + 0x00000000 + 0x7FFF7FFF + + + Y + This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + 16 + 15 + read-write + + + X + This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + 0 + 15 + read-write + + + + + PS_0_OFFSET + Layer offset register + 0x4c + 32 + 0x00000000 + 0x0FFF0FFF + + + Y + This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. +It is applied after the decimation filter stage, and before the bilinear filter stage. + 16 + 12 + read-write + + + X + This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. +It is applied after the decimation filter stage, and before the bilinear filter stage. + 0 + 12 + read-write + + + + + PS_0_CLRKEY_LOW + Layer low color key register + 0x50 + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + PS_0_CLRKEY_HIGH + Layer high color key register + 0x54 + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 + 0 + 24 + read-write + + + + + PS_0_ORG + Layer original size register + 0x58 + 32 + 0x00000000 + 0x3FFF3FFF + + + HIGHT + The number of vertical pixels of the original frame (not -1) + 16 + 14 + read-write + + + WIDTH + The number of horizontal pixels of the original frame (not -1) + 0 + 14 + read-write + + + + + PS_1_CTRL + layer control register + 0x60 + 32 + 0x00000000 + 0x001FFFFF + + + INB13_SWAP + Swap bit[31:24] and bit [15:8] before pack_dir operation. + 20 + 1 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 18 + 2 + read-write + + + BKGCL4CLR + Enable to use background color for clear area + 17 + 1 + read-write + + + YCBCR_MODE + YCbCr mode or YUV mode + 16 + 1 + read-write + + + BYPASS + Asserted to bypass the CSC stage + 15 + 1 + read-write + + + VFLIP + Indicates that the input should be flipped vertically (effect applied before rotation). + 14 + 1 + read-write + + + HFLIP + Indicates that the input should be flipped horizontally (effect applied before rotation). + 13 + 1 + read-write + + + ROTATE + Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring +after the FLIP_X and FLIP_Y permutation. +0x0 ROT_0 +0x1 ROT_90 +0x2 ROT_180 +0x3 ROT_270 + 11 + 2 + read-write + + + DECY + Verticle pre decimation filter control. +0x0 DISABLE - Disable pre-decimation filter. +0x1 DECY2 - Decimate PS by 2. +0x2 DECY4 - Decimate PS by 4. +0x3 DECY8 - Decimate PS by 8. + 9 + 2 + read-write + + + DECX + Horizontal pre decimation filter control. +0x0 DISABLE - Disable pre-decimation filter. +0x1 DECX2 - Decimate PS by 2. +0x2 DECX4 - Decimate PS by 4. +0x3 DECX8 - Decimate PS by 8. + 7 + 2 + read-write + + + HW_BYTE_SWAP + Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. + 6 + 1 + read-write + + + FORMAT + PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. +0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A +0xE RGB565 - 16-bit pixels, byte sequence as B,R +0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) + 0 + 6 + read-write + + + + + PS_1_BUF + Layer data buffer address + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Address pointer for the PS RGB or Y (luma) input buffer. + 0 + 32 + read-write + + + + + PS_1_PITCH + Layer data pitch register + 0x70 + 32 + 0x00000000 + 0x0000FFFF + + + BYTELEN + Indicates the number of bytes in memory between two vertically adjacent pixels. + 0 + 16 + read-write + + + + + PS_1_BKGD + Layer background color register + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + COLOR + Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. + 0 + 32 + read-write + + + + + PS_1_SCALE + Layer scale register + 0x78 + 32 + 0x00000000 + 0x7FFF7FFF + + + Y + This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + 16 + 15 + read-write + + + X + This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + 0 + 15 + read-write + + + + + PS_1_OFFSET + Layer offset register + 0x7c + 32 + 0x00000000 + 0x0FFF0FFF + + + Y + This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. +It is applied after the decimation filter stage, and before the bilinear filter stage. + 16 + 12 + read-write + + + X + This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. +It is applied after the decimation filter stage, and before the bilinear filter stage. + 0 + 12 + read-write + + + + + PS_1_CLRKEY_LOW + Layer low color key register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + 0 + 24 + read-write + + + + + PS_1_CLRKEY_HIGH + Layer high color key register + 0x84 + 32 + 0x00000000 + 0x00FFFFFF + + + LIMIT + High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 + 0 + 24 + read-write + + + + + PS_1_ORG + Layer original size register + 0x88 + 32 + 0x00000000 + 0x3FFF3FFF + + + HIGHT + The number of vertical pixels of the original frame (not -1) + 16 + 14 + read-write + + + WIDTH + The number of horizontal pixels of the original frame (not -1) + 0 + 14 + read-write + + + + + YUV2RGB_COEF0 + YUV2RGB coefficients register 0 + 0xa0 + 32 + 0x00000000 + 0x1FFFFFFF + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + YUV2RGB_COEF1 + YUV2RGB coefficients register 1 + 0xa4 + 32 + 0x00000000 + 0x07FF07FF + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + YUV2RGB_COEF2 + YUV2RGB coefficients register 2 + 0xa8 + 32 + 0x00000000 + 0x07FF07FF + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + RGB2YUV_COEF0 + RGB2YUV coefficients register 0 + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + Asserted to use YCrCb mode + 31 + 1 + read-write + + + ENABLE + Asserted to enable this RGB2YUV CSC stage + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + CSC parameters C0 + 18 + 11 + read-write + + + UV_OFFSET + CSC parameters UV_OFFSET + 9 + 9 + read-write + + + Y_OFFSET + CSC parameters Y_OFFSET + 0 + 9 + read-write + + + + + RGB2YUV_COEF1 + RGB2YUV coefficients register 1 + 0xb0 + 32 + 0x00000000 + 0x07FF07FF + + + C1 + CSC parameters C1 + 16 + 11 + read-write + + + C4 + CSC parameters C4 + 0 + 11 + read-write + + + + + RGB2YUV_COEF2 + RGB2YUV coefficients register 2 + 0xb4 + 32 + 0x00000000 + 0x07FF07FF + + + C2 + CSC parameters C2 + 16 + 11 + read-write + + + C3 + CSC parameters C3 + 0 + 11 + read-write + + + + + RGB2YUV_COEF3 + RGB2YUV coefficients register 3 + 0xb8 + 32 + 0x00000000 + 0x07FF07FF + + + C6 + CSC parameters C6 + 16 + 11 + read-write + + + C5 + CSC parameters C5 + 0 + 11 + read-write + + + + + RGB2YUV_COEF4 + RGB2YUV coefficients register 4 + 0xbc + 32 + 0x00000000 + 0x07FF07FF + + + C8 + CSC parameters C8 + 16 + 11 + read-write + + + C7 + CSC parameters C7 + 0 + 11 + read-write + + + + + + + JPEG + JPEG + JPEG + 0xf1014000 + + 0x0 + 0xa0 + registers + + + + INDMA_MISC + In DMA Misc Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFC + + + RSV + Reserved + 23 + 9 + read-write + + + ARQOS + QoS for AXI read channel + 19 + 4 + read-write + + + MAX_OT + max_ot when input are RGB pixels. +For 16 bits per pixel, it can be set as 4. +For 32 bits per pixel, it will be set as 2. + 15 + 4 + read-write + + + INB13_SWAP + Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. + 14 + 1 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. +2'b00: no change {A3, A2, A1, A0} +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 12 + 2 + read-write + + + INDMA_RENEW + Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. + 11 + 1 + read-write + + + NXT_IRQ_EN + In DMA Next Interrupt Enable + 10 + 1 + read-write + + + IN_DMA_DONE_IRQ_EN + In DMA Done enable + 9 + 1 + read-write + + + AXI_ERR_IRQ_EN + In DMA axi bus error inetrrupt enable + 8 + 1 + read-write + + + IRQ_EN + interrupt enable for all interrupt sources of In DMA module + 7 + 1 + read-write + + + IN_DMA_ID + 0: Pixel (In) +1: ECS (In) +2: Qmem +3: HuffEnc +4: HuffMin +5: HuffBase +6: HuffSymb + 4 + 3 + read-write + + + IN_DMA_REQ + Asserted to request DMA. Automatically clear after DMA is done. + 3 + 1 + read-write + + + INDMA2D + Asserted if In_DMA_ID=Pixel. + 2 + 1 + read-write + + + + + INDMABASE + In DMA Buf Address + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Y plane (or Encoded Bit Plane) + 0 + 32 + read-write + + + + + INDMA_CTRL0 + In DMA Buf Control 0 Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TTLEN + Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. + 16 + 16 + read-write + + + PITCH + Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. + 0 + 16 + read-write + + + + + INDMA_CTRL1 + In DMA Buf Control 1 Register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + ROWLEN + Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] + 0 + 16 + read-write + + + + + INXT_CMD + In DMA Next Command Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The address pointing to the next command + 2 + 30 + read-write + + + OP_VALID + asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. + 1 + 1 + read-write + + + EN + NXTCMD phase Enable Bit + 0 + 1 + read-write + + + + + OUTDMA_MISC + Out DMA Misc Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFC + + + RSV + Reserved + 18 + 14 + read-write + + + AWQOS + No description avaiable + 14 + 4 + read-write + + + PACK_DIR + Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. +2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) +2'b01: {A2, A3, A0, A1} +2'b10: {A1, A0, A3, A2} +2'b11: {A0, A1, A2, A3} + 12 + 2 + read-write + + + EN_OUTCNT + Enable output counter (unit as bytes) + 11 + 1 + read-write + + + INI_OUTCNT + Asserted to ini output counter + 10 + 1 + read-write + + + ADD_ODMA_ENDINGS + Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. + 9 + 1 + read-write + + + NXT_IRQ_EN + Out DMA Next Interrupt Enable + 8 + 1 + read-write + + + OUT_DMA_DONE_IRQ_EN + Out DMA Done interrupt Enable + 7 + 1 + read-write + + + AXI_ERR_IRQ_EN + Out DMA axi bus error inetrrupt enable + 6 + 1 + read-write + + + IRQ_EN + interrupt enable for all interrupt sources of Out DMA module + 5 + 1 + read-write + + + OUT_DMA_ID + 0: Pixel (Out) +1: ECS (Out) + 4 + 1 + read-write + + + OUT_DMA_REQ + Asserted to enable Out DMA request + 3 + 1 + read-write + + + OUTDMA2D + Asserted if Out_DMA_ID==Pixel + 2 + 1 + read-write + + + + + OUTDMABASE + Out DMA Buf Address + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + Y plane (or Encoded Bit Plane) + 0 + 32 + read-write + + + + + OUTDMA_CTRL0 + Out DMA Buf Control 0 Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + TTLEN + Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. + 16 + 16 + read-write + + + PITCH + Pitch between the starting point of Rows when Out_DMA_ID==Pixel + 0 + 16 + read-write + + + + + OUTDMA_CTRL1 + Out DMA Buf Control 1 Register + 0x30 + 32 + 0x00000000 + 0x0000FFFF + + + ROWLEN + Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] + 0 + 16 + read-write + + + + + ONXT_CMD + Out DMA Next Command Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The address pointing to the next command + 2 + 30 + read-write + + + OP_VALID + asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. + 1 + 1 + read-write + + + EN + NXTCMD phase Enable Bit + 0 + 1 + read-write + + + + + CFG + Configuration Register + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 23 + 9 + read-write + + + JD_UVSWAP + Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. + 22 + 1 + read-write + + + CFG_IPATH_SEL + 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V +2'b01:ARGB8888, byte sequence as B,G,R,A +2'b10:RGB565, byte sequence as B,R +2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 + 20 + 2 + read-write + + + CODEC_OVER_IRQ_EN + The jpg endec process done interrupt enable + 19 + 1 + read-write + + + CODEC_RESTART_ERR_IRQ_EN + The jpg endec restart error interrupt enable + 18 + 1 + read-write + + + MEM_DEBUG_CLK_SEL + asserted to use APB clock, so that the memory contents could be read out through APB interface + 17 + 1 + read-write + + + RSV + memory power down + 16 + 1 + read-write + + + RSV + No description avaiable + 10 + 6 + read-write + + + CLKGATE + Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. + 9 + 1 + read-write + + + CFG_OPATH_SEL + 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V +2'b01:ARGB8888, byte sequence as B,G,R,A +2'b10:RGB565, byte sequence as R,B +2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 + 7 + 2 + read-write + + + JDATA_FORMAT + 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU +3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU +3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU +3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU +3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU +Others: Undefined + 4 + 3 + read-write + + + JPEG_SFTRST + Software Reset + 3 + 1 + read-write + + + START + Asserted if to start a new encoder/decoder conversion. +It will at first stop the inner JPEG module, then reset it, and then re-run it. +It is a different mode from DMA phase mode. +It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. +Auto clear. + 2 + 1 + read-write + + + MODE + 1: decoder, 0:encoder + 1 + 1 + read-write + + + JPEG_EN + 1b - Enabled + 0 + 1 + read-write + + + + + STAT + Status Register + 0x44 + 32 + 0x00000000 + 0xFFFFBFFE + + + BUSY + When 1 means that the module is busy doing conversion and data transfer. + 31 + 1 + read-only + + + RSV + Reserved + 15 + 16 + read-only + + + AXI_ERR_ID + the axi err id + 10 + 4 + read-only + + + AXI_READ_ERR + in-dma axi bus error + 9 + 1 + read-only + + + AXI_WRITE_ERR + out-dma axi bus error + 8 + 1 + read-only + + + AXI_ERR + axi bus error + 7 + 1 + read-write + + + ONXT_IRQ + OutDMA next interrupt + 6 + 1 + read-write + + + INXT_IRQ + InDMA next interrupt + 5 + 1 + read-write + + + OUT_DMA_TRANSFER_DONE + OutDMA process done + 4 + 1 + read-write + + + IN_DMA_TRANSFER_DONE + InDMA process done + 3 + 1 + read-write + + + CODEC_OVER + Coding or decoding process is over. DMA is not included. +The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. + 2 + 1 + read-write + + + RESTART_MARKER_ERROR + codec restart marker error interrupt + 1 + 1 + read-write + + + + + WIDTH + Image width register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 16 + 16 + read-write + + + IMG + Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) + 0 + 16 + read-write + + + + + HEIGHT + Image height register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 16 + 16 + read-write + + + IMG + Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) + 0 + 16 + read-write + + + + + BUFADDR + Buf Access Addr + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + ADDR[31:28] denotes the buffer type: +0x2: Qmem +0x3: HuffEnc +0x4: HuffMin +0x5: HuffBase +0x6: HuffSymb +ADDR[27:0] is the address inside the buffer + 0 + 32 + read-write + + + + + BUFDATA + Buf Access Data + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + The data write-to/read-from buffer. +The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. + 0 + 32 + read-write + + + + + OUTDMACNT + Out DMA Bytes Counter + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + The out DMA counter + 0 + 32 + read-only + + + + + CSC_COEF0 + YUV2RGB coefficients Register 0 + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + This bit changes the behavior when performing U/V converting. +0b - Converting YUV to RGB data +1b - Converting YCbCr to RGB data + 31 + 1 + read-write + + + ENABLE + Enable the CSC unit. +0b - The CSC is bypassed +1b - The CSC is enabled + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + 18 + 11 + read-write + + + UV_OFFSET + Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. +YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + 9 + 9 + read-write + + + Y_OFFSET + Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is +typically -16 (0x1F0). + 0 + 9 + read-write + + + + + CSC_COEF1 + YUV2RGB coefficients Register 1 + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + 0 + 11 + read-write + + + + + CSC_COEF2 + YUV2RGB coefficients Register 2 + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + 0 + 11 + read-write + + + + + RGB2YUV_COEF0 + RGB2YUV coefficients Register 0 + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + YCBCR_MODE + Asserted to use YCrCb mode. Must be assigned as 1. + 31 + 1 + read-write + + + ENABLE + Asserted to enable this RGB2YCbCr CSC stage + 30 + 1 + read-write + + + RSV + Reserved + 29 + 1 + read-write + + + C0 + CSC parameters C0 + 18 + 11 + read-write + + + UV_OFFSET + CSC parameters UV_OFFSET + 9 + 9 + read-write + + + Y_OFFSET + CSC parameters Y_OFFSET + 0 + 9 + read-write + + + + + RGB2YUV_COEF1 + RGB2YUV coefficients Register 1 + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C1 + CSC parameters C1 + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C4 + CSC parameters C4 + 0 + 11 + read-write + + + + + RGB2YUV_COEF2 + RGB2YUV coefficients Register 2 + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C2 + CSC parameters C2 + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C3 + CSC parameters C3 + 0 + 11 + read-write + + + + + RGB2YUV_COEF3 + RGB2YUV coefficients Register 3 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C6 + CSC parameters C6 + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C5 + CSC parameters C5 + 0 + 11 + read-write + + + + + RGB2YUV_COEF4 + RGB2YUV coefficients Register 4 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + Reserved + 27 + 5 + read-write + + + C8 + CSC parameters C8 + 16 + 11 + read-write + + + RSV + Reserved + 11 + 5 + read-write + + + C7 + CSC parameters C7 + 0 + 11 + read-write + + + + + IMGREG1 + Image Control Register 1 + 0x84 + 32 + 0x00000000 + 0xFFFFFFF7 + + + RSV + No description avaiable + 4 + 28 + read-write + + + RE + Encoder Use only. +Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs + 2 + 1 + read-write + + + NCOL + Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 + 0 + 2 + read-write + + + + + IMGREG2 + Image Control Register 2 + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 26 + 6 + read-write + + + NMCU + Encoder Use only. +The number of NMCU to be generated in encoder mode + 0 + 26 + read-write + + + + + IMGREG3 + Image Control Register 3 + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 16 + 16 + read-write + + + NRST + Encoder use only. +It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. + 0 + 16 + read-write + + + + + IMGREG_REG40 + Image Control Register 40 + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 8 + 24 + read-write + + + NBLOCK + Encoder use only. +The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. + 4 + 4 + read-write + + + QT + Encoder use only. +The selection of the quantization table. + 2 + 2 + read-write + + + HA + Encoder use only. +The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. + 1 + 1 + read-write + + + HD + Encoder use only. +The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. + 0 + 1 + read-write + + + + + IMGREG_REG41 + Image Control Register 41 + 0x94 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 8 + 24 + read-write + + + NBLOCK + Encoder use only. +The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. + 4 + 4 + read-write + + + QT + Encoder use only. +The selection of the quantization table. + 2 + 2 + read-write + + + HA + Encoder use only. +The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. + 1 + 1 + read-write + + + HD + Encoder use only. +The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. + 0 + 1 + read-write + + + + + IMGREG_REG42 + Image Control Register 42 + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 8 + 24 + read-write + + + NBLOCK + Encoder use only. +The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. + 4 + 4 + read-write + + + QT + Encoder use only. +The selection of the quantization table. + 2 + 2 + read-write + + + HA + Encoder use only. +The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. + 1 + 1 + read-write + + + HD + Encoder use only. +The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. + 0 + 1 + read-write + + + + + IMGREG_REG43 + Image Control Register 43 + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + RSV + No description avaiable + 8 + 24 + read-write + + + NBLOCK + Encoder use only. +The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. + 4 + 4 + read-write + + + QT + Encoder use only. +The selection of the quantization table. + 2 + 2 + read-write + + + HA + Encoder use only. +The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. + 1 + 1 + read-write + + + HD + Encoder use only. +The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. + 0 + 1 + read-write + + + + + + + ENET0 + ENET0 + ENET + 0xf2000000 + + 0x0 + 0x3028 + registers + + + + MACCFG + MAC Configuration Register + 0x0 + 32 + 0x00000000 + 0x7FFFFFFF + + + SARC + Source Address Insertion or Replacement Control + This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: +- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. +- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. +- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. Note: - Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. + 28 + 3 + read-write + + + TWOKPE + IEEE 802.3as Support for 2K Packets + When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status. + 27 + 1 + read-write + + + SFTERR + SMII Force Transmit Error + When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. + 26 + 1 + read-write + + + CST + CRC Stripping for Type Frames + When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. + 25 + 1 + read-write + + + TC + Transmit Configuration in RGMII, SGMII, or SMII + When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. + 24 + 1 + read-write + + + WD + Watchdog Disable + When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. + 23 + 1 + read-write + + + JD + Jabber Disable + When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. + 22 + 1 + read-write + + + BE + Frame Burst Enable + When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. + 21 + 1 + read-write + + + JE + Jumbo Frame Enable + When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. + 20 + 1 + read-write + + + IFG + Inter-Frame Gap + These bits control the minimum IFG between frames during transmission. +- 000: 96 bit times +- 001: 88 bit times +- 010: 80 bit times - ... +- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. + 17 + 3 + read-write + + + DCRS + Disable Carrier Sense During Transmission + When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. + 16 + 1 + read-write + + + PS + Port Select + This bit selects the Ethernet line speed. +- 0: For 1000 Mbps operations +- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. + 15 + 1 + read-write + + + FES + Speed + This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: +- 0: 10 Mbps +- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. + 14 + 1 + read-write + + + DO + Disable Receive Own + When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. + 13 + 1 + read-write + + + LM + Loopback Mode + When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. + 12 + 1 + read-write + + + DM + Duplex Mode + When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configuration. + 11 + 1 + read-write + + + IPC + Checksum Offload +When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. + 10 + 1 + read-write + + + DR + Disable Retry +When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). + 9 + 1 + read-write + + + LUD + Link Up or Down + This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: +- 0: Link Down +- 1: Link Up + 8 + 1 + read-write + + + ACS + Automatic Pad or CRC Stripping + When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. + 7 + 1 + read-write + + + BL + Back-Off Limit + The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. +- 00: k= min (n, 10) +- 01: k = min (n, 8) +- 10: k = min (n, 4) +- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k + 5 + 2 + read-write + + + DC + Deferral Check + When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. + 4 + 1 + read-write + + + TE + Transmitter Enable + When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. + 3 + 1 + read-write + + + RE + Receiver Enable + When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. + 2 + 1 + read-write + + + PRELEN + Preamble Length for Transmit frames + These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. +- 2'b00: 7 bytes of preamble +- 2'b01: 5 bytes of preamble +- 2'b10: 3 bytes of preamble +- 2'b11: Reserved + 0 + 2 + read-write + + + + + MACFF + MAC Frame Filter + 0x4 + 32 + 0x00000000 + 0x803087FF + + + RA + Receive All + When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. + 31 + 1 + read-write + + + DNTU + Drop non-TCP/UDP over IP Frames + When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. + 21 + 1 + read-write + + + IPFE + Layer 3 and Layer 4 Filter Enable + When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. + 20 + 1 + read-write + + + VTFE + VLAN Tag Filter Enable + When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. + 15 + 1 + read-write + + + HPF + Hash or Perfect Filter + When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. + 10 + 1 + read-write + + + SAF + Source Address Filter Enable + When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. + 9 + 1 + read-write + + + SAIF + SA Inverse Filtering +When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. + 8 + 1 + read-write + + + PCF + Pass Control Frames + These bits control the forwarding of all control frames (including unicast and multicast Pause frames). +- 00: MAC filters all control frames from reaching the application. +- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. +- 10: MAC forwards all control frames to application even if they fail the Address Filter. +- 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing: - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). + 6 + 2 + read-write + + + DBF + Disable Broadcast Frames + When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. + 5 + 1 + read-write + + + PM + Pass All Multicast +When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. + 4 + 1 + read-write + + + DAIF + DA Inverse Filtering + When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. + 3 + 1 + read-write + + + HMC + Hash Multicast +When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. + 2 + 1 + read-write + + + HUC + Hash Unicast + When set, the MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. + 1 + 1 + read-write + + + PR + Promiscuous Mode +When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. + 0 + 1 + read-write + + + + + HASH_H + Hash Table High Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HTH + Hash Table High + This field contains the upper 32 bits of the Hash table. + 0 + 32 + read-write + + + + + HASH_L + Hash Table Low Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + HTL + Hash Table Low + This field contains the lower 32 bits of the Hash table. + 0 + 32 + read-write + + + + + GMII_ADDR + GMII Address Register + 0x10 + 32 + 0x00000000 + 0x0000FFFF + + + PA + Physical Layer Address + This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. + 11 + 5 + read-write + + + GR + GMII Register + These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. + 6 + 5 + read-write + + + CR + CSR Clock Range + The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. +- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. +- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. +- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. +- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. +- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. +- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. +- 0110, 0111: Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. +- 1000: CSR clock/4 +- 1001: CSR clock/6 +- 1010: CSR clock/8 +- 1011: CSR clock/10 +- 1100: CSR clock/12 +- 1101: CSR clock/14 +- 1110: CSR clock/16 +- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. + 2 + 4 + read-write + + + GW + GMII Write + When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. + 1 + 1 + read-write + + + GB + GMII Busy + This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. + 0 + 1 + read-write + + + + + GMII_DATA + GMII Data Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + GD + GMII Data + This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. + 0 + 16 + read-write + + + + + FLOWCTRL + Flow Control Register + 0x18 + 32 + 0x00000000 + 0xFFFF00BF + + + PT + Pause Time + This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. + 16 + 16 + read-write + + + DZPQ + Disable Zero-Quanta Pause + When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. + 7 + 1 + read-write + + + PLT + Pause Low Threshold + This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: +- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). +- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). +- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). +- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. + 4 + 2 + read-write + + + UP + Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. + 3 + 1 + read-write + + + RFE + Receive Flow Control Enable + When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. + 2 + 1 + read-write + + + TFE + Transmit Flow Control Enable +In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. + 1 + 1 + read-write + + + FCB_BPA + Flow Control Busy or Backpressure Activate + This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. + 0 + 1 + read-write + + + + + VLAN_TAG + VLAN Tag Register + 0x1c + 32 + 0x00000000 + 0x000FFFFF + + + VTHM + VLAN Tag Hash Table Match Enable + When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. + 19 + 1 + read-write + + + ESVL + Enable S-VLAN + When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. + 18 + 1 + read-write + + + VTIM + VLAN Tag Inverse Match Enable +When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. + 17 + 1 + read-write + + + ETV + Enable 12-Bit VLAN Tag Comparison + When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. + 16 + 1 + read-write + + + VL + VLAN Tag Identifier for Receive Frames + This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: - Bits [15:13]: User Priority - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. + 0 + 16 + read-write + + + + + VERSION + Version Register + 0x20 + 32 + 0x00000000 + 0x0000FFFF + + + USERVER + User-defined Version + 8 + 8 + read-only + + + SNPSVER + Synopsys-defined Version (3.7) + 0 + 8 + read-only + + + + + DEBUGGING + Debug Register + 0x24 + 32 + 0x00000000 + 0x037F0377 + + + TXSTSFSTS + MTL TxStatus FIFO Full Status + When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. + 25 + 1 + read-only + + + TXFSTS + MTL Tx FIFO Not Empty Status +When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. + 24 + 1 + read-only + + + TWCSTS + MTL Tx FIFO Write Controller Status +When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. + 22 + 1 + read-only + + + TRCSTS + MTL Tx FIFO Read Controller Status +This field indicates the state of the Tx FIFO Read Controller: +- 00: IDLE state +- 01: READ state (transferring data to the MAC transmitter) +- 10: Waiting for TxStatus from the MAC transmitter +- 11: Writing the received TxStatus or flushing the Tx FIFO + 20 + 2 + read-only + + + TXPAUSED + MAC Transmitter in Pause +When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-only mode) and hence does not schedule any frame for transmission. + 19 + 1 + read-only + + + TFCSTS + MAC Transmit Frame Controller Status +This field indicates the state of the MAC Transmit Frame Controller module: +- 00: IDLE state +- 01: Waiting for status of previous frame or IFG or backoff period to be over +- 10: Generating and transmitting a Pause frame (in the full-duplex mode) +- 11: Transferring input frame for transmission + 17 + 2 + read-only + + + TPESTS + MAC GMII or MII Transmit Protocol Engine Status + When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. + 16 + 1 + read-only + + + RXFSTS + MTL RxFIFO Fill-Level Status +This field gives the status of the fill-level of the Rx FIFO: +- 00: Rx FIFO Empty +- 01: Rx FIFO fill-level below flow-control deactivate threshold +- 10: Rx FIFO fill-level above flow-control activate threshold +- 11: Rx FIFO Full + 8 + 2 + read-only + + + RRCSTS + MTL RxFIFO Read Controller State +This field gives the state of the Rx FIFO read Controller: +- 00: IDLE state +- 01: Reading frame data +- 10: Reading frame status (or timestamp) +- 11: Flushing the frame data and status + 5 + 2 + read-only + + + RWCSTS + MTL Rx FIFO Write Controller Active Status + When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. + 4 + 1 + read-only + + + RFCFCSTS + MAC Receive Frame FIFO Controller Status + When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. - RFCFCSTS[1] represents the status of small FIFO Read controller. - RFCFCSTS[0] represents the status of small FIFO Write controller. + 1 + 2 + read-only + + + RPESTS + MAC GMII or MII Receive Protocol Engine Status +When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. + 0 + 1 + read-only + + + + + RWKFRMFILT + Remote Wake-Up Frame Filter Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + WKUPFRMFILT + This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers + 0 + 32 + read-write + + + + + PMT_CSR + PMT Control and Status Register + 0x2c + 32 + 0x00000000 + 0x9F000267 + + + RWKFILTRST + Remote Wake-Up Frame Filter Register Pointer Reset +When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. + 31 + 1 + read-write + + + RWKPTR + Remote Wake-up FIFO Pointer +This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. + 24 + 5 + read-write + + + GLBLUCAST + Global Unicast +When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. + 9 + 1 + read-write + + + RWKPRCVD + Remote Wake-Up Frame Received +When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. + 6 + 1 + read-write + + + MGKPRCVD + Magic Packet Received +When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. + 5 + 1 + read-write + + + RWKPKTEN + Remote Wake-Up Frame Enable +When set, enables generation of a power management event because of remote wake-up frame reception. + 2 + 1 + read-write + + + MGKPKTEN + Magic Packet Enable +When set, enables generation of a power management event because of magic packet reception. + 1 + 1 + read-write + + + PWRDWN + Power Down +When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. The frames, received by the MAC after this bit is cleared, are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. + 0 + 1 + read-write + + + + + LPI_CSR + LPI Control and Status Regsiter + 0x30 + 32 + 0x00000000 + 0x000F030F + + + LPITXA + LPI TX Automate +This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + 19 + 1 + read-write + + + PLSEN + PHY Link Status Enable +This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. + 18 + 1 + read-write + + + PLS + PHY Link Status +This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. + 17 + 1 + read-write + + + LPIEN + LPI Enable +When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + 16 + 1 + read-write + + + RLPIST + Receive LPI State +When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. + 9 + 1 + read-write + + + TLPIST + Transmit LPI State +When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. + 8 + 1 + read-write + + + RLPIEX + Receive LPI Exit +When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 3 + 1 + read-write + + + RLPIEN + Receive LPI Entry +When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + 2 + 1 + read-write + + + TLPIEX + Transmit LPI Exit +When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. + 1 + 1 + read-write + + + TLPIEN + Transmit LPI Entry + When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. + 0 + 1 + read-write + + + + + LPI_TCR + LPI Timers Control Register + 0x34 + 32 + 0x00000000 + 0x03FFFFFF + + + LST + LPI LS TIMER +This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. + 16 + 10 + read-write + + + TWT + LPI TW TIMER +This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. + 0 + 16 + read-write + + + + + INTR_STATUS + Interrupt Status Register + 0x38 + 32 + 0x00000000 + 0x00000EFF + + + GPIIS + GPI Interrupt Status +When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved. + 11 + 1 + read-only + + + LPIIS + LPI Interrupt Status +When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. + 10 + 1 + read-only + + + TSIS + Timestamp Interrupt Status +When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - There is an overflow in the seconds register. - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). + 9 + 1 + read-only + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 7 + 1 + read-only + + + MMCTXIS + MMC Transmit Interrupt Status +This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 6 + 1 + read-only + + + MMCRXIS + MMC Receive Interrupt Status +This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + 5 + 1 + read-only + + + MMCIS + MMC Interrupt Status +This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. + 4 + 1 + read-only + + + PMTIS + PMT Interrupt Status +This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. + 3 + 1 + read-only + + + PCSANCIS + PCS Auto-Negotiation Complete +This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. + 2 + 1 + read-only + + + PCSLCHGIS + PCS Link Status Changed +This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. + 1 + 1 + read-only + + + RGSMIIIS + RGMII or SMII Interrupt Status +This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. + 0 + 1 + read-only + + + + + INTR_MASK + Interrupt Mask Register + 0x3c + 32 + 0x00000000 + 0x0000060F + + + LPIIM + LPI Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). + 10 + 1 + read-write + + + TSIM + Timestamp Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). + 9 + 1 + read-write + + + PMTIM + PMT Interrupt Mask + When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). + 3 + 1 + read-write + + + PCSANCIM + PCS AN Completion Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). + 2 + 1 + read-write + + + PCSLCHGIM + PCS Link Status Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). + 1 + 1 + read-write + + + RGSMIIIM + RGMII or SMII Interrupt Mask +When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). + 0 + 1 + read-write + + + + + MAC_ADDR_0_HIGH + MAC Address 0 High Register + 0x40 + 32 + 0x00000000 + 0x8000FFFF + + + AE + Address Enable + This bit is always set to 1. + 31 + 1 + read-only + + + ADDRHI + MAC Address0 [47:32] + This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 16 + read-write + + + + + MAC_ADDR_0_LOW + MAC Address 0 Low Register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address0 [31:0] + This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + 0 + 32 + read-write + + + + + MAC_ADDR_1_HIGH + MAC Address High Register + 0x48 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + MAC_ADDR_1_LOW + MAC Address Low Register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + MAC_ADDR_2_HIGH + MAC Address2 High Register + 0x50 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + MAC_ADDR_2_LOW + MAC Address2 Low Register + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + MAC_ADDR_3_HIGH + MAC Address3 High Register + 0x58 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + MAC_ADDR_3_LOW + MAC Address3 Low Register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + MAC_ADDR_4_HIGH + MAC Address4 High Register + 0x60 + 32 + 0x00000000 + 0xFF00FFFF + + + AE + Address Enable +When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + 31 + 1 + read-write + + + SA + Source Address +When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + 30 + 1 + read-write + + + MBC + Mask Byte Control +These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + 24 + 6 + read-write + + + ADDRHI + MAC Address1 [47:32] +This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + 0 + 16 + read-write + + + + + MAC_ADDR_4_LOW + MAC Address4 Low Register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDRLO + MAC Address1 [31:0] +This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + 0 + 32 + read-write + + + + + XMII_CSR + SGMII/RGMII/SMII Control and Status Register + 0xd8 + 32 + 0x00000000 + 0x0001003F + + + SMIDRXS + Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal. If the SMII PHY Interface with source synchronous mode is selected during core configuration, this bit is reserved (RO with default value). + 16 + 1 + read-only + + + FALSCARDET + False Carrier Detected + This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 5 + 1 + read-write + + + JABTO + Jabber Timeout + This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + 4 + 1 + read-write + + + LNKSTS + Link Status + This bit indicates whether the link between the local PHY and the remote PHY is up or down. It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. + 3 + 1 + read-write + + + LNKSPEED + Link Speed + This bit indicates the current speed of the link: +- 00: 2.5 MHz +- 01: 25 MHz +- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. + 1 + 2 + read-write + + + LNKMOD + Link Mode + This bit indicates the current mode of operation of the link: +- 1’b0: Half-duplex mode +- 1’b1: Full-duplex mode + 0 + 1 + read-write + + + + + WDOG_WTO + Watchdog Timeout Register + 0xdc + 32 + 0x00000000 + 0x00013FFF + + + PWE + Programmable Watchdog Enable + When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). + 16 + 1 + read-write + + + WTO + Watchdog Timeout +When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. + 0 + 14 + read-write + + + + + GPIO + General Purpose IO Register + 0xe0 + 32 + 0x00000000 + 0x0F0F0F0F + + + GPIT + No description avaiable + 24 + 4 + read-write + + + GPIE + No description avaiable + 16 + 4 + read-write + + + GPO + No description avaiable + 8 + 4 + read-write + + + GPIS + No description avaiable + 0 + 4 + read-write + + + + + MMC_CNTRL + MMC Control establishes the operating mode of MMC. + 0x100 + 32 + 0x00000000 + 0x0000013F + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames +When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). When reset, the MMC Counters are not updated for dropped Broadcast frames. + 8 + 1 + read-write + + + CNTPRSTLVL + Full-Half Preset +When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half +- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half +- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full +- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full +- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. + 5 + 1 + read-write + + + CNTPRST + Counters Preset +When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. + 4 + 1 + read-write + + + CNTFREEZ + MMC Counter Freeze +When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. + 3 + 1 + read-write + + + RSTONRD + Reset on Read +When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. + 2 + 1 + read-write + + + CNTSTOPRO + Counter Stop Rollover +When this bit is set, the counter does not roll over to zero after reaching the maximum value. + 1 + 1 + read-write + + + CNTRST + Counters Reset +When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle + 0 + 1 + read-write + + + + + MMC_INTR_RX + MMC Receive Interrupt maintains the interrupt generated from all +of the receive statistic counters. + 0x104 + 32 + 0x00000000 + 0x03FFFFFF + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status +This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status +This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status +This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status +This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status +This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status +This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status. +This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status +This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status +This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. +This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status +This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status +This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status +This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status +This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status +This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status +This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status +This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status +This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status +This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status +This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status +This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + MMC_INTR_TX + MMC Transmit Interrupt maintains the interrupt generated from all +of the transmit statistic counters + 0x108 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status +This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status +This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status +This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status +This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status +This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status +This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status +This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status +This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status +This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status +This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status +This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status +This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status +This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status +The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status +This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status +This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status +This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status +This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status +This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status +This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + MMC_INTR_MASK_RX + MMC Receive Interrupt mask maintains the mask for the interrupt +generated from all of the receive statistic counters + 0x10c + 32 + 0x00000000 + 0x03FFFFFE + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. +Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask. +Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + + + MMC_INTR_MASK_TX + MMC Transmit Interrupt Mask + 0x110 + 32 + 0x00000000 + 0x03FFFFFF + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. + 15 + 1 + read-write + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + 14 + 1 + read-write + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + TX256T511OCTGBFIM + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + TXOCTETCOUNT_GB + Number of bytes transmitted, exclusive of preamble and retried +bytes, in good and bad frames. + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. + 0 + 32 + read-write + + + + + TXFRAMECOUNT_GB + Number of good and bad frames transmitted, exclusive of retried +frames. + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted, exclusive of retried frames. + 0 + 32 + read-write + + + + + TXBROADCASTFRAMES_G + Number of good broadcast frames transmitted + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good broadcast frames transmitted. + 0 + 32 + read-write + + + + + TXMLTICASTFRAMES_G + Number of good multicast frames transmitted + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good multicast frames transmitted. + 0 + 32 + read-write + + + + + TX64OCTETS_GB + Number of good and bad frames transmitted with length 64 bytes, +exclusive of preamble and retried frames. + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX65TO127OCTETS_GB + Number of good and bad frames transmitted with length between +65 and 127 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX128TO255OCTETS_GB + Number of good and bad frames transmitted with length between +128 and 255 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX256TO511OCTETS_GB + Number of good and bad frames transmitted with length between +256 and 511 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX512TO1023OCTETS_GB + Number of good and bad frames transmitted with length between +512 and 1,023 (inclusive) bytes, exclusive of preamble and retried +frames. + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TX1024TOMAXOCTETS_GB + Number of good and bad frames transmitted with length between +1,024 and maxsize (inclusive) bytes, exclusive of preamble and +retried frames. + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + TXUNICASTFRAMES_GB + Number of good and bad unicast frames transmitted. + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad unicast frames transmitted. + 0 + 32 + read-write + + + + + TXMULTICASTFRAMES_GB + Number of good and bad multicast frames transmitted. + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad multicast frames transmitted. + 0 + 32 + read-write + + + + + TXBROADCASTFRAMES_GB + Number of good and bad broadcast frames transmitted. + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad broadcast frames transmitted. + 0 + 32 + read-write + + + + + TXUNDERFLOWERROR + Number of frames aborted because of frame underflow error. + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of frame underflow error. + 0 + 32 + read-write + + + + + TXSINGLECOL_G + Number of successfully transmitted frames after a single collision +in the half-duplex mode. + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of successfully transmitted frames after a single collision in the half-duplex mode. + 0 + 32 + read-write + + + + + TXMULTICOL_G + Number of successfully transmitted frames after multiple collisions +in the half-duplex mode. + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of successfully transmitted frames after multiple collisions in the half-duplex mode. + 0 + 32 + read-write + + + + + TXDEFERRED + Number of successfully transmitted frames after a deferral in the +half-duplex mode. + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of successfully transmitted frames after a deferral in the half-duplex mode. + 0 + 32 + read-write + + + + + TXLATECOL + Number of frames aborted because of late collision error + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of late collision error. + 0 + 32 + read-write + + + + + TXEXESSCOL + Number of frames aborted because of excessive (16) collision +errors + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of excessive (16) collision errors. + 0 + 32 + read-write + + + + + TXCARRIERERROR + Number of frames aborted because of carrier sense error (no +carrier or loss of carrier). + 0x160 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of carrier sense error (no carrier or loss of carrier). + 0 + 32 + read-write + + + + + TXOCTETCOUNT_G + Number of bytes transmitted, exclusive of preamble, only in good +frames. + 0x164 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes transmitted, exclusive of preamble, only in good frames. + 0 + 32 + read-write + + + + + TXFRAMECOUNT_G + Number of good frames transmitted + 0x168 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good frames transmitted. + 0 + 32 + read-write + + + + + TXEXCESSDEF + Number of frames aborted because of excessive deferral error +(deferred for more than two max-sized frame times). + 0x16c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames aborted because of excessive deferral error (deferred for more than two max-sized frame times). + 0 + 32 + read-write + + + + + TXPAUSEFRAMES + Number of good Pause frames transmitted + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good Pause frames transmitted. + 0 + 32 + read-write + + + + + TXVLANFRAMES_G + Number of good VLAN frames transmitted, exclusive of retried +frames. + 0x174 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good VLAN frames transmitted, exclusive of retried frames. + 0 + 32 + read-write + + + + + TXOVERSIZE_G + Number of frames transmitted without errors and with length +greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged +frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC +Configuration Register)). + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). + 0 + 32 + read-write + + + + + RXFRAMECOUNT_GB + Number of good and bad frames received + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received. + 0 + 32 + read-write + + + + + RXOCTETCOUNT_G + Number of bytes received, exclusive of preamble, only in good +frames. + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received, exclusive of preamble, in good and bad frames. + 0 + 32 + read-write + + + + + RXOCTETCOUNT_GB + Number of bytes received, exclusive of preamble, in good and bad +frames. + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received, exclusive of preamble, only in good frames. + 0 + 32 + read-write + + + + + RXBROADCASTFRAMES_G + Number of good broadcast frames received + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good broadcast frames received. + 0 + 32 + read-write + + + + + RXMULTICASTFRAMES_G + Number of good multicast frames received + 0x190 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good multicast frames received. + 0 + 32 + read-write + + + + + RXCRCERROR + Number of frames received with CRC error + 0x194 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with CRC error. + 0 + 32 + read-write + + + + + RXALIGNMENTERROR + Number of frames received with alignment (dribble) error. Valid +only in 10/100 mode + 0x198 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. + 0 + 32 + read-write + + + + + RXRUNTERROR + Number of frames received with runt (<64 bytes and CRC error) +error. + 0x19c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with runt (<64 bytes and CRC error) error. + 0 + 32 + read-write + + + + + RXJABBERERROR + Number of giant frames received with length (including CRC) +greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with +CRC error. If Jumbo Frame mode is enabled, then frames of +length greater than 9,018 bytes (9,022 for VLAN tagged) are +considered as giant frames. + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. + 0 + 32 + read-write + + + + + RXUNDERSIZE_G + Number of frames received with length less than 64 bytes, without +any errors. + 0x1a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with length less than 64 bytes, without any errors. + 0 + 32 + read-write + + + + + RXOVERSIZE_G + Number of frames received without errors, with length greater +than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 +bytes if enabled in Bit 27 of Register 0 (MAC Configuration +Register)) + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). + 0 + 32 + read-write + + + + + RX64OCTETS_GB + Number of good and bad frames received with length 64 bytes, +exclusive of preamble. + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length 64 bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX65TO127OCTETS_GB + No description avaiable + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX128TO255OCTETS_GB + No description avaiable + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX256TO511OCTETS_GB + Number of good and bad frames received with length between +256 and 511 (inclusive) bytes, exclusive of preamble. + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX512TO1023OCTETS_GB + Number of good and bad frames received with length between +512 and 1023 (inclusive) bytes, exclusive of preamble. + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. + 0 + 32 + read-write + + + + + RX1024TOMAXOCTETS_GB + Number of good and bad frames received with length between +1024 and maxsize (inclusive) bytes, exclusive of preamble. + 0x1c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + 0 + 32 + read-write + + + + + RXUNICASTFRAMES_G + Number of received good unicast frames. + 0x1c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of received good unicast frames. + 0 + 32 + read-write + + + + + RXLENGTHERROR + Number of frames received with length error (Length type field ≠ +frame size), for all frames with valid length field. + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with length error (Length type field ≠ frame size), for all frames with valid length field. + 0 + 32 + read-write + + + + + RXOUTOFRANGETYPE + Number of frames received with length field not equal to the valid +frame size (greater than 1,500 but less than 1,536). + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). + 0 + 32 + read-write + + + + + RXPAUSEFRAMES + Number of good and valid Pause frames received. + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and valid Pause frames received. + 0 + 32 + read-write + + + + + RXFIFOOVERFLOW + Number of missed received frames because of FIFO overflow. +This counter is not present in the GMAC-CORE configuration. + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of missed received frames because of FIFO overflow. This counter is not present in the GMAC-CORE configuration. + 0 + 32 + read-write + + + + + RXVLANFRAMES_GB + Number of good and bad VLAN frames received. + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good and bad VLAN frames received. + 0 + 32 + read-write + + + + + RXWATCHDOGERROR + Number of frames received with error because of watchdog +timeout error (frames with a data load larger than 2,048 bytes or +the value programmed in Register 55 (Watchdog Timeout +Register)). + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with error because of watchdog timeout error (frames with a data load larger than 2,048 bytes or the value programmed in Register 55 (Watchdog Timeout Register)). + 0 + 32 + read-write + + + + + RXRCVERROR + Number of frames received with Receive error or Frame Extension +error on the GMII or MII interface. + 0x1e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. + 0 + 32 + read-write + + + + + RXCTRLFRAMES_G + Number of received good control frames + 0x1e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of received good control frames. + 0 + 32 + read-write + + + + + MMC_IPC_INTR_MASK_RX + MMC IPC Receive Checksum Offload Interrupt Mask maintains +the mask for the interrupt generated from the receive IPC statistic +counters. + 0x200 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIM + MMC Receive ICMP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIM + MMC Receive ICMP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIM + MMC Receive TCP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIM + MMC Receive TCP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + 26 + 1 + read-write + + + RXUDPEROIM + MMC Receive UDP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIM + MMC Receive IPV6 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIM + MMC Receive IPV6 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIM + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIM + MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIM + MMC Receive IPV4 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIM + MMC Receive IPV4 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIM + MMC Receive IPV4 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIM + MMC Receive ICMP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIM + MMC Receive ICMP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIM + MMC Receive TCP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIM + MMC Receive TCP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIM + MMC Receive UDP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIM + MMC Receive UDP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIM + MMC Receive IPV6 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIM + MMC Receive IPV6 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIM + MMC Receive IPV6 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIM + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIM + MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIM + MMC Receive IPV4 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIM + MMC Receive IPV4 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIM + MMC Receive IPV4 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + MMC_IPC_INTR_RX + MMC Receive Checksum Offload Interrupt maintains the interrupt +that the receive IPC statistic counters generate. See Table 4-25 +for further detail. + 0x208 + 32 + 0x00000000 + 0x3FFF3FFF + + + RXICMPEROIS + MMC Receive ICMP Error Octet Counter Interrupt Status +This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 + read-write + + + RXICMPGOIS + MMC Receive ICMP Good Octet Counter Interrupt Status +This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 + read-write + + + RXTCPEROIS + MMC Receive TCP Error Octet Counter Interrupt Status +This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 + read-write + + + RXTCPGOIS + MMC Receive TCP Good Octet Counter Interrupt Status +This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value + 26 + 1 + read-write + + + RXUDPEROIS + MMC Receive UDP Error Octet Counter Interrupt Status +This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 + read-write + + + RXUDPGOIS + MMC Receive UDP Good Octet Counter Interrupt Status +This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 + read-write + + + RXIPV6NOPAYOIS + MMC Receive IPV6 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 + read-write + + + RXIPV6HEROIS + MMC Receive IPV6 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 + read-write + + + RXIPV6GOIS + MMC Receive IPV6 Good Octet Counter Interrupt Status +This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 + read-write + + + RXIPV4UDSBLOIS + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status +This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 + read-write + + + RXIPV4FRAGOIS + MMC Receive IPV4 Fragmented Octet Counter Interrupt Status +This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 + read-write + + + RXIPV4NOPAYOIS + MMC Receive IPV4 No Payload Octet Counter Interrupt Status +This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 + read-write + + + RXIPV4HEROIS + MMC Receive IPV4 Header Error Octet Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 + read-write + + + RXIPV4GOIS + MMC Receive IPV4 Good Octet Counter Interrupt Status +This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 + read-write + + + RXICMPERFIS + MMC Receive ICMP Error Frame Counter Interrupt Status +This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 + read-write + + + RXICMPGFIS + MMC Receive ICMP Good Frame Counter Interrupt Status +This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 + read-write + + + RXTCPERFIS + MMC Receive TCP Error Frame Counter Interrupt Status +This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 + read-write + + + RXTCPGFIS + MMC Receive TCP Good Frame Counter Interrupt Status +This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 + read-write + + + RXUDPERFIS + MMC Receive UDP Error Frame Counter Interrupt Status +This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 + read-write + + + RXUDPGFIS + MMC Receive UDP Good Frame Counter Interrupt Status +This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 + read-write + + + RXIPV6NOPAYFIS + MMC Receive IPV6 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 + read-write + + + RXIPV6HERFIS + MMC Receive IPV6 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 + read-write + + + RXIPV6GFIS + MMC Receive IPV6 Good Frame Counter Interrupt Status +This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 + read-write + + + RXIPV4UDSBLFIS + MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status +This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + 4 + 1 + read-write + + + RXIPV4FRAGFIS + MMC Receive IPV4 Fragmented Frame Counter Interrupt Status +This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + 3 + 1 + read-write + + + RXIPV4NOPAYFIS + MMC Receive IPV4 No Payload Frame Counter Interrupt Status +This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + 2 + 1 + read-write + + + RXIPV4HERFIS + MMC Receive IPV4 Header Error Frame Counter Interrupt Status +This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 1 + 1 + read-write + + + RXIPV4GFIS + MMC Receive IPV4 Good Frame Counter Interrupt Status +This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + 0 + 1 + read-write + + + + + RXIPV4_GD_FMS + Number of good IPv4 datagrams received with the TCP, UDP, or +ICMP payload + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload + 0 + 32 + read-write + + + + + RXIPV4_HDRERR_FRMS + Number of IPv4 datagrams received with header (checksum, +length, or version mismatch) errors + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors + 0 + 32 + read-write + + + + + RXIPV4_NOPAY_FRMS + Number of IPv4 datagram frames received that did not have a +TCP, UDP, or ICMP payload processed by the Checksum engine + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine + 0 + 32 + read-write + + + + + RXIPV4_FRAG_FRMS + Number of good IPv4 datagrams with fragmentation + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv4 datagrams with fragmentation + 0 + 32 + read-write + + + + + RXIPV4_UDSBL_FRMS + Number of good IPv4 datagrams received that had a UDP +payload with checksum disabled + 0x220 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv4 datagrams received that had a UDP payload with checksum disabled + 0 + 32 + read-write + + + + + RXIPV6_GD_FRMS + Number of good IPv6 datagrams received with TCP, UDP, or +ICMP payloads + 0x224 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads + 0 + 32 + read-write + + + + + RXIPV6_HDRERR_FRMS + Number of IPv6 datagrams received with header errors (length or +version mismatch) + 0x228 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of IPv6 datagrams received with header errors (length or version mismatch) + 0 + 32 + read-write + + + + + RXIPV6_NOPAY_FRMS + Number of IPv6 datagram frames received that did not have a +TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with +fragmentation or security extension headers + 0x22c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers + 0 + 32 + read-write + + + + + RXUDP_GD_FRMS + Number of good IP datagrams with a good UDP payload. This +counter is not updated when the rxipv4_udsbl_frms counter is +incremented. + 0x230 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. + 0 + 32 + read-write + + + + + RXUDP_ERR_FRMS + Number of good IP datagrams whose UDP payload has a +checksum error + 0x234 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams whose UDP payload has a checksum error + 0 + 32 + read-write + + + + + RXTCP_GD_FRMS + Number of good IP datagrams with a good TCP payload + 0x238 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams with a good TCP payload + 0 + 32 + read-write + + + + + RXTCP_ERR_FRMS + Number of good IP datagrams whose TCP payload has a +checksum error + 0x23c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams whose TCP payload has a checksum error + 0 + 32 + read-write + + + + + RXICMP_GD_FRMS + Number of good IP datagrams with a good ICMP payload + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams with a good ICMP payload + 0 + 32 + read-write + + + + + RXICMP_ERR_FRMS + Number of good IP datagrams whose ICMP payload has a +checksum error + 0x244 + 32 + 0x00000000 + 0xFFFFFFFF + + + FRMCNT + Number of good IP datagrams whose ICMP payload has a checksum error + 0 + 32 + read-write + + + + + RXIPV4_GD_OCTETS + Number of bytes received in good IPv4 datagrams encapsulating +TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad +bytes are not included in this counter or in the octet counters listed +below). + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). + 0 + 32 + read-write + + + + + RXIPV4_HDRERR_OCTETS + Number of bytes received in IPv4 datagrams with header errors +(checksum, length, version mismatch). The value in the Length +field of IPv4 header is used to update this counter. + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. + 0 + 32 + read-write + + + + + RXIPV4_NOPAY_OCTETS + Number of bytes received in IPv4 datagrams that did not have a +TCP, UDP, or ICMP payload. The value in the IPv4 header’s +Length field is used to update this counter. + 0x258 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header’s Length field is used to update this counter. + 0 + 32 + read-write + + + + + RXIPV4_FRAG_OCTETS + Number of bytes received in fragmented IPv4 datagrams. The +value in the IPv4 header’s Length field is used to update this +counter + 0x25c + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header’s Length field is used to update this counter. + 0 + 32 + read-write + + + + + RXIPV4_UDSBL_OCTETS + Number of bytes received in a UDP segment that had the UDP +checksum disabled. This counter does not count IP Header bytes. + 0x260 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. + 0 + 32 + read-write + + + + + RXIPV6_GD_OCTETS + Number of bytes received in good IPv6 datagrams encapsulating +TCP, UDP or ICMPv6 data + 0x264 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data + 0 + 32 + read-write + + + + + RXIPV6_HDRERR_OCTETS + Number of bytes received in IPv6 datagrams with header errors +(length, version mismatch). The value in the IPv6 header’s Length +field is used to update this counter. + 0x268 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header’s Length field is used to update this counter. + 0 + 32 + read-write + + + + + RXIPV6_NOPAY_OCTETS + Number of bytes received in IPv6 datagrams that did not have a +TCP, UDP, or ICMP payload. The value in the IPv6 header’s +Length field is used to update this counter. + 0x26c + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header’s Length field is used to update this counter. + 0 + 32 + read-write + + + + + RXUDP_GD_OCTETS + Number of bytes received in a good UDP segment. This counter +(and the counters below) does not count IP header bytes. + 0x270 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. + 0 + 32 + read-write + + + + + RXUDP_ERR_OCTETS + Number of bytes received in a UDP segment that had checksum +errors + 0x274 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a UDP segment that had checksum errors + 0 + 32 + read-write + + + + + RXTCP_GD_OCTETS + Number of bytes received in a good TCP segment + 0x278 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a good TCP segment + 0 + 32 + read-write + + + + + RXTCP_ERR_OCTETS + Number of bytes received in a TCP segment with checksum +errors + 0x27c + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a TCP segment with checksum errors + 0 + 32 + read-write + + + + + RXICMP_GD_OCTETS + Number of bytes received in a good ICMP segment + 0x280 + 32 + 0x00000000 + 0xFFFFFFFF + + + BYTECNT + Number of bytes received in a good ICMP segment + 0 + 32 + read-write + + + + + L3_L4_CFG_0_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x400 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L3_L4_CFG_0_L4_ADDR + Layer 4 Address Register + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_L4_CFG_0_L3_ADDR_0 + Layer 3 Address 0 Register + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_0_L3_ADDR_1 + Layer 3 Address 1 Register + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_0_L3_ADDR_2 + Layer 3 Address 2 Register + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_0_L3_ADDR_3 + Layer 3 Address 3 Register + 0x41c + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_1_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x430 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L3_L4_CFG_1_L4_ADDR + Layer 4 Address Register + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_L4_CFG_1_L3_ADDR_0 + Layer 3 Address 0 Register + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_1_L3_ADDR_1 + Layer 3 Address 1 Register + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_1_L3_ADDR_2 + Layer 3 Address 2 Register + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_1_L3_ADDR_3 + Layer 3 Address 3 Register + 0x44c + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_2_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x460 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L3_L4_CFG_2_L4_ADDR + Layer 4 Address Register + 0x464 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_L4_CFG_2_L3_ADDR_0 + Layer 3 Address 0 Register + 0x470 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_2_L3_ADDR_1 + Layer 3 Address 1 Register + 0x474 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_2_L3_ADDR_2 + Layer 3 Address 2 Register + 0x478 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_2_L3_ADDR_3 + Layer 3 Address 3 Register + 0x47c + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_3_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x490 + 32 + 0x00000000 + 0x003DFFFD + + + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + + + L3_L4_CFG_3_L4_ADDR + Layer 4 Address Register + 0x494 + 32 + 0x00000000 + 0xFFFFFFFF + + + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + 0 + 16 + read-write + + + + + L3_L4_CFG_3_L3_ADDR_0 + Layer 3 Address 0 Register + 0x4a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_3_L3_ADDR_1 + Layer 3 Address 1 Register + 0x4a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + 0 + 32 + read-write + + + + + L3_L4_CFG_3_L3_ADDR_2 + Layer 3 Address 2 Register + 0x4a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + L3_L4_CFG_3_L3_ADDR_3 + Layer 3 Address 3 Register + 0x4ac + 32 + 0x00000000 + 0xFFFFFFFF + + + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER0 + Hash Table Register 0 + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER1 + Hash Table Register 1 + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER2 + Hash Table Register 2 + 0x508 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER3 + Hash Table Register 3 + 0x50c + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER4 + Hash Table Register 4 + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER5 + Hash Table Register 5 + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER6 + Hash Table Register 6 + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + HASH_TABLE_REGISTER7 + Hash Table Register 7 + 0x51c + 32 + 0x00000000 + 0xFFFFFFFF + + + HT31T0 + First 32 bits of Hash Table + This field contains the first 32 Bits (31:0) of the Hash table. + 0 + 32 + read-write + + + + + VLAN_TAG_INC_RPL + VLAN Tag Inclusion or Replacement Register + 0x584 + 32 + 0x00000000 + 0x000FFFFF + + + CSVL + C-VLAN or S-VLAN + When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. + 19 + 1 + read-write + + + VLP + VLAN Priority Control +When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. + 18 + 1 + read-write + + + VLC + VLAN Tag Control in Transmit Frames +- 2’b00: No VLAN tag deletion, insertion, or replacement +- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. +- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. +- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. + 16 + 2 + read-write + + + VLT + VLAN Tag for Transmit Frames + This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. + 0 + 16 + read-write + + + + + VLAN_HASH + VLAN Hash Table Register + 0x588 + 32 + 0x00000000 + 0x0000FFFF + + + VLHT + VLAN Hash Table + This field contains the 16-bit VLAN Hash Table. + 0 + 16 + read-write + + + + + TS_CTRL + Timestamp Control Register + 0x700 + 32 + 0x00000000 + 0x1F07FF3F + + + ATSEN3 + Auxiliary Snapshot 3 Enable +This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. + 28 + 1 + read-write + + + ATSEN2 + Auxiliary Snapshot 2 Enable +This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. + 27 + 1 + read-write + + + ATSEN1 + Auxiliary Snapshot 1 Enable +This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. + 26 + 1 + read-write + + + ATSEN0 + Auxiliary Snapshot 0 Enable +This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. + 25 + 1 + read-write + + + ATSFC + Auxiliary Snapshot FIFO Clear +When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. + 24 + 1 + read-write + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering +When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. + 18 + 1 + read-write + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. + 16 + 2 + read-write + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master +When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. + 15 + 1 + read-write + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages +When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. + 14 + 1 + read-write + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. + 13 + 1 + read-write + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP +When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. + 12 + 1 + read-write + + + TSIPENA + Enable Processing of PTP over Ethernet Frames +When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets + 11 + 1 + read-write + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format +When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. + 10 + 1 + read-write + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control +When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. + 9 + 1 + read-write + + + TSENALL + Enable Timestamp for All Frames +When set, the timestamp snapshot is enabled for all frames received by the MAC. + 8 + 1 + read-write + + + TSADDREG + Addend Reg Update +When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. + 5 + 1 + read-write + + + TSTRIG + Timestamp Interrupt Trigger Enable +When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. + 4 + 1 + read-write + + + TSUPDT + Timestamp Update +When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. + 3 + 1 + read-write + + + TSINIT + Timestamp Initialize +When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. + 2 + 1 + read-write + + + TSCFUPDT + Timestamp Fine or Coarse Update +When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. + 1 + 1 + read-write + + + TSENA + Timestamp Enable +When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. + 0 + 1 + read-write + + + + + SUB_SEC_INCR + Sub-Second Increment Register + 0x704 + 32 + 0x00000000 + 0x000000FF + + + SSINC + Sub-second Increment Value +The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. + 0 + 8 + read-write + + + + + SYST_SEC + System Time - Seconds Register + 0x708 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the current value in seconds of the System Time maintained by the MAC. + 0 + 32 + read-write + + + + + SYST_NSEC + System Time - Nanoseconds Register + 0x70c + 32 + 0x00000000 + 0x7FFFFFFF + + + TSSS + Timestamp Sub Seconds + The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. + 0 + 31 + read-write + + + + + SYST_SEC_UPD + System Time - Seconds Update Register + 0x710 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSS + Timestamp Second + The value in this field indicates the time in seconds to be initialized or added to the system time. + 0 + 32 + read-write + + + + + SYST_NSEC_UPD + System Time - Nanoseconds Update Register + 0x714 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDSUB + Add or Subtract Time + When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. + 31 + 1 + read-write + + + TSSS + Timestamp Sub Seconds +The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. + 0 + 31 + read-write + + + + + TS_ADDEND + Timestamp Addend Register + 0x718 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSAR + Timestamp Addend Register +This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. + 0 + 32 + read-write + + + + + TGTTM_SEC + Target Time Seconds Register + 0x71c + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTR + Target Time Seconds Register + This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + TGTTM_NSEC + Target Time Nanoseconds Register + 0x720 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY + Target Time Register Busy + The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. + 31 + 1 + read-write + + + TTSLO + Target Timestamp Low Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + SYSTM_H_SEC + System Time - Higher Word Seconds Register + 0x724 + 32 + 0x00000000 + 0x0000FFFF + + + TSHWR + Timestamp Higher Word Register +This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. + 0 + 16 + read-write + + + + + TS_STATUS + Timestamp Status Register + 0x728 + 32 + 0x00000000 + 0x3F0F03FF + + + ATSNS + Number of Auxiliary Timestamp Snapshots +This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 25 + 5 + read-only + + + ATSSTM + Auxiliary Timestamp Snapshot Trigger Missed + This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 24 + 1 + read-only + + + ATSSTN + Auxiliary Timestamp Snapshot Trigger Identifier +These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. + 16 + 4 + read-only + + + TSTRGTERR3 + Timestamp Target Time Error +This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. + 9 + 1 + read-only + + + TSTARGT3 + Timestamp Target Time Reached for Target Time PPS3 +When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). + 8 + 1 + read-only + + + TSTRGTERR2 + No description avaiable + 7 + 1 + read-only + + + TSTARGT2 + No description avaiable + 6 + 1 + read-only + + + TSTRGTERR1 + No description avaiable + 5 + 1 + read-only + + + TSTARGT1 + No description avaiable + 4 + 1 + read-only + + + TSTRGTERR + No description avaiable + 3 + 1 + read-only + + + AUXTSTRIG + No description avaiable + 2 + 1 + read-only + + + TSTARGT + No description avaiable + 1 + 1 + read-only + + + TSSOVF + No description avaiable + 0 + 1 + read-only + + + + + PPS_CTRL + PPS Control Register + 0x72c + 32 + 0x00000000 + 0x6767677F + + + TRGTMODSEL3 + Target Time Register Mode for PPS3 Output +This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. + 29 + 2 + read-write + + + PPSCMD3 + Flexible PPS3 Output Control +This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 24 + 3 + read-write + + + TRGTMODSEL2 + Target Time Register Mode for PPS2 Output +This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. + 21 + 2 + read-write + + + PPSCMD2 + Flexible PPS2 Output Control +This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 16 + 3 + read-write + + + TRGTMODSEL1 + Target Time Register Mode for PPS1 Output +This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. + 13 + 2 + read-write + + + PPSCMD1 + Flexible PPS1 Output Control +This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 8 + 3 + read-write + + + TRGTMODSEL0 + Target Time Register Mode for PPS0 Output + This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: +- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. +- 01: Reserved +- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. +- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. + 5 + 2 + read-write + + + PPSEN0 + Flexible PPS Output Mode Enable +When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. + 4 + 1 + read-write + + + PPSCTRL0 + PPSCTRL0: PPS0 Output Frequency Control +This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: +- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. +- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. +- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. +- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... +- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) + 0 + 4 + read-write + + + + + AUX_TS_NSEC + Auxiliary Timestamp - Nanoseconds Register + 0x730 + 32 + 0x00000000 + 0x7FFFFFFF + + + AUXTSLO + Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. + 0 + 31 + read-write + + + + + AUX_TS_SEC + Auxiliary Timestamp - Seconds Register + 0x734 + 32 + 0x00000000 + 0xFFFFFFFF + + + AUXTSHI + Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. + 0 + 32 + read-write + + + + + PPS0_INTERVAL + PPS0 Interval Register + 0x760 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS0 Output Signal Interval +These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS0_WIDTH + PPS0 Width Register + 0x764 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS0 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_1_TGTTM_SEC + PPS Target Time Seconds Register + 0x780 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + PPS_1_TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x784 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + PPS_1_INTERVAL + PPS Interval Register + 0x788 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_1_WIDTH + PPS Width Register + 0x78c + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_2_TGTTM_SEC + PPS2 Target Time Seconds Register + 0x7a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + PPS_2_TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x7a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + PPS_2_INTERVAL + PPS Interval Register + 0x7a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_2_WIDTH + PPS Width Register + 0x7ac + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_3_TGTTM_SEC + PPS3 Target Time Seconds Register + 0x7c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 + read-write + + + + + PPS_3_TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x7c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 + read-write + + + + + PPS_3_INTERVAL + PPS Interval Register + 0x7c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 + read-write + + + + + PPS_3_WIDTH + PPS Width Register + 0x7cc + 32 + 0x00000000 + 0xFFFFFFFF + + + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 + read-write + + + + + DMA_BUS_MODE + Bus Mode Register + 0x1000 + 32 + 0x00000000 + 0xBFFFFFFF + + + RIB + Rebuild INCRx Burst +When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. + 31 + 1 + read-write + + + PRWG + Channel Priority +Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. +- 00: The priority weight is 1. +- 01: The priority weight is 2. +- 10: The priority weight is 3. +- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). + 28 + 2 + read-write + + + TXPR + Transmit Priority +When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). + 27 + 1 + read-write + + + MB + Mixed Burst +When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. + 26 + 1 + read-write + + + AAL + Address-Aligned Beats +When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. + 25 + 1 + read-write + + + PBLX8 + PBLx8 Mode +When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. + 24 + 1 + read-write + + + USP + Use Separate PBL +When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. + 23 + 1 + read-write + + + RPBL + Rx DMA PBL +This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. + 17 + 6 + read-write + + + FB + Fixed Burst + This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. + 16 + 1 + read-write + + + PR + Priority Ratio + These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. +- 00: The Priority Ratio is 1:1. +- 01: The Priority Ratio is 2:1. +- 10: The Priority Ratio is 3:1. +- 11: The Priority Ratio is 4:1. + 14 + 2 + read-write + + + PBL + Programmable Burst Length +These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. + 8 + 6 + read-write + + + ATDS + Alternate Descriptor Size +When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). + 7 + 1 + read-write + + + DSL + Descriptor Skip Length +This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. + 2 + 5 + read-write + + + DA + DMA Arbitration Scheme +This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. +- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). +- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. + 1 + 1 + read-write + + + SWR + Software Reset + When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. + 0 + 1 + read-write + + + + + DMA_TX_POLL_DEMAND + Transmit Poll Demand Register + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPD + Transmit Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. + 0 + 32 + read-write + + + + + DMA_RX_POLL_DEMAND + Receive Poll Demand Register + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + RPD + Receive Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. + 0 + 32 + read-write + + + + + DMA_RX_DESC_LIST_ADDR + Receive Descriptor List Address Register + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + RDESLA + Start of Receive List +This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_TX_DESC_LIST_ADDR + Transmit Descriptor List Address Register + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDESLA + Start of Transmit List +This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + 0 + 32 + read-write + + + + + DMA_STATUS + Status Register + 0x1014 + 32 + 0x00000000 + 0x7FFFE7FF + + + GLPII + GLPII: GMAC LPI Interrupt (for Channel 0) +This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. + 30 + 1 + read-write + + + TTI + Timestamp Trigger Interrupt +This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. + 29 + 1 + read-write + + + GPI + GMAC PMT Interrupt +This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. + 28 + 1 + read-write + + + GMI + GMAC MMC Interrupt + This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. + 27 + 1 + read-write + + + GLI + GMAC Line Interface Interrupt +When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. + 26 + 1 + read-write + + + EB + Error Bits +This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. +- 0 0 0: Error during Rx DMA Write Data Transfer +- 0 1 1: Error during Tx DMA Read Data Transfer +- 1 0 0: Error during Rx DMA Descriptor Write Access +- 1 0 1: Error during Tx DMA Descriptor Write Access +- 1 1 0: Error during Rx DMA Descriptor Read Access +- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. + 23 + 3 + read-write + + + TS + Transmit Process State +This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped; Reset or Stop Transmit Command issued +- 3’b001: Running; Fetching Transmit Transfer Descriptor +- 3’b010: Running; Waiting for status +- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) +- 3’b100: TIME_STAMP write state +- 3’b101: Reserved for future use +- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow +- 3’b111: Running; Closing Transmit Descriptor + 20 + 3 + read-write + + + RS + Receive Process State +This field indicates the Receive DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped: Reset or Stop Receive Command issued +- 3’b001: Running: Fetching Receive Transfer Descriptor +- 3’b010: Reserved for future use +- 3’b011: Running: Waiting for receive packet +- 3’b100: Suspended: Receive Descriptor Unavailable +- 3’b101: Running: Closing Receive Descriptor +- 3’b110: TIME_STAMP write state +- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory + 17 + 3 + read-write + + + NIS + Normal Interrupt Summary +Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. + 16 + 1 + read-write + + + AIS + Abnormal Interrupt Summary +Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. + 15 + 1 + read-write + + + ERI + Early Receive Interrupt +This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). + 14 + 1 + read-write + + + FBI + Fatal Bus Error Interrupt +This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. + 13 + 1 + read-write + + + ETI + Early Transmit Interrupt +This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + 10 + 1 + read-write + + + RWT + Receive Watchdog Timeout +When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + 9 + 1 + read-write + + + RPS + Receive Process Stopped +This bit is asserted when the Receive Process enters the Stopped state. + 8 + 1 + read-write + + + RU + Receive Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. + 7 + 1 + read-write + + + RI + Receive Interrupt +This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. + 6 + 1 + read-write + + + UNF + Transmit Underflow +This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + 5 + 1 + read-write + + + OVF + Receive Overflow +This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. + 4 + 1 + read-write + + + TJT + Transmit Jabber Timeout +This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + 3 + 1 + read-write + + + TU + Transmit Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. + 2 + 1 + read-write + + + TPS + Transmit Process Stopped +This bit is set when the transmission is stopped. + 1 + 1 + read-write + + + TI + Transmit Interrupt +This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. + 0 + 1 + read-write + + + + + DMA_OP_MODE + Operation Mode Register + 0x1018 + 32 + 0x00000000 + 0x13F1FFFE + + + DT + Disable Dropping of TCP/IP Checksum Error Frames +When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). + 28 + 1 + read-write + + + RSF + Receive Store and Forward +When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. + 25 + 1 + read-write + + + DFF + Disable Flushing of Received Frames +When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) + 24 + 1 + read-write + + + RFA_2 + MSB of Threshold for Activating Flow Control +If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 23 + 1 + read-write + + + RFD_2 + MSB of Threshold for Deactivating Flow Control +If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 22 + 1 + read-write + + + TSF + Transmit Store and Forward +When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. + 21 + 1 + read-write + + + FTF + Flush Transmit FIFO +When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. + 20 + 1 + read-write + + + TTC + Transmit Threshold Control +These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. +- 000: 64 +- 001: 128 +- 010: 192 +- 011: 256 +- 100: 40 +- 101: 32 +- 110: 24 +- 111: 16 + 14 + 3 + read-write + + + ST + Start or Stop Transmission Command +When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. + 13 + 1 + read-write + + + RFD + Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. +- 00: Full minus 1 KB, that is, FULL — 1 KB +- 01: Full minus 2 KB, that is, FULL — 2 KB +- 10: Full minus 3 KB, that is, FULL — 3 KB +- 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. + 11 + 2 + read-write + + + RFA + Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. +- 00: Full minus 1 KB, that is, FULL—1KB. +- 01: Full minus 2 KB, that is, FULL—2KB. +- 10: Full minus 3 KB, that is, FULL—3KB. +- 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition + 9 + 2 + read-write + + + EFC + Enable HW Flow Control +When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. + 8 + 1 + read-write + + + FEF + Forward Error Frames +When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. + 7 + 1 + read-write + + + FUF + Forward Undersized Good Frames +When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. + 6 + 1 + read-write + + + DGF + Drop Giant Frames +When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). + 5 + 1 + read-write + + + RTC + Receive Threshold Control +These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. +- 00: 64 +- 01: 32 +- 10: 96 +- 11: 128 + 3 + 2 + read-write + + + OSF + Operate on Second Frame +When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + 2 + 1 + read-write + + + SR + Start or Stop Receive +When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. + 1 + 1 + read-write + + + + + DMA_INTR_EN + Interrupt Enable Register + 0x101c + 32 + 0x00000000 + 0x0001E7FF + + + NIE + Normal Interrupt Summary Enable +When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt + 16 + 1 + read-write + + + AIE + Abnormal Interrupt Summary Enable +When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error + 15 + 1 + read-write + + + ERE + Early Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. + 14 + 1 + read-write + + + FBE + Fatal Bus Error Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. + 13 + 1 + read-write + + + ETE + Early Transmit Interrupt Enable +When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. + 10 + 1 + read-write + + + RWE + Receive Watchdog Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. + 9 + 1 + read-write + + + RSE + Receive Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. + 8 + 1 + read-write + + + RUE + Receive Buffer Unavailable Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. + 7 + 1 + read-write + + + RIE + Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. + 6 + 1 + read-write + + + UNE + Underflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. + 5 + 1 + read-write + + + OVE + Overflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. + 4 + 1 + read-write + + + TJE + Transmit Jabber Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. + 3 + 1 + read-write + + + TUE + Transmit Buffer Unavailable Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. + 2 + 1 + read-write + + + TSE + Transmit Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. + 1 + 1 + read-write + + + TIE + Transmit Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. + 0 + 1 + read-write + + + + + DMA_MISS_OVF_CNT + Missed Frame And Buffer Overflow Counter Register + 0x1020 + 32 + 0x00000000 + 0x1FFFFFFF + + + ONFCNTOVF + Overflow Bit for FIFO Overflow Counter +This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 28 + 1 + read-write + + + OVFFRMCNT + Overflow Frame Counter +This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. + 17 + 11 + read-write + + + MISCNTOVF + Overflow Bit for Missed Frame Counter +This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 16 + 1 + read-write + + + MISFRMCNT + Missed Frame Counter +This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. + 0 + 16 + read-write + + + + + DMA_RX_INTR_WDOG + Receive Interrupt Watchdog Timer Register + 0x1024 + 32 + 0x00000000 + 0x000000FF + + + RIWT + RI Watchdog Timer Count +This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + 0 + 8 + read-write + + + + + DMA_AXI_MODE + AXI Bus Mode Register + 0x1028 + 32 + 0x00000000 + 0xC0FF30FF + + + EN_LPI + Enable Low Power Interface (LPI) +When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. + 31 + 1 + read-write + + + LPI_XIT_FRM + Unlock on Magic Packet or Remote Wake-Up Frame +When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. + 30 + 1 + read-write + + + WR_OSR_LMT + AXI Maximum Write Outstanding Request Limit +This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. + 20 + 4 + read-write + + + RD_OSR_LMT + AXI Maximum Read Outstanding Request Limit +This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. + 16 + 4 + read-write + + + ONEKBBE + 1 KB Boundary Crossing Enable for the GMAC-AXI Master +When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. + 13 + 1 + read-write + + + AXI_AAL + Address-Aligned Beats +This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. + 12 + 1 + read-write + + + BLEN256 + AXI Burst Length 256 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). + 7 + 1 + read-write + + + BLEN128 + AXI Burst Length 128 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). + 6 + 1 + read-write + + + BLEN64 + AXI Burst Length 64 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). + 5 + 1 + read-write + + + BLEN32 + AXI Burst Length 32 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). + 4 + 1 + read-write + + + BLEN16 + AXI Burst Length 16 +When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. + 3 + 1 + read-write + + + BLEN8 + AXI Burst Length 8 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 2 + 1 + read-write + + + BLEN4 + AXI Burst Length 4 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 1 + 1 + read-write + + + UNDEF + AXI Undefined Burst Length +This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. + 0 + 1 + read-write + + + + + DMA_BUS_STATUS + AHB or AXI Status Register + 0x102c + 32 + 0x00000000 + 0x00000003 + + + AXIRDSTS + AXI Master Read Channel Status +When high, it indicates that AXI master's read channel is active and transferring data. + 1 + 1 + read-write + + + AXWHSTS + AXI Master Write Channel or AHB Master Status +When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. + 0 + 1 + read-write + + + + + DMA_CURR_HOST_TX_DESC + Current Host Transmit Descriptor Register + 0x1048 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTDESAPTR + Host Transmit Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_DESC + Current Host Receive Descriptor Register + 0x104c + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRDESAPTR + Host Receive Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_TX_BUF + Current Host Transmit Buffer Address Register + 0x1050 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURTBUFAPTR + Host Transmit Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_CURR_HOST_RX_BUF + Current Host Receive Buffer Address Register + 0x1054 + 32 + 0x00000000 + 0xFFFFFFFF + + + CURRBUFAPTR + Host Receive Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. + 0 + 32 + read-write + + + + + DMA_HW_FEATURE + HW Feature Register + 0x1058 + 32 + 0x00000000 + 0x7FFFFFFF + + + ACTPHYIF + Active or selected PHY interface +When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. +- 000: GMII or MII +- 001: RGMII +- 010: SGMII +- 011: TBI +- 100: RMII +- 101: RTBI +- 110: SMII +- 111: RevMII - All Others: Reserved + 28 + 3 + read-write + + + SAVLANINS + Source Address or VLAN Insertion + 27 + 1 + read-write + + + FLEXIPPSEN + Flexible Pulse-Per-Second Output + 26 + 1 + read-write + + + INTTSEN + Timestamping with Internal System Time + 25 + 1 + read-write + + + ENHDESSEL + Alternate (Enhanced Descriptor) + 24 + 1 + read-write + + + TXCHCNT + Number of additional Tx Channels + 22 + 2 + read-write + + + RXCHCNT + Number of additional Rx Channels + 20 + 2 + read-write + + + RXFIFOSIZE + Rx FIFO > 2,048 Bytes + 19 + 1 + read-write + + + RXTYP2COE + IP Checksum Offload (Type 2) in Rx + 18 + 1 + read-write + + + RXTYP1COE + IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1. + 17 + 1 + read-write + + + TXCOESEL + Checksum Offload in Tx + 16 + 1 + read-write + + + AVSEL + AV feature + 15 + 1 + read-write + + + EEESEL + Energy Efficient Ethernet + 14 + 1 + read-write + + + TSVER2SEL + IEEE 1588-2008 Advanced timestamp + 13 + 1 + read-write + + + TSVER1SEL + Only IEEE 1588-2002 timestamp + 12 + 1 + read-write + + + MMCSEL + RMON module + 11 + 1 + read-write + + + MGKSEL + PMT magic packet + 10 + 1 + read-write + + + RWKSEL + PMT remote wake-up frame + 9 + 1 + read-write + + + SMASEL + SMA (MDIO) Interface + 8 + 1 + read-write + + + L3L4FLTREN + Layer 3 and Layer 4 feature + 7 + 1 + read-write + + + PCSSEL + PCS registers (TBI, SGMII, or RTBI PHY interface) + 6 + 1 + read-write + + + ADDMACADRSEL + Multiple MAC Address registers + 5 + 1 + read-write + + + HASHSEL + HASH filter + 4 + 1 + read-write + + + EXTHASHEN + Expanded DA Hash filter + 3 + 1 + read-write + + + HDSEL + Half-duplex support + 2 + 1 + read-write + + + GMIISEL + 1000 Mbps support + 1 + 1 + read-write + + + MIISEL + 10 or 100 Mbps support + 0 + 1 + read-write + + + + + CTRL0 + Control Register 0 + 0x3000 + 32 + 0x00000000 + 0x000003FF + + + ENET0_RXCLK_DLY_SEL + No description avaiable + 5 + 5 + read-write + + + ENET0_TXCLK_DLY_SEL + No description avaiable + 0 + 5 + read-write + + + + + CTRL2 + Control Register 1 + 0x3008 + 32 + 0x00000000 + 0xF808F400 + + + ENET0_IRQ_EN + No description avaiable + 27 + 5 + read-write + + + ENET0_REFCLK_OE + No description avaiable + 19 + 1 + read-write + + + ENET0_PHY_INF_SEL + No description avaiable + 13 + 3 + read-write + + + ENET0_FLOWCTRL + No description avaiable + 12 + 1 + read-write + + + ENET0_RMII_TXCLK_SEL + No description avaiable + 10 + 1 + read-write + + + + + + + ENET1 + ENET1 + ENET + 0xf2004000 + + + NTMR0 + NTMR0 + TMR + 0xf2010000 + + 0x0 + 0x20c + registers + + + + CHANNEL_CH0_CR + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 15 + 16 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- RLD flag, counter reload; +01- Input signal toggle captured +10- CMP0 flag +11- CMP1 flag + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH0_CMP0 + Comparator register 0 + 0x4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH0_CMP1 + Comparator register 1 + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH0_RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH0_CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH0_CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH0_CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH0_CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH0_CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH0_CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + CHANNEL_CH1_CR + Control Register + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 15 + 16 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- RLD flag, counter reload; +01- Input signal toggle captured +10- CMP0 flag +11- CMP1 flag + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH1_CMP0 + Comparator register 0 + 0x44 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH1_CMP1 + Comparator register 1 + 0x48 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH1_RLD + Reload register + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH1_CNTUPTVAL + Counter update value register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH1_CAPPOS + Capture rising edge register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH1_CAPNEG + Capture falling edge register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH1_CAPPRD + PWM period measure register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH1_CAPDTY + PWM duty cycle measure register + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH1_CNT + Counter + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + CHANNEL_CH2_CR + Control Register + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 15 + 16 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- RLD flag, counter reload; +01- Input signal toggle captured +10- CMP0 flag +11- CMP1 flag + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH2_CMP0 + Comparator register 0 + 0x84 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH2_CMP1 + Comparator register 1 + 0x88 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH2_RLD + Reload register + 0x8c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH2_CNTUPTVAL + Counter update value register + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH2_CAPPOS + Capture rising edge register + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH2_CAPNEG + Capture falling edge register + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH2_CAPPRD + PWM period measure register + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH2_CAPDTY + PWM duty cycle measure register + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH2_CNT + Counter + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + CHANNEL_CH3_CR + Control Register + 0xc0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 15 + 16 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- RLD flag, counter reload; +01- Input signal toggle captured +10- CMP0 flag +11- CMP1 flag + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH3_CMP0 + Comparator register 0 + 0xc4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH3_CMP1 + Comparator register 1 + 0xc8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH3_RLD + Reload register + 0xcc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH3_CNTUPTVAL + Counter update value register + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH3_CAPPOS + Capture rising edge register + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH3_CAPNEG + Capture falling edge register + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH3_CAPPRD + PWM period measure register + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH3_CAPDTY + PWM duty cycle measure register + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH3_CNT + Counter + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + read-write + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + read-write + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + read-write + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + read-write + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + read-write + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + read-write + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + read-write + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + read-write + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + read-write + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + read-write + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + read-write + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + read-write + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + read-write + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + read-write + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + read-write + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + read-write + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software coutner sync event + 0 + 4 + read-write + + + + + + + NTMR1 + NTMR1 + TMR + 0xf2014000 + + + GPTMR0 + GPTMR0 + TMR + 0xf3000000 + + + GPTMR1 + GPTMR1 + TMR + 0xf3004000 + + + GPTMR2 + GPTMR2 + TMR + 0xf3008000 + + + GPTMR3 + GPTMR3 + TMR + 0xf300c000 + + + GPTMR4 + GPTMR4 + TMR + 0xf3010000 + + + GPTMR5 + GPTMR5 + TMR + 0xf3014000 + + + GPTMR6 + GPTMR6 + TMR + 0xf3018000 + + + GPTMR7 + GPTMR7 + TMR + 0xf301c000 + + + PTMR + PTMR + TMR + 0xf40e0000 + + + USB0 + USB0 + USB + 0xf2020000 + + 0x80 + 0x1a8 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00000000 + 0x00FFEB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0x00FF00FF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0x00FF00FF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 8 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x000000FF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 8 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0x00FF00FF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0x00FF00FF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0x00FF00FF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0x00FF00FF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTCTRL_ENDPTCTRL0 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL1 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c4 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL2 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c8 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL3 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1cc + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL4 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL5 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d4 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL6 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d8 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL7 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1dc + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + read-write + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + read-write + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description avaiable + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description avaiable + 25 + 1 + read-write + + + AUTORESUME_EN + No description avaiable + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description avaiable + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description avaiable + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description avaiable + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description avaiable + 10 + 1 + read-write + + + OTG_POWER_MASK + No description avaiable + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description avaiable + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description avaiable + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description avaiable + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description avaiable + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description avaiable + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description avaiable + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description avaiable + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description avaiable + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description avaiable + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description avaiable + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description avaiable + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description avaiable + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description avaiable + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description avaiable + 31 + 1 + read-write + + + + + PHY_STATUS + No description avaiable + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description avaiable + 31 + 1 + read-write + + + LINE_STATE + No description avaiable + 6 + 2 + read-write + + + HOST_DISCONNECT + No description avaiable + 5 + 1 + read-write + + + ID_DIG + No description avaiable + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description avaiable + 2 + 1 + read-write + + + VBUS_VALID + No description avaiable + 0 + 1 + read-write + + + + + + + USB1 + USB1 + USB + 0xf2024000 + + + SDXC0 + SDXC0 + SDXC + 0xf2030000 + + 0x0 + 0x548 + registers + + + + SDMASA + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + BLOCKCNT_SDMASA + 32-bit Block Count (SDMA System Address) +- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. +When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. +It can be accessed only if no transaction is executing. Reading this register during data transfers may +return an invalid value. +- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. +The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. +This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. +Following are the values for BLOCKCNT_SDMASA: +- 0xFFFF_FFFF: 4G - 1 Block +- +- 0x0000_0002: 2 Blocks +- 0x0000_0001: 1 Block +- 0x0000_0000: Stop Count +Note: +- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. +The system address must be programmed in the ADMA System Address register. +- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. +Auto CMD23 cannot be used with SDMA. +- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. + 0 + 32 + read-write + + + + + BLK_ATTR + No description avaiable + 0x4 + 32 + 0x00020210 + 0xFFFF7FFF + + + BLOCK_CNT + 16-bit Block Count +- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. +- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. +Following are the values for BLOCK_CNT: +- 0x0: Stop Count +- 0x1: 1 Block +- 0x2: 2 Blocks +- . +- 0xFFFF: 65535 Blocks +Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. + 16 + 16 + read-write + + + SDMA_BUF_BDARY + SDMA Buffer Boundary +These bits specify the size of contiguous buffer in system memory. +The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. +Values: +- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary +- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary +- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary +- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary +- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary +- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary +- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary +- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + 12 + 3 + read-write + + + XFER_BLOCK_SIZE + Transfer Block Size +These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. +Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: +- 0x1: 1 byte +- 0x2: 2 bytes +- 0x3: 3 bytes +- . +- 0x1FF: 511 byte +- 0x200: 512 byt es +- . +- 0x800: 2048 bytes +Note: This register must be programmed with a non-zero value for data transfer. + 0 + 12 + read-write + + + + + CMD_ARG + No description avaiable + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ARGUMNET + Command Argument +These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. + 0 + 32 + read-write + + + + + CMD_XFER + No description avaiable + 0xc + 32 + 0x00000000 + 0x3FFF01FF + + + CMD_INDEX + Command Index +These bits are set to the command number that is specified in bits 45-40 of the Command Format. + 24 + 6 + read-write + + + CMD_TYPE + Command Type +These bits indicate the command type. +Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. +Values: +0x3 (ABORT_CMD): Abort +0x2 (RESUME_CMD): Resume +0x1 (SUSPEND_CMD): Suspend +0x0 (NORMAL_CMD): Normal + 22 + 2 + read-write + + + DATA_PRESENT_SEL + Data Present Select +This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: +Command using the CMD line +Command with no data transfer but using busy signal on the DAT[0] line +Resume Command +Values: +0x0 (NO_DATA): No Data Present +0x1 (DATA): Data Present + 21 + 1 + read-write + + + CMD_IDX_CHK_ENABLE + Command Index Check Enable +This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. +If the value is not the same, it is reported as a Command Index error. +Note: +Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. +For the tuning command, this bit must always be set to enable the index check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 20 + 1 + read-write + + + CMD_CRC_CHK_ENABLE + Command CRC Check Enable +This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. +Note: +CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. +For the tuning command, this bit must always be set to 1 to enable the CRC check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 19 + 1 + read-write + + + SUB_CMD_FLAG + Sub Command Flag +This bit distinguishes between a main command and a sub command. +Values: +0x0 (MAIN): Main Command +0x1 (SUB): Sub Command + 18 + 1 + read-write + + + RESP_TYPE_SELECT + Response Type Select +This bit indicates the type of response expected from the card. +Values: +0x0 (NO_RESP): No Response +0x1 (RESP_LEN_136): Response Length 136 +0x2 (RESP_LEN_48): Response Length 48 +0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response + 16 + 2 + read-write + + + RESP_INT_DISABLE + Response Interrupt Disable +The Host Controller supports response check function to avoid overhead of response error check by the Host driver. +Response types of only R1 and R5 can be checked by the Controller. +If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. +If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. +The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. +Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. +Values: +- 0x0 (ENABLED): Response Interrupt is enabled +- 0x1 (DISABLED): Response Interrupt is disabled + 8 + 1 + read-write + + + RESP_ERR_CHK_ENABLE + Response Error Check Enable +The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. +Note: +- Response error check must not be enabled for any response type other than R1 and R5. +- Response check must not be enabled for the tuning command. +Values: +- 0x0 (DISABLED): Response Error Check is disabled +- 0x1 (ENABLED): Response Error Check is enabled + 7 + 1 + read-write + + + RESP_TYPE + Response Type R1/R5 +This bit selects either R1 or R5 as a response type when the Response Error Check is selected. +Error statuses checked in R1: +OUT_OF_RANGE +ADDRESS_ERROR +BLOCK_LEN_ERROR +WP_VIOLATION +CARD_IS_LOCKED +COM_CRC_ERROR +CARD_ECC_FAILED +CC_ERROR +ERROR +Response Flags checked in R5: +COM_CRC_ERROR +ERROR +FUNCTION_NUMBER +OUT_OF_RANGE +Values: +0x0 (RESP_R1): R1 (Memory) +0x1 (RESP_R5): R5 (SDIO) + 6 + 1 + read-write + + + MULTI_BLK_SEL + Multi/Single Block Select +This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. +Values: +0x0 (SINGLE): Single Block +0x1 (MULTI): Multiple Block + 5 + 1 + read-write + + + DATA_XFER_DIR + Data Transfer Direction Select +This bit defines the direction of DAT line data transfers. +This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. +Values: +0x1 (READ): Read (Card to Host) +0x0 (WRITE): Write (Host to Card) + 4 + 1 + read-write + + + AUTO_CMD_ENABLE + Auto Command Enable +This field determines use of Auto Command functions. +Note: In SDIO, this field must be set as 00b (Auto Command Disabled). +Values: +0x0 (AUTO_CMD_DISABLED): Auto Command Disabled +0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable +0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable +0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel + 2 + 2 + read-write + + + BLOCK_COUNT_ENABLE + Block Count Enable +This bit is used to enable the Block Count register, which is relevant for multiple block transfers. +If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. +The Host Driver must set this bit to 0 when ADMA is used. +Values: +0x1 (ENABLED): Enable +0x0 (DISABLED): Disable + 1 + 1 + read-write + + + DMA_ENABLE + DMA Enable +This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. +You can select one of the DMA modes by using DMA Select in the Host Control 1 register. +Values: +0x1 (ENABLED): DMA Data transfer +0x0 (DISABLED): No data transfer or Non-DMA data transfer + 0 + 1 + read-write + + + + + RESP_RESP01 + No description avaiable + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + + RESP_RESP23 + No description avaiable + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + + RESP_RESP45 + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + + RESP_RESP67 + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + + BUF_DATA + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF_DATA + Buffer Data +These bits enable access to the Host Controller packet buffer. + 0 + 32 + read-write + + + + + PSTATE + No description avaiable + 0x24 + 32 + 0x00000000 + 0x19FF0FFF + + + SUB_CMD_STAT + Sub Command Status +This bit is used to distinguish between a main command and a sub command status. +Values: +0x0 (FALSE): Main Command Status +0x1 (TRUE): Sub Command Status + 28 + 1 + read-only + + + CMD_ISSUE_ERR + Command Not Issued by Error +This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. +Values: +0x0 (FALSE): No error for issuing a command +0x1 (TRUE): Command cannot be issued + 27 + 1 + read-only + + + CMD_LINE_LVL + Command-Line Signal Level +This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. + 24 + 1 + read-only + + + DAT_3_0 + DAT[3:0] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. + 20 + 4 + read-only + + + WR_PROTECT_SW_LVL + Write Protect Switch Pin Level +This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. +Values: +0x0 (FALSE): Write protected +0x1 (TRUE): Write enabled + 19 + 1 + read-only + + + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level +This bit reflects the inverse synchronized value of the card_detect_n signal. +Values: +0x0 (FALSE): No card present +0x1 (TRUE): Card Present + 18 + 1 + read-only + + + CARD_STABLE + Card Stable +This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. +Values: +0x0 (FALSE): Reset or Debouncing +0x1 (TRUE): No Card or Inserted + 17 + 1 + read-only + + + CARD_INSERTED + Card Inserted +This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. +Values: +0x0 (FALSE): Reset, Debouncing, or No card +0x1 (TRUE): Card Inserted + 16 + 1 + read-only + + + BUF_RD_ENABLE + Buffer Read Enable +This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. +Values: +0x0 (DISABLED): Read disable +0x1 (ENABLED): Read enable + 11 + 1 + read-only + + + BUF_WR_ENABLE + Buffer Write Enable +This bit is used for non-DMA transfers. This bit is set if space is available for writing data. +Values: +0x0 (DISABLED): Write disable +0x1 (ENABLED): Write enable + 10 + 1 + read-only + + + RD_XFER_ACTIVE + Read Transfer Active +This bit indicates whether a read transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 9 + 1 + read-only + + + WR_XFER_ACTIVE + Write Transfer Active +This status indicates whether a write transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data + 8 + 1 + read-only + + + DAT_7_4 + DAT[7:4] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. + 4 + 4 + read-only + + + RE_TUNE_REQ + Re-Tuning Request +SDXC does not generate retuning request. The software must maintain the Retuning timer. + 3 + 1 + read-only + + + DAT_LINE_ACTIVE + DAT Line Active ( +This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. +In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. +In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. +For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. +Values: +0x0 (INACTIVE): DAT Line Inactive +0x1 (ACTIVE): DAT Line Active + 2 + 1 + read-only + + + DAT_INHIBIT + Command Inhibit (DAT) +This bit is generated if either DAT line active or Read transfer active is set to 1. +If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. +Values: +0x0 (READY): Can issue command which used DAT line +0x1 (NOT_READY): Cannot issue command which used DAT line + 1 + 1 + read-only + + + CMD_INHIBIT + Command Inhibit (CMD) +This bit indicates the following : +If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. +This bit is set when the command register is written. This bit is cleared when the command response is received. +This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. +Values: +0x0 (READY): Host Controller is ready to issue a command +0x1 (NOT_READY): Host Controller is not ready to issue a command + 0 + 1 + read-only + + + + + PROT_CTRL + No description avaiable + 0x28 + 32 + 0x00000000 + 0x070F0E3E + + + CARD_REMOVAL + Wakeup Event Enable on SD Card Removal +This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. +For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 26 + 1 + read-write + + + CARD_INSERT + Wakeup Event Enable on SD Card Insertion +This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. +FN_WUS (Wake Up Support) in CIS does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 25 + 1 + read-write + + + CARD_INT + Wakeup Event Enable on Card Interrupt +This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. +This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 24 + 1 + read-write + + + INT_AT_BGAP + Interrupt At Block Gap +This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. +Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. +Values: +0x0 (DISABLE): Disabled +0x1 (ENABLE): Enabled + 19 + 1 + read-write + + + RD_WAIT_CTRL + Read Wait Control +This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. +Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. +Values: +0x0 (DISABLE): Disable Read Wait Control +0x1 (ENABLE): Enable Read Wait Control + 18 + 1 + read-write + + + CONTINUE_REQ + Continue Request +This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. +The Host Controller automatically clears this bit when the transaction restarts. +If stop at block gap request is set to 1, any write to this bit is ignored. +Values: +0x0 (NO_AFFECT): No Affect +0x1 (RESTART): Restart + 17 + 1 + read-write + + + STOP_BG_REQ + Stop At Block Gap Request +This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. +Values: +0x0 (XFER): Transfer +0x1 (STOP): Stop + 16 + 1 + read-write + + + SD_BUS_VOL_VDD1 + SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD +These bits enable the Host Driver to select the voltage level for an SD/eMMC card. +Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. +If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. +The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. +SD Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 3.0V(Typical) +0x5 : 1.8V(Typical) for Embedded +0x4 : 0x0 - Reserved +eMMC Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 1.8V(Typical) +0x5 : 1.2V(Typical) +0x4 : 0x0 - Reserved +Values: +0x7 (V_3_3): 3.3V (Typ.) +0x6 (V_3_0): 3.0V (Typ.) +0x5 (V_1_8): 1.8V (Typ.) for Embedded +0x4 (RSVD4): Reserved +0x3 (RSVD3): Reserved +0x2 (RSVD2): Reserved +0x1 (RSVD1): Reserved +0x0 (RSVD0): Reserved + 9 + 3 + read-write + + + EXT_DAT_XFER + Extended Data Transfer Width +This bit controls 8-bit bus width mode of embedded device. +Values: +0x1 (EIGHT_BIT): 8-bit Bus Width +0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width + 5 + 1 + read-write + + + DMA_SEL + DMA Select +This field is used to select the DMA type. +When Host Version 4 Enable is 1 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : ADMA2 is selected +0x3 : ADMA2 or ADMA3 is selected +When Host Version 4 Enable is 0 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : 32-bit Address ADMA2 is selected +0x3 : 64-bit Address ADMA2 is selected +Values: +0x0 (SDMA): SDMA is selected +0x1 (RSVD_BIT): Reserved +0x2 (ADMA2): ADMA2 is selected +0x3 (ADMA2_3): ADMA2 or ADMA3 is selected + 3 + 2 + read-write + + + HIGH_SPEED_EN + High Speed Enable +this bit is used to determine the selection of preset value for High Speed mode. +Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. +Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. +Values: +0x1 (HIGH_SPEED): High Speed mode +0x0 (NORMAL_SPEED): Normal Speed mode + 2 + 1 + read-write + + + DAT_XFER_WIDTH + Data Transfer Width +For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. +The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. +Values: +0x1 (FOUR_BIT): 4-bit mode +0x0 (ONE_BIT): 1-bit mode + 1 + 1 + read-write + + + + + SYS_CTRL + No description avaiable + 0x2c + 32 + 0x00000000 + 0x070FFFEF + + + SW_RST_DAT + Software Reset For DAT line +This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. +The following registers and bits are cleared by this bit: +Buffer Data Port register +-Buffer is cleared and initialized. +Present state register +-Buffer Read Enable +-Buffer Write Enable +-Read Transfer Active +-Write Transfer Active +-DAT Line Active +-Command Inhibit (DAT) +Block Gap Control register +-Continue Request +-Stop At Block Gap Request +Normal Interrupt status register +-Buffer Read Ready +-Buffer Write Ready +-DMA Interrupt +-Block Gap Event +-Transfer Complete +In UHS-II mode, this bit shall be set to 0 +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 26 + 1 + read-write + + + SW_RST_CMD + Software Reset For CMD line +This bit resets only a part of the command circuit to be able to issue a command. +It bit is also used to initialize a UHS-II command circuit. +This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. +Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. +The following registers and bits are cleared by this bit: +Present State register : Command Inhibit (CMD) bit +Normal Interrupt Status register : Command Complete bit +Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 25 + 1 + read-write + + + SW_RST_ALL + Software Reset For All +This reset affects the entire Host Controller except for the card detection circuit. +During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. +All registers are reset except the capabilities register. +If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 24 + 1 + read-write + + + TOUT_CNT + Data Timeout Counter Value. +This value determines the interval by which DAT line timeouts are detected. +The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. +When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). +The values for these bits are: +0xF : Reserved +0xE : TMCLK x 2^27 +......... +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 +Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. + 16 + 4 + read-write + + + FREQ_SEL + SDCLK/RCLK Frequency Select +These bits are used to select the frequency of the SDCLK signal. +These bits depend on setting of Preset Value Enable in the Host Control 2 register. +If Preset Value Enable = 0, these bits are set by the Host Driver. +If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. +The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. +10-bit Divided Clock Mode: +0x3FF : 1/2046 Divided clock +.......... +N : 1/2N Divided Clock +.......... +0x002 : 1/4 Divided Clock +0x001 : 1/2 Divided Clock +0x000 : Base clock (10MHz - 255 MHz) +Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: +0x3FF : Base clock * M /1024 +.......... +N-1 : Base clock * M /N +.......... +0x002 : Base clock * M /3 +0x001 : Base clock * M /2 +0x000 : Base clock * M + 8 + 8 + read-write + + + UPPER_FREQ_SEL + These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. +The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. + 6 + 2 + read-write + + + CLK_GEN_SELECT + Clock Generator Select +This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. +If Preset Value Enable = 0, this bit is set by the Host Driver. +If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. +The value is reflected on the card_clk_gen_sel signal. +Values: +0x0 (FALSE): Divided Clock Mode +0x1 (TRUE): Programmable Clock Mode + 5 + 1 + read-write + + + PLL_ENABLE + PLL Enable +This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). +When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. +Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): PLL is in low power mode +0x1 (TRUE): PLL is enabled + 3 + 1 + read-write + + + SD_CLK_EN + SD/eMMC Clock Enable +This bit stops the SDCLK or RCLK when set to 0. +The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. +The value is reflected on the clk2card_on pin. +Values: +0x0 (FALSE): Disable providing SDCLK/RCLK +0x1 (TRUE): Enable providing SDCLK/RCLK + 2 + 1 + read-write + + + INTERNAL_CLK_STABLE + Internal Clock Stable +This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. +This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, +and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. +Values: +0x0 (FALSE): Not Ready +0x1 (TRUE): Ready + 1 + 1 + read-write + + + INTERNAL_CLK_EN + Internal Clock Enable +This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. +The Host Controller must stop its internal clock to enter a very low power state. +However, registers can still be read and written to. The value is reflected on the intclk_en signal. +Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): Stop +0x1 (TRUE): Oscillate + 0 + 1 + read-write + + + + + INT_STAT + No description avaiable + 0x30 + 32 + 0x00000000 + 0x1FFFF1FF + + + BOOT_ACK_ERR + Boot Acknowledgement Error +This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. +In SD/UHS-II mode, this bit is irrelevant. + 28 + 1 + read-write + + + RESP_ERR + Response Error +Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 27 + 1 + read-write + + + TUNING_ERR + Tuning Error +This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure +(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). +By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. +To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. +The Tuning Error is higher priority than the other error interrupts generated during data transfer. +By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. +This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 26 + 1 + read-write + + + ADMA_ERR + ADMA Error +This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: +Error response received from System bus (Master I/F) +ADMA3,ADMA2 Descriptors invalid +CQE Task or Transfer descriptors invalid +When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. +In eMMC CQE mode: +The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. +ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. +The Host Driver may find that Valid bit is not set at the error descriptor. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 25 + 1 + read-write + + + AUTO_CMD_ERR + Auto CMD Error +This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. +This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. +D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 24 + 1 + read-write + + + CUR_LMT_ERR + Current Limit Error +By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. +If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. +A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. +A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. +The Host Controller may require some sampling time to detect the current limit. +SDXC Host Controller does not support this function, this bit is always set to 0. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Power Fail + 23 + 1 + read-write + + + DATA_END_BIT_ERR + Data End Bit Error +This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 22 + 1 + read-write + + + DATA_CRC_ERR + Data CRC Error +This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, +when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 21 + 1 + read-write + + + DATA_TOUT_ERR + Data Timeout Error +This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: +Busy timeout for R1b, R5b type +Busy timeout after Write CRC status +Write CRC Status timeout +Read Data timeout +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 20 + 1 + read-write + + + CMD_IDX_ERR + Command Index Error +This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR + Command End Bit Error +This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): End Bit error generated + 18 + 1 + read-write + + + CMD_CRC_ERR + Command CRC Error +Command CRC Error is generated in SD/eMMC mode for following two cases. +If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. +The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. +If the Host Controller drives the CMD line to 1 level, +but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. +The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. +Values: +0x0 (FALSE): No error +0x1 (TRUE): CRC error generated + 17 + 1 + read-write + + + CMD_TOUT_ERR + Command Timeout Error +In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. +If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 16 + 1 + read-write + + + ERR_INTERRUPT + Error Interrupt +If any of the bits in the Error Interrupt Status register are set, then this bit is set. +Values: +0x0 (FALSE): No Error +0x1 (TRUE): Error + 15 + 1 + read-only + + + CQE_EVENT + Command Queuing Event +This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): Command Queuing Event is detected + 14 + 1 + read-write + + + FX_EVENT + FX Event +This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): FX Event is detected + 13 + 1 + read-only + + + RE_TUNE_EVENT + Re-tuning Event +This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. + 12 + 1 + read-only + + + CARD_INTERRUPT + Card Interrupt +This bit reflects the synchronized value of: +DAT[1] Interrupt Input for SD Mode +DAT[2] Interrupt Input for UHS-II Mode +Values: +0x0 (FALSE): No Card Interrupt +0x1 (TRUE): Generate Card Interrupt + 8 + 1 + read-only + + + CARD_REMOVAL + Card Removal +This bit is set if the Card Inserted in the Present State register changes from 1 to 0. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Removed + 7 + 1 + read-write + + + CARD_INSERTION + Card Insertion +This bit is set if the Card Inserted in the Present State register changes from 0 to 1. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Inserted + 6 + 1 + read-write + + + BUF_RD_READY + Buffer Read Ready +This bit is set if the Buffer Read Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to read buffer +0x1 (TRUE): Ready to read buffer + 5 + 1 + read-write + + + BUF_WR_READY + Buffer Write Ready +This bit is set if the Buffer Write Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to write buffer +0x1 (TRUE): Ready to write buffer + 4 + 1 + read-write + + + DMA_INTERRUPT + DMA Interrupt +This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. +In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. +This interrupt is not generated after a Transfer Complete. +Values: +0x0 (FALSE): No DMA Interrupt +0x1 (TRUE): DMA Interrupt is generated + 3 + 1 + read-write + + + BGAP_EVENT + Block Gap Event +This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. +Values: +0x0 (FALSE): No Block Gap Event +0x1 (TRUE): Transaction stopped at block gap + 2 + 1 + read-write + + + XFER_COMPLETE + Transfer Complete +This bit is set when a read/write transfer and a command with status busy is completed. +Values: +0x0 (FALSE): Not complete +0x1 (TRUE): Command execution is completed + 1 + 1 + read-write + + + CMD_COMPLETE + Command Complete +In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. +This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. +Values: +0x0 (FALSE): No command complete +0x1 (TRUE): Command Complete + 0 + 1 + read-write + + + + + INT_STAT_EN + No description avaiable + 0x34 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_STAT_EN + Boot Acknowledgment Error (eMMC Mode only) +Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_STAT_EN + Response Error Status Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_STAT_EN + Tuning Error Status Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_STAT_EN + ADMA Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_STAT_EN + Auto CMD Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_STAT_EN + Current Limit Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_STAT_EN + Data End Bit Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_STAT_EN + Data CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_STAT_EN + Data Timeout Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_STAT_EN + Command Index Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 19 + 1 + read-write + + + CMD_END_BIT_ERR_STAT_EN + Command End Bit Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_STAT_EN + Command CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_STAT_EN + Command Timeout Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_STAT_EN + CQE Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_STAT_EN + FX Event Status Enable +This bit is added from Version 4.10. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_STAT_EN + Re-Tuning Event (UHS-I only) Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_STAT_EN + Card Interrupt Status Enable +If this bit is set to 0, the Host Controller clears the interrupt request to the System. +The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. +The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. +By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_STAT_EN + Card Removal Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_STAT_EN + Card Insertion Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_STAT_EN + Buffer Read Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_STAT_EN + Buffer Write Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_STAT_EN + DMA Interrupt Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_STAT_EN + Block Gap Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_STAT_EN + Transfer Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_STAT_EN + Command Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + INT_SIGNAL_EN + No description avaiable + 0x38 + 32 + 0x00000000 + 0x1FFF71FF + + + BOOT_ACK_ERR_SIGNAL_EN + Boot Acknowledgment Error (eMMC Mode only). +Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgement Error in Error Interrupt Status register is set. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 + read-write + + + RESP_ERR_SIGNAL_EN + Response Error Signal Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 + read-write + + + TUNING_ERR_SIGNAL_EN + Tuning Error Signal Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 + read-write + + + ADMA_ERR_SIGNAL_EN + ADMA Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 + read-write + + + AUTO_CMD_ERR_SIGNAL_EN + Auto CMD Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 + 1 + read-write + + + CUR_LMT_ERR_SIGNAL_EN + Current Limit Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 + 1 + read-write + + + DATA_END_BIT_ERR_SIGNAL_EN + Data End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 + 1 + read-write + + + DATA_CRC_ERR_SIGNAL_EN + Data CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 + read-write + + + DATA_TOUT_ERR_SIGNAL_EN + Data Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 + 1 + read-write + + + CMD_IDX_ERR_SIGNAL_EN + Command Index Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 + read-write + + + CMD_END_BIT_ERR_SIGNAL_EN + Command End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 + read-write + + + CMD_CRC_ERR_SIGNAL_EN + Command CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 + read-write + + + CMD_TOUT_ERR_SIGNAL_EN + Command Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 + read-write + + + CQE_EVENT_SIGNAL_EN + Command Queuing Engine Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_SIGNAL_EN + FX Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_SIGNAL_EN + Re-Tuning Event (UHS-I only) Signal Enable. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 + read-write + + + CARD_INTERRUPT_SIGNAL_EN + Card Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 + read-write + + + CARD_REMOVAL_SIGNAL_EN + Card Removal Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 + read-write + + + CARD_INSERTION_SIGNAL_EN + Card Insertion Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 + read-write + + + BUF_RD_READY_SIGNAL_EN + Buffer Read Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 + read-write + + + BUF_WR_READY_SIGNAL_EN + Buffer Write Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 + read-write + + + DMA_INTERRUPT_SIGNAL_EN + DMA Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 + read-write + + + BGAP_EVENT_SIGNAL_EN + Block Gap Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 + read-write + + + XFER_COMPLETE_SIGNAL_EN + Transfer Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 + read-write + + + CMD_COMPLETE_SIGNAL_EN + Command Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 0 + 1 + read-write + + + + + AC_HOST_CTRL + No description avaiable + 0x3c + 32 + 0x00000000 + 0xDCCF00BF + + + PRESET_VAL_ENABLE + Preset Value Enable +This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. +When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. +These values are selected from set of Preset Value registers based on selected speed mode. +Values: +0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver +0x1 (TRUE): Automatic Selection by Preset Value are Enabled + 31 + 1 + read-write + + + ASYNC_INT_ENABLE + Asynchronous Interrupt Enable +This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. +Values: +0x0 (FALSE): Disabled +0x1 (TRUE): Enabled + 30 + 1 + read-write + + + HOST_VER4_ENABLE + Host Version 4 Enable +This bit selects either Version 3.00 compatible mode or Version 4 mode. +Functions of following fields are modified for Host Version 4 mode: +SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) +ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register +64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 +Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register +32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register +Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, +UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). +Values: +0x0 (FALSE): Version 3.00 compatible mode +0x1 (TRUE): Version 4 mode + 28 + 1 + read-write + + + CMD23_ENABLE + CMD23 Enable +If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. +Values: +0x0 (FALSE): Auto CMD23 is disabled +0x1 (TRUE): Auto CMD23 is enabled + 27 + 1 + read-write + + + ADMA2_LEN_MODE + ADMA2 Length Mode +This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. +Values: +0x0 (FALSE): 16-bit Data Length Mode +0x1 (TRUE): 26-bit Data Length Mode + 26 + 1 + read-write + + + SAMPLE_CLK_SEL + Sampling Clock Select +This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. +This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). +Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. +The value is reflected on the sample_cclk_sel pin. +Values: +0x0 (FALSE): Fixed clock is used to sample data +0x1 (TRUE): Tuned clock is used to sample data + 23 + 1 + read-write + + + EXEC_TUNING + Execute Tuning +This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. +Values: +0x0 (FALSE): Not Tuned or Tuning completed +0x1 (TRUE): Execute Tuning + 22 + 1 + read-write + + + SIGNALING_EN + 1.8V Signaling Enable +This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. +Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. +Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. +Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). +Values: +0x0 (V_3_3): 3.3V Signalling +0x1 (V_1_8): 1.8V Signalling + 19 + 1 + read-write + + + UHS_MODE_SEL + UHS Mode/eMMC Speed Mode Select +These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. +UHS Mode (SD/UHS-II mode only): +0x0 (SDR12): SDR12/Legacy +0x1 (SDR25): SDR25/High Speed SDR +0x2 (SDR50): SDR50 +0x3 (SDR104): SDR104/HS200 +0x4 (DDR50): DDR50/High Speed DDR +0x5 (RSVD5): Reserved +0x6 (RSVD6): Reserved +0x7 (UHS2): UHS-II/HS400 +eMMC Speed Mode (eMMC mode only): +0x0: Legacy +0x1: High Speed SDR +0x2: Reserved +0x3: HS200 +0x4: High Speed DDR +0x5: Reserved +0x6: Reserved +0x7: HS400 + 16 + 3 + read-write + + + CMD_NOT_ISSUED_AUTO_CMD12 + Command Not Issued By Auto CMD12 Error +If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Issued +0x0 (FALSE): No Error + 7 + 1 + read-only + + + AUTO_CMD_RESP_ERR + Auto CMD Response Error +This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. +This status is ignored if any bit between D00 to D04 is set to 1. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 5 + 1 + read-only + + + AUTO_CMD_IDX_ERR + Auto CMD Index Error +This bit is set if the command index error occurs in response to a command. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 4 + 1 + read-only + + + AUTO_CMD_EBIT_ERR + Auto CMD End Bit Error +This bit is set when detecting that the end bit of command response is 0. +Values: +0x1 (TRUE): End Bit Error Generated +0x0 (FALSE): No Error + 3 + 1 + read-only + + + AUTO_CMD_CRC_ERR + Auto CMD CRC Error +This bit is set when detecting a CRC error in the command response. +Values: +0x1 (TRUE): CRC Error Generated +0x0 (FALSE): No Error + 2 + 1 + read-only + + + AUTO_CMD_TOUT_ERR + Auto CMD Timeout Error +This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. +If this bit is set to 1, error status bits (D04-D01) are meaningless. +Values: +0x1 (TRUE): Time out +0x0 (FALSE): No Error + 1 + 1 + read-only + + + AUTO_CMD12_NOT_EXEC + Auto CMD12 Not Executed +If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. +Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. + If this bit is set to 1, error status bits (D04-D01) is meaningless. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Executed +0x0 (FALSE): Executed + 0 + 1 + read-only + + + + + CAPABILITIES1 + No description avaiable + 0x40 + 32 + 0x00000000 + 0xE7EFFFBF + + + SLOT_TYPE_R + Slot Type +These bits indicate usage of a slot by a specific Host System. +Values: +0x0 (REMOVABLE_SLOT): Removable Card Slot +0x1 (EMBEDDED_SLOT): Embedded Slot for one Device +0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) +0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices + 30 + 2 + read-only + + + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support (SD Mode only) +Values: +0x0 (FALSE): Asynchronous Interrupt Not Supported +0x1 (TRUE): Asynchronous Interrupt Supported + 29 + 1 + read-only + + + VOLT_18 + Voltage Support for 1.8V +Values: +0x0 (FALSE): 1.8V Not Supported +0x1 (TRUE): 1.8V Supported + 26 + 1 + read-only + + + VOLT_30 + Voltage Support for SD 3.0V or Embedded 1.2V +Values: +0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported +0x1 (TRUE): SD 3.0V or Embedded Supported + 25 + 1 + read-only + + + VOLT_33 + Voltage Support for 3.3V +Values: +0x0 (FALSE): 3.3V Not Supported +0x1 (TRUE): 3.3V Supported + 24 + 1 + read-only + + + SUS_RES_SUPPORT + Suspense/Resume Support +This bit indicates whether the Host Controller supports Suspend/Resume functionality. +If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. +Values: +0x0 (FALSE): Not Supported +0x1 (TRUE): Supported + 23 + 1 + read-only + + + SDMA_SUPPORT + SDMA Support +This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. +Values: +0x0 (FALSE): SDMA not Supported +0x1 (TRUE): SDMA Supported + 22 + 1 + read-only + + + HIGH_SPEED_SUPPORT + High Speed Support +This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. +Values: +0x0 (FALSE): High Speed not Supported +0x1 (TRUE): High Speed Supported + 21 + 1 + read-only + + + ADMA2_SUPPORT + ADMA2 Support +This bit indicates whether the Host Controller is capable of using ADMA2. +Values: +0x0 (FALSE): ADMA2 not Supported +0x1 (TRUE): ADMA2 Supported + 19 + 1 + read-only + + + EMBEDDED_8_BIT + 8-bit Support for Embedded Device +This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. +Values: +0x0 (FALSE): 8-bit Bus Width not Supported +0x1 (TRUE): 8-bit Bus Width Supported + 18 + 1 + read-only + + + MAX_BLK_LEN + Maximum Block Length +This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. +The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit +Values: +0x0 (ZERO): 512 Byte +0x1 (ONE): 1024 Byte +0x2 (TWO): 2048 Byte +0x3 (THREE): Reserved + 16 + 2 + read-only + + + BASE_CLK_FREQ + Base Clock Frequency for SD clock +These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. +6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. +The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............. +-0x3F : 63 MHz +-0x40-0xFF : Not Supported +8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............ +-0xFF : 255 MHz +If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. +If these bits are all 0, the Host system has to get information using a different method. + 8 + 8 + read-only + + + TOUT_CLK_UNIT + Timeout Clock Unit +This bit shows the unit of base clock frequency used to detect Data TImeout Error. +Values: +0x0 (KHZ): KHz +0x1 (MHZ): MHz + 7 + 1 + read-only + + + TOUT_CLK_FREQ + Timeout Clock Frequency +This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. +0x00 : Get information through another method +0x01 : 1KHz / 1MHz +0x02 : 2KHz / 2MHz +0x03 : 3KHz / 3MHz + ........... +0x3F : 63KHz / 63MHz + 0 + 6 + read-only + + + + + CAPABILITIES2 + No description avaiable + 0x44 + 32 + 0x00000000 + 0x18FFEF7F + + + VDD2_18V_SUPPORT + 1.8V VDD2 Support +This bit indicates support of VDD2 for the Host System. +0x0 (FALSE): 1.8V VDD2 is not Supported +0x1 (TRUE): 1.8V VDD2 is Supported + 28 + 1 + read-only + + + ADMA3_SUPPORT + ADMA3 Support +This bit indicates whether the Host Controller is capable of using ADMA3. +Values: +0x0 (FALSE): ADMA3 not Supported +0x1 (TRUE): ADMA3 Supported + 27 + 1 + read-only + + + CLK_MUL + Clock Multiplier +These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. +0x0: Clock Multiplier is not Supported +0x1: Clock Multiplier M = 2 +0x2: Clock Multiplier M = 3 + ......... +0xFF: Clock Multiplier M = 256 + 16 + 8 + read-only + + + RE_TUNING_MODES + Re-Tuning Modes (UHS-I only) +These bits select the re-tuning method and limit the maximum data length. +Values: +0x0 (MODE1): Timer +0x1 (MODE2): Timer and Re-Tuning Request (Not supported) +0x2 (MODE3): Auto Re-Tuning (for transfer) +0x3 (RSVD_MODE): Reserved + 14 + 2 + read-only + + + USE_TUNING_SDR50 + Use Tuning for SDR50 (UHS-I only) +Values: +0x0 (ZERO): SDR50 does not require tuning +0x1 (ONE): SDR50 requires tuning + 13 + 1 + read-only + + + RETUNE_CNT + Timer Count for Re-Tuning (UHS-I only) +0x0: Re-Tuning Timer disabled +0x1: 1 seconds +0x2: 2 seconds +0x3: 4 seconds + ........ +0xB: 1024 seconds +0xC: Reserved +0xD: Reserved +0xE: Reserved +0xF: Get information from other source + 8 + 4 + read-only + + + DRV_TYPED + Driver Type D Support (UHS-I only) +This bit indicates support of Driver Type D for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type D is not supported +0x1 (TRUE): Driver Type D is supported + 6 + 1 + read-only + + + DRV_TYPEC + Driver Type C Support (UHS-I only) +This bit indicates support of Driver Type C for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type C is not supported +0x1 (TRUE): Driver Type C is supported + 5 + 1 + read-only + + + DRV_TYPEA + Driver Type A Support (UHS-I only) +This bit indicates support of Driver Type A for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type A is not supported +0x1 (TRUE): Driver Type A is supported + 4 + 1 + read-only + + + UHS2_SUPPORT + UHS-II Support (UHS-II only) +This bit indicates whether Host Controller supports UHS-II. +Values: +0x0 (FALSE): UHS-II is not supported +0x1 (TRUE): UHS-II is supported + 3 + 1 + read-only + + + DDR50_SUPPORT + DDR50 Support (UHS-I only) +Values: +0x0 (FALSE): DDR50 is not supported +0x1 (TRUE): DDR50 is supported + 2 + 1 + read-only + + + SDR104_SUPPORT + SDR104 Support (UHS-I only) +This bit mentions that SDR104 requires tuning. +Values: +0x0 (FALSE): SDR104 is not supported +0x1 (TRUE): SDR104 is supported + 1 + 1 + read-only + + + SDR50_SUPPORT + SDR50 Support (UHS-I only) +This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. +Values: +0x0 (FALSE): SDR50 is not supported +0x1 (TRUE): SDR50 is supported + 0 + 1 + read-only + + + + + CURR_CAPABILITIES1 + No description avaiable + 0x48 + 32 + 0x00000000 + 0x00FFFFFF + + + MAX_CUR_18V + Maximum Current for 1.8V +This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 16 + 8 + read-only + + + MAX_CUR_30V + Maximum Current for 3.0V +This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 8 + 8 + read-only + + + MAX_CUR_33V + Maximum Current for 3.3V +This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + CURR_CAPABILITIES2 + No description avaiable + 0x4c + 32 + 0x00000000 + 0x000000FF + + + MAX_CUR_VDD2_18V + Maximum Current for 1.8V VDD2 +This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 0 + 8 + read-only + + + + + FORCE_EVENT + No description avaiable + 0x50 + 32 + 0x00000000 + 0x1FFF00BF + + + FORCE_BOOT_ACK_ERR + Force Event for Boot Ack error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Boot ack Error Status is set + 28 + 1 + write-only + + + FORCE_RESP_ERR + Force Event for Response Error (SD Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Response Error Status is set + 27 + 1 + write-only + + + FORCE_TUNING_ERR + Force Event for Tuning Error (UHS-I Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Tuning Error Status is set + 26 + 1 + write-only + + + FORCE_ADMA_ERR + Force Event for ADMA Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): ADMA Error Status is set + 25 + 1 + write-only + + + FORCE_AUTO_CMD_ERR + Force Event for Auto CMD Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Auto CMD Error Status is set + 24 + 1 + write-only + + + FORCE_CUR_LMT_ERR + Force Event for Current Limit Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Current Limit Error Status is set + 23 + 1 + write-only + + + FORCE_DATA_END_BIT_ERR + Force Event for Data End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data End Bit Error Status is set + 22 + 1 + write-only + + + FORCE_DATA_CRC_ERR + Force Event for Data CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data CRC Error Status is set + 21 + 1 + write-only + + + FORCE_DATA_TOUT_ERR + Force Event for Data Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data Timeout Error Status is set + 20 + 1 + write-only + + + FORCE_CMD_IDX_ERR + Force Event for Command Index Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Index Error Status is set + 19 + 1 + write-only + + + FORCE_CMD_END_BIT_ERR + Force Event for Command End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command End Bit Error Status is set + 18 + 1 + write-only + + + FORCE_CMD_CRC_ERR + Force Event for Command CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command CRC Error Status is set + 17 + 1 + write-only + + + FORCE_CMD_TOUT_ERR + Force Event for Command Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Timeout Error Status is set + 16 + 1 + write-only + + + FORCE_CMD_NOT_ISSUED_AUTO_CMD12 + Force Event for Command Not Issued By Auto CMD12 Error +Values: +0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set +0x0 (FALSE): Not Affected + 7 + 1 + write-only + + + FORCE_AUTO_CMD_RESP_ERR + Force Event for Auto CMD Response Error +Values: +0x1 (TRUE): Auto CMD Response Error Status is set +0x0 (FALSE): Not Affected + 5 + 1 + write-only + + + FORCE_AUTO_CMD_IDX_ERR + Force Event for Auto CMD Index Error +Values: +0x1 (TRUE): Auto CMD Index Error Status is set +0x0 (FALSE): Not Affected + 4 + 1 + write-only + + + FORCE_AUTO_CMD_EBIT_ERR + Force Event for Auto CMD End Bit Error +Values: +0x1 (TRUE): Auto CMD End Bit Error Status is set +0x0 (FALSE): Not Affected + 3 + 1 + write-only + + + FORCE_AUTO_CMD_CRC_ERR + Force Event for Auto CMD CRC Error +Values: +0x1 (TRUE): Auto CMD CRC Error Status is set +0x0 (FALSE): Not Affected + 2 + 1 + write-only + + + FORCE_AUTO_CMD_TOUT_ERR + Force Event for Auto CMD Timeout Error +Values: +0x1 (TRUE): Auto CMD Timeout Error Status is set +0x0 (FALSE): Not Affected + 1 + 1 + write-only + + + FORCE_AUTO_CMD12_NOT_EXEC + Force Event for Auto CMD12 Not Executed +Values: +0x1 (TRUE): Auto CMD12 Not Executed Status is set +0x0 (FALSE): Not Affected + 0 + 1 + write-only + + + + + ADMA_ERR_STAT + No description avaiable + 0x54 + 32 + 0x00000000 + 0x00000007 + + + ADMA_LEN_ERR + ADMA Length Mismatch Error States +This error occurs in the following instances: +While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length +When the total data length cannot be divided by the block length +Values: +0x0 (NO_ERR): No Error +0x1 (ERROR): Error + 2 + 1 + read-only + + + ADMA_ERR_STATES + ADMA Error States +These bits indicate the state of ADMA when an error occurs during ADMA data transfer. +Values: +0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor +0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor +0x2 (UNUSED): Never set this state +0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor + 0 + 2 + read-only + + + + + ADMA_SYS_ADDR + No description avaiable + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_SA + ADMA System Address +These bits indicate the lower 32 bits of the ADMA system address. +SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location +ADMA2: This register stores the byte address of the executing command of the descriptor table +ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. + 0 + 32 + read-write + + + + + PRESET_INIT + No description avaiable + 0x60 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_DS + No description avaiable + 0x62 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_HS + No description avaiable + 0x64 + 16 + 0x0001 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_SDR12 + No description avaiable + 0x66 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_SDR25 + No description avaiable + 0x68 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_SDR50 + No description avaiable + 0x6a + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_SDR104 + No description avaiable + 0x6c + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_DDR50 + No description avaiable + 0x6e + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_UHS2 + No description avaiable + 0x74 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 + 1 + read-only + + + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + ADMA_ID_ADDR + No description avaiable + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADMA_ID_ADDR + ADMA Integrated Descriptor Address +These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. +The start address of Integrated Descriptor is set to these register bits. +The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. + 0 + 32 + read-write + + + + + P_EMBEDDED_CNTRL + No description avaiable + 0xe6 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Offset Address of Embedded Control register. + 0 + 12 + read-only + + + + + P_VENDOR_SPECIFIC_AREA + No description avaiable + 0xe8 + 16 + 0x0000 + 0x0FFF + + + REG_OFFSET_ADDR + Base offset Address for Vendor-Specific registers. + 0 + 12 + read-only + + + + + P_VENDOR2_SPECIFIC_AREA + No description avaiable + 0xea + 16 + 0x0000 + 0xFFFF + + + REG_OFFSET_ADDR + Base offset Address for Command Queuing registers. + 0 + 16 + read-only + + + + + SLOT_INTR_STATUS + No description avaiable + 0xfc + 16 + 0x0000 + 0x00FF + + + INTR_SLOT + Interrupt signal for each Slot +These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. +A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. + By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. +Bit 00: Slot 1 +Bit 01: Slot 2 +Bit 02: Slot 3 +.......... +.......... +Bit 07: Slot 8 +Note: MSHC Host Controller support single card slot. This register shall always return 0. + 0 + 8 + read-only + + + + + CQVER + No description avaiable + 0x180 + 32 + 0x00000000 + 0x00000FFF + + + EMMC_VER_MAHOR + This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. + 8 + 4 + read-only + + + EMMC_VER_MINOR + This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. + 4 + 4 + read-only + + + EMMC_VER_SUFFIX + This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. + 0 + 4 + read-only + + + + + CQCAP + No description avaiable + 0x184 + 32 + 0x00000000 + 0x1000F3FF + + + CRYPTO_SUPPORT + Crypto Support +This bit indicates whether the Host Controller supports cryptographic operations. +Values: +0x0 (FALSE): Crypto not Supported +0x1 (TRUE): Crypto Supported + 28 + 1 + read-only + + + ITCFMUL + Internal Timer Clock Frequency Multiplier (ITCFMUL) +This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS +polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. +Values: +0x0 (CLK_1KHz): 1KHz clock +0x1 (CLK_10KHz): 10KHz clock +0x2 (CLK_100KHz): 100KHz clock +0x3 (CLK_1MHz): 1MHz clock +0x4 (CLK_10MHz): 10MHz clock + 12 + 4 + read-only + + + ITCFVAL + Internal Timer Clock Frequency Value (ITCFVAL) +This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. + 0 + 10 + read-only + + + + + CQCFG + No description avaiable + 0x188 + 32 + 0x00000000 + 0x00001101 + + + DCMD_EN + This bit indicates to the hardware whether the Task +Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. +Values: +0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor +0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor + 12 + 1 + read-write + + + TASK_DESC_SIZE + Bit Value Description +This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). +Values: +0x1 (TASK_DESC_128b): Task descriptor size is 128 bits +0x0 (TASK_DESC_64b): Task descriptor size is 64 bit + 8 + 1 + read-write + + + CQ_EN + No description avaiable + 0 + 1 + read-write + + + + + CQCTL + No description avaiable + 0x18c + 32 + 0x00000000 + 0x00000101 + + + CLR_ALL_TASKS + Clear all tasks +This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. +Values: +0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller +0x0 (NO_EFFECT): Programming 0 has no effect + 8 + 1 + read-write + + + HALT + Halt request and resume +Values: +0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. +For example, issuing a Discard Task command (CMDQ_TASK_MGMT). +When the software writes 1, CQE completes the ongoing task (if any in progress). +After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. +The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. +0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity + 0 + 1 + read-write + + + + + CQIS + No description avaiable + 0x190 + 32 + 0x00000000 + 0x0000000F + + + TCL + Task cleared interrupt +This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. +The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). +A value of 1 clears this status bit. +Values: +0x1 (SET): TCL Interrupt is set +0x0 (NOTSET): TCL Interrupt is not set + 3 + 1 + read-write + + + RED + Response error detected interrupt +This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status +field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. +A value of 1 clears this status bit. +Values: +0x1 (SET): RED Interrupt is set +0x0 (NOTSET): RED Interrupt is not set + 2 + 1 + read-write + + + TCC + Task complete interrupt +This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: +A task is completed and the INT bit is set in its Task Descriptor +Interrupt caused by Interrupt Coalescing logic due to timeout +Interrupt Coalescing logic reached the configured threshold +A value of 1 clears this status bit + 1 + 1 + read-write + + + HAC + Halt complete interrupt +This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. +A value of 1 clears this status bit. +Values: +0x1 (SET): HAC Interrupt is set +0x0 (NOTSET): HAC Interrupt is not set + 0 + 1 + read-write + + + + + CQISE + No description avaiable + 0x194 + 32 + 0x00000000 + 0x0000000F + + + TCL_STE + Task cleared interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + 3 + 1 + read-write + + + RED_STE + Response error detected interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.RED is disabled + 2 + 1 + read-write + + + TCC_STE + Task complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + 1 + 1 + read-write + + + HAC_STE + Halt complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.HAC is disabled + 0 + 1 + read-write + + + + + CQISGE + No description avaiable + 0x198 + 32 + 0x00000000 + 0x0000000F + + + TCL_SGE + Task cleared interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled + 3 + 1 + read-write + + + RED_SGE + Response error detected interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled + 2 + 1 + read-write + + + TCC_SGE + Task complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled + 1 + 1 + read-write + + + HAC_SGE + Halt complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled + 0 + 1 + read-write + + + + + CQIC + No description avaiable + 0x19c + 32 + 0x00000000 + 0x80119FFF + + + INTC_EN + Interrupt Coalescing Enable Bit +Values: +0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated +0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) + 31 + 1 + read-write + + + INTC_STAT + Interrupt Coalescing Status Bit +This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt +coalescing (that is, this is set if and only if INTC counter > 0). +Values: +0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) +0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) + 20 + 1 + read-only + + + INTC_RST + Counter and Timer Reset +When host driver writes 1, the interrupt coalescing timer and counter are reset. +Values: +0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset +0x0 (NO_EFFECT): No Effect + 16 + 1 + write-only + + + INTC_TH_WEN + Interrupt Coalescing Counter Threshold Write Enable +When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets INTC_TH_WEN +0x0 (WEN_CLR): Clears INTC_TH_WEN + 15 + 1 + write-only + + + INTC_TH + Interrupt Coalescing Counter Threshold filed +Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. +Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. +The counter is reset by software during the interrupt service routine. +The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. +0x0: Interrupt coalescing feature disabled +0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes +0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes +........ +0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes +To write to this field, the INTC_TH_WEN bit must be set during the same write operation. + 8 + 5 + write-only + + + TOUT_VAL_WEN + When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets TOUT_VAL_WEN +0x0 (WEN_CLR): clears TOUT_VAL_WEN + 7 + 1 + write-only + + + TOUT_VAL + Interrupt Coalescing Timeout Value +Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. +Timer Operation: The timer is reset by software during the interrupt service routine. +It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. +When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. +The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +0x0: Timer is disabled. Timeout-based interrupt is not generated +0x1: Timeout on 01x1024 cycles of timer clock frequency +0x2: Timeout on 02x1024 cycles of timer clock frequency +........ +0x7f: Timeout on 127x1024 cycles of timer clock frequency +In order to write to this field, the TOUT_VAL_WEN bit must +be set at the same write operation. + 0 + 7 + read-write + + + + + CQTDLBA + No description avaiable + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TDLBA + This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. +The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. +This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE + 0 + 32 + read-write + + + + + CQTDBR + No description avaiable + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DBR + The software configures TDLBA and TDLBAU, and enable +CQE in CQCFG before using this register. +Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. +Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. +CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. +CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to +the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. +The corresponding bit is cleared to 0 by CQE in one of the following events: +A task execution is completed (with success or error). +The task is cleared using CQTCLR register. +All tasks are cleared using CQCTL register. +CQE is disabled using CQCFG register. +Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. +In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. +If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. + 0 + 32 + read-write + + + + + CQTCN + No description avaiable + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + TCN + Task Completion Notification +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has completed execution (with success or errors) +Bit-N(0): Task-N has not completed, could be pending or not submitted. +On task completion, software may read this register to know tasks that have completed. After reading this register, +software may clear the relevant bit fields by writing 1 to the corresponding bits. + 0 + 32 + read-write + + + + + CQDQS + No description avaiable + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DQS + Device Queue Status +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Device has marked task N as ready for execution +Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. +Host controller updates this register with response of the Device Queue Status command. + 0 + 32 + read-write + + + + + CQDPT + No description avaiable + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DPT + Device-Pending Tasks +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution +Bit-N(0): Task-N is not yet queued. +Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. +The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. +Software reads this register in the task-discard procedure to determine if the task is queued in the device + 0 + 32 + read-write + + + + + CQTCLR + No description avaiable + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TCLR + Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. +This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. +When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. +CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. +Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. + 0 + 32 + read-write + + + + + CQSSC1 + No description avaiable + 0x1c0 + 32 + 0x00000000 + 0x000FFFFF + + + SQSCMD_BLK_CNT + This field indicates when SQS CMD is sent while data transfer is in progress. +A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. +0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. +0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. +0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. +0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. +........ +0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. +Should be programmed only when CQCFG.CQ_EN is 0 + 16 + 4 + read-write + + + SQSCMD_IDLE_TMR + This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. +Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. +When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. +Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). +For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). +If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. +Should be programmed only when CQCFG.CQ_EN is '0' + 0 + 16 + read-write + + + + + CQSSC2 + No description avaiable + 0x1c4 + 32 + 0x00000000 + 0x0000FFFF + + + SQSCMD_RCA + This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. +CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. + 0 + 16 + read-write + + + + + CQCRDCT + No description avaiable + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DCMD_RESP + This register contains the response of the command generated by the last direct command (DCMD) task that was sent. +Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. + 0 + 32 + read-only + + + + + CQRMEM + No description avaiable + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESP_ERR_MASK + The bits of this field are bit mapped to the device response. +This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. +1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. +0: When a R1/R1b response is received, bit i in the device status is ignored. +The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. +Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. + 0 + 32 + read-write + + + + + CQTERRI + No description avaiable + 0x1d4 + 32 + 0x00000000 + 0x1F3F9F3F + + + TRANS_ERR_TASKID + This field captures the ID of the task that was executed and whose data transfer has errors. + 24 + 5 + read-only + + + TRANS_ERR_CMD_INDX + This field captures the index of the command that was executed and whose data transfer has errors. + 16 + 6 + read-only + + + RESP_ERR_FIELDS_VALID + This bit is updated when an error is detected while a command transaction was in progress. +Values: +0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields +0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX + 15 + 1 + read-only + + + RESP_ERR_TASKID + This field captures the ID of the task which was executed on the command line when the error occurred. + 8 + 5 + read-only + + + RESP_ERR_CMD_INDX + This field captures the index of the command that was executed on the command line when the error occurred + 0 + 6 + read-only + + + + + CQCRI + No description avaiable + 0x1d8 + 32 + 0x00000000 + 0x0000003F + + + CMD_RESP_INDX + Last Command Response index +This field stores the index of the last received command response. Controller updates the value every time a command response is received + 0 + 6 + read-only + + + + + CQCRA + No description avaiable + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_RESP_ARG + Last Command Response argument +This field stores the argument of the last received command response. Controller updates the value every time a command response is received. + 0 + 32 + read-only + + + + + MSHC_VER_ID + No description avaiable + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_ID + No description avaiable + 0 + 32 + read-only + + + + + MSHC_VER_TYPE + No description avaiable + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + VER_TYPE + No description avaiable + 0 + 32 + read-only + + + + + MBIU_CTRL + Y + 0x510 + 32 + 0x00000000 + 0x0000000F + + + BURST_INCR16_EN + No description avaiable + 3 + 1 + read-write + + + BURST_INCR8_EN + No description avaiable + 2 + 1 + read-write + + + BUSRT_INCR4_EN + No description avaiable + 1 + 1 + read-write + + + UNDEFL_INCR_EN + No description avaiable + 0 + 1 + read-write + + + + + EMMC_BOOT_CTRL + No description avaiable + 0x52c + 32 + 0x00000000 + 0xF181070F + + + BOOT_TOUT_CNT + Boot Ack Timeout Counter Value. +This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. +0xF : Reserved +0xE : TMCLK x 2^27 + ............ +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 + 28 + 4 + read-write + + + BOOT_ACK_ENABLE + Boot Acknowledge Enable +When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. +Values: +0x1 (TRUE): Boot Ack enable +0x0 (FALSE): Boot Ack disable + 24 + 1 + read-write + + + VALIDATE_BOOT + Validate Mandatory Boot Enable bit +This bit is used to validate the MAN_BOOT_EN bit. +Values: +0x1 (TRUE): Validate Mandatory boot enable bit +0x0 (FALSE): Ignore Mandatory boot Enable bit + 23 + 1 + write-only + + + MAN_BOOT_EN + Mandatory Boot Enable +This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. +Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. +Values: +0x1 (MAN_BOOT_EN): Mandatory boot enable +0x0 (MAN_BOOT_DIS): Mandatory boot disable + 16 + 1 + read-write + + + CQE_PREFETCH_DISABLE + Enable or Disable CQE's PREFETCH feature +This field allows Software to disable CQE's data prefetch feature when set to 1. +Values: +0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers +0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled + 10 + 1 + read-write + + + CQE_ALGO_SEL + Scheduler algorithm selected for execution +This bit selects the Algorithm used for selecting one of the many ready tasks for execution. +Values: +0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks +0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings + 9 + 1 + read-write + + + ENH_STROBE_ENABLE + Enhanced Strobe Enable +This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. +Values: +0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode +0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode + 8 + 1 + read-write + + + EMMC_RST_N_OE + Output Enable control for EMMC Device Reset signal PAD +control. +This field drived sd_rst_n_oe output of SDXC +Values: +0x1 (ENABLE): sd_rst_n_oe is 1 +0x0 (DISABLE): sd_rst_n_oe is 0 + 3 + 1 + read-write + + + EMMC_RST_N + EMMC Device Reset signal control. +This register field controls the sd_rst_n output of SDXC +Values: +0x1 (RST_DEASSERT): Reset to eMMC device is deasserted +0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) + 2 + 1 + read-write + + + DISABLE_DATA_CRC_CHK + Disable Data CRC Check +This bit controls masking of CRC16 error for Card Write in eMMC mode. +This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, +which may generate CRC error. This CRC error can be masked using this bit during bus testing. +Values: +0x1 (DISABLE): DATA CRC check is disabled +0x0 (ENABLE): DATA CRC check is enabled + 1 + 1 + read-write + + + CARD_IS_EMMC + eMMC Card present +This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. +Values: +0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card +0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card + 0 + 1 + read-write + + + + + AUTO_TUNING_CTRL + No description avaiable + 0x540 + 32 + 0x00000000 + 0x7F1F0F1F + + + SWIN_TH_VAL + Sampling window threshold value setting +The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps +can use values from 0x0 to 0x1F. +This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' +0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. +0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. +0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. +........ +0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. + 24 + 7 + read-write + + + POST_CHANGE_DLY + Time taken for phase switching and stable clock output. +Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 19 + 2 + read-write + + + PRE_CHANGE_DLY + Maximum Latency specification between cclk_tx and cclk_rx. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 17 + 2 + read-write + + + TUNE_CLK_STOP_EN + Clock stopping control for Tuning and auto-tuning circuit. +When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. +This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. + Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. +Values: +0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change +0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching + 16 + 1 + read-write + + + WIN_EDGE_SEL + This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. +0x0: User selection disabled. Tuning calculated edges are used. +0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. +0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess +... +0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. + 8 + 4 + read-write + + + SW_TUNE_EN + This fields enables software-managed tuning flow. +Values: +0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable. +0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled + 4 + 1 + read-write + + + RPT_TUNE_ERR + Framing errors are not generated when executing tuning. +This debug bit allows users to report these errors. +Values: +0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors +0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. + 3 + 1 + read-write + + + SWIN_TH_EN + Sampling window Threshold enable +Selects the tuning mode +Field should be programmed only when SAMPLE_CLK_SEL is '0' +Values: +0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold +set by SWIN_TH_VAL field +0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window + 2 + 1 + read-write + + + CI_SEL + Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. +Values: +0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval +0x1 (WHEN_IN_IDLE): Driven at the end of the transfer + 1 + 1 + read-write + + + AT_EN + Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. +Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. +This field should be programmed only when CLK_CTRL_R.SD_CLK_EN is 0. +Values: +0x1 (AT_ENABLE): AutoTuning is enabled +0x0 (AT_DISABLE): AutoTuning is disabled + 0 + 1 + read-write + + + + + AUTO_TUNING_STAT + No description avaiable + 0x544 + 32 + 0x00000000 + 0x00FFFFFF + + + L_EDGE_PH_CODE + Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. + 16 + 8 + read-only + + + R_EDGE_PH_CODE + Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. + 8 + 8 + read-only + + + CENTER_PH_CODE + Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel + 0 + 8 + read-write + + + + + + + SDXC1 + SDXC1 + SDXC + 0xf2034000 + + + CONCTL + CONCTL + CONCTL + 0xf2040000 + + 0x0 + 0x18 + registers + + + + CTRL0 + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFF0FFFFF + + + RESERVED + No description avaiable + 24 + 8 + read-write + + + ENET1_RXCLK_DLY_SEL + No description avaiable + 15 + 5 + read-write + + + ENET1_TXCLK_DLY_SEL + No description avaiable + 10 + 5 + read-write + + + ENET0_RXCLK_DLY_SEL + No description avaiable + 5 + 5 + read-write + + + ENET0_TXCLK_DLY_SEL + No description avaiable + 0 + 5 + read-write + + + + + CTRL2 + No description avaiable + 0x8 + 32 + 0x00000000 + 0x0008F400 + + + ENET0_REFCLK_OE + No description avaiable + 19 + 1 + read-write + + + ENET0_PHY_INTF_SEL + 000:Reserved +001:RGMII +100:RMII +111:Reserved + 13 + 3 + read-write + + + ENET0_FLOWCTRL + No description avaiable + 12 + 1 + read-write + + + ENET0_RMII_TXCLK_SEL + default to use internal clk. +set from pad， two option here: + internal 50MHz clock out to pad then in; + use external clock; + 10 + 1 + read-write + + + + + CTRL3 + No description avaiable + 0xc + 32 + 0x00000000 + 0x0008F400 + + + ENET1_REFCLK_OE + No description avaiable + 19 + 1 + read-write + + + ENET1_PHY_INTF_SEL + No description avaiable + 13 + 3 + read-write + + + ENET1_FLOWCTRL + No description avaiable + 12 + 1 + read-write + + + ENET1_RMII_TXCLK_SEL + No description avaiable + 10 + 1 + read-write + + + + + CTRL4 + No description avaiable + 0x10 + 32 + 0x00000000 + 0xDFFE0000 + + + SDXC0_SYS_IRQ_EN + system irq enable + 31 + 1 + read-write + + + SDXC0_WKP_IRQ_EN + wakeup irq enable + 30 + 1 + read-write + + + SDXC0_CARDCLK_INV_EN + card clock inverter enable + 28 + 1 + read-write + + + SDXC0_GPR_TUNING_CARD_CLK_SEL + for card clock DLL, default 0 + 23 + 5 + read-write + + + SDXC0_GPR_TUNING_STROBE_SEL + for strobe DLL, default 7taps(1ns) + 18 + 5 + read-write + + + SDXC0_GPR_STROBE_IN_ENABLE + enable strobe clock, maybe used when update strobe DLL + 17 + 1 + read-write + + + + + CTRL5 + No description avaiable + 0x14 + 32 + 0x00000000 + 0xDFFE0000 + + + SDXC1_SYS_IRQ_EN + system irq enable + 31 + 1 + read-write + + + SDXC1_WKP_IRQ_EN + wakeup irq enable + 30 + 1 + read-write + + + SDXC1_CARDCLK_INV_EN + card clock inverter enable + 28 + 1 + read-write + + + SDXC1_GPR_TUNING_CARD_CLK_SEL + No description avaiable + 23 + 5 + read-write + + + SDXC1_GPR_TUNING_STROBE_SEL + No description avaiable + 18 + 5 + read-write + + + SDXC1_GPR_STROBE_IN_ENABLE + No description avaiable + 17 + 1 + read-write + + + + + + + I2C0 + I2C0 + I2C + 0xf3020000 + + 0x4 + 0x30 + registers + + + + CFG + Configuration Register + 0x10 + 32 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 2 + 30 + read-write + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + INTEN + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 10 + 22 + read-write + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + STATUS + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 15 + 17 + read-write + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + read-write + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + read-write + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + read-write + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + read-write + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + read-write + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + read-write + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + read-write + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + ADDR + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 10 + 22 + read-write + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + DATA + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 8 + 24 + read-write + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + CTRL + Control Register + 0x24 + 32 + 0x00001E00 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 13 + 19 + read-write + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means 256 bytes. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + CMD + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 3 + 29 + read-write + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + SETUP + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 29 + 3 + read-write + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + RESERVED + No description avaiable + 14 + 2 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 5 + 27 + read-write + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf3024000 + + + I2C2 + I2C2 + I2C + 0xf3028000 + + + I2C3 + I2C3 + I2C + 0xf302c000 + + + SDP + SDP + SDP + 0xf304c000 + + 0x0 + 0x60 + registers + + + + SDPCR + SDP control register + 0x0 + 32 + 0x30000000 + 0xFFFE0101 + + + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. + 31 + 1 + read-write + + + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + 30 + 1 + read-write + + + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 + 1 + read-only + + + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 + 1 + read-only + + + RESERVED + Not used + 24 + 4 + read-only + + + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 + 1 + read-write + + + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 + 1 + read-write + + + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 + read-write + + + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 + 1 + read-write + + + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 + 1 + read-write + + + RESERVED + Reserved + 18 + 1 + read-write + + + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 + 1 + read-write + + + RDSCEN + when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) +when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + 8 + 1 + read-write + + + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. + 0 + 1 + read-write + + + + + MODCTRL + Mod control register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +Others, reserved. + 28 + 4 + read-write + + + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write + + + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 + read-write + + + RESERVED + Not used + 17 + 1 + read-only + + + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 + 1 + read-write + + + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 + read-write + + + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 + 1 + read-write + + + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 + 1 + read-write + + + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 + read-write + + + RESERVED + Not used + 8 + 1 + read-only + + + RESERVED + Not used + 6 + 2 + read-only + + + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format + 0 + 2 + read-write + + + + + PKTCNT + packet counter registers. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 31 + 1 + read-write + + + RESERVED + Not used + 30 + 1 + read-write + + + RESERVED + Not used + 24 + 6 + read-only + + + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 + read-only + + + RESERVED + Not used + 8 + 8 + read-only + + + CNTINCR + The value written to this field is added to the spacket count. + 0 + 8 + read-write + + + + + STA + Status Registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TAG + packet tag. + 24 + 8 + read-only + + + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 + 1 + read-write + + + RESERVED + Not used + 21 + 2 + read-only + + + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + read-write + + + AESBSY + AES Busy + 19 + 1 + read-only + + + HASBSY + Hashing Busy + 18 + 1 + read-only + + + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + read-write + + + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 + 1 + read-write + + + RESERVED + Not used + 6 + 10 + read-only + + + ERRSET + Working mode setup error. + 5 + 1 + read-write + + + ERRPKT + Packet head access error, or status update error. + 4 + 1 + read-write + + + ERRSRC + Source Buffer Access Error + 3 + 1 + read-write + + + ERRDST + Destination Buffer Error + 2 + 1 + read-write + + + ERRHAS + Hashing Check Error + 1 + 1 + read-write + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + 0 + 1 + read-write + + + + + KEYADDR + Key Address + 0x10 + 32 + 0x00000040 + 0xFFFFFFFF + + + RESERVED + Not used + 24 + 8 + read-only + + + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + RESERVED + Not used + 2 + 14 + read-only + + + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. + 0 + 2 + read-write + + + + + KEYDAT + Key Data + 0x14 + 32 + 0x00000030 + 0xFFFFFFFF + + + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV0 + Cipher Initializtion Vector 0 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV1 + Cipher Initializtion Vector 1 + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV2 + Cipher Initializtion Vector 2 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV3 + Cipher Initializtion Vector 3 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + HASWRD_HASWRD0 + Hash Data Word 0 + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD1 + Hash Data Word 1 + 0x2c + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD2 + Hash Data Word 2 + 0x30 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD3 + Hash Data Word 3 + 0x34 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD4 + Hash Data Word 4 + 0x38 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD5 + Hash Data Word 5 + 0x3c + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD6 + Hash Data Word 6 + 0x40 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD7 + Hash Data Word 7 + 0x44 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + CMDPTR + Command Pointer + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) + 0 + 32 + read-write + + + + + NPKTPTR + Next Packet Address Pointer + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + NPKTPTR + Next Packet Address Pointer + 0 + 32 + read-write + + + + + PKTCTL + Packet Control Registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTTAG + packet tag + 24 + 8 + read-write + + + RESERVED + Not used + 7 + 17 + read-write + + + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 + read-write + + + HASFNL + Hash Termination packet + 5 + 1 + read-write + + + HASINI + Hash Initialization packat + 4 + 1 + read-write + + + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 + read-write + + + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 + 1 + read-write + + + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 + 1 + read-write + + + RESERVED + Not used + 0 + 1 + read-write + + + + + PKTSRC + Packet Memory Source Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTSRC + Packet Memory Source Address + 0 + 32 + read-write + + + + + PKTDST + Packet Memory Destination Address + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTDST + Packet Memory Destination Address + 0 + 32 + read-write + + + + + PKTBUF + Packet buffer size. + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTBUF + No description avaiable + 0 + 32 + read-write + + + + + + + DRAM + DRAM + DRAM + 0xf3050000 + + 0x0 + 0x154 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x1FFF0007 + + + BTO + Bus timeout cycles +AXI Bus timeout cycle is as following (255*(2^BTO)): +00000b - 255*1 +00001-11110b - 255*2 - 255*2^30 +11111b - 255*2^31 + 24 + 5 + read-write + + + CTO + Command Execution timeout cycles +When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is +generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is +CTO*1024 cycle. + 16 + 8 + read-write + + + DQS + DQS (read strobe) mode +0b - Dummy read strobe loopbacked internally +1b - Dummy read strobe loopbacked from DQS pad + 2 + 1 + read-write + + + DIS + Module Disable +0b - Module enabled +1b - Module disabled + 1 + 1 + read-write + + + RST + Software Reset +Reset all internal logic in SEMC except configuration register + 0 + 1 + read-write + + + + + BMW0 + Bus (AXI) Weight Control Register 0 + 0x8 + 32 + 0x00000000 + 0x00FFFFFF + + + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 + read-write + + + SH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write + + + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + + + BMW1 + Bus (AXI) Weight Control Register 1 + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + BR + Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current +executing command. + 24 + 8 + read-write + + + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 + read-write + + + PH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write + + + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. + 0 + 4 + read-write + + + + + BR_BASE0 + Base Register 0 (for SDRAM CS0 device) + 0x10 + 32 + 0x00000000 + 0xFFFFF03F + + + BASE + Base Address +This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low +position 12 bits are all zero. + 12 + 20 + read-write + + + SIZE + Memory size +00000b - 4KB +00001b - 8KB +00010b - 16KB +00011b - 32KB +00100b - 64KB +00101b - 128KB +00110b - 256KB +00111b - 512KB +01000b - 1MB +01001b - 2MB +01010b - 4MB +01011b - 8MB +01100b - 16MB +01101b - 32MB +01110b - 64MB +01111b - 128MB +10000b - 256MB +10001b - 512MB +10010b - 1GB +10011b - 2GB +10100-11111b - 4GB + 1 + 5 + read-write + + + VLD + Valid + 0 + 1 + read-write + + + + + BR_BASE1 + Base Register 1 (for SDRAM CS1 device) + 0x14 + 32 + 0x00000000 + 0xFFFFF03F + + + BASE + Base Address +This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low +position 12 bits are all zero. + 12 + 20 + read-write + + + SIZE + Memory size +00000b - 4KB +00001b - 8KB +00010b - 16KB +00011b - 32KB +00100b - 64KB +00101b - 128KB +00110b - 256KB +00111b - 512KB +01000b - 1MB +01001b - 2MB +01010b - 4MB +01011b - 8MB +01100b - 16MB +01101b - 32MB +01110b - 64MB +01111b - 128MB +10000b - 256MB +10001b - 512MB +10010b - 1GB +10011b - 2GB +10100-11111b - 4GB + 1 + 5 + read-write + + + VLD + Valid + 0 + 1 + read-write + + + + + INTEN + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000000F + + + AXIBUSERR + AXI BUS error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 3 + 1 + read-write + + + AXICMDERR + AXI command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 2 + 1 + read-write + + + IPCMDERR + IP command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 1 + 1 + read-write + + + IPCMDDONE + IP command done interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 0 + 1 + read-write + + + + + INTR + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000000F + + + AXIBUSERR + AXI bus error interrupt +AXI Bus error interrupt is generated in following cases: +• AXI address is invalid +• AXI 8-bit or 16-bit WRAP write/read + 3 + 1 + read-write + + + AXICMDERR + AXI command error interrupt +AXI command error interrupt is generated when AXI command execution timeout. + 2 + 1 + read-write + + + IPCMDERR + IP command error done interrupt +IP command error interrupt is generated in following case: +• IP Command Address target invalid device space +• IP Command Code unsupported +• IP Command triggered when previous command + 1 + 1 + read-write + + + IPCMDDONE + IP command normal done interrupt + 0 + 1 + read-write + + + + + SDRCTRL0 + SDRAM Control Register 0 + 0x40 + 32 + 0x00000000 + 0x00004FFB + + + BANK2 + 2 Bank selection bit +0b - SDRAM device has 4 banks. +1b - SDRAM device has 2 banks. + 14 + 1 + read-write + + + CAS + CAS Latency +00b - 1 +01b - 1 +10b - 2 +11b - 3 + 10 + 2 + read-write + + + COL + Column address bit number +00b - 12 bit +01b - 11 bit +10b - 10 bit +11b - 9 bit + 8 + 2 + read-write + + + COL8 + Column 8 selection bit +0b - Column address bit number is decided by COL field. +1b - Column address bit number is 8. COL field is ignored. + 7 + 1 + read-write + + + BURSTLEN + Burst Length +000b - 1 +001b - 2 +010b - 4 +011b - 8 +100b - 8 +101b - 8 +110b - 8 +111b - 8 + 4 + 3 + read-write + + + HIGHBAND + high band select +0: use data[15:0] for 16bit SDRAM; +1: use data[31:16] for 16bit SDRAM; +only used when Port Size is 16bit(PORTSZ=01b) + 3 + 1 + read-write + + + PORTSZ + Port Size +00b - 8bit +01b - 16bit +10b - 32bit + 0 + 2 + read-write + + + + + SDRCTRL1 + SDRAM Control Register 1 + 0x44 + 32 + 0x00000000 + 0x00FFFFFF + + + ACT2PRE + ACT to Precharge minimum time +It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. + 20 + 4 + read-write + + + CKEOFF + CKE OFF minimum time +It is promised clock suspend last at leat CKEOFF+1 clock cycles. + 16 + 4 + read-write + + + WRC + Write recovery time +It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. + 13 + 3 + read-write + + + RFRC + Refresh recovery time +It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. + 8 + 5 + read-write + + + ACT2RW + ACT to Read/Write wait time +It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. + 4 + 4 + read-write + + + PRE2ACT + PRECHARGE to ACT/Refresh wait time +It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. + 0 + 4 + read-write + + + + + SDRCTRL2 + SDRAM Control Register 2 + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + ITO + SDRAM Idle timeout +It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is +considered idle when there is no AXI Bus transfer and no SDRAM command pending. +00000000b - IDLE timeout period is 256*Prescale period. +00000001-11111111b - IDLE timeout period is ITO*Prescale period. + 24 + 8 + read-write + + + ACT2ACT + ACT to ACT wait time +It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This +could help to meet tRRD timing requirement by SDRAM device. + 16 + 8 + read-write + + + REF2REF + Refresh to Refresh wait time +It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. +This could help to meet tRFC timing requirement by SDRAM device. + 8 + 8 + read-write + + + SRRC + Self Refresh Recovery time +It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. + 0 + 8 + read-write + + + + + SDRCTRL3 + SDRAM Control Register 3 + 0x4c + 32 + 0x00000000 + 0xFFFFFF0F + + + UT + Refresh urgent threshold +Internal refresh request is generated on every Refresh period. Before internal request timer count up to +urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh +request is handled in lower priority than any pending AXI command or IP command to SDRAM device. +When internal request timer count up to this urgent threshold, refresh request is considered as urgent +refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP +command to SDRAM device. +NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as +urgent refresh request. +Refresh urgent threshold is as follwoing: +00000000b - 256*Prescaler period +00000001-11111111b - UT*Prescaler period + 24 + 8 + read-write + + + RT + Refresh timer period +Refresh timer period is as following: +00000000b - 256*Prescaler period +00000001-11111111b - RT*Prescaler period + 16 + 8 + read-write + + + PRESCALE + Prescaler timer period +Prescaler timer period is as following: +00000000b - 256*16 clock cycles +00000001-11111111b - PRESCALE*16 clock cycles + 8 + 8 + read-write + + + REBL + Refresh burst length +It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The +number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. +000b - 1 +001b - 2 +010b - 3 +011b - 4 +100b - 5 +101b - 6 +110b - 7 +111b - 8 + 1 + 3 + read-write + + + REN + Refresh enable + 0 + 1 + read-write + + + + + SADDR + IP Command Control Register 0 + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + SA + Slave address + 0 + 32 + read-write + + + + + DATSZ + IP Command Control Register 1 + 0x94 + 32 + 0x00000000 + 0x00000007 + + + DATSZ + Data Size in Byte +When IP command is not a write/read operation, DATSZ field would be ignored. +000b - 4 +001b - 1 +010b - 2 +011b - 3 +100b - 4 +101b - 4 +110b - 4 +111b - 4 + 0 + 3 + read-write + + + + + BYTEMSK + IP Command Control Register 2 + 0x98 + 32 + 0x00000000 + 0x0000000F + + + BM3 + Byte Mask for Byte 3 (IPTXD bit 31:24) +0b - Byte Unmasked +1b - Byte Masked + 3 + 1 + read-write + + + BM2 + Byte Mask for Byte 2 (IPTXD bit 23:16) +0b - Byte Unmasked +1b - Byte Masked + 2 + 1 + read-write + + + BM1 + Byte Mask for Byte 1 (IPTXD bit 15:8) +0b - Byte Unmasked +1b - Byte Masked + 1 + 1 + read-write + + + BM0 + Byte Mask for Byte 0 (IPTXD bit 7:0) +0b - Byte Unmasked +1b - Byte Masked + 0 + 1 + read-write + + + + + IPCMD + IP Command Register + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory +device is selected by BRx settings and IPCR0 registers. + 16 + 16 + write-only + + + CMD + SDRAM Commands: +• 0x8: READ +• 0x9: WRITE +• 0xA: MODESET +• 0xB: ACTIVE +• 0xC: AUTO REFRESH +• 0xD: SELF REFRESH +• 0xE: PRECHARGE +• 0xF: PRECHARGE ALL +• Others: RSVD +NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. + 0 + 16 + read-write + + + + + IPTX + TX DATA Register + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + Data + 0 + 32 + read-write + + + + + IPRX + RX DATA Register + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT + Data + 0 + 32 + read-write + + + + + STAT0 + Status Register 0 + 0xc0 + 32 + 0x00000000 + 0x00000001 + + + IDLE + Indicating whether it is in IDLE state. +When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no +pending device access. + 0 + 1 + read-only + + + + + DLYCFG + Delay Line Config Register + 0x150 + 32 + 0x00000000 + 0x0000203F + + + OE + delay clock output enable, should be set after setting DLYEN and DLYSEL + 13 + 1 + read-write + + + DLYSEL + delay line select, 0 for 1 cell, 31 for all 32 cells + 1 + 5 + read-write + + + DLYEN + delay line enable + 0 + 1 + read-write + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x3000 + registers + + + + RESOURCE_CPU0_CORE + Resource control register for cpu0 + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CPU0_SUBSYS + Resource control register for cpx0 + 0x4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CPU1_CORE + Resource control register for cpu1 + 0x20 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CPX1_SUBSYS + Resource control register for cpx1 + 0x24 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_POW_CON + Resource control register for pow_con + 0x54 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_POW_VIS + Resource control register for pow_vis + 0x58 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_POW_CPU0 + Resource control register for pow_cpu0 + 0x5c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_POW_CPU1 + Resource control register for pow_cpu1 + 0x60 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_SOC + Resource control register for rst_soc + 0x64 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_CON + Resource control register for rst_con + 0x68 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_VIS + Resource control register for rst_vis + 0x6c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_CPU0 + Resource control register for rst_cpu0 + 0x70 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_CPU1 + Resource control register for rst_cpu1 + 0x74 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_XTAL + Resource control register for xtal + 0x80 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL0 + Resource control register for pll0 + 0x84 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL0CLK0 + Resource control register for clk0_pll0 + 0x88 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL1 + Resource control register for pll1 + 0x8c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL1CLK0 + Resource control register for clk0_pll1 + 0x90 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL1CLK1 + Resource control register for clk1_pll1 + 0x94 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL2 + Resource control register for pll2 + 0x98 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL2CLK0 + Resource control register for clk0_pll2 + 0x9c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL2CLK1 + Resource control register for clk1_pll2 + 0xa0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL3 + Resource control register for pll3 + 0xa4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL3CLK0 + Resource control register for clk0_pll3 + 0xa8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL4 + Resource control register for pll4 + 0xac + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL4CLK0 + Resource control register for clk0_pll4 + 0xb0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CPU0 + Resource control register for clk_top_cpu0 + 0x100 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_MCHTMR0 + Resource control register for clk_top_mct0 + 0x104 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CPU1 + Resource control register for clk_top_cpu1 + 0x108 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_MCHTMR1 + Resource control register for clk_top_mct1 + 0x10c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_AXI + Resource control register for clk_top_axi0 + 0x110 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CONN + Resource control register for clk_top_axi1 + 0x114 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_VIS + Resource control register for clk_top_axi2 + 0x118 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_AHB + Resource control register for clk_top_ahb0 + 0x11c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_DRAM + Resource control register for clk_top_dram + 0x120 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_XPI0 + Resource control register for clk_top_xpi0 + 0x124 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_XPI1 + Resource control register for clk_top_xpi1 + 0x128 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_GPTMR0 + Resource control register for clk_top_tmr0 + 0x12c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_GPTMR1 + Resource control register for clk_top_tmr1 + 0x130 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_GPTMR2 + Resource control register for clk_top_tmr2 + 0x134 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_GPTMR3 + Resource control register for clk_top_tmr3 + 0x138 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_GPTMR4 + Resource control register for clk_top_tmr4 + 0x13c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_GPTMR5 + Resource control register for clk_top_tmr5 + 0x140 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_GPTMR6 + Resource control register for clk_top_tmr6 + 0x144 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_GPTMR7 + Resource control register for clk_top_tmr7 + 0x148 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART0 + Resource control register for clk_top_urt0 + 0x14c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART1 + Resource control register for clk_top_urt1 + 0x150 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART2 + Resource control register for clk_top_urt2 + 0x154 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART3 + Resource control register for clk_top_urt3 + 0x158 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART4 + Resource control register for clk_top_urt4 + 0x15c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART5 + Resource control register for clk_top_urt5 + 0x160 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART6 + Resource control register for clk_top_urt6 + 0x164 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART7 + Resource control register for clk_top_urt7 + 0x168 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART8 + Resource control register for clk_top_urt8 + 0x16c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART9 + Resource control register for clk_top_urt9 + 0x170 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART10 + Resource control register for clk_top_urta + 0x174 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART11 + Resource control register for clk_top_urtb + 0x178 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART12 + Resource control register for clk_top_urtc + 0x17c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART13 + Resource control register for clk_top_urtd + 0x180 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART14 + Resource control register for clk_top_urte + 0x184 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_UART15 + Resource control register for clk_top_urtf + 0x188 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C0 + Resource control register for clk_top_i2c0 + 0x18c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C1 + Resource control register for clk_top_i2c1 + 0x190 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C2 + Resource control register for clk_top_i2c2 + 0x194 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C3 + Resource control register for clk_top_i2c3 + 0x198 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI0 + Resource control register for clk_top_spi0 + 0x19c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI1 + Resource control register for clk_top_spi1 + 0x1a0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI2 + Resource control register for clk_top_spi2 + 0x1a4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI3 + Resource control register for clk_top_spi3 + 0x1a8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN0 + Resource control register for clk_top_can0 + 0x1ac + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN1 + Resource control register for clk_top_can1 + 0x1b0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN2 + Resource control register for clk_top_can2 + 0x1b4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN3 + Resource control register for clk_top_can3 + 0x1b8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_PTPC + Resource control register for clk_top_ptpc + 0x1bc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA0 + Resource control register for clk_top_ana0 + 0x1c0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA1 + Resource control register for clk_top_ana1 + 0x1c4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA2 + Resource control register for clk_top_ana2 + 0x1c8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_AUD0 + Resource control register for clk_top_aud0 + 0x1cc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_AUD1 + Resource control register for clk_top_aud1 + 0x1d0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_AUD2 + Resource control register for clk_top_aud2 + 0x1d4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_LCDC + Resource control register for clk_top_dis0 + 0x1d8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAM0 + Resource control register for clk_top_cam0 + 0x1dc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAM1 + Resource control register for clk_top_cam1 + 0x1e0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ENET0 + Resource control register for clk_top_eth0 + 0x1e4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ENET1 + Resource control register for clk_top_eth1 + 0x1e8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_PTP0 + Resource control register for clk_top_ptp0 + 0x1ec + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_PTP1 + Resource control register for clk_top_ptp1 + 0x1f0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_REF0 + Resource control register for clk_top_ref0 + 0x1f4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_REF1 + Resource control register for clk_top_ref1 + 0x1f8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_NTMR0 + Resource control register for clk_top_ntm0 + 0x1fc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_NTMR1 + Resource control register for clk_top_ntm1 + 0x200 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SDXC0 + Resource control register for clk_top_sdc0 + 0x204 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SDXC1 + Resource control register for clk_top_sdc1 + 0x208 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC0 + Resource control register for clk_top_adc0 + 0x300 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC1 + Resource control register for clk_top_adc1 + 0x304 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC2 + Resource control register for clk_top_adc2 + 0x308 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC3 + Resource control register for clk_top_adc3 + 0x30c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2S0 + Resource control register for clk_top_i2s0 + 0x310 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2S1 + Resource control register for clk_top_i2s1 + 0x314 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2S2 + Resource control register for clk_top_i2s2 + 0x318 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2S3 + Resource control register for clk_top_i2s3 + 0x31c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AHBAPB_BUS + Resource control register for ahbp + 0x400 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AXI_BUS + Resource control register for axis + 0x404 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CONN_BUS + Resource control register for axic + 0x408 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_VIS_BUS + Resource control register for axiv + 0x40c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_DRAM + Resource control register for dram + 0x410 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ROM + Resource control register for rom0 + 0x414 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LMM0 + Resource control register for lmm0 + 0x418 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LMM1 + Resource control register for lmm1 + 0x41c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MCHTMR0 + Resource control register for mct0 + 0x420 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MCHTMR1 + Resource control register for mct1 + 0x424 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AXI_SRAM0 + Resource control register for ram0 + 0x428 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AXI_SRAM1 + Resource control register for ram1 + 0x42c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_XPI0 + Resource control register for xpi0 + 0x430 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_XPI1 + Resource control register for xpi1 + 0x434 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SDP + Resource control register for sdp0 + 0x438 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RNG + Resource control register for rng0 + 0x43c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_KEYM + Resource control register for kman + 0x440 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_HDMA + Resource control register for dma0 + 0x444 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_XDMA + Resource control register for dma1 + 0x448 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPIO + Resource control register for gpio + 0x44c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MBX0 + Resource control register for mbx0 + 0x450 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MBX1 + Resource control register for mbx1 + 0x454 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_WDG0 + Resource control register for wdg0 + 0x458 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_WDG1 + Resource control register for wdg1 + 0x45c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_WDG2 + Resource control register for wdg2 + 0x460 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_WDG3 + Resource control register for wdg3 + 0x464 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPTMR0 + Resource control register for tmr0 + 0x468 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPTMR1 + Resource control register for tmr1 + 0x46c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPTMR2 + Resource control register for tmr2 + 0x470 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPTMR3 + Resource control register for tmr3 + 0x474 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPTMR4 + Resource control register for tmr4 + 0x478 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPTMR5 + Resource control register for tmr5 + 0x47c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPTMR6 + Resource control register for tmr6 + 0x480 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPTMR7 + Resource control register for tmr7 + 0x484 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART0 + Resource control register for urt0 + 0x488 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART1 + Resource control register for urt1 + 0x48c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART2 + Resource control register for urt2 + 0x490 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART3 + Resource control register for urt3 + 0x494 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART4 + Resource control register for urt4 + 0x498 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART5 + Resource control register for urt5 + 0x49c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART6 + Resource control register for urt6 + 0x4a0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART7 + Resource control register for urt7 + 0x4a4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART8 + Resource control register for urt8 + 0x4a8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART9 + Resource control register for urt9 + 0x4ac + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART10 + Resource control register for urta + 0x4b0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART11 + Resource control register for urtb + 0x4b4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART12 + Resource control register for urtc + 0x4b8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART13 + Resource control register for urtd + 0x4bc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART14 + Resource control register for urte + 0x4c0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_UART15 + Resource control register for urtf + 0x4c4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C0 + Resource control register for i2c0 + 0x4c8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C1 + Resource control register for i2c1 + 0x4cc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C2 + Resource control register for i2c2 + 0x4d0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C3 + Resource control register for i2c3 + 0x4d4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI0 + Resource control register for spi0 + 0x4d8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI1 + Resource control register for spi1 + 0x4dc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI2 + Resource control register for spi2 + 0x4e0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI3 + Resource control register for spi3 + 0x4e4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN0 + Resource control register for can0 + 0x4e8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN1 + Resource control register for can1 + 0x4ec + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN2 + Resource control register for can2 + 0x4f0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN3 + Resource control register for can3 + 0x4f4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_PTPC + Resource control register for ptpc + 0x4f8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC0 + Resource control register for adc0 + 0x4fc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC1 + Resource control register for adc1 + 0x500 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC2 + Resource control register for adc2 + 0x504 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC3 + Resource control register for adc3 + 0x508 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ACMP + Resource control register for acmp + 0x50c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2S0 + Resource control register for i2s0 + 0x510 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2S1 + Resource control register for i2s1 + 0x514 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2S2 + Resource control register for i2s2 + 0x518 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2S3 + Resource control register for i2s3 + 0x51c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_PDM + Resource control register for pdm0 + 0x520 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_DAO + Resource control register for clsd + 0x524 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SYNT + Resource control register for msyn + 0x528 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT0 + Resource control register for mot0 + 0x52c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT1 + Resource control register for mot1 + 0x530 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT2 + Resource control register for mot2 + 0x534 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT3 + Resource control register for mot3 + 0x538 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LCDC + Resource control register for dis0 + 0x53c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAM0 + Resource control register for cam0 + 0x540 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAM1 + Resource control register for cam1 + 0x544 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_JPEG + Resource control register for jpeg + 0x548 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_PDMA + Resource control register for pdma + 0x54c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ENET0 + Resource control register for eth0 + 0x550 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ENET1 + Resource control register for eth1 + 0x554 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_NTMR0 + Resource control register for ntm0 + 0x558 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_NTMR1 + Resource control register for ntm1 + 0x55c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SDXC0 + Resource control register for sdc0 + 0x560 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SDXC1 + Resource control register for sdc1 + 0x564 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_USB0 + Resource control register for usb0 + 0x568 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_USB1 + Resource control register for usb1 + 0x56c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_REF0 + Resource control register for ref0 + 0x570 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_REF1 + Resource control register for ref1 + 0x574 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + GROUP0_0_VALUE + Goup setting + 0x800 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_0_SET + Goup setting + 0x804 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_0_CLEAR + Goup setting + 0x808 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_0_TOGGLE + Goup setting + 0x80c + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_1_VALUE + Goup setting + 0x810 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_1_SET + Goup setting + 0x814 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_1_CLEAR + Goup setting + 0x818 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_1_TOGGLE + Goup setting + 0x81c + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_2_VALUE + Goup setting + 0x820 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_2_SET + Goup setting + 0x824 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_2_CLEAR + Goup setting + 0x828 + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_2_TOGGLE + Goup setting + 0x82c + 32 + 0x00000023 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_0_VALUE + Goup setting + 0x840 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_0_SET + Goup setting + 0x844 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_0_CLEAR + Goup setting + 0x848 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_0_TOGGLE + Goup setting + 0x84c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_1_VALUE + Goup setting + 0x850 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_1_SET + Goup setting + 0x854 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_1_CLEAR + Goup setting + 0x858 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_1_TOGGLE + Goup setting + 0x85c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_2_VALUE + Goup setting + 0x860 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_2_SET + Goup setting + 0x864 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_2_CLEAR + Goup setting + 0x868 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_2_TOGGLE + Goup setting + 0x86c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + AFFILIATE_CPU0_VALUE + Affiliate of Group + 0x900 + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU0_SET + Affiliate of Group + 0x904 + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU0_CLEAR + Affiliate of Group + 0x908 + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU0_TOGGLE + Affiliate of Group + 0x90c + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU1_VALUE + Affiliate of Group + 0x910 + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU1_SET + Affiliate of Group + 0x914 + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU1_CLEAR + Affiliate of Group + 0x918 + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU1_TOGGLE + Affiliate of Group + 0x91c + 32 + 0x00000001 + 0x0000000F + + + LINK + Affiliate groups of cpu0 +bit0: cpu0 depends on logic node0 +bit1: cpu0 depends on logic node1 +bit2: cpu0 depends on logic node2 +bit3: cpu0 depends on logic node3 + 0 + 4 + read-write + + + + + RETENTION_CPU0_VALUE + Retention Contol + 0x920 + 32 + 0x0000000F + 0x0003FFFF + + + LINK + retention setting while system sleep, each bit represents a resource +bit0: soc_pow +bit1: soc_rst +bit2: cpu0_pow +bit3: cpu0_rst +bit4: cpu1_pow +bit5: cpu1_rst +bit6: con_pow +bit7: con_rst +bit8: vis_pow +bit9: vis_rst +bit10: xtal +bit11: pll0 +bit12: pll1 +bit13: pll2 +bit14: pll3 +bit15: pll4 + 0 + 18 + read-write + + + + + RETENTION_CPU0_SET + Retention Contol + 0x924 + 32 + 0x0000000F + 0x0003FFFF + + + LINK + retention setting while system sleep + 0 + 18 + read-write + + + + + RETENTION_CPU0_CLEAR + Retention Contol + 0x928 + 32 + 0x0000000F + 0x0003FFFF + + + LINK + retention setting while system sleep + 0 + 18 + read-write + + + + + RETENTION_CPU0_TOGGLE + Retention Contol + 0x92c + 32 + 0x0000000F + 0x0003FFFF + + + LINK + retention setting while system sleep + 0 + 18 + read-write + + + + + RETENTION_CPU1_VALUE + Retention Contol + 0x930 + 32 + 0x00000000 + 0x0003FFFF + + + LINK + retention setting while system sleep, each bit represents a resource +bit0: soc_pow +bit1: soc_rst +bit2: cpu0_pow +bit3: cpu0_rst +bit4: cpu1_pow +bit5: cpu1_rst +bit6: con_pow +bit7: con_rst +bit8: vis_pow +bit9: vis_rst +bit10: xtal +bit11: pll0 +bit12: pll1 +bit13: pll2 +bit14: pll3 +bit15: pll4 + 0 + 18 + read-write + + + + + RETENTION_CPU1_SET + Retention Contol + 0x934 + 32 + 0x00000000 + 0x0003FFFF + + + LINK + retention setting while system sleep + 0 + 18 + read-write + + + + + RETENTION_CPU1_CLEAR + Retention Contol + 0x938 + 32 + 0x00000000 + 0x0003FFFF + + + LINK + retention setting while system sleep + 0 + 18 + read-write + + + + + RETENTION_CPU1_TOGGLE + Retention Contol + 0x93c + 32 + 0x00000000 + 0x0003FFFF + + + LINK + retention setting while system sleep + 0 + 18 + read-write + + + + + POWER_CPU0_STATUS + Power Setting + 0x1000 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + POWER_CPU0_LF_WAIT + Power Setting + 0x1004 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_CPU0_OFF_WAIT + Power Setting + 0x100c + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_CPU1_STATUS + Power Setting + 0x1010 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + POWER_CPU1_LF_WAIT + Power Setting + 0x1014 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_CPU1_OFF_WAIT + Power Setting + 0x101c + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_CON_STATUS + Power Setting + 0x1020 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + POWER_CON_LF_WAIT + Power Setting + 0x1024 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_CON_OFF_WAIT + Power Setting + 0x102c + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_VIS_STATUS + Power Setting + 0x1030 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + POWER_VIS_LF_WAIT + Power Setting + 0x1034 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_VIS_OFF_WAIT + Power Setting + 0x103c + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + RESET_SOC_CONTROL + Reset Setting + 0x1400 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_SOC_CONFIG + Reset Setting + 0x1404 + 32 + 0x00643203 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_SOC_COUNTER + Reset Setting + 0x140c + 32 + 0x00000000 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + RESET_CON_CONTROL + Reset Setting + 0x1410 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_CON_CONFIG + Reset Setting + 0x1414 + 32 + 0x00000064 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_CON_COUNTER + Reset Setting + 0x141c + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + RESET_VIS_CONTROL + Reset Setting + 0x1420 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_VIS_CONFIG + Reset Setting + 0x1424 + 32 + 0x00000064 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_VIS_COUNTER + Reset Setting + 0x142c + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + RESET_CPU0_CONTROL + Reset Setting + 0x1430 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_CPU0_CONFIG + Reset Setting + 0x1434 + 32 + 0x00000064 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_CPU0_COUNTER + Reset Setting + 0x143c + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + RESET_CPU1_CONTROL + Reset Setting + 0x1440 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_CPU1_CONFIG + Reset Setting + 0x1444 + 32 + 0x00000064 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_CPU1_COUNTER + Reset Setting + 0x144c + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + CLOCK_CLK_TOP_CPU0 + Clock setting + 0x1800 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_MCHTMR0 + Clock setting + 0x1804 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CPU1 + Clock setting + 0x1808 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_MCHTMR + Clock setting + 0x180c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_AXI + Clock setting + 0x1810 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CONN + Clock setting + 0x1814 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_VIS + Clock setting + 0x1818 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_AHB + Clock setting + 0x181c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_DRAM + Clock setting + 0x1820 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_XPI0 + Clock setting + 0x1824 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_XPI1 + Clock setting + 0x1828 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_GPTMR0 + Clock setting + 0x182c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_GPTMR1 + Clock setting + 0x1830 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_GPTMR2 + Clock setting + 0x1834 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_GPTMR3 + Clock setting + 0x1838 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_GPTMR4 + Clock setting + 0x183c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_GPTMR5 + Clock setting + 0x1840 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_GPTMR6 + Clock setting + 0x1844 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_GPTMR7 + Clock setting + 0x1848 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART0 + Clock setting + 0x184c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART1 + Clock setting + 0x1850 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART2 + Clock setting + 0x1854 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART3 + Clock setting + 0x1858 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART4 + Clock setting + 0x185c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART5 + Clock setting + 0x1860 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART6 + Clock setting + 0x1864 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART7 + Clock setting + 0x1868 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART8 + Clock setting + 0x186c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART9 + Clock setting + 0x1870 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART10 + Clock setting + 0x1874 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART11 + Clock setting + 0x1878 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART12 + Clock setting + 0x187c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART13 + Clock setting + 0x1880 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART14 + Clock setting + 0x1884 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_UART15 + Clock setting + 0x1888 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C0 + Clock setting + 0x188c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C1 + Clock setting + 0x1890 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C2 + Clock setting + 0x1894 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C3 + Clock setting + 0x1898 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI0 + Clock setting + 0x189c + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI1 + Clock setting + 0x18a0 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI2 + Clock setting + 0x18a4 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI3 + Clock setting + 0x18a8 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN0 + Clock setting + 0x18ac + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN1 + Clock setting + 0x18b0 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN2 + Clock setting + 0x18b4 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN3 + Clock setting + 0x18b8 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_PTPC + Clock setting + 0x18bc + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA0 + Clock setting + 0x18c0 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA1 + Clock setting + 0x18c4 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA2 + Clock setting + 0x18c8 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_AUD0 + Clock setting + 0x18cc + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_AUD1 + Clock setting + 0x18d0 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_AUD2 + Clock setting + 0x18d4 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_LCDC + Clock setting + 0x18d8 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAM0 + Clock setting + 0x18dc + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAM1 + Clock setting + 0x18e0 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ENET0 + Clock setting + 0x18e4 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ENET1 + Clock setting + 0x18e8 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_PTP0 + Clock setting + 0x18ec + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_PTP1 + Clock setting + 0x18f0 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_REF0 + Clock setting + 0x18f4 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_REF1 + Clock setting + 0x18f8 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_NTMR0 + Clock setting + 0x18fc + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_NTMR1 + Clock setting + 0x1900 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SDXC0 + Clock setting + 0x1904 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SDXC1 + Clock setting + 0x1908 + 32 + 0x00000000 + 0xC0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0:osc0_clk0 +1:pll0_clk0 +2:pll1_clk0 +3:pll1_clk1 +4:pll2_clk0 +5:pll2_clk1 +6:pll3_clk0 +7:pll4_clk0 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by1 +1: divider by 2 +2 divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + ADCCLK_CLK_TOP_ADC0 + Clock setting + 0x1c00 + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: adc clock 0 +2: adc clock 1 +3: adc clock 2 + 8 + 3 + read-write + + + + + ADCCLK_CLK_TOP_ADC1 + Clock setting + 0x1c04 + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: adc clock 0 +2: adc clock 1 +3: adc clock 2 + 8 + 3 + read-write + + + + + ADCCLK_CLK_TOP_ADC2 + Clock setting + 0x1c08 + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: adc clock 0 +2: adc clock 1 +3: adc clock 2 + 8 + 3 + read-write + + + + + ADCCLK_CLK_TOP_ADC3 + Clock setting + 0x1c0c + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: adc clock 0 +2: adc clock 1 +3: adc clock 2 + 8 + 3 + read-write + + + + + I2SCLK_CLK_TOP_I2S0 + Clock setting + 0x1c10 + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: i2s clock 0 +2: i2s clock 1 +3: i2s clock 2 + 8 + 3 + read-write + + + + + I2SCLK_CLK_TOP_I2S1 + Clock setting + 0x1c14 + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: i2s clock 0 +2: i2s clock 1 +3: i2s clock 2 + 8 + 3 + read-write + + + + + I2SCLK_CLK_TOP_I2S2 + Clock setting + 0x1c18 + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: i2s clock 0 +2: i2s clock 1 +3: i2s clock 2 + 8 + 3 + read-write + + + + + I2SCLK_CLK_TOP_I2S3 + Clock setting + 0x1c1c + 32 + 0x00000000 + 0xC0000700 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MUX + clock source selection +0: ahb clock +1: i2s clock 0 +2: i2s clock 1 +3: i2s clock 2 + 8 + 3 + read-write + + + + + GLOBAL00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + PRESET + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 + 0 + 4 + read-write + + + + + MONITOR_SLICE0_CONTROL + Clock measure and monitor control + 0x2400 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + MONITOR_SLICE0_CURRENT + Clock measure result + 0x2404 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE0_LOW_LIMIT + Clock lower limit + 0x2408 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE0_HIGH_LIMIT + Clock upper limit + 0x240c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE1_CONTROL + Clock measure and monitor control + 0x2420 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + MONITOR_SLICE1_CURRENT + Clock measure result + 0x2424 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE1_LOW_LIMIT + Clock lower limit + 0x2428 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE1_HIGH_LIMIT + Clock upper limit + 0x242c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE2_CONTROL + Clock measure and monitor control + 0x2440 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + MONITOR_SLICE2_CURRENT + Clock measure result + 0x2444 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE2_LOW_LIMIT + Clock lower limit + 0x2448 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE2_HIGH_LIMIT + Clock upper limit + 0x244c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE3_CONTROL + Clock measure and monitor control + 0x2460 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + MONITOR_SLICE3_CURRENT + Clock measure result + 0x2464 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE3_LOW_LIMIT + Clock lower limit + 0x2468 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE3_HIGH_LIMIT + Clock upper limit + 0x246c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + CPU_CPU0_LP + No description avaiable + 0x2800 + 32 + 0x00001200 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter saturated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wakeup happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + CPU_CPU0_LOCK + No description avaiable + 0x2804 + 32 + 0x00000002 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + CPU_CPU0_GPR0 + No description avaiable + 0x2808 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR1 + No description avaiable + 0x280c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR2 + No description avaiable + 0x2810 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR3 + No description avaiable + 0x2814 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR4 + No description avaiable + 0x2818 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR5 + No description avaiable + 0x281c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR6 + No description avaiable + 0x2820 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR7 + No description avaiable + 0x2824 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR8 + No description avaiable + 0x2828 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR9 + No description avaiable + 0x282c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR10 + No description avaiable + 0x2830 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR11 + No description avaiable + 0x2834 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR12 + No description avaiable + 0x2838 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR13 + No description avaiable + 0x283c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_STATUS0 + No description avaiable + 0x2840 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS1 + No description avaiable + 0x2844 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS2 + No description avaiable + 0x2848 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS3 + No description avaiable + 0x284c + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS4 + No description avaiable + 0x2850 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS5 + No description avaiable + 0x2854 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS6 + No description avaiable + 0x2858 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_STATUS7 + No description avaiable + 0x285c + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_ENABLE0 + No description avaiable + 0x2880 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE1 + No description avaiable + 0x2884 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE2 + No description avaiable + 0x2888 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE3 + No description avaiable + 0x288c + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE4 + No description avaiable + 0x2890 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE5 + No description avaiable + 0x2894 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE6 + No description avaiable + 0x2898 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_ENABLE7 + No description avaiable + 0x289c + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_LP + No description avaiable + 0x2c00 + 32 + 0x00001200 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter saturated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wakeup happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + CPU_CPU1_LOCK + No description avaiable + 0x2c04 + 32 + 0x00000002 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + CPU_CPU1_GPR0 + No description avaiable + 0x2c08 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR1 + No description avaiable + 0x2c0c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR2 + No description avaiable + 0x2c10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR3 + No description avaiable + 0x2c14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR4 + No description avaiable + 0x2c18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR5 + No description avaiable + 0x2c1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR6 + No description avaiable + 0x2c20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR7 + No description avaiable + 0x2c24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR8 + No description avaiable + 0x2c28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR9 + No description avaiable + 0x2c2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR10 + No description avaiable + 0x2c30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR11 + No description avaiable + 0x2c34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR12 + No description avaiable + 0x2c38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR13 + No description avaiable + 0x2c3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_STATUS0 + No description avaiable + 0x2c40 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_STATUS1 + No description avaiable + 0x2c44 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_STATUS2 + No description avaiable + 0x2c48 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_STATUS3 + No description avaiable + 0x2c4c + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_STATUS4 + No description avaiable + 0x2c50 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_STATUS5 + No description avaiable + 0x2c54 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_STATUS6 + No description avaiable + 0x2c58 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_STATUS7 + No description avaiable + 0x2c5c + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_ENABLE0 + No description avaiable + 0x2c80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_ENABLE1 + No description avaiable + 0x2c84 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_ENABLE2 + No description avaiable + 0x2c88 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_ENABLE3 + No description avaiable + 0x2c8c + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_ENABLE4 + No description avaiable + 0x2c90 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_ENABLE5 + No description avaiable + 0x2c94 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_ENABLE6 + No description avaiable + 0x2c98 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_ENABLE7 + No description avaiable + 0x2c9c + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xf64 + registers + + + + PAD_PA00_FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA00_PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA01_FUNC_CTL + ALT SELECT + 0x8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA01_PAD_CTL + PAD SETTINGS + 0xc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA02_FUNC_CTL + ALT SELECT + 0x10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA02_PAD_CTL + PAD SETTINGS + 0x14 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA03_FUNC_CTL + ALT SELECT + 0x18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA03_PAD_CTL + PAD SETTINGS + 0x1c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA04_FUNC_CTL + ALT SELECT + 0x20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA04_PAD_CTL + PAD SETTINGS + 0x24 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA05_FUNC_CTL + ALT SELECT + 0x28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA05_PAD_CTL + PAD SETTINGS + 0x2c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA06_FUNC_CTL + ALT SELECT + 0x30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA06_PAD_CTL + PAD SETTINGS + 0x34 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA07_FUNC_CTL + ALT SELECT + 0x38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA07_PAD_CTL + PAD SETTINGS + 0x3c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA08_FUNC_CTL + ALT SELECT + 0x40 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA08_PAD_CTL + PAD SETTINGS + 0x44 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA09_FUNC_CTL + ALT SELECT + 0x48 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA09_PAD_CTL + PAD SETTINGS + 0x4c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA10_FUNC_CTL + ALT SELECT + 0x50 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA10_PAD_CTL + PAD SETTINGS + 0x54 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA11_FUNC_CTL + ALT SELECT + 0x58 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA11_PAD_CTL + PAD SETTINGS + 0x5c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA12_FUNC_CTL + ALT SELECT + 0x60 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA12_PAD_CTL + PAD SETTINGS + 0x64 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA13_FUNC_CTL + ALT SELECT + 0x68 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA13_PAD_CTL + PAD SETTINGS + 0x6c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA14_FUNC_CTL + ALT SELECT + 0x70 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA14_PAD_CTL + PAD SETTINGS + 0x74 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA15_FUNC_CTL + ALT SELECT + 0x78 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA15_PAD_CTL + PAD SETTINGS + 0x7c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA16_FUNC_CTL + ALT SELECT + 0x80 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA16_PAD_CTL + PAD SETTINGS + 0x84 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA17_FUNC_CTL + ALT SELECT + 0x88 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA17_PAD_CTL + PAD SETTINGS + 0x8c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA18_FUNC_CTL + ALT SELECT + 0x90 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA18_PAD_CTL + PAD SETTINGS + 0x94 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA19_FUNC_CTL + ALT SELECT + 0x98 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA19_PAD_CTL + PAD SETTINGS + 0x9c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA20_FUNC_CTL + ALT SELECT + 0xa0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA20_PAD_CTL + PAD SETTINGS + 0xa4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA21_FUNC_CTL + ALT SELECT + 0xa8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA21_PAD_CTL + PAD SETTINGS + 0xac + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA22_FUNC_CTL + ALT SELECT + 0xb0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA22_PAD_CTL + PAD SETTINGS + 0xb4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA23_FUNC_CTL + ALT SELECT + 0xb8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA23_PAD_CTL + PAD SETTINGS + 0xbc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA24_FUNC_CTL + ALT SELECT + 0xc0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA24_PAD_CTL + PAD SETTINGS + 0xc4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA25_FUNC_CTL + ALT SELECT + 0xc8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA25_PAD_CTL + PAD SETTINGS + 0xcc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA26_FUNC_CTL + ALT SELECT + 0xd0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA26_PAD_CTL + PAD SETTINGS + 0xd4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA27_FUNC_CTL + ALT SELECT + 0xd8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA27_PAD_CTL + PAD SETTINGS + 0xdc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA28_FUNC_CTL + ALT SELECT + 0xe0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA28_PAD_CTL + PAD SETTINGS + 0xe4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA29_FUNC_CTL + ALT SELECT + 0xe8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA29_PAD_CTL + PAD SETTINGS + 0xec + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA30_FUNC_CTL + ALT SELECT + 0xf0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA30_PAD_CTL + PAD SETTINGS + 0xf4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PA31_FUNC_CTL + ALT SELECT + 0xf8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA31_PAD_CTL + PAD SETTINGS + 0xfc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB00_FUNC_CTL + ALT SELECT + 0x100 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB00_PAD_CTL + PAD SETTINGS + 0x104 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB01_FUNC_CTL + ALT SELECT + 0x108 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB01_PAD_CTL + PAD SETTINGS + 0x10c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB02_FUNC_CTL + ALT SELECT + 0x110 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB02_PAD_CTL + PAD SETTINGS + 0x114 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB03_FUNC_CTL + ALT SELECT + 0x118 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB03_PAD_CTL + PAD SETTINGS + 0x11c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB04_FUNC_CTL + ALT SELECT + 0x120 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB04_PAD_CTL + PAD SETTINGS + 0x124 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB05_FUNC_CTL + ALT SELECT + 0x128 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB05_PAD_CTL + PAD SETTINGS + 0x12c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB06_FUNC_CTL + ALT SELECT + 0x130 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB06_PAD_CTL + PAD SETTINGS + 0x134 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB07_FUNC_CTL + ALT SELECT + 0x138 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB07_PAD_CTL + PAD SETTINGS + 0x13c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB08_FUNC_CTL + ALT SELECT + 0x140 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB08_PAD_CTL + PAD SETTINGS + 0x144 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB09_FUNC_CTL + ALT SELECT + 0x148 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB09_PAD_CTL + PAD SETTINGS + 0x14c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB10_FUNC_CTL + ALT SELECT + 0x150 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB10_PAD_CTL + PAD SETTINGS + 0x154 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB11_FUNC_CTL + ALT SELECT + 0x158 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB11_PAD_CTL + PAD SETTINGS + 0x15c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB12_FUNC_CTL + ALT SELECT + 0x160 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB12_PAD_CTL + PAD SETTINGS + 0x164 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB13_FUNC_CTL + ALT SELECT + 0x168 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB13_PAD_CTL + PAD SETTINGS + 0x16c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB14_FUNC_CTL + ALT SELECT + 0x170 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB14_PAD_CTL + PAD SETTINGS + 0x174 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB15_FUNC_CTL + ALT SELECT + 0x178 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB15_PAD_CTL + PAD SETTINGS + 0x17c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB16_FUNC_CTL + ALT SELECT + 0x180 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB16_PAD_CTL + PAD SETTINGS + 0x184 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB17_FUNC_CTL + ALT SELECT + 0x188 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB17_PAD_CTL + PAD SETTINGS + 0x18c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB18_FUNC_CTL + ALT SELECT + 0x190 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB18_PAD_CTL + PAD SETTINGS + 0x194 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB19_FUNC_CTL + ALT SELECT + 0x198 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB19_PAD_CTL + PAD SETTINGS + 0x19c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB20_FUNC_CTL + ALT SELECT + 0x1a0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB20_PAD_CTL + PAD SETTINGS + 0x1a4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB21_FUNC_CTL + ALT SELECT + 0x1a8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB21_PAD_CTL + PAD SETTINGS + 0x1ac + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB22_FUNC_CTL + ALT SELECT + 0x1b0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB22_PAD_CTL + PAD SETTINGS + 0x1b4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB23_FUNC_CTL + ALT SELECT + 0x1b8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB23_PAD_CTL + PAD SETTINGS + 0x1bc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB24_FUNC_CTL + ALT SELECT + 0x1c0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB24_PAD_CTL + PAD SETTINGS + 0x1c4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB25_FUNC_CTL + ALT SELECT + 0x1c8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB25_PAD_CTL + PAD SETTINGS + 0x1cc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB26_FUNC_CTL + ALT SELECT + 0x1d0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB26_PAD_CTL + PAD SETTINGS + 0x1d4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB27_FUNC_CTL + ALT SELECT + 0x1d8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB27_PAD_CTL + PAD SETTINGS + 0x1dc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB28_FUNC_CTL + ALT SELECT + 0x1e0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB28_PAD_CTL + PAD SETTINGS + 0x1e4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB29_FUNC_CTL + ALT SELECT + 0x1e8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB29_PAD_CTL + PAD SETTINGS + 0x1ec + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB30_FUNC_CTL + ALT SELECT + 0x1f0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB30_PAD_CTL + PAD SETTINGS + 0x1f4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PB31_FUNC_CTL + ALT SELECT + 0x1f8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB31_PAD_CTL + PAD SETTINGS + 0x1fc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC00_FUNC_CTL + ALT SELECT + 0x200 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC00_PAD_CTL + PAD SETTINGS + 0x204 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC01_FUNC_CTL + ALT SELECT + 0x208 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC01_PAD_CTL + PAD SETTINGS + 0x20c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC02_FUNC_CTL + ALT SELECT + 0x210 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC02_PAD_CTL + PAD SETTINGS + 0x214 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC03_FUNC_CTL + ALT SELECT + 0x218 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC03_PAD_CTL + PAD SETTINGS + 0x21c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC04_FUNC_CTL + ALT SELECT + 0x220 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC04_PAD_CTL + PAD SETTINGS + 0x224 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC05_FUNC_CTL + ALT SELECT + 0x228 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC05_PAD_CTL + PAD SETTINGS + 0x22c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC06_FUNC_CTL + ALT SELECT + 0x230 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC06_PAD_CTL + PAD SETTINGS + 0x234 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC07_FUNC_CTL + ALT SELECT + 0x238 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC07_PAD_CTL + PAD SETTINGS + 0x23c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC08_FUNC_CTL + ALT SELECT + 0x240 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC08_PAD_CTL + PAD SETTINGS + 0x244 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC09_FUNC_CTL + ALT SELECT + 0x248 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC09_PAD_CTL + PAD SETTINGS + 0x24c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC10_FUNC_CTL + ALT SELECT + 0x250 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC10_PAD_CTL + PAD SETTINGS + 0x254 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC11_FUNC_CTL + ALT SELECT + 0x258 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC11_PAD_CTL + PAD SETTINGS + 0x25c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC12_FUNC_CTL + ALT SELECT + 0x260 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC12_PAD_CTL + PAD SETTINGS + 0x264 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC13_FUNC_CTL + ALT SELECT + 0x268 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC13_PAD_CTL + PAD SETTINGS + 0x26c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC14_FUNC_CTL + ALT SELECT + 0x270 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC14_PAD_CTL + PAD SETTINGS + 0x274 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC15_FUNC_CTL + ALT SELECT + 0x278 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC15_PAD_CTL + PAD SETTINGS + 0x27c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC16_FUNC_CTL + ALT SELECT + 0x280 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC16_PAD_CTL + PAD SETTINGS + 0x284 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC17_FUNC_CTL + ALT SELECT + 0x288 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC17_PAD_CTL + PAD SETTINGS + 0x28c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC18_FUNC_CTL + ALT SELECT + 0x290 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC18_PAD_CTL + PAD SETTINGS + 0x294 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC19_FUNC_CTL + ALT SELECT + 0x298 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC19_PAD_CTL + PAD SETTINGS + 0x29c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC20_FUNC_CTL + ALT SELECT + 0x2a0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC20_PAD_CTL + PAD SETTINGS + 0x2a4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC21_FUNC_CTL + ALT SELECT + 0x2a8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC21_PAD_CTL + PAD SETTINGS + 0x2ac + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC22_FUNC_CTL + ALT SELECT + 0x2b0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC22_PAD_CTL + PAD SETTINGS + 0x2b4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC23_FUNC_CTL + ALT SELECT + 0x2b8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC23_PAD_CTL + PAD SETTINGS + 0x2bc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC24_FUNC_CTL + ALT SELECT + 0x2c0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC24_PAD_CTL + PAD SETTINGS + 0x2c4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC25_FUNC_CTL + ALT SELECT + 0x2c8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC25_PAD_CTL + PAD SETTINGS + 0x2cc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC26_FUNC_CTL + ALT SELECT + 0x2d0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC26_PAD_CTL + PAD SETTINGS + 0x2d4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC27_FUNC_CTL + ALT SELECT + 0x2d8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC27_PAD_CTL + PAD SETTINGS + 0x2dc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC28_FUNC_CTL + ALT SELECT + 0x2e0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC28_PAD_CTL + PAD SETTINGS + 0x2e4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC29_FUNC_CTL + ALT SELECT + 0x2e8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC29_PAD_CTL + PAD SETTINGS + 0x2ec + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC30_FUNC_CTL + ALT SELECT + 0x2f0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC30_PAD_CTL + PAD SETTINGS + 0x2f4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PC31_FUNC_CTL + ALT SELECT + 0x2f8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC31_PAD_CTL + PAD SETTINGS + 0x2fc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD00_FUNC_CTL + ALT SELECT + 0x300 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD00_PAD_CTL + PAD SETTINGS + 0x304 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD01_FUNC_CTL + ALT SELECT + 0x308 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD01_PAD_CTL + PAD SETTINGS + 0x30c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD02_FUNC_CTL + ALT SELECT + 0x310 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD02_PAD_CTL + PAD SETTINGS + 0x314 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD03_FUNC_CTL + ALT SELECT + 0x318 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD03_PAD_CTL + PAD SETTINGS + 0x31c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD04_FUNC_CTL + ALT SELECT + 0x320 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD04_PAD_CTL + PAD SETTINGS + 0x324 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD05_FUNC_CTL + ALT SELECT + 0x328 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD05_PAD_CTL + PAD SETTINGS + 0x32c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD06_FUNC_CTL + ALT SELECT + 0x330 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD06_PAD_CTL + PAD SETTINGS + 0x334 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD07_FUNC_CTL + ALT SELECT + 0x338 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD07_PAD_CTL + PAD SETTINGS + 0x33c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD08_FUNC_CTL + ALT SELECT + 0x340 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD08_PAD_CTL + PAD SETTINGS + 0x344 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD09_FUNC_CTL + ALT SELECT + 0x348 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD09_PAD_CTL + PAD SETTINGS + 0x34c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD10_FUNC_CTL + ALT SELECT + 0x350 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD10_PAD_CTL + PAD SETTINGS + 0x354 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD11_FUNC_CTL + ALT SELECT + 0x358 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD11_PAD_CTL + PAD SETTINGS + 0x35c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD12_FUNC_CTL + ALT SELECT + 0x360 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD12_PAD_CTL + PAD SETTINGS + 0x364 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD13_FUNC_CTL + ALT SELECT + 0x368 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD13_PAD_CTL + PAD SETTINGS + 0x36c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD14_FUNC_CTL + ALT SELECT + 0x370 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD14_PAD_CTL + PAD SETTINGS + 0x374 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD15_FUNC_CTL + ALT SELECT + 0x378 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD15_PAD_CTL + PAD SETTINGS + 0x37c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD16_FUNC_CTL + ALT SELECT + 0x380 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD16_PAD_CTL + PAD SETTINGS + 0x384 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD17_FUNC_CTL + ALT SELECT + 0x388 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD17_PAD_CTL + PAD SETTINGS + 0x38c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD18_FUNC_CTL + ALT SELECT + 0x390 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD18_PAD_CTL + PAD SETTINGS + 0x394 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD19_FUNC_CTL + ALT SELECT + 0x398 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD19_PAD_CTL + PAD SETTINGS + 0x39c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD20_FUNC_CTL + ALT SELECT + 0x3a0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD20_PAD_CTL + PAD SETTINGS + 0x3a4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD21_FUNC_CTL + ALT SELECT + 0x3a8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD21_PAD_CTL + PAD SETTINGS + 0x3ac + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD22_FUNC_CTL + ALT SELECT + 0x3b0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD22_PAD_CTL + PAD SETTINGS + 0x3b4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD23_FUNC_CTL + ALT SELECT + 0x3b8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD23_PAD_CTL + PAD SETTINGS + 0x3bc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD24_FUNC_CTL + ALT SELECT + 0x3c0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD24_PAD_CTL + PAD SETTINGS + 0x3c4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD25_FUNC_CTL + ALT SELECT + 0x3c8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD25_PAD_CTL + PAD SETTINGS + 0x3cc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD26_FUNC_CTL + ALT SELECT + 0x3d0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD26_PAD_CTL + PAD SETTINGS + 0x3d4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD27_FUNC_CTL + ALT SELECT + 0x3d8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD27_PAD_CTL + PAD SETTINGS + 0x3dc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD28_FUNC_CTL + ALT SELECT + 0x3e0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD28_PAD_CTL + PAD SETTINGS + 0x3e4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD29_FUNC_CTL + ALT SELECT + 0x3e8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD29_PAD_CTL + PAD SETTINGS + 0x3ec + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD30_FUNC_CTL + ALT SELECT + 0x3f0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD30_PAD_CTL + PAD SETTINGS + 0x3f4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PD31_FUNC_CTL + ALT SELECT + 0x3f8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PD31_PAD_CTL + PAD SETTINGS + 0x3fc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE00_FUNC_CTL + ALT SELECT + 0x400 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE00_PAD_CTL + PAD SETTINGS + 0x404 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE01_FUNC_CTL + ALT SELECT + 0x408 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE01_PAD_CTL + PAD SETTINGS + 0x40c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE02_FUNC_CTL + ALT SELECT + 0x410 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE02_PAD_CTL + PAD SETTINGS + 0x414 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE03_FUNC_CTL + ALT SELECT + 0x418 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE03_PAD_CTL + PAD SETTINGS + 0x41c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE04_FUNC_CTL + ALT SELECT + 0x420 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE04_PAD_CTL + PAD SETTINGS + 0x424 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE05_FUNC_CTL + ALT SELECT + 0x428 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE05_PAD_CTL + PAD SETTINGS + 0x42c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE06_FUNC_CTL + ALT SELECT + 0x430 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE06_PAD_CTL + PAD SETTINGS + 0x434 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE07_FUNC_CTL + ALT SELECT + 0x438 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE07_PAD_CTL + PAD SETTINGS + 0x43c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE08_FUNC_CTL + ALT SELECT + 0x440 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE08_PAD_CTL + PAD SETTINGS + 0x444 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE09_FUNC_CTL + ALT SELECT + 0x448 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE09_PAD_CTL + PAD SETTINGS + 0x44c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE10_FUNC_CTL + ALT SELECT + 0x450 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE10_PAD_CTL + PAD SETTINGS + 0x454 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE11_FUNC_CTL + ALT SELECT + 0x458 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE11_PAD_CTL + PAD SETTINGS + 0x45c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE12_FUNC_CTL + ALT SELECT + 0x460 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE12_PAD_CTL + PAD SETTINGS + 0x464 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE13_FUNC_CTL + ALT SELECT + 0x468 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE13_PAD_CTL + PAD SETTINGS + 0x46c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE14_FUNC_CTL + ALT SELECT + 0x470 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE14_PAD_CTL + PAD SETTINGS + 0x474 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE15_FUNC_CTL + ALT SELECT + 0x478 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE15_PAD_CTL + PAD SETTINGS + 0x47c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE16_FUNC_CTL + ALT SELECT + 0x480 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE16_PAD_CTL + PAD SETTINGS + 0x484 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE17_FUNC_CTL + ALT SELECT + 0x488 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE17_PAD_CTL + PAD SETTINGS + 0x48c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE18_FUNC_CTL + ALT SELECT + 0x490 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE18_PAD_CTL + PAD SETTINGS + 0x494 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE19_FUNC_CTL + ALT SELECT + 0x498 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE19_PAD_CTL + PAD SETTINGS + 0x49c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE20_FUNC_CTL + ALT SELECT + 0x4a0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE20_PAD_CTL + PAD SETTINGS + 0x4a4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE21_FUNC_CTL + ALT SELECT + 0x4a8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE21_PAD_CTL + PAD SETTINGS + 0x4ac + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE22_FUNC_CTL + ALT SELECT + 0x4b0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE22_PAD_CTL + PAD SETTINGS + 0x4b4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE23_FUNC_CTL + ALT SELECT + 0x4b8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE23_PAD_CTL + PAD SETTINGS + 0x4bc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE24_FUNC_CTL + ALT SELECT + 0x4c0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE24_PAD_CTL + PAD SETTINGS + 0x4c4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE25_FUNC_CTL + ALT SELECT + 0x4c8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE25_PAD_CTL + PAD SETTINGS + 0x4cc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE26_FUNC_CTL + ALT SELECT + 0x4d0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE26_PAD_CTL + PAD SETTINGS + 0x4d4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE27_FUNC_CTL + ALT SELECT + 0x4d8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE27_PAD_CTL + PAD SETTINGS + 0x4dc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE28_FUNC_CTL + ALT SELECT + 0x4e0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE28_PAD_CTL + PAD SETTINGS + 0x4e4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE29_FUNC_CTL + ALT SELECT + 0x4e8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE29_PAD_CTL + PAD SETTINGS + 0x4ec + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE30_FUNC_CTL + ALT SELECT + 0x4f0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE30_PAD_CTL + PAD SETTINGS + 0x4f4 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PE31_FUNC_CTL + ALT SELECT + 0x4f8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PE31_PAD_CTL + PAD SETTINGS + 0x4fc + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF00_FUNC_CTL + ALT SELECT + 0x500 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF00_PAD_CTL + PAD SETTINGS + 0x504 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF01_FUNC_CTL + ALT SELECT + 0x508 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF01_PAD_CTL + PAD SETTINGS + 0x50c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF02_FUNC_CTL + ALT SELECT + 0x510 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF02_PAD_CTL + PAD SETTINGS + 0x514 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF03_FUNC_CTL + ALT SELECT + 0x518 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF03_PAD_CTL + PAD SETTINGS + 0x51c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF04_FUNC_CTL + ALT SELECT + 0x520 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF04_PAD_CTL + PAD SETTINGS + 0x524 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF05_FUNC_CTL + ALT SELECT + 0x528 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF05_PAD_CTL + PAD SETTINGS + 0x52c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF06_FUNC_CTL + ALT SELECT + 0x530 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF06_PAD_CTL + PAD SETTINGS + 0x534 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF07_FUNC_CTL + ALT SELECT + 0x538 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF07_PAD_CTL + PAD SETTINGS + 0x53c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF08_FUNC_CTL + ALT SELECT + 0x540 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF08_PAD_CTL + PAD SETTINGS + 0x544 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF09_FUNC_CTL + ALT SELECT + 0x548 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF09_PAD_CTL + PAD SETTINGS + 0x54c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PF10_FUNC_CTL + ALT SELECT + 0x550 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PF10_PAD_CTL + PAD SETTINGS + 0x554 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX00_FUNC_CTL + ALT SELECT + 0xd00 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX00_PAD_CTL + PAD SETTINGS + 0xd04 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX01_FUNC_CTL + ALT SELECT + 0xd08 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX01_PAD_CTL + PAD SETTINGS + 0xd0c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX02_FUNC_CTL + ALT SELECT + 0xd10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX02_PAD_CTL + PAD SETTINGS + 0xd14 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX03_FUNC_CTL + ALT SELECT + 0xd18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX03_PAD_CTL + PAD SETTINGS + 0xd1c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX04_FUNC_CTL + ALT SELECT + 0xd20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX04_PAD_CTL + PAD SETTINGS + 0xd24 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX05_FUNC_CTL + ALT SELECT + 0xd28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX05_PAD_CTL + PAD SETTINGS + 0xd2c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX06_FUNC_CTL + ALT SELECT + 0xd30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX06_PAD_CTL + PAD SETTINGS + 0xd34 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX07_FUNC_CTL + ALT SELECT + 0xd38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX07_PAD_CTL + PAD SETTINGS + 0xd3c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX08_FUNC_CTL + ALT SELECT + 0xd40 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX08_PAD_CTL + PAD SETTINGS + 0xd44 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX09_FUNC_CTL + ALT SELECT + 0xd48 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX09_PAD_CTL + PAD SETTINGS + 0xd4c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX10_FUNC_CTL + ALT SELECT + 0xd50 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX10_PAD_CTL + PAD SETTINGS + 0xd54 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PX11_FUNC_CTL + ALT SELECT + 0xd58 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX11_PAD_CTL + PAD SETTINGS + 0xd5c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY00_FUNC_CTL + ALT SELECT + 0xe00 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY00_PAD_CTL + PAD SETTINGS + 0xe04 + 32 + 0x00001110 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY01_FUNC_CTL + ALT SELECT + 0xe08 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY01_PAD_CTL + PAD SETTINGS + 0xe0c + 32 + 0x00001110 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY02_FUNC_CTL + ALT SELECT + 0xe10 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY02_PAD_CTL + PAD SETTINGS + 0xe14 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY03_FUNC_CTL + ALT SELECT + 0xe18 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY03_PAD_CTL + PAD SETTINGS + 0xe1c + 32 + 0x00001110 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY04_FUNC_CTL + ALT SELECT + 0xe20 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY04_PAD_CTL + PAD SETTINGS + 0xe24 + 32 + 0x00001110 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY05_FUNC_CTL + ALT SELECT + 0xe28 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY05_PAD_CTL + PAD SETTINGS + 0xe2c + 32 + 0x00001000 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY06_FUNC_CTL + ALT SELECT + 0xe30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY06_PAD_CTL + PAD SETTINGS + 0xe34 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY07_FUNC_CTL + ALT SELECT + 0xe38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY07_PAD_CTL + PAD SETTINGS + 0xe3c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY08_FUNC_CTL + ALT SELECT + 0xe40 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY08_PAD_CTL + PAD SETTINGS + 0xe44 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY09_FUNC_CTL + ALT SELECT + 0xe48 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY09_PAD_CTL + PAD SETTINGS + 0xe4c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY10_FUNC_CTL + ALT SELECT + 0xe50 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY10_PAD_CTL + PAD SETTINGS + 0xe54 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PY11_FUNC_CTL + ALT SELECT + 0xe58 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY11_PAD_CTL + PAD SETTINGS + 0xe5c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ00_FUNC_CTL + ALT SELECT + 0xf00 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ00_PAD_CTL + PAD SETTINGS + 0xf04 + 32 + 0x00001100 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ01_FUNC_CTL + ALT SELECT + 0xf08 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ01_PAD_CTL + PAD SETTINGS + 0xf0c + 32 + 0x00001110 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ02_FUNC_CTL + ALT SELECT + 0xf10 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ02_PAD_CTL + PAD SETTINGS + 0xf14 + 32 + 0x00001110 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ03_FUNC_CTL + ALT SELECT + 0xf18 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ03_PAD_CTL + PAD SETTINGS + 0xf1c + 32 + 0x00001110 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ04_FUNC_CTL + ALT SELECT + 0xf20 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ04_PAD_CTL + PAD SETTINGS + 0xf24 + 32 + 0x00003000 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ05_FUNC_CTL + ALT SELECT + 0xf28 + 32 + 0x00000001 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ05_PAD_CTL + PAD SETTINGS + 0xf2c + 32 + 0x00003000 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ06_FUNC_CTL + ALT SELECT + 0xf30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ06_PAD_CTL + PAD SETTINGS + 0xf34 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ07_FUNC_CTL + ALT SELECT + 0xf38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ07_PAD_CTL + PAD SETTINGS + 0xf3c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ08_FUNC_CTL + ALT SELECT + 0xf40 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ08_PAD_CTL + PAD SETTINGS + 0xf44 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ09_FUNC_CTL + ALT SELECT + 0xf48 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ09_PAD_CTL + PAD SETTINGS + 0xf4c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ10_FUNC_CTL + ALT SELECT + 0xf50 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ10_PAD_CTL + PAD SETTINGS + 0xf54 + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + PAD_PZ11_FUNC_CTL + ALT SELECT + 0xf58 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ11_PAD_CTL + PAD SETTINGS + 0xf5c + 32 + 0x00001010 + 0x00007817 + + + MS + pin voltage select, only available in high-speed IO +0: 3.3V +1: 1.8V + 14 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 13 + 1 + read-write + + + SMT + schmitt trigger enable, only avaiable in high-speed IO +0: disable +1: enable + 12 + 1 + read-write + + + PS + pull select +0: pull down +1: pull up + 11 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 4 + 1 + read-write + + + DS + drive strength +for high-speed IO 3.3V: +000: 85.61Ohm +001: 61.2 Ohm +010: 42.88Ohm +011: 35.76Ohm +111: 30.67Ohm +for high-speed IO 1.8V: +000: 84.07Ohm +001: 60.14Ohm +010: 42.15Ohm +011: 35.19Ohm +111: 30.2 Ohm +for general IO: +00: 4mA +01: 8mA +11: 12mA + 0 + 3 + read-write + + + + + + + PIOC + PIOC + IOC + 0xf40d8000 + + + BIOC + BIOC + IOC + 0xf5010000 + + + OTPSHW + OTPSHW + OTP + 0xf4080000 + + 0x0 + 0xc08 + registers + + + + SHADOW_SHADOW000 + Fuse shadow registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW001 + Fuse shadow registers + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW002 + Fuse shadow registers + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW003 + Fuse shadow registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW004 + Fuse shadow registers + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW005 + Fuse shadow registers + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW006 + Fuse shadow registers + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW007 + Fuse shadow registers + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW008 + Fuse shadow registers + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW009 + Fuse shadow registers + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW010 + Fuse shadow registers + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW011 + Fuse shadow registers + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW012 + Fuse shadow registers + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW013 + Fuse shadow registers + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW014 + Fuse shadow registers + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW015 + Fuse shadow registers + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW016 + Fuse shadow registers + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW017 + Fuse shadow registers + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW018 + Fuse shadow registers + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW019 + Fuse shadow registers + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW020 + Fuse shadow registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW021 + Fuse shadow registers + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW022 + Fuse shadow registers + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW023 + Fuse shadow registers + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW024 + Fuse shadow registers + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW025 + Fuse shadow registers + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW026 + Fuse shadow registers + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW027 + Fuse shadow registers + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW028 + Fuse shadow registers + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW029 + Fuse shadow registers + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW030 + Fuse shadow registers + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW031 + Fuse shadow registers + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW032 + Fuse shadow registers + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW033 + Fuse shadow registers + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW034 + Fuse shadow registers + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW035 + Fuse shadow registers + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW036 + Fuse shadow registers + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW037 + Fuse shadow registers + 0x94 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW038 + Fuse shadow registers + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW039 + Fuse shadow registers + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW040 + Fuse shadow registers + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW041 + Fuse shadow registers + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW042 + Fuse shadow registers + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW043 + Fuse shadow registers + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW044 + Fuse shadow registers + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW045 + Fuse shadow registers + 0xb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW046 + Fuse shadow registers + 0xb8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW047 + Fuse shadow registers + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW048 + Fuse shadow registers + 0xc0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW049 + Fuse shadow registers + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW050 + Fuse shadow registers + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW051 + Fuse shadow registers + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW052 + Fuse shadow registers + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW053 + Fuse shadow registers + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW054 + Fuse shadow registers + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW055 + Fuse shadow registers + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW056 + Fuse shadow registers + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW057 + Fuse shadow registers + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW058 + Fuse shadow registers + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW059 + Fuse shadow registers + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW060 + Fuse shadow registers + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW061 + Fuse shadow registers + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW062 + Fuse shadow registers + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW063 + Fuse shadow registers + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW064 + Fuse shadow registers + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW065 + Fuse shadow registers + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW066 + Fuse shadow registers + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW067 + Fuse shadow registers + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW068 + Fuse shadow registers + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW069 + Fuse shadow registers + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW070 + Fuse shadow registers + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW071 + Fuse shadow registers + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW072 + Fuse shadow registers + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW073 + Fuse shadow registers + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW074 + Fuse shadow registers + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW075 + Fuse shadow registers + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW076 + Fuse shadow registers + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW077 + Fuse shadow registers + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW078 + Fuse shadow registers + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW079 + Fuse shadow registers + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW080 + Fuse shadow registers + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW081 + Fuse shadow registers + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW082 + Fuse shadow registers + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW083 + Fuse shadow registers + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW084 + Fuse shadow registers + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW085 + Fuse shadow registers + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW086 + Fuse shadow registers + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW087 + Fuse shadow registers + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW088 + Fuse shadow registers + 0x160 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW089 + Fuse shadow registers + 0x164 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW090 + Fuse shadow registers + 0x168 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW091 + Fuse shadow registers + 0x16c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW092 + Fuse shadow registers + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW093 + Fuse shadow registers + 0x174 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW094 + Fuse shadow registers + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW095 + Fuse shadow registers + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW096 + Fuse shadow registers + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW097 + Fuse shadow registers + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW098 + Fuse shadow registers + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW099 + Fuse shadow registers + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW100 + Fuse shadow registers + 0x190 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW101 + Fuse shadow registers + 0x194 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW102 + Fuse shadow registers + 0x198 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW103 + Fuse shadow registers + 0x19c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW104 + Fuse shadow registers + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW105 + Fuse shadow registers + 0x1a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW106 + Fuse shadow registers + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW107 + Fuse shadow registers + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW108 + Fuse shadow registers + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW109 + Fuse shadow registers + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW110 + Fuse shadow registers + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW111 + Fuse shadow registers + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW112 + Fuse shadow registers + 0x1c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW113 + Fuse shadow registers + 0x1c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW114 + Fuse shadow registers + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW115 + Fuse shadow registers + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW116 + Fuse shadow registers + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW117 + Fuse shadow registers + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW118 + Fuse shadow registers + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW119 + Fuse shadow registers + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW120 + Fuse shadow registers + 0x1e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW121 + Fuse shadow registers + 0x1e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW122 + Fuse shadow registers + 0x1e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW123 + Fuse shadow registers + 0x1ec + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW124 + Fuse shadow registers + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW125 + Fuse shadow registers + 0x1f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW126 + Fuse shadow registers + 0x1f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW127 + Fuse shadow registers + 0x1fc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK00 + Fuse shadow lock + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK01 + Fuse shadow lock + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK02 + Fuse shadow lock + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK03 + Fuse shadow lock + 0x20c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK04 + Fuse shadow lock + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK05 + Fuse shadow lock + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK06 + Fuse shadow lock + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK07 + Fuse shadow lock + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_FUSE000 + Fuse Array + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE001 + Fuse Array + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE002 + Fuse Array + 0x408 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE003 + Fuse Array + 0x40c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE004 + Fuse Array + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE005 + Fuse Array + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE006 + Fuse Array + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE007 + Fuse Array + 0x41c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE008 + Fuse Array + 0x420 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE009 + Fuse Array + 0x424 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE010 + Fuse Array + 0x428 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE011 + Fuse Array + 0x42c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE012 + Fuse Array + 0x430 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE013 + Fuse Array + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE014 + Fuse Array + 0x438 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE015 + Fuse Array + 0x43c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE016 + Fuse Array + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE017 + Fuse Array + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE018 + Fuse Array + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE019 + Fuse Array + 0x44c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE020 + Fuse Array + 0x450 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE021 + Fuse Array + 0x454 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE022 + Fuse Array + 0x458 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE023 + Fuse Array + 0x45c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE024 + Fuse Array + 0x460 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE025 + Fuse Array + 0x464 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE026 + Fuse Array + 0x468 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE027 + Fuse Array + 0x46c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE028 + Fuse Array + 0x470 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE029 + Fuse Array + 0x474 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE030 + Fuse Array + 0x478 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE031 + Fuse Array + 0x47c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE032 + Fuse Array + 0x480 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE033 + Fuse Array + 0x484 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE034 + Fuse Array + 0x488 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE035 + Fuse Array + 0x48c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE036 + Fuse Array + 0x490 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE037 + Fuse Array + 0x494 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE038 + Fuse Array + 0x498 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE039 + Fuse Array + 0x49c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE040 + Fuse Array + 0x4a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE041 + Fuse Array + 0x4a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE042 + Fuse Array + 0x4a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE043 + Fuse Array + 0x4ac + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE044 + Fuse Array + 0x4b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE045 + Fuse Array + 0x4b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE046 + Fuse Array + 0x4b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE047 + Fuse Array + 0x4bc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE048 + Fuse Array + 0x4c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE049 + Fuse Array + 0x4c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE050 + Fuse Array + 0x4c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE051 + Fuse Array + 0x4cc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE052 + Fuse Array + 0x4d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE053 + Fuse Array + 0x4d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE054 + Fuse Array + 0x4d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE055 + Fuse Array + 0x4dc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE056 + Fuse Array + 0x4e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE057 + Fuse Array + 0x4e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE058 + Fuse Array + 0x4e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE059 + Fuse Array + 0x4ec + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE060 + Fuse Array + 0x4f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE061 + Fuse Array + 0x4f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE062 + Fuse Array + 0x4f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE063 + Fuse Array + 0x4fc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE064 + Fuse Array + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE065 + Fuse Array + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE066 + Fuse Array + 0x508 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE067 + Fuse Array + 0x50c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE068 + Fuse Array + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE069 + Fuse Array + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE070 + Fuse Array + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE071 + Fuse Array + 0x51c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE072 + Fuse Array + 0x520 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE073 + Fuse Array + 0x524 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE074 + Fuse Array + 0x528 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE075 + Fuse Array + 0x52c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE076 + Fuse Array + 0x530 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE077 + Fuse Array + 0x534 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE078 + Fuse Array + 0x538 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE079 + Fuse Array + 0x53c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE080 + Fuse Array + 0x540 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE081 + Fuse Array + 0x544 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE082 + Fuse Array + 0x548 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE083 + Fuse Array + 0x54c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE084 + Fuse Array + 0x550 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE085 + Fuse Array + 0x554 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE086 + Fuse Array + 0x558 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE087 + Fuse Array + 0x55c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE088 + Fuse Array + 0x560 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE089 + Fuse Array + 0x564 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE090 + Fuse Array + 0x568 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE091 + Fuse Array + 0x56c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE092 + Fuse Array + 0x570 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE093 + Fuse Array + 0x574 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE094 + Fuse Array + 0x578 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE095 + Fuse Array + 0x57c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE096 + Fuse Array + 0x580 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE097 + Fuse Array + 0x584 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE098 + Fuse Array + 0x588 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE099 + Fuse Array + 0x58c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE100 + Fuse Array + 0x590 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE101 + Fuse Array + 0x594 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE102 + Fuse Array + 0x598 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE103 + Fuse Array + 0x59c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE104 + Fuse Array + 0x5a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE105 + Fuse Array + 0x5a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE106 + Fuse Array + 0x5a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE107 + Fuse Array + 0x5ac + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE108 + Fuse Array + 0x5b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE109 + Fuse Array + 0x5b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE110 + Fuse Array + 0x5b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE111 + Fuse Array + 0x5bc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE112 + Fuse Array + 0x5c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE113 + Fuse Array + 0x5c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE114 + Fuse Array + 0x5c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE115 + Fuse Array + 0x5cc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE116 + Fuse Array + 0x5d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE117 + Fuse Array + 0x5d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE118 + Fuse Array + 0x5d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE119 + Fuse Array + 0x5dc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE120 + Fuse Array + 0x5e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE121 + Fuse Array + 0x5e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE122 + Fuse Array + 0x5e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE123 + Fuse Array + 0x5ec + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE124 + Fuse Array + 0x5f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE125 + Fuse Array + 0x5f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE126 + Fuse Array + 0x5f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE127 + Fuse Array + 0x5fc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK00 + Fuse lock + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK01 + Fuse lock + 0x604 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK02 + Fuse lock + 0x608 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK03 + Fuse lock + 0x60c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK04 + Fuse lock + 0x610 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK05 + Fuse lock + 0x614 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK06 + Fuse lock + 0x618 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK07 + Fuse lock + 0x61c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + REGION_LOAD_REGION0 + LOAD region + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + REGION_LOAD_REGION1 + LOAD region + 0xa24 + 32 + 0x00001008 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + REGION_LOAD_REGION2 + LOAD region + 0xa28 + 32 + 0x00000010 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + REGION_LOAD_REGION3 + LOAD region + 0xa2c + 32 + 0x00000000 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + OTP + OTP + OTP + 0xf40c8000 + + + PPOR + PPOR + PPOR + 0xf40c0000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOT + reset type triggered by reset + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TYPE + reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_COLD + reset type attribute + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf40c4000 + + 0x0 + 0x70 + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LOWPOWER_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 24 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0001044C + 0x00010FFF + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x00B010B0 + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: trun off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00B010B0 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000000 + 0x11818191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-write + + + DISABLE_POWER_LOSS + disable power loss protection +0: power loss protection enabled, DCDC shuts down when power loss +1: power loss protection disabled, DCDC try working after power voltage drop + 23 + 1 + read-write + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + ouput over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x00EF1C6E + 0x073F007F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_AUTOLP + enable auto enter low power mode +0: do not enter low power mode +1: enter low power mode if current is detected low + 4 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00EF1C6E + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + SOC power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: clock gated according to low power flow +10: clock is always off +11: clock is always on +bit0-1: fuse +bit2-3: sram +bit4-5: vad +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart +bit16-17:debug + 0 + 32 + read-write + + + + + DEBUG_STOP + Debug stop config + 0x50 + 32 + 0x00000001 + 0x00000003 + + + CPU1 + Stop peripheral when CPU1 enter debug mode +0: peripheral keep running when CPU1 in debug mode +1: peripheral enter debug mode when CPU1 enter debug + 1 + 1 + read-write + + + CPU0 + Stop peripheral when CPU0 enter debug mode +0: peripheral keep running when CPU0 in debug mode +1: peripheral enter debug mode when CPU0 enter debug + 0 + 1 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000316 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + + + PSEC + PSEC + PSEC + 0xf40cc000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + PMON + PMON + PMON + 0xf40d0000 + + 0x0 + 0x48 + registers + + + + MONITOR_GLITCH0_CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_GLITCH0_STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_GLITCH1_CONTROL + Glitch and clock monitor control + 0x8 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_GLITCH1_STATUS + Glitch and clock monitor status + 0xc + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_CONTROL + Glitch and clock monitor control + 0x10 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_STATUS + Glitch and clock monitor status + 0x14 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_CLOCK1_CONTROL + Glitch and clock monitor control + 0x18 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_CLOCK1_STATUS + Glitch and clock monitor status + 0x1c + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + IRQ_FLAG + No description avaiable + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description avaiable + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + PGPR + PGPR + PGPR + 0xf40d4000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + VAD + VAD + VAD + 0xf40ec000 + + 0x0 + 0xa4 + registers + + + + CTRL + Control Register + 0x0 + 32 + 0x00000000 + 0x0FF7FBFF + + + CAPT_DLY + Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + 24 + 4 + read-write + + + PDM_CLK_HFDIV + The clock divider will work at least 4. +0: div-by-2, +1: div-by-4 +. . . +n: div-by-2*(n+1) + 20 + 4 + read-write + + + VAD_IE + VAD event interrupt enable + 18 + 1 + read-write + + + OFIFO_AV_IE + OFIFO data available interrupt enable + 17 + 1 + read-write + + + MEMBUF_EMPTY_IE + Buf empty interrupt enable + 16 + 1 + read-write + + + OFIFO_OVFL_ERR_IE + OFIFO overflow error interrupt enable + 15 + 1 + read-write + + + IIR_OVLD_ERR_IE + IIR overload error interrupt enable + 14 + 1 + read-write + + + IIR_OVFL_ERR_IE + IIR overflow error interrupt enable + 13 + 1 + read-write + + + CIC_OVLD_ERR_IE + CIC overload Interrupt Enable + 12 + 1 + read-write + + + CIC_SAT_ERR_IE + CIC saturation Interrupt Enable + 11 + 1 + read-write + + + MEMBUF_DISABLE + asserted to disable membuf + 9 + 1 + read-write + + + FIFO_THRSH + OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) + 5 + 4 + read-write + + + PDM_CLK_DIV_BYPASS + asserted to bypass the pdm clock divider + 4 + 1 + read-write + + + PDM_CLK_OE + pdm_clk_output_en + 3 + 1 + read-write + + + CH_POL + Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + 1 + 2 + read-write + + + CHNUM + the number of channels to be stored in buffer. Asserted to enable 2 channels. + 0 + 1 + read-write + + + + + FILTCTRL + Filter Control Register + 0x4 + 32 + 0x00000000 + 0x000007FF + + + DECRATIO + the decimation ratio of iir after CIC -1 +2: means dec-by-3 + 8 + 3 + read-write + + + IIR_SLOT_EN + IIR slot enable + 0 + 8 + read-write + + + + + DEC_CTRL0 + Decision Control Register 0 + 0x8 + 32 + 0x00000000 + 0xFFFF03FF + + + NOISE_TOL + the value of amplitude for noise determination when calculationg ZCR + 16 + 16 + read-write + + + BLK_CFG + asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks + 9 + 1 + read-write + + + SUBBLK_LEN + length of sub-block + 0 + 9 + read-write + + + + + DEC_CTRL1 + Decision Control Register 1 + 0xc + 32 + 0x00000000 + 0x003FFFFF + + + ZCR_HIGH + ZCR high limit + 11 + 11 + read-write + + + ZCR_LOW + ZCR low limit + 0 + 11 + read-write + + + + + DEC_CTRL2 + Decision Control Register 2 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + AMP_HIGH + amplitude high limit + 16 + 16 + read-write + + + AMP_LOW + amplitude low limit + 0 + 16 + read-write + + + + + ST + Status + 0x18 + 32 + 0x00000000 + 0x000000FF + + + VAD + VAD event found + 7 + 1 + read-write + + + OFIFO_AV + OFIFO data available + 6 + 1 + read-only + + + MEMBUF_EMPTY + Buf empty + 5 + 1 + read-write + + + OFIFO_OVFL + OFIFO overflow + 4 + 1 + read-write + + + IIR_OVLD + IIR overloading + 3 + 1 + read-write + + + IIR_OVFL + IIR oberflow + 2 + 1 + read-write + + + CIC_OVLD_ERR + CIC overload + 1 + 1 + read-write + + + CIC_SAT_ERR + CIC saturation + 0 + 1 + read-write + + + + + OFIFO + Out FIFO + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + D + The PCM data. +When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). +When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). + 0 + 32 + read-write + + + + + RUN + Run Command Register + 0x20 + 32 + 0x00000000 + 0x00000003 + + + SFTRST + software reset. Self-clear + 1 + 1 + read-write + + + VAD_EN + module enable + 0 + 1 + read-write + + + + + OFIFO_CTRL + Out FIFO Control Register + 0x24 + 32 + 0x00000000 + 0x00000001 + + + EN + Asserted to enable OFIFO + 0 + 1 + read-write + + + + + CIC_CFG + CIC Configuration Register + 0x28 + 32 + 0x00000000 + 0x0000FC00 + + + POST_SCALE + the shift value after CIC results. + 10 + 6 + read-write + + + + + COEF_STE_ACT + Short Time Energy Register + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + The current detected short time energy + 0 + 32 + read-only + + + + + + + PLLCTL + PLLCTL + PLLCTL + 0xf4100000 + + 0x0 + 0x344 + registers + + + + XTAL + Crystal control and status + 0x0 + 32 + 0x00000000 + 0x300FFFFF + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of IRC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + PLL_PLL0_CFG0 + PLLx config0 + 0x80 + 32 + 0x00140460 + 0xBF77FFE8 + + + SS_RSTPTR + reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb + 31 + 1 + read-write + + + REFDIV + refclk diverder, lock when lock_en[24]&~pll_ana_pd + 24 + 6 + read-write + + + POSTDIV1 + lock when lock_en[20]&~pll_ana_pd + 20 + 3 + read-write + + + SS_SPREAD + lock when lock_en[14]&~pll_ana_pd + 14 + 5 + read-write + + + SS_DIVVAL + sscg divval, lock when lock_en[8]&~pll_ana_pd + 8 + 6 + read-write + + + SS_DOWNSPREAD + Downspread control +1’b0 –> Center-Spread +1’b1 –> Downspread + 7 + 1 + read-write + + + SS_RESET + No description avaiable + 6 + 1 + read-write + + + SS_DISABLE_SSCG + No description avaiable + 5 + 1 + read-write + + + DSMPD + 1: int mode; 0: frac mode + 3 + 1 + read-write + + + + + PLL_PLL0_CFG1 + PLLx config1 + 0x84 + 32 + 0x80000000 + 0x86008000 + + + PLLCTRL_HW_EN + 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value +0: full software control PLL settings + 31 + 1 + read-write + + + CLKEN_SW + the clock enable used to gate pll output, should be set after lock, and clear before power down pll. +pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; + 26 + 1 + read-write + + + PLLPD_SW + pll power down. +pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; +pll_pd_soc is just delay of soc enable, for soc to control pll on/off; +pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence + 25 + 1 + read-write + + + LOCK_CNT_CFG + used to wait lock if set larger than lock time; +default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 + 15 + 1 + read-write + + + + + PLL_PLL0_CFG2 + PLLx config2 + 0x88 + 32 + 0x00000000 + 0x00000FFF + + + FBDIV_INT + fbdiv used in int mode + 0 + 12 + read-write + + + + + PLL_PLL0_FREQ + PLLx frac mode frequency adjust + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRAC + PLL output frequency is : +Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 +for default refdiv=1 and postdiv1=1, 24MHz refclk +Fout is 24*fbdiv in int mode +if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) +Fout is 24*fbdiv in int mode +if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) + 8 + 24 + read-write + + + FBDIV_FRAC + fbdiv used in frac mode + 0 + 8 + read-write + + + + + PLL_PLL0_LOCK + PLLx lock control + 0x90 + 32 + 0x00000000 + 0x81104100 + + + LOCK_SS_RSTPTR + lock bit of field ss_rstptr +0: field is open foe software to change +1: field is locked, not changeable + 31 + 1 + read-write + + + LOCK_REFDIV + lock bit of field refdiv +0: field is open foe software to change +1: field is locked, not changeable + 24 + 1 + read-write + + + LOCK_POSTDIV1 + lock bit of field postdiv1 +0: field is open foe software to change +1: field is locked, not changeable + 20 + 1 + read-write + + + LOCK_SS_SPEAD + lock bit of field ss_spead +0: field is open foe software to change +1: field is locked, not changeable + 14 + 1 + read-write + + + LOCK_SS_DIVVAL + lock bit of field ss_divval +0: field is open foe software to change +1: field is locked, not changeable + 8 + 1 + read-write + + + + + PLL_PLL0_STATUS + PLLx status + 0xa0 + 32 + 0x00000000 + 0x08000007 + + + ENABLE + enable from SYSCTL block + 27 + 1 + read-only + + + RESPONSE + response to SYSCTL, PLL is power down when both enable and response are 0. + 2 + 1 + read-only + + + PLL_LOCK_COMB + No description avaiable + 1 + 1 + read-only + + + PLL_LOCK_SYNC + No description avaiable + 0 + 1 + read-only + + + + + PLL_PLL0_DIV0 + PLLx divider0 control + 0xc0 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + PLL_PLL0_DIV1 + PLLx divider1 control + 0xc4 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + PLL_PLL1_CFG0 + PLLx config0 + 0x100 + 32 + 0x00140460 + 0xBF77FFE8 + + + SS_RSTPTR + reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb + 31 + 1 + read-write + + + REFDIV + refclk diverder, lock when lock_en[24]&~pll_ana_pd + 24 + 6 + read-write + + + POSTDIV1 + lock when lock_en[20]&~pll_ana_pd + 20 + 3 + read-write + + + SS_SPREAD + lock when lock_en[14]&~pll_ana_pd + 14 + 5 + read-write + + + SS_DIVVAL + sscg divval, lock when lock_en[8]&~pll_ana_pd + 8 + 6 + read-write + + + SS_DOWNSPREAD + Downspread control +1’b0 –> Center-Spread +1’b1 –> Downspread + 7 + 1 + read-write + + + SS_RESET + No description avaiable + 6 + 1 + read-write + + + SS_DISABLE_SSCG + No description avaiable + 5 + 1 + read-write + + + DSMPD + 1: int mode; 0: frac mode + 3 + 1 + read-write + + + + + PLL_PLL1_CFG1 + PLLx config1 + 0x104 + 32 + 0x80000000 + 0x86008000 + + + PLLCTRL_HW_EN + 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value +0: full software control PLL settings + 31 + 1 + read-write + + + CLKEN_SW + the clock enable used to gate pll output, should be set after lock, and clear before power down pll. +pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; + 26 + 1 + read-write + + + PLLPD_SW + pll power down. +pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; +pll_pd_soc is just delay of soc enable, for soc to control pll on/off; +pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence + 25 + 1 + read-write + + + LOCK_CNT_CFG + used to wait lock if set larger than lock time; +default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 + 15 + 1 + read-write + + + + + PLL_PLL1_CFG2 + PLLx config2 + 0x108 + 32 + 0x00000000 + 0x00000FFF + + + FBDIV_INT + fbdiv used in int mode + 0 + 12 + read-write + + + + + PLL_PLL1_FREQ + PLLx frac mode frequency adjust + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRAC + PLL output frequency is : +Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 +for default refdiv=1 and postdiv1=1, 24MHz refclk +Fout is 24*fbdiv in int mode +if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) +Fout is 24*fbdiv in int mode +if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) + 8 + 24 + read-write + + + FBDIV_FRAC + fbdiv used in frac mode + 0 + 8 + read-write + + + + + PLL_PLL1_LOCK + PLLx lock control + 0x110 + 32 + 0x00000000 + 0x81104100 + + + LOCK_SS_RSTPTR + lock bit of field ss_rstptr +0: field is open foe software to change +1: field is locked, not changeable + 31 + 1 + read-write + + + LOCK_REFDIV + lock bit of field refdiv +0: field is open foe software to change +1: field is locked, not changeable + 24 + 1 + read-write + + + LOCK_POSTDIV1 + lock bit of field postdiv1 +0: field is open foe software to change +1: field is locked, not changeable + 20 + 1 + read-write + + + LOCK_SS_SPEAD + lock bit of field ss_spead +0: field is open foe software to change +1: field is locked, not changeable + 14 + 1 + read-write + + + LOCK_SS_DIVVAL + lock bit of field ss_divval +0: field is open foe software to change +1: field is locked, not changeable + 8 + 1 + read-write + + + + + PLL_PLL1_STATUS + PLLx status + 0x120 + 32 + 0x00000000 + 0x08000007 + + + ENABLE + enable from SYSCTL block + 27 + 1 + read-only + + + RESPONSE + response to SYSCTL, PLL is power down when both enable and response are 0. + 2 + 1 + read-only + + + PLL_LOCK_COMB + No description avaiable + 1 + 1 + read-only + + + PLL_LOCK_SYNC + No description avaiable + 0 + 1 + read-only + + + + + PLL_PLL1_DIV0 + PLLx divider0 control + 0x140 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + PLL_PLL1_DIV1 + PLLx divider1 control + 0x144 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + PLL_PLL2_CFG0 + PLLx config0 + 0x180 + 32 + 0x00140460 + 0xBF77FFE8 + + + SS_RSTPTR + reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb + 31 + 1 + read-write + + + REFDIV + refclk diverder, lock when lock_en[24]&~pll_ana_pd + 24 + 6 + read-write + + + POSTDIV1 + lock when lock_en[20]&~pll_ana_pd + 20 + 3 + read-write + + + SS_SPREAD + lock when lock_en[14]&~pll_ana_pd + 14 + 5 + read-write + + + SS_DIVVAL + sscg divval, lock when lock_en[8]&~pll_ana_pd + 8 + 6 + read-write + + + SS_DOWNSPREAD + Downspread control +1’b0 –> Center-Spread +1’b1 –> Downspread + 7 + 1 + read-write + + + SS_RESET + No description avaiable + 6 + 1 + read-write + + + SS_DISABLE_SSCG + No description avaiable + 5 + 1 + read-write + + + DSMPD + 1: int mode; 0: frac mode + 3 + 1 + read-write + + + + + PLL_PLL2_CFG1 + PLLx config1 + 0x184 + 32 + 0x80000000 + 0x86008000 + + + PLLCTRL_HW_EN + 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value +0: full software control PLL settings + 31 + 1 + read-write + + + CLKEN_SW + the clock enable used to gate pll output, should be set after lock, and clear before power down pll. +pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; + 26 + 1 + read-write + + + PLLPD_SW + pll power down. +pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; +pll_pd_soc is just delay of soc enable, for soc to control pll on/off; +pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence + 25 + 1 + read-write + + + LOCK_CNT_CFG + used to wait lock if set larger than lock time; +default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 + 15 + 1 + read-write + + + + + PLL_PLL2_CFG2 + PLLx config2 + 0x188 + 32 + 0x00000000 + 0x00000FFF + + + FBDIV_INT + fbdiv used in int mode + 0 + 12 + read-write + + + + + PLL_PLL2_FREQ + PLLx frac mode frequency adjust + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRAC + PLL output frequency is : +Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 +for default refdiv=1 and postdiv1=1, 24MHz refclk +Fout is 24*fbdiv in int mode +if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) +Fout is 24*fbdiv in int mode +if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) + 8 + 24 + read-write + + + FBDIV_FRAC + fbdiv used in frac mode + 0 + 8 + read-write + + + + + PLL_PLL2_LOCK + PLLx lock control + 0x190 + 32 + 0x00000000 + 0x81104100 + + + LOCK_SS_RSTPTR + lock bit of field ss_rstptr +0: field is open foe software to change +1: field is locked, not changeable + 31 + 1 + read-write + + + LOCK_REFDIV + lock bit of field refdiv +0: field is open foe software to change +1: field is locked, not changeable + 24 + 1 + read-write + + + LOCK_POSTDIV1 + lock bit of field postdiv1 +0: field is open foe software to change +1: field is locked, not changeable + 20 + 1 + read-write + + + LOCK_SS_SPEAD + lock bit of field ss_spead +0: field is open foe software to change +1: field is locked, not changeable + 14 + 1 + read-write + + + LOCK_SS_DIVVAL + lock bit of field ss_divval +0: field is open foe software to change +1: field is locked, not changeable + 8 + 1 + read-write + + + + + PLL_PLL2_STATUS + PLLx status + 0x1a0 + 32 + 0x00000000 + 0x08000007 + + + ENABLE + enable from SYSCTL block + 27 + 1 + read-only + + + RESPONSE + response to SYSCTL, PLL is power down when both enable and response are 0. + 2 + 1 + read-only + + + PLL_LOCK_COMB + No description avaiable + 1 + 1 + read-only + + + PLL_LOCK_SYNC + No description avaiable + 0 + 1 + read-only + + + + + PLL_PLL2_DIV0 + PLLx divider0 control + 0x1c0 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + PLL_PLL2_DIV1 + PLLx divider1 control + 0x1c4 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + PLL_PLL3_CFG0 + PLLx config0 + 0x200 + 32 + 0x00140460 + 0xBF77FFE8 + + + SS_RSTPTR + reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb + 31 + 1 + read-write + + + REFDIV + refclk diverder, lock when lock_en[24]&~pll_ana_pd + 24 + 6 + read-write + + + POSTDIV1 + lock when lock_en[20]&~pll_ana_pd + 20 + 3 + read-write + + + SS_SPREAD + lock when lock_en[14]&~pll_ana_pd + 14 + 5 + read-write + + + SS_DIVVAL + sscg divval, lock when lock_en[8]&~pll_ana_pd + 8 + 6 + read-write + + + SS_DOWNSPREAD + Downspread control +1’b0 –> Center-Spread +1’b1 –> Downspread + 7 + 1 + read-write + + + SS_RESET + No description avaiable + 6 + 1 + read-write + + + SS_DISABLE_SSCG + No description avaiable + 5 + 1 + read-write + + + DSMPD + 1: int mode; 0: frac mode + 3 + 1 + read-write + + + + + PLL_PLL3_CFG1 + PLLx config1 + 0x204 + 32 + 0x80000000 + 0x86008000 + + + PLLCTRL_HW_EN + 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value +0: full software control PLL settings + 31 + 1 + read-write + + + CLKEN_SW + the clock enable used to gate pll output, should be set after lock, and clear before power down pll. +pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; + 26 + 1 + read-write + + + PLLPD_SW + pll power down. +pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; +pll_pd_soc is just delay of soc enable, for soc to control pll on/off; +pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence + 25 + 1 + read-write + + + LOCK_CNT_CFG + used to wait lock if set larger than lock time; +default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 + 15 + 1 + read-write + + + + + PLL_PLL3_CFG2 + PLLx config2 + 0x208 + 32 + 0x00000000 + 0x00000FFF + + + FBDIV_INT + fbdiv used in int mode + 0 + 12 + read-write + + + + + PLL_PLL3_FREQ + PLLx frac mode frequency adjust + 0x20c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRAC + PLL output frequency is : +Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 +for default refdiv=1 and postdiv1=1, 24MHz refclk +Fout is 24*fbdiv in int mode +if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) +Fout is 24*fbdiv in int mode +if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) + 8 + 24 + read-write + + + FBDIV_FRAC + fbdiv used in frac mode + 0 + 8 + read-write + + + + + PLL_PLL3_LOCK + PLLx lock control + 0x210 + 32 + 0x00000000 + 0x81104100 + + + LOCK_SS_RSTPTR + lock bit of field ss_rstptr +0: field is open foe software to change +1: field is locked, not changeable + 31 + 1 + read-write + + + LOCK_REFDIV + lock bit of field refdiv +0: field is open foe software to change +1: field is locked, not changeable + 24 + 1 + read-write + + + LOCK_POSTDIV1 + lock bit of field postdiv1 +0: field is open foe software to change +1: field is locked, not changeable + 20 + 1 + read-write + + + LOCK_SS_SPEAD + lock bit of field ss_spead +0: field is open foe software to change +1: field is locked, not changeable + 14 + 1 + read-write + + + LOCK_SS_DIVVAL + lock bit of field ss_divval +0: field is open foe software to change +1: field is locked, not changeable + 8 + 1 + read-write + + + + + PLL_PLL3_STATUS + PLLx status + 0x220 + 32 + 0x00000000 + 0x08000007 + + + ENABLE + enable from SYSCTL block + 27 + 1 + read-only + + + RESPONSE + response to SYSCTL, PLL is power down when both enable and response are 0. + 2 + 1 + read-only + + + PLL_LOCK_COMB + No description avaiable + 1 + 1 + read-only + + + PLL_LOCK_SYNC + No description avaiable + 0 + 1 + read-only + + + + + PLL_PLL3_DIV0 + PLLx divider0 control + 0x240 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + PLL_PLL3_DIV1 + PLLx divider1 control + 0x244 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + PLL_PLL4_CFG0 + PLLx config0 + 0x280 + 32 + 0x00140460 + 0xBF77FFE8 + + + SS_RSTPTR + reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb + 31 + 1 + read-write + + + REFDIV + refclk diverder, lock when lock_en[24]&~pll_ana_pd + 24 + 6 + read-write + + + POSTDIV1 + lock when lock_en[20]&~pll_ana_pd + 20 + 3 + read-write + + + SS_SPREAD + lock when lock_en[14]&~pll_ana_pd + 14 + 5 + read-write + + + SS_DIVVAL + sscg divval, lock when lock_en[8]&~pll_ana_pd + 8 + 6 + read-write + + + SS_DOWNSPREAD + Downspread control +1’b0 –> Center-Spread +1’b1 –> Downspread + 7 + 1 + read-write + + + SS_RESET + No description avaiable + 6 + 1 + read-write + + + SS_DISABLE_SSCG + No description avaiable + 5 + 1 + read-write + + + DSMPD + 1: int mode; 0: frac mode + 3 + 1 + read-write + + + + + PLL_PLL4_CFG1 + PLLx config1 + 0x284 + 32 + 0x80000000 + 0x86008000 + + + PLLCTRL_HW_EN + 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value +0: full software control PLL settings + 31 + 1 + read-write + + + CLKEN_SW + the clock enable used to gate pll output, should be set after lock, and clear before power down pll. +pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; + 26 + 1 + read-write + + + PLLPD_SW + pll power down. +pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; +pll_pd_soc is just delay of soc enable, for soc to control pll on/off; +pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence + 25 + 1 + read-write + + + LOCK_CNT_CFG + used to wait lock if set larger than lock time; +default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 + 15 + 1 + read-write + + + + + PLL_PLL4_CFG2 + PLLx config2 + 0x288 + 32 + 0x00000000 + 0x00000FFF + + + FBDIV_INT + fbdiv used in int mode + 0 + 12 + read-write + + + + + PLL_PLL4_FREQ + PLLx frac mode frequency adjust + 0x28c + 32 + 0x00000000 + 0xFFFFFFFF + + + FRAC + PLL output frequency is : +Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 +for default refdiv=1 and postdiv1=1, 24MHz refclk +Fout is 24*fbdiv in int mode +if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) +Fout is 24*fbdiv in int mode +if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) + 8 + 24 + read-write + + + FBDIV_FRAC + fbdiv used in frac mode + 0 + 8 + read-write + + + + + PLL_PLL4_LOCK + PLLx lock control + 0x290 + 32 + 0x00000000 + 0x81104100 + + + LOCK_SS_RSTPTR + lock bit of field ss_rstptr +0: field is open foe software to change +1: field is locked, not changeable + 31 + 1 + read-write + + + LOCK_REFDIV + lock bit of field refdiv +0: field is open foe software to change +1: field is locked, not changeable + 24 + 1 + read-write + + + LOCK_POSTDIV1 + lock bit of field postdiv1 +0: field is open foe software to change +1: field is locked, not changeable + 20 + 1 + read-write + + + LOCK_SS_SPEAD + lock bit of field ss_spead +0: field is open foe software to change +1: field is locked, not changeable + 14 + 1 + read-write + + + LOCK_SS_DIVVAL + lock bit of field ss_divval +0: field is open foe software to change +1: field is locked, not changeable + 8 + 1 + read-write + + + + + PLL_PLL4_STATUS + PLLx status + 0x2a0 + 32 + 0x00000000 + 0x08000007 + + + ENABLE + enable from SYSCTL block + 27 + 1 + read-only + + + RESPONSE + response to SYSCTL, PLL is power down when both enable and response are 0. + 2 + 1 + read-only + + + PLL_LOCK_COMB + No description avaiable + 1 + 1 + read-only + + + PLL_LOCK_SYNC + No description avaiable + 0 + 1 + read-only + + + + + PLL_PLL4_DIV0 + PLLx divider0 control + 0x2c0 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + PLL_PLL4_DIV1 + PLLx divider1 control + 0x2c4 + 32 + 0x00000000 + 0xB00000FF + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + DIV + Divider +0: divide by 1 +1: divide by2 +. . . +255: divide by 256 + 0 + 8 + read-write + + + + + + + BPOR + BPOR + BPOR + 0xf5004000 + + 0x0 + 0x10 + registers + + + + POR_CAUSE + Power on cause + 0x0 + 32 + 0x00000000 + 0x0000001F + + + CAUSE + Power on cause, each bit represnts one cause, write 1 to clear each bit +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_SELECT + Power on select + 0x4 + 32 + 0x00000000 + 0x0000001F + + + SELECT + Power on cause select, each bit represnts one cause, value 1 enables corresponding cause +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_CONFIG + Power on reset config + 0x8 + 32 + 0x00000000 + 0x00000001 + + + RETENTION + retention battery domain setting +0: battery reset on reset pin reset happen +1: battery domain retention when reset pin reset happen + 0 + 1 + read-write + + + + + POR_CONTROL + Power down control + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + COUNTER + Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + 0 + 16 + read-write + + + + + + + BCFG + BCFG + TRIM + 0xf5008000 + + 0x0 + 0x14 + registers + + + + VBG_CFG + Bandgap config + 0x0 + 32 + 0x00000000 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LP_MODE + Bandgap works in low power mode +0: not in low power mode +1: bandgap work in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Bandgap works in power save mode +0: not in power save mode +1: bandgap work in power save mode + 24 + 1 + read-write + + + VBG_1P0 + Bandgap 1.0V output trim + 16 + 5 + read-write + + + VBG_P65 + Bandgap 0.65V output trim + 8 + 5 + read-write + + + VBG_P50 + Bandgap 0.50V output trim + 0 + 5 + read-write + + + + + LDO_CFG + LDO config + 0x4 + 32 + 0x00010000 + 0x03370FFF + + + RES_TRIM + Resistor trim + 24 + 2 + read-write + + + CP_TRIM + Capacitor trim + 20 + 2 + read-write + + + EN_SL + enable selfload, this bit helps improve LDO performance when current less than 200nA +0: self load disabled +1: selfload enabled + 18 + 1 + read-write + + + DIS_PD + disable pull down resistor, enable pull down may lead to more power but better response +0: pulldown resistor enabled +1: pulldown resistor disabled + 17 + 1 + read-write + + + ENABLE + LDO enable +0: LDO is disabled +1: LDO is enabled + 16 + 1 + read-write + + + VOLT + LDO voltage setting in mV, valid range through 600mV to 1100mV, step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1100mV. +600: 600mV +620: 620mV +. . . +1100:1100mV + 0 + 12 + read-write + + + + + IRC32K_CFG + On-chip 32k oscillator config + 0x8 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + XTAL32K_CFG + XTAL 32K config + 0xc + 32 + 0x00000000 + 0x00001313 + + + HYST_EN + crystal 32k hysteres enable + 12 + 1 + read-write + + + GMSEL + crystal 32k gm selection + 8 + 2 + read-write + + + CFG + crystal 32k config + 4 + 1 + read-write + + + AMP + crystal 32k amplifier + 0 + 2 + read-write + + + + + CLK_CFG + Clock config + 0x10 + 32 + 0x00000000 + 0x10010010 + + + XTAL_SEL + crystal selected + 28 + 1 + read-only + + + KEEP_IRC + force irc32k run + 16 + 1 + read-write + + + FORCE_XTAL + force switch to crystal + 4 + 1 + read-write + + + + + + + BUTN + BUTN + BUTN + 0xf500c000 + + 0x0 + 0xc + registers + + + + BTN_STATUS + Button status + 0x0 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + BTN_IRQ_MASK + Button interrupt mask + 0x4 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + LED_INTENSE + Debounce setting + 0x8 + 32 + 0x00000000 + 0x000F000F + + + RLED + Rbutton brightness 0 + 16 + 4 + read-write + + + PLED + Pbutton brightness 0 + 0 + 4 + read-write + + + + + + + BGPR + BGPR + BGPR + 0xf5018000 + + 0x0 + 0x20 + registers + + + + BATT_GPR0 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR1 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR2 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR3 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR4 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR5 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR6 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR7 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + RTCSHW + RTCSHW + RTC + 0xf501c000 + + 0x0 + 0x28 + registers + + + + SECOND + Second counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SECOND + second counter + 0 + 32 + read-write + + + + + SUBSEC + Sub-second counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SUBSEC + sub second counter + 0 + 32 + read-only + + + + + SEC_SNAP + Second counter snap shot + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_SNAP + second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + SUB_SNAP + Sub-second counter snap shot + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SUB_SNAP + sub second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + ALARM0 + RTC alarm0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM0_INC + Alarm0 incremental + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM1 + RTC alarm1 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM1_INC + Alarm1 incremental + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM_FLAG + RTC alarm flag + 0x20 + 32 + 0x00000000 + 0x00000003 + + + ALARM1 + alarm1 happen + 1 + 1 + read-write + + + ALARM0 + alarm0 happen + 0 + 1 + read-write + + + + + ALARM_EN + RTC alarm enable + 0x24 + 32 + 0x00000000 + 0x00000003 + + + ENABLE1 + alarm1 mask +0: alarm1 disabled +1: alarm1 enabled + 1 + 1 + read-write + + + ENABLE0 + alarm0 mask +0: alarm0 disabled +1: alarm0 enabled + 0 + 1 + read-write + + + + + + + RTC + RTC + RTC + 0xf5044000 + + + BSEC + BSEC + BSEC + 0xf5040000 + + 0x0 + 0x14 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x0003000F + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + BATT_FAIL + BATT secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 3 + 1 + read-write + + + BATT_NSC + BATT secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 2 + 1 + read-write + + + BATT_SEC + BATT secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 1 + 1 + read-write + + + BATT_INS + BATT secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 0 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF0003 + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + BATT_ESC_NSC + BATT is escalating non-secure event + 1 + 1 + read-only + + + BATT_ESC_SEC + BATT is escalting ssecure event + 0 + 1 + read-only + + + + + + + BKEY + BKEY + BKEY + 0xf5048000 + + 0x0 + 0x4c + registers + + + + KEY_0_DATA_0 + Key data + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_1 + Key data + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_2 + Key data + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_3 + Key data + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_4 + Key data + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_5 + Key data + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_6 + Key data + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_7 + Key data + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_0 + Key data + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_1 + Key data + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_2 + Key data + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_3 + Key data + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_4 + Key data + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_5 + Key data + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_6 + Key data + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_7 + Key data + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + ECC_KEY0 + Key ECC and access control + 0x40 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + ECC_KEY1 + Key 1 ECC and access control + 0x44 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + SELECT + Key selection + 0x48 + 32 + 0x00000000 + 0x00000001 + + + SELECT + select key, key0 treated as secure key, in non-scure mode, only key1 can be selected +0: select key0 in secure mode, key1 in non-secure mode +1: select key1 in secure or nonsecure mode + 0 + 1 + read-write + + + + + + + BMON + BMON + BMON + 0xf504c000 + + 0x0 + 0x1c + registers + + + + MONITOR_GLITCH0_CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_GLITCH0_STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_CONTROL + Glitch and clock monitor control + 0x10 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_STATUS + Glitch and clock monitor status + 0x14 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + + TAMP + TAMP + TAMP + 0xf5050000 + + 0x0 + 0x88 + registers + + + + TAMP_TAMP0_CONTROL + Tamper n control + 0x0 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP0_POLY + Tamper n Polynomial of LFSR + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP0_LFSR + Tamper n LFSR shift register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP1_CONTROL + Tamper1 control + 0x10 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP1_POLY + Tamper1 Polynomial of LFSR + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP1_LFSR + Tamper1 LFSR shift register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP2_CONTROL + Tamper2 control + 0x20 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP2_POLY + Tamper2 Polynomial of LFSR + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP2_LFSR + Tamper2 LFSR shift register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP3_CONTROL + Tamper3 control + 0x30 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP3_POLY + Tamper3 Polynomial of LFSR + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP3_LFSR + Tamper3 LFSR shift register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP4_CONTROL + Tamper4 control + 0x40 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP4_POLY + Tamper4 Polynomial of LFSR + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP4_LFSR + Tamper4 LFSR shift register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP5_CONTROL + Tamper5 control + 0x50 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP5_POLY + Tamper5 Polynomial of LFSR + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP5_LFSR + Tamper5 LFSR shift register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_FLAG + Tamper flag + 0x80 + 32 + 0x00000000 + 0x00000FFF + + + FLAG + tamper flag, each bit represents one tamper pin, write 1 to clear the flag +Note, clear can only be cleared when tamper disapeared + 0 + 12 + read-write + + + + + IRQ_EN + Tamper interrupt enable + 0x84 + 32 + 0x00000000 + 0x80000FFF + + + LOCK + lock bit for IRQ enable +0: enable bits can be changed +1: enable bits hold until next battery domain power cycle + 31 + 1 + read-write + + + IRQ_EN + interrupt enable, each bit represents one tamper pin +0: interrupt disabled +1: interrupt enabled + 0 + 12 + read-write + + + + + + + MONO + MONO + MONO + 0xf5054000 + + 0x0 + 0x8 + registers + + + + MONOL + Low part of monotonic counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + low part of monotonica counter, write to this counter will cause counter increase by 1 + 0 + 32 + read-write + + + + + MONOH + High part of monotonic counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPOCH + Fuse value for high part of monotonica + 16 + 16 + read-write + + + COUNTER + high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow + 0 + 16 + read-write + + + + + + + \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/SConscript new file mode 100644 index 0000000000..985fd5d7e6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/SConscript @@ -0,0 +1,24 @@ +import os +import sys +Import('rtconfig') +from building import * + +#get current directory +cwd = GetCurrentDir() + +# Update include path +path = [ cwd, cwd + '/boot' ] + +# The set of source files associated with this SConscript file. +src = Split(''' + system.c + hpm_l1c_drv.c + hpm_sysctl_drv.c + hpm_clock_drv.c + boot/hpm_bootheader.c +''') + + +group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) + +Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.c new file mode 100644 index 0000000000..30c2edc202 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_bootheader.h" + +/* symbol exported from startup.S */ +extern uint32_t _start[]; + +/* following symbols exported from linker script */ +extern uint32_t __app_load_addr__[]; +extern uint32_t __app_offset__[]; +extern uint32_t __fw_size__[]; + +#define FW_SIZE (32768) +__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { + (uint32_t)__app_offset__, /* offset */ + (uint32_t)__fw_size__, /* size */ + 0, /* flags */ + 0, /* reserved0 */ + (uint32_t) &__app_load_addr__, /* load_addr */ + 0, /* reserved1 */ + (uint32_t) _start, /* entry_point */ + 0, /* reserved2 */ + {0}, /* hash */ + {0}, /* iv */ +}; + +__attribute__ ((section(".boot_header"))) const boot_header_t header = { + HPM_BOOTHEADER_TAG, /* tag */ + 0x10, /* version*/ + sizeof(header) + sizeof(fw_info), + 0, /* flags */ + 0, /* sw_version */ + 0, /* fuse_version */ + 1, /* fw_count */ + 0, + 0, /* sig_block_offset */ +}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.h new file mode 100644 index 0000000000..c2bf30d0b0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/boot/hpm_bootheader.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BOOT_HEADER_H +#define HPM_BOOT_HEADER_H + +#include "hpm_common.h" + +#define HPM_BOOTHEADER_TAG (0xBFU) +#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) + +#ifndef HPM_BOOT_FW_COUNT +#define HPM_BOOT_FW_COUNT 1 +#endif + +#if HPM_BOOT_FW_COUNT < 1 +#error "HPM_BOOT_FW_COUNT can't be less than 1" +#endif + +typedef struct { + uint32_t offset; /* 0x0: offset to boot_header start */ + uint32_t size; /* 0x4: size in bytes */ + uint32_t flags; /* 0x8: [3:0] fw type: */ + /* 0 - executable */ + /* 1 - cmd container */ + /* [11:8] - hash type */ + /* 0 - none */ + /* 1 - sha256 */ + /* 2 - sm3 */ + uint32_t reserved0; /* 0xC */ + uint32_t load_addr; /* 0x10: load address */ + uint32_t reserved1; /* 0x14 */ + uint32_t entry_point; /* 0x18: application entry */ + uint32_t reserved2; /* 0x1C */ + uint8_t hash[64]; /* 0x20: hash value */ + uint8_t iv[32]; /* 0x60: initial vector */ +} fw_info_table_t; + +typedef struct { + uint8_t tag; /* 0x0: must be '0xbf' */ + uint8_t version; /* 0x1: header version */ + uint16_t length; /* 0x2: header length, max 8KB */ + uint32_t flags; /* 0x4: [3:0] SRK set */ + /* [7:4] SRK index */ + /* [15:8] SRK_REVOKE_MASK */ + /* [19:16] Signature Type */ + /* 1: ECDSA */ + /* 2: SM2 */ + uint16_t sw_version; /* 0x8: software version */ + uint8_t fuse_version; /* 0xA: fuse version */ + uint8_t fw_count; /* 0xB: number of fw */ + uint16_t dc_block_offset; /* 0xC: device config block offset*/ + uint16_t sig_block_offset; /* 0xE: signature block offset */ + /* + * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] + * uint32_t dc_info[]; [> <] + */ +} boot_header_t; + +#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h new file mode 100644 index 0000000000..8d6e337a35 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BATT_IOMUX_H +#define HPM_BATT_IOMUX_H + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ08_FUNC_CTL function mux definitions */ +#define IOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ08_FUNC_CTL_TAMP_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ09_FUNC_CTL function mux definitions */ +#define IOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ09_FUNC_CTL_TAMP_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ10_FUNC_CTL function mux definitions */ +#define IOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ10_FUNC_CTL_HIBERNATE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ10_FUNC_CTL_TAMP_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ11_FUNC_CTL function mux definitions */ +#define IOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ11_FUNC_CTL_STANDBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ11_FUNC_CTL_TAMP_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_BATT_IOMUX_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c new file mode 100644 index 0000000000..0c4736ff5d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c @@ -0,0 +1,512 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_pllctl_drv.h" +#include "hpm_csr_regs.h" +#include "riscv/riscv_core.h" +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define FREQ_1MHz (1000000UL) + +/* Clock preset values */ +#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) +#define FREQ_PRESET1_PLL0_CLK0 (648000000UL) +#define FREQ_PRESET1_PLL1_CLK0 (266000000UL) +#define FREQ_PRESET1_PLL1_CLK1 (400000000UL) +#define FREQ_PRESET1_PLL2_CLK0 (333000000UL) +#define FREQ_PRESET1_PLL2_CLK1 (250000000UL) +#define FREQ_PRESET1_PLL3_CLK0 (614400000UL) +#define FREQ_PRESET1_PLL4_CLK0 (594000000UL) +#define FREQ_32KHz (32768UL) +#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) +#define I2S_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->I2SCLK) +#define WDG_INSTANCE_NUM (4U) + +/* Clock On/Off definitions */ +#define CLOCK_ON (true) +#define CLOCK_OFF (false) + + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ + +/** + * @brief Get Clock frequency for selected clock source + */ +static uint32_t get_frequency_for_source(clock_source_t source); + +/** + * @brief Get Clock frequency for IP in common group + */ +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); + +/** + * @brief Get Clock frequency for I2S or ADC + */ +static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t instance); + +/** + * @brief Get Clock frequency for WDG + */ +static uint32_t get_frequency_for_wdg(uint32_t instance); + +/** + * @brief Turn on/off the IP clock + */ +static void switch_ip_clock(clock_name_t clock_name, bool on); + +static uint64_t get_core_mcycle(void); + +/*********************************************************************************************************************** + * Variables + **********************************************************************************************************************/ +static const clock_node_t s_adc_clk_mux_node[] = { + clock_node_ahb0, + clock_node_ana0, + clock_node_ana1, + clock_node_ana2, +}; +static const clock_node_t s_i2s_clk_mux_node[] = { + clock_node_ahb0, + clock_node_aud0, + clock_node_aud1, + clock_node_aud2, +}; + +static WDG_Type *const s_wdgs[] = { HPM_WDG0, HPM_WDG1, HPM_WDG2, HPM_WDG3 }; + +uint32_t hpm_core_clock; + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +uint32_t clock_get_frequency(clock_name_t clock_name) +{ + uint32_t clk_freq = 0UL; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); + break; + case CLK_SRC_GROUP_ADC: + clk_freq = get_frequency_for_i2s_or_adc(CLK_SRC_GROUP_ADC, node_or_instance); + break; + case CLK_SRC_GROUP_I2S: + clk_freq = get_frequency_for_i2s_or_adc(CLK_SRC_GROUP_I2S, node_or_instance); + break; + case CLK_SRC_GROUP_WDG: + clk_freq = get_frequency_for_wdg(node_or_instance); + break; + case CLK_SRC_GROUP_PMIC: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case CLK_SRC_GROUP_AHB: + clk_freq = get_frequency_for_ip_in_common_group(clock_node_ahb0); + break; + case CLK_SRC_GROUP_AXI0: + clk_freq = get_frequency_for_ip_in_common_group(clock_node_axi0); + break; + case CLK_SRC_GROUP_AXI1: + clk_freq = get_frequency_for_ip_in_common_group(clock_node_axi1); + break; + case CLK_SRC_GROUP_AXI2: + clk_freq = get_frequency_for_ip_in_common_group(clock_node_axi2); + break; + case CLK_SRC_GROUP_CPU0: + clk_freq = get_frequency_for_ip_in_common_group(clock_node_cpu0); + break; + case CLK_SRC_GROUP_CPU1: + clk_freq = get_frequency_for_ip_in_common_group(clock_node_cpu1); + break; + case CLK_SRC_GROUP_SRC: + clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); + break; + default: + clk_freq = 0UL; + break; + } + return clk_freq; +} + +static uint32_t get_frequency_for_source(clock_source_t source) +{ + uint32_t clk_freq = 0UL; + uint32_t div = 1; + switch (source) { + case clock_source_osc0_clk0: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case clock_source_pll0_clk0: + clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 0U); + break; + case clock_source_pll1_clk0: + div = pllctl_get_div(HPM_PLLCTL, 1, 0); + clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 1U) / div; + break; + case clock_source_pll1_clk1: + div = pllctl_get_div(HPM_PLLCTL, 1, 1); + clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 1U) / div; + break; + case clock_source_pll2_clk0: + div = pllctl_get_div(HPM_PLLCTL, 2, 0); + clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 2U) / div; + break; + case clock_source_pll2_clk1: + div = pllctl_get_div(HPM_PLLCTL, 2, 1); + clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 2U) / div; + break; + case clock_source_pll3_clk0: + clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 3U); + break; + case clock_source_pll4_clk0: + clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 4U); + break; + default: + clk_freq = 0UL; + break; + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) +{ + uint32_t clk_freq = 0UL; + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); + + if (node_or_instance < clock_node_end) { + uint32_t clk_node = (uint32_t) node_or_instance; + + uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); + clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); + clk_freq = get_frequency_for_source(clk_mux) / clk_div; + } + return clk_freq; +} + +static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + if (clk_src_type == CLK_SRC_GROUP_ADC) { + uint32_t adc_index = instance; + if (adc_index < ADC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); + if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { + node = s_adc_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + } else { + uint32_t i2s_index = instance; + if (i2s_index < I2S_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[i2s_index]); + if (mux_in_reg < ARRAY_SIZE(s_i2s_clk_mux_node)) { + node = s_i2s_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + } + + if (is_mux_valid) { + clk_freq = get_frequency_for_ip_in_common_group(node); + } + return clk_freq; +} + +static uint32_t get_frequency_for_wdg(uint32_t instance) +{ + uint32_t freq_in_hz; + /* EXT clock is chosen */ + if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { + freq_in_hz = get_frequency_for_ip_in_common_group(clock_node_ahb0); + } + /* PCLK is chosen */ + else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +clk_src_t clock_get_source(clock_name_t clock_name) +{ + uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; + uint8_t clk_src_index = 0xFU; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_ADC: + if (node_or_instance < ADC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_ADC; + clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_I2S: + if (node_or_instance < I2S_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_I2S; + clk_src_index = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_WDG; + clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); + } + break; + case CLK_SRC_GROUP_PMIC: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = clock_source_osc0_clk0; + break; + case CLK_SRC_GROUP_AHB: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_ahb0]); + break; + case CLK_SRC_GROUP_AXI0: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi0]); + break; + case CLK_SRC_GROUP_AXI1: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi1]); + break; + case CLK_SRC_GROUP_AXI2: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi2]); + break; + case CLK_SRC_GROUP_CPU0: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_cpu0]); + break; + case CLK_SRC_GROUP_CPU1: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_cpu1]); + break; + case CLK_SRC_GROUP_SRC: + clk_src_index = (clk_src_t) node_or_instance; + break; + default: + clk_src_group = CLK_SRC_GROUP_INVALID; + break; + } + + clk_src_t clk_src; + if (clk_src_group != CLK_SRC_GROUP_INVALID) { + clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); + } else { + clk_src = clk_src_invalid; + } + + return clk_src; +} + +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src <= clk_adc_src_ahb0) || (src >= clk_adc_src_ana2)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->ADCCLK[node_or_instance] = + (HPM_SYSCTL->ADCCLK[node_or_instance] & SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_I2S) || (node_or_instance >= I2S_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src <= clk_i2s_src_ahb0) || (src >= clk_i2s_src_aud2)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->I2SCLK[node_or_instance] = + (HPM_SYSCTL->I2SCLK[node_or_instance] & SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) +{ + hpm_stat_t status = status_success; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + if ((div < 1U) || (div > 256U)) { + status = status_clk_div_invalid; + } else { + clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); + sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); + } + break; + case CLK_SRC_GROUP_ADC: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_I2S: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + if (src == clk_wdg_src_ahb0) { + s_wdgs[node_or_instance]->CTRL &= ~WDG_CTRL_CLKSEL_MASK; + } else if (src == clk_wdg_src_osc32k) { + s_wdgs[node_or_instance]->CTRL |= WDG_CTRL_CLKSEL_MASK; + } else { + status = status_clk_src_invalid; + } + } + break; + case CLK_SRC_GROUP_PMIC: + status = status_clk_fixed; + break; + case CLK_SRC_GROUP_AHB: + status = status_clk_shared_ahb; + break; + case CLK_SRC_GROUP_AXI0: + status = status_clk_shared_axi0; + break; + case CLK_SRC_GROUP_AXI1: + status = status_clk_shared_axi1; + break; + case CLK_SRC_GROUP_AXI2: + status = status_clk_shared_axi2; + break; + case CLK_SRC_GROUP_CPU0: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_CPU1: + status = status_clk_shared_cpu1; + break; + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; + break; + default: + status = status_clk_src_invalid; + break; + } + + return status; +} + +void switch_ip_clock(clock_name_t clock_name, bool on) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + uint32_t mode = on ? 1UL : 2UL; + HPM_SYSCTL->RESOURCE[resource] = + (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + } +} + + +void clock_enable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_ON); +} + +void clock_disable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_OFF); +} + +void clock_add_to_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); + } +} + +void clock_remove_from_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); + } +} + +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 2U) { + HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); + } +} + +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 2U) { + HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); + } +} + + +static uint64_t get_core_mcycle(void) +{ + uint64_t result; + uint32_t resultl_first = read_csr(CSR_CYCLE); + uint32_t resulth = read_csr(CSR_CYCLEH); + uint32_t resultl_second = read_csr(CSR_CYCLE); + if (resultl_first < resultl_second) { + result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ + } else { + resulth = read_csr(CSR_CYCLEH); + result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ + } + return result; + } + +void clock_cpu_delay_us(uint32_t us) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = get_core_mcycle() + ticks_per_us * us; + while (get_core_mcycle() < expected_ticks) { + } +} + +void clock_cpu_delay_ms(uint32_t ms) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (get_core_mcycle() < expected_ticks) { + } +} + +void clock_update_core_clock(void) +{ + uint32_t hart_id = read_csr(CSR_MHARTID); + clock_name_t cpu_clk_name = (hart_id == 1U) ? clock_cpu1 : clock_cpu0; + hpm_core_clock = clock_get_frequency(cpu_clk_name); +} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h new file mode 100644 index 0000000000..4da5b1f1c5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CLOCK_DRV_H +#define HPM_CLOCK_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_drv.h" + +/** + * @brief CLOCK driver APIs + * @defgroup clock_interface CLOCK driver APIs + * @{ + * + */ + +/** + * @brief Error codes for clock driver + */ +enum { + status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), /**< Clock divider is invalid */ + status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), /**< Clock source is invalid */ + status_clk_invalid = MAKE_STATUS(status_group_clk, 2), /**< Clock name is invalid */ + status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), /**< Clock operation is unsupported */ + status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), /**< The clock source is shared with AHB */ + status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), /**< The clock source is shared with AXI0 */ + status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), /**< THe clock source is shared with AXI1 */ + status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), /**< The clock source is shared with AXI2 */ + status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), /**< The clock source is shared with CPU0 */ + status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), /**< The clock source is shared with CPU1 */ + status_clk_fixed = MAKE_STATUS(status_group_clk, 10), /**< The clock source is a fixed clock source */ + +}; + +/** + * @brief Clock source group definitions + */ +#define CLK_SRC_GROUP_COMMON (0U) +#define CLK_SRC_GROUP_ADC (1U) +#define CLK_SRC_GROUP_I2S (2U) +#define CLK_SRC_GROUP_WDG (3U) +#define CLK_SRC_GROUP_PMIC (4U) +#define CLK_SRC_GROUP_AHB (5U) +#define CLK_SRC_GROUP_AXI0 (6U) +#define CLK_SRC_GROUP_AXI1 (7U) +#define CLK_SRC_GROUP_AXI2 (8U) +#define CLK_SRC_GROUP_CPU0 (9U) +#define CLK_SRC_GROUP_CPU1 (10U) +#define CLK_SRC_GROUP_SRC (11U) +#define CLK_SRC_GROUP_INVALID (15U) + +#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp) << 4) | (index)) +#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src) >> 4) & 0x0FU) +#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src)&0x0FU) + +#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) + +/** + * @brief Clock source definitions + */ +typedef enum _clock_sources { + clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), + clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), + clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), + clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), + clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), + clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), + clk_src_pll3_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), + clk_src_pll4_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), + clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), + + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 2), + clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 3), + + clk_i2s_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), + clk_i2s_src_aud0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 1), + clk_i2s_src_aud1 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 2), + clk_i2s_src_aud2 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 3), + + clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), + clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), +} clk_src_t; + +#define RESOURCE_INVALID (0xFFFFU) + +/* Clock NAME related Macros */ +#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)node)) +#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) +#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name)&0xFFUL) +#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) + +/** + * @brief Peripheral Clock Type Description + */ +typedef enum _clock_name { + clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_COMMON, clock_node_cpu0), + clock_cpu1 = MAKE_CLOCK_NAME(sysctl_resource_cpu1, CLK_SRC_GROUP_COMMON, clock_node_cpu1), + clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), + clock_mchtmr1 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr1, CLK_SRC_GROUP_COMMON, clock_node_mchtmr1), + clock_axi0 = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_COMMON, clock_node_axi0), + clock_axi1 = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_COMMON, clock_node_axi1), + clock_axi2 = MAKE_CLOCK_NAME(sysctl_resource_axiv, CLK_SRC_GROUP_COMMON, clock_node_axi2), + clock_ahb = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_COMMON, clock_node_ahb0), + clock_dram = MAKE_CLOCK_NAME(sysctl_resource_dram, CLK_SRC_GROUP_COMMON, clock_node_dram), + clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), + clock_xpi1 = MAKE_CLOCK_NAME(sysctl_resource_xpi1, CLK_SRC_GROUP_COMMON, clock_node_xpi1), + clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), + clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), + clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), + clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), + clock_gptmr4 = MAKE_CLOCK_NAME(sysctl_resource_gptmr4, CLK_SRC_GROUP_COMMON, clock_node_gptmr4), + clock_gptmr5 = MAKE_CLOCK_NAME(sysctl_resource_gptmr5, CLK_SRC_GROUP_COMMON, clock_node_gptmr5), + clock_gptmr6 = MAKE_CLOCK_NAME(sysctl_resource_gptmr6, CLK_SRC_GROUP_COMMON, clock_node_gptmr6), + clock_gptmr7 = MAKE_CLOCK_NAME(sysctl_resource_gptmr7, CLK_SRC_GROUP_COMMON, clock_node_gptmr7), + clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), + clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), + clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), + clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), + clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), + clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), + clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), + clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), + clock_uart8 = MAKE_CLOCK_NAME(sysctl_resource_uart8, CLK_SRC_GROUP_COMMON, clock_node_uart8), + clock_uart9 = MAKE_CLOCK_NAME(sysctl_resource_uart9, CLK_SRC_GROUP_COMMON, clock_node_uart9), + clock_uart10 = MAKE_CLOCK_NAME(sysctl_resource_uarta, CLK_SRC_GROUP_COMMON, clock_node_uarta), + clock_uart11 = MAKE_CLOCK_NAME(sysctl_resource_uartb, CLK_SRC_GROUP_COMMON, clock_node_uartb), + clock_uart12 = MAKE_CLOCK_NAME(sysctl_resource_uartc, CLK_SRC_GROUP_COMMON, clock_node_uartc), + clock_uart13 = MAKE_CLOCK_NAME(sysctl_resource_uartd, CLK_SRC_GROUP_COMMON, clock_node_uartd), + clock_uart14 = MAKE_CLOCK_NAME(sysctl_resource_uarte, CLK_SRC_GROUP_COMMON, clock_node_uarte), + clock_uart15 = MAKE_CLOCK_NAME(sysctl_resource_uartf, CLK_SRC_GROUP_COMMON, clock_node_uartf), + clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), + clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), + clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), + clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), + clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), + clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), + clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), + clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), + clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), + clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), + clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), + clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), + clock_display = MAKE_CLOCK_NAME(sysctl_resource_dis0, CLK_SRC_GROUP_COMMON, clock_node_dis0), + clock_sdxc0 = MAKE_CLOCK_NAME(sysctl_resource_sdxc0, CLK_SRC_GROUP_COMMON, clock_node_sdxc0), + clock_sdxc1 = MAKE_CLOCK_NAME(sysctl_resource_sdxc1, CLK_SRC_GROUP_COMMON, clock_node_sdxc1), + clock_camera0 = MAKE_CLOCK_NAME(sysctl_resource_cam0, CLK_SRC_GROUP_COMMON, clock_node_cam0), + clock_camera1 = MAKE_CLOCK_NAME(sysctl_resource_cam1, CLK_SRC_GROUP_COMMON, clock_node_cam1), + clock_ntmr0 = MAKE_CLOCK_NAME(sysctl_resource_ntmr0, CLK_SRC_GROUP_COMMON, clock_node_ntmr0), + clock_ntmr1 = MAKE_CLOCK_NAME(sysctl_resource_ntmr1, CLK_SRC_GROUP_COMMON, clock_node_ntmr1), + + clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), + clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), + clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), + clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), + clock_watchdog2 = MAKE_CLOCK_NAME(sysctl_resource_wdg2, CLK_SRC_GROUP_WDG, 2), + clock_watchdog3 = MAKE_CLOCK_NAME(sysctl_resource_wdg3, CLK_SRC_GROUP_WDG, 3), + clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), + clock_eth1 = MAKE_CLOCK_NAME(sysctl_resource_eth1, CLK_SRC_GROUP_COMMON, clock_node_eth1), + clock_ptp0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ptp0), + clock_ptp1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ptp1), + clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI0, 0), + clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI0, 1), + clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI0, 2), + clock_ram0 = MAKE_CLOCK_NAME(sysctl_resource_ram0, CLK_SRC_GROUP_AXI0, 3), + clock_ram1 = MAKE_CLOCK_NAME(sysctl_resource_ram1, CLK_SRC_GROUP_AXI0, 4), + clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI1, 0), + clock_usb1 = MAKE_CLOCK_NAME(sysctl_resource_usb1, CLK_SRC_GROUP_AXI1, 1), + clock_jpeg = MAKE_CLOCK_NAME(sysctl_resource_jpeg, CLK_SRC_GROUP_AXI2, 0), + clock_pdma = MAKE_CLOCK_NAME(sysctl_resource_pdma, CLK_SRC_GROUP_AXI2, 1), + clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 0), + clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 1), + clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 2), + clock_mbx1 = MAKE_CLOCK_NAME(sysctl_resource_mbx1, CLK_SRC_GROUP_AHB, 3), + clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AHB, 4), + clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 5), + clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 6), + clock_mot1 = MAKE_CLOCK_NAME(sysctl_resource_mot1, CLK_SRC_GROUP_AHB, 7), + clock_mot2 = MAKE_CLOCK_NAME(sysctl_resource_mot2, CLK_SRC_GROUP_AHB, 8), + clock_mot3 = MAKE_CLOCK_NAME(sysctl_resource_mot3, CLK_SRC_GROUP_AHB, 9), + clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), + clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_i2spdm0, CLK_SRC_GROUP_AHB, 11), + clock_dao = MAKE_CLOCK_NAME(sysctl_resource_i2sdao, CLK_SRC_GROUP_AHB, 12), + clock_msyn = MAKE_CLOCK_NAME(sysctl_resource_msyn, CLK_SRC_GROUP_AHB, 12), + clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), + clock_lmm1 = MAKE_CLOCK_NAME(sysctl_resource_lmm1, CLK_SRC_GROUP_CPU1, 0), + + /* For ADC, there are 2-stage clock source and divider configuration */ + clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), + clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), + clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), + clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), + clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), + clock_adc2 = MAKE_CLOCK_NAME(sysctl_resource_adc2, CLK_SRC_GROUP_ADC, 2), + clock_adc3 = MAKE_CLOCK_NAME(sysctl_resource_adc3, CLK_SRC_GROUP_ADC, 3), + + /* For I2S, there are 2-stage clock source and divider configuration */ + clock_aud0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud0), + clock_aud1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud1), + clock_aud2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud2), + clock_i2s0 = MAKE_CLOCK_NAME(sysctl_resource_i2s0, CLK_SRC_GROUP_I2S, 0), + clock_i2s1 = MAKE_CLOCK_NAME(sysctl_resource_i2s1, CLK_SRC_GROUP_I2S, 1), + clock_i2s2 = MAKE_CLOCK_NAME(sysctl_resource_i2s2, CLK_SRC_GROUP_I2S, 2), + clock_i2s3 = MAKE_CLOCK_NAME(sysctl_resource_i2s3, CLK_SRC_GROUP_I2S, 3), + + /* Clock sources */ + clk_osc0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 1), + clk_pll1clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 2), + clk_pll1clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 3), + clk_pll2clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 4), + clk_pll2clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 5), + clk_pll3clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 6), + clk_pll4clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 7), +} clock_name_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Get specified IP frequency + * @param[in] clock_name IP clock name + * + * @return IP clock frequency in Hz + */ + uint32_t clock_get_frequency(clock_name_t clock_name); + + /** + * @brief Get the IP clock source + * Note: This API return the direct clock source + * @return IP clock source + */ + clk_src_t clock_get_source(clock_name_t clock_name); + + /** + * @brief Set ADC clock source + * @param[in] clock_name ADC clock name + * @param[in] src ADC clock source + * + * @retval status_success Setting ADC clock source is successful + * @retval status_clk_invalid Invalid ADC clock + * @retval status_clk_src_invalid Invalid ADC clock source + */ + hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); + + /** + * @brief Set I2S clock source + * @param[in] clock_name I2S clock name + * @param[in] src I2S clock source + * + * @retval status_success Setting I2S clock source is successful + * @retval status_clk_invalid Invalid I2S clock + * @retval status_clk_src_invalid Invalid I2S clock source + */ + hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src); + + /** + * @brief Set the IP clock source and divider + * @param[in] clock_name clock name + * @param[in] src clock source + * @param[in] div clock divider, valid range (1 - 256) + * + * @retval status_success Setting Clock source and divider is successful. + * @retval status_clk_set_by_other_api The clock should be set by other API + * @retval status_clk_src_invalid clock source is invalid. + * @retval status_clk_fixed clock source and divider is a fixed value + * @retval status_clk_shared_ahb Clock is shared with the AHB clock + * @retval status_clk_shared_axi0 Clock is shared with the AXI0 clock + * @retval status_clk_shared_axi1 CLock is shared with the AXI1 clock + * @retval status_clk_shared_axi2 Clock is shared with the AXI2 clock + * @retval status_clk_shared_cpu0 Clock is shared with the CPU0 clock + * @retval status_clk_shared_cpu1 Clock is shared with the CPU1 clock + */ + hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); + + /** + * @brief Enable IP clock + * @param[in] clock_name IP clock name + */ + void clock_enable(clock_name_t clock_name); + + /** + * @brief Disable IP clock + * @param[in] clock_name IP clock name + */ + void clock_disable(clock_name_t clock_name); + + /** + * @brief Add IP to specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ + void clock_add_to_group(clock_name_t clock_name, uint32_t group); + + /** + * @brief Remove IP from specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ + void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + + /** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ + void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); + + /** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ + void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); + + + /** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ + void clock_cpu_delay_us(uint32_t us); + + /** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ + void clock_cpu_delay_ms(uint32_t ms); + + /** + * @brief Update the Core clock frequency + */ + void clock_update_core_clock(void); + + /** + * @brief HPM Core clock variable + */ + extern uint32_t hpm_core_clock; + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h new file mode 100644 index 0000000000..72f6fb746f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h @@ -0,0 +1,6512 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CSR_H +#define HPM_CSR_H + +/* STANDARD CRS address definition */ +#define CSR_USTATUS (0x0) +#define CSR_UIE (0x4) +#define CSR_UTVEC (0x5) +#define CSR_USCRATCH (0x40) +#define CSR_UEPC (0x41) +#define CSR_UCAUSE (0x42) +#define CSR_UTVAL (0x43) +#define CSR_UIP (0x44) +#define CSR_SSTATUS (0x100) +#define CSR_SEDELEG (0x102) +#define CSR_SIDELEG (0x103) +#define CSR_SIE (0x104) +#define CSR_STVEC (0x105) +#define CSR_SSCRATCH (0x140) +#define CSR_SEPC (0x141) +#define CSR_SCAUSE (0x142) +#define CSR_STVAL (0x143) +#define CSR_SIP (0x144) +#define CSR_SATP (0x180) +#define CSR_MSTATUS (0x300) +#define CSR_MISA (0x301) +#define CSR_MEDELEG (0x302) +#define CSR_MIDELEG (0x303) +#define CSR_MIE (0x304) +#define CSR_MTVEC (0x305) +#define CSR_MCOUNTEREN (0x306) +#define CSR_MHPMEVENT3 (0x323) +#define CSR_MHPMEVENT4 (0x324) +#define CSR_MHPMEVENT5 (0x325) +#define CSR_MHPMEVENT6 (0x326) +#define CSR_MSCRATCH (0x340) +#define CSR_MEPC (0x341) +#define CSR_MCAUSE (0x342) +#define CSR_MTVAL (0x343) +#define CSR_MIP (0x344) +#define CSR_PMPCFG0 (0x3A0) +#define CSR_PMPCFG1 (0x3A1) +#define CSR_PMPCFG2 (0x3A2) +#define CSR_PMPCFG3 (0x3A3) +#define CSR_PMPADDR0 (0x3B0) +#define CSR_PMPADDR1 (0x3B1) +#define CSR_PMPADDR2 (0x3B2) +#define CSR_PMPADDR3 (0x3B3) +#define CSR_PMPADDR4 (0x3B4) +#define CSR_PMPADDR5 (0x3B5) +#define CSR_PMPADDR6 (0x3B6) +#define CSR_PMPADDR7 (0x3B7) +#define CSR_PMPADDR8 (0x3B8) +#define CSR_PMPADDR9 (0x3B9) +#define CSR_PMPADDR10 (0x3BA) +#define CSR_PMPADDR11 (0x3BB) +#define CSR_PMPADDR12 (0x3BC) +#define CSR_PMPADDR13 (0x3BD) +#define CSR_PMPADDR14 (0x3BE) +#define CSR_PMPADDR15 (0x3BF) +#define CSR_TSELECT (0x7A0) +#define CSR_TDATA1 (0x7A1) +#define CSR_MCONTROL (0x7A1) +#define CSR_ICOUNT (0x7A1) +#define CSR_ITRIGGER (0x7A1) +#define CSR_ETRIGGER (0x7A1) +#define CSR_TDATA2 (0x7A2) +#define CSR_TDATA3 (0x7A3) +#define CSR_TEXTRA (0x7A3) +#define CSR_TINFO (0x7A4) +#define CSR_TCONTROL (0x7A5) +#define CSR_MCONTEXT (0x7A8) +#define CSR_SCONTEXT (0x7AA) +#define CSR_DCSR (0x7B0) +#define CSR_DPC (0x7B1) +#define CSR_DSCRATCH0 (0x7B2) +#define CSR_DSCRATCH1 (0x7B3) +#define CSR_MCYCLE (0xB00) +#define CSR_MINSTRET (0xB02) +#define CSR_MHPMCOUNTER3 (0xB03) +#define CSR_MHPMCOUNTER4 (0xB04) +#define CSR_MHPMCOUNTER5 (0xB05) +#define CSR_MHPMCOUNTER6 (0xB06) +#define CSR_MCYCLEH (0xB80) +#define CSR_MINSTRETH (0xB82) +#define CSR_MHPMCOUNTER3H (0xB83) +#define CSR_MHPMCOUNTER4H (0xB84) +#define CSR_MHPMCOUNTER5H (0xB85) +#define CSR_MHPMCOUNTER6H (0xB86) +#define CSR_PMACFG0 (0xBC0) +#define CSR_PMACFG1 (0xBC1) +#define CSR_PMACFG2 (0xBC2) +#define CSR_PMACFG3 (0xBC3) +#define CSR_PMAADDR0 (0xBD0) +#define CSR_PMAADDR1 (0xBD1) +#define CSR_PMAADDR2 (0xBD2) +#define CSR_PMAADDR3 (0xBD3) +#define CSR_PMAADDR4 (0xBD4) +#define CSR_PMAADDR5 (0xBD5) +#define CSR_PMAADDR6 (0xBD6) +#define CSR_PMAADDR7 (0xBD7) +#define CSR_PMAADDR8 (0xBD8) +#define CSR_PMAADDR9 (0xBD9) +#define CSR_PMAADDR10 (0xBDA) +#define CSR_PMAADDR11 (0xBDB) +#define CSR_PMAADDR12 (0xBDC) +#define CSR_PMAADDR13 (0xBDD) +#define CSR_PMAADDR14 (0xBDE) +#define CSR_PMAADDR15 (0xBDF) +#define CSR_CYCLE (0xC00) +#define CSR_CYCLEH (0xC80) +#define CSR_MVENDORID (0xF11) +#define CSR_MARCHID (0xF12) +#define CSR_MIMPID (0xF13) +#define CSR_MHARTID (0xF14) + +/* NON-STANDARD CRS address definition */ +#define CSR_SCOUNTEREN (0x106) +#define CSR_MCOUNTINHIBIT (0x320) +#define CSR_MILMB (0x7C0) +#define CSR_MDLMB (0x7C1) +#define CSR_MECC_CODE (0x7C2) +#define CSR_MNVEC (0x7C3) +#define CSR_MXSTATUS (0x7C4) +#define CSR_MPFT_CTL (0x7C5) +#define CSR_MHSP_CTL (0x7C6) +#define CSR_MSP_BOUND (0x7C7) +#define CSR_MSP_BASE (0x7C8) +#define CSR_MDCAUSE (0x7C9) +#define CSR_MCACHE_CTL (0x7CA) +#define CSR_MCCTLBEGINADDR (0x7CB) +#define CSR_MCCTLCOMMAND (0x7CC) +#define CSR_MCCTLDATA (0x7CD) +#define CSR_MCOUNTERWEN (0x7CE) +#define CSR_MCOUNTERINTEN (0x7CF) +#define CSR_MMISC_CTL (0x7D0) +#define CSR_MCOUNTERMASK_M (0x7D1) +#define CSR_MCOUNTERMASK_S (0x7D2) +#define CSR_MCOUNTERMASK_U (0x7D3) +#define CSR_MCOUNTEROVF (0x7D4) +#define CSR_MSLIDELEG (0x7D5) +#define CSR_MCLK_CTL (0x7DF) +#define CSR_DEXC2DBG (0x7E0) +#define CSR_DDCAUSE (0x7E1) +#define CSR_UITB (0x800) +#define CSR_UCODE (0x801) +#define CSR_UDCAUSE (0x809) +#define CSR_UCCTLBEGINADDR (0x80B) +#define CSR_UCCTLCOMMAND (0x80C) +#define CSR_SLIE (0x9C4) +#define CSR_SLIP (0x9C5) +#define CSR_SDCAUSE (0x9C9) +#define CSR_SCCTLDATA (0x9CD) +#define CSR_SCOUNTERINTEN (0x9CF) +#define CSR_SCOUNTERMASK_M (0x9D1) +#define CSR_SCOUNTERMASK_S (0x9D2) +#define CSR_SCOUNTERMASK_U (0x9D3) +#define CSR_SCOUNTEROVF (0x9D4) +#define CSR_SCOUNTINHIBIT (0x9E0) +#define CSR_SHPMEVENT3 (0x9E3) +#define CSR_SHPMEVENT4 (0x9E4) +#define CSR_SHPMEVENT5 (0x9E5) +#define CSR_SHPMEVENT6 (0x9E6) +#define CSR_MICM_CFG (0xFC0) +#define CSR_MDCM_CFG (0xFC1) +#define CSR_MMSC_CFG (0xFC2) +#define CSR_MMSC_CFG2 (0xFC3) + +/* STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: USTATUS */ +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_USTATUS_UPIE_MASK (0x10U) +#define CSR_USTATUS_UPIE_SHIFT (4U) +#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) +#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_USTATUS_UIE_MASK (0x1U) +#define CSR_USTATUS_UIE_SHIFT (0U) +#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) +#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) + +/* Bitfield definition for register: UIE */ +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UEIE_MASK (0x100U) +#define CSR_UIE_UEIE_SHIFT (8U) +#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) +#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UTIE_MASK (0x10U) +#define CSR_UIE_UTIE_SHIFT (4U) +#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) +#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_USIE_MASK (0x1U) +#define CSR_UIE_USIE_SHIFT (0U) +#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) +#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) + +/* Bitfield definition for register: UTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_UTVEC_BASE_31_2_SHIFT (2U) +#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) +#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: USCRATCH */ +/* + * USCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_USCRATCH_USCRATCH_SHIFT (0U) +#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) +#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) + +/* Bitfield definition for register: UEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_UEPC_EPC_SHIFT (1U) +#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) +#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) + +/* Bitfield definition for register: UCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) +#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 4:User timer interrupt + * 8:User external interrupt + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9-11:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32：Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) +#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: UTVAL */ +/* + * UTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) +#define CSR_UTVAL_UTVAL_SHIFT (0U) +#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) +#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) + +/* Bitfield definition for register: UIP */ +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UEIP_MASK (0x100U) +#define CSR_UIP_UEIP_SHIFT (8U) +#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) +#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UTIP_MASK (0x10U) +#define CSR_UIP_UTIP_SHIFT (4U) +#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) +#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_USIP_MASK (0x1U) +#define CSR_UIP_USIP_SHIFT (0U) +#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) +#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) + +/* Bitfield definition for register: SSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_SSTATUS_SD_MASK (0x80000000UL) +#define CSR_SSTATUS_SD_SHIFT (31U) +#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_SSTATUS_MXR_MASK (0x80000UL) +#define CSR_SSTATUS_MXR_SHIFT (19U) +#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) +#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_SSTATUS_SUM_MASK (0x40000UL) +#define CSR_SSTATUS_SUM_SHIFT (18U) +#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) +#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggeredwhen XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. + * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_XS_MASK (0x18000UL) +#define CSR_SSTATUS_XS_SHIFT (15U) +#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. + * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_FS_MASK (0x6000U) +#define CSR_SSTATUS_FS_SHIFT (13U) +#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) +#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_SSTATUS_SPP_MASK (0x100U) +#define CSR_SSTATUS_SPP_SHIFT (8U) +#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) +#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_SSTATUS_SPIE_MASK (0x20U) +#define CSR_SSTATUS_SPIE_SHIFT (5U) +#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) +#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_SSTATUS_UPIE_MASK (0x10U) +#define CSR_SSTATUS_UPIE_SHIFT (4U) +#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) +#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_SIE_MASK (0x2U) +#define CSR_SSTATUS_SIE_SHIFT (1U) +#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) +#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_UIE_MASK (0x1U) +#define CSR_SSTATUS_UIE_SHIFT (0U) +#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) +#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: SEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SPF_MASK (0x8000U) +#define CSR_SEDELEG_SPF_SHIFT (15U) +#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) +#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LPF_MASK (0x2000U) +#define CSR_SEDELEG_LPF_SHIFT (13U) +#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) +#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IPF_MASK (0x1000U) +#define CSR_SEDELEG_IPF_SHIFT (12U) +#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) +#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_UEC_MASK (0x100U) +#define CSR_SEDELEG_UEC_SHIFT (8U) +#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) +#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAF_MASK (0x80U) +#define CSR_SEDELEG_SAF_SHIFT (7U) +#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) +#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAM_MASK (0x40U) +#define CSR_SEDELEG_SAM_SHIFT (6U) +#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) +#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAF_MASK (0x20U) +#define CSR_SEDELEG_LAF_SHIFT (5U) +#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) +#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAM_MASK (0x10U) +#define CSR_SEDELEG_LAM_SHIFT (4U) +#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) +#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) + +/* + * B (RW) + * + * B indicates whether an exception triggered by breakpoint will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_B_MASK (0x8U) +#define CSR_SEDELEG_B_SHIFT (3U) +#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) +#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_II_MASK (0x4U) +#define CSR_SEDELEG_II_SHIFT (2U) +#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) +#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAF_MASK (0x2U) +#define CSR_SEDELEG_IAF_SHIFT (1U) +#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) +#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAM_MASK (0x1U) +#define CSR_SEDELEG_IAM_SHIFT (0U) +#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) +#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: SIDELEG */ +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UEI_MASK (0x100U) +#define CSR_SIDELEG_UEI_SHIFT (8U) +#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) +#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UTI_MASK (0x10U) +#define CSR_SIDELEG_UTI_SHIFT (4U) +#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) +#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_USI_MASK (0x1U) +#define CSR_SIDELEG_USI_SHIFT (0U) +#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) +#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) + +/* Bitfield definition for register: SIE */ +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SEIE_MASK (0x200U) +#define CSR_SIE_SEIE_SHIFT (9U) +#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) +#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UEIE_MASK (0x100U) +#define CSR_SIE_UEIE_SHIFT (8U) +#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) +#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_STIE_MASK (0x20U) +#define CSR_SIE_STIE_SHIFT (5U) +#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) +#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UTIE_MASK (0x10U) +#define CSR_SIE_UTIE_SHIFT (4U) +#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) +#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SSIE_MASK (0x2U) +#define CSR_SIE_SSIE_SHIFT (1U) +#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) +#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_USIE_MASK (0x1U) +#define CSR_SIE_USIE_SHIFT (0U) +#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) +#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) + +/* Bitfield definition for register: STVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_STVEC_BASE_31_2_SHIFT (2U) +#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) +#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: SSCRATCH */ +/* + * SSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) +#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) +#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) + +/* Bitfield definition for register: SEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_SEPC_EPC_SHIFT (1U) +#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) +#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) + +/* Bitfield definition for register: SCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) +#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 256+16:Slave port ECC error interrupt (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt(S-mode) + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:10:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) +#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: STVAL */ +/* + * STVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) +#define CSR_STVAL_STVAL_SHIFT (0U) +#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) +#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) + +/* Bitfield definition for register: SIP */ +/* + * SEIP (RO) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SEIP_MASK (0x200U) +#define CSR_SIP_SEIP_SHIFT (9U) +#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UEIP_MASK (0x100U) +#define CSR_SIP_UEIP_SHIFT (8U) +#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) +#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) + +/* + * STIP (RO) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_STIP_MASK (0x20U) +#define CSR_SIP_STIP_SHIFT (5U) +#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) + +/* + * UTIP (RO) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UTIP_MASK (0x10U) +#define CSR_SIP_UTIP_SHIFT (4U) +#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SSIP_MASK (0x2U) +#define CSR_SIP_SSIP_SHIFT (1U) +#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) +#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_USIP_MASK (0x1U) +#define CSR_SIP_USIP_SHIFT (0U) +#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) +#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) + +/* Bitfield definition for register: SATP */ +/* + * MODE (RW) + * + * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is + * not supported in the product, this CSR will be + * hardwired to 0. + * 0:No page translation + * 1:Page-based 32-bit virtual addressing + */ +#define CSR_SATP_MODE_MASK (0x80000000UL) +#define CSR_SATP_MODE_SHIFT (31U) +#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) +#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) + +/* + * ASID (RW) + * + * ASID holds the address space identifier. + */ +#define CSR_SATP_ASID_MASK (0x7FC00000UL) +#define CSR_SATP_ASID_SHIFT (22U) +#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) +#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) + +/* + * PPN (RW) + * + * PPN holds the physical page number of the root page table. + */ +#define CSR_SATP_PPN_MASK (0x3FFFFFUL) +#define CSR_SATP_PPN_SHIFT (0U) +#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) +#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) + +/* Bitfield definition for register: MSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_MSTATUS_SD_MASK (0x80000000UL) +#define CSR_MSTATUS_SD_SHIFT (31U) +#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) + +/* + * TSR (RW) + * + * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TSR_MASK (0x400000UL) +#define CSR_MSTATUS_TSR_SHIFT (22U) +#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) +#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) + +/* + * TW (RW) + * + * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TW_MASK (0x200000UL) +#define CSR_MSTATUS_TW_SHIFT (21U) +#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) +#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) + +/* + * TVM (RW) + * + * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. + * 0:Normal execution + * 1:Raising exceptions + */ +#define CSR_MSTATUS_TVM_MASK (0x100000UL) +#define CSR_MSTATUS_TVM_SHIFT (20U) +#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) +#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_MSTATUS_MXR_MASK (0x80000UL) +#define CSR_MSTATUS_MXR_SHIFT (19U) +#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) +#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_MSTATUS_SUM_MASK (0x40000UL) +#define CSR_MSTATUS_SUM_SHIFT (18U) +#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) +#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) + +/* + * MPRV (RW) + * + * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. + */ +#define CSR_MSTATUS_MPRV_MASK (0x20000UL) +#define CSR_MSTATUS_MPRV_SHIFT (17U) +#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) +#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggered when XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_XS_MASK (0x18000UL) +#define CSR_MSTATUS_XS_SHIFT (15U) +#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state + * managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_FS_MASK (0x6000U) +#define CSR_MSTATUS_FS_SHIFT (13U) +#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) +#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) + +/* + * MPP (RW) + * + * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. + */ +#define CSR_MSTATUS_MPP_MASK (0x1800U) +#define CSR_MSTATUS_MPP_SHIFT (11U) +#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) +#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_MSTATUS_SPP_MASK (0x100U) +#define CSR_MSTATUS_SPP_SHIFT (8U) +#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) +#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) + +/* + * MPIE (RW) + * + * MPIE holds the value of the MIE bit prior to a trap. + */ +#define CSR_MSTATUS_MPIE_MASK (0x80U) +#define CSR_MSTATUS_MPIE_SHIFT (7U) +#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) +#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_MSTATUS_SPIE_MASK (0x20U) +#define CSR_MSTATUS_SPIE_SHIFT (5U) +#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) +#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_MSTATUS_UPIE_MASK (0x10U) +#define CSR_MSTATUS_UPIE_SHIFT (4U) +#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) +#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) + +/* + * MIE (RW) + * + * M mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_MIE_MASK (0x8U) +#define CSR_MSTATUS_MIE_SHIFT (3U) +#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) +#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_SIE_MASK (0x2U) +#define CSR_MSTATUS_SIE_SHIFT (1U) +#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) +#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_UIE_MASK (0x1U) +#define CSR_MSTATUS_UIE_SHIFT (0U) +#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) +#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: MISA */ +/* + * BASE (RO) + * + * The general-purpose register width of the native base integer ISA. + * 0:Reserved + * 1:32 + * 2:64 + * 3:128 + */ +#define CSR_MISA_BASE_MASK (0xC0000000UL) +#define CSR_MISA_BASE_SHIFT (30U) +#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) + +/* + * Z (RO) + * + * Reserved + */ +#define CSR_MISA_Z_MASK (0x2000000UL) +#define CSR_MISA_Z_SHIFT (25U) +#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) + +/* + * Y (RO) + * + * Reserved + */ +#define CSR_MISA_Y_MASK (0x1000000UL) +#define CSR_MISA_Y_SHIFT (24U) +#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) + +/* + * X (RO) + * + * Non-standard extensions present + */ +#define CSR_MISA_X_MASK (0x800000UL) +#define CSR_MISA_X_SHIFT (23U) +#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) + +/* + * W (RO) + * + * Reserved + */ +#define CSR_MISA_W_MASK (0x400000UL) +#define CSR_MISA_W_SHIFT (22U) +#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) + +/* + * V (RO) + * + * Tentatively reserved for Vector extension + */ +#define CSR_MISA_V_MASK (0x200000UL) +#define CSR_MISA_V_SHIFT (21U) +#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) + +/* + * U (RO) + * + * User mode implemented + * 0:Machine + * 1:Machine + User / Machine + Supervisor + User + */ +#define CSR_MISA_U_MASK (0x100000UL) +#define CSR_MISA_U_SHIFT (20U) +#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) + +/* + * T (RO) + * + * Tentatively reserved for Transactional Memory extension + */ +#define CSR_MISA_T_MASK (0x80000UL) +#define CSR_MISA_T_SHIFT (19U) +#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) + +/* + * S (RO) + * + * Supervisor mode implemented + * 0:Machine / Machine + User + * 1:Machine + Supervisor + User + */ +#define CSR_MISA_S_MASK (0x40000UL) +#define CSR_MISA_S_SHIFT (18U) +#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) + +/* + * R (RO) + * + * Reserved + */ +#define CSR_MISA_R_MASK (0x20000UL) +#define CSR_MISA_R_SHIFT (17U) +#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) + +/* + * Q (RO) + * + * Quad-precision floating-point extension + */ +#define CSR_MISA_Q_MASK (0x10000UL) +#define CSR_MISA_Q_SHIFT (16U) +#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) + +/* + * P (RO) + * + * Tentatively reserved for Packed-SIMD extension + */ +#define CSR_MISA_P_MASK (0x8000U) +#define CSR_MISA_P_SHIFT (15U) +#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) + +/* + * O (RO) + * + * Reserved + */ +#define CSR_MISA_O_MASK (0x4000U) +#define CSR_MISA_O_SHIFT (14U) +#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) + +/* + * N (RO) + * + * User-level interrupts supported + * 0:no + * 1:yes + */ +#define CSR_MISA_N_MASK (0x2000U) +#define CSR_MISA_N_SHIFT (13U) +#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) + +/* + * M (RO) + * + * Integer Multiply/Divide extension + */ +#define CSR_MISA_M_MASK (0x1000U) +#define CSR_MISA_M_SHIFT (12U) +#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) + +/* + * L (RO) + * + * Tentatively reserved for Decimal Floating-Point extension + */ +#define CSR_MISA_L_MASK (0x800U) +#define CSR_MISA_L_SHIFT (11U) +#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) + +/* + * K (RO) + * + * Reserved + */ +#define CSR_MISA_K_MASK (0x400U) +#define CSR_MISA_K_SHIFT (10U) +#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) + +/* + * J (RO) + * + * Tentatively reserved for Dynamically Translated Languages extension + */ +#define CSR_MISA_J_MASK (0x200U) +#define CSR_MISA_J_SHIFT (9U) +#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) + +/* + * I (RO) + * + * RV32I/64I/128I base ISA + */ +#define CSR_MISA_I_MASK (0x100U) +#define CSR_MISA_I_SHIFT (8U) +#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) + +/* + * H (RO) + * + * Reserved + */ +#define CSR_MISA_H_MASK (0x80U) +#define CSR_MISA_H_SHIFT (7U) +#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) + +/* + * G (RO) + * + * Additional standard extensions present + */ +#define CSR_MISA_G_MASK (0x40U) +#define CSR_MISA_G_SHIFT (6U) +#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) + +/* + * F (RO) + * + * Single-precision floating-point extension + * 0:none + * 1:double+single precision / single precision + */ +#define CSR_MISA_F_MASK (0x20U) +#define CSR_MISA_F_SHIFT (5U) +#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) + +/* + * E (RO) + * + * RV32E base ISA + */ +#define CSR_MISA_E_MASK (0x10U) +#define CSR_MISA_E_SHIFT (4U) +#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) + +/* + * D (RO) + * + * Double-precision floating-point extension + * 0:single precision / none + * 1:double+single precision + */ +#define CSR_MISA_D_MASK (0x8U) +#define CSR_MISA_D_SHIFT (3U) +#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) + +/* + * C (RO) + * + * Compressed extension + */ +#define CSR_MISA_C_MASK (0x4U) +#define CSR_MISA_C_SHIFT (2U) +#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) + +/* + * B (RO) + * + * Tentatively reserved for Bit operations extension + */ +#define CSR_MISA_B_MASK (0x2U) +#define CSR_MISA_B_SHIFT (1U) +#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) + +/* + * A (RO) + * + * Atomic extension + * 0:no + * 1:yes + */ +#define CSR_MISA_A_MASK (0x1U) +#define CSR_MISA_A_SHIFT (0U) +#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) + +/* Bitfield definition for register: MEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SPF_MASK (0x8000U) +#define CSR_MEDELEG_SPF_SHIFT (15U) +#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) +#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LPF_MASK (0x2000U) +#define CSR_MEDELEG_LPF_SHIFT (13U) +#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) +#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IPF_MASK (0x1000U) +#define CSR_MEDELEG_IPF_SHIFT (12U) +#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) +#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) + +/* + * SEC (RW) + * + * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SEC_MASK (0x200U) +#define CSR_MEDELEG_SEC_SHIFT (9U) +#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) +#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_UEC_MASK (0x100U) +#define CSR_MEDELEG_UEC_SHIFT (8U) +#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) +#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAF_MASK (0x80U) +#define CSR_MEDELEG_SAF_SHIFT (7U) +#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) +#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAM_MASK (0x40U) +#define CSR_MEDELEG_SAM_SHIFT (6U) +#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) +#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAF_MASK (0x20U) +#define CSR_MEDELEG_LAF_SHIFT (5U) +#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) +#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAM_MASK (0x10U) +#define CSR_MEDELEG_LAM_SHIFT (4U) +#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) +#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_II_MASK (0x4U) +#define CSR_MEDELEG_II_SHIFT (2U) +#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) +#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAF_MASK (0x2U) +#define CSR_MEDELEG_IAF_SHIFT (1U) +#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) +#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAM_MASK (0x1U) +#define CSR_MEDELEG_IAM_SHIFT (0U) +#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) +#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: MIDELEG */ +/* + * SEI (RW) + * + * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SEI_MASK (0x200U) +#define CSR_MIDELEG_SEI_SHIFT (9U) +#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) +#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) + +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UEI_MASK (0x100U) +#define CSR_MIDELEG_UEI_SHIFT (8U) +#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) +#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) + +/* + * STI (RW) + * + * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_STI_MASK (0x20U) +#define CSR_MIDELEG_STI_SHIFT (5U) +#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) +#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UTI_MASK (0x10U) +#define CSR_MIDELEG_UTI_SHIFT (4U) +#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) +#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) + +/* + * SSI (RW) + * + * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SSI_MASK (0x2U) +#define CSR_MIDELEG_SSI_SHIFT (1U) +#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) +#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_USI_MASK (0x1U) +#define CSR_MIDELEG_USI_SHIFT (0U) +#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) +#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) + +/* Bitfield definition for register: MIE */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_PMOVI_MASK (0x40000UL) +#define CSR_MIE_PMOVI_SHIFT (18U) +#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) +#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_BWEI_MASK (0x20000UL) +#define CSR_MIE_BWEI_SHIFT (17U) +#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) +#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_IMECCI_MASK (0x10000UL) +#define CSR_MIE_IMECCI_SHIFT (16U) +#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) +#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) + +/* + * MEIE (RW) + * + * M mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MEIE_MASK (0x800U) +#define CSR_MIE_MEIE_SHIFT (11U) +#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) +#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) + +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SEIE_MASK (0x200U) +#define CSR_MIE_SEIE_SHIFT (9U) +#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) +#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UEIE_MASK (0x100U) +#define CSR_MIE_UEIE_SHIFT (8U) +#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) +#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) + +/* + * MTIE (RW) + * + * M mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MTIE_MASK (0x80U) +#define CSR_MIE_MTIE_SHIFT (7U) +#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) +#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_STIE_MASK (0x20U) +#define CSR_MIE_STIE_SHIFT (5U) +#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) +#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UTIE_MASK (0x10U) +#define CSR_MIE_UTIE_SHIFT (4U) +#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) +#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) + +/* + * MSIE (RW) + * + * M mode software interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MSIE_MASK (0x8U) +#define CSR_MIE_MSIE_SHIFT (3U) +#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) +#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SSIE_MASK (0x2U) +#define CSR_MIE_SSIE_SHIFT (1U) +#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) +#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_USIE_MASK (0x1U) +#define CSR_MIE_USIE_SHIFT (0U) +#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) +#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) + +/* Bitfield definition for register: MTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode + */ +#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_MTVEC_BASE_31_2_SHIFT (2U) +#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) +#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: MCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) +#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) +#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) +#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) +#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_IR_MASK (0x4U) +#define CSR_MCOUNTEREN_IR_SHIFT (2U) +#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) +#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_TM_MASK (0x2U) +#define CSR_MCOUNTEREN_TM_SHIFT (1U) +#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) +#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_CY_MASK (0x1U) +#define CSR_MCOUNTEREN_CY_SHIFT (0U) +#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) +#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT3_SEL_SHIFT (4U) +#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) +#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) +#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT4_SEL_SHIFT (4U) +#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) +#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) +#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT5_SEL_SHIFT (4U) +#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) +#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) +#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT6_SEL_SHIFT (4U) +#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) +#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) +#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MSCRATCH */ +/* + * MSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) +#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) +#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) + +/* Bitfield definition for register: MEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_MEPC_EPC_SHIFT (1U) +#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) +#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) + +/* Bitfield definition for register: MCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt + */ +#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) +#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception code + * When interrupt is 1, the value means: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 3:Machine software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 7:Machine timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 11:Machine external interrupt + * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) + * 17:Bus read/write transaction error interrupt (M-mode) + * 18:Performance monitor overflow interrupt (M-mode) + * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt (S-mode) + * When interrupt bit is 0, the value means: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:Environment call from M-mode + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) +#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) +#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: MTVAL */ +/* + * MTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) +#define CSR_MTVAL_MTVAL_SHIFT (0U) +#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) +#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) + +/* Bitfield definition for register: MIP */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_PMOVI_MASK (0x40000UL) +#define CSR_MIP_PMOVI_SHIFT (18U) +#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) +#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_BWEI_MASK (0x20000UL) +#define CSR_MIP_BWEI_SHIFT (17U) +#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) +#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_IMECCI_MASK (0x10000UL) +#define CSR_MIP_IMECCI_SHIFT (16U) +#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) +#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) + +/* + * MEIP (RW) + * + * M mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MEIP_MASK (0x800U) +#define CSR_MIP_MEIP_SHIFT (11U) +#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) +#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) + +/* + * SEIP (RW) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SEIP_MASK (0x200U) +#define CSR_MIP_SEIP_SHIFT (9U) +#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) +#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UEIP_MASK (0x100U) +#define CSR_MIP_UEIP_SHIFT (8U) +#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) +#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) + +/* + * MTIP (RW) + * + * M mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MTIP_MASK (0x80U) +#define CSR_MIP_MTIP_SHIFT (7U) +#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) +#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) + +/* + * STIP (RW) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_STIP_MASK (0x20U) +#define CSR_MIP_STIP_SHIFT (5U) +#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) +#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UTIP_MASK (0x10U) +#define CSR_MIP_UTIP_SHIFT (4U) +#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) +#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) + +/* + * MSIP (RW) + * + * M mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MSIP_MASK (0x8U) +#define CSR_MIP_MSIP_SHIFT (3U) +#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) +#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SSIP_MASK (0x2U) +#define CSR_MIP_SSIP_SHIFT (1U) +#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) +#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_USIP_MASK (0x1U) +#define CSR_MIP_USIP_SHIFT (0U) +#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) +#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) + +/* Bitfield definition for register: PMPCFG0 */ +/* + * PMP3CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) +#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) +#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) + +/* + * PMP2CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) +#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) +#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) + +/* + * PMP1CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) +#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) +#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) +#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) + +/* + * PMP0CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) +#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) +#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) +#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG1 */ +/* + * PMP7CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) +#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) +#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) + +/* + * PMP6CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) +#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) +#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) + +/* + * PMP5CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) +#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) +#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) +#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) + +/* + * PMP4CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) +#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) +#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) +#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG2 */ +/* + * PMP11CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) +#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) +#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) + +/* + * PMP10CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) +#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) +#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) + +/* + * PMP9CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) +#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) +#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) +#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) + +/* + * PMP8CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) +#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) +#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) +#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG3 */ +/* + * PMP15CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) +#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) +#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) + +/* + * PMP14CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) +#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) +#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) + +/* + * PMP13CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) +#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) +#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) +#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) + +/* + * PMP12CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) +#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) +#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) +#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaa0 8 + * aaaa. . . aa01 16 + * aaaa. . . a011 32 + * . . . . . . + * aa01. . . 1111 2^{XLEN} + * a011. . . 1111 2^{XLEN+1} + * 0111. . . 1111 2^{XLEN+2} + * 1111. . . 1111 2^{XLEN+3*1} + */ +#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) +#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) +#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) +#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) +#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) +#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) +#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) +#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) +#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) +#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) +#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) +#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) +#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) +#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) +#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) +#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) +#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register: TSELECT */ +/* + * TRIGGER_INDEX (RW) + * + * This register determines which trigger is accessible through other trigger registers. + */ +#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) +#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) +#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) +#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) + +/* Bitfield definition for register: TDATA1 */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + * 3:The selected trigger is an instruction count trigger + * 4:The selected trigger is an interrupt trigger. + * 5:The selected trigger is an exception trigger. + */ +#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) +#define CSR_TDATA1_TYPE_SHIFT (28U) +#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) +#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_TDATA1_DMODE_MASK (0x8000000UL) +#define CSR_TDATA1_DMODE_SHIFT (27U) +#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) +#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) + +/* + * DATA (RW) + * + * Trigger-specific data + */ +#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) +#define CSR_TDATA1_DATA_SHIFT (0U) +#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) +#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) + +/* Bitfield definition for register: MCONTROL */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + */ +#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) +#define CSR_MCONTROL_TYPE_SHIFT (28U) +#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) +#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) +#define CSR_MCONTROL_DMODE_SHIFT (27U) +#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) +#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) + +/* + * MASKMAX (RO) + * + * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. + */ +#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) +#define CSR_MCONTROL_MASKMAX_SHIFT (21U) +#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_MCONTROL_ACTION_MASK (0xF000U) +#define CSR_MCONTROL_ACTION_SHIFT (12U) +#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) +#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) + +/* + * CHAIN (RW) + * + * Setting this field to enable trigger chain. + * 0:When this trigger matches, the configured action is taken. + * 1:While this trigger does not match, it prevents the trigger with the next index from matching. + * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). + * If Number of Triggers is 4, this field is hardwired + * to 0 on trigger 3 (tselect = 3). + * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). + */ +#define CSR_MCONTROL_CHAIN_MASK (0x800U) +#define CSR_MCONTROL_CHAIN_SHIFT (11U) +#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) +#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) + +/* + * MATCH (RW) + * + * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. + * 2:Matches when the value is greater than (unsigned) or equal to tdata2. + * 3:Matches when the value is less than (unsigned) tdata2 + */ +#define CSR_MCONTROL_MATCH_MASK (0x780U) +#define CSR_MCONTROL_MATCH_SHIFT (7U) +#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) +#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_MCONTROL_M_MASK (0x40U) +#define CSR_MCONTROL_M_SHIFT (6U) +#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) +#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_MCONTROL_S_MASK (0x10U) +#define CSR_MCONTROL_S_SHIFT (4U) +#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) +#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_MCONTROL_U_MASK (0x8U) +#define CSR_MCONTROL_U_SHIFT (3U) +#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) +#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) + +/* + * EXECUTE (RW) + * + * Setting this field to enable this trigger to compare virtual address of an instruction. + */ +#define CSR_MCONTROL_EXECUTE_MASK (0x4U) +#define CSR_MCONTROL_EXECUTE_SHIFT (2U) +#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) +#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) + +/* + * STORE (RW) + * + * Setting this field to enable this trigger to compare virtual address of a store. + */ +#define CSR_MCONTROL_STORE_MASK (0x2U) +#define CSR_MCONTROL_STORE_SHIFT (1U) +#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) +#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) + +/* + * LOAD (RW) + * + * Setting this field to enable this trigger to compare virtual address of a load. + */ +#define CSR_MCONTROL_LOAD_MASK (0x1U) +#define CSR_MCONTROL_LOAD_SHIFT (0U) +#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) +#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) + +/* Bitfield definition for register: ICOUNT */ +/* + * TYPE (RW) + * + * The selected trigger is an instruction count trigger. + */ +#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) +#define CSR_ICOUNT_TYPE_SHIFT (28U) +#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) +#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) +#define CSR_ICOUNT_DMODE_SHIFT (27U) +#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) +#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) + +/* + * COUNT (RO) + * + * This field is hardwired to 1 for single-stepping support + */ +#define CSR_ICOUNT_COUNT_MASK (0x400U) +#define CSR_ICOUNT_COUNT_SHIFT (10U) +#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ICOUNT_M_MASK (0x200U) +#define CSR_ICOUNT_M_SHIFT (9U) +#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) +#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ICOUNT_S_MASK (0x80U) +#define CSR_ICOUNT_S_SHIFT (7U) +#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) +#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ICOUNT_U_MASK (0x40U) +#define CSR_ICOUNT_U_SHIFT (6U) +#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) +#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ICOUNT_ACTION_MASK (0x3FU) +#define CSR_ICOUNT_ACTION_SHIFT (0U) +#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) +#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) + +/* Bitfield definition for register: ITRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an interrupt trigger. + */ +#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ITRIGGER_TYPE_SHIFT (28U) +#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) +#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ITRIGGER_DMODE_SHIFT (27U) +#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) +#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ITRIGGER_M_MASK (0x200U) +#define CSR_ITRIGGER_M_SHIFT (9U) +#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) +#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ITRIGGER_S_MASK (0x80U) +#define CSR_ITRIGGER_S_SHIFT (7U) +#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) +#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ITRIGGER_U_MASK (0x40U) +#define CSR_ITRIGGER_U_SHIFT (6U) +#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) +#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception. + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ITRIGGER_ACTION_MASK (0x3FU) +#define CSR_ITRIGGER_ACTION_SHIFT (0U) +#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) +#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: ETRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an exception trigger. + */ +#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ETRIGGER_TYPE_SHIFT (28U) +#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) +#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ETRIGGER_DMODE_SHIFT (27U) +#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) +#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) + +/* + * NMI (RW) + * + * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. + */ +#define CSR_ETRIGGER_NMI_MASK (0x400U) +#define CSR_ETRIGGER_NMI_SHIFT (10U) +#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) +#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ETRIGGER_M_MASK (0x200U) +#define CSR_ETRIGGER_M_SHIFT (9U) +#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) +#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ETRIGGER_S_MASK (0x80U) +#define CSR_ETRIGGER_S_SHIFT (7U) +#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) +#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ETRIGGER_U_MASK (0x40U) +#define CSR_ETRIGGER_U_SHIFT (6U) +#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) +#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ETRIGGER_ACTION_MASK (0x3FU) +#define CSR_ETRIGGER_ACTION_SHIFT (0U) +#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) +#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: TDATA2 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA2_DATA_SHIFT (0U) +#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) +#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) + +/* Bitfield definition for register: TDATA3 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA3_DATA_SHIFT (0U) +#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) +#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) + +/* Bitfield definition for register: TEXTRA */ +/* + * MVALUE (RW) + * + * Data used together with MSELECT. + */ +#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) +#define CSR_TEXTRA_MVALUE_SHIFT (26U) +#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) +#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) + +/* + * MSELECT (RW) + * + * 0:Ignore MVALUE. + * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. + */ +#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) +#define CSR_TEXTRA_MSELECT_SHIFT (25U) +#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) +#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) + +/* + * SVALUE (RW) + * + * Data used together with SSELECT. + */ +#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) +#define CSR_TEXTRA_SVALUE_SHIFT (2U) +#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) +#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) + +/* + * SSELECT (RW) + * + * 0:Ignore MVALUE + * 1:This trigger will only match if the lower bits of scontext equal SVALUE + * 2This trigger will only match if satp.ASID equals SVALUE. + */ +#define CSR_TEXTRA_SSELECT_MASK (0x3U) +#define CSR_TEXTRA_SSELECT_SHIFT (0U) +#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) +#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) + +/* Bitfield definition for register: TINFO */ +/* + * INFO (RO) + * + * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that + * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. + * 0:When this bit is set, there is no trigger at this tselect + * 1:Reserved and hardwired to 0. + * 2：When this bit is set, the selected trigger supports type of address/data match trigger + * 3:When this bit is set, the selected trigger supports type of instruction count trigger. + * 4:When this bit is set, the selected trigger supports type of interrupt trigger + * 5:When this bit is set, the selected trigger supports type of exception trigger + * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. + * Others:Reserved for future use. + */ +#define CSR_TINFO_INFO_MASK (0xFFFFU) +#define CSR_TINFO_INFO_SHIFT (0U) +#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) + +/* Bitfield definition for register: TCONTROL */ +/* + * MPTE (RW) + * + * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. + */ +#define CSR_TCONTROL_MPTE_MASK (0x80U) +#define CSR_TCONTROL_MPTE_SHIFT (7U) +#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) +#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) + +/* + * MTE (RW) + * + * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. + * 0:Triggers do not match/fire while the hart is in M-mode. + * 1:Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_MASK (0x8U) +#define CSR_TCONTROL_MTE_SHIFT (3U) +#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) +#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) + +/* Bitfield definition for register: MCONTEXT */ +/* + * MCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) +#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) +#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) +#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) + +/* Bitfield definition for register: SCONTEXT */ +/* + * SCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) +#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) +#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) +#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) + +/* Bitfield definition for register: DCSR */ +/* + * XDEBUGVER (RO) + * + * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 + */ +#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) +#define CSR_DCSR_XDEBUGVER_SHIFT (28U) +#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) + +/* + * EBREAKM (RW) + * + * This bit controls the behavior of EBREAK instructions in Machine Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKM_MASK (0x8000U) +#define CSR_DCSR_EBREAKM_SHIFT (15U) +#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) +#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) + +/* + * EBREAKS (RW) + * + * This bit controls the behavior of EBREAK instructions in Supervisor Mode. + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKS_MASK (0x2000U) +#define CSR_DCSR_EBREAKS_SHIFT (13U) +#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) +#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) + +/* + * EBREAKU (RW) + * + * This bit controls the behavior of EBREAK instructions in User/Application Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKU_MASK (0x1000U) +#define CSR_DCSR_EBREAKU_SHIFT (12U) +#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) +#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) + +/* + * STEPIE (RW) + * + * This bit controls whether interrupts are enabled during single stepping + * 0:Disable interrupts during single stepping + * 1:Allow interrupts in single stepping + */ +#define CSR_DCSR_STEPIE_MASK (0x800U) +#define CSR_DCSR_STEPIE_SHIFT (11U) +#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) +#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) + +/* + * STOPCOUNT (RW) + * + * This bit controls whether performance counters are stopped in Debug Mode. + * 0:Do not stop counters in Debug Mode + * 1:Stop counters in Debug Mode + */ +#define CSR_DCSR_STOPCOUNT_MASK (0x400U) +#define CSR_DCSR_STOPCOUNT_SHIFT (10U) +#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) +#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) + +/* + * STOPTIME (RW) + * + * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. + * 0:Do not stop timers in Debug Mode + * 1:Stop timers in Debug Mode + */ +#define CSR_DCSR_STOPTIME_MASK (0x200U) +#define CSR_DCSR_STOPTIME_SHIFT (9U) +#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) +#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) + +/* + * CAUSE (RO) + * + * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger + * 0:Reserved + * 1:EBREAK + * 2:Trigger module + * 3:Halt request + * 4:Single step + * 5:Halt-on-reset + * 6-7:Reserved + */ +#define CSR_DCSR_CAUSE_MASK (0x1C0U) +#define CSR_DCSR_CAUSE_SHIFT (6U) +#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) + +/* + * MPRVEN (RW) + * + * This bit controls whether mstatus.MPRV takes effect in Debug Mode. + * 0:MPRV in mstatus is ignored in Debug Mode. + * 1:MPRV in mstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_MASK (0x10U) +#define CSR_DCSR_MPRVEN_SHIFT (4U) +#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) +#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) + +/* + * NMIP (RO) + * + * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. + */ +#define CSR_DCSR_NMIP_MASK (0x8U) +#define CSR_DCSR_NMIP_SHIFT (3U) +#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) + +/* + * STEP (RW) + * + * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. + * 0:Single Step Mode is off + * 1:Single Step Mode is on + */ +#define CSR_DCSR_STEP_MASK (0x4U) +#define CSR_DCSR_STEP_SHIFT (2U) +#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) +#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) + +/* + * PRV (RW) + * + * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. + * 0:User/Application + * 1:Supervisor + * 2:Reserved + * 3:Machine + */ +#define CSR_DCSR_PRV_MASK (0x3U) +#define CSR_DCSR_PRV_SHIFT (0U) +#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) +#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) + +/* Bitfield definition for register: DPC */ +/* + * DPC (RW) + * + * Debug Program Counter. Bit 0 is hardwired to 0. + */ +#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) +#define CSR_DPC_DPC_SHIFT (0U) +#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) +#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) + +/* Bitfield definition for register: DSCRATCH0 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) + +/* Bitfield definition for register: DSCRATCH1 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) + +/* Bitfield definition for register: MCYCLE */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLE_COUNTER_SHIFT (0U) +#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) +#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRET */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRET_COUNTER_SHIFT (0U) +#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) +#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) +#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) +#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) +#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) +#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) + +/* Bitfield definition for register: MCYCLEH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLEH_COUNTER_SHIFT (0U) +#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) +#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRETH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRETH_COUNTER_SHIFT (0U) +#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) +#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) +#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) +#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) +#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) +#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) + +/* Bitfield definition for register: PMACFG0 */ +/* + * PMA3CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) +#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) +#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) +#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) + +/* + * PMA2CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) +#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) +#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) +#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) + +/* + * PMA1CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) +#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) +#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) +#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) + +/* + * PMA0CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) +#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) +#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) +#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) + +/* Bitfield definition for register: PMACFG1 */ +/* + * PMA7CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) +#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) +#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) +#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) + +/* + * PMA6CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) +#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) +#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) +#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) + +/* + * PMA5CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) +#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) +#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) +#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) + +/* + * PMA4CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) +#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) +#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) +#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) + +/* Bitfield definition for register: PMACFG2 */ +/* + * PMA11CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) +#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) +#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) +#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) + +/* + * PMA10CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) +#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) +#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) +#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) + +/* + * PMA9CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) +#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) +#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) +#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) + +/* + * PMA8CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) +#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) +#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) +#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) + +/* Bitfield definition for register: PMACFG3 */ +/* + * PMA15CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) +#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) +#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) +#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) + +/* + * PMA14CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) +#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) +#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) +#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) + +/* + * PMA13CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) +#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) +#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) +#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) + +/* + * PMA12CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) +#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) +#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) +#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaaaaaaaaaa Reserved + * . . . . . . + * aaaa. . . aa011111111 Reserved + * aaaa. . . a0111111111 2^{12} + * aaaa. . . 01111111111 2^{13} + * . . . . . . + * aa01. . . 11111111111 2^{XLEN} + * a011. . . 11111111111 2^{XLEN+1} + * 0111. . . 11111111111 2^{XLEN+2} + * 1111. . . 11111111111 Reserved + */ +#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) +#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) +#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) +#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) +#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) +#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) +#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) +#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) +#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) +#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) +#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) +#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) +#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) +#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) +#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) +#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) +#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register: CYCLE */ +/* + * CYCLE (RW) + * + * Cycle Counter + */ +#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) +#define CSR_CYCLE_CYCLE_SHIFT (0U) +#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) +#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) + +/* Bitfield definition for register: CYCLEH */ +/* + * CYCLEH (RW) + * + * Cycle Counter Higher 32-bit + */ +#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) +#define CSR_CYCLEH_CYCLEH_SHIFT (0U) +#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) +#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) + +/* Bitfield definition for register: MVENDORID */ +/* + * MVENDORID (RO) + * + * The manufacturer ID + */ +#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) +#define CSR_MVENDORID_MVENDORID_SHIFT (0U) +#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) + +/* Bitfield definition for register: MARCHID */ +/* + * CPU_ID (RO) + * + * CPU ID + */ +#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) +#define CSR_MARCHID_CPU_ID_SHIFT (0U) +#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) + +/* Bitfield definition for register: MIMPID */ +/* + * MAJOR (RO) + * + * Revision major + */ +#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) +#define CSR_MIMPID_MAJOR_SHIFT (8U) +#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) + +/* + * MINOR (RO) + * + * Revision minor + */ +#define CSR_MIMPID_MINOR_MASK (0xF0U) +#define CSR_MIMPID_MINOR_SHIFT (4U) +#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) + +/* + * EXTENSION (RO) + * + * Revision extension + */ +#define CSR_MIMPID_EXTENSION_MASK (0xFU) +#define CSR_MIMPID_EXTENSION_SHIFT (0U) +#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) + +/* Bitfield definition for register: MHARTID */ +/* + * MHARTID (RO) + * + * Hart ID + */ +#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) +#define CSR_MHARTID_MHARTID_SHIFT (0U) +#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) + +/* NON-STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: SCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) +#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) +#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) +#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) +#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_IR_MASK (0x4U) +#define CSR_SCOUNTEREN_IR_SHIFT (2U) +#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) +#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_CY_MASK (0x1U) +#define CSR_SCOUNTEREN_CY_SHIFT (0U) +#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) +#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) +#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) +#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) +#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) +#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) +#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) +#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) +#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: MILMB */ +/* + * IBPA (RO) + * + * The base physical address of ILM. It has to be an integer multiple of the ILM size + */ +#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) +#define CSR_MILMB_IBPA_SHIFT (10U) +#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MILMB_RWECC_MASK (0x8U) +#define CSR_MILMB_RWECC_SHIFT (3U) +#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) +#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MILMB_ECCEN_MASK (0x6U) +#define CSR_MILMB_ECCEN_SHIFT (1U) +#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) +#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) + +/* + * IEN (RO) + * + * ILM enable control: + * 0:ILM is disabled + * 1:ILM is enabled + */ +#define CSR_MILMB_IEN_MASK (0x1U) +#define CSR_MILMB_IEN_SHIFT (0U) +#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) + +/* Bitfield definition for register: MDLMB */ +/* + * DBPA (RO) + * + * The base physical address of DLM. It has to be an integer multiple of the DLM size + */ +#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) +#define CSR_MDLMB_DBPA_SHIFT (10U) +#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MDLMB_RWECC_MASK (0x8U) +#define CSR_MDLMB_RWECC_SHIFT (3U) +#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) +#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MDLMB_ECCEN_MASK (0x6U) +#define CSR_MDLMB_ECCEN_SHIFT (1U) +#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) +#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) + +/* + * DEN (RO) + * + * DLM enable control: + * 0:DLM is disabled + * 1:DLM is enabled + */ +#define CSR_MDLMB_DEN_MASK (0x1U) +#define CSR_MDLMB_DEN_SHIFT (0U) +#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) + +/* Bitfield definition for register: MECC_CODE */ +/* + * INSN (RO) + * + * Indicates if the parity/ECC error is caused by instruction fetch or data access. + * 0:Data access + * 1:Instruction fetch + */ +#define CSR_MECC_CODE_INSN_MASK (0x400000UL) +#define CSR_MECC_CODE_INSN_SHIFT (22U) +#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) + +/* + * RAMID (RO) + * + * The ID of RAM that caused parity/ECC errors. + * This bit is updated on parity/ECC error exceptions. + * 0–1:Reserved + * 2:Tag RAM of I-Cache + * 3:Data RAM of I-Cache + * 4:Tag RAM of D-Cache + * 5:Data RAM of D-Cache + * 6:Tag RAM of TLB + * 7:Data RAM of TLB + * 8:ILM + * 9:DLM + * 10–15:Reserved + */ +#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) +#define CSR_MECC_CODE_RAMID_SHIFT (18U) +#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) + +/* + * P (RO) + * + * Precise error. This bit is updated on parity/ECC error exceptions. + * 0:Imprecise error + * 1:Precise error + */ +#define CSR_MECC_CODE_P_MASK (0x20000UL) +#define CSR_MECC_CODE_P_SHIFT (17U) +#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) + +/* + * C (RO) + * + * Correctable error. This bit is updated on parity/ECC error exceptions. + * 0:Uncorrectable error + * 1:Correctable error + */ +#define CSR_MECC_CODE_C_MASK (0x10000UL) +#define CSR_MECC_CODE_C_SHIFT (16U) +#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) + +/* + * CODE (RW) + * + * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). + */ +#define CSR_MECC_CODE_CODE_MASK (0x7FU) +#define CSR_MECC_CODE_CODE_SHIFT (0U) +#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) +#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) + +/* Bitfield definition for register: MNVEC */ +/* + * MNVEC (RO) + * + * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. + */ +#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) +#define CSR_MNVEC_MNVEC_SHIFT (0U) +#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) + +/* Bitfield definition for register: MXSTATUS */ +/* + * PDME (RW) + * + * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. + */ +#define CSR_MXSTATUS_PDME_MASK (0x20U) +#define CSR_MXSTATUS_PDME_SHIFT (5U) +#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) +#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) + +/* + * DME (RW) + * + * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. + */ +#define CSR_MXSTATUS_DME_MASK (0x10U) +#define CSR_MXSTATUS_DME_SHIFT (4U) +#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) +#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) + +/* + * PPFT_EN (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) +#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) +#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) +#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) + +/* + * PFT_EN (RW) + * + * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: + * PPFT_EN <= PFT_EN; + * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; + * On executing an MRET instruction: + * PFT_EN <= PPFT_EN; + * This field is hardwired to 0 if the PowerBrake feature is not supported. + */ +#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) +#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) +#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) +#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) + +/* Bitfield definition for register: MPFT_CTL */ +/* + * FAST_INT (RW) + * + * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. + */ +#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) +#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) +#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) +#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) + +/* + * T_LEVEL (RW) + * + * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest + * performance at throttling level 15. + * 0:Level 0 (the highest performance) + * 1-14:Level 1-14 + * 15:Level 15 (the lowest performance) + */ +#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) +#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) +#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) +#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) + +/* Bitfield definition for register: MHSP_CTL */ +/* + * M (RW) + * + * Enables the SP protection and recording mechanism in Machine mode + * 0:The mechanism is disabled in Machine mode. + * 1: The mechanism is enabled in Machine mode. + */ +#define CSR_MHSP_CTL_M_MASK (0x20U) +#define CSR_MHSP_CTL_M_SHIFT (5U) +#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) +#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) + +/* + * S (RW) + * + * Enables the SP protection and recording mechanism in Supervisor mode + * 0:The mechanism is disabled in Supervisor mode + * 1:The mechanism is enabled in Supervisor mode + */ +#define CSR_MHSP_CTL_S_MASK (0x10U) +#define CSR_MHSP_CTL_S_SHIFT (4U) +#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) +#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) + +/* + * U (RW) + * + * Enables the SP protection and recording mechanism in User mode + * 0:The mechanism is disabled in User mode + * 1:The mechanism is enabled in User mode. + */ +#define CSR_MHSP_CTL_U_MASK (0x8U) +#define CSR_MHSP_CTL_U_SHIFT (3U) +#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) +#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) + +/* + * SCHM (RW) + * + * Selects the operating scheme of the stack protection and recording mechanism + * 0:Stack overflow/underflow detection + * 1:Top-of-stack recording + */ +#define CSR_MHSP_CTL_SCHM_MASK (0x4U) +#define CSR_MHSP_CTL_SCHM_SHIFT (2U) +#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) +#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) + +/* + * UDF_EN (RW) + * + * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack underflow protection is disabled + * 1:The stack underflow protection is enabled. + */ +#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) +#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) +#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) +#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) + +/* + * OVF_EN (RW) + * + * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack overflow protection and recording mechanism are disabled. + * 1:The stack overflow protection and recording mechanism are enabled. + */ +#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) +#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) +#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) +#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) + +/* Bitfield definition for register: MSP_BOUND */ +/* + * MSP_BOUND (RW) + * + * Machine SP Bound + */ +#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) +#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) +#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) + +/* Bitfield definition for register: MSP_BASE */ +/* + * SP_BASE (RW) + * + * Machine SP base + */ +#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) +#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) +#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) + +/* Bitfield definition for register: MDCAUSE */ +/* + * PM (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MDCAUSE_PM_MASK (0x60U) +#define CSR_MDCAUSE_PM_SHIFT (5U) +#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) +#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) + +/* + * MDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the mcause register. + * The value of MDCAUSE for precise exception: + * When mcause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When mcause == 2 (Illegal instruction): + * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When mcause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When mcause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of MDCAUSE for imprecise exception: + * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) +#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) +#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) +#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) + +/* Bitfield definition for register: MCACHE_CTL */ +/* + * DC_WAROUND (RW) + * + * Cache Write-Around threshold + * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. + * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. + * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. + * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. + */ +#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) +#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) +#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) +#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) + +/* + * DC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) + +/* + * IC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) + +/* + * DPREF_EN (RW) + * + * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 + * 0:Disable hardware prefetch on load/store memory accesses + * 1:Enable hardware prefetch on load/store memory accesses + */ +#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) +#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) +#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) +#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) + +/* + * IPREF_EN (RW) + * + * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 + * 0:Disable hardware prefetch on instruction fetches + * 1:Enable hardware prefetch on instruction fetches + */ +#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) +#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) +#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) +#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) + +/* + * CCTL_SUEN (RW) + * + * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs + * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) +#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) + +/* + * DC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) +#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) +#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) +#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) + +/* + * IC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) +#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) +#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) +#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) + +/* + * DC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * data cache. + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) +#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) +#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) +#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) + +/* + * IC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * instruction cache + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) +#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) +#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) +#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) + +/* + * DC_EN (RW) + * + * Controls if the data cache is enabled or not. + * 0:D-Cache is disabled + * 1:D-Cache is enabled + */ +#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) +#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) +#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) +#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) + +/* + * IC_EN (RW) + * + * Controls if the instruction cache is enabled or not. + * 0:I-Cache is disabled + * 1:I-Cache is enabled + */ +#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) +#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) +#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) +#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) + +/* Bitfield definition for register: MCCTLBEGINADDR */ +/* + * VA (RW) + * + * This register holds the address information required by CCTL operations + */ +#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) +#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: MCCTLCOMMAND */ +/* + * VA (RW) + * + * See CCTL Command Definition Table + */ +#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) +#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_MCCTLDATA_VA_MASK (0x1FU) +#define CSR_MCCTLDATA_VA_SHIFT (0U) +#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) +#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: MCOUNTERWEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) +#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) +#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) +#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) +#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_IR_MASK (0x4U) +#define CSR_MCOUNTERWEN_IR_SHIFT (2U) +#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) +#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_CY_MASK (0x1U) +#define CSR_MCOUNTERWEN_CY_SHIFT (0U) +#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) +#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) +#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) +#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) +#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) +#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) +#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) +#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: MMISC_CTL */ +/* + * NBLD_EN (RW) + * + * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. + * 0:Load to memory regions are blocking. + * 1:Load to memory regions are non-blocking. + */ +#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) +#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) +#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) +#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) + +/* + * MSA_UNA (RW) + * + * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. + * Supported instructions: LW/LH/LHU/SW/SH + * 0:Misaligned accesses generate Address Misaligned exceptions. + * 1:Misaligned accesses generate Address Misaligned exceptions. + */ +#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) +#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) +#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) +#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) + +/* + * BRPE (RW) + * + * Branch prediction enable bit. This bit controls all branch prediction structures. + * 0:Disabled + * 1:Enabled + * This bit is hardwired to 0 if branch prediction structure is not supported. + */ +#define CSR_MMISC_CTL_BRPE_MASK (0x8U) +#define CSR_MMISC_CTL_BRPE_SHIFT (3U) +#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) +#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) + +/* + * RVCOMPM (RW) + * + * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions + * 0:Disabled + * 1:Enabled + */ +#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) +#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) +#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) +#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) + +/* + * VEC_PLIC (RW) + * + * Selects the operation mode of PLIC: + * 0:Regular mode + * 1:Vector mode + * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. + */ +#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) +#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) +#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) +#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) +#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) +#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) +#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) +#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) +#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) +#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) +#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) +#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) +#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) +#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) +#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) +#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) +#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) +#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) +#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) +#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) +#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) +#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) +#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) +#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) +#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) +#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_IR_MASK (0x4U) +#define CSR_MCOUNTEROVF_IR_SHIFT (2U) +#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) +#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_CY_MASK (0x1U) +#define CSR_MCOUNTEROVF_CY_SHIFT (0U) +#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) +#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: MSLIDELEG */ +/* + * PMOVI (RW) + * + * Delegate S-mode performance monitor overflow local interrupt to S-mode. + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) +#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) +#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) +#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Delegate S-mode bus read/write transaction error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) +#define CSR_MSLIDELEG_BWEI_SHIFT (17U) +#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) +#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Delegate S-mode slave-port ECC error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) +#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) +#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) +#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) + +/* Bitfield definition for register: MCLK_CTL */ +/* + * FUNIT (RW) + * + * Level 2 clock gating enable for function units listed in the following table. + * 16:integer arithmetic unit + * 17:integer permutation unit + * 18:integer mask unit + * 19:integer division unit + * 20:integer multiply and add unit + * 21:floating-point multiply and add + * unit + * 22:floating-point miscellaneous unit + * 23:floating-point division unit + * 24:load/store unit + * 31:25:Reserved + */ +#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) +#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) +#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) +#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) + +/* + * VI (RW) + * + * Level 1 clock gating enable for the vector/floating-point issue queues. + */ +#define CSR_MCLK_CTL_VI_MASK (0x8000U) +#define CSR_MCLK_CTL_VI_SHIFT (15U) +#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) +#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) + +/* + * VR (RW) + * + * Level 1 clock gating enable for the vector/floating-point register file. + */ +#define CSR_MCLK_CTL_VR_MASK (0x4000U) +#define CSR_MCLK_CTL_VR_SHIFT (14U) +#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) +#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) + +/* + * AQ (RW) + * + * Level 1 clock gating enable for ACE load/store queues. + */ +#define CSR_MCLK_CTL_AQ_MASK (0x2000U) +#define CSR_MCLK_CTL_AQ_SHIFT (13U) +#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) +#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) + +/* + * DQ (RW) + * + * Level 1 clock gating enable for data cache load/store queues. + */ +#define CSR_MCLK_CTL_DQ_MASK (0x1000U) +#define CSR_MCLK_CTL_DQ_SHIFT (12U) +#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) +#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) + +/* + * UQ (RW) + * + * Level 1 clock gating enable for uncached queues + */ +#define CSR_MCLK_CTL_UQ_MASK (0x800U) +#define CSR_MCLK_CTL_UQ_SHIFT (11U) +#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) +#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) + +/* + * FP (RW) + * + * Level 1 clock gating enable for scalar floating point issue unit and queues. + */ +#define CSR_MCLK_CTL_FP_MASK (0x400U) +#define CSR_MCLK_CTL_FP_SHIFT (10U) +#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) +#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) + +/* + * CLKGATE (RW) + * + * One-hot clock gating levels. + * 0:Level 1 clock gating in module level + * 1:Level 2 clock gating in unit level + * 2:Level 3 clock gating in VPU level + * 7:3:Reserved + */ +#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) +#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) +#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) +#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) + +/* Bitfield definition for register: DEXC2DBG */ +/* + * PMOV (RW) + * + * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) +#define CSR_DEXC2DBG_PMOV_SHIFT (19U) +#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) +#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) + +/* + * SPF (RW) + * + * Indicates whether store page fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) +#define CSR_DEXC2DBG_SPF_SHIFT (18U) +#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) +#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) + +/* + * LPF (RW) + * + * Indicates whether load fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) +#define CSR_DEXC2DBG_LPF_SHIFT (17U) +#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) +#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) + +/* + * IPF (RW) + * + * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) +#define CSR_DEXC2DBG_IPF_SHIFT (16U) +#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) +#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) + +/* + * BWE (RW) + * + * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_BWE_MASK (0x8000U) +#define CSR_DEXC2DBG_BWE_SHIFT (15U) +#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) +#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) + +/* + * SLPECC (RW) + * + * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) +#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) +#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) +#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) + +/* + * ACE (RW) + * + * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_ACE_MASK (0x2000U) +#define CSR_DEXC2DBG_ACE_SHIFT (13U) +#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) +#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) + +/* + * HSP (RW) + * + * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_HSP_MASK (0x1000U) +#define CSR_DEXC2DBG_HSP_SHIFT (12U) +#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) +#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) + +/* + * MEC (RW) + * + * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_MEC_MASK (0x800U) +#define CSR_DEXC2DBG_MEC_SHIFT (11U) +#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) +#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) + +/* + * SEC (RW) + * + * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SEC_MASK (0x200U) +#define CSR_DEXC2DBG_SEC_SHIFT (9U) +#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) +#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) + +/* + * UEC (RW) + * + * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_UEC_MASK (0x100U) +#define CSR_DEXC2DBG_UEC_SHIFT (8U) +#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) +#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) + +/* + * SAF (RW) + * + * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAF_MASK (0x80U) +#define CSR_DEXC2DBG_SAF_SHIFT (7U) +#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) +#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) + +/* + * SAM (RW) + * + * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAM_MASK (0x40U) +#define CSR_DEXC2DBG_SAM_SHIFT (6U) +#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) +#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) + +/* + * LAF (RW) + * + * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAF_MASK (0x20U) +#define CSR_DEXC2DBG_LAF_SHIFT (5U) +#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) +#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) + +/* + * LAM (RW) + * + * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAM_MASK (0x10U) +#define CSR_DEXC2DBG_LAM_SHIFT (4U) +#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) +#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) + +/* + * NMI (RW) + * + * Indicates whether Non-Maskable Interrupt + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_NMI_MASK (0x8U) +#define CSR_DEXC2DBG_NMI_SHIFT (3U) +#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) +#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) + +/* + * II (RW) + * + * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_II_MASK (0x4U) +#define CSR_DEXC2DBG_II_SHIFT (2U) +#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) +#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) + +/* + * IAF (RW) + * + * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAF_MASK (0x2U) +#define CSR_DEXC2DBG_IAF_SHIFT (1U) +#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) +#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) + +/* + * IAM (RW) + * + * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAM_MASK (0x1U) +#define CSR_DEXC2DBG_IAM_SHIFT (0U) +#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) +#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) + +/* Bitfield definition for register: DDCAUSE */ +/* + * SUBTYPE (RO) + * + * Subtypes for main type. + * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. + * 0:Illegal instruction + * 1:Privileged instruction + * 2:Non-existent CSR + * 3:Privilege CSR access + * 4:Read-only CSR update + */ +#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) +#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) +#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) + +/* + * MAINTYPE (RO) + * + * Cause for redirection to Debug Mode. + * 0:Software Breakpoint (EBREAK) + * 1:Instruction Access Misaligned (IAM) + * 2:Instruction Access Fault (IAF) + * 3:Illegal Instruction (II) + * 4:Non-Maskable Interrupt (NMI) + * 5:Load Access Misaligned (LAM) + * 6:Load Access Fault (LAF) + * 7:Store Access Misaligned (SAM) + * 8:Store Access Fault (SAF) + * 9:U-mode Environment Call (UEC) + * 10:S-mode Environment Call (SEC) + * 11:Instruction page fault + * 12:M-mode Environment Call (MEC) + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 16:Imprecise ECC error + * 17;Bus write transaction error + * 18:Performance Counter overflow + * 19–31:Reserved + * 32:Stack overflow exception + * 33:Stack underflow exception + * 34:ACE disabled exception + * 35–39:Reserved + * 40–47:ACE exception + * ≥48:Reserved + */ +#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) +#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) +#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) + +/* Bitfield definition for register: UITB */ +/* + * ADDR (RW) + * + * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. + */ +#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) +#define CSR_UITB_ADDR_SHIFT (2U) +#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) +#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) + +/* + * HW (RO) + * + * This bit specifies if the CoDense instruction table is hardwired. + * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. + * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. + */ +#define CSR_UITB_HW_MASK (0x1U) +#define CSR_UITB_HW_SHIFT (0U) +#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) + +/* Bitfield definition for register: UCODE */ +/* + * OV (RW) + * + * Overflow flag. It will be set by DSP instructions with a saturated result. + * 0:A saturated result is not generated + * 1:A saturated result is generated + */ +#define CSR_UCODE_OV_MASK (0x1U) +#define CSR_UCODE_OV_SHIFT (0U) +#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) +#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) + +/* Bitfield definition for register: UDCAUSE */ +/* + * UDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. + * The value of UDCAUSE for precise exception: + * When ucause == 1 (Instruction access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP instruction access violation + * 3:Bus error + * 4:PMA empty hole access + * When ucause == 2 (Illegal instruction) + * 0:Please parse the utval CSR + * 1:FP disabled exception + * 2:ACE disabled exception + * When ucause == 5 (Load access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP load access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + * When ucause == 7 (Store access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP store access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + */ +#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) +#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) +#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) +#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) + +/* Bitfield definition for register: UCCTLBEGINADDR */ +/* + * VA (RW) + * + * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. + */ +#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) +#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: UCCTLCOMMAND */ +/* + * VA (RW) + * + * See User CCTL Command Definition Table + */ +#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) +#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: SLIE */ +/* + * PMOVI (RW) + * + * Enable S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_PMOVI_MASK (0x40000UL) +#define CSR_SLIE_PMOVI_SHIFT (18U) +#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) +#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_BWEI_MASK (0x20000UL) +#define CSR_SLIE_BWEI_SHIFT (17U) +#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) +#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Enable S-mode slave-port ECC error local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_IMECCI_MASK (0x10000UL) +#define CSR_SLIE_IMECCI_SHIFT (16U) +#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) +#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) + +/* Bitfield definition for register: SLIP */ +/* + * PMOVI (RW) + * + * Pending control and status of S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_PMOVI_MASK (0x40000UL) +#define CSR_SLIP_PMOVI_SHIFT (18U) +#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) +#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_BWEI_MASK (0x20000UL) +#define CSR_SLIP_BWEI_SHIFT (17U) +#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) +#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Pending control and status of S-mode slave-port ECC error local interrupt.. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_IMECCI_MASK (0x10000UL) +#define CSR_SLIP_IMECCI_SHIFT (16U) +#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) +#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) + +/* Bitfield definition for register: SDCAUSE */ +/* + * PM (RW) + * + * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0:User mode + * 1:Supervisor mode + * 2:Reserved + * 3:Machine mode + */ +#define CSR_SDCAUSE_PM_MASK (0x60U) +#define CSR_SDCAUSE_PM_SHIFT (5U) +#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) +#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) + +/* + * SDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. + * The value of SDCAUSE for precise exception: + * When scause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When scause == 2 (Illegal instruction): + * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When scause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When scause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of SDCAUSE for imprecise exception: + * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) +#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) +#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) +#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) + +/* Bitfield definition for register: SCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_SCCTLDATA_VA_MASK (0x1FU) +#define CSR_SCCTLDATA_VA_SHIFT (0U) +#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) +#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: SCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) +#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) +#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) +#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) +#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) +#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) +#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) +#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) +#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) +#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) +#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) +#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) +#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) +#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) +#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) +#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) +#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) +#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) +#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) +#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) +#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) +#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) +#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) +#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) +#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) +#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) +#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) +#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) +#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_IR_MASK (0x4U) +#define CSR_SCOUNTEROVF_IR_SHIFT (2U) +#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) +#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_CY_MASK (0x1U) +#define CSR_SCOUNTEROVF_CY_SHIFT (0U) +#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) +#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) +#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) +#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) +#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) +#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) +#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) +#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) +#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: SHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT3_SEL_SHIFT (4U) +#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) +#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) +#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT4_SEL_SHIFT (4U) +#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) +#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) +#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT5_SEL_SHIFT (4U) +#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) +#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) +#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT6_SEL_SHIFT (4U) +#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) +#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) +#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MICM_CFG */ +/* + * SETH (RO) + * + * This bit extends the ISET field. + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MICM_CFG_SETH_SHIFT (24U) +#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) + +/* + * ILM_ECC (RO) + * + * ILM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) +#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) +#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) + +/* + * ILMSZ (RO) + * + * ILM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) +#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) +#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) + +/* + * ILMB (RW) + * + * Number of ILM base registers present + * 0:No ILM base register present + * 1:One ILM base register present + * 2-7:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMB_MASK (0x7000U) +#define CSR_MICM_CFG_ILMB_SHIFT (12U) +#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) +#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) + +/* + * IC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) +#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) +#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) + +/* + * ILCK (RO) + * + * I-Cache locking support + * 0:No locking support + * 1:With locking support + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILCK_MASK (0x200U) +#define CSR_MICM_CFG_ILCK_SHIFT (9U) +#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) + +/* + * ISZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) +#define CSR_MICM_CFG_ISZ_SHIFT (6U) +#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) + +/* + * IWAY (RO) + * + * Associativity of I-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IWAY_MASK (0x38U) +#define CSR_MICM_CFG_IWAY_SHIFT (3U) +#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) + +/* + * ISET (RO) + * + * I-Cache sets (# of cache lines per way): + * When micm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When micm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + */ +#define CSR_MICM_CFG_ISET_MASK (0x7U) +#define CSR_MICM_CFG_ISET_SHIFT (0U) +#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) + +/* Bitfield definition for register: MDCM_CFG */ +/* + * SETH (RO) + * + * This bit extends the DSET field. + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MDCM_CFG_SETH_SHIFT (24U) +#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) + +/* + * DLM_ECC (RO) + * + * DLM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When DLM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) +#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) +#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) + +/* + * DLMSZ (RO) + * + * DLM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) +#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) +#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) + +/* + * DLMB (RO) + * + * Number of DLM base registers present + * 0:No DLM base register present + * 1:One DLM base register present + * 2-7:Reserved + * When DLM is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) +#define CSR_MDCM_CFG_DLMB_SHIFT (12U) +#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) + +/* + * DC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC support + * 1:Has parity support + * 2:Has ECC support + * 3:Reserved + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) +#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) +#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) + +/* + * DLCK (RO) + * + * D-Cache locking support + * 0:No locking support + * 1:With locking support + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLCK_MASK (0x200U) +#define CSR_MDCM_CFG_DLCK_SHIFT (9U) +#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) + +/* + * DSZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) +#define CSR_MDCM_CFG_DSZ_SHIFT (6U) +#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) + +/* + * DWAY (RO) + * + * Associativity of D-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DWAY_MASK (0x38U) +#define CSR_MDCM_CFG_DWAY_SHIFT (3U) +#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) + +/* + * DSET (RO) + * + * D-Cache sets (# of cache lines per way): + * When mdcm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When mdcm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DSET_MASK (0x7U) +#define CSR_MDCM_CFG_DSET_SHIFT (0U) +#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) + +/* Bitfield definition for register: MMSC_CFG */ +/* + * MSC_EXT (RO) + * + * Indicates if the mmsc_cfg2 CSR is present or not. + * 0:The mmsc_cfg2 CSR is not present. + * 1:The mmsc_cfg2 CSR is present + */ +#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) +#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) +#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) + +/* + * PPMA (RO) + * + * Indicates if programmable PMA setup with PMA region CSRs is supported or not + * 0:Programmable PMA setup is not supported. + * 1:Programmable PMA setup is supported. + */ +#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) +#define CSR_MMSC_CFG_PPMA_SHIFT (30U) +#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) + +/* + * EDSP (RO) + * + * Indicates if the DSP extension is supported or not + * 0:The DSP extension is not supported. + * 1:The DSP extension is supported. + */ +#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) +#define CSR_MMSC_CFG_EDSP_SHIFT (29U) +#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) + +/* + * VCCTL (RO) + * + * Indicates the version number of CCTL command operation scheme supported by an implementation + * 0:instruction cache and data cache are not configured. + * 1:instruction cache or data cache is configured. + */ +#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) +#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) +#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) + +/* + * EFHW (RO) + * + * Indicates the support of FLHW and FSHW instructions + * 0:FLHW and FSHW instructions are not supported + * 1:FLHW and FSHW instructions are supported. + */ +#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) +#define CSR_MMSC_CFG_EFHW_SHIFT (17U) +#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) + +/* + * CCTLCSR (RO) + * + * Indicates the presence of CSRs for CCTL operations. + * 0:Feature of CSRs for CCTL operations is not supported. + * 1:Feature of CSRs for CCTL operations is supported. + */ +#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) +#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) +#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) + +/* + * PMNDS (RO) + * + * Indicates if Andes-enhanced performance monitoring feature is present or no. + * 0:Andes-enhanced performance monitoring feature is not supported. + * 1:Andes-enhanced performance monitoring feature is supported. + */ +#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) +#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) +#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) + +/* + * LMSLVP (RO) + * + * Indicates if local memory slave port is present or not. + * 0:Local memory slave port is not present. + * 1:Local memory slave port is implemented. + */ +#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) +#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) +#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) + +/* + * EV5PE (RO) + * + * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) +#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) +#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) + +/* + * VPLIC (RO) + * + * Indicates whether the Andes Vectored PLIC Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) +#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) +#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) + +/* + * ACE (RO) + * + * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ACE_MASK (0x40U) +#define CSR_MMSC_CFG_ACE_SHIFT (6U) +#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) + +/* + * HSP (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_HSP_MASK (0x20U) +#define CSR_MMSC_CFG_HSP_SHIFT (5U) +#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) + +/* + * PFT (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_PFT_MASK (0x10U) +#define CSR_MMSC_CFG_PFT_SHIFT (4U) +#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) + +/* + * ECD (RO) + * + * Indicates whether the Andes CoDense Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ECD_MASK (0x8U) +#define CSR_MMSC_CFG_ECD_SHIFT (3U) +#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) + +/* + * TLB_ECC (RO) + * + * TLB parity/ECC support configuration. + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + */ +#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) +#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) +#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) + +/* + * ECC (RO) + * + * Indicates whether the parity/ECC soft-error protection is implemented or not. + * 0:Not implemented. + * 1:Implemented. + * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. + * micm_cfg.IC_ECC + * micm_cfg.ILM_ECC + * mdcm_cfg.DC_ECC + * mdcm_cfg.DLM_ECC + * mmsc_cfg.TLB_ECC + */ +#define CSR_MMSC_CFG_ECC_MASK (0x1U) +#define CSR_MMSC_CFG_ECC_SHIFT (0U) +#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) + +/* Bitfield definition for register: MMSC_CFG2 */ +/* + * FINV (RO) + * + * Indicates if scalar FPU is implemented in VPU + * 0:Scalar FPU is not implemented in VPU + * 1:Scalar FPU is implemented in VPU + */ +#define CSR_MMSC_CFG2_FINV_MASK (0x20U) +#define CSR_MMSC_CFG2_FINV_SHIFT (5U) +#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) + +/* + * ZFH (RO) + * + * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. + * 0:The FP16 extension is not supported. + * 1:The FP16 extension is supported + */ +#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) +#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) +#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) + +/* + * BF16CVT (RO) + * + * Indicates if the BFLOAT16 conversion extension + * is supported or not. + * 0:The BFLOAT16 conversion extension is not supported + * 1:The BFLOAT16 conversion extension is supported + */ +#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) +#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) +#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) + + +#endif /* HPM_CSR_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h new file mode 100644 index 0000000000..612b4d6e75 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_SRC_H +#define HPM_DMAMUX_SRC_H + +/* dma mux definitions */ +#define HPM_DMA_SRC_SPI0_RX (0x0UL) +#define HPM_DMA_SRC_SPI0_TX (0x1UL) +#define HPM_DMA_SRC_SPI1_RX (0x2UL) +#define HPM_DMA_SRC_SPI1_TX (0x3UL) +#define HPM_DMA_SRC_SPI2_RX (0x4UL) +#define HPM_DMA_SRC_SPI2_TX (0x5UL) +#define HPM_DMA_SRC_SPI3_RX (0x6UL) +#define HPM_DMA_SRC_SPI3_TX (0x7UL) +#define HPM_DMA_SRC_UART0_RX (0x8UL) +#define HPM_DMA_SRC_UART0_TX (0x9UL) +#define HPM_DMA_SRC_UART1_RX (0xAUL) +#define HPM_DMA_SRC_UART1_TX (0xBUL) +#define HPM_DMA_SRC_UART2_RX (0xCUL) +#define HPM_DMA_SRC_UART2_TX (0xDUL) +#define HPM_DMA_SRC_UART3_RX (0xEUL) +#define HPM_DMA_SRC_UART3_TX (0xFUL) +#define HPM_DMA_SRC_UART4_RX (0x10UL) +#define HPM_DMA_SRC_UART4_TX (0x11UL) +#define HPM_DMA_SRC_UART5_RX (0x12UL) +#define HPM_DMA_SRC_UART5_TX (0x13UL) +#define HPM_DMA_SRC_UART6_RX (0x14UL) +#define HPM_DMA_SRC_UART6_TX (0x15UL) +#define HPM_DMA_SRC_UART7_RX (0x16UL) +#define HPM_DMA_SRC_UART7_TX (0x17UL) +#define HPM_DMA_SRC_UART8_RX (0x18UL) +#define HPM_DMA_SRC_UART8_TX (0x19UL) +#define HPM_DMA_SRC_UART9_RX (0x1AUL) +#define HPM_DMA_SRC_UART9_TX (0x1BUL) +#define HPM_DMA_SRC_UART10_RX (0x1CUL) +#define HPM_DMA_SRC_UART10_TX (0x1DUL) +#define HPM_DMA_SRC_UART11_RX (0x1EUL) +#define HPM_DMA_SRC_UART11_TX (0x1FUL) +#define HPM_DMA_SRC_UART12_RX (0x20UL) +#define HPM_DMA_SRC_UART12_TX (0x21UL) +#define HPM_DMA_SRC_UART13_RX (0x22UL) +#define HPM_DMA_SRC_UART13_TX (0x23UL) +#define HPM_DMA_SRC_UART14_RX (0x24UL) +#define HPM_DMA_SRC_UART14_TX (0x25UL) +#define HPM_DMA_SRC_UART15_RX (0x26UL) +#define HPM_DMA_SRC_UART15_TX (0x27UL) +#define HPM_DMA_SRC_I2S0_RX (0x28UL) +#define HPM_DMA_SRC_I2S0_TX (0x29UL) +#define HPM_DMA_SRC_I2S1_RX (0x2AUL) +#define HPM_DMA_SRC_I2S1_TX (0x2BUL) +#define HPM_DMA_SRC_I2S2_RX (0x2CUL) +#define HPM_DMA_SRC_I2S2_TX (0x2DUL) +#define HPM_DMA_SRC_I2S3_RX (0x2EUL) +#define HPM_DMA_SRC_I2S3_TX (0x2FUL) +#define HPM_DMA_SRC_MOT0_0 (0x30UL) +#define HPM_DMA_SRC_MOT0_1 (0x31UL) +#define HPM_DMA_SRC_MOT0_2 (0x32UL) +#define HPM_DMA_SRC_MOT0_3 (0x33UL) +#define HPM_DMA_SRC_MOT1_0 (0x34UL) +#define HPM_DMA_SRC_MOT1_1 (0x35UL) +#define HPM_DMA_SRC_MOT1_2 (0x36UL) +#define HPM_DMA_SRC_MOT1_3 (0x37UL) +#define HPM_DMA_SRC_MOT2_0 (0x38UL) +#define HPM_DMA_SRC_MOT2_1 (0x39UL) +#define HPM_DMA_SRC_MOT2_2 (0x3AUL) +#define HPM_DMA_SRC_MOT2_3 (0x3BUL) +#define HPM_DMA_SRC_MOT3_0 (0x3CUL) +#define HPM_DMA_SRC_MOT3_1 (0x3DUL) +#define HPM_DMA_SRC_MOT3_2 (0x3EUL) +#define HPM_DMA_SRC_MOT3_3 (0x3FUL) +#define HPM_DMA_SRC_NTMR0_0 (0x40UL) +#define HPM_DMA_SRC_NTMR0_1 (0x41UL) +#define HPM_DMA_SRC_NTMR0_2 (0x42UL) +#define HPM_DMA_SRC_NTMR0_3 (0x43UL) +#define HPM_DMA_SRC_NTMR1_0 (0x44UL) +#define HPM_DMA_SRC_NTMR1_1 (0x45UL) +#define HPM_DMA_SRC_NTMR1_2 (0x46UL) +#define HPM_DMA_SRC_NTMR1_3 (0x47UL) +#define HPM_DMA_SRC_GPTMR0_0 (0x48UL) +#define HPM_DMA_SRC_GPTMR0_1 (0x49UL) +#define HPM_DMA_SRC_GPTMR0_2 (0x4AUL) +#define HPM_DMA_SRC_GPTMR0_3 (0x4BUL) +#define HPM_DMA_SRC_GPTMR1_0 (0x4CUL) +#define HPM_DMA_SRC_GPTMR1_1 (0x4DUL) +#define HPM_DMA_SRC_GPTMR1_2 (0x4EUL) +#define HPM_DMA_SRC_GPTMR1_3 (0x4FUL) +#define HPM_DMA_SRC_GPTMR2_0 (0x50UL) +#define HPM_DMA_SRC_GPTMR2_1 (0x51UL) +#define HPM_DMA_SRC_GPTMR2_2 (0x52UL) +#define HPM_DMA_SRC_GPTMR2_3 (0x53UL) +#define HPM_DMA_SRC_GPTMR3_0 (0x54UL) +#define HPM_DMA_SRC_GPTMR3_1 (0x55UL) +#define HPM_DMA_SRC_GPTMR3_2 (0x56UL) +#define HPM_DMA_SRC_GPTMR3_3 (0x57UL) +#define HPM_DMA_SRC_GPTMR4_0 (0x58UL) +#define HPM_DMA_SRC_GPTMR4_1 (0x59UL) +#define HPM_DMA_SRC_GPTMR4_2 (0x5AUL) +#define HPM_DMA_SRC_GPTMR4_3 (0x5BUL) +#define HPM_DMA_SRC_GPTMR5_0 (0x5CUL) +#define HPM_DMA_SRC_GPTMR5_1 (0x5DUL) +#define HPM_DMA_SRC_GPTMR5_2 (0x5EUL) +#define HPM_DMA_SRC_GPTMR5_3 (0x5FUL) +#define HPM_DMA_SRC_GPTMR6_0 (0x60UL) +#define HPM_DMA_SRC_GPTMR6_1 (0x61UL) +#define HPM_DMA_SRC_GPTMR6_2 (0x62UL) +#define HPM_DMA_SRC_GPTMR6_3 (0x63UL) +#define HPM_DMA_SRC_GPTMR7_0 (0x64UL) +#define HPM_DMA_SRC_GPTMR7_1 (0x65UL) +#define HPM_DMA_SRC_GPTMR7_2 (0x66UL) +#define HPM_DMA_SRC_GPTMR7_3 (0x67UL) +#define HPM_DMA_SRC_I2C0 (0x68UL) +#define HPM_DMA_SRC_I2C1 (0x69UL) +#define HPM_DMA_SRC_I2C2 (0x6AUL) +#define HPM_DMA_SRC_I2C3 (0x6BUL) +#define HPM_DMA_SRC_XPI0_RX (0x6CUL) +#define HPM_DMA_SRC_XPI0_TX (0x6DUL) +#define HPM_DMA_SRC_XPI1_RX (0x6EUL) +#define HPM_DMA_SRC_XPI1_TX (0x6FUL) +#define HPM_DMA_SRC_ACMP_0 (0x70UL) +#define HPM_DMA_SRC_ACMP_1 (0x71UL) +#define HPM_DMA_SRC_ACMP_2 (0x72UL) +#define HPM_DMA_SRC_ACMP_3 (0x73UL) + + + +#endif /* HPM_DMAMUX_SRC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h new file mode 100644 index 0000000000..846a796630 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ENET_SOC_DRV_H +#define HPM_ENET_SOC_DRV_H + +#include "hpm_soc.h" + +#if defined __cplusplus +extern "C" { +#endif + +static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK); + HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx_delay); + } else if (ptr == HPM_ENET1) { + HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK); + HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(rx_delay); + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal) +{ + hpm_stat_t stat = status_success; + + /* use an internal PLL clock as reference clock for rmii mode */ + if (ptr == HPM_ENET0) { + if (internal == true) { + /* use a pll clock */ + HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_REFCLK_OE_MASK | CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; + } else { + /* use an external clock as reference clock for rmii mode */ + HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; /* use an external clock */ + } + } else if (ptr == HPM_ENET1) { + if (internal == true) { + /* use a pll clock */ + HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_REFCLK_OE_MASK | CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK; + } else { + /* use an external clock as reference clock for rmii mode */ + HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK; /* use an external clock */ + } + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_rgmii_enable_clock(ENET_Type *ptr) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + /* use an internal PLL clock for rgmii mode */ + HPM_CONCTL->CTRL2 &= ~CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; + } else if (ptr == HPM_ENET1) { + /* use an internal PLL clock for rgmii mode */ + HPM_CONCTL->CTRL3 &= ~CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK; + } else { + return status_invalid_argument; + } + + return stat; +} + +static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) +{ + hpm_stat_t stat = status_success; + + if (ptr == HPM_ENET0) { + HPM_CONCTL->CTRL2 &= ~CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK; + HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET(inf_type); + } else if (ptr == HPM_ENET1) { + HPM_CONCTL->CTRL3 &= ~CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK; + HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET(inf_type); + } else { + return status_invalid_argument; + } + + return stat; +} +#if defined __cplusplus +} /* __cplusplus */ +#endif + +#endif /* HPM_ENET_SOC_DRV_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h new file mode 100644 index 0000000000..4f4197eedf --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPIOM_H +#define HPM_GPIOM_H + +typedef struct { + struct { + __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ + } ASSIGN[16]; +} GPIOM_Type; + + +/* Bitfield definition for register of struct array ASSIGN: PIN00 */ +/* + * LOCK (RW) + * + * lock fields in this register, lock can only be cleared by soc reset + * 0: fields can be changed + * 1: fields locked to current value, not changeable + */ +#define GPIOM_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_PIN_LOCK_SHIFT (31U) +#define GPIOM_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_PIN_LOCK_SHIFT) & GPIOM_PIN_LOCK_MASK) +#define GPIOM_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_PIN_LOCK_MASK) >> GPIOM_PIN_LOCK_SHIFT) + +/* + * HIDE (RW) + * + * pin value visibility to gpios, + * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 + * bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 + * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + * bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + */ +#define GPIOM_PIN_HIDE_MASK (0xF00U) +#define GPIOM_PIN_HIDE_SHIFT (8U) +#define GPIOM_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_PIN_HIDE_SHIFT) & GPIOM_PIN_HIDE_MASK) +#define GPIOM_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_PIN_HIDE_MASK) >> GPIOM_PIN_HIDE_SHIFT) + +/* + * SELECT (RW) + * + * select which gpio controls chip pin, + * 0: soc gpio0; + * 1: soc gpio1; + * 2: cpu0 fastgpio + * 3: cpu1 fast gpio + */ +#define GPIOM_PIN_SELECT_MASK (0x3U) +#define GPIOM_PIN_SELECT_SHIFT (0U) +#define GPIOM_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_PIN_SELECT_SHIFT) & GPIOM_PIN_SELECT_MASK) +#define GPIOM_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_PIN_SELECT_MASK) >> GPIOM_PIN_SELECT_SHIFT) + + + +/* PIN register group index macro definition */ +#define GPIOM_ASSIGN_PIN_PIN00 (0UL) +#define GPIOM_ASSIGN_PIN_PIN01 (1UL) +#define GPIOM_ASSIGN_PIN_PIN02 (2UL) +#define GPIOM_ASSIGN_PIN_PIN03 (3UL) +#define GPIOM_ASSIGN_PIN_PIN04 (4UL) +#define GPIOM_ASSIGN_PIN_PIN05 (5UL) +#define GPIOM_ASSIGN_PIN_PIN06 (6UL) +#define GPIOM_ASSIGN_PIN_PIN07 (7UL) +#define GPIOM_ASSIGN_PIN_PIN08 (8UL) +#define GPIOM_ASSIGN_PIN_PIN09 (9UL) +#define GPIOM_ASSIGN_PIN_PIN10 (10UL) +#define GPIOM_ASSIGN_PIN_PIN11 (11UL) +#define GPIOM_ASSIGN_PIN_PIN12 (12UL) +#define GPIOM_ASSIGN_PIN_PIN13 (13UL) +#define GPIOM_ASSIGN_PIN_PIN14 (14UL) +#define GPIOM_ASSIGN_PIN_PIN15 (15UL) +#define GPIOM_ASSIGN_PIN_PIN16 (16UL) +#define GPIOM_ASSIGN_PIN_PIN17 (17UL) +#define GPIOM_ASSIGN_PIN_PIN18 (18UL) +#define GPIOM_ASSIGN_PIN_PIN19 (19UL) +#define GPIOM_ASSIGN_PIN_PIN20 (20UL) +#define GPIOM_ASSIGN_PIN_PIN21 (21UL) +#define GPIOM_ASSIGN_PIN_PIN22 (22UL) +#define GPIOM_ASSIGN_PIN_PIN23 (23UL) +#define GPIOM_ASSIGN_PIN_PIN24 (24UL) +#define GPIOM_ASSIGN_PIN_PIN25 (25UL) +#define GPIOM_ASSIGN_PIN_PIN26 (26UL) +#define GPIOM_ASSIGN_PIN_PIN27 (27UL) +#define GPIOM_ASSIGN_PIN_PIN28 (28UL) +#define GPIOM_ASSIGN_PIN_PIN29 (29UL) +#define GPIOM_ASSIGN_PIN_PIN30 (30UL) +#define GPIOM_ASSIGN_PIN_PIN31 (31UL) + +/* ASSIGN register group index macro definition */ +#define GPIOM_ASSIGN_GPIOA (0UL) +#define GPIOM_ASSIGN_GPIOB (1UL) +#define GPIOM_ASSIGN_GPIOC (2UL) +#define GPIOM_ASSIGN_GPIOD (3UL) +#define GPIOM_ASSIGN_GPIOE (4UL) +#define GPIOM_ASSIGN_GPIOF (5UL) +#define GPIOM_ASSIGN_GPIOX (13UL) +#define GPIOM_ASSIGN_GPIOY (14UL) +#define GPIOM_ASSIGN_GPIOZ (15UL) + + +#endif /* HPM_GPIOM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h new file mode 100644 index 0000000000..23e5140883 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIOM_SOC_DRV_H +#define HPM_GPIOM_SOC_DRV_H + +/** + * @addtogroup gpiom_interface GPIOM driver APIs + * @{ + */ + +/* @brief gpiom control module */ +typedef enum hpm6700_gpiom_gpio { + gpiom_soc_gpio0 = 0, + gpiom_soc_gpio1 = 1, + gpiom_core0_fast = 2, + gpiom_core1_fast = 3, +} gpiom_gpio_t; + +/** + * @} + */ + +#endif /* HPM_GPIOM_SOC_DRV_H */ + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h new file mode 100644 index 0000000000..e361b87730 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_INTERRUPT_H +#define HPM_INTERRUPT_H +#include "riscv/riscv_core.h" +#include "hpm_common.h" +#include "hpm_plic_drv.h" + +/** + * @brief INTERRUPT driver APIs + * @defgroup irq_interface INTERRUPT driver APIs + * @{ + */ + +#define M_MODE 0 /*!< Machine mode */ +#define S_MODE 1 /*!< Supervisor mode */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable global IRQ with mask + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask + * + * @param[in] mask interrupt mask to be disabled + */ +ATTR_ALWAYS_INLINE static inline void disable_global_irq(uint32_t mask) +{ + clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Enable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) +{ + set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Disable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ + */ +ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) +{ + set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/* + * CPU Machine SWI control + * + * Machine SWI (MSIP) is connected to PLICSW irq 1. + */ +#define PLICSWI 1 + +/** + * @brief Initialize software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) +{ + __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + + +/** + * @brief Enable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) +{ + set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Disable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Trigger software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) +{ + __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); +} + + +/** + * @brief Claim software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) +{ + __plic_claim_irq(HPM_PLICSW_BASE, 0); +} + +/** + * @brief Complete software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) +{ + __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + +/* + * @brief Enable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Disable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +#define intc_m_set_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) + +/* + * @brief Complete IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Claim IRQ for machine mode + * + */ +#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) + +/* + * @brief Enable IRQ for machine mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_m_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_m_enable_irq(irq); \ + } while(0); + +/* + * @brief Enable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) +{ + __plic_enable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) +{ + __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); +} + +/** + * @brief Disable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) +{ + __plic_disable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt threshold + * + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + */ +ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) +{ + __plic_set_threshold(HPM_PLIC_BASE, target, threshold); +} + +/** + * @brief Claim IRQ + * + * @param[in] target Target to handle specific interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) +{ + return __plic_claim_irq(HPM_PLIC_BASE, target); +} + +/** + * @brief Complete IRQ + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Specific IRQ to be completed + * + */ +ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) +{ + __plic_complete_irq(HPM_PLIC_BASE, target, irq); +} + +/* + * Vectored based irq install and uninstall + */ +extern int __vector_table[]; +extern void default_irq_entry(void); + +/** + * @brief Install ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) +{ + __vector_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) +{ + __vector_table[irq] = (int)default_irq_entry; +} + +/* + * Inline nested irq entry/exit macros + */ +/* + * @brief Save CSR + * @param[in] r Target CSR to be saved + */ +#define SAVE_CSR(r) register long __##r = read_csr(r); + +/* + * @brief Restore macro + * + * @param[in] r Target CSR to be restored + */ +#define RESTORE_CSR(r) write_csr(r, __##r); + +#if SUPPORT_PFT_ARCH +#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) +#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) +#else +#define SAVE_MXSTATUS() +#define RESTORE_MXSTATUS() +#endif + +#ifdef __riscv_flen +#define SAVE_FCSR() register int __fcsr = read_fcsr(); +#define RESTORE_FCSR() write_fcsr(__fcsr); +#else +#define SAVE_FCSR() +#define RESTORE_FCSR() +#endif + +#ifdef __riscv_dsp +#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) +#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) +#else +#define SAVE_UCODE() +#define RESTORE_UCODE() +#endif + +#ifdef __riscv_flen +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP) + 21 FPU caller registers */ +#define CONTEXT_REG_NUM (4*(16 + 4 + 1 + 21)) +#else +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ +#define CONTEXT_REG_NUM (4*(16 + 4 + 1)) +#endif + +#ifdef __riscv_flen +/* + * Save FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack + */ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("fsw ft0, 21*4(sp) \n\ + fsw ft1, 22*4(sp) \n\ + fsw ft2, 23*4(sp) \n\ + fsw ft3, 24*4(sp) \n\ + fsw ft4, 25*4(sp) \n\ + fsw ft5, 26*4(sp) \n\ + fsw ft6, 27*4(sp) \n\ + fsw ft7, 28*4(sp) \n\ + fsw fa0, 29*4(sp) \n\ + fsw fa1, 30*4(sp) \n\ + fsw fa2, 31*4(sp) \n\ + fsw fa3, 32*4(sp) \n\ + fsw fa4, 33*4(sp) \n\ + fsw fa5, 34*4(sp) \n\ + fsw fa6, 35*4(sp) \n\ + fsw fa7, 36*4(sp) \n\ + fsw ft8, 37*4(sp) \n\ + fsw ft9, 38*4(sp) \n\ + fsw ft10, 39*4(sp) \n\ + fsw ft11, 40*4(sp) \n\ + frsr t6 \n\ + sw t6, 41*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 21 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("flw ft0, 21*4(sp) \n\ + flw ft1, 22*4(sp) \n\ + flw ft2, 23*4(sp) \n\ + flw ft3, 24*4(sp) \n\ + flw ft4, 25*4(sp) \n\ + flw ft5, 26*4(sp) \n\ + flw ft6, 27*4(sp) \n\ + flw ft7, 28*4(sp) \n\ + flw fa0, 29*4(sp) \n\ + flw fa1, 30*4(sp) \n\ + flw fa2, 31*4(sp) \n\ + flw fa3, 32*4(sp) \n\ + flw fa4, 33*4(sp) \n\ + flw fa5, 34*4(sp) \n\ + flw fa6, 35*4(sp) \n\ + flw fa7, 36*4(sp) \n\ + flw ft8, 37*4(sp) \n\ + flw ft9, 38*4(sp) \n\ + flw ft10, 39*4(sp) \n\ + flw ft11, 40*4(sp) \n\ + lw t6, 41*4(sp) \n\ + fssr t6, t6 \n");\ +} +#else +#define SAVE_FPU_CONTEXT() +#define RESTORE_FPU_CONTEXT() +#endif + +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("sw ra, 0*4(sp) \n\ + sw t0, 1*4(sp) \n\ + sw t1, 2*4(sp) \n\ + sw t2, 3*4(sp) \n\ + sw a0, 4*4(sp) \n\ + sw a1, 5*4(sp) \n\ + sw a2, 6*4(sp) \n\ + sw a3, 7*4(sp) \n\ + sw a4, 8*4(sp) \n\ + sw a5, 9*4(sp) \n\ + sw a6, 10*4(sp) \n\ + sw a7, 11*4(sp) \n\ + sw t3, 12*4(sp) \n\ + sw t4, 13*4(sp) \n\ + sw t5, 14*4(sp) \n\ + sw t6, 15*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("lw ra, 0*4(sp) \n\ + lw t0, 1*4(sp) \n\ + lw t1, 2*4(sp) \n\ + lw t2, 3*4(sp) \n\ + lw a0, 4*4(sp) \n\ + lw a1, 5*4(sp) \n\ + lw a2, 6*4(sp) \n\ + lw a3, 7*4(sp) \n\ + lw a4, 8*4(sp) \n\ + lw a5, 9*4(sp) \n\ + lw a6, 10*4(sp) \n\ + lw a7, 11*4(sp) \n\ + lw t3, 12*4(sp) \n\ + lw t4, 13*4(sp) \n\ + lw t5, 14*4(sp) \n\ + lw t6, 15*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} + +#ifdef __riscv_dsp +/* + * Save DSP context + * NOTE: To simplify the logic, DSP context registers are always stored at word offset 20 in the stack + */ +#define SAVE_DSP_CONTEXT() { \ + __asm volatile("csrr t6, ucode\n\ + sw t6, 20*4(sp)\n"); \ +} +/* + * @brief Restore DSP context + * @note To simplify the logic, DSP context registers are always stored at word offset 20 in the stack + */ +#define RESTORE_DSP_CONTEXT() {\ + __asm volatile("lw t6, 20*4(sp)\n\ + csrw ucode, t6 \n"); \ +} +#else +#define SAVE_DSP_CONTEXT() +#define RESTORE_DSP_CONTEXT() +#endif + +/* + * @brief Enter Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define ENTER_NESTED_IRQ_HANDLING_M() {\ + __asm volatile("csrr t6, mepc \n\ + sw t6, 17*4(sp) \n\ + csrr t6, mstatus \n\ + sw t6, 18*4(sp) \n\ + csrr t6, %0\n\ + sw t6, 19*4(sp) \n\ + " : : "i" CSR_MSTATUS);\ + SAVE_DSP_CONTEXT(); \ + __asm volatile("li t6, %0\n" : : "i" (CSR_MSTATUS_MIE_MASK)); \ + __asm volatile("csrrs t6, mstatus, t6\n"); \ +} +#define COMPLETE_IRQ_HANDLING_M(irq_num) {\ + __asm volatile("li t0, 0xe4000000 \n\ + li t1, 0x200004 \n\ + add t0, t0, t1 \n\ + lui t1, 0 \n\ + slli t2, t1, 0xc \n\ + add t0, t0, t2 \n");\ + __asm volatile("li t1, %0" : : "i" (irq_num) :); \ + __asm volatile("sw t1, 0(t0) \n\ + fence io, io \n\ + li t6, 1\n\ + addi t6, t6, -0x800\n\ + csrrs t6, mie, t6 \n"); \ +} + +/* + * @brief Exit Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define EXIT_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("csrrci t6, mstatus, 8 \n\ + lw t6, 18*4(sp) \n\ + csrw mstatus, t6 \n\ + lw t6, 17*4(sp) \n\ + csrw mepc, t6 \n\ + lw t6, 19*4(sp) \n\ + csrw %0, t6 \n" : : "i" CSR_MSTATUS);\ + RESTORE_DSP_CONTEXT(); \ +} + + +/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ +#define NESTED_IRQ_ENTER() \ + SAVE_CSR(CSR_MEPC) \ + SAVE_CSR(CSR_MSTATUS) \ + SAVE_MXSTATUS() \ + SAVE_FCSR() \ + SAVE_UCODE() \ + set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +/* @brief Nested IRQ exit macro : Restore CSRs */ +#define NESTED_IRQ_EXIT() \ + clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); \ + RESTORE_CSR(CSR_MSTATUS) \ + RESTORE_CSR(CSR_MEPC) \ + RESTORE_MXSTATUS() \ + RESTORE_FCSR() \ + RESTORE_UCODE() + +/* + * @brief Nested IRQ exit macro : Restore CSRs + * @param[in] irq Target interrupt number + */ +#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ +do { \ + clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ + __asm volatile("fence io, io"); \ + set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ +} while(0) + +#ifdef __cplusplus +#define HPM_EXTERN_C extern "C" +#else +#define HPM_EXTERN_C +#endif + +#define ISR_NAME_M(irq_num) default_isr_##irq_num +/** + * @brief Declare an external interrupt handler for machine mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#ifndef USE_NONVECTOR_MODE +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) {\ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_M();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + EXIT_NESTED_IRQ_HANDLING_M();\ + COMPLETE_IRQ_HANDLING_M(irq_num);\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("mret\n");\ +} +#else +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) { \ + isr(); \ +} +#endif + + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_isr(void) {\ + isr();\ +} + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h new file mode 100644 index 0000000000..a8d2aec494 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h @@ -0,0 +1,358 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOC_H +#define HPM_IOC_H + +typedef struct { + struct { + __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ + __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ + } PAD[492]; +} IOC_Type; + + +/* Bitfield definition for register of struct array PAD: FUNC_CTL */ +/* + * LOOP_BACK (RW) + * + * force input on + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) + +/* + * ANALOG (RW) + * + * select analog pin in pad + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) +#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) +#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) +#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) + +/* + * ALT_SELECT (RW) + * + * alt select + * 0: ALT0 + * 1: ALT1 + * … + * 31:ALT31 + */ +#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) + +/* Bitfield definition for register of struct array PAD: PAD_CTL */ +/* + * MS (RW) + * + * pin voltage select, only available in high-speed IO + * 0: 3.3V + * 1: 1.8V + */ +#define IOC_PAD_PAD_CTL_MS_MASK (0x4000U) +#define IOC_PAD_PAD_CTL_MS_SHIFT (14U) +#define IOC_PAD_PAD_CTL_MS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_MS_SHIFT) & IOC_PAD_PAD_CTL_MS_MASK) +#define IOC_PAD_PAD_CTL_MS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_MS_MASK) >> IOC_PAD_PAD_CTL_MS_SHIFT) + +/* + * OD (RW) + * + * open drain + * 0: open drain disable + * 1: open drain enable + */ +#define IOC_PAD_PAD_CTL_OD_MASK (0x2000U) +#define IOC_PAD_PAD_CTL_OD_SHIFT (13U) +#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) +#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) + +/* + * SMT (RW) + * + * schmitt trigger enable, only avaiable in high-speed IO + * 0: disable + * 1: enable + */ +#define IOC_PAD_PAD_CTL_SMT_MASK (0x1000U) +#define IOC_PAD_PAD_CTL_SMT_SHIFT (12U) +#define IOC_PAD_PAD_CTL_SMT_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SMT_SHIFT) & IOC_PAD_PAD_CTL_SMT_MASK) +#define IOC_PAD_PAD_CTL_SMT_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SMT_MASK) >> IOC_PAD_PAD_CTL_SMT_SHIFT) + +/* + * PS (RW) + * + * pull select + * 0: pull down + * 1: pull up + */ +#define IOC_PAD_PAD_CTL_PS_MASK (0x800U) +#define IOC_PAD_PAD_CTL_PS_SHIFT (11U) +#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) +#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) + +/* + * PE (RW) + * + * pull enable + * 0: pull disable + * 1: pull enable + */ +#define IOC_PAD_PAD_CTL_PE_MASK (0x10U) +#define IOC_PAD_PAD_CTL_PE_SHIFT (4U) +#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) +#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) + +/* + * DS (RW) + * + * drive strength + * for high-speed IO 3.3V: + * 000: 85.61Ohm + * 001: 61.2 Ohm + * 010: 42.88Ohm + * 011: 35.76Ohm + * 111: 30.67Ohm + * for high-speed IO 1.8V: + * 000: 84.07Ohm + * 001: 60.14Ohm + * 010: 42.15Ohm + * 011: 35.19Ohm + * 111: 30.2 Ohm + * for general IO: + * 00: 4mA + * 01: 8mA + * 11: 12mA + */ +#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) +#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) +#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) +#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) + + + +/* PAD register group index macro definition */ +#define IOC_PAD_PA00 (0UL) +#define IOC_PAD_PA01 (1UL) +#define IOC_PAD_PA02 (2UL) +#define IOC_PAD_PA03 (3UL) +#define IOC_PAD_PA04 (4UL) +#define IOC_PAD_PA05 (5UL) +#define IOC_PAD_PA06 (6UL) +#define IOC_PAD_PA07 (7UL) +#define IOC_PAD_PA08 (8UL) +#define IOC_PAD_PA09 (9UL) +#define IOC_PAD_PA10 (10UL) +#define IOC_PAD_PA11 (11UL) +#define IOC_PAD_PA12 (12UL) +#define IOC_PAD_PA13 (13UL) +#define IOC_PAD_PA14 (14UL) +#define IOC_PAD_PA15 (15UL) +#define IOC_PAD_PA16 (16UL) +#define IOC_PAD_PA17 (17UL) +#define IOC_PAD_PA18 (18UL) +#define IOC_PAD_PA19 (19UL) +#define IOC_PAD_PA20 (20UL) +#define IOC_PAD_PA21 (21UL) +#define IOC_PAD_PA22 (22UL) +#define IOC_PAD_PA23 (23UL) +#define IOC_PAD_PA24 (24UL) +#define IOC_PAD_PA25 (25UL) +#define IOC_PAD_PA26 (26UL) +#define IOC_PAD_PA27 (27UL) +#define IOC_PAD_PA28 (28UL) +#define IOC_PAD_PA29 (29UL) +#define IOC_PAD_PA30 (30UL) +#define IOC_PAD_PA31 (31UL) +#define IOC_PAD_PB00 (32UL) +#define IOC_PAD_PB01 (33UL) +#define IOC_PAD_PB02 (34UL) +#define IOC_PAD_PB03 (35UL) +#define IOC_PAD_PB04 (36UL) +#define IOC_PAD_PB05 (37UL) +#define IOC_PAD_PB06 (38UL) +#define IOC_PAD_PB07 (39UL) +#define IOC_PAD_PB08 (40UL) +#define IOC_PAD_PB09 (41UL) +#define IOC_PAD_PB10 (42UL) +#define IOC_PAD_PB11 (43UL) +#define IOC_PAD_PB12 (44UL) +#define IOC_PAD_PB13 (45UL) +#define IOC_PAD_PB14 (46UL) +#define IOC_PAD_PB15 (47UL) +#define IOC_PAD_PB16 (48UL) +#define IOC_PAD_PB17 (49UL) +#define IOC_PAD_PB18 (50UL) +#define IOC_PAD_PB19 (51UL) +#define IOC_PAD_PB20 (52UL) +#define IOC_PAD_PB21 (53UL) +#define IOC_PAD_PB22 (54UL) +#define IOC_PAD_PB23 (55UL) +#define IOC_PAD_PB24 (56UL) +#define IOC_PAD_PB25 (57UL) +#define IOC_PAD_PB26 (58UL) +#define IOC_PAD_PB27 (59UL) +#define IOC_PAD_PB28 (60UL) +#define IOC_PAD_PB29 (61UL) +#define IOC_PAD_PB30 (62UL) +#define IOC_PAD_PB31 (63UL) +#define IOC_PAD_PC00 (64UL) +#define IOC_PAD_PC01 (65UL) +#define IOC_PAD_PC02 (66UL) +#define IOC_PAD_PC03 (67UL) +#define IOC_PAD_PC04 (68UL) +#define IOC_PAD_PC05 (69UL) +#define IOC_PAD_PC06 (70UL) +#define IOC_PAD_PC07 (71UL) +#define IOC_PAD_PC08 (72UL) +#define IOC_PAD_PC09 (73UL) +#define IOC_PAD_PC10 (74UL) +#define IOC_PAD_PC11 (75UL) +#define IOC_PAD_PC12 (76UL) +#define IOC_PAD_PC13 (77UL) +#define IOC_PAD_PC14 (78UL) +#define IOC_PAD_PC15 (79UL) +#define IOC_PAD_PC16 (80UL) +#define IOC_PAD_PC17 (81UL) +#define IOC_PAD_PC18 (82UL) +#define IOC_PAD_PC19 (83UL) +#define IOC_PAD_PC20 (84UL) +#define IOC_PAD_PC21 (85UL) +#define IOC_PAD_PC22 (86UL) +#define IOC_PAD_PC23 (87UL) +#define IOC_PAD_PC24 (88UL) +#define IOC_PAD_PC25 (89UL) +#define IOC_PAD_PC26 (90UL) +#define IOC_PAD_PC27 (91UL) +#define IOC_PAD_PC28 (92UL) +#define IOC_PAD_PC29 (93UL) +#define IOC_PAD_PC30 (94UL) +#define IOC_PAD_PC31 (95UL) +#define IOC_PAD_PD00 (96UL) +#define IOC_PAD_PD01 (97UL) +#define IOC_PAD_PD02 (98UL) +#define IOC_PAD_PD03 (99UL) +#define IOC_PAD_PD04 (100UL) +#define IOC_PAD_PD05 (101UL) +#define IOC_PAD_PD06 (102UL) +#define IOC_PAD_PD07 (103UL) +#define IOC_PAD_PD08 (104UL) +#define IOC_PAD_PD09 (105UL) +#define IOC_PAD_PD10 (106UL) +#define IOC_PAD_PD11 (107UL) +#define IOC_PAD_PD12 (108UL) +#define IOC_PAD_PD13 (109UL) +#define IOC_PAD_PD14 (110UL) +#define IOC_PAD_PD15 (111UL) +#define IOC_PAD_PD16 (112UL) +#define IOC_PAD_PD17 (113UL) +#define IOC_PAD_PD18 (114UL) +#define IOC_PAD_PD19 (115UL) +#define IOC_PAD_PD20 (116UL) +#define IOC_PAD_PD21 (117UL) +#define IOC_PAD_PD22 (118UL) +#define IOC_PAD_PD23 (119UL) +#define IOC_PAD_PD24 (120UL) +#define IOC_PAD_PD25 (121UL) +#define IOC_PAD_PD26 (122UL) +#define IOC_PAD_PD27 (123UL) +#define IOC_PAD_PD28 (124UL) +#define IOC_PAD_PD29 (125UL) +#define IOC_PAD_PD30 (126UL) +#define IOC_PAD_PD31 (127UL) +#define IOC_PAD_PE00 (128UL) +#define IOC_PAD_PE01 (129UL) +#define IOC_PAD_PE02 (130UL) +#define IOC_PAD_PE03 (131UL) +#define IOC_PAD_PE04 (132UL) +#define IOC_PAD_PE05 (133UL) +#define IOC_PAD_PE06 (134UL) +#define IOC_PAD_PE07 (135UL) +#define IOC_PAD_PE08 (136UL) +#define IOC_PAD_PE09 (137UL) +#define IOC_PAD_PE10 (138UL) +#define IOC_PAD_PE11 (139UL) +#define IOC_PAD_PE12 (140UL) +#define IOC_PAD_PE13 (141UL) +#define IOC_PAD_PE14 (142UL) +#define IOC_PAD_PE15 (143UL) +#define IOC_PAD_PE16 (144UL) +#define IOC_PAD_PE17 (145UL) +#define IOC_PAD_PE18 (146UL) +#define IOC_PAD_PE19 (147UL) +#define IOC_PAD_PE20 (148UL) +#define IOC_PAD_PE21 (149UL) +#define IOC_PAD_PE22 (150UL) +#define IOC_PAD_PE23 (151UL) +#define IOC_PAD_PE24 (152UL) +#define IOC_PAD_PE25 (153UL) +#define IOC_PAD_PE26 (154UL) +#define IOC_PAD_PE27 (155UL) +#define IOC_PAD_PE28 (156UL) +#define IOC_PAD_PE29 (157UL) +#define IOC_PAD_PE30 (158UL) +#define IOC_PAD_PE31 (159UL) +#define IOC_PAD_PF00 (160UL) +#define IOC_PAD_PF01 (161UL) +#define IOC_PAD_PF02 (162UL) +#define IOC_PAD_PF03 (163UL) +#define IOC_PAD_PF04 (164UL) +#define IOC_PAD_PF05 (165UL) +#define IOC_PAD_PF06 (166UL) +#define IOC_PAD_PF07 (167UL) +#define IOC_PAD_PF08 (168UL) +#define IOC_PAD_PF09 (169UL) +#define IOC_PAD_PF10 (170UL) +#define IOC_PAD_PX00 (416UL) +#define IOC_PAD_PX01 (417UL) +#define IOC_PAD_PX02 (418UL) +#define IOC_PAD_PX03 (419UL) +#define IOC_PAD_PX04 (420UL) +#define IOC_PAD_PX05 (421UL) +#define IOC_PAD_PX06 (422UL) +#define IOC_PAD_PX07 (423UL) +#define IOC_PAD_PX08 (424UL) +#define IOC_PAD_PX09 (425UL) +#define IOC_PAD_PX10 (426UL) +#define IOC_PAD_PX11 (427UL) +#define IOC_PAD_PY00 (448UL) +#define IOC_PAD_PY01 (449UL) +#define IOC_PAD_PY02 (450UL) +#define IOC_PAD_PY03 (451UL) +#define IOC_PAD_PY04 (452UL) +#define IOC_PAD_PY05 (453UL) +#define IOC_PAD_PY06 (454UL) +#define IOC_PAD_PY07 (455UL) +#define IOC_PAD_PY08 (456UL) +#define IOC_PAD_PY09 (457UL) +#define IOC_PAD_PY10 (458UL) +#define IOC_PAD_PY11 (459UL) +#define IOC_PAD_PZ00 (480UL) +#define IOC_PAD_PZ01 (481UL) +#define IOC_PAD_PZ02 (482UL) +#define IOC_PAD_PZ03 (483UL) +#define IOC_PAD_PZ04 (484UL) +#define IOC_PAD_PZ05 (485UL) +#define IOC_PAD_PZ06 (486UL) +#define IOC_PAD_PZ07 (487UL) +#define IOC_PAD_PZ08 (488UL) +#define IOC_PAD_PZ09 (489UL) +#define IOC_PAD_PZ10 (490UL) +#define IOC_PAD_PZ11 (491UL) + + +#endif /* HPM_IOC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h new file mode 100644 index 0000000000..5c123a6372 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h @@ -0,0 +1,1789 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOMUX_H +#define HPM_IOMUX_H + +/* IOC_PA00_FUNC_CTL function mux definitions */ +#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA00_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA00_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA00_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA00_FUNC_CTL_CAM0_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA01_FUNC_CTL function mux definitions */ +#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA01_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA01_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA01_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA01_FUNC_CTL_CAM0_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA02_FUNC_CTL function mux definitions */ +#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA02_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA02_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA02_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA02_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA02_FUNC_CTL_CAM0_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA03_FUNC_CTL function mux definitions */ +#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA03_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA03_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA03_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA03_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA03_FUNC_CTL_CAM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA04_FUNC_CTL function mux definitions */ +#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA04_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA04_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA04_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA04_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA04_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA04_FUNC_CTL_CAM0_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA05_FUNC_CTL function mux definitions */ +#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA05_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA05_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA05_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA05_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA05_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA05_FUNC_CTL_CAM0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA06_FUNC_CTL function mux definitions */ +#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA06_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA06_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA06_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA06_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA06_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA06_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA06_FUNC_CTL_CAM0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA07_FUNC_CTL function mux definitions */ +#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA07_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA07_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA07_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA07_FUNC_CTL_CAM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA07_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA08_FUNC_CTL function mux definitions */ +#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA08_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA08_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA08_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA08_FUNC_CTL_CAM0_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA09_FUNC_CTL function mux definitions */ +#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA09_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA09_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA09_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA09_FUNC_CTL_CAM0_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA09_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA10_FUNC_CTL function mux definitions */ +#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA10_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA10_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA10_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA10_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA10_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA10_FUNC_CTL_CAM0_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA11_FUNC_CTL function mux definitions */ +#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA11_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA11_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA11_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA11_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA11_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA11_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA11_FUNC_CTL_CAM0_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA12_FUNC_CTL function mux definitions */ +#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA12_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA12_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA12_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA12_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA12_FUNC_CTL_DIS0_B_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA12_FUNC_CTL_CAM0_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA13_FUNC_CTL function mux definitions */ +#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA13_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA13_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA13_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA13_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA13_FUNC_CTL_DIS0_B_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA13_FUNC_CTL_CAM0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA14_FUNC_CTL function mux definitions */ +#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA14_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA14_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA14_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA14_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA14_FUNC_CTL_I2S2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA14_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA14_FUNC_CTL_DIS0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA15_FUNC_CTL function mux definitions */ +#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA15_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA15_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA15_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA15_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA15_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA15_FUNC_CTL_I2S2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA15_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA15_FUNC_CTL_DIS0_EN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA16_FUNC_CTL function mux definitions */ +#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA16_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA16_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA16_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA16_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA16_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA16_FUNC_CTL_DIS0_B_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA16_FUNC_CTL_CAM0_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA17_FUNC_CTL function mux definitions */ +#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA17_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA17_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA17_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA17_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA17_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA17_FUNC_CTL_DIS0_B_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA17_FUNC_CTL_CAM0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA18_FUNC_CTL function mux definitions */ +#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA18_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA18_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA18_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA18_FUNC_CTL_DIS0_B_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA18_FUNC_CTL_CAM0_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA19_FUNC_CTL function mux definitions */ +#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA19_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA19_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA19_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA19_FUNC_CTL_I2S2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA19_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA19_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA19_FUNC_CTL_DIS0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA20_FUNC_CTL function mux definitions */ +#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA20_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA20_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA20_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA20_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA20_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA20_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA20_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA20_FUNC_CTL_DIS0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA21_FUNC_CTL function mux definitions */ +#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA21_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA21_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA21_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA21_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA21_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA21_FUNC_CTL_DIS0_R_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA22_FUNC_CTL function mux definitions */ +#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA22_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA22_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA22_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA22_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA22_FUNC_CTL_DIS0_G_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA22_FUNC_CTL_CAM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA23_FUNC_CTL function mux definitions */ +#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA23_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA23_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA23_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA23_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA23_FUNC_CTL_DIS0_G_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA23_FUNC_CTL_CAM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA24_FUNC_CTL function mux definitions */ +#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA24_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA24_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA24_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA24_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA24_FUNC_CTL_DIS0_G_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA24_FUNC_CTL_CAM0_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA25_FUNC_CTL function mux definitions */ +#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA25_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA25_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA25_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA25_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA25_FUNC_CTL_DIS0_G_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA25_FUNC_CTL_CAM0_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA26_FUNC_CTL function mux definitions */ +#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA26_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA26_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA26_FUNC_CTL_I2S3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA26_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA26_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA26_FUNC_CTL_DIS0_R_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA27_FUNC_CTL function mux definitions */ +#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA27_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA27_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA27_FUNC_CTL_I2S3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA27_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PA27_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA27_FUNC_CTL_DIS0_R_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA28_FUNC_CTL function mux definitions */ +#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA28_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA28_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA28_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA28_FUNC_CTL_DIS0_R_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA28_FUNC_CTL_CAM0_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA29_FUNC_CTL function mux definitions */ +#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA29_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA29_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA29_FUNC_CTL_I2S2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA29_FUNC_CTL_I2S3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA29_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA29_FUNC_CTL_DIS0_G_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA29_FUNC_CTL_CAM0_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA30_FUNC_CTL function mux definitions */ +#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA30_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA30_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA30_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PA30_FUNC_CTL_I2S3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA30_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA30_FUNC_CTL_DIS0_G_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA30_FUNC_CTL_CAM0_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA31_FUNC_CTL function mux definitions */ +#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA31_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA31_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA31_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA31_FUNC_CTL_I2S3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PA31_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA31_FUNC_CTL_DIS0_R_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB00_FUNC_CTL function mux definitions */ +#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB00_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB00_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB00_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB00_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB00_FUNC_CTL_I2S3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PB00_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB00_FUNC_CTL_DIS0_R_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB01_FUNC_CTL function mux definitions */ +#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB01_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB01_FUNC_CTL_I2S2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB01_FUNC_CTL_I2S3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PB01_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB01_FUNC_CTL_DIS0_G_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB01_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB02_FUNC_CTL function mux definitions */ +#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB02_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB02_FUNC_CTL_I2S2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB02_FUNC_CTL_I2S3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PB02_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB02_FUNC_CTL_DIS0_B_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB03_FUNC_CTL function mux definitions */ +#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB03_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB03_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PB03_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB03_FUNC_CTL_DIS0_R_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB03_FUNC_CTL_CAM1_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB04_FUNC_CTL function mux definitions */ +#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB04_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB04_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB04_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB04_FUNC_CTL_I2S3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB04_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PB04_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB04_FUNC_CTL_DIS0_R_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB04_FUNC_CTL_CAM1_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB05_FUNC_CTL function mux definitions */ +#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB05_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB05_FUNC_CTL_I2S3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB05_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PB05_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB05_FUNC_CTL_DIS0_B_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB05_FUNC_CTL_CAM1_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB06_FUNC_CTL function mux definitions */ +#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB06_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB06_FUNC_CTL_I2S3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB06_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB06_FUNC_CTL_DIS0_G_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB06_FUNC_CTL_CAM1_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PB06_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB07_FUNC_CTL function mux definitions */ +#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB07_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB07_FUNC_CTL_I2S3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB07_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB07_FUNC_CTL_DIS0_B_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB07_FUNC_CTL_CAM1_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PB07_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB08_FUNC_CTL function mux definitions */ +#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB08_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB08_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB08_FUNC_CTL_I2S3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB08_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PB08_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB08_FUNC_CTL_CAM1_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB09_FUNC_CTL function mux definitions */ +#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB09_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB09_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB09_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB09_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB09_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PB09_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB09_FUNC_CTL_CAM1_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB10_FUNC_CTL function mux definitions */ +#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB10_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB10_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB10_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB10_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB10_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB10_FUNC_CTL_CAM1_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB11_FUNC_CTL function mux definitions */ +#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB11_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB11_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB11_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB11_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB11_FUNC_CTL_I2S3_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB11_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB11_FUNC_CTL_CAM1_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB12_FUNC_CTL function mux definitions */ +#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB12_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB12_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB12_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB12_FUNC_CTL_I2S3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB12_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PB12_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB12_FUNC_CTL_CAM1_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB13_FUNC_CTL function mux definitions */ +#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB13_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB13_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB13_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB13_FUNC_CTL_I2S3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB13_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB13_FUNC_CTL_CAM1_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB14_FUNC_CTL function mux definitions */ +#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB14_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB14_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB14_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB14_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB14_FUNC_CTL_I2S3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PB14_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB14_FUNC_CTL_CAM1_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB15_FUNC_CTL function mux definitions */ +#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB15_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB15_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB15_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB15_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PB15_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB15_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB16_FUNC_CTL function mux definitions */ +#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB16_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB16_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PB16_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB16_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB17_FUNC_CTL function mux definitions */ +#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB17_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB17_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB17_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PB17_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB18_FUNC_CTL function mux definitions */ +#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB18_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB18_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB18_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PB18_FUNC_CTL_DRAM_DQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB18_FUNC_CTL_XPI_SLV_ADQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB19_FUNC_CTL function mux definitions */ +#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB19_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB19_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB19_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB19_FUNC_CTL_DRAM_DQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB19_FUNC_CTL_XPI_SLV_ADQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB20_FUNC_CTL function mux definitions */ +#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB20_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB20_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB20_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB20_FUNC_CTL_DRAM_DQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB20_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB20_FUNC_CTL_XPI_SLV_ADQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB21_FUNC_CTL function mux definitions */ +#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB21_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB21_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB21_FUNC_CTL_DRAM_DQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB21_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB21_FUNC_CTL_XPI_SLV_ADQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB22_FUNC_CTL function mux definitions */ +#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB22_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB22_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB22_FUNC_CTL_DRAM_DQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB22_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB22_FUNC_CTL_XPI_SLV_ADQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB23_FUNC_CTL function mux definitions */ +#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB23_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB23_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB23_FUNC_CTL_DRAM_DQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB23_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB23_FUNC_CTL_XPI_SLV_ADQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB24_FUNC_CTL function mux definitions */ +#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB24_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB24_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB24_FUNC_CTL_DRAM_DQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB24_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB24_FUNC_CTL_XPI_SLV_ADQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB25_FUNC_CTL function mux definitions */ +#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB25_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB25_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB25_FUNC_CTL_DRAM_DQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB25_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB25_FUNC_CTL_XPI_SLV_ADQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB26_FUNC_CTL function mux definitions */ +#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB26_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB26_FUNC_CTL_DRAM_DQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB26_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB26_FUNC_CTL_XPI_SLV_ADQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB27_FUNC_CTL function mux definitions */ +#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB27_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB27_FUNC_CTL_DRAM_DQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB27_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB27_FUNC_CTL_XPI_SLV_ADQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB28_FUNC_CTL function mux definitions */ +#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB28_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB28_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB28_FUNC_CTL_DRAM_DQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB28_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB28_FUNC_CTL_XPI_SLV_ADQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB29_FUNC_CTL function mux definitions */ +#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB29_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB29_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB29_FUNC_CTL_DRAM_DQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB29_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB29_FUNC_CTL_XPI_SLV_ADQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PB30_FUNC_CTL function mux definitions */ +#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB30_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB30_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB30_FUNC_CTL_DRAM_DQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB30_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB31_FUNC_CTL function mux definitions */ +#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB31_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB31_FUNC_CTL_DRAM_DQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PB31_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB31_FUNC_CTL_XPI_SLV_ADQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC00_FUNC_CTL function mux definitions */ +#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC00_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC00_FUNC_CTL_DRAM_DQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC00_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC00_FUNC_CTL_XPI_SLV_ADQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC01_FUNC_CTL function mux definitions */ +#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC01_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC01_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC01_FUNC_CTL_DRAM_DQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC01_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC01_FUNC_CTL_XPI_SLV_ERR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC02_FUNC_CTL function mux definitions */ +#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC02_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC02_FUNC_CTL_DRAM_DM_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC02_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC02_FUNC_CTL_XPI_SLV_ADQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC03_FUNC_CTL function mux definitions */ +#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC03_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC03_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC03_FUNC_CTL_DRAM_DM_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC03_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC03_FUNC_CTL_XPI_SLV_ADQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC04_FUNC_CTL function mux definitions */ +#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC04_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC04_FUNC_CTL_DRAM_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC04_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC04_FUNC_CTL_XPI_SLV_ADQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC04_FUNC_CTL_UTMI_CFG_ADDR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC05_FUNC_CTL function mux definitions */ +#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC05_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC05_FUNC_CTL_DRAM_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC05_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC05_FUNC_CTL_XPI_SLV_ADQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC05_FUNC_CTL_UTMI_CFG_DDIR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC06_FUNC_CTL function mux definitions */ +#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC06_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC06_FUNC_CTL_DRAM_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC06_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC06_FUNC_CTL_XPI_SLV_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC06_FUNC_CTL_UTMI_CFG_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC07_FUNC_CTL function mux definitions */ +#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC07_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC07_FUNC_CTL_DRAM_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC07_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC07_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC07_FUNC_CTL_XPI_SLV_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC08_FUNC_CTL function mux definitions */ +#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC08_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC08_FUNC_CTL_DRAM_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC08_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC08_FUNC_CTL_ETH1_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC08_FUNC_CTL_XPI_SLV_ADQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC08_FUNC_CTL_UTMI_CFG_ADDR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC09_FUNC_CTL function mux definitions */ +#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC09_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC09_FUNC_CTL_DRAM_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC09_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC09_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC09_FUNC_CTL_ETH1_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC09_FUNC_CTL_UTMI_CFG_REN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC10_FUNC_CTL function mux definitions */ +#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC10_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC10_FUNC_CTL_DRAM_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC10_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC10_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC10_FUNC_CTL_XPI_SLV_ADQ_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC10_FUNC_CTL_UTMI_CFG_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC11_FUNC_CTL function mux definitions */ +#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC11_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC11_FUNC_CTL_DRAM_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC11_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC11_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC11_FUNC_CTL_XPI_SLV_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC11_FUNC_CTL_UTMI_CFG_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC12_FUNC_CTL function mux definitions */ +#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC12_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC12_FUNC_CTL_DRAM_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC12_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC12_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC12_FUNC_CTL_XPI_SLV_ADQ_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC13_FUNC_CTL function mux definitions */ +#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC13_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC13_FUNC_CTL_DRAM_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC13_FUNC_CTL_ETH1_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC13_FUNC_CTL_XPI_SLV_ADQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC13_FUNC_CTL_UTMI_CFG_ADDR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC14_FUNC_CTL function mux definitions */ +#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC14_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC14_FUNC_CTL_DRAM_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC14_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC14_FUNC_CTL_TRGM3_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC14_FUNC_CTL_ETH1_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC14_FUNC_CTL_UTMI_CFG_WEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC15_FUNC_CTL function mux definitions */ +#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC15_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC15_FUNC_CTL_DRAM_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC15_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC15_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC15_FUNC_CTL_XPI_SLV_RDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC15_FUNC_CTL_UTMI_CFG_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC16_FUNC_CTL function mux definitions */ +#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC16_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC16_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC16_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC16_FUNC_CTL_TRGM2_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC16_FUNC_CTL_XPI_SLV_ADQ_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC16_FUNC_CTL_UTMI_CFG_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC17_FUNC_CTL function mux definitions */ +#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC17_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC17_FUNC_CTL_DRAM_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC17_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC17_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC17_FUNC_CTL_XPI_SLV_ADQ_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC18_FUNC_CTL function mux definitions */ +#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC18_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC18_FUNC_CTL_DRAM_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC18_FUNC_CTL_TRGM3_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC18_FUNC_CTL_ETH1_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC18_FUNC_CTL_XPI_SLV_ADQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC18_FUNC_CTL_UTMI_CFG_ADDR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC19_FUNC_CTL function mux definitions */ +#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC19_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC19_FUNC_CTL_DRAM_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC19_FUNC_CTL_XPI1_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC19_FUNC_CTL_TRGM3_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC19_FUNC_CTL_ETH1_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC19_FUNC_CTL_UTMI_CFG_RST_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC20_FUNC_CTL function mux definitions */ +#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC20_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC20_FUNC_CTL_DRAM_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC20_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC20_FUNC_CTL_TRGM3_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC20_FUNC_CTL_XPI_SLV_ADQ_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC20_FUNC_CTL_UTMI_CFG_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC21_FUNC_CTL function mux definitions */ +#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC21_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC21_FUNC_CTL_DRAM_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC21_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC21_FUNC_CTL_TRGM2_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC21_FUNC_CTL_XPI_SLV_ADQ_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC21_FUNC_CTL_UTMI_CFG_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC22_FUNC_CTL function mux definitions */ +#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC22_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC22_FUNC_CTL_DRAM_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC22_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC22_FUNC_CTL_TRGM2_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC22_FUNC_CTL_XPI_SLV_ADQ_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC23_FUNC_CTL function mux definitions */ +#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC23_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC23_FUNC_CTL_DRAM_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC23_FUNC_CTL_TRGM3_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC23_FUNC_CTL_ETH1_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC23_FUNC_CTL_XPI_SLV_ADQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC23_FUNC_CTL_UTMI_CFG_ADDR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC24_FUNC_CTL function mux definitions */ +#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC24_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC24_FUNC_CTL_DRAM_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC24_FUNC_CTL_TRGM3_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC24_FUNC_CTL_ETH1_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC24_FUNC_CTL_XPI_SLV_ADQ_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC24_FUNC_CTL_UTMI_CFG_ADDR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC25_FUNC_CTL function mux definitions */ +#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC25_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC25_FUNC_CTL_DRAM_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC25_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC25_FUNC_CTL_TRGM2_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC25_FUNC_CTL_XPI_SLV_ADQ_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) +#define IOC_PC25_FUNC_CTL_UTMI_CFG_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC26_FUNC_CTL function mux definitions */ +#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC26_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC26_FUNC_CTL_DRAM_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC26_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC26_FUNC_CTL_TRGM2_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC26_FUNC_CTL_XPI_SLV_ADQ_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) + +/* IOC_PC27_FUNC_CTL function mux definitions */ +#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC27_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC27_FUNC_CTL_DRAM_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC27_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC27_FUNC_CTL_ETH1_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC27_FUNC_CTL_UTMI_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC28_FUNC_CTL function mux definitions */ +#define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC28_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC28_FUNC_CTL_DRAM_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC28_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC28_FUNC_CTL_ETH1_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC28_FUNC_CTL_UTMI_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC29_FUNC_CTL function mux definitions */ +#define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC29_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC29_FUNC_CTL_DRAM_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC29_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC29_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC29_FUNC_CTL_ETH1_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PC29_FUNC_CTL_UTMI_DM_PULLDOWN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC30_FUNC_CTL function mux definitions */ +#define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC30_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC30_FUNC_CTL_DRAM_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC30_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC30_FUNC_CTL_TRGM2_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC30_FUNC_CTL_UTMI_OP_MOD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PC31_FUNC_CTL function mux definitions */ +#define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC31_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC31_FUNC_CTL_DRAM_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PC31_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PC31_FUNC_CTL_PWM2_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC31_FUNC_CTL_UTMI_LINE_STAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD00_FUNC_CTL function mux definitions */ +#define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD00_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD00_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD00_FUNC_CTL_DRAM_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD00_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD00_FUNC_CTL_ETH1_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD00_FUNC_CTL_UTMI_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD01_FUNC_CTL function mux definitions */ +#define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD01_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD01_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD01_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD01_FUNC_CTL_DRAM_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD01_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD01_FUNC_CTL_ETH1_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD01_FUNC_CTL_UTMI_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD02_FUNC_CTL function mux definitions */ +#define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD02_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD02_FUNC_CTL_DRAM_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD02_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD02_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD02_FUNC_CTL_ETH1_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD02_FUNC_CTL_UTMI_DP_PULLDOWN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD03_FUNC_CTL function mux definitions */ +#define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD03_FUNC_CTL_DRAM_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD03_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD03_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD03_FUNC_CTL_UTMI_OP_MOD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD04_FUNC_CTL function mux definitions */ +#define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD04_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD04_FUNC_CTL_DRAM_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD04_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD04_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD04_FUNC_CTL_UTMI_LINE_STAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD05_FUNC_CTL function mux definitions */ +#define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD05_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD05_FUNC_CTL_DRAM_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD05_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD05_FUNC_CTL_ETH1_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD05_FUNC_CTL_UTMI_FSS_MOD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD06_FUNC_CTL function mux definitions */ +#define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD06_FUNC_CTL_DRAM_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD06_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD06_FUNC_CTL_UTMI_SESS_VLD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD07_FUNC_CTL function mux definitions */ +#define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD07_FUNC_CTL_DRAM_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD07_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD07_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD07_FUNC_CTL_UTMI_SUSPDM IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD08_FUNC_CTL function mux definitions */ +#define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD08_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD08_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD08_FUNC_CTL_DRAM_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD08_FUNC_CTL_XPI1_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD08_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD08_FUNC_CTL_ETH1_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD08_FUNC_CTL_UTMI_H_DISCNT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD09_FUNC_CTL function mux definitions */ +#define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD09_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD09_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD09_FUNC_CTL_DRAM_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD09_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD09_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD09_FUNC_CTL_UTMI_VBUS_VLD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD10_FUNC_CTL function mux definitions */ +#define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD10_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD10_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD10_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD10_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD10_FUNC_CTL_DRAM_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD10_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD10_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD10_FUNC_CTL_UTMI_TERM_SEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD11_FUNC_CTL function mux definitions */ +#define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD11_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD11_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD11_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD11_FUNC_CTL_PWM3_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD11_FUNC_CTL_ETH1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD11_FUNC_CTL_UTMI_TXBST_EN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD12_FUNC_CTL function mux definitions */ +#define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD12_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD12_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD12_FUNC_CTL_DRAM_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD12_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD12_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD12_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD12_FUNC_CTL_UTMI_TEST_BIST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD13_FUNC_CTL function mux definitions */ +#define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD13_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD13_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PD13_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD13_FUNC_CTL_DRAM_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PD13_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD13_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD13_FUNC_CTL_UTMI_SELF_TEST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD14_FUNC_CTL function mux definitions */ +#define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD14_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD14_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD14_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD14_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD14_FUNC_CTL_PWM3_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD14_FUNC_CTL_ETH1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD14_FUNC_CTL_UTMI_PLL_EN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD15_FUNC_CTL function mux definitions */ +#define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD15_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD15_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD15_FUNC_CTL_PWM2_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD15_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PD15_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PD15_FUNC_CTL_UTMI_RESET IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD16_FUNC_CTL function mux definitions */ +#define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD16_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD16_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD16_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD16_FUNC_CTL_TRGM2_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD16_FUNC_CTL_SDC1_DATA_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD16_FUNC_CTL_ETH1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD16_FUNC_CTL_UTMI_DDIR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD17_FUNC_CTL function mux definitions */ +#define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD17_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD17_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD17_FUNC_CTL_TRGM3_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD17_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD17_FUNC_CTL_ETH1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD17_FUNC_CTL_UTMI_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD18_FUNC_CTL function mux definitions */ +#define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD18_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD18_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD18_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD18_FUNC_CTL_TRGM3_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD18_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD18_FUNC_CTL_ETH1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD18_FUNC_CTL_UTMI_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD19_FUNC_CTL function mux definitions */ +#define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD19_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD19_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD19_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD19_FUNC_CTL_TRGM2_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD19_FUNC_CTL_SDC1_DATA_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD19_FUNC_CTL_ETH1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD19_FUNC_CTL_UTMI_RX_ACTIVE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD20_FUNC_CTL function mux definitions */ +#define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD20_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD20_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD20_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD20_FUNC_CTL_TRGM2_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD20_FUNC_CTL_SDC1_DS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD20_FUNC_CTL_ETH1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD20_FUNC_CTL_UTMI_RX_VLD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD21_FUNC_CTL function mux definitions */ +#define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD21_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD21_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD21_FUNC_CTL_TRGM3_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD21_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD21_FUNC_CTL_ETH1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD21_FUNC_CTL_UTMI_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD22_FUNC_CTL function mux definitions */ +#define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD22_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD22_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD22_FUNC_CTL_TRGM3_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD22_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD22_FUNC_CTL_ETH1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD22_FUNC_CTL_UTMI_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD23_FUNC_CTL function mux definitions */ +#define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD23_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD23_FUNC_CTL_TRGM2_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD23_FUNC_CTL_SDC1_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD23_FUNC_CTL_ETH1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD23_FUNC_CTL_UTMI_XCVR_SEL_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD24_FUNC_CTL function mux definitions */ +#define IOC_PD24_FUNC_CTL_GPIO_D_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD24_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD24_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD24_FUNC_CTL_TRGM2_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD24_FUNC_CTL_SDC1_DATA_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD24_FUNC_CTL_ETH1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD24_FUNC_CTL_UTMI_XCVR_SEL_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD25_FUNC_CTL function mux definitions */ +#define IOC_PD25_FUNC_CTL_GPIO_D_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD25_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PD25_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD25_FUNC_CTL_TRGM2_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD25_FUNC_CTL_SDC1_DATA_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD25_FUNC_CTL_ETH1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD25_FUNC_CTL_UTMI_RX_VLDH IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD26_FUNC_CTL function mux definitions */ +#define IOC_PD26_FUNC_CTL_GPIO_D_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD26_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD26_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD26_FUNC_CTL_TRGM3_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD26_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD26_FUNC_CTL_ETH1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD26_FUNC_CTL_UTMI_TX_VLDH IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD27_FUNC_CTL function mux definitions */ +#define IOC_PD27_FUNC_CTL_GPIO_D_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD27_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD27_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD27_FUNC_CTL_TRGM3_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD27_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD27_FUNC_CTL_ETH1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD27_FUNC_CTL_UTMI_TX_VLD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD28_FUNC_CTL function mux definitions */ +#define IOC_PD28_FUNC_CTL_GPIO_D_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD28_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD28_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD28_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD28_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD28_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD28_FUNC_CTL_UTMI_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD29_FUNC_CTL function mux definitions */ +#define IOC_PD29_FUNC_CTL_GPIO_D_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD29_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD29_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD29_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD29_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PD29_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD29_FUNC_CTL_UTMI_CLK60_TO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD30_FUNC_CTL function mux definitions */ +#define IOC_PD30_FUNC_CTL_GPIO_D_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD30_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD30_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD30_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD30_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD30_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD30_FUNC_CTL_UTMI_TX_RDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PD31_FUNC_CTL function mux definitions */ +#define IOC_PD31_FUNC_CTL_GPIO_D_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PD31_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PD31_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PD31_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PD31_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PD31_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PD31_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PD31_FUNC_CTL_UTMI_RX_ERR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE00_FUNC_CTL function mux definitions */ +#define IOC_PE00_FUNC_CTL_GPIO_E_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE00_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE00_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE00_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE00_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE00_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE00_FUNC_CTL_UTMI_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE01_FUNC_CTL function mux definitions */ +#define IOC_PE01_FUNC_CTL_GPIO_E_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE01_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE01_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE01_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE01_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE01_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE01_FUNC_CTL_UTMI_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE02_FUNC_CTL function mux definitions */ +#define IOC_PE02_FUNC_CTL_GPIO_E_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE02_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE02_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE02_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE02_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE02_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE02_FUNC_CTL_UTMI_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE03_FUNC_CTL function mux definitions */ +#define IOC_PE03_FUNC_CTL_GPIO_E_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE03_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE03_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE03_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE03_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE03_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE03_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE03_FUNC_CTL_UTMI_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE04_FUNC_CTL function mux definitions */ +#define IOC_PE04_FUNC_CTL_GPIO_E_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE04_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE04_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE04_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE04_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE04_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE04_FUNC_CTL_UTMI_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE05_FUNC_CTL function mux definitions */ +#define IOC_PE05_FUNC_CTL_GPIO_E_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE05_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE05_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE05_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE05_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE05_FUNC_CTL_UTMI_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE06_FUNC_CTL function mux definitions */ +#define IOC_PE06_FUNC_CTL_GPIO_E_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE06_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE06_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE06_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE06_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE06_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE06_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE06_FUNC_CTL_UTMI_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE07_FUNC_CTL function mux definitions */ +#define IOC_PE07_FUNC_CTL_GPIO_E_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE07_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE07_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE07_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE07_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE07_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE07_FUNC_CTL_UTMI_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE08_FUNC_CTL function mux definitions */ +#define IOC_PE08_FUNC_CTL_GPIO_E_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE08_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE08_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE08_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE08_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE08_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE08_FUNC_CTL_UTMI_RX_DM IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE09_FUNC_CTL function mux definitions */ +#define IOC_PE09_FUNC_CTL_GPIO_E_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE09_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE09_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE09_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE09_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE09_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE09_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE09_FUNC_CTL_UTMI_RX_DP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE10_FUNC_CTL function mux definitions */ +#define IOC_PE10_FUNC_CTL_GPIO_E_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE10_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE10_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE10_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE10_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE10_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE10_FUNC_CTL_ETH1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE10_FUNC_CTL_UTMI_RX_RCV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE11_FUNC_CTL function mux definitions */ +#define IOC_PE11_FUNC_CTL_GPIO_E_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE11_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE11_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE11_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE11_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE11_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE11_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE11_FUNC_CTL_ETH1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE11_FUNC_CTL_UTMI_TX_SE0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE12_FUNC_CTL function mux definitions */ +#define IOC_PE12_FUNC_CTL_GPIO_E_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE12_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE12_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE12_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE12_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE12_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE12_FUNC_CTL_UTMI_TXEN_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE13_FUNC_CTL function mux definitions */ +#define IOC_PE13_FUNC_CTL_GPIO_E_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE13_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE13_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE13_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE13_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PE13_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE13_FUNC_CTL_UTMI_TX_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE14_FUNC_CTL function mux definitions */ +#define IOC_PE14_FUNC_CTL_GPIO_E_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE14_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE14_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE14_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE14_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE14_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE14_FUNC_CTL_ETH1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE14_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE15_FUNC_CTL function mux definitions */ +#define IOC_PE15_FUNC_CTL_GPIO_E_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE15_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE15_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE15_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE15_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE15_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE15_FUNC_CTL_ETH1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE15_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE16_FUNC_CTL function mux definitions */ +#define IOC_PE16_FUNC_CTL_GPIO_E_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE16_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE16_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE16_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE16_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE16_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE16_FUNC_CTL_ETH1_REFCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE16_FUNC_CTL_UTMI_D16_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(31) + +/* IOC_PE17_FUNC_CTL function mux definitions */ +#define IOC_PE17_FUNC_CTL_GPIO_E_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE17_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE17_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE17_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE17_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE17_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE17_FUNC_CTL_ETH1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE17_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE18_FUNC_CTL function mux definitions */ +#define IOC_PE18_FUNC_CTL_GPIO_E_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE18_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE18_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE18_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE18_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE18_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE18_FUNC_CTL_ETH1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE18_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE19_FUNC_CTL function mux definitions */ +#define IOC_PE19_FUNC_CTL_GPIO_E_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE19_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE19_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE19_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE19_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE19_FUNC_CTL_ETH1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE19_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE20_FUNC_CTL function mux definitions */ +#define IOC_PE20_FUNC_CTL_GPIO_E_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE20_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE20_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE20_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE20_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE20_FUNC_CTL_ETH1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE20_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE20_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE21_FUNC_CTL function mux definitions */ +#define IOC_PE21_FUNC_CTL_GPIO_E_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE21_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE21_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE21_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE21_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE21_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE21_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PE22_FUNC_CTL function mux definitions */ +#define IOC_PE22_FUNC_CTL_GPIO_E_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE22_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE22_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE22_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE22_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE22_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE22_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE23_FUNC_CTL function mux definitions */ +#define IOC_PE23_FUNC_CTL_GPIO_E_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE23_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE23_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE23_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PE23_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE23_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE23_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE23_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE24_FUNC_CTL function mux definitions */ +#define IOC_PE24_FUNC_CTL_GPIO_E_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE24_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE24_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE24_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE24_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE24_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE24_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE25_FUNC_CTL function mux definitions */ +#define IOC_PE25_FUNC_CTL_GPIO_E_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE25_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE25_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE25_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PE25_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PE25_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE26_FUNC_CTL function mux definitions */ +#define IOC_PE26_FUNC_CTL_GPIO_E_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE26_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE26_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE26_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE26_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE26_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PE26_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE26_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PE27_FUNC_CTL function mux definitions */ +#define IOC_PE27_FUNC_CTL_GPIO_E_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE27_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE27_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE27_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE27_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE27_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE27_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE27_FUNC_CTL_ETH1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE28_FUNC_CTL function mux definitions */ +#define IOC_PE28_FUNC_CTL_GPIO_E_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE28_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PE28_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE28_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE28_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE28_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PE28_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PE28_FUNC_CTL_ETH1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PE29_FUNC_CTL function mux definitions */ +#define IOC_PE29_FUNC_CTL_GPIO_E_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PE29_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE29_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE29_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE29_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE30_FUNC_CTL function mux definitions */ +#define IOC_PE30_FUNC_CTL_GPIO_E_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE30_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE30_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE30_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE30_FUNC_CTL_USB1_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PE31_FUNC_CTL function mux definitions */ +#define IOC_PE31_FUNC_CTL_GPIO_E_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PE31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PE31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PE31_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PE31_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PE31_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PF00_FUNC_CTL function mux definitions */ +#define IOC_PF00_FUNC_CTL_GPIO_F_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF00_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF00_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF00_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF00_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF00_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF00_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF01_FUNC_CTL function mux definitions */ +#define IOC_PF01_FUNC_CTL_GPIO_F_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF01_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF01_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF01_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF01_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF01_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF01_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF02_FUNC_CTL function mux definitions */ +#define IOC_PF02_FUNC_CTL_GPIO_F_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF02_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF02_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PF02_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF02_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF02_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF03_FUNC_CTL function mux definitions */ +#define IOC_PF03_FUNC_CTL_GPIO_F_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF03_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF03_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF03_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF03_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF03_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF03_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PF04_FUNC_CTL function mux definitions */ +#define IOC_PF04_FUNC_CTL_GPIO_F_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF04_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF04_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF04_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF04_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PF05_FUNC_CTL function mux definitions */ +#define IOC_PF05_FUNC_CTL_GPIO_F_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF05_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF05_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF05_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF05_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF05_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PF05_FUNC_CTL_USB1_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PF06_FUNC_CTL function mux definitions */ +#define IOC_PF06_FUNC_CTL_GPIO_F_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF06_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF06_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF06_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF06_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF06_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PF06_FUNC_CTL_USB1_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PF07_FUNC_CTL function mux definitions */ +#define IOC_PF07_FUNC_CTL_GPIO_F_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF07_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF07_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF07_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF07_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PF07_FUNC_CTL_USB1_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PF08_FUNC_CTL function mux definitions */ +#define IOC_PF08_FUNC_CTL_GPIO_F_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF08_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF08_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PF08_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF08_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF08_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PF08_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PF09_FUNC_CTL function mux definitions */ +#define IOC_PF09_FUNC_CTL_GPIO_F_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF09_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PF09_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF09_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF09_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF09_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF09_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PF09_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PF10_FUNC_CTL function mux definitions */ +#define IOC_PF10_FUNC_CTL_GPIO_F_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PF10_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PF10_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PF10_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PF10_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) +#define IOC_PF10_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PX00_FUNC_CTL function mux definitions */ +#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX00_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX00_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX01_FUNC_CTL function mux definitions */ +#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX01_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PX01_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX01_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX02_FUNC_CTL function mux definitions */ +#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX02_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PX03_FUNC_CTL function mux definitions */ +#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX03_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX03_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PX04_FUNC_CTL function mux definitions */ +#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX04_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX04_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PX04_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PX05_FUNC_CTL function mux definitions */ +#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX05_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX05_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX06_FUNC_CTL function mux definitions */ +#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX06_FUNC_CTL_DRAM_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) +#define IOC_PX06_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX07_FUNC_CTL function mux definitions */ +#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX07_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX08_FUNC_CTL function mux definitions */ +#define IOC_PX08_FUNC_CTL_GPIO_X_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX08_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX08_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX09_FUNC_CTL function mux definitions */ +#define IOC_PX09_FUNC_CTL_GPIO_X_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX09_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PX09_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PX10_FUNC_CTL function mux definitions */ +#define IOC_PX10_FUNC_CTL_GPIO_X_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX10_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX11_FUNC_CTL function mux definitions */ +#define IOC_PX11_FUNC_CTL_GPIO_X_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX11_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY00_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY00_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY00_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY01_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY01_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY02_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY02_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY03_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY03_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY04_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY04_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY04_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY04_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY04_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PY04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY05_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY05_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY05_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY05_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PY05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY06_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY07_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) + +/* IOC_PY08_FUNC_CTL function mux definitions */ +#define IOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY08_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY08_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY08_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PY08_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY08_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY09_FUNC_CTL function mux definitions */ +#define IOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY09_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY09_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY09_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) +#define IOC_PY09_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY09_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY10_FUNC_CTL function mux definitions */ +#define IOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY10_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY10_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY10_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY10_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PY10_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PY11_FUNC_CTL function mux definitions */ +#define IOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY11_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY11_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY11_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PY11_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PZ02_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PZ03_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ04_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PZ04_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PZ04_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PZ05_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ06_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PZ06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PZ07_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) + +/* IOC_PZ08_FUNC_CTL function mux definitions */ +#define IOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ08_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ08_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ08_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PZ08_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PZ08_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PZ09_FUNC_CTL function mux definitions */ +#define IOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ09_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ09_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) +#define IOC_PZ09_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PZ09_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PZ10_FUNC_CTL function mux definitions */ +#define IOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ10_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ10_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ10_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ10_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ10_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PZ11_FUNC_CTL function mux definitions */ +#define IOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ11_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ11_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ11_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PZ11_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + + +#endif /* HPM_IOMUX_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.c new file mode 100644 index 0000000000..51b368fa22 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + + +#define ASSERT_ADDR_SIZE(addr, size) do { \ + assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ + assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ + } while (0) + +static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) +{ + register uint32_t i; + register uint32_t next_address = 0; + register uint32_t tmp; + +#define CCTL_VERSION (3U << 18) + + if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { + l1c_cctl_address(address); + while (next_address < (address + size)) { + l1c_cctl_cmd(opcode); + next_address = l1c_cctl_get_address(); + } + } else { + for (i = 0, tmp = 0; tmp < size; i++) { + l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); + tmp += HPM_L1C_CACHELINE_SIZE; + } + } +} + +void l1c_dc_enable(void) +{ + if (!l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); + set_csr(CSR_MCACHE_CTL, +#ifdef L1C_DC_WAROUND_VALUE + HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | +#endif + HPM_MCACHE_CTL_DPREF_EN_MASK + | HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_dc_disable(void) +{ + if (l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_ic_enable(void) +{ + if (!l1c_ic_is_enabled()) { + set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK + | HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_ic_disable(void) +{ + if (l1c_ic_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_fence_i() +{ + __asm("fence.i"); +} + +void l1c_dc_invalidate_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); +} + +void l1c_dc_writeback_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); +} + +void l1c_dc_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); +} + +void l1c_dc_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); +} + +void l1c_dc_writeback(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); +} + +void l1c_dc_flush(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); +} + +void l1c_ic_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); +} + +void l1c_ic_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h new file mode 100644 index 0000000000..d64cd4791f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h @@ -0,0 +1,479 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_L1_CACHE_H +#define _HPM_L1_CACHE_H +#include "riscv/riscv_core.h" +#include "hpm_common.h" + +/** + * + * @brief L1CACHE driver APIs + * @defgroup l1cache_interface L1CACHE driver APIs + * @{ + */ + +/* cache size is 32KB */ +#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) +#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) +#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) +/* cache line size is 64B */ +#define HPM_L1C_CACHELINE_SIZE (64) +/* cache way is 128 */ +#define HPM_L1C_CACHELINES_PER_WAY (128) + +/* mcache_ctl register */ +/* + * Controls if the instruction cache is enabled or not. + * + * 0 I-Cache is disabled + * 1 I-Cache is enabled + */ +#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) +#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) +#define HPM_MCACHE_CTL_IC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) + +/* + * Controls if the data cache is enabled or not. + * + * 0 D-Cache is disabled + * 1 D-Cache is enabled + */ +#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) +#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) +#define HPM_MCACHE_CTL_DC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) + +/* + * Parity/ECC error checking enable control for the instruction cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) +#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_IC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) + +/* + * + * Parity/ECC error checking enable control for the data cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) +#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_DC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. + * It is set to enable CCTL operations to access the ECC codes. This bit + * can be set for injecting ECC errors to test the ECC handler. + * + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) +#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_IC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is + * set to enable CCTL operations to access the ECC codes. This bit can be + * set for injecting + * + * ECC errors to test the ECC handler. + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) +#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_DC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) + +/* + * Enable bit for Superuser-mode and User-mode software to access + * ucctlbeginaddr and ucctlcommand CSRs. + * + * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) +#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) +#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) + +/* + * This bit controls hardware prefetch for instruction fetches to cacheable + * memory regions when I-Cache size is not 0. + * + * 0 Disable hardware prefetch on instruction fetches + * 1 Enable hardware prefetch on instruction fetches + */ +#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) +#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_IPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) + +/* + * This bit controls hardware prefetch for load/store accesses to cacheable + * memory regions when D-Cache size is not 0. + * + * 0 Disable hardware prefetch on load/store memory accesses. + * 1 Enable hardware prefetch on load/store memory accesses. + */ +#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) +#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_DPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) + +/* + * I-Cache miss allocation filling policy Value Meaning + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) +#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) + +/* + * D-Cache miss allocation filling policy + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) +#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) + +/* + * D-Cache Write-Around threshold + * + * 0 Disables streaming. All cacheable write misses allocate a cache line + * according to PMA settings. + * 1 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 4 cache lines. + * 2 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 64 cache lines. + * 3 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 128 cache lines. + */ +#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) +#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) +#define HPM_MCACHE_CTL_DC_WAROUND(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) + +/* CCTL command list */ +#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) +#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) +#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) + +#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) + +#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) + +#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) + +#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) +#define HPM_L1C_CCTL_CMD_FAIL (0UL) + +#ifdef __cplusplus +extern "C" { +#endif +/* get cache control register value */ +__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) +{ + return read_csr(CSR_MCACHE_CTL); +} + +__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; +} + +__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; +} + +/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ +#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) +#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) +#define HPM_MCCTLBEGINADDR_OFFSET(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) +#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) +#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) +#define HPM_MCCTLBEGINADDR_INDEX(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) +#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) +#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) +#define HPM_MCCTLBEGINADDR_WAY(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) + +/* send IX command */ +__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); +} + +/* send command */ +__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) +{ + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) +{ + return read_csr(CSR_MCCTLBEGINADDR); +} + +/* send IX command */ +__attribute__((always_inline)) static inline + void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) +#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) +#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) +#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) +#define HPM_MCCTLDATA_I_TAG_VALID(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) + +#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) +#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) +#define HPM_MCCTLDATA_D_TAG_MESI(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) + +#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) +#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) +#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_TAG(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) + +/* + * @brief Cache control command read address + * + * Send IX read tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] ecc_data ECC value + * @return data read + */ +ATTR_ALWAYS_INLINE static inline + uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + *ecc_data = read_csr(CSR_MECC_CODE); + return read_csr(CSR_MCCTLDATA); +} + +/* + * @brief Cache control command write address + * + * Send IX write tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] data Data to be written + * @param[in] ecc_data ECC of data + */ +ATTR_ALWAYS_INLINE static inline + void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + write_csr(CSR_MCCTLDATA, data); + write_csr(CSR_MECC_CODE, ecc_data); +} + +#define HPM_L1C_CFG_SET_SHIFT (0UL) +#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) +#define HPM_L1C_CFG_WAY_SHIFT (3UL) +#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) +#define HPM_L1C_CFG_SIZE_SHIFT (6UL) +#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) +#define HPM_L1C_CFG_LOCK_SHIFT (9UL) +#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) +#define HPM_L1C_CFG_ECC_SHIFT (10UL) +#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) +#define HPM_L1C_CFG_LMB_SHIFT (12UL) +#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) +#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) +#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) +#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) +#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) +#define HPM_L1C_CFG_SETH_SHIFT (24UL) +#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) + +/** + * @brief Align down based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) + +/** + * @brief Align up based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) + +/** + * @brief Get I-cache configuration + * + * @return I-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) +{ + return read_csr(CSR_MICM_CFG); +} + +/** + * @brief Get D-cache configuration + * + * @return D-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) +{ + return read_csr(CSR_MDCM_CFG); +} + +/* + * @brief D-cache disable + */ +void l1c_dc_disable(void); + +/* + * @brief D-cache enable + */ +void l1c_dc_enable(void); + +/* + * @brief D-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_dc_invalidate(uint32_t address, uint32_t size); + +/* + * @brief D-cache writeback by address + * @param[in] address Start address to be writtenback + * @param[in] size Size of memory to be writtenback + */ +void l1c_dc_writeback(uint32_t address, uint32_t size); + +/* + * @brief D-cache invalidate and writeback by address + * @param[in] address Start address to be invalidated and writtenback + * @param[in] size Size of memory to be invalidted and writtenback + */ +void l1c_dc_flush(uint32_t address, uint32_t size); + +/* + * @brief D-cache fill and lock by address + * @param[in] address Start address to be filled and locked + * @param[in] size Size of memory to be filled and locked + */ +void l1c_dc_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief I-cache disable + */ +void l1c_ic_disable(void); + +/* + * @brief I-cache enable + */ +void l1c_ic_enable(void); + +/* + * @brief I-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_ic_invalidate(uint32_t address, uint32_t size); + +/* + * @brief I-cache fill and lock by address + * @param[in] address Start address to be locked + * @param[in] size Size of memory to be locked + */ +void l1c_ic_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief Invalidate all icache and writeback all dcache + */ +void l1c_fence_i(void); + +/* + * @brief Invalidate all d-cache + */ +void l1c_dc_invalidate_all(void); + +/* + * @brief Writeback all d-cache + */ +void l1c_dc_writeback_all(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_misc.h new file mode 100644 index 0000000000..85cd427d9b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_misc.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MISC_H +#define HPM_MISC_H + +#define ILM_LOCAL_BASE (0x0U) +#define ILM_SIZE_IN_BYTE (0x40000U) +#define DLM_LOCAL_BASE (0x80000U) +#define DLM_SIZE_IN_BYTE (0x40000U) +#define CORE0_ILM_SYSTEM_BASE (0x1000000U) +#define CORE0_DLM_SYSTEM_BASE (0x1040000U) +#define CORE1_ILM_SYSTEM_BASE (0x1180000U) +#define CORE1_DLM_SYSTEM_BASE (0x11C0000U) + +#define ADDRESS_IN_ILM(address) \ + ((ILM_LOCAL_BASE) <= (address)) && \ + ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_DLM(address) \ + ((DLM_LOCAL_BASE) <= (address)) && \ + ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ + ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + +#define ADDRESS_IN_CORE0_ILM_SYSTEM(address) \ + ((CORE0_ILM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_ILM_SYSTEM_BASE + ILM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ + ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + +#define ADDRESS_IN_CORE1_ILM_SYSTEM(address) \ + ((CORE1_ILM_SYSTEM_BASE) <= (address)) && \ + ((CORE1_ILM_SYSTEM_BASE + ILM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_CORE1_DLM_SYSTEM(address) \ + ((CORE1_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE1_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + +#define DLM_TO_SYSTEM(address) \ + (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) +#define ILM_TO_SYSTEM(address) \ + (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) +#define SYSTEM_TO_DLM(address) \ + ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) + +#define HPM_CORE0 (0U) +#define HPM_CORE1 (1U) + +/* map core local memory(DLM/ILM) to system address */ +static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) +{ + uint32_t sys_addr; + if (ADDRESS_IN_ILM(addr)) { + sys_addr = ILM_TO_SYSTEM(addr); + } else if (ADDRESS_IN_DLM(addr)) { + sys_addr = DLM_TO_SYSTEM(addr); + } else { + return addr; + } + if (core_id == HPM_CORE1) { + sys_addr += CORE1_ILM_SYSTEM_BASE - CORE0_ILM_SYSTEM_BASE; + } + + return sys_addr; +} + +/* map system address to core local memory(DLM/ILM) */ +static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) +{ + if (core_id == HPM_CORE1) { + if (ADDRESS_IN_CORE1_DLM_SYSTEM(addr)) { + addr = addr - CORE1_DLM_SYSTEM_BASE + DLM_LOCAL_BASE; + } else if (ADDRESS_IN_CORE1_ILM_SYSTEM(addr)) { + addr = addr - CORE1_ILM_SYSTEM_BASE + ILM_LOCAL_BASE; + } + } else { + if (ADDRESS_IN_CORE0_DLM_SYSTEM(addr)) { + addr = addr - CORE0_DLM_SYSTEM_BASE + DLM_LOCAL_BASE; + } else if (ADDRESS_IN_CORE0_ILM_SYSTEM(addr)) { + addr = addr - CORE0_ILM_SYSTEM_BASE + ILM_LOCAL_BASE; + } + } + + return addr; +} +#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c new file mode 100644 index 0000000000..986bfe88d7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.c @@ -0,0 +1,202 @@ +/* +* Copyright (c) 2021 hpmicro +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_otp_drv.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) +#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ +#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ +#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +void otp_init(void) +{ + +} + +void otp_deinit(void) +{ + +} + +uint32_t otp_read_from_shadow(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP->SHADOW[addr] : HPM_OTPSHW->SHADOW[addr]; + } + + return ret_val; +} + +uint32_t otp_read_from_ip(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + HPM_OTP->ADDR = addr; + HPM_OTP->INT_FLAG = OTP_INT_FLAG_READ_MASK; /* Write-1-Clear */ + HPM_OTP->CMD = OTP_CMD_READ; + while(!IS_HPM_BITMASK_SET(HPM_OTP->INT_FLAG, OTP_INT_FLAG_READ_MASK)) { + } + ret_val = HPM_OTP->DATA; + } + return ret_val; +} + +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((addr >=fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); + + /* Enable 2.5V LDO for FUSE programming */ + uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); + HPM_PCFG->LDO2P5 = reg_val; + //TODO: delay 1ms, wait for design team's update to get a steady bit (bit28 in this reg) + + for (uint32_t i=0; iUNLOCK = OTP_UNLOCK_MAGIC_NUM; + HPM_OTP->FUSE[addr++] = *src++; + */ + HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; + HPM_OTP->ADDR = addr; + HPM_OTP->DATA = *src; + HPM_OTP->INT_FLAG = OTP_INT_FLAG_WRITE_MASK; /* Write-1-Clear */ + HPM_OTP->CMD = OTP_CMD_PROGRAM; + + ++src; + ++addr; + while(!IS_HPM_BITMASK_SET(HPM_OTP->INT_FLAG, OTP_INT_FLAG_WRITE_MASK)) { + + } + + } + /* Disable 2.5V LDO after FUSE programming for saving power */ + HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; + status = status_success; + }while(false); + + return status; +} + +hpm_stat_t otp_reload(otp_region_t region) +{ + hpm_stat_t status = status_invalid_argument; + if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { + HPM_OTP->LOAD_REQ = (uint32_t)region; + HPM_OTP->LOAD_COMP = (uint32_t)region; + while(!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { + + } + status = status_success; + } + + return status; +} + + +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + + +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + + + + +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); + + HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) + | OTP_REGION_STOP_SET(start + num_of_words); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + uint32_t lock_mask = 3U << lock_reg_offset; + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) + >> lock_reg_offset); + + if (lock_opt != otp_no_lock) { + status = otp_write_disallowed; + break; + } + + otp_base->SHADOW[addr] = val; + + status = status_success; + } while (false); + + return status; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h new file mode 100644 index 0000000000..bedd300b95 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_otp_drv.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_OTP_DRV_H +#define HPM_OTP_DRV_H + +/** + * @brief OTP APIs + * @defgroup otp_interface OTP driver APIs + * @{ + */ + +#include "hpm_common.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * @brief OTP region definitions + */ +typedef enum { + otp_region0_mask = 1U, /*!< Address range: [0, 7] */ + otp_region1_mask = 2U, /*!< Address range: [8, 15] */ + otp_region2_mask = 4U, /*!< Address range: [16, 127] */ + otp_region3_mask = 8U, /*!< Address range: user defined */ +}otp_region_t; + +/** + * @brief OTP lock options + */ +typedef enum { + otp_no_lock = 0, + otp_read_only = 1, + otp_permanent_no_lock = 2, + otp_disable_access = 3, + otp_lock_option_max = otp_disable_access, +}otp_lock_option_t; + + +enum +{ + otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), +}; + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +#ifdef __cpluscplus +extern "C" { +#endif + + /** + * @brief Initialize OTP controller + */ + void otp_init(void); + + /** + * @brief De-initialize OTP controller + */ + void otp_deinit(void); + + /** + * @brief Read the OTP word from shadow register + * @param [in] addr OTP word index + * @retval OTP word value + */ + uint32_t otp_read_from_shadow(uint32_t addr); + + /** + * @brief Read the specified OTP word from OTP IP bus + * @param [in] addr OTP word index + * @retval OTP word value + */ + uint32_t otp_read_from_ip(uint32_t addr); + + /** + * @brief Program a word to specified OTP field + * @param [in] addr OTP word index + * @param [in] src Pointer to the data to be programmed + * @param [in] num_of_words Number of words to be programmed, only 1 is allowed + * @return API execution status + */ + hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + + /** + * @brief Reload a OTP region + * @param [in] region OTP region option + * @return API execution status + */ + hpm_stat_t otp_reload(otp_region_t region); + + /** + * @brief Change the Software lock permission + * @param [in] addr OTP word index + * @param [in] lock_option OTP lcok option + * @return API execution status + */ + hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); + + + /** + * @brief OTP lock shadow + * @param [in] addr OTP word index + * @param [in] lock_option OTP lock option + * @return API execution status + */ + hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); + + /** + * @brief Set the configurable region range + * @param [in] start OTP word start index + * @param [in] num_of_words Number of words in configuration region + * @retval status_out_of_range Invalid range + * @retval status_success Operation is successful + */ + hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); + + /** + * @return Write data to OTP shadow register + * @param [in] addr OTP word index + * @param [val] val Data to be written + * @return API execution status + */ + hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); + + +#ifdef __cpluscplus +} +#endif +/** + * @} + */ + + + + +#endif + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_plic_drv.h new file mode 100644 index 0000000000..dc0b95e00e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_plic_drv.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLIC_DRV_H +#define HPM_PLIC_DRV_H + +/** + * @brief PLIC driver APIs + * @defgroup plic_interface PLIC driver APIs + * @{ + */ + +#define HPM_PLIC_TARGET_M_MODE 0 +#define HPM_PLIC_TARGET_S_MODE 1 + +/* Feature Register */ +#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) +#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) +#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) + +/* Priority Register - 32 bits per irq */ +#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) +#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per source */ +#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) +#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 + +/* Enable Register - 0x80 per target */ +#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) +#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + +/* Claim Register - 0x1000 per target */ +#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) +#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if !defined(__ASSEMBLER__) + +/** + * @brief Set plic feature + * + * @param[in] base PLIC base address + * @param[in] feature Specific feature to be set + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) +{ + *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; +} + +/** + * @brief Set plic threshold + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, + uint32_t target, + uint32_t threshold) +{ + volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + + HPM_PLIC_THRESHOLD_OFFSET + + (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +/** + * @brief Set interrupt priority + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * @param[in] priority Priority to be assigned + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, + uint32_t irq, + uint32_t priority) +{ + volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +/** + * @brief Set interrupt pending bit + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); + *current_ptr = (1 << (irq & 0x1F)); +} + +/** + * @brief Enable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be enabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current | (1 << (irq & 0x1F)); + *current_ptr = current; +} + +/** + * @brief Disable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be disabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current & ~((1 << (irq & 0x1F))); + *current_ptr = current; +} + +/** + * @brief Claim interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to claim interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +/** + * @brief Complete interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = irq; +} +#endif /* __ASSEMBLER__ */ +/** + * @} + */ +#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h new file mode 100644 index 0000000000..960ac3207e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PMIC_IOMUX_H +#define HPM_PMIC_IOMUX_H + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY08_FUNC_CTL function mux definitions */ +#define IOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY08_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY09_FUNC_CTL function mux definitions */ +#define IOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY09_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY10_FUNC_CTL function mux definitions */ +#define IOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY10_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY10_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY11_FUNC_CTL function mux definitions */ +#define IOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY11_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY11_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_PMIC_IOMUX_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h new file mode 100644 index 0000000000..10b6c359af --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h @@ -0,0 +1,660 @@ +/* +* Copyright (c) 2021 hpmicro +* +* SPDX-License-Identifier: BSD-3-Clause +* +*/ + +#ifndef HPM_ROMAPI_H +#define HPM_ROMAPI_H + +/** + * @brief ROM APIs + * @defgroup romapi_interface ROM APIs + * @{ + */ + +#include "hpm_common.h" +#include "hpm_otp_drv.h" +#include "hpm_romapi_xpi_def.h" +#include "hpm_romapi_xpi_soc_def.h" +#include "hpm_romapi_xpi_nor_def.h" +#include "hpm_romapi_xpi_ram_def.h" +#include "hpm_sdp_drv.h" + +/* XPI0 base address */ +#define HPM_XPI0_BASE (0xF3040000UL) /**< XPI0 Base address */ +/* XPI0 base pointer */ +#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ +/* XPI1 base address */ +#define HPM_XPI1_BASE (0xF3044000UL) /**< XPI1 Base address */ +/* XPI1 base pointer */ +#define HPM_XPI1 ((XPI_Type *) HPM_XPI1_BASE) /**< XPI1 Base pointer */ + + +/*********************************************************************************************************************** + * + * + * Definitions + * + * + **********************************************************************************************************************/ +/** + * @brief Enter Bootloader API argument + */ +typedef union { + uint32_t U; + struct { + uint32_t index: 8; /**< Image index */ + uint32_t peripheral: 8; /**< Boot peripheral */ + uint32_t src: 8; /**< Boot source */ + uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ + }; +} api_boot_arg_t; + +#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ +#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ +#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ +#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ +#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ +#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ +#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ +#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ + +/** + * @brief OTP driver interface + */ +typedef struct { + /**< OTP driver interface version */ + uint32_t version; + /**< OTP driver interface: init */ + void (*init)(void); + /**< OTP driver interface: deinit */ + void (*deinit)(void); + /**< OTP driver interface: read from shadow */ + uint32_t (*read_from_shadow)(uint32_t addr); + /**< OTP driver interface: read from ip */ + uint32_t (*read_from_ip)(uint32_t addr); + /**< OTP driver interface: program */ + hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + /**< OTP driver interface: reload */ + hpm_stat_t (*reload)(otp_region_t region); + /**< OTP driver interface: lock */ + hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: lock_shadow */ + hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: set_configurable_region */ + hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); + /**< OTP driver interface: write_shadow_register */ + hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); +} otp_driver_interface_t; + +/** + * @brief XPI driver interface + */ +typedef struct { + /**< XPI driver interface: version */ + uint32_t version; + /**< XPI driver interface: get default configuration */ + hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); + /**< XPI driver interface: get default device configuration */ + hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); + /**< XPI driver interface: initialize the XPI using xpi_config */ + hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); + /**< XPI driver interface: configure the AHB buffer */ + hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); + /**< XPI driver interface: configure the device */ + hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); + /**< XPI driver interface: update instruction talbe */ + hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); + /**< XPI driver interface: transfer command/data using block interface */ + hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); + /**< Software reset the XPI controller */ + void (*software_reset)(XPI_Type *base); + /**< XPI driver interface: Check whether IP is idle */ + bool (*is_idle)(XPI_Type *base); + /**< XPI driver interface: update delay line setting */ + void (*update_dllcr)(XPI_Type *base, uint32_t serial_root_clk_freq, uint32_t data_valid_time, xpi_channel_t channel, + uint32_t dly_target); + /**< XPI driver interface: Get absolute address for APB transfer */ + hpm_stat_t (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); +} xpi_driver_interface_t; + +/** + * @brief XPI NOR driver interface + */ +typedef struct { + /**< XPI NOR driver interface: API version */ + uint32_t version; + /**< XPI NOR driver interface: Get FLASH configuration */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + /**< XPI NOR driver interface: initialize FLASH */ + hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Enable write access to FLASH */ + hpm_stat_t (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Get FLASH status register */ + hpm_stat_t (*get_status)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr, + uint16_t *out_status); + /**< XPI NOR driver interface: Wait when FLASH is still busy */ + hpm_stat_t (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: erase a specified FLASH region */ + hpm_stat_t (*erase)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: Erase the whole FLASH */ + hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Erase specified FLASH sector */ + hpm_stat_t (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Erase specified FLASH block */ + hpm_stat_t (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Program data to specified FLASH address */ + hpm_stat_t (*program)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, const uint32_t *src, + uint32_t dst_addr, uint32_t length); + /**< XPI NOR driver interface: read data from specified FLASH address */ + hpm_stat_t (*read)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t *dst, + uint32_t start, uint32_t length); + /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + const uint32_t *src, uint32_t dst_addr, uint32_t length); + /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ + hpm_stat_t (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + + uint32_t reserved0[3]; + + /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ + hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + + /**< XPI NOR driver interface: Get FLASH properties */ + hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); + +} xpi_nor_driver_interface_t; + +/** + * @brief XPI RAM driver interface + */ +typedef struct { + /**< XPI RAM driver interface: API version */ + uint32_t version; + + /**< Get XPI RAM configuration based on cfg_option */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); + + /**< XPI RAM driver interface: Initialize XPI RAM */ + hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); +} xpi_ram_driver_interface_t; + +/** + * @brief SDP API interface + */ +typedef struct { + /**< SDP API interface: API version */ + uint32_t version; + /**< SDP API interface: Initialize IP */ + hpm_stat_t (*sdp_ip_init)(void); + /**< SDP API interface: Deinitialize IP */ + hpm_stat_t (*sdp_ip_deinit)(void); + /**< SDP API interface: Set AES key */ + hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: AES ECB crypto operation */ + hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API interface: AES CBC crypto operation */ + hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, uint8_t iv[16], + const uint8_t *input, uint8_t *output); + /**< SDP API interface: AES CTR crypto operation */ + hpm_stat_t (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, + uint32_t length); + /**< SDP API interface: AES CCM encryption */ + hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *nonce, uint32_t nonce_len, + const uint8_t *aad, uint32_t aad_len, const uint8_t *input, uint8_t *output, + uint8_t *tag, uint32_t tag_len); + /**< SDP API interface: AES CCM Decrypt and verify */ + hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *nonce, + uint32_t nonce_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, + uint8_t *output, const uint8_t *tag, uint32_t tag_len); + /**< SDP API interface: memcpy */ + hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); + /**< SDP API interface: memset */ + hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); + /**< SDP API interface: HASH initialization */ + hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + /**< SDP API interface: HASH update */ + hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + /**< SDP API interface: HASH finish */ + hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); +} sdp_driver_interface_t; + +/** + * @brief Bootloader API table + */ +typedef struct { + /**< Bootloader API table: version */ + const uint32_t version; + /**< Bootloader API table: copyright string address */ + const char *copyright; + /**< Bootloader API table: run_bootloader API */ + const hpm_stat_t (*run_bootloader)(void *arg); + /**< Bootloader API table: otp driver interface address */ + const otp_driver_interface_t *otp_driver_if; + /**< Bootloader API table: xpi driver interface address */ + const xpi_driver_interface_t *xpi_driver_if; + /**< Bootloader API table: xpi nor driver interface address */ + const xpi_nor_driver_interface_t *xpi_nor_driver_if; + /**< Bootloader API table: xpi ram driver interface address */ + const xpi_ram_driver_interface_t *xpi_ram_driver_if; + /**< Bootloader API table: sdp driver interface address */ + const sdp_driver_interface_t *sdp_driver_if; +} bootloader_api_table_t; + +/**< Bootloader API table Root */ +#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t*)0x2001FF00U) + + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * + * + * Enter bootloader Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Eneter specified Boot mode + * @param [in] ctx Enter bootloader context + * @retval status_invalid Invalid parameters were deteced + */ +static inline hpm_stat_t rom_enter_bootloader(void *ctx) +{ + return ROM_API_TABLE_ROOT->run_bootloader(ctx); +} + +/*********************************************************************************************************************** + * + * + * XPI NOR Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Get XPI NOR configuration via cfg_option + * @param [in] base XPI base address + * @param [out] nor_cfg XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, xpi_nor_config_t *nor_cfg, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); +} + +/** + * @brief Initialize XPI NOR based on nor_config + * @param [in] base XPI base address + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); +} + +/** + * @brief Erase specified FLASH region + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI nOR configuration + * @param[in] start Erase address start address + * @param[in] length Region size to be erased + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t start, uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); +} + +/** + * @brief Erase specified FLASH sector in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH sector in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); +} + + +/** + * @brief Erase the whole FLASH in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); +} + +/** + * @brief Erase the whole FLASH in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); +} + + +/** + * @brief Program data to specified FLASH address in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + const uint32_t *src, uint32_t dst_addr, uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Page-Program data to specified FLASH address in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, const uint32_t *src, + uint32_t dst_addr, uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->page_program_nonblocking(base, channel, nor_config, src, dst_addr, + length); +} + +/** + * @brief Read data from specified FLASH address + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] dst Memory start address to store the data read out from FLASH + * @param [in] start FLASH address for data read + * @param [in] length length of data to be read out + * @return API exection address + */ +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t *dst, uint32_t start, uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); +} + +/** + * @brief Automatically configure XPI NOR based on cfg_option + * @param [in] base XPI base address + * @param [out] config XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, xpi_nor_config_t *config, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); +} + +/** + * @brief Get XPI NOR properties + * @param [in] base XPI base address + * @param [in] nor_cfg XPI NOR configuration structure + * @param [in] property_id + * @param [out] value property value retrieved by this API + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, + uint32_t *value) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); +} + + +/*********************************************************************************************************************** + * + * + * XPI RAM Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Get XPI RAM configuration based on cfg_option + * @param [in] base XPI base address + * @param [out] ram_cfg XPI RAM configuration structure + * @param [in] cfg_option XPI RAM configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, xpi_ram_config_t *ram_cfg, + xpi_ram_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); +} + +/** + * @brief Initialize XPI RAM + * @param [in] base XPI base address + * @param [in] ram_cfg XPI ram configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); +} + +/*********************************************************************************************************************** + * + * + * SDP Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Initialize SDP IP + */ +static inline void rom_sdp_init(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); +} + +/** + * @brief De-initialize SDP IP + */ +static inline void rom_sdp_deinit(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); +} + +/** + * @brief Set AES key to SDP + * @param [in] aes_ctx AES context + * @param [in] key AES key buffer + * @param [in] key_bits AES key-bit option + * @param[in] key_idx AES key index + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, + sdp_aes_key_bits_t key_bits, uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] len Data length for AES encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, + uint32_t len, const uint8_t *in, uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); +} + +/** + * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] length Data length for AES encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, uint8_t iv[16], + const uint8_t *in, uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); +} + +/** + * @brief HASH initialization + * @param [in] hash_ctx HASH context + * @param [in] alg HASH algorithm + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); +} + +/** + * @brief HASH Update + * @param [in] hash_ctx HASH context + * @param [in] data Data for HASH operation + * @param [in] length of the data for HASH operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); +} + +/** + * @brief HASH finialize + * @param [in] hash_ctx HASH context + * @param [out] digest the output digest + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); +} + +/** + * @brief SDP memcpy operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memcpy + * @param [in] src Source address for memcpy + * @param [in] length Size of data for memcpy operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); +} + +/** + * @brief SDP memset operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memset + * @param [in] pattern pattern for memset + * @param [in] length Size of data for memset operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi_xpi_soc_def.h new file mode 100644 index 0000000000..13edd92e2c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_romapi_xpi_soc_def.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_XPI_SOC_DEF_H +#define HPM_ROMAPI_XPI_SOC_DEF_H + +#include "hpm_common.h" +#include "hpm_romapi_xpi_def.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) +#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) +#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) +#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) +#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) +#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) +#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) +#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) +#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) + +typedef struct { + struct { + uint8_t priority; /* Offset: 0x00 */ + uint8_t master_idx; /* Offset: 0x01 */ + uint8_t buf_size_in_dword; /* Offset: 0x02 */ + bool enable_prefetch; /* Offset: 0x03 */ + } entry[8]; +} xpi_ahb_buffer_cfg_t; + +typedef struct { + uint8_t data_pads; + xpi_channel_t channel; + xpi_io_group_t io_group; + uint8_t drive_strength; + bool enable_dqs; + bool enable_diff_clk; +} xpi_io_config_t; + +typedef enum { + xpi_freq_type_typical, + xpi_freq_type_mhz, +} clk_freq_type_t; + +typedef enum { + xpi_clk_src_auto, + xpi_clk_src_osc, + xpi_clk_src_pll0clk0, + xpi_clk_src_pll1clk0, + xpi_clk_src_pll1clk1, + xpi_clk_src_pll2clk0, + xpi_clk_src_pll2clk1, + xpi_clk_src_pll3clk0, + xpi_clk_src_pll4clk0, +} xpi_clk_src_t; + + +typedef union +{ + struct { + uint8_t freq; + bool enable_ddr; + xpi_clk_src_t clk_src; + clk_freq_type_t freq_type; + }; + uint32_t freq_opt; +} xpi_clk_config_t; + +typedef enum { + xpi_clock_bus, + xpi_clock_serial_root, + xpi_clock_serial, +} xpi_clock_t; + +#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h new file mode 100644 index 0000000000..3c737107a6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SDXC_SOC_DRV_H +#define HPM_SDXC_SOC_DRV_H + +#include "hpm_soc.h" +#include "hpm_sdxc_regs.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** + * @brief Wait at least 74 clocks until card is ready to receive the first command + */ +static inline void sdxc_wait_card_active(SDXC_Type *base) +{ + base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; + + while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_SD_CLK_EN_MASK)) {} + /* + * Assume that the BUS clock is 200MHz, while in the identification state, the SD clock is 400KHz. + * - Reading the register costs about 5ns in best case, hence the loop should be (74 / 400KHz) * 1000000000 / 5 + * - For robustness, use 50000 here + */ + for (volatile uint32_t i = 0; i < 50000U; i++) { + (void) base->CAPABILITIES1; + } +} + +static inline void sdxc_enable_inverse_clock(SDXC_Type *base, bool enable) +{ + volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; + if (enable) { + *reg |= (1UL << 28); + } else { + *reg &= ~(1UL << 28); + } +} + + +#if defined(__cplusplus) +} +#endif + + +#endif /* HPM_SDXC_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml new file mode 100644 index 0000000000..5756e2ccce --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml @@ -0,0 +1,42459 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h new file mode 100644 index 0000000000..067c709029 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h @@ -0,0 +1,856 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SOC_H +#define HPM_SOC_H + + +/* List of external IRQs */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ +#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ +#define IRQn_GPIO0_E 5 /* GPIO0_E IRQ */ +#define IRQn_GPIO0_F 6 /* GPIO0_F IRQ */ +#define IRQn_GPIO0_X 7 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 8 /* GPIO0_Y IRQ */ +#define IRQn_GPIO0_Z 9 /* GPIO0_Z IRQ */ +#define IRQn_GPIO1_A 10 /* GPIO1_A IRQ */ +#define IRQn_GPIO1_B 11 /* GPIO1_B IRQ */ +#define IRQn_GPIO1_C 12 /* GPIO1_C IRQ */ +#define IRQn_GPIO1_D 13 /* GPIO1_D IRQ */ +#define IRQn_GPIO1_E 14 /* GPIO1_E IRQ */ +#define IRQn_GPIO1_F 15 /* GPIO1_F IRQ */ +#define IRQn_GPIO1_X 16 /* GPIO1_X IRQ */ +#define IRQn_GPIO1_Y 17 /* GPIO1_Y IRQ */ +#define IRQn_GPIO1_Z 18 /* GPIO1_Z IRQ */ +#define IRQn_ADC0 19 /* ADC0 IRQ */ +#define IRQn_ADC1 20 /* ADC1 IRQ */ +#define IRQn_ADC2 21 /* ADC2 IRQ */ +#define IRQn_ADC3 22 /* ADC3 IRQ */ +#define IRQn_ACMP_0 23 /* ACMP[0] IRQ */ +#define IRQn_ACMP_1 24 /* ACMP[1] IRQ */ +#define IRQn_ACMP_2 25 /* ACMP[2] IRQ */ +#define IRQn_ACMP_3 26 /* ACMP[3] IRQ */ +#define IRQn_SPI0 27 /* SPI0 IRQ */ +#define IRQn_SPI1 28 /* SPI1 IRQ */ +#define IRQn_SPI2 29 /* SPI2 IRQ */ +#define IRQn_SPI3 30 /* SPI3 IRQ */ +#define IRQn_UART0 31 /* UART0 IRQ */ +#define IRQn_UART1 32 /* UART1 IRQ */ +#define IRQn_UART2 33 /* UART2 IRQ */ +#define IRQn_UART3 34 /* UART3 IRQ */ +#define IRQn_UART4 35 /* UART4 IRQ */ +#define IRQn_UART5 36 /* UART5 IRQ */ +#define IRQn_UART6 37 /* UART6 IRQ */ +#define IRQn_UART7 38 /* UART7 IRQ */ +#define IRQn_UART8 39 /* UART8 IRQ */ +#define IRQn_UART9 40 /* UART9 IRQ */ +#define IRQn_UART10 41 /* UART10 IRQ */ +#define IRQn_UART11 42 /* UART11 IRQ */ +#define IRQn_UART12 43 /* UART12 IRQ */ +#define IRQn_UART13 44 /* UART13 IRQ */ +#define IRQn_UART14 45 /* UART14 IRQ */ +#define IRQn_UART15 46 /* UART15 IRQ */ +#define IRQn_CAN0 47 /* CAN0 IRQ */ +#define IRQn_CAN1 48 /* CAN1 IRQ */ +#define IRQn_CAN2 49 /* CAN2 IRQ */ +#define IRQn_CAN3 50 /* CAN3 IRQ */ +#define IRQn_PTPC 51 /* PTPC IRQ */ +#define IRQn_WDG0 52 /* WDG0 IRQ */ +#define IRQn_WDG1 53 /* WDG1 IRQ */ +#define IRQn_WDG2 54 /* WDG2 IRQ */ +#define IRQn_WDG3 55 /* WDG3 IRQ */ +#define IRQn_MBX0A 56 /* MBX0A IRQ */ +#define IRQn_MBX0B 57 /* MBX0B IRQ */ +#define IRQn_MBX1A 58 /* MBX1A IRQ */ +#define IRQn_MBX1B 59 /* MBX1B IRQ */ +#define IRQn_GPTMR0 60 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 61 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 62 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 63 /* GPTMR3 IRQ */ +#define IRQn_GPTMR4 64 /* GPTMR4 IRQ */ +#define IRQn_GPTMR5 65 /* GPTMR5 IRQ */ +#define IRQn_GPTMR6 66 /* GPTMR6 IRQ */ +#define IRQn_GPTMR7 67 /* GPTMR7 IRQ */ +#define IRQn_I2C0 68 /* I2C0 IRQ */ +#define IRQn_I2C1 69 /* I2C1 IRQ */ +#define IRQn_I2C2 70 /* I2C2 IRQ */ +#define IRQn_I2C3 71 /* I2C3 IRQ */ +#define IRQn_PWM0 72 /* PWM0 IRQ */ +#define IRQn_HALL0 73 /* HALL0 IRQ */ +#define IRQn_QEI0 74 /* QEI0 IRQ */ +#define IRQn_PWM1 75 /* PWM1 IRQ */ +#define IRQn_HALL1 76 /* HALL1 IRQ */ +#define IRQn_QEI1 77 /* QEI1 IRQ */ +#define IRQn_PWM2 78 /* PWM2 IRQ */ +#define IRQn_HALL2 79 /* HALL2 IRQ */ +#define IRQn_QEI2 80 /* QEI2 IRQ */ +#define IRQn_PWM3 81 /* PWM3 IRQ */ +#define IRQn_HALL3 82 /* HALL3 IRQ */ +#define IRQn_QEI3 83 /* QEI3 IRQ */ +#define IRQn_SDP 84 /* SDP IRQ */ +#define IRQn_XPI0 85 /* XPI0 IRQ */ +#define IRQn_XPI1 86 /* XPI1 IRQ */ +#define IRQn_XDMA 87 /* XDMA IRQ */ +#define IRQn_HDMA 88 /* HDMA IRQ */ +#define IRQn_DRAM 89 /* DRAM IRQ */ +#define IRQn_RNG 90 /* RNG IRQ */ +#define IRQn_I2S0 91 /* I2S0 IRQ */ +#define IRQn_I2S1 92 /* I2S1 IRQ */ +#define IRQn_I2S2 93 /* I2S2 IRQ */ +#define IRQn_I2S3 94 /* I2S3 IRQ */ +#define IRQn_DAO 95 /* DAO IRQ */ +#define IRQn_PDM 96 /* PDM IRQ */ +#define IRQn_CAM0 97 /* CAM0 IRQ */ +#define IRQn_CAM1 98 /* CAM1 IRQ */ +#define IRQn_LCDC_D0 99 /* LCDC_D0 IRQ */ +#define IRQn_LCDC_D1 100 /* LCDC_D1 IRQ */ +#define IRQn_PDMA_D0 101 /* PDMA_D0 IRQ */ +#define IRQn_PDMA_D1 102 /* PDMA_D1 IRQ */ +#define IRQn_JPEG 103 /* JPEG IRQ */ +#define IRQn_NTMR0 104 /* NTMR0 IRQ */ +#define IRQn_NTMR1 105 /* NTMR1 IRQ */ +#define IRQn_USB0 106 /* USB0 IRQ */ +#define IRQn_USB1 107 /* USB1 IRQ */ +#define IRQn_ENET0 108 /* ENET0 IRQ */ +#define IRQn_ENET1 109 /* ENET1 IRQ */ +#define IRQn_SDXC0 110 /* SDXC0 IRQ */ +#define IRQn_SDXC1 111 /* SDXC1 IRQ */ +#define IRQn_PSEC 112 /* PSEC IRQ */ +#define IRQn_PGPIO 113 /* PGPIO IRQ */ +#define IRQn_PWDG 114 /* PWDG IRQ */ +#define IRQn_PTMR 115 /* PTMR IRQ */ +#define IRQn_PUART 116 /* PUART IRQ */ +#define IRQn_VAD 117 /* VAD IRQ */ +#define IRQn_FUSE 118 /* FUSE IRQ */ +#define IRQn_SECMON 119 /* SECMON IRQ */ +#define IRQn_RTC 120 /* RTC IRQ */ +#define IRQn_BUTN 121 /* BUTN IRQ */ +#define IRQn_BGPIO 122 /* BGPIO IRQ */ +#define IRQn_BVIO 123 /* BVIO IRQ */ +#define IRQn_BROWNOUT 124 /* BROWNOUT IRQ */ +#define IRQn_SYSCTL 125 /* SYSCTL IRQ */ +#define IRQn_DEBUG_0 126 /* DEBUG[0] IRQ */ +#define IRQn_DEBUG_1 127 /* DEBUG[1] IRQ */ + +#include "hpm_common.h" + +#include "hpm_gpio_regs.h" +/* Address of GPIO instances */ +/* FGPIO base address */ +#define HPM_FGPIO_BASE (0xC0000UL) +/* FGPIO base pointer */ +#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) +/* GPIO0 base address */ +#define HPM_GPIO0_BASE (0xF0000000UL) +/* GPIO0 base pointer */ +#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) +/* GPIO1 base address */ +#define HPM_GPIO1_BASE (0xF0004000UL) +/* GPIO1 base pointer */ +#define HPM_GPIO1 ((GPIO_Type *) HPM_GPIO1_BASE) +/* PGPIO base address */ +#define HPM_PGPIO_BASE (0xF40DC000UL) +/* PGPIO base pointer */ +#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) +/* BGPIO base address */ +#define HPM_BGPIO_BASE (0xF5014000UL) +/* BGPIO base pointer */ +#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) + +/* Address of DM instances */ +/* DM base address */ +#define HPM_DM_BASE (0x30000000UL) + +#include "hpm_plic_regs.h" +/* Address of PLIC instances */ +/* PLIC base address */ +#define HPM_PLIC_BASE (0xE4000000UL) +/* PLIC base pointer */ +#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) + +#include "hpm_mchtmr_regs.h" +/* Address of MCHTMR instances */ +/* MCHTMR base address */ +#define HPM_MCHTMR_BASE (0xE6000000UL) +/* MCHTMR base pointer */ +#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) + +#include "hpm_plic_sw_regs.h" +/* Address of PLICSW instances */ +/* PLICSW base address */ +#define HPM_PLICSW_BASE (0xE6400000UL) +/* PLICSW base pointer */ +#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) + +#include "hpm_gpiom_regs.h" +/* Address of GPIOM instances */ +/* GPIOM base address */ +#define HPM_GPIOM_BASE (0xF0008000UL) +/* GPIOM base pointer */ +#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) + +#include "hpm_adc12_regs.h" +/* Address of ADC12 instances */ +/* ADC0 base address */ +#define HPM_ADC0_BASE (0xF0010000UL) +/* ADC0 base pointer */ +#define HPM_ADC0 ((ADC12_Type *) HPM_ADC0_BASE) +/* ADC1 base address */ +#define HPM_ADC1_BASE (0xF0014000UL) +/* ADC1 base pointer */ +#define HPM_ADC1 ((ADC12_Type *) HPM_ADC1_BASE) +/* ADC2 base address */ +#define HPM_ADC2_BASE (0xF0018000UL) +/* ADC2 base pointer */ +#define HPM_ADC2 ((ADC12_Type *) HPM_ADC2_BASE) + +#include "hpm_adc16_regs.h" +/* Address of ADC16 instances */ +/* ADC3 base address */ +#define HPM_ADC3_BASE (0xF001C000UL) +/* ADC3 base pointer */ +#define HPM_ADC3 ((ADC16_Type *) HPM_ADC3_BASE) + +#include "hpm_acmp_regs.h" +/* Address of ACMP instances */ +/* ACMP base address */ +#define HPM_ACMP_BASE (0xF0020000UL) +/* ACMP base pointer */ +#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) + +#include "hpm_spi_regs.h" +/* Address of SPI instances */ +/* SPI0 base address */ +#define HPM_SPI0_BASE (0xF0030000UL) +/* SPI0 base pointer */ +#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) +/* SPI1 base address */ +#define HPM_SPI1_BASE (0xF0034000UL) +/* SPI1 base pointer */ +#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) +/* SPI2 base address */ +#define HPM_SPI2_BASE (0xF0038000UL) +/* SPI2 base pointer */ +#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) +/* SPI3 base address */ +#define HPM_SPI3_BASE (0xF003C000UL) +/* SPI3 base pointer */ +#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) + +#include "hpm_uart_regs.h" +/* Address of UART instances */ +/* UART0 base address */ +#define HPM_UART0_BASE (0xF0040000UL) +/* UART0 base pointer */ +#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) +/* UART1 base address */ +#define HPM_UART1_BASE (0xF0044000UL) +/* UART1 base pointer */ +#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) +/* UART2 base address */ +#define HPM_UART2_BASE (0xF0048000UL) +/* UART2 base pointer */ +#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) +/* UART3 base address */ +#define HPM_UART3_BASE (0xF004C000UL) +/* UART3 base pointer */ +#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) +/* UART4 base address */ +#define HPM_UART4_BASE (0xF0050000UL) +/* UART4 base pointer */ +#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) +/* UART5 base address */ +#define HPM_UART5_BASE (0xF0054000UL) +/* UART5 base pointer */ +#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) +/* UART6 base address */ +#define HPM_UART6_BASE (0xF0058000UL) +/* UART6 base pointer */ +#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) +/* UART7 base address */ +#define HPM_UART7_BASE (0xF005C000UL) +/* UART7 base pointer */ +#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) +/* UART8 base address */ +#define HPM_UART8_BASE (0xF0060000UL) +/* UART8 base pointer */ +#define HPM_UART8 ((UART_Type *) HPM_UART8_BASE) +/* UART9 base address */ +#define HPM_UART9_BASE (0xF0064000UL) +/* UART9 base pointer */ +#define HPM_UART9 ((UART_Type *) HPM_UART9_BASE) +/* UART10 base address */ +#define HPM_UART10_BASE (0xF0068000UL) +/* UART10 base pointer */ +#define HPM_UART10 ((UART_Type *) HPM_UART10_BASE) +/* UART11 base address */ +#define HPM_UART11_BASE (0xF006C000UL) +/* UART11 base pointer */ +#define HPM_UART11 ((UART_Type *) HPM_UART11_BASE) +/* UART12 base address */ +#define HPM_UART12_BASE (0xF0070000UL) +/* UART12 base pointer */ +#define HPM_UART12 ((UART_Type *) HPM_UART12_BASE) +/* UART13 base address */ +#define HPM_UART13_BASE (0xF0074000UL) +/* UART13 base pointer */ +#define HPM_UART13 ((UART_Type *) HPM_UART13_BASE) +/* UART14 base address */ +#define HPM_UART14_BASE (0xF0078000UL) +/* UART14 base pointer */ +#define HPM_UART14 ((UART_Type *) HPM_UART14_BASE) +/* UART15 base address */ +#define HPM_UART15_BASE (0xF007C000UL) +/* UART15 base pointer */ +#define HPM_UART15 ((UART_Type *) HPM_UART15_BASE) +/* PUART base address */ +#define HPM_PUART_BASE (0xF40E4000UL) +/* PUART base pointer */ +#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) + +#include "hpm_can_regs.h" +/* Address of CAN instances */ +/* CAN0 base address */ +#define HPM_CAN0_BASE (0xF0080000UL) +/* CAN0 base pointer */ +#define HPM_CAN0 ((CAN_Type *) HPM_CAN0_BASE) +/* CAN1 base address */ +#define HPM_CAN1_BASE (0xF0084000UL) +/* CAN1 base pointer */ +#define HPM_CAN1 ((CAN_Type *) HPM_CAN1_BASE) +/* CAN2 base address */ +#define HPM_CAN2_BASE (0xF0088000UL) +/* CAN2 base pointer */ +#define HPM_CAN2 ((CAN_Type *) HPM_CAN2_BASE) +/* CAN3 base address */ +#define HPM_CAN3_BASE (0xF008C000UL) +/* CAN3 base pointer */ +#define HPM_CAN3 ((CAN_Type *) HPM_CAN3_BASE) + +#include "hpm_wdg_regs.h" +/* Address of WDOG instances */ +/* WDG0 base address */ +#define HPM_WDG0_BASE (0xF0090000UL) +/* WDG0 base pointer */ +#define HPM_WDG0 ((WDG_Type *) HPM_WDG0_BASE) +/* WDG1 base address */ +#define HPM_WDG1_BASE (0xF0094000UL) +/* WDG1 base pointer */ +#define HPM_WDG1 ((WDG_Type *) HPM_WDG1_BASE) +/* WDG2 base address */ +#define HPM_WDG2_BASE (0xF0098000UL) +/* WDG2 base pointer */ +#define HPM_WDG2 ((WDG_Type *) HPM_WDG2_BASE) +/* WDG3 base address */ +#define HPM_WDG3_BASE (0xF009C000UL) +/* WDG3 base pointer */ +#define HPM_WDG3 ((WDG_Type *) HPM_WDG3_BASE) +/* PWDG base address */ +#define HPM_PWDG_BASE (0xF40E8000UL) +/* PWDG base pointer */ +#define HPM_PWDG ((WDG_Type *) HPM_PWDG_BASE) + +#include "hpm_mbx_regs.h" +/* Address of MBX instances */ +/* MBX0A base address */ +#define HPM_MBX0A_BASE (0xF00A0000UL) +/* MBX0A base pointer */ +#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) +/* MBX0B base address */ +#define HPM_MBX0B_BASE (0xF00A4000UL) +/* MBX0B base pointer */ +#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) +/* MBX1A base address */ +#define HPM_MBX1A_BASE (0xF00A8000UL) +/* MBX1A base pointer */ +#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) +/* MBX1B base address */ +#define HPM_MBX1B_BASE (0xF00AC000UL) +/* MBX1B base pointer */ +#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) + +#include "hpm_ptpc_regs.h" +/* Address of PTPC instances */ +/* PTPC base address */ +#define HPM_PTPC_BASE (0xF00B0000UL) +/* PTPC base pointer */ +#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) + +#include "hpm_dmamux_regs.h" +/* Address of DMAMUX instances */ +/* DMAMUX base address */ +#define HPM_DMAMUX_BASE (0xF00C0000UL) +/* DMAMUX base pointer */ +#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) + +#include "hpm_dma_regs.h" +/* Address of DMA instances */ +/* HDMA base address */ +#define HPM_HDMA_BASE (0xF00C4000UL) +/* HDMA base pointer */ +#define HPM_HDMA ((DMA_Type *) HPM_HDMA_BASE) +/* XDMA base address */ +#define HPM_XDMA_BASE (0xF3048000UL) +/* XDMA base pointer */ +#define HPM_XDMA ((DMA_Type *) HPM_XDMA_BASE) + +#include "hpm_rng_regs.h" +/* Address of RNG instances */ +/* RNG base address */ +#define HPM_RNG_BASE (0xF00C8000UL) +/* RNG base pointer */ +#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) + +#include "hpm_keym_regs.h" +/* Address of KEYM instances */ +/* KEYM base address */ +#define HPM_KEYM_BASE (0xF00CC000UL) +/* KEYM base pointer */ +#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) + +#include "hpm_i2s_regs.h" +/* Address of I2S instances */ +/* I2S0 base address */ +#define HPM_I2S0_BASE (0xF0100000UL) +/* I2S0 base pointer */ +#define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE) +/* I2S1 base address */ +#define HPM_I2S1_BASE (0xF0104000UL) +/* I2S1 base pointer */ +#define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE) +/* I2S2 base address */ +#define HPM_I2S2_BASE (0xF0108000UL) +/* I2S2 base pointer */ +#define HPM_I2S2 ((I2S_Type *) HPM_I2S2_BASE) +/* I2S3 base address */ +#define HPM_I2S3_BASE (0xF010C000UL) +/* I2S3 base pointer */ +#define HPM_I2S3 ((I2S_Type *) HPM_I2S3_BASE) + +#include "hpm_dao_regs.h" +/* Address of DAO instances */ +/* DAO base address */ +#define HPM_DAO_BASE (0xF0110000UL) +/* DAO base pointer */ +#define HPM_DAO ((DAO_Type *) HPM_DAO_BASE) + +#include "hpm_pdm_regs.h" +/* Address of PDM instances */ +/* PDM base address */ +#define HPM_PDM_BASE (0xF0114000UL) +/* PDM base pointer */ +#define HPM_PDM ((PDM_Type *) HPM_PDM_BASE) + +#include "hpm_pwm_regs.h" +/* Address of PWM instances */ +/* PWM0 base address */ +#define HPM_PWM0_BASE (0xF0200000UL) +/* PWM0 base pointer */ +#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) +/* PWM1 base address */ +#define HPM_PWM1_BASE (0xF0210000UL) +/* PWM1 base pointer */ +#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) +/* PWM2 base address */ +#define HPM_PWM2_BASE (0xF0220000UL) +/* PWM2 base pointer */ +#define HPM_PWM2 ((PWM_Type *) HPM_PWM2_BASE) +/* PWM3 base address */ +#define HPM_PWM3_BASE (0xF0230000UL) +/* PWM3 base pointer */ +#define HPM_PWM3 ((PWM_Type *) HPM_PWM3_BASE) + +#include "hpm_hall_regs.h" +/* Address of HALL instances */ +/* HALL0 base address */ +#define HPM_HALL0_BASE (0xF0204000UL) +/* HALL0 base pointer */ +#define HPM_HALL0 ((HALL_Type *) HPM_HALL0_BASE) +/* HALL1 base address */ +#define HPM_HALL1_BASE (0xF0214000UL) +/* HALL1 base pointer */ +#define HPM_HALL1 ((HALL_Type *) HPM_HALL1_BASE) +/* HALL2 base address */ +#define HPM_HALL2_BASE (0xF0224000UL) +/* HALL2 base pointer */ +#define HPM_HALL2 ((HALL_Type *) HPM_HALL2_BASE) +/* HALL3 base address */ +#define HPM_HALL3_BASE (0xF0234000UL) +/* HALL3 base pointer */ +#define HPM_HALL3 ((HALL_Type *) HPM_HALL3_BASE) + +#include "hpm_qei_regs.h" +/* Address of QEI instances */ +/* QEI0 base address */ +#define HPM_QEI0_BASE (0xF0208000UL) +/* QEI0 base pointer */ +#define HPM_QEI0 ((QEI_Type *) HPM_QEI0_BASE) +/* QEI1 base address */ +#define HPM_QEI1_BASE (0xF0218000UL) +/* QEI1 base pointer */ +#define HPM_QEI1 ((QEI_Type *) HPM_QEI1_BASE) +/* QEI2 base address */ +#define HPM_QEI2_BASE (0xF0228000UL) +/* QEI2 base pointer */ +#define HPM_QEI2 ((QEI_Type *) HPM_QEI2_BASE) +/* QEI3 base address */ +#define HPM_QEI3_BASE (0xF0238000UL) +/* QEI3 base pointer */ +#define HPM_QEI3 ((QEI_Type *) HPM_QEI3_BASE) + +#include "hpm_trgm_regs.h" +/* Address of TRGM instances */ +/* TRGM0 base address */ +#define HPM_TRGM0_BASE (0xF020C000UL) +/* TRGM0 base pointer */ +#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) +/* TRGM1 base address */ +#define HPM_TRGM1_BASE (0xF021C000UL) +/* TRGM1 base pointer */ +#define HPM_TRGM1 ((TRGM_Type *) HPM_TRGM1_BASE) +/* TRGM2 base address */ +#define HPM_TRGM2_BASE (0xF022C000UL) +/* TRGM2 base pointer */ +#define HPM_TRGM2 ((TRGM_Type *) HPM_TRGM2_BASE) +/* TRGM3 base address */ +#define HPM_TRGM3_BASE (0xF023C000UL) +/* TRGM3 base pointer */ +#define HPM_TRGM3 ((TRGM_Type *) HPM_TRGM3_BASE) + +#include "hpm_synt_regs.h" +/* Address of SYNT instances */ +/* SYNT base address */ +#define HPM_SYNT_BASE (0xF0240000UL) +/* SYNT base pointer */ +#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) + +#include "hpm_lcdc_regs.h" +/* Address of LCDC instances */ +/* LCDC base address */ +#define HPM_LCDC_BASE (0xF1000000UL) +/* LCDC base pointer */ +#define HPM_LCDC ((LCDC_Type *) HPM_LCDC_BASE) + +#include "hpm_cam_regs.h" +/* Address of CAM instances */ +/* CAM0 base address */ +#define HPM_CAM0_BASE (0xF1008000UL) +/* CAM0 base pointer */ +#define HPM_CAM0 ((CAM_Type *) HPM_CAM0_BASE) +/* CAM1 base address */ +#define HPM_CAM1_BASE (0xF100C000UL) +/* CAM1 base pointer */ +#define HPM_CAM1 ((CAM_Type *) HPM_CAM1_BASE) + +#include "hpm_pdma_regs.h" +/* Address of PDMA instances */ +/* PDMA base address */ +#define HPM_PDMA_BASE (0xF1010000UL) +/* PDMA base pointer */ +#define HPM_PDMA ((PDMA_Type *) HPM_PDMA_BASE) + +#include "hpm_jpeg_regs.h" +/* Address of JPEG instances */ +/* JPEG base address */ +#define HPM_JPEG_BASE (0xF1014000UL) +/* JPEG base pointer */ +#define HPM_JPEG ((JPEG_Type *) HPM_JPEG_BASE) + +#include "hpm_enet_regs.h" +/* Address of ENET instances */ +/* ENET0 base address */ +#define HPM_ENET0_BASE (0xF2000000UL) +/* ENET0 base pointer */ +#define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE) +/* ENET1 base address */ +#define HPM_ENET1_BASE (0xF2004000UL) +/* ENET1 base pointer */ +#define HPM_ENET1 ((ENET_Type *) HPM_ENET1_BASE) + +#include "hpm_gptmr_regs.h" +/* Address of TMR instances */ +/* NTMR0 base address */ +#define HPM_NTMR0_BASE (0xF2010000UL) +/* NTMR0 base pointer */ +#define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE) +/* NTMR1 base address */ +#define HPM_NTMR1_BASE (0xF2014000UL) +/* NTMR1 base pointer */ +#define HPM_NTMR1 ((GPTMR_Type *) HPM_NTMR1_BASE) +/* GPTMR0 base address */ +#define HPM_GPTMR0_BASE (0xF3000000UL) +/* GPTMR0 base pointer */ +#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) +/* GPTMR1 base address */ +#define HPM_GPTMR1_BASE (0xF3004000UL) +/* GPTMR1 base pointer */ +#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) +/* GPTMR2 base address */ +#define HPM_GPTMR2_BASE (0xF3008000UL) +/* GPTMR2 base pointer */ +#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) +/* GPTMR3 base address */ +#define HPM_GPTMR3_BASE (0xF300C000UL) +/* GPTMR3 base pointer */ +#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) +/* GPTMR4 base address */ +#define HPM_GPTMR4_BASE (0xF3010000UL) +/* GPTMR4 base pointer */ +#define HPM_GPTMR4 ((GPTMR_Type *) HPM_GPTMR4_BASE) +/* GPTMR5 base address */ +#define HPM_GPTMR5_BASE (0xF3014000UL) +/* GPTMR5 base pointer */ +#define HPM_GPTMR5 ((GPTMR_Type *) HPM_GPTMR5_BASE) +/* GPTMR6 base address */ +#define HPM_GPTMR6_BASE (0xF3018000UL) +/* GPTMR6 base pointer */ +#define HPM_GPTMR6 ((GPTMR_Type *) HPM_GPTMR6_BASE) +/* GPTMR7 base address */ +#define HPM_GPTMR7_BASE (0xF301C000UL) +/* GPTMR7 base pointer */ +#define HPM_GPTMR7 ((GPTMR_Type *) HPM_GPTMR7_BASE) +/* PTMR base address */ +#define HPM_PTMR_BASE (0xF40E0000UL) +/* PTMR base pointer */ +#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) + +#include "hpm_usb_regs.h" +/* Address of USB instances */ +/* USB0 base address */ +#define HPM_USB0_BASE (0xF2020000UL) +/* USB0 base pointer */ +#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) +/* USB1 base address */ +#define HPM_USB1_BASE (0xF2024000UL) +/* USB1 base pointer */ +#define HPM_USB1 ((USB_Type *) HPM_USB1_BASE) + +#include "hpm_sdxc_regs.h" +/* Address of SDXC instances */ +/* SDXC0 base address */ +#define HPM_SDXC0_BASE (0xF2030000UL) +/* SDXC0 base pointer */ +#define HPM_SDXC0 ((SDXC_Type *) HPM_SDXC0_BASE) +/* SDXC1 base address */ +#define HPM_SDXC1_BASE (0xF2034000UL) +/* SDXC1 base pointer */ +#define HPM_SDXC1 ((SDXC_Type *) HPM_SDXC1_BASE) + +#include "hpm_conctl_regs.h" +/* Address of CONCTL instances */ +/* CONCTL base address */ +#define HPM_CONCTL_BASE (0xF2040000UL) +/* CONCTL base pointer */ +#define HPM_CONCTL ((CONCTL_Type *) HPM_CONCTL_BASE) + +#include "hpm_i2c_regs.h" +/* Address of I2C instances */ +/* I2C0 base address */ +#define HPM_I2C0_BASE (0xF3020000UL) +/* I2C0 base pointer */ +#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) +/* I2C1 base address */ +#define HPM_I2C1_BASE (0xF3024000UL) +/* I2C1 base pointer */ +#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) +/* I2C2 base address */ +#define HPM_I2C2_BASE (0xF3028000UL) +/* I2C2 base pointer */ +#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) +/* I2C3 base address */ +#define HPM_I2C3_BASE (0xF302C000UL) +/* I2C3 base pointer */ +#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) + +#include "hpm_sdp_regs.h" +/* Address of SDP instances */ +/* SDP base address */ +#define HPM_SDP_BASE (0xF304C000UL) +/* SDP base pointer */ +#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) + +#include "hpm_dram_regs.h" +/* Address of DRAM instances */ +/* DRAM base address */ +#define HPM_DRAM_BASE (0xF3050000UL) +/* DRAM base pointer */ +#define HPM_DRAM ((DRAM_Type *) HPM_DRAM_BASE) + +#include "hpm_sysctl_regs.h" +/* Address of SYSCTL instances */ +/* SYSCTL base address */ +#define HPM_SYSCTL_BASE (0xF4000000UL) +/* SYSCTL base pointer */ +#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) + +#include "hpm_ioc_regs.h" +/* Address of IOC instances */ +/* IOC base address */ +#define HPM_IOC_BASE (0xF4040000UL) +/* IOC base pointer */ +#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) +/* PIOC base address */ +#define HPM_PIOC_BASE (0xF40D8000UL) +/* PIOC base pointer */ +#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) +/* BIOC base address */ +#define HPM_BIOC_BASE (0xF5010000UL) +/* BIOC base pointer */ +#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) + +#include "hpm_otp_regs.h" +/* Address of OTP instances */ +/* OTPSHW base address */ +#define HPM_OTPSHW_BASE (0xF4080000UL) +/* OTPSHW base pointer */ +#define HPM_OTPSHW ((OTP_Type *) HPM_OTPSHW_BASE) +/* OTP base address */ +#define HPM_OTP_BASE (0xF40C8000UL) +/* OTP base pointer */ +#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) + +#include "hpm_ppor_regs.h" +/* Address of PPOR instances */ +/* PPOR base address */ +#define HPM_PPOR_BASE (0xF40C0000UL) +/* PPOR base pointer */ +#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) + +#include "hpm_pcfg_regs.h" +/* Address of PCFG instances */ +/* PCFG base address */ +#define HPM_PCFG_BASE (0xF40C4000UL) +/* PCFG base pointer */ +#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) + +#include "hpm_psec_regs.h" +/* Address of PSEC instances */ +/* PSEC base address */ +#define HPM_PSEC_BASE (0xF40CC000UL) +/* PSEC base pointer */ +#define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE) + +#include "hpm_pmon_regs.h" +/* Address of PMON instances */ +/* PMON base address */ +#define HPM_PMON_BASE (0xF40D0000UL) +/* PMON base pointer */ +#define HPM_PMON ((PMON_Type *) HPM_PMON_BASE) + +#include "hpm_pgpr_regs.h" +/* Address of PGPR instances */ +/* PGPR base address */ +#define HPM_PGPR_BASE (0xF40D4000UL) +/* PGPR base pointer */ +#define HPM_PGPR ((PGPR_Type *) HPM_PGPR_BASE) + +#include "hpm_vad_regs.h" +/* Address of VAD instances */ +/* VAD base address */ +#define HPM_VAD_BASE (0xF40EC000UL) +/* VAD base pointer */ +#define HPM_VAD ((VAD_Type *) HPM_VAD_BASE) + +#include "hpm_pllctl_regs.h" +/* Address of PLLCTL instances */ +/* PLLCTL base address */ +#define HPM_PLLCTL_BASE (0xF4100000UL) +/* PLLCTL base pointer */ +#define HPM_PLLCTL ((PLLCTL_Type *) HPM_PLLCTL_BASE) + +#include "hpm_bpor_regs.h" +/* Address of BPOR instances */ +/* BPOR base address */ +#define HPM_BPOR_BASE (0xF5004000UL) +/* BPOR base pointer */ +#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) + +#include "hpm_bcfg_regs.h" +/* Address of BCFG instances */ +/* BCFG base address */ +#define HPM_BCFG_BASE (0xF5008000UL) +/* BCFG base pointer */ +#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) + +#include "hpm_butn_regs.h" +/* Address of BUTN instances */ +/* BUTN base address */ +#define HPM_BUTN_BASE (0xF500C000UL) +/* BUTN base pointer */ +#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE) + +#include "hpm_bgpr_regs.h" +/* Address of BGPR instances */ +/* BGPR base address */ +#define HPM_BGPR_BASE (0xF5018000UL) +/* BGPR base pointer */ +#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) + +#include "hpm_rtc_regs.h" +/* Address of RTC instances */ +/* RTCSHW base address */ +#define HPM_RTCSHW_BASE (0xF501C000UL) +/* RTCSHW base pointer */ +#define HPM_RTCSHW ((RTC_Type *) HPM_RTCSHW_BASE) +/* RTC base address */ +#define HPM_RTC_BASE (0xF5044000UL) +/* RTC base pointer */ +#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) + +#include "hpm_bsec_regs.h" +/* Address of BSEC instances */ +/* BSEC base address */ +#define HPM_BSEC_BASE (0xF5040000UL) +/* BSEC base pointer */ +#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) + +#include "hpm_bkey_regs.h" +/* Address of BKEY instances */ +/* BKEY base address */ +#define HPM_BKEY_BASE (0xF5048000UL) +/* BKEY base pointer */ +#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) + +#include "hpm_bmon_regs.h" +/* Address of BMON instances */ +/* BMON base address */ +#define HPM_BMON_BASE (0xF504C000UL) +/* BMON base pointer */ +#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) + +#include "hpm_tamp_regs.h" +/* Address of TAMP instances */ +/* TAMP base address */ +#define HPM_TAMP_BASE (0xF5050000UL) +/* TAMP base pointer */ +#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) + +#include "hpm_mono_regs.h" +/* Address of MONO instances */ +/* MONO base address */ +#define HPM_MONO_BASE (0xF5054000UL) +/* MONO base pointer */ +#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) + + +#include "riscv/riscv_core.h" +#include "hpm_csr_regs.h" +#include "hpm_interrupt.h" +#include "hpm_misc.h" +#include "hpm_dmamux_src.h" +#include "hpm_trgmmux_src.h" +#include "hpm_iomux.h" +#include "hpm_pmic_iomux.h" +#include "hpm_batt_iomux.h" +#include "hpm_ioc_regs.h" +#include "hpm_gpiom_regs.h" +#include "hpm_sysctl_regs.h" +#include "hpm_trgm_regs.h" +#endif /* HPM_SOC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h new file mode 100644 index 0000000000..08ed7da2b4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SOC_FEATURE_H +#define HPM_SOC_FEATURE_H + +#include "hpm_soc.h" + +/* + * I2C Section + */ +#define I2C_SOC_FIFO_SIZE (4U) + +/* + * PMIC Section + */ +#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) +#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) +#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) +#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) +#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) +#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) + +/* + * I2S Section + */ +#define I2S_SOC_MAX_CHANNEL_NUM (16U) +#define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) +#define PDM_I2S HPM_I2S0 +#define DAO_I2S HPM_I2S1 +#define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) +#define VAD_SOC_SAMPLE_RATE_IN_HZ (16000U) +#define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U) +#define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U) +#define DAO_SOC_VAD_SAMPLE_RATE_RATIO (3U) + +/* + * PLLCTL Section + */ +#define PLLCTL_SOC_PLL_MAX_COUNT (5U) +/* PLL reference clock in hz */ +#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) +/* only PLL1 and PLL2 have DIV0, DIV1 */ +#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) +#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) + + +/* + * PWM Section + */ +#define PWM_SOC_PWM_MAX_COUNT (8U) +#define PWM_SOC_CMP_MAX_COUNT (24U) +#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) +#define PWM_SOC_OUTPUT_MAX_COUNT (24U) + +/* + * DMA Section + */ +#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) +#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) +#define DMA_SOC_BUS_NUM (1U) +#define DMA_SOC_CHANNEL_NUM (8U) +#define DMA_SOC_MAX_COUNT (2U) +#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) + +/* + * PDMA Section + */ +#define PDMA_SOC_PS_MAX_COUNT (2U) + +/* + * LCDC Section + */ +#define LCDC_SOC_MAX_LAYER_COUNT (8U) +#define LCDC_SOC_MAX_CSC_LAYER_COUNT (2U) +#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) +#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) + +/* +* USB Section +*/ +#define USB_SOC_MAX_COUNT (2U) + +#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) +#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) +#define USB_SOC_DCD_QTD_ALIGNMENT (32U) +#define USB_SOC_DCD_QHD_ALIGNMENT (64U) +#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) + +#define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) +#define USB_SOC_HCD_QTD_ALIGNMENT (32U) +#define USB_SOC_HCD_QHD_ALIGNMENT (32U) +#define USB_SOC_HCD_MAX_ENDPOINT_COUNT (8U) +#define USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT (USB_SOC_HCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) +#define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) + +/* +* ENET Section +*/ +#define ENET_SOC_DESC_ADDR_ALIGNMENT (16U) +#define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) +#define ENET_SOC_ADDR_MAX_COUNT (5U) +#define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) +#define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) +#define ENET_SOC_ALT_EHD_DES_LEN (8U) + +/* +* ADC Section +*/ +#define ADC_SOC_SEQ_MAX_LEN (16U) +#define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) +#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) +#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (0U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (1024U) +#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) + +#define ADC12_SOC_CLOCK_CLK_DIV (2U) +#define ADC12_SOC_CALIBRATION_WAITING_LOOP_CNT (10) +#define ADC12_SOC_MAX_CH_NUM (17U) +#define ADC12_SOC_TEMP_CH_NUM (18U) +#define ADC12_SOC_INVALID_TEMP_BASE (0xF0010000UL) + +#define ADC16_SOC_PARAMS_LEN (34U) +#define ADC16_SOC_MAX_CH_NUM (7U) +#define ADC16_SOC_TEMP_CH_NUM (14U) + +/* + * SYSCTL Section + */ +#define SYSCTL_SOC_CPU_GPR_COUNT (14U) +#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) + +/* + * PTPC Section + */ +#define PTPC_SOC_TIMER_MAX_COUNT (2U) + +/* + * CAN Section + */ +#define CAN_SOC_MAX_COUNT (4U) + +/* + * UART Section + */ +#define UART_SOC_FIFO_SIZE (16U) + +/* + * SPI Section + */ +#define SPI_SOC_TRANSFER_COUNT_MAX (512U) + +/* + * SDXC Section + */ +#define SDXC_SOC_MAX_COUNT (2) +/* + * JPEG Section + */ +/*jpg file sampling factor*/ +#define JPEG_SOC_SAMPLING_FORMAT_420 (0x2211U) +#define JPEG_SOC_SAMPLING_FORMAT_422H (0x2111U) +#define JPEG_SOC_SAMPLING_FORMAT_422V (0x1211U) +#define JPEG_SOC_SAMPLING_FORMAT_444 (0x1111U) +#define JPEG_SOC_SAMPLING_FORMAT_400 (0x2200U) + +#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c new file mode 100644 index 0000000000..38fafa6a14 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sysctl_drv.h" +#include "hpm_soc_feature.h" + +#define SYSCTL_RESOURCE_GROUP0 0 +#define SYSCTL_RESOURCE_GROUP1 1 + +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24 )) + +static inline bool sysctl_valid_cpu_index(uint8_t cpu) +{ + if ((cpu != SYSCTL_CPU_CPU0) && (cpu != SYSCTL_CPU_CPU1)) { + return false; + } + return true; +} + +hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, + uint32_t *data, uint32_t size) +{ + uint32_t i; + if ((!sysctl_valid_cpu_index(cpu)) + || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { + return status_invalid_argument; + } + for (i = 0; i < size; i++) { + *(data + i) = ptr->CPU[cpu].GPR[i] ; + } + return status_success; +} + +static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, + uint8_t cpu, + uint8_t start, + uint8_t count, + uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) + || (data == NULL) + || !count || start > size || count > size + || (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + *(data + i) = ptr->CPU[cpu].GPR[start + i]; + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, + uint8_t start, + uint8_t count, + uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); +} + +hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, + uint8_t start, + uint8_t count, + uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); +} + +static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, + uint8_t cpu, + uint8_t start, + uint8_t count, + uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) + || (data == NULL) + || !count || start > size || count > size + || (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + ptr->CPU[cpu].GPR[start + i] = *(data + i); + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, + uint8_t start, + uint8_t count, + uint32_t *data, + bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, + uint8_t start, + uint8_t count, + uint32_t *data, + bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 1, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu1_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) +{ + config->mode = monitor_work_mode_record; + config->accuracy = monitor_accuracy_1khz; + config->reference = monitor_reference_24mhz; + config->divide_by = 1; + config->high_limit = 0; + config->low_limit = 0; + config->start_measure = true; + config->enable_output = false; + config->target = monitor_target_clk_top_cpu0; +} + +void sysctl_monitor_init(SYSCTL_Type *ptr, + uint8_t slice, monitor_config_t *config) +{ + ptr->MONITOR[slice].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + + if (config->mode == monitor_work_mode_compare) { + ptr->MONITOR[slice].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[slice].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + } + + ptr->MONITOR[slice].CONTROL = (ptr->MONITOR[slice].CONTROL + & ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK + | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | SYSCTL_MONITOR_CONTROL_REFERENCE_MASK + | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) + | (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) + | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) + | SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) + | SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) + | SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) + | SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) + | SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); +} + +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output) +{ + uint32_t frequency = 0; + monitor_config_t monitor = {0}; + sysctl_monitor_get_default_config(ptr, &monitor); + monitor.target = target; + monitor.enable_output = enable_output; + sysctl_monitor_init(ptr, monitor_index, &monitor); + if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { + frequency = sysctl_monitor_get_current_result(ptr, monitor_index); + } + return frequency; +} + +static hpm_stat_t _sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) +{ + if (!sysctl_valid_cpu_index(cpu)) { + return status_invalid_argument; + } + ptr->CPU[cpu].GPR[0] = entry; + ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); + return status_success; +} + +hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return _sysctl_set_cpu_entry(ptr, 1, entry); +} + +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return _sysctl_set_cpu_entry(ptr, 0, entry); +} + +void sysctl_release_cpu1(SYSCTL_Type *ptr) +{ + ptr->CPU[1].LP &= ~SYSCTL_CPU_LP_HALT_MASK; +} + +bool sysctl_is_cpu1_released(SYSCTL_Type *ptr) +{ + return ((ptr->CPU[1].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); +} + +hpm_stat_t sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu, cpu_lp_mode_t mode) +{ + if (!sysctl_valid_cpu_index(cpu)) { + return status_invalid_argument; + } + ptr->CPU[cpu].LP = (ptr->CPU[cpu].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); + return status_success; +} + +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t linkable_resource, + bool enable) +{ + uint32_t index, offset; + if (linkable_resource < sysctl_resource_linkable_start) { + return status_invalid_argument; + } + + index = (linkable_resource - sysctl_resource_linkable_start) / 32; + offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) + | (enable ? (1UL << offset) : 0); + break; + case SYSCTL_RESOURCE_GROUP1: + ptr->GROUP1[index].VALUE = (ptr->GROUP1[index].VALUE & ~(1UL << offset)) + | (enable ? (1UL << offset) : 0); + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); +} + +hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, false); +} + +hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, + clock_node_t node, + clock_source_adc_i2s_t source) +{ + uint32_t index; + if ((node < clock_node_adc_i2s_start) + || (source >= clock_source_adc_i2s_clk_end)) { + return status_invalid_argument; + } + + switch(node) { + case clock_node_adc3: + case clock_node_adc2: + case clock_node_adc1: + case clock_node_adc0: + index = node - clock_node_adc0; + ptr->ADCCLK[index] + = (ptr->ADCCLK[index] & ~SYSCTL_ADCCLK_MUX_MASK) + | SYSCTL_ADCCLK_MUX_SET(source); + break; + case clock_node_i2s3: + case clock_node_i2s2: + case clock_node_i2s1: + case clock_node_i2s0: + index = node - clock_node_i2s0; + ptr->I2SCLK[index] + = (ptr->I2SCLK[index] & ~SYSCTL_I2SCLK_MUX_MASK) + | SYSCTL_I2SCLK_MUX_SET(source); + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_i2s_start) { + return status_invalid_argument; + } + + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); + while(sysctl_clock_target_is_busy(ptr, node)); + return status_success; +} + + +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, + clock_source_t source, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_i2s_start) { + return status_invalid_argument; + } + + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + ptr->CLOCK[node] = (ptr->CLOCK[node] & + ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) + | (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); + while(sysctl_clock_target_is_busy(ptr, node)); + return status_success; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h new file mode 100644 index 0000000000..9a8f72674d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h @@ -0,0 +1,1234 @@ +/** + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SYSCTL_DRV_H +#define HPM_SYSCTL_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_regs.h" + +/** + * + * @brief SYSCTL driver APIs + * @defgroup sysctl_interface SYSCTL driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Retention domains + */ +typedef enum { + sysctl_retention_domain_sys = 0, + sysctl_retention_domain_cpu0 = 2, + sysctl_retention_domain_cpu1 = 4, + sysctl_retention_domain_conn = 6, + sysctl_retention_domain_vis = 8, + sysctl_retention_domain_xtal24m = 10, + sysctl_retention_domain_pll0 = 11, + sysctl_retention_domain_pll1 = 12, + sysctl_retention_domain_pll2 = 13, + sysctl_retention_domain_pll3 = 14, + sysctl_retention_domain_pll4 = 15, +} sysctl_retention_domain_t; + +/** + * @brief Clock presets + */ +typedef enum { + sysctl_preset_0 = 1 << 0, + sysctl_preset_1 = 1 << 1, + sysctl_preset_2 = 1 << 2, + sysctl_preset_3 = 1 << 3, +} sysctl_preset_t; + +/** + * @brief Reset domains + */ +typedef enum { + sysctl_reset_domain_soc = 0, + sysctl_reset_domain_con, + sysctl_reset_domain_vis, + sysctl_reset_domain_cpu0, + sysctl_reset_domain_cpu1, +} sysctl_reset_domain_t; + +/** + * @brief Resource + */ +typedef enum { + sysctl_resource_cpu0 = 0, + sysctl_resource_cpx0 = 1, + sysctl_resource_exe0 = 2, + sysctl_resource_wak0 = 3, + sysctl_resource_cpu0_per = 4, + sysctl_resource_cpu1 = 8, + sysctl_resource_cpx1 = 9, + sysctl_resource_exe1 = 10, + sysctl_resource_wak1 = 11, + sysctl_resource_cpu1_per = 12, + sysctl_resource_logic0 = 16, + sysctl_resource_logic1 = 17, + sysctl_resource_logic2 = 18, + sysctl_resource_logic3 = 19, + sysctl_resource_pmic = 20, + sysctl_resource_pow_con = 21, + sysctl_resource_pow_vis = 22, + sysctl_resource_pow_cpu0 = 23, + sysctl_resource_pow_cpu1 = 24, + sysctl_resource_rst_soc = 25, + sysctl_resource_rst_con = 26, + sysctl_resource_rst_vis = 27, + sysctl_resource_rst_cpu0 = 28, + sysctl_resource_rst_cpu1 = 29, + sysctl_resource_xtal = 32, + sysctl_resource_pll0 = 33, + sysctl_resource_clk0_pll0 = 34, + sysctl_resource_pll1 = 35, + sysctl_resource_clk0_pll1 = 36, + sysctl_resource_clk1_pll1 = 37, + sysctl_resource_pll2 = 38, + sysctl_resource_clk0_pll2 = 39, + sysctl_resource_clk1_pll2 = 40, + sysctl_resource_pll3 = 41, + sysctl_resource_clk0_pll3 = 42, + sysctl_resource_pll4 = 43, + sysctl_resource_clk0_pll4 = 44, + sysctl_resource_mbist_soc = 48, + sysctl_resource_mbist_cpu = 49, + sysctl_resource_mbist_cpu1 = 50, + sysctl_resource_mbist_con = 51, + sysctl_resource_mbist_vis = 52, + sysctl_resource_clk_top_cpu0 = 64, + sysctl_resource_clk_top_mchtmr0 = 65, + sysctl_resource_clk_top_cpu1 = 66, + sysctl_resource_clk_top_mchtmr1 = 67, + sysctl_resource_clk_top_axi0 = 68, + sysctl_resource_clk_top_axi1 = 69, + sysctl_resource_clk_top_axi2 = 70, + sysctl_resource_clk_top_ahb0 = 71, + sysctl_resource_clk_top_dram = 72, + sysctl_resource_clk_top_xpi0 = 73, + sysctl_resource_clk_top_xpi1 = 74, + sysctl_resource_clk_top_gptmr0 = 75, + sysctl_resource_clk_top_gptmr1 = 76, + sysctl_resource_clk_top_gptmr2 = 77, + sysctl_resource_clk_top_gptmr3 = 78, + sysctl_resource_clk_top_gptmr4 = 79, + sysctl_resource_clk_top_gptmr5 = 80, + sysctl_resource_clk_top_gptmr6 = 81, + sysctl_resource_clk_top_gptmr7 = 82, + sysctl_resource_clk_top_uart0 = 83, + sysctl_resource_clk_top_uart1 = 84, + sysctl_resource_clk_top_uart2 = 85, + sysctl_resource_clk_top_uart3 = 86, + sysctl_resource_clk_top_uart4 = 87, + sysctl_resource_clk_top_uart5 = 88, + sysctl_resource_clk_top_uart6 = 89, + sysctl_resource_clk_top_uart7 = 90, + sysctl_resource_clk_top_uart8 = 91, + sysctl_resource_clk_top_uart9 = 92, + sysctl_resource_clk_top_uarta = 93, + sysctl_resource_clk_top_uartb = 94, + sysctl_resource_clk_top_uartc = 95, + sysctl_resource_clk_top_uartd = 96, + sysctl_resource_clk_top_uarte = 97, + sysctl_resource_clk_top_uartf = 98, + sysctl_resource_clk_top_i2c0 = 99, + sysctl_resource_clk_top_i2c1 = 100, + sysctl_resource_clk_top_i2c2 = 101, + sysctl_resource_clk_top_i2c3 = 102, + sysctl_resource_clk_top_spi0 = 103, + sysctl_resource_clk_top_spi1 = 104, + sysctl_resource_clk_top_spi2 = 105, + sysctl_resource_clk_top_spi3 = 106, + sysctl_resource_clk_top_can0 = 107, + sysctl_resource_clk_top_can1 = 108, + sysctl_resource_clk_top_can2 = 109, + sysctl_resource_clk_top_can3 = 110, + sysctl_resource_clk_top_ptpc = 111, + sysctl_resource_clk_top_ana0 = 112, + sysctl_resource_clk_top_ana1 = 113, + sysctl_resource_clk_top_ana2 = 114, + sysctl_resource_clk_top_aud0 = 115, + sysctl_resource_clk_top_aud1 = 116, + sysctl_resource_clk_top_aud2 = 117, + sysctl_resource_clk_top_dis0 = 118, + sysctl_resource_clk_top_cam0 = 119, + sysctl_resource_clk_top_cam1 = 120, + sysctl_resource_clk_top_eth0 = 121, + sysctl_resource_clk_top_eth1 = 122, + sysctl_resource_clk_top_ptp0 = 123, + sysctl_resource_clk_top_ptp1 = 124, + sysctl_resource_clk_top_ref0 = 125, + sysctl_resource_clk_top_ref1 = 126, + sysctl_resource_clk_top_ntmr0 = 127, + sysctl_resource_clk_top_ntmr1 = 128, + sysctl_resource_clk_top_sdxc0 = 129, + sysctl_resource_clk_top_sdxc1 = 130, + sysctl_resource_clk_top_adc0 = 192, + sysctl_resource_clk_top_adc1 = 193, + sysctl_resource_clk_top_adc2 = 194, + sysctl_resource_clk_top_adc3 = 195, + sysctl_resource_clk_top_i2s0 = 196, + sysctl_resource_clk_top_i2s1 = 197, + sysctl_resource_clk_top_i2s2 = 198, + sysctl_resource_clk_top_i2s3 = 199, + + sysctl_resource_linkable_start = 256, + sysctl_resource_ahbp = 256, + sysctl_resource_axis = 257, + sysctl_resource_axic = 258, + sysctl_resource_axiv = 259, + sysctl_resource_dram = 260, + sysctl_resource_rom0 = 261, + sysctl_resource_lmm0 = 262, + sysctl_resource_lmm1 = 263, + sysctl_resource_mchtmr0 = 264, + sysctl_resource_mchtmr1 = 265, + sysctl_resource_ram0 = 266, + sysctl_resource_ram1 = 267, + sysctl_resource_xpi0 = 268, + sysctl_resource_xpi1 = 269, + sysctl_resource_sdp0 = 270, + sysctl_resource_rng0 = 271, + sysctl_resource_kman = 272, + sysctl_resource_dma0 = 273, + sysctl_resource_dma1 = 274, + sysctl_resource_gpio = 275, + sysctl_resource_mbx0 = 276, + sysctl_resource_mbx1 = 277, + sysctl_resource_wdg0 = 278, + sysctl_resource_wdg1 = 279, + sysctl_resource_wdg2 = 280, + sysctl_resource_wdg3 = 281, + sysctl_resource_gptmr0 = 282, + sysctl_resource_gptmr1 = 283, + sysctl_resource_gptmr2 = 284, + sysctl_resource_gptmr3 = 285, + sysctl_resource_gptmr4 = 286, + sysctl_resource_gptmr5 = 287, + sysctl_resource_gptmr6 = 288, + sysctl_resource_gptmr7 = 289, + sysctl_resource_uart0 = 290, + sysctl_resource_uart1 = 291, + sysctl_resource_uart2 = 292, + sysctl_resource_uart3 = 293, + sysctl_resource_uart4 = 294, + sysctl_resource_uart5 = 295, + sysctl_resource_uart6 = 296, + sysctl_resource_uart7 = 297, + sysctl_resource_uart8 = 298, + sysctl_resource_uart9 = 299, + sysctl_resource_uarta = 300, + sysctl_resource_uartb = 301, + sysctl_resource_uartc = 302, + sysctl_resource_uartd = 303, + sysctl_resource_uarte = 304, + sysctl_resource_uartf = 305, + sysctl_resource_i2c0 = 306, + sysctl_resource_i2c1 = 307, + sysctl_resource_i2c2 = 308, + sysctl_resource_i2c3 = 309, + sysctl_resource_spi0 = 310, + sysctl_resource_spi1 = 311, + sysctl_resource_spi2 = 312, + sysctl_resource_spi3 = 313, + sysctl_resource_can0 = 314, + sysctl_resource_can1 = 315, + sysctl_resource_can2 = 316, + sysctl_resource_can3 = 317, + sysctl_resource_ptpc = 318, + sysctl_resource_adc0 = 319, + sysctl_resource_adc1 = 320, + sysctl_resource_adc2 = 321, + sysctl_resource_adc3 = 322, + sysctl_resource_acmp = 323, + sysctl_resource_i2s0 = 324, + sysctl_resource_i2s1 = 325, + sysctl_resource_i2s2 = 326, + sysctl_resource_i2s3 = 327, + sysctl_resource_i2spdm0 = 328, + sysctl_resource_i2sdao = 329, + sysctl_resource_msyn = 330, + sysctl_resource_mot0 = 331, + sysctl_resource_mot1 = 332, + sysctl_resource_mot2 = 333, + sysctl_resource_mot3 = 334, + sysctl_resource_dis0 = 335, + sysctl_resource_cam0 = 336, + sysctl_resource_cam1 = 337, + sysctl_resource_jpeg = 338, + sysctl_resource_pdma = 339, + sysctl_resource_eth0 = 340, + sysctl_resource_eth1 = 341, + sysctl_resource_ntmr0 = 342, + sysctl_resource_ntmr1 = 343, + sysctl_resource_sdxc0 = 344, + sysctl_resource_sdxc1 = 345, + sysctl_resource_usb0 = 346, + sysctl_resource_usb1 = 347, + sysctl_resource_ref0 = 348, + sysctl_resource_ref1 = 349, + sysctl_resource_linkable_end, + sysctl_resource_end = sysctl_resource_linkable_end, +} sysctl_resource_t; + +/** + * @brief Resource modes + */ +typedef enum { + sysctl_resource_mode_auto = 0, + sysctl_resource_mode_force_on, + sysctl_resource_mode_force_off, +} sysctl_resource_mode_t; + +/** + * @brief Clock nodes + */ +typedef enum { + clock_node_cpu0 = 0, + clock_node_mchtmr0 = 1, + clock_node_cpu1 = 2, + clock_node_mchtmr1 = 3, + clock_node_axi0 = 4, + clock_node_axi1 = 5, + clock_node_axi2 = 6, + clock_node_ahb0 = 7, + clock_node_dram = 8, + clock_node_xpi0 = 9, + clock_node_xpi1 = 10, + clock_node_gptmr0 = 11, + clock_node_gptmr1 = 12, + clock_node_gptmr2 = 13, + clock_node_gptmr3 = 14, + clock_node_gptmr4 = 15, + clock_node_gptmr5 = 16, + clock_node_gptmr6 = 17, + clock_node_gptmr7 = 18, + clock_node_uart0 = 19, + clock_node_uart1 = 20, + clock_node_uart2 = 21, + clock_node_uart3 = 22, + clock_node_uart4 = 23, + clock_node_uart5 = 24, + clock_node_uart6 = 25, + clock_node_uart7 = 26, + clock_node_uart8 = 27, + clock_node_uart9 = 28, + clock_node_uarta = 29, + clock_node_uartb = 30, + clock_node_uartc = 31, + clock_node_uartd = 32, + clock_node_uarte = 33, + clock_node_uartf = 34, + clock_node_i2c0 = 35, + clock_node_i2c1 = 36, + clock_node_i2c2 = 37, + clock_node_i2c3 = 38, + clock_node_spi0 = 39, + clock_node_spi1 = 40, + clock_node_spi2 = 41, + clock_node_spi3 = 42, + clock_node_can0 = 43, + clock_node_can1 = 44, + clock_node_can2 = 45, + clock_node_can3 = 46, + clock_node_ptpc = 47, + clock_node_ana0 = 48, + clock_node_ana1 = 49, + clock_node_ana2 = 50, + clock_node_aud0 = 51, + clock_node_aud1 = 52, + clock_node_aud2 = 53, + clock_node_dis0 = 54, + clock_node_cam0 = 55, + clock_node_cam1 = 56, + clock_node_eth0 = 57, + clock_node_eth1 = 58, + clock_node_ptp0 = 59, + clock_node_ptp1 = 60, + clock_node_ref0 = 61, + clock_node_ref1 = 62, + clock_node_ntmr0 = 63, + clock_node_ntmr1 = 64, + clock_node_sdxc0 = 65, + clock_node_sdxc1 = 66, + + clock_node_adc_i2s_start, + clock_node_adc0 = clock_node_adc_i2s_start, + clock_node_adc1, + clock_node_adc2, + clock_node_adc3, + + clock_node_i2s0, + clock_node_i2s1, + clock_node_i2s2, + clock_node_i2s3, + clock_node_end, +} clock_node_t; + +/** + * @brief General clock sources + */ +typedef enum { + clock_source_osc0_clk0 = 0, + clock_source_pll0_clk0 = 1, + clock_source_pll1_clk0 = 2, + clock_source_pll1_clk1 = 3, + clock_source_pll2_clk0 = 4, + clock_source_pll2_clk1 = 5, + clock_source_pll3_clk0 = 6, + clock_source_pll4_clk0 = 7, + clock_source_general_source_end, +} clock_source_t; + +/** + * @brief ADC/I2S clock sources + */ +typedef enum { + clock_source_adc_i2s_ahb_clk = 0, + clock_source_adc_ana0_clk = 1, + clock_source_i2s_aud0_clk = 1, + clock_source_adc_ana1_clk = 2, + clock_source_i2s_aud1_clk = 2, + clock_source_adc_ana2_clk = 3, + clock_source_i2s_aud2_clk = 3, + clock_source_adc_i2s_clk_end, +} clock_source_adc_i2s_t; + +/** + * @brief CPU low power mode + */ +typedef enum { + cpu_lp_mode_gate_cpu_clock = 0, + cpu_lp_mode_trigger_system_lp = 0x1, + cpu_lp_mode_ungate_cpu_clock = 0x2, +} cpu_lp_mode_t; + +/** + * @brief Monitor targets + */ +typedef enum { + monitor_target_clk_32k = 0, + monitor_target_clk_irc24m = 1, + monitor_target_clk_xtal_24m = 2, + monitor_target_clk_usb0_phy = 3, + monitor_target_clk_usb1_phy = 4, + monitor_target_osc0_clk0 = 8, + monitor_target_pll0_clk0 = 9, + monitor_target_pll1_clk0 = 10, + monitor_target_pll1_clk1 = 11, + monitor_target_pll2_clk0 = 12, + monitor_target_pll2_clk1 = 13, + monitor_target_pll3_clk0 = 14, + monitor_target_pll4_clk0 = 15, + monitor_target_clk_top_cpu0 = 128, + monitor_target_clk_top_mchtmr0 = 129, + monitor_target_clk_top_cpu1 = 130, + monitor_target_clk_top_mchtmr1 = 131, + monitor_target_clk_top_axi0 = 132, + monitor_target_clk_top_axi1 = 133, + monitor_target_clk_top_axi2 = 134, + monitor_target_clk_top_ahb0 = 135, + monitor_target_clk_top_dram = 136, + monitor_target_clk_top_xpi0 = 137, + monitor_target_clk_top_xpi1 = 138, + monitor_target_clk_top_gptmr0 = 139, + monitor_target_clk_top_gptmr1 = 140, + monitor_target_clk_top_gptmr2 = 141, + monitor_target_clk_top_gptmr3 = 142, + monitor_target_clk_top_gptmr4 = 143, + monitor_target_clk_top_gptmr5 = 144, + monitor_target_clk_top_gptmr6 = 145, + monitor_target_clk_top_gptmr7 = 146, + monitor_target_clk_top_uart0 = 147, + monitor_target_clk_top_uart1 = 148, + monitor_target_clk_top_uart2 = 149, + monitor_target_clk_top_uart3 = 150, + monitor_target_clk_top_uart4 = 151, + monitor_target_clk_top_uart5 = 152, + monitor_target_clk_top_uart6 = 153, + monitor_target_clk_top_uart7 = 154, + monitor_target_clk_top_uart8 = 155, + monitor_target_clk_top_uart9 = 156, + monitor_target_clk_top_uarta = 157, + monitor_target_clk_top_uartb = 158, + monitor_target_clk_top_uartc = 159, + monitor_target_clk_top_uartd = 160, + monitor_target_clk_top_uarte = 161, + monitor_target_clk_top_uartf = 162, + monitor_target_clk_top_i2c0 = 163, + monitor_target_clk_top_i2c1 = 164, + monitor_target_clk_top_i2c2 = 165, + monitor_target_clk_top_i2c3 = 166, + monitor_target_clk_top_spi0 = 167, + monitor_target_clk_top_spi1 = 168, + monitor_target_clk_top_spi2 = 169, + monitor_target_clk_top_spi3 = 170, + monitor_target_clk_top_can0 = 171, + monitor_target_clk_top_can1 = 172, + monitor_target_clk_top_can2 = 173, + monitor_target_clk_top_can3 = 174, + monitor_target_clk_top_ptpc = 175, + monitor_target_clk_top_ana0 = 176, + monitor_target_clk_top_ana1 = 177, + monitor_target_clk_top_ana2 = 178, + monitor_target_clk_top_aud0 = 179, + monitor_target_clk_top_aud1 = 180, + monitor_target_clk_top_aud2 = 181, + monitor_target_clk_top_dis0 = 182, + monitor_target_clk_top_cam0 = 183, + monitor_target_clk_top_cam1 = 184, + monitor_target_clk_top_eth0 = 185, + monitor_target_clk_top_eth1 = 186, + monitor_target_clk_top_ptp0 = 187, + monitor_target_clk_top_ptp1 = 188, + monitor_target_clk_top_ref0 = 189, + monitor_target_clk_top_ref1 = 190, + monitor_target_clk_top_ntmr0 = 191, + monitor_target_clk_top_ntmr1 = 192, + monitor_target_clk_top_sdxc0 = 193, + monitor_target_clk_top_sdxc1 = 194, +} monitor_target_t; + +/** + * @brief Monitor work mode + */ +typedef enum { + monitor_work_mode_compare = 0, + monitor_work_mode_record = 1, +} monitor_work_mode_t; + +/** + * @brief Monitor accuracy + */ +typedef enum { + monitor_accuracy_1khz = 0, + monitor_accuracy_1hz = 1, +} monitor_accuracy_t; + +/** + * @brief Monitor reference clock source + */ +typedef enum { + monitor_reference_32khz = 0, + monitor_reference_24mhz = 1, +} monitor_reference_t; + +/** + * @brief Monitor config + */ +typedef struct monitor_config { + uint8_t divide_by; /**< Divider to be used for OBS output to pads */ + monitor_work_mode_t mode; /**< Monitor work mode */ + monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ + monitor_reference_t reference; /**< Monitor reference clock source */ + monitor_target_t target; /**< Monitor target */ + bool start_measure; /**< Start flag */ + bool enable_output; /**< Enable output to pads if true */ + uint32_t high_limit; /**< Maximum frequency at compare mode */ + uint32_t low_limit; /**< Minimum frequency at compare mode */ +} monitor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if monitor result is valid + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * + * @return true if it is valid + */ +static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); +} + +/** + * @brief Get target monitor instance result + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return value of monitor result measured + */ +static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, + uint8_t monitor_index) +{ + while(!sysctl_monitor_result_is_valid(ptr, monitor_index)); + return ptr->MONITOR[monitor_index].CURRENT; +} + +/** + * @brief Set work mode for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record + */ +static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_work_mode_t mode) +{ + ptr->MONITOR[monitor_index].CONTROL = + (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) + | (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); +} + +/** + * @brief Set minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, + uint8_t monitor_index, + uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement high limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, + uint8_t monitor_index, + uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set frequency limit for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit_high measurement high limit + * @param[in] limit_low measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, + uint8_t monitor_index, + uint32_t limit_high, + uint32_t limit_low) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); + return status_success; +} + +/** + * @brief Get maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current high limit value + */ +static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); +} + +/** + * @brief Get minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current low limit value + */ +static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); +} + +/** + * @brief Measure specific target frequency + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] target monitor target to be measured + * @param[in] enable_output enable clock obs output + * @return frequency of monitor target measured + */ +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output); + +/** + * @brief Link current CPU core its own group + * + * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; +} + +/** + * @brief Unlink current CPU core with its own group + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; +} + +/** + * @brief Check if any resource is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any resource is busy + */ +static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; +} + +/** + * @brief Check if specific target is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return true if target resource is busy + */ +static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; +} + +/** + * @brief Set target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @param[in] mode target resource mode + */ +static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource, + sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = + (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | + SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Disable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to clear + */ +static inline void sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint32_t mask) +{ + ptr->RETENTION[cpu_index].CLEAR = mask; +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to set + */ +static inline void sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint32_t mask) +{ + ptr->RETENTION[cpu_index].SET = mask; +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_cpu_lp_retain_domain(SYSCTL_Type *ptr, + uint8_t cpu_index, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + uint8_t set_mask = 0x1; + if (domain < sysctl_retention_domain_xtal24m) { + set_mask = retain_mem ? 0x3 : 0x1; + } + ptr->RETENTION[cpu_index].SET = (set_mask << domain); +} + +/** + * @brief Check if any clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; +} + +/** + * @brief Check if target clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + * @return true if target clock is busy + */ +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, + uint32_t clock) +{ + return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; +} + +/** + * @brief Set clock preset + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] preset preset + */ +static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, + sysctl_preset_t preset) +{ + ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_PRESET_MASK) + | SYSCTL_GLOBAL00_PRESET_SET(preset); +} + +/** + * @brief Check if target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken wakeup reset + */ +static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, + sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, + sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken reset + */ +static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, + sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, + sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain for all reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, + sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Get target CPU wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t status_index) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; +} + +/** + * @brief Check wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline + uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t status_index, + uint32_t mask) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; +} + +/** + * @brief Enable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline + void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Disable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline + void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; +} + +/** + * @brief Disable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); +} + +/** + * @brief Enable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num % 32); +} + +/** + * @brief Lock CPU0 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, + uint16_t gpr_mask) +{ + ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + +/** + * @brief Lock CPU1 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, + uint16_t gpr_mask) +{ + ptr->CPU[1].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + +/** + * @brief Lock CPU0 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) +{ + ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; +} + +/** + * @brief Lock CPU1 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr) +{ + ptr->CPU[1].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; +} + +/** + * @brief Config lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @param[in] divide_by clock frequency divider + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, + clock_node_t node, + clock_source_t source, + uint32_t divide_by); + +/** + * @brief Set ADC/I2S clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, + clock_node_t node, + clock_source_adc_i2s_t source); + +/** + * @brief Set CPU low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mode target mode to set + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, + uint8_t cpu_index, + cpu_lp_mode_t mode); + +/** + * @brief Enable group resource + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be modified + * @param[in] resource target resource to be added/removed from group + * @param[in] enable set true to add resource, remove otherwise + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource, + bool enable); +/** + * @brief Add resource to CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource resource to be added to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Add resource to CPU1 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be added to CPU1 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU1 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU1 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Get default monitor config + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); + +/** + * @brief Initialize Monitor + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index Monitor instance to be initialized + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_init(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_config_t *config); + +/** + * @brief Save data to GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, + uint8_t start, + uint8_t count, + uint32_t *data, + bool lock); + +/** + * @brief Get data saved from GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, + uint8_t start, + uint8_t count, + uint32_t *data); + +/** + * @brief Set data to CPU1 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, + uint8_t start, + uint8_t count, + uint32_t *data, + bool lock); + +/** + * @brief Get data saved in CPU1 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, + uint8_t start, + uint8_t count, + uint32_t *data); +/** + * @brief Release cpu1 + * + * @param[in] ptr SYSCTL_Type base address + */ +void sysctl_release_cpu1(SYSCTL_Type *ptr); + +/** + * @brief Check whether CPU1 is released or not + * + * @param [in] ptr SYSCTL_Type base address + * @retval true CPU1 is released + * @retval false CPU1 is on-hold + */ +bool sysctl_is_cpu1_released(SYSCTL_Type *ptr); + +/** + * @brief Set entry point on CPU0 wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU0 on its wakeup + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); + +/** + * @brief Set entry point on either CPU1 boot or wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU1 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h new file mode 100644 index 0000000000..48e2316b6c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h @@ -0,0 +1,1331 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SYSCTL_H +#define HPM_SYSCTL_H + +typedef struct { + __RW uint32_t RESOURCE[350]; /* 0x0 - 0x574: Resource control register for cpu0 */ + __R uint8_t RESERVED0[648]; /* 0x578 - 0x7FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x800: Goup setting */ + __RW uint32_t SET; /* 0x804: Goup setting */ + __RW uint32_t CLEAR; /* 0x808: Goup setting */ + __RW uint32_t TOGGLE; /* 0x80C: Goup setting */ + } GROUP0[3]; + __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x840: Goup setting */ + __RW uint32_t SET; /* 0x844: Goup setting */ + __RW uint32_t CLEAR; /* 0x848: Goup setting */ + __RW uint32_t TOGGLE; /* 0x84C: Goup setting */ + } GROUP1[3]; + __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ + __RW uint32_t SET; /* 0x904: Affiliate of Group */ + __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ + __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ + } AFFILIATE[2]; + struct { + __RW uint32_t VALUE; /* 0x920: Retention Contol */ + __RW uint32_t SET; /* 0x924: Retention Contol */ + __RW uint32_t CLEAR; /* 0x928: Retention Contol */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ + } RETENTION[2]; + __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */ + struct { + __RW uint32_t STATUS; /* 0x1000: Power Setting */ + __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ + __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ + __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ + } POWER[4]; + __R uint8_t RESERVED4[960]; /* 0x1040 - 0x13FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ + __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ + __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ + __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ + } RESET[5]; + __R uint8_t RESERVED5[944]; /* 0x1450 - 0x17FF: Reserved */ + __RW uint32_t CLOCK[67]; /* 0x1800 - 0x1908: Clock setting */ + __R uint8_t RESERVED6[756]; /* 0x190C - 0x1BFF: Reserved */ + __RW uint32_t ADCCLK[4]; /* 0x1C00 - 0x1C0C: Clock setting */ + __RW uint32_t I2SCLK[4]; /* 0x1C10 - 0x1C1C: Clock setting */ + __R uint8_t RESERVED7[992]; /* 0x1C20 - 0x1FFF: Reserved */ + __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ + __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ + __R uint32_t CURRENT; /* 0x2404: Clock measure result */ + __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ + __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ + __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ + } MONITOR[4]; + __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ + struct { + __RW uint32_t LP; /* 0x2800: */ + __RW uint32_t LOCK; /* 0x2804: */ + __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: */ + __R uint32_t WAKEUP_STATUS[8]; /* 0x2840 - 0x285C: */ + __R uint8_t RESERVED0[32]; /* 0x2860 - 0x287F: Reserved */ + __RW uint32_t WAKEUP_ENABLE[8]; /* 0x2880 - 0x289C: */ + __R uint8_t RESERVED1[864]; /* 0x28A0 - 0x2BFF: Reserved */ + } CPU[2]; +} SYSCTL_Type; + + +/* Bitfield definition for register array: RESOURCE */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any nodes + * 1: any of nodes is changing status + */ +#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) +#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: no change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) +#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) + +/* + * MODE (RW) + * + * resource work mode + * 0:auto turn on and off as system required(recommended) + * 1:always on + * 2:always off + * 3:reserved + */ +#define SYSCTL_RESOURCE_MODE_MASK (0x3U) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) +#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) +#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) +#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) +#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK) +#define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK) +#define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK) +#define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: VALUE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0 + * bit0: cpu0 depends on logic node0 + * bit1: cpu0 depends on logic node1 + * bit2: cpu0 depends on logic node2 + * bit3: cpu0 depends on logic node3 + */ +#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) +#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: SET */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0 + * bit0: cpu0 depends on logic node0 + * bit1: cpu0 depends on logic node1 + * bit2: cpu0 depends on logic node2 + * bit3: cpu0 depends on logic node3 + */ +#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) +#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0 + * bit0: cpu0 depends on logic node0 + * bit1: cpu0 depends on logic node1 + * bit2: cpu0 depends on logic node2 + * bit3: cpu0 depends on logic node3 + */ +#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) +#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0 + * bit0: cpu0 depends on logic node0 + * bit1: cpu0 depends on logic node1 + * bit2: cpu0 depends on logic node2 + * bit3: cpu0 depends on logic node3 + */ +#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: VALUE */ +/* + * LINK (RW) + * + * retention setting while system sleep, each bit represents a resource + * bit0: soc_pow + * bit1: soc_rst + * bit2: cpu0_pow + * bit3: cpu0_rst + * bit4: cpu1_pow + * bit5: cpu1_rst + * bit6: con_pow + * bit7: con_rst + * bit8: vis_pow + * bit9: vis_rst + * bit10: xtal + * bit11: pll0 + * bit12: pll1 + * bit13: pll2 + * bit14: pll3 + * bit15: pll4 + */ +#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x3FFFFUL) +#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) +#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: SET */ +/* + * LINK (RW) + * + * retention setting while system sleep + */ +#define SYSCTL_RETENTION_SET_LINK_MASK (0x3FFFFUL) +#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) +#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: CLEAR */ +/* + * LINK (RW) + * + * retention setting while system sleep + */ +#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x3FFFFUL) +#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) +#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: TOGGLE */ +/* + * LINK (RW) + * + * retention setting while system sleep + */ +#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x3FFFFUL) +#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) +#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array POWER: STATUS */ +/* + * FLAG (RW) + * + * flag represents power cycle happened from last clear of this bit + * 0: power domain did not edurance power cycle since last clear of this bit + * 1: power domain enduranced power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) +#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) +#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) +#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup power cycle happened from last clear of this bit + * 0: power domain did not edurance wakeup power cycle since last clear of this bit + * 1: power domain enduranced wakeup power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) + +/* + * LF_DISABLE (RO) + * + * low fanout power switch disable + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) + +/* + * LF_ACK (RO) + * + * low fanout power switch feedback + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) +#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) +#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) + +/* Bitfield definition for register of struct array POWER: LF_WAIT */ +/* + * WAIT (RW) + * + * wait time for low fan out power switch turn on, default value is 255 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: OFF_WAIT */ +/* + * WAIT (RW) + * + * wait time for power switch turn off, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONTROL */ +/* + * FLAG (RW) + * + * flag represents reset happened from last clear of this bit + * 0: domain did not edurance reset cycle since last clear of this bit + * 1: domain enduranced reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) +#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup reset happened from last clear of this bit + * 0: domain did not edurance wakeup reset cycle since last clear of this bit + * 1: domain enduranced wakeup reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) + +/* + * HOLD (RW) + * + * perform reset and hold in reset, until ths bit cleared by software + * 0: reset is released for function + * 1: reset is assert and hold + */ +#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) +#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) +#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) +#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) + +/* + * RESET (RW) + * + * perform reset and release imediately + * 0: reset is released + * 1 reset is asserted and will release automaticly + */ +#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) +#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) +#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) +#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONFIG */ +/* + * PRE_WAIT (RW) + * + * wait cycle numbers before assert reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) + +/* + * RSTCLK_NUM (RW) + * + * reset clock number(must be even number) + * 0: 0 cycle + * 1: 0 cycles + * 2: 2 cycles + * 3: 2 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) + +/* + * POST_WAIT (RW) + * + * time guard band for reset release + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: COUNTER */ +/* + * COUNTER (RW) + * + * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) +#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) +#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +/* Bitfield definition for register array: CLOCK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) + +/* + * MUX (RW) + * + * clock source selection + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll1_clk0 + * 3:pll1_clk1 + * 4:pll2_clk0 + * 5:pll2_clk1 + * 6:pll3_clk0 + * 7:pll4_clk0 + */ +#define SYSCTL_CLOCK_MUX_MASK (0xF00U) +#define SYSCTL_CLOCK_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) +#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by1 + * 1: divider by 2 + * 2 divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) +#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) + +/* Bitfield definition for register array: ADCCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) + +/* + * MUX (RW) + * + * clock source selection + * 0: ahb clock + * 1: adc clock 0 + * 2: adc clock 1 + * 3: adc clock 2 + */ +#define SYSCTL_ADCCLK_MUX_MASK (0x700U) +#define SYSCTL_ADCCLK_MUX_SHIFT (8U) +#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) +#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) + +/* Bitfield definition for register array: I2SCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT) + +/* + * MUX (RW) + * + * clock source selection + * 0: ahb clock + * 1: i2s clock 0 + * 2: i2s clock 1 + * 3: i2s clock 2 + */ +#define SYSCTL_I2SCLK_MUX_MASK (0x700U) +#define SYSCTL_I2SCLK_MUX_SHIFT (8U) +#define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK) +#define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT) + +/* Bitfield definition for register: GLOBAL00 */ +/* + * PRESET (RW) + * + * global clock override request + * bit0: override to preset0 + * bit1: override to preset1 + * bit2: override to preset2 + * bit3: override to preset3 + */ +#define SYSCTL_GLOBAL00_PRESET_MASK (0xFU) +#define SYSCTL_GLOBAL00_PRESET_SHIFT (0U) +#define SYSCTL_GLOBAL00_PRESET_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_PRESET_SHIFT) & SYSCTL_GLOBAL00_PRESET_MASK) +#define SYSCTL_GLOBAL00_PRESET_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_PRESET_MASK) >> SYSCTL_GLOBAL00_PRESET_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * VALID (RW) + * + * result is ready for read + * 0: not ready + * 1: result is ready + */ +#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) +#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) +#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) +#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) + +/* + * DIV_BUSY (RO) + * + * divider is applying new setting + */ +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) + +/* + * OUTEN (RW) + * + * enable clock output + */ +#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) +#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) + +/* + * DIV (RW) + * + * output divider + */ +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) +#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) +#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) + +/* + * HIGH (RW) + * + * clock frequency higher than upper limit + */ +#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) +#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) + +/* + * LOW (RW) + * + * clock frequency lower than lower limit + */ +#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) +#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) +#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) +#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) + +/* + * START (RW) + * + * start measurement + */ +#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) +#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) +#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) +#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) + +/* + * MODE (RW) + * + * work mode, + * 0: register value will be compared to measurement + * 1: upper and lower value will be recordered in register + */ +#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) +#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) +#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) +#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) + +/* + * ACCURACY (RW) + * + * measurement accuracy, + * 0: resolution is 1kHz + * 1: resolution is 1Hz + */ +#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) + +/* + * REFERENCE (RW) + * + * refrence clock selection, + * 0: 32k + * 1: 24M + */ +#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) + +/* + * SELECTION (RW) + * + * clock measurement selection + */ +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) +#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CURRENT */ +/* + * FREQUENCY (RO) + * + * self updating measure result + */ +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ +/* + * FREQUENCY (RW) + * + * lower frequency + */ +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ +/* + * FREQUENCY (RW) + * + * upper frequency + */ +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array CPU: LP */ +/* + * WAKE_CNT (RW) + * + * CPU0 wake up counter, counter saturated at 255, write 0x00 to clear + */ +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) +#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) +#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) + +/* + * HALT (RW) + * + * halt request for CPU0, + * 0: CPU0 will start to execute after reset or receive wakeup request + * 1: CPU0 will not start after reset, or wakeup after WFI + */ +#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) +#define SYSCTL_CPU_LP_HALT_SHIFT (16U) +#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) +#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) + +/* + * WAKE (RO) + * + * CPU0 is waking up + * 0: CPU0 wake up not asserted + * 1: CPU0 wake up asserted + */ +#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) +#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) +#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) + +/* + * EXEC (RO) + * + * CPU0 is executing + * 0: CPU0 is not executing + * 1: CPU0 is executing + */ +#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) +#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) +#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) + +/* + * WAKE_FLAG (RW) + * + * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit + * 0: CPU0 wakeup not happened + * 1: CPU0 wakeup happened + */ +#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) +#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) + +/* + * SLEEP_FLAG (RW) + * + * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit + * 0: CPU0 sleep not happened + * 1: CPU0 sleep happened + */ +#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) +#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) + +/* + * RESET_FLAG (RW) + * + * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit + * 0: CPU0 sleep not happened + * 1: CPU0 sleep happened + */ +#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) +#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) +#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) +#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) + +/* + * MODE (RW) + * + * Low power mode, system behavior after WFI + * 00: CPU clock stop after WFI + * 01: System enter low power mode after WFI + * 10: Keep running after WFI + * 11: reserved + */ +#define SYSCTL_CPU_LP_MODE_MASK (0x3U) +#define SYSCTL_CPU_LP_MODE_SHIFT (0U) +#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) +#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) + +/* Bitfield definition for register of struct array CPU: LOCK */ +/* + * GPR (RW) + * + * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + */ +#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) +#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) +#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) + +/* + * LOCK (RW) + * + * Lock bit for CPU_LOCK + */ +#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) +#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) +#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) +#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register of struct array CPU: GPR0 */ +/* + * GPR (RW) + * + * register for software to handle resume, can save resume address or status + */ +#define SYSCTL_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_GPR_GPR_SHIFT (0U) +#define SYSCTL_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_GPR_GPR_SHIFT) & SYSCTL_GPR_GPR_MASK) +#define SYSCTL_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_GPR_GPR_MASK) >> SYSCTL_GPR_GPR_SHIFT) + +/* Bitfield definition for register of struct array CPU: STATUS0 */ +/* + * STATUS (RO) + * + * IRQ values + */ +#define SYSCTL_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_WAKEUP_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register of struct array CPU: ENABLE0 */ +/* + * ENABLE (RW) + * + * IRQ wakeup enable + */ +#define SYSCTL_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_WAKEUP_ENABLE_ENABLE_SHIFT) + + + +/* RESOURCE register group index macro definition */ +#define SYSCTL_RESOURCE_CPU0_CORE (0UL) +#define SYSCTL_RESOURCE_CPU0_SUBSYS (1UL) +#define SYSCTL_RESOURCE_CPU1_CORE (8UL) +#define SYSCTL_RESOURCE_CPX1_SUBSYS (9UL) +#define SYSCTL_RESOURCE_POW_CON (21UL) +#define SYSCTL_RESOURCE_POW_VIS (22UL) +#define SYSCTL_RESOURCE_POW_CPU0 (23UL) +#define SYSCTL_RESOURCE_POW_CPU1 (24UL) +#define SYSCTL_RESOURCE_RST_SOC (25UL) +#define SYSCTL_RESOURCE_RST_CON (26UL) +#define SYSCTL_RESOURCE_RST_VIS (27UL) +#define SYSCTL_RESOURCE_RST_CPU0 (28UL) +#define SYSCTL_RESOURCE_RST_CPU1 (29UL) +#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0CLK0 (34UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (35UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1CLK0 (36UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1CLK1 (37UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (38UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2CLK0 (39UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2CLK1 (40UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL3 (41UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL3CLK0 (42UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL4 (43UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL4CLK0 (44UL) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCHTMR0 (65UL) +#define SYSCTL_RESOURCE_CLK_TOP_CPU1 (66UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCHTMR1 (67UL) +#define SYSCTL_RESOURCE_CLK_TOP_AXI (68UL) +#define SYSCTL_RESOURCE_CLK_TOP_CONN (69UL) +#define SYSCTL_RESOURCE_CLK_TOP_VIS (70UL) +#define SYSCTL_RESOURCE_CLK_TOP_AHB (71UL) +#define SYSCTL_RESOURCE_CLK_TOP_DRAM (72UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (73UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI1 (74UL) +#define SYSCTL_RESOURCE_CLK_TOP_GPTMR0 (75UL) +#define SYSCTL_RESOURCE_CLK_TOP_GPTMR1 (76UL) +#define SYSCTL_RESOURCE_CLK_TOP_GPTMR2 (77UL) +#define SYSCTL_RESOURCE_CLK_TOP_GPTMR3 (78UL) +#define SYSCTL_RESOURCE_CLK_TOP_GPTMR4 (79UL) +#define SYSCTL_RESOURCE_CLK_TOP_GPTMR5 (80UL) +#define SYSCTL_RESOURCE_CLK_TOP_GPTMR6 (81UL) +#define SYSCTL_RESOURCE_CLK_TOP_GPTMR7 (82UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART0 (83UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART1 (84UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART2 (85UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART3 (86UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART4 (87UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART5 (88UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART6 (89UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART7 (90UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART8 (91UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART9 (92UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART10 (93UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART11 (94UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART12 (95UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART13 (96UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART14 (97UL) +#define SYSCTL_RESOURCE_CLK_TOP_UART15 (98UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (99UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (100UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (101UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (102UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (103UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (104UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (105UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (106UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (107UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (108UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (109UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (110UL) +#define SYSCTL_RESOURCE_CLK_TOP_PTPC (111UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (112UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (113UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (114UL) +#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (115UL) +#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (116UL) +#define SYSCTL_RESOURCE_CLK_TOP_AUD2 (117UL) +#define SYSCTL_RESOURCE_CLK_TOP_LCDC (118UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAM0 (119UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAM1 (120UL) +#define SYSCTL_RESOURCE_CLK_TOP_ENET0 (121UL) +#define SYSCTL_RESOURCE_CLK_TOP_ENET1 (122UL) +#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (123UL) +#define SYSCTL_RESOURCE_CLK_TOP_PTP1 (124UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (125UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (126UL) +#define SYSCTL_RESOURCE_CLK_TOP_NTMR0 (127UL) +#define SYSCTL_RESOURCE_CLK_TOP_NTMR1 (128UL) +#define SYSCTL_RESOURCE_CLK_TOP_SDXC0 (129UL) +#define SYSCTL_RESOURCE_CLK_TOP_SDXC1 (130UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (192UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (193UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (194UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC3 (195UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (196UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (197UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S2 (198UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2S3 (199UL) +#define SYSCTL_RESOURCE_AHBAPB_BUS (256UL) +#define SYSCTL_RESOURCE_AXI_BUS (257UL) +#define SYSCTL_RESOURCE_CONN_BUS (258UL) +#define SYSCTL_RESOURCE_VIS_BUS (259UL) +#define SYSCTL_RESOURCE_DRAM (260UL) +#define SYSCTL_RESOURCE_ROM (261UL) +#define SYSCTL_RESOURCE_LMM0 (262UL) +#define SYSCTL_RESOURCE_LMM1 (263UL) +#define SYSCTL_RESOURCE_MCHTMR0 (264UL) +#define SYSCTL_RESOURCE_MCHTMR1 (265UL) +#define SYSCTL_RESOURCE_AXI_SRAM0 (266UL) +#define SYSCTL_RESOURCE_AXI_SRAM1 (267UL) +#define SYSCTL_RESOURCE_XPI0 (268UL) +#define SYSCTL_RESOURCE_XPI1 (269UL) +#define SYSCTL_RESOURCE_SDP (270UL) +#define SYSCTL_RESOURCE_RNG (271UL) +#define SYSCTL_RESOURCE_KEYM (272UL) +#define SYSCTL_RESOURCE_HDMA (273UL) +#define SYSCTL_RESOURCE_XDMA (274UL) +#define SYSCTL_RESOURCE_GPIO (275UL) +#define SYSCTL_RESOURCE_MBX0 (276UL) +#define SYSCTL_RESOURCE_MBX1 (277UL) +#define SYSCTL_RESOURCE_WDG0 (278UL) +#define SYSCTL_RESOURCE_WDG1 (279UL) +#define SYSCTL_RESOURCE_WDG2 (280UL) +#define SYSCTL_RESOURCE_WDG3 (281UL) +#define SYSCTL_RESOURCE_GPTMR0 (282UL) +#define SYSCTL_RESOURCE_GPTMR1 (283UL) +#define SYSCTL_RESOURCE_GPTMR2 (284UL) +#define SYSCTL_RESOURCE_GPTMR3 (285UL) +#define SYSCTL_RESOURCE_GPTMR4 (286UL) +#define SYSCTL_RESOURCE_GPTMR5 (287UL) +#define SYSCTL_RESOURCE_GPTMR6 (288UL) +#define SYSCTL_RESOURCE_GPTMR7 (289UL) +#define SYSCTL_RESOURCE_UART0 (290UL) +#define SYSCTL_RESOURCE_UART1 (291UL) +#define SYSCTL_RESOURCE_UART2 (292UL) +#define SYSCTL_RESOURCE_UART3 (293UL) +#define SYSCTL_RESOURCE_UART4 (294UL) +#define SYSCTL_RESOURCE_UART5 (295UL) +#define SYSCTL_RESOURCE_UART6 (296UL) +#define SYSCTL_RESOURCE_UART7 (297UL) +#define SYSCTL_RESOURCE_UART8 (298UL) +#define SYSCTL_RESOURCE_UART9 (299UL) +#define SYSCTL_RESOURCE_UART10 (300UL) +#define SYSCTL_RESOURCE_UART11 (301UL) +#define SYSCTL_RESOURCE_UART12 (302UL) +#define SYSCTL_RESOURCE_UART13 (303UL) +#define SYSCTL_RESOURCE_UART14 (304UL) +#define SYSCTL_RESOURCE_UART15 (305UL) +#define SYSCTL_RESOURCE_I2C0 (306UL) +#define SYSCTL_RESOURCE_I2C1 (307UL) +#define SYSCTL_RESOURCE_I2C2 (308UL) +#define SYSCTL_RESOURCE_I2C3 (309UL) +#define SYSCTL_RESOURCE_SPI0 (310UL) +#define SYSCTL_RESOURCE_SPI1 (311UL) +#define SYSCTL_RESOURCE_SPI2 (312UL) +#define SYSCTL_RESOURCE_SPI3 (313UL) +#define SYSCTL_RESOURCE_CAN0 (314UL) +#define SYSCTL_RESOURCE_CAN1 (315UL) +#define SYSCTL_RESOURCE_CAN2 (316UL) +#define SYSCTL_RESOURCE_CAN3 (317UL) +#define SYSCTL_RESOURCE_PTPC (318UL) +#define SYSCTL_RESOURCE_ADC0 (319UL) +#define SYSCTL_RESOURCE_ADC1 (320UL) +#define SYSCTL_RESOURCE_ADC2 (321UL) +#define SYSCTL_RESOURCE_ADC3 (322UL) +#define SYSCTL_RESOURCE_ACMP (323UL) +#define SYSCTL_RESOURCE_I2S0 (324UL) +#define SYSCTL_RESOURCE_I2S1 (325UL) +#define SYSCTL_RESOURCE_I2S2 (326UL) +#define SYSCTL_RESOURCE_I2S3 (327UL) +#define SYSCTL_RESOURCE_PDM (328UL) +#define SYSCTL_RESOURCE_DAO (329UL) +#define SYSCTL_RESOURCE_SYNT (330UL) +#define SYSCTL_RESOURCE_MOT0 (331UL) +#define SYSCTL_RESOURCE_MOT1 (332UL) +#define SYSCTL_RESOURCE_MOT2 (333UL) +#define SYSCTL_RESOURCE_MOT3 (334UL) +#define SYSCTL_RESOURCE_LCDC (335UL) +#define SYSCTL_RESOURCE_CAM0 (336UL) +#define SYSCTL_RESOURCE_CAM1 (337UL) +#define SYSCTL_RESOURCE_JPEG (338UL) +#define SYSCTL_RESOURCE_PDMA (339UL) +#define SYSCTL_RESOURCE_ENET0 (340UL) +#define SYSCTL_RESOURCE_ENET1 (341UL) +#define SYSCTL_RESOURCE_NTMR0 (342UL) +#define SYSCTL_RESOURCE_NTMR1 (343UL) +#define SYSCTL_RESOURCE_SDXC0 (344UL) +#define SYSCTL_RESOURCE_SDXC1 (345UL) +#define SYSCTL_RESOURCE_USB0 (346UL) +#define SYSCTL_RESOURCE_USB1 (347UL) +#define SYSCTL_RESOURCE_REF0 (348UL) +#define SYSCTL_RESOURCE_REF1 (349UL) + +/* GROUP0 register group index macro definition */ +#define SYSCTL_GROUP0_0 (0UL) +#define SYSCTL_GROUP0_1 (1UL) +#define SYSCTL_GROUP0_2 (2UL) + +/* GROUP1 register group index macro definition */ +#define SYSCTL_GROUP1_0 (0UL) +#define SYSCTL_GROUP1_1 (1UL) +#define SYSCTL_GROUP1_2 (2UL) + +/* AFFILIATE register group index macro definition */ +#define SYSCTL_AFFILIATE_CPU0 (0UL) +#define SYSCTL_AFFILIATE_CPU1 (1UL) + +/* RETENTION register group index macro definition */ +#define SYSCTL_RETENTION_CPU0 (0UL) +#define SYSCTL_RETENTION_CPU1 (1UL) + +/* POWER register group index macro definition */ +#define SYSCTL_POWER_CPU0 (0UL) +#define SYSCTL_POWER_CPU1 (1UL) +#define SYSCTL_POWER_CON (2UL) +#define SYSCTL_POWER_VIS (3UL) + +/* RESET register group index macro definition */ +#define SYSCTL_RESET_SOC (0UL) +#define SYSCTL_RESET_CON (1UL) +#define SYSCTL_RESET_VIS (2UL) +#define SYSCTL_RESET_CPU0 (3UL) +#define SYSCTL_RESET_CPU1 (4UL) + +/* CLOCK register group index macro definition */ +#define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL) +#define SYSCTL_CLOCK_CLK_TOP_MCHTMR0 (1UL) +#define SYSCTL_CLOCK_CLK_TOP_CPU1 (2UL) +#define SYSCTL_CLOCK_CLK_TOP_MCHTMR (3UL) +#define SYSCTL_CLOCK_CLK_TOP_AXI (4UL) +#define SYSCTL_CLOCK_CLK_TOP_CONN (5UL) +#define SYSCTL_CLOCK_CLK_TOP_VIS (6UL) +#define SYSCTL_CLOCK_CLK_TOP_AHB (7UL) +#define SYSCTL_CLOCK_CLK_TOP_DRAM (8UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI0 (9UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI1 (10UL) +#define SYSCTL_CLOCK_CLK_TOP_GPTMR0 (11UL) +#define SYSCTL_CLOCK_CLK_TOP_GPTMR1 (12UL) +#define SYSCTL_CLOCK_CLK_TOP_GPTMR2 (13UL) +#define SYSCTL_CLOCK_CLK_TOP_GPTMR3 (14UL) +#define SYSCTL_CLOCK_CLK_TOP_GPTMR4 (15UL) +#define SYSCTL_CLOCK_CLK_TOP_GPTMR5 (16UL) +#define SYSCTL_CLOCK_CLK_TOP_GPTMR6 (17UL) +#define SYSCTL_CLOCK_CLK_TOP_GPTMR7 (18UL) +#define SYSCTL_CLOCK_CLK_TOP_UART0 (19UL) +#define SYSCTL_CLOCK_CLK_TOP_UART1 (20UL) +#define SYSCTL_CLOCK_CLK_TOP_UART2 (21UL) +#define SYSCTL_CLOCK_CLK_TOP_UART3 (22UL) +#define SYSCTL_CLOCK_CLK_TOP_UART4 (23UL) +#define SYSCTL_CLOCK_CLK_TOP_UART5 (24UL) +#define SYSCTL_CLOCK_CLK_TOP_UART6 (25UL) +#define SYSCTL_CLOCK_CLK_TOP_UART7 (26UL) +#define SYSCTL_CLOCK_CLK_TOP_UART8 (27UL) +#define SYSCTL_CLOCK_CLK_TOP_UART9 (28UL) +#define SYSCTL_CLOCK_CLK_TOP_UART10 (29UL) +#define SYSCTL_CLOCK_CLK_TOP_UART11 (30UL) +#define SYSCTL_CLOCK_CLK_TOP_UART12 (31UL) +#define SYSCTL_CLOCK_CLK_TOP_UART13 (32UL) +#define SYSCTL_CLOCK_CLK_TOP_UART14 (33UL) +#define SYSCTL_CLOCK_CLK_TOP_UART15 (34UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C0 (35UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C1 (36UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C2 (37UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C3 (38UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI0 (39UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI1 (40UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI2 (41UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI3 (42UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN0 (43UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN1 (44UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN2 (45UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN3 (46UL) +#define SYSCTL_CLOCK_CLK_TOP_PTPC (47UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA0 (48UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA1 (49UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA2 (50UL) +#define SYSCTL_CLOCK_CLK_TOP_AUD0 (51UL) +#define SYSCTL_CLOCK_CLK_TOP_AUD1 (52UL) +#define SYSCTL_CLOCK_CLK_TOP_AUD2 (53UL) +#define SYSCTL_CLOCK_CLK_TOP_LCDC (54UL) +#define SYSCTL_CLOCK_CLK_TOP_CAM0 (55UL) +#define SYSCTL_CLOCK_CLK_TOP_CAM1 (56UL) +#define SYSCTL_CLOCK_CLK_TOP_ENET0 (57UL) +#define SYSCTL_CLOCK_CLK_TOP_ENET1 (58UL) +#define SYSCTL_CLOCK_CLK_TOP_PTP0 (59UL) +#define SYSCTL_CLOCK_CLK_TOP_PTP1 (60UL) +#define SYSCTL_CLOCK_CLK_TOP_REF0 (61UL) +#define SYSCTL_CLOCK_CLK_TOP_REF1 (62UL) +#define SYSCTL_CLOCK_CLK_TOP_NTMR0 (63UL) +#define SYSCTL_CLOCK_CLK_TOP_NTMR1 (64UL) +#define SYSCTL_CLOCK_CLK_TOP_SDXC0 (65UL) +#define SYSCTL_CLOCK_CLK_TOP_SDXC1 (66UL) + +/* ADCCLK register group index macro definition */ +#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC3 (3UL) + +/* I2SCLK register group index macro definition */ +#define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL) +#define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL) +#define SYSCTL_I2SCLK_CLK_TOP_I2S2 (2UL) +#define SYSCTL_I2SCLK_CLK_TOP_I2S3 (3UL) + +/* MONITOR register group index macro definition */ +#define SYSCTL_MONITOR_SLICE0 (0UL) +#define SYSCTL_MONITOR_SLICE1 (1UL) +#define SYSCTL_MONITOR_SLICE2 (2UL) +#define SYSCTL_MONITOR_SLICE3 (3UL) + +/* GPR register group index macro definition */ +#define SYSCTL_CPU_GPR_GPR0 (0UL) +#define SYSCTL_CPU_GPR_GPR1 (1UL) +#define SYSCTL_CPU_GPR_GPR2 (2UL) +#define SYSCTL_CPU_GPR_GPR3 (3UL) +#define SYSCTL_CPU_GPR_GPR4 (4UL) +#define SYSCTL_CPU_GPR_GPR5 (5UL) +#define SYSCTL_CPU_GPR_GPR6 (6UL) +#define SYSCTL_CPU_GPR_GPR7 (7UL) +#define SYSCTL_CPU_GPR_GPR8 (8UL) +#define SYSCTL_CPU_GPR_GPR9 (9UL) +#define SYSCTL_CPU_GPR_GPR10 (10UL) +#define SYSCTL_CPU_GPR_GPR11 (11UL) +#define SYSCTL_CPU_GPR_GPR12 (12UL) +#define SYSCTL_CPU_GPR_GPR13 (13UL) + +/* WAKEUP_STATUS register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS4 (4UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS5 (5UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS6 (6UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS7 (7UL) + +/* WAKEUP_ENABLE register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE4 (4UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE5 (5UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE6 (6UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE7 (7UL) + +/* CPU register group index macro definition */ +#define SYSCTL_CPU_CPU0 (0UL) +#define SYSCTL_CPU_CPU1 (1UL) + + +#endif /* HPM_SYSCTL_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h new file mode 100644 index 0000000000..e34cb1bd5e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGM_H +#define HPM_TRGM_H + +typedef struct { + __RW uint32_t FILTCFG[20]; /* 0x0 - 0x4C: Filter configure register */ + __R uint8_t RESERVED0[176]; /* 0x50 - 0xFF: Reserved */ + __RW uint32_t TRGOCFG[64]; /* 0x100 - 0x1FC: Trigger manager output configure register */ + __RW uint32_t DMACFG[4]; /* 0x200 - 0x20C: DMA request configure register */ + __R uint8_t RESERVED1[496]; /* 0x210 - 0x3FF: Reserved */ + __RW uint32_t GCR; /* 0x400: General Control Register */ +} TRGM_Type; + + +/* Bitfield definition for register array: FILTCFG */ +/* + * OUTINV (RW) + * + * 1- Filter will invert the output + * 0- Filter will not invert the output + */ +#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) +#define TRGM_FILTCFG_OUTINV_SHIFT (16U) +#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) +#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) + +/* + * MODE (RW) + * + * This bitfields defines the filter mode + * 000-bypass; + * 100-rapid change mode; + * 101-delay filter mode; + * 110-stalbe low mode; + * 111-stable high mode + */ +#define TRGM_FILTCFG_MODE_MASK (0xE000U) +#define TRGM_FILTCFG_MODE_SHIFT (13U) +#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) +#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) + +/* + * SYNCEN (RW) + * + * set to enable sychronization input signal with TRGM clock + */ +#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) +#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) +#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) +#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) + +/* + * FILTLEN (RW) + * + * This bitfields defines the filter counter length. + */ +#define TRGM_FILTCFG_FILTLEN_MASK (0xFFFU) +#define TRGM_FILTCFG_FILTLEN_SHIFT (0U) +#define TRGM_FILTCFG_FILTLEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT) & TRGM_FILTCFG_FILTLEN_MASK) +#define TRGM_FILTCFG_FILTLEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT) + +/* Bitfield definition for register array: TRGOCFG */ +/* + * OUTINV (RW) + * + * 1- Invert the output + */ +#define TRGM_TRGOCFG_OUTINV_MASK (0x100U) +#define TRGM_TRGOCFG_OUTINV_SHIFT (8U) +#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) +#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) + +/* + * FEDG2PEN (RW) + * + * 1- The selected input signal falling edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x80U) +#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (7U) +#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) +#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) + +/* + * REDG2PEN (RW) + * + * 1- The selected input signal rising edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_REDG2PEN_MASK (0x40U) +#define TRGM_TRGOCFG_REDG2PEN_SHIFT (6U) +#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) +#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) + +/* + * TRIGOSEL (RW) + * + * This bitfield selects one of the TRGM inputs as output. + */ +#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x3FU) +#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) +#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) +#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) + +/* Bitfield definition for register array: DMACFG */ +/* + * DMASRCSEL (RW) + * + * This field selects one of the DMA requests as the DMA request output. + */ +#define TRGM_DMACFG_DMASRCSEL_MASK (0x1FU) +#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) +#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) +#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) + +/* Bitfield definition for register: GCR */ +/* + * TRGOPEN (RW) + * + * The bitfield enable the TRGM outputs. + */ +#define TRGM_GCR_TRGOPEN_MASK (0xFFFU) +#define TRGM_GCR_TRGOPEN_SHIFT (0U) +#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) +#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) + + + +/* FILTCFG register group index macro definition */ +#define TRGM_FILTCFG_PWM_IN0 (0UL) +#define TRGM_FILTCFG_PWM_IN1 (1UL) +#define TRGM_FILTCFG_PWM_IN2 (2UL) +#define TRGM_FILTCFG_PWM_IN3 (3UL) +#define TRGM_FILTCFG_PWM_IN4 (4UL) +#define TRGM_FILTCFG_PWM_IN5 (5UL) +#define TRGM_FILTCFG_PWM_IN6 (6UL) +#define TRGM_FILTCFG_PWM_IN7 (7UL) +#define TRGM_FILTCFG_TRGM_IN0 (8UL) +#define TRGM_FILTCFG_TRGM_IN1 (9UL) +#define TRGM_FILTCFG_TRGM_IN2 (10UL) +#define TRGM_FILTCFG_TRGM_IN3 (11UL) +#define TRGM_FILTCFG_TRGM_IN4 (12UL) +#define TRGM_FILTCFG_TRGM_IN5 (13UL) +#define TRGM_FILTCFG_TRGM_IN6 (14UL) +#define TRGM_FILTCFG_TRGM_IN7 (15UL) +#define TRGM_FILTCFG_TRGM_IN8 (16UL) +#define TRGM_FILTCFG_TRGM_IN9 (17UL) +#define TRGM_FILTCFG_TRGM_IN10 (18UL) +#define TRGM_FILTCFG_TRGM_IN11 (19UL) + +/* TRGOCFG register group index macro definition */ +#define TRGM_TRGOCFG_TRGM_OUT0 (0UL) +#define TRGM_TRGOCFG_TRGM_OUT1 (1UL) +#define TRGM_TRGOCFG_TRGM_OUT2 (2UL) +#define TRGM_TRGOCFG_TRGM_OUT3 (3UL) +#define TRGM_TRGOCFG_TRGM_OUT4 (4UL) +#define TRGM_TRGOCFG_TRGM_OUT5 (5UL) +#define TRGM_TRGOCFG_TRGM_OUT6 (6UL) +#define TRGM_TRGOCFG_TRGM_OUT7 (7UL) +#define TRGM_TRGOCFG_TRGM_OUT8 (8UL) +#define TRGM_TRGOCFG_TRGM_OUT9 (9UL) +#define TRGM_TRGOCFG_TRGM_OUT10 (10UL) +#define TRGM_TRGOCFG_TRGM_OUT11 (11UL) +#define TRGM_TRGOCFG_TRGM_OUTX0 (12UL) +#define TRGM_TRGOCFG_TRGM_OUTX1 (13UL) +#define TRGM_TRGOCFG_PWM_SYNCI (14UL) +#define TRGM_TRGOCFG_PWM_FRCI (15UL) +#define TRGM_TRGOCFG_PWM_FRCSYNCI (16UL) +#define TRGM_TRGOCFG_PWM_SHRLDSYNCI (17UL) +#define TRGM_TRGOCFG_PWM_FAULTI0 (18UL) +#define TRGM_TRGOCFG_PWM_FAULTI1 (19UL) +#define TRGM_TRGOCFG_PWM_FAULTI2 (20UL) +#define TRGM_TRGOCFG_PWM_FAULTI3 (21UL) +#define TRGM_TRGOCFG_PWM_IN8 (22UL) +#define TRGM_TRGOCFG_PWM_IN9 (23UL) +#define TRGM_TRGOCFG_PWM_IN10 (24UL) +#define TRGM_TRGOCFG_PWM_IN11 (25UL) +#define TRGM_TRGOCFG_PWM_IN12 (26UL) +#define TRGM_TRGOCFG_PWM_IN13 (27UL) +#define TRGM_TRGOCFG_PWM_IN14 (28UL) +#define TRGM_TRGOCFG_PWM_IN15 (29UL) +#define TRGM_TRGOCFG_PWM_IN16 (30UL) +#define TRGM_TRGOCFG_PWM_IN17 (31UL) +#define TRGM_TRGOCFG_PWM_IN18 (32UL) +#define TRGM_TRGOCFG_PWM_IN19 (33UL) +#define TRGM_TRGOCFG_PWM_IN20 (34UL) +#define TRGM_TRGOCFG_PWM_IN21 (35UL) +#define TRGM_TRGOCFG_PWM_IN22 (36UL) +#define TRGM_TRGOCFG_PWM_IN23 (37UL) +#define TRGM_TRGOCFG_QEI_A (38UL) +#define TRGM_TRGOCFG_QEI_B (39UL) +#define TRGM_TRGOCFG_QEI_Z (40UL) +#define TRGM_TRGOCFG_QEI_H (41UL) +#define TRGM_TRGOCFG_QEI_PAUSE (42UL) +#define TRGM_TRGOCFG_QEI_SNAPI (43UL) +#define TRGM_TRGOCFG_HALL_U (44UL) +#define TRGM_TRGOCFG_HALL_V (45UL) +#define TRGM_TRGOCFG_HALL_W (46UL) +#define TRGM_TRGOCFG_HALL_SNAPI (47UL) +#define TRGM_TRGOCFG_ADC0_STRGI (48UL) +#define TRGM_TRGOCFG_ADC1_STRGI (49UL) +#define TRGM_TRGOCFG_ADC2_STRGI (50UL) +#define TRGM_TRGOCFG_ADC3_STRGI (51UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL) +#define TRGM_TRGOCFG_GPTMRA_SYNCI (55UL) +#define TRGM_TRGOCFG_GPTMRA_IN2 (56UL) +#define TRGM_TRGOCFG_GPTMRA_IN3 (57UL) +#define TRGM_TRGOCFG_GPTMRB_SYNCI (58UL) +#define TRGM_TRGOCFG_GPTMRB_IN2 (59UL) +#define TRGM_TRGOCFG_GPTMRB_IN3 (60UL) +#define TRGM_TRGOCFG_CMPX_WIN (61UL) +#define TRGM_TRGOCFG_CAN_PTPC0_CAP (62UL) +#define TRGM_TRGOCFG_CAN_PTPC1_CAP (63UL) + +/* DMACFG register group index macro definition */ +#define TRGM_DMACFG_0 (0UL) +#define TRGM_DMACFG_1 (1UL) +#define TRGM_DMACFG_2 (2UL) +#define TRGM_DMACFG_3 (3UL) + + +#endif /* HPM_TRGM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h new file mode 100644 index 0000000000..feedbbf098 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h @@ -0,0 +1,726 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGMMUX_SRC_H +#define HPM_TRGMMUX_SRC_H + +/* trgm0_input mux definitions */ +#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN0 (0x2UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN1 (0x3UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN2 (0x4UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN3 (0x5UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN4 (0x6UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN5 (0x7UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN6 (0x8UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN7 (0x9UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN8 (0xAUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN9 (0xBUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN10 (0xCUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_IN11 (0xDUL) +#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) +#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) +#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) +#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX1 (0x11UL) +#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) +#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH16REF (0x1CUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH17REF (0x1DUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH18REF (0x1EUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH19REF (0x1FUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH20REF (0x20UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH21REF (0x21UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH22REF (0x22UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH23REF (0x23UL) +#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x24UL) +#define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x25UL) +#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x26UL) +#define HPM_TRGM0_INPUT_SRC_USB1_SOF (0x27UL) +#define HPM_TRGM0_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) +#define HPM_TRGM0_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x2AUL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x2BUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x2CUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x2DUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x2EUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x2FUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x30UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x31UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x32UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) +#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) + +/* trgm1_input mux definitions */ +#define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) +#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX0 (0xEUL) +#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX1 (0xFUL) +#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX0 (0x10UL) +#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX1 (0x11UL) +#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH16REF (0x1CUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH17REF (0x1DUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH18REF (0x1EUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH19REF (0x1FUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH20REF (0x20UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH21REF (0x21UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH22REF (0x22UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH23REF (0x23UL) +#define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x24UL) +#define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x25UL) +#define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x26UL) +#define HPM_TRGM1_INPUT_SRC_USB1_SOF (0x27UL) +#define HPM_TRGM1_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) +#define HPM_TRGM1_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) +#define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x2AUL) +#define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x2BUL) +#define HPM_TRGM1_INPUT_SRC_SYNT_CH0 (0x2CUL) +#define HPM_TRGM1_INPUT_SRC_SYNT_CH1 (0x2DUL) +#define HPM_TRGM1_INPUT_SRC_SYNT_CH2 (0x2EUL) +#define HPM_TRGM1_INPUT_SRC_SYNT_CH3 (0x2FUL) +#define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2 (0x30UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT3 (0x31UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT2 (0x32UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) +#define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) + +/* trgm2_input mux definitions */ +#define HPM_TRGM2_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM2_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P0 (0x2UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P1 (0x3UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P2 (0x4UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P3 (0x5UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P4 (0x6UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P5 (0x7UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P6 (0x8UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P7 (0x9UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P8 (0xAUL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P9 (0xBUL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P10 (0xCUL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P11 (0xDUL) +#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX0 (0xEUL) +#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX1 (0xFUL) +#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX0 (0x10UL) +#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX1 (0x11UL) +#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH8REF (0x14UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH9REF (0x15UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH10REF (0x16UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH11REF (0x17UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH12REF (0x18UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH13REF (0x19UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH14REF (0x1AUL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH15REF (0x1BUL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH16REF (0x1CUL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH17REF (0x1DUL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH18REF (0x1EUL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH19REF (0x1FUL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH20REF (0x20UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH21REF (0x21UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH22REF (0x22UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH23REF (0x23UL) +#define HPM_TRGM2_INPUT_SRC_QEI2_TRGO (0x24UL) +#define HPM_TRGM2_INPUT_SRC_HALL2_TRGO (0x25UL) +#define HPM_TRGM2_INPUT_SRC_USB0_SOF (0x26UL) +#define HPM_TRGM2_INPUT_SRC_USB1_SOF (0x27UL) +#define HPM_TRGM2_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) +#define HPM_TRGM2_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) +#define HPM_TRGM2_INPUT_SRC_PTPC_CMP0 (0x2AUL) +#define HPM_TRGM2_INPUT_SRC_PTPC_CMP1 (0x2BUL) +#define HPM_TRGM2_INPUT_SRC_SYNT_CH0 (0x2CUL) +#define HPM_TRGM2_INPUT_SRC_SYNT_CH1 (0x2DUL) +#define HPM_TRGM2_INPUT_SRC_SYNT_CH2 (0x2EUL) +#define HPM_TRGM2_INPUT_SRC_SYNT_CH3 (0x2FUL) +#define HPM_TRGM2_INPUT_SRC_GPTMR4_OUT2 (0x30UL) +#define HPM_TRGM2_INPUT_SRC_GPTMR4_OUT3 (0x31UL) +#define HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2 (0x32UL) +#define HPM_TRGM2_INPUT_SRC_GPTMR5_OUT3 (0x33UL) +#define HPM_TRGM2_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM2_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM2_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM2_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM2_INPUT_SRC_DEBUG_FLAG (0x38UL) + +/* trgm3_input mux definitions */ +#define HPM_TRGM3_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM3_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P0 (0x2UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P1 (0x3UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P2 (0x4UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P3 (0x5UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P4 (0x6UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P5 (0x7UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P6 (0x8UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P7 (0x9UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P8 (0xAUL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P9 (0xBUL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P10 (0xCUL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P11 (0xDUL) +#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX0 (0xEUL) +#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX1 (0xFUL) +#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX0 (0x10UL) +#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX1 (0x11UL) +#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH8REF (0x14UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH9REF (0x15UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH10REF (0x16UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH11REF (0x17UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH12REF (0x18UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH13REF (0x19UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH14REF (0x1AUL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH15REF (0x1BUL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH16REF (0x1CUL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH17REF (0x1DUL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH18REF (0x1EUL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH19REF (0x1FUL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH20REF (0x20UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH21REF (0x21UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH22REF (0x22UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH23REF (0x23UL) +#define HPM_TRGM3_INPUT_SRC_QEI3_TRGO (0x24UL) +#define HPM_TRGM3_INPUT_SRC_HALL3_TRGO (0x25UL) +#define HPM_TRGM3_INPUT_SRC_USB0_SOF (0x26UL) +#define HPM_TRGM3_INPUT_SRC_USB1_SOF (0x27UL) +#define HPM_TRGM3_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) +#define HPM_TRGM3_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) +#define HPM_TRGM3_INPUT_SRC_PTPC_CMP0 (0x2AUL) +#define HPM_TRGM3_INPUT_SRC_PTPC_CMP1 (0x2BUL) +#define HPM_TRGM3_INPUT_SRC_SYNT_CH0 (0x2CUL) +#define HPM_TRGM3_INPUT_SRC_SYNT_CH1 (0x2DUL) +#define HPM_TRGM3_INPUT_SRC_SYNT_CH2 (0x2EUL) +#define HPM_TRGM3_INPUT_SRC_SYNT_CH3 (0x2FUL) +#define HPM_TRGM3_INPUT_SRC_GPTMR6_OUT2 (0x30UL) +#define HPM_TRGM3_INPUT_SRC_GPTMR6_OUT3 (0x31UL) +#define HPM_TRGM3_INPUT_SRC_GPTMR7_OUT2 (0x32UL) +#define HPM_TRGM3_INPUT_SRC_GPTMR7_OUT3 (0x33UL) +#define HPM_TRGM3_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM3_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM3_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM3_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM3_INPUT_SRC_DEBUG_FLAG (0x38UL) + +/* trgm0_output mux definitions */ +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN16 (0x1EUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN17 (0x1FUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN18 (0x20UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN19 (0x21UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN20 (0x22UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN21 (0x23UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN22 (0x24UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN23 (0x25UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) +#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC3_STRGI (0x33UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x3AUL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x3BUL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x3CUL) +#define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) +#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) + +/* trgm1_output mux definitions */ +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN16 (0x1EUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN17 (0x1FUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN18 (0x20UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN19 (0x21UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN20 (0x22UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN21 (0x23UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN22 (0x24UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN23 (0x25UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) +#define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM1_OUTPUT_SRC_ADC3_STRGI (0x33UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_SYNCI (0x3AUL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN2 (0x3BUL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN3 (0x3CUL) +#define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) +#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) + +/* trgm2_output mux definitions */ +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P0 (0x0UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P1 (0x1UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P2 (0x2UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P3 (0x3UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P4 (0x4UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P5 (0x5UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P6 (0x6UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P7 (0x7UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P8 (0x8UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P9 (0x9UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P10 (0xAUL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P11 (0xBUL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX0 (0xCUL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX1 (0xDUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_SYNCI (0xEUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCI (0xFUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCSYNCI (0x10UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_SHRLDSYNCI (0x11UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI0 (0x12UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI1 (0x13UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI2 (0x14UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI3 (0x15UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN8 (0x16UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN9 (0x17UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN10 (0x18UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN11 (0x19UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN12 (0x1AUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN13 (0x1BUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN14 (0x1CUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN15 (0x1DUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN16 (0x1EUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN17 (0x1FUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN18 (0x20UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN19 (0x21UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN20 (0x22UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN21 (0x23UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN22 (0x24UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN23 (0x25UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_A (0x26UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_B (0x27UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_Z (0x28UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_H (0x29UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_PAUSE (0x2AUL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_SNAPI (0x2BUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_U (0x2CUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_V (0x2DUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_W (0x2EUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_SNAPI (0x2FUL) +#define HPM_TRGM2_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM2_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM2_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM2_OUTPUT_SRC_ADC3_STRGI (0x33UL) +#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2A (0x34UL) +#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2B (0x35UL) +#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2C (0x36UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI (0x37UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 (0x38UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN3 (0x39UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR5_SYNCI (0x3AUL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR5_IN2 (0x3BUL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR5_IN3 (0x3CUL) +#define HPM_TRGM2_OUTPUT_SRC_ACMP2_WIN (0x3DUL) +#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) + +/* trgm3_output mux definitions */ +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P0 (0x0UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P1 (0x1UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P2 (0x2UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P3 (0x3UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P4 (0x4UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P5 (0x5UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P6 (0x6UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P7 (0x7UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P8 (0x8UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P9 (0x9UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P10 (0xAUL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P11 (0xBUL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX0 (0xCUL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX1 (0xDUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_SYNCI (0xEUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCI (0xFUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCSYNCI (0x10UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_SHRLDSYNCI (0x11UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI0 (0x12UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI1 (0x13UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI2 (0x14UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI3 (0x15UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN8 (0x16UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN9 (0x17UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN10 (0x18UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN11 (0x19UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN12 (0x1AUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN13 (0x1BUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN14 (0x1CUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN15 (0x1DUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN16 (0x1EUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN17 (0x1FUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN18 (0x20UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN19 (0x21UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN20 (0x22UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN21 (0x23UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN22 (0x24UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN23 (0x25UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_A (0x26UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_B (0x27UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_Z (0x28UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_H (0x29UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_PAUSE (0x2AUL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_SNAPI (0x2BUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_U (0x2CUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_V (0x2DUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_W (0x2EUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_SNAPI (0x2FUL) +#define HPM_TRGM3_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM3_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM3_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM3_OUTPUT_SRC_ADC3_STRGI (0x33UL) +#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3A (0x34UL) +#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3B (0x35UL) +#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3C (0x36UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR6_SYNCI (0x37UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR6_IN2 (0x38UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR6_IN3 (0x39UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR7_SYNCI (0x3AUL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR7_IN2 (0x3BUL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR7_IN3 (0x3CUL) +#define HPM_TRGM3_OUTPUT_SRC_ACMP3_WIN (0x3DUL) +#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) + +/* trgm0_filter mux definitions */ +#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) + +/* trgm1_filter mux definitions */ +#define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) + +/* trgm2_filter mux definitions */ +#define HPM_TRGM2_FILTER_SRC_PWM2_IN0 (0x0UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN1 (0x1UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN2 (0x2UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN3 (0x3UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN4 (0x4UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN5 (0x5UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN6 (0x6UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN7 (0x7UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN0 (0x8UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN1 (0x9UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN2 (0xAUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN3 (0xBUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN4 (0xCUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN5 (0xDUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN6 (0xEUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN7 (0xFUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN8 (0x10UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN9 (0x11UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN10 (0x12UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN11 (0x13UL) + +/* trgm3_filter mux definitions */ +#define HPM_TRGM3_FILTER_SRC_PWM3_IN0 (0x0UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN1 (0x1UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN2 (0x2UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN3 (0x3UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN4 (0x4UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN5 (0x5UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN6 (0x6UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN7 (0x7UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN0 (0x8UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN1 (0x9UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN2 (0xAUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN3 (0xBUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN4 (0xCUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN5 (0xDUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN6 (0xEUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN7 (0xFUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN8 (0x10UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN9 (0x11UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN10 (0x12UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN11 (0x13UL) + +/* trgm0_dma mux definitions */ +#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) +#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) +#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) +#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) +#define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) +#define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) + +/* trgm1_dma mux definitions */ +#define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) +#define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) +#define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) +#define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) +#define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) +#define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) + +/* trgm2_dma mux definitions */ +#define HPM_TRGM2_DMA_SRC_PWM2_CMP0 (0x0UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP1 (0x1UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP2 (0x2UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP3 (0x3UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP4 (0x4UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP5 (0x5UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP6 (0x6UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP7 (0x7UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP8 (0x8UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP9 (0x9UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP10 (0xAUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP11 (0xBUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP12 (0xCUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP13 (0xDUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP14 (0xEUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP15 (0xFUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP16 (0x10UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP17 (0x11UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP18 (0x12UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP19 (0x13UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP20 (0x14UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP21 (0x15UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP22 (0x16UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP23 (0x17UL) +#define HPM_TRGM2_DMA_SRC_PWM2_RLD (0x18UL) +#define HPM_TRGM2_DMA_SRC_PWM2_HALFRLD (0x19UL) +#define HPM_TRGM2_DMA_SRC_PWM2_XRLD (0x1AUL) +#define HPM_TRGM2_DMA_SRC_QEI2 (0x1BUL) +#define HPM_TRGM2_DMA_SRC_HALL2 (0x1CUL) + +/* trgm3_dma mux definitions */ +#define HPM_TRGM3_DMA_SRC_PWM3_CMP0 (0x0UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP1 (0x1UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP2 (0x2UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP3 (0x3UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP4 (0x4UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP5 (0x5UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP6 (0x6UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP7 (0x7UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP8 (0x8UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP9 (0x9UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP10 (0xAUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP11 (0xBUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP12 (0xCUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP13 (0xDUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP14 (0xEUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP15 (0xFUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP16 (0x10UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP17 (0x11UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP18 (0x12UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP19 (0x13UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP20 (0x14UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP21 (0x15UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP22 (0x16UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP23 (0x17UL) +#define HPM_TRGM3_DMA_SRC_PWM3_RLD (0x18UL) +#define HPM_TRGM3_DMA_SRC_PWM3_HALFRLD (0x19UL) +#define HPM_TRGM3_DMA_SRC_PWM3_XRLD (0x1AUL) +#define HPM_TRGM3_DMA_SRC_QEI3 (0x1BUL) +#define HPM_TRGM3_DMA_SRC_HALL3 (0x1CUL) + + + +#endif /* HPM_TRGMMUX_SRC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list new file mode 100644 index 0000000000..e422ffcce5 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/soc_modules.list @@ -0,0 +1,38 @@ +# Copyright 2022 hpmicro +# SPDX-License-Identifier: BSD-3-Clause +# +# In this file, all modules available on this part are listed + +CONFIG_HAS_HPMSDK_UART=y +CONFIG_HAS_HPMSDK_DRAM=y +CONFIG_HAS_HPMSDK_SDP=y +CONFIG_HAS_HPMSDK_LCDC=y +CONFIG_HAS_HPMSDK_I2C=y +CONFIG_HAS_HPMSDK_PMP=y +CONFIG_HAS_HPMSDK_RNG=y +CONFIG_HAS_HPMSDK_GPIO=y +CONFIG_HAS_HPMSDK_SPI=y +CONFIG_HAS_HPMSDK_PDMA=y +CONFIG_HAS_HPMSDK_WDG=y +CONFIG_HAS_HPMSDK_DMA=y +CONFIG_HAS_HPMSDK_GPTMR=y +CONFIG_HAS_HPMSDK_PWM=y +CONFIG_HAS_HPMSDK_PLLCTL=y +CONFIG_HAS_HPMSDK_USB=y +CONFIG_HAS_HPMSDK_RTC=y +CONFIG_HAS_HPMSDK_ACMP=y +CONFIG_HAS_HPMSDK_I2S=y +CONFIG_HAS_HPMSDK_DAO=y +CONFIG_HAS_HPMSDK_PDM=y +CONFIG_HAS_HPMSDK_VAD=y +CONFIG_HAS_HPMSDK_CAM=y +CONFIG_HAS_HPMSDK_CAN=y +CONFIG_HAS_HPMSDK_JPEG=y +CONFIG_HAS_HPMSDK_ENET=y +CONFIG_HAS_HPMSDK_SDXC=y +CONFIG_HAS_HPMSDK_ADC12=y +CONFIG_HAS_HPMSDK_ADC16=y +CONFIG_HAS_HPMSDK_PCFG=y +CONFIG_HAS_HPMSDK_PTPC=y +CONFIG_HAS_HPMSDK_MCHTMR=y + diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c new file mode 100644 index 0000000000..d5c3a0e86e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/system.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" + +void enable_plic_feature(void) +{ + uint32_t plic_feature = 0; +#ifndef USE_NONVECTOR_MODE + /* enabled vector mode and preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; +#endif +#ifndef DISABLE_IRQ_PREEMPTIVE + /* enabled preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; +#endif + __plic_set_feature(HPM_PLIC_BASE, plic_feature); +} + +__attribute__((weak)) void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_plic_feature(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); + +#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ +#endif +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + l1c_dc_invalidate_all(); +#endif +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld new file mode 100644 index 0000000000..1089782cf8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld @@ -0,0 +1,180 @@ +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (wx) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .vectors ORIGIN(ILM) : AT(etext) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld new file mode 100644 index 0000000000..383517c877 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld @@ -0,0 +1,188 @@ +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) + SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M + AXI_SRAM (wx) : ORIGIN = 0x1000000, LENGTH = 2M +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(AXI_SRAM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + } > SDRAM + + .stack_safe : { + . = ALIGN(8); + . += 0x1000; + . = ALIGN(8); + PROVIDE (_stack_safe = .); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld new file mode 100644 index 0000000000..3606a3f9d8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld @@ -0,0 +1,200 @@ +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) + SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M + AXI_SRAM (wx) : ORIGIN = 0x1000000, LENGTH = 2M +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(AXI_SRAM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > AXI_SRAM + + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > SDRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > SDRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > SDRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld new file mode 100644 index 0000000000..e6eb786cdf --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld @@ -0,0 +1,182 @@ +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (wx) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld new file mode 100644 index 0000000000..99846a3361 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld @@ -0,0 +1,200 @@ +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (wx) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > AXI_SRAM + + __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld new file mode 100644 index 0000000000..d054978073 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld @@ -0,0 +1,188 @@ +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + /* It's alias address of core0 ILM+DLM, but accessing via system bus */ + CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K + /* It's alias address of core1 ILM+DLM, but accessing via system bus */ + CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = 32M + + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > CORE0_LM_SLV + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > CORE0_LM_SLV + + .rel : { + KEEP(*(.rel*)) + } > CORE0_LM_SLV + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > CORE0_LM_SLV + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > AXI_SRAM + + .dual_core_share (NOLOAD) : { + KEEP(*(.dual_core_share)) + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > AXI_SRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + ASSERT(__stack_base__ >= __heap_end__, "stack overlapped with heap") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld new file mode 100644 index 0000000000..d333beac88 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld @@ -0,0 +1,188 @@ +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + /* It's alias address of core0 ILM+DLM, but accessing via system bus */ + CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K + /* It's alias address of core1 ILM+DLM, but accessing via system bus */ + CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = 32M + + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 768K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01140000, LENGTH = 256K +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > CORE1_LM_SLV + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > CORE1_LM_SLV + + .rel : { + KEEP(*(.rel*)) + } > CORE1_LM_SLV + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > CORE1_LM_SLV + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > AXI_SRAM + + .dual_core_share (NOLOAD) : { + KEEP(*(.dual_core_share)) + } > AXI_SRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > AXI_SRAM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > AXI_SRAM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + + ASSERT(__stack_base__ >= __heap_end__, "stack overlapped with heap") +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S new file mode 100644 index 0000000000..bee793f35c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_csr_regs.h" + + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + + /* reset mstatus to 0*/ + csrrw x0, mstatus, x0 + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_safe + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifndef CONFIG_FREERTOS + #define HANDLER_TRAP irq_handler_trap +#else + #define HANDLER_TRAP freertos_risc_v_trap_handler +#endif + +#ifndef USE_NONVECTOR_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak exit +exit: +1: j 1b + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c new file mode 100644 index 0000000000..1d44f2e153 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c @@ -0,0 +1,129 @@ +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include "hpm_interrupt.h" + +#ifdef __cplusplus +extern "C" { +#endif +extern void system_init(void); +extern void __libc_init_array(void); +extern void __libc_fini_array(void); +#ifdef __cplusplus +} +#endif + +__attribute__((weak)) void _clean_up(void) +{ + /* clean up plic, it will help while debuging */ + disable_irq_from_intc(); + intc_m_set_threshold(0); + for (uint32_t irq = 0; irq < 128; irq++) { + intc_m_complete_irq(irq); + } + /* clear any bits left in plic enable regster */ + for (uint32_t i = 0; i < 4; i++) { + *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; + } +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#if defined(FLASH_XIP) || defined(FLASH_UF2) + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +__attribute__((weak)) void reset_handler(void) +{ + l1c_dc_disable(); + l1c_dc_invalidate_all(); +#if !defined(__SEGGER_RTL_VERSION) || defined(__GNU_LINKER) + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); +#endif + + /* Call platform specific hardware initialization */ + system_init(); + +#ifdef __cplusplus + /* Do global constructors */ + __libc_init_array(); +#endif + + /* Entry function */ + main(); +} + +/* + * When compiling C++ code with static objects, the compiler inserts + * a call to __cxa_atexit() with __dso_handle as one of the arguments. + * The dummy versions of these symbols should be provided. + */ +void __cxa_atexit(void (*arg1)(void*), void* arg2, void* arg3) +{ +} + +#ifndef __SEGGER_RTL_VERSION +void* __dso_handle = (void*) &__dso_handle; +#endif + +__attribute__((weak)) void _init() +{ +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf new file mode 100644 index 0000000000..fd9b3a0a9d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf @@ -0,0 +1,89 @@ +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ +define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ +define region DLM = [from 0x80000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 768k]; +define region SDRAM = [from 0x40000000 size _extram_size]; +define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM_SLV with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM_SLV { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack }; // Stack reserved block at the end +place at end of DLM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf new file mode 100644 index 0000000000..962c865fa6 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf @@ -0,0 +1,85 @@ +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region AXI_SRAM = [from 0x1000000 size 2M]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order {symbol _start}; +keep { section .uf2_signature }; + +place at start of AXI_SRAM with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in SDRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SDRAM { block heap }; // Heap reserved block +place at end of SDRAM { block stack }; // Stack reserved block at the end +place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf new file mode 100644 index 0000000000..da4cec78f1 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf @@ -0,0 +1,96 @@ +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region AXI_SRAM = [from 0x1000000 size 2M]; +define region SDRAM = [from 0x40000000 size _extram_size - 4M]; +define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; + +place at start of AXI_SRAM with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM with auto order { section .fast, section .fast.*, // "ramfunc" section + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in SDRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SDRAM { block heap }; // Heap reserved block +place at end of SDRAM { block stack }; // Stack reserved block at the end +place at end of AXI_SRAM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf new file mode 100644 index 0000000000..0ecf3ae292 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf @@ -0,0 +1,92 @@ +/* + * Copyright 2021-2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ +define region DLM = [from 0x80000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 768k]; +define region SDRAM = [from 0x40000000 size _extram_size]; +define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order {symbol _start}; +keep { section .uf2_signature }; + +place at start of ILM_SLV with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM_SLV { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack }; // Stack reserved block at the end +place at end of DLM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf new file mode 100644 index 0000000000..4905f88846 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf @@ -0,0 +1,103 @@ +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x3000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM_SLV = [from 0x1000000 size 256k]; /* ILM slave */ +define region DLM = [from 0x80000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x1080000 size 768k]; +define region SDRAM = [from 0x40000000 size _extram_size]; +define region NONCACHEABLE_RAM = [from 0x1140000 size 256k]; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +define block framebuffer with alignment = 8 { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; + +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block safe_stack + 1; +define exported symbol _stack = end of block stack + 1; + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start}; + +place at start of ILM_SLV with fixed order { block vectors }; +initialize by copy { block vectors }; + +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM_SLV { + section .fast, section .fast.*, // "ramfunc" section + }; + +place in DLM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in AXI_SRAM { block framebuffer }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack }; // Stack reserved block at the end +place at end of DLM { block safe_stack }; // Safe stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf new file mode 100644 index 0000000000..25e32ed3f7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf @@ -0,0 +1,79 @@ +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */ +define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */ +define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */ +define region NONCACHEABLE_RAM = [from 0x1140000 size 256K]; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack = end of block stack + 1; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block framebuffer { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; +define exported symbol _stack_safe = end of block safe_stack + 1; + + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of CORE0_LM_SLV { symbol _start }; +place in CORE0_LM_SLV { block vectors }; // Vector table section +place in CORE0_LM_SLV with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec, // Catch-all for (readonly) executable code (e.g. .text) + section .fast, section .fast.*, // "ramfunc" section + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +/* Explicit placement in AXI_SRAM */ +place in AXI_SRAM { block framebuffer }; + +place in AXI_SRAM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf new file mode 100644 index 0000000000..600e3a16ca --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf @@ -0,0 +1,79 @@ +/* + * Copyright 2021 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region CORE0_LM_SLV = [from 0x1000000 size 512k]; /* CORE0 LM slave */ +define region CORE1_LM_SLV = [from 0x1180000 size 512k]; /* CORE1 LM slave */ +define region AXI_SRAM = [from 0x1080000 size 768k]; /* reserve 256K for noncacheable region */ +define region NONCACHEABLE_RAM = [from 0x1140000 size 256K]; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol _stack = end of block stack + 1; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block framebuffer { section .framebuffer }; +define block safe_stack with size = 512, readwrite access {}; +define exported symbol _stack_safe = end of block safe_stack + 1; + + +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +place at start of CORE1_LM_SLV { symbol _start }; +place in CORE1_LM_SLV { block vectors }; // Vector table section +place in CORE1_LM_SLV with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec, // Catch-all for (readonly) executable code (e.g. .text) + section .fast, section .fast.*, // "ramfunc" section + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +/* Explicit placement in AXI_SRAM */ +place in AXI_SRAM { block framebuffer }; + +place in AXI_SRAM with auto order { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit, // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in AXI_SRAM { block heap }; // Heap reserved block +place at end of AXI_SRAM { block stack, block safe_stack }; // Stack reserved block at the end diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s new file mode 100644 index 0000000000..abf30a0bce --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s @@ -0,0 +1,373 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_RISCV_crt0.s +Purpose : Generic runtime init startup code for RISC-V CPUs. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then + calls SEGGER_SEMIHOST_Exit(). + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and + halts in a loop. +*/ + +#include "hpm_csr_regs.h" + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT reset_handler +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ +// +// Declare a label as function symbol (without switching sections) +// +.macro MARK_FUNC Name + .global \Name + .type \Name, function +\Name: +.endm + +// +// Declare a regular function. +// Functions from the startup are placed in the init section. +// +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Declare a weak function +// +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .global \Name + .weak \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Mark the end of a function and calculate its size +// +.macro END_FUNC name + .size \name,.-\name +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized +* - by hardware (such as on Cortex-M), +* - by the device-specific reset handler, +* - or by the debugger (such as for RAM Code). +*/ +#undef L +#define L(label) .L_start_##label + +START_FUNC _start + .option push + .option norelax + lui gp, %hi(__global_pointer$) + addi gp, gp, %lo(__global_pointer$) + lui tp, %hi(__thread_pointer$) + addi tp, tp, %lo(__thread_pointer$) + .option pop + + csrw mstatus, zero + csrw mcause, zero + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_safe + mv sp, t0 + call _init_ext_ram +#endif + + lui t0, %hi(__stack_end__) + addi sp, t0, %lo(__stack_end__) + +#ifndef __NO_SYSTEM_INIT + // + // Call _init + // + call _init +#endif + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table +L(RunInit): + lw a0, (s0) // Get next initialization function from table + add s0, s0, 4 // Increment table pointer to point to function arguments + jalr a0 // Call initialization function + j L(RunInit) + // +MARK_FUNC __SEGGER_init_done + // + // Time to call main(), the application entry point. + // + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifndef CONFIG_FREERTOS + #define HANDLER_TRAP irq_handler_trap +#else + #define HANDLER_TRAP freertos_risc_v_trap_handler +#endif + +#ifndef USE_NONVECTOR_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + +MARK_FUNC start +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init a0 and a1. + // + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + // + // end of _start + // Fall-through to exit if main ever returns. + // +MARK_FUNC exit + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + j . + .size exit,.-exit +#else + // + // In a hosted environment, + // we need to load a0 and a1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args + + call APP_ENTRY_POINT // Call to application entry point (usually main()) + call exit // Call exit function + j . // If we unexpectedly return from exit, hang. +END_FUNC _start +#endif + +#ifdef FULL_LIBRARY + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args +#else + li a0, 0 + li a1, 0 +#endif + + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + + // +#ifdef FULL_LIBRARY +/********************************************************************* +* +* exit +* +* Function description +* Exit of the system. +* Called on return from application entry point or explicit call +* to exit. +* +* Additional information +* In a hosted environment exit gracefully, by +* saving the return value, +* calling destructurs of global objects, +* calling registered atexit functions, +* and notifying the host/debugger. +*/ +#undef L +#define L(label) .L_exit_##label + +WEAK_FUNC exit + mv s1, a0 // Save the exit parameter/return result + // + // Call destructors + // + la s0, __dtors_start__ +L(Loop): + la t0, __dtors_end__ + beq s0, t0, L(End) + lw t1, 0(s0) + addi s0, s0, 4 + jalr t1 + j L(Loop) +L(End): + // + // Call atexit functions + // + call _execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mv a0, s1 + call debug_exit + // + // If execution is not terminated, loop forever + // +L(ExitLoop): + j L(ExitLoop) // Loop forever. +END_FUNC exit +#endif + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE + .size args, .-args + .type args, %object +#endif + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" + +/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c new file mode 100644 index 0000000000..c4abe867e4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" + +/********************** MCAUSE exception types **************************************/ +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + + + +__attribute__((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void swi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) +{ +} + +__attribute__((weak)) long exception_handler(long cause, long epc) +{ + switch (cause) { + case MCAUSE_INSTR_ADDR_MISALIGNED: + break; + case MCAUSE_INSTR_ACCESS_FAULT: + break; + case MCAUSE_ILLEGAL_INSTR: + break; + case MCAUSE_BREAKPOINT: + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + break; + case MCAUSE_LOAD_ACCESS_FAULT: + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + break; + case MCAUSE_ECALL_FROM_USER_MODE: + break; + case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: + break; + case MCAUSE_ECALL_FROM_MACHINE_MODE: + break; + case MCAUSE_INSTR_PAGE_FAULT: + break; + case MCAUSE_LOAD_PAGE_FAULT: + break; + case MCAUSE_STORE_AMO_PAGE_FAULT: + break; + default: + break; + } + /* Unhandled Trap */ + return epc; +} + +#ifndef CONFIG_FREERTOS +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#else +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); +#endif +void irq_handler_trap(void) +{ + long mcause = read_csr(CSR_MCAUSE); + long mepc = read_csr(CSR_MEPC); + long mstatus = read_csr(CSR_MSTATUS); +#if SUPPORT_PFT_ARCH + long mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { + /* Machine timer interrupt */ + mchtmr_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + if (irq_index) { + /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ +#ifndef DISABLE_IRQ_PREEMPTIVE + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + ((isr_func_t)__vector_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + + } +#endif + + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { + /* Machine SWI interrupt */ + intc_m_claim_swi(); + swi_isr(); + intc_m_complete_swi(); + } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + mepc += 4; + } else { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h new file mode 100644 index 0000000000..c64c586819 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +.global default_irq_handler +.weak default_irq_handler +.align 2 +default_irq_handler: +1: j 1b + +.macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq +.endm + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_E IRQ handler */ + IRQ_HANDLER 15 /* GPIO1_F IRQ handler */ + IRQ_HANDLER 16 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 17 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 18 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 19 /* ADC0 IRQ handler */ + IRQ_HANDLER 20 /* ADC1 IRQ handler */ + IRQ_HANDLER 21 /* ADC2 IRQ handler */ + IRQ_HANDLER 22 /* ADC3 IRQ handler */ + IRQ_HANDLER 23 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 25 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 26 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 27 /* SPI0 IRQ handler */ + IRQ_HANDLER 28 /* SPI1 IRQ handler */ + IRQ_HANDLER 29 /* SPI2 IRQ handler */ + IRQ_HANDLER 30 /* SPI3 IRQ handler */ + IRQ_HANDLER 31 /* UART0 IRQ handler */ + IRQ_HANDLER 32 /* UART1 IRQ handler */ + IRQ_HANDLER 33 /* UART2 IRQ handler */ + IRQ_HANDLER 34 /* UART3 IRQ handler */ + IRQ_HANDLER 35 /* UART4 IRQ handler */ + IRQ_HANDLER 36 /* UART5 IRQ handler */ + IRQ_HANDLER 37 /* UART6 IRQ handler */ + IRQ_HANDLER 38 /* UART7 IRQ handler */ + IRQ_HANDLER 39 /* UART8 IRQ handler */ + IRQ_HANDLER 40 /* UART9 IRQ handler */ + IRQ_HANDLER 41 /* UART10 IRQ handler */ + IRQ_HANDLER 42 /* UART11 IRQ handler */ + IRQ_HANDLER 43 /* UART12 IRQ handler */ + IRQ_HANDLER 44 /* UART13 IRQ handler */ + IRQ_HANDLER 45 /* UART14 IRQ handler */ + IRQ_HANDLER 46 /* UART15 IRQ handler */ + IRQ_HANDLER 47 /* CAN0 IRQ handler */ + IRQ_HANDLER 48 /* CAN1 IRQ handler */ + IRQ_HANDLER 49 /* CAN2 IRQ handler */ + IRQ_HANDLER 50 /* CAN3 IRQ handler */ + IRQ_HANDLER 51 /* PTPC IRQ handler */ + IRQ_HANDLER 52 /* WDG0 IRQ handler */ + IRQ_HANDLER 53 /* WDG1 IRQ handler */ + IRQ_HANDLER 54 /* WDG2 IRQ handler */ + IRQ_HANDLER 55 /* WDG3 IRQ handler */ + IRQ_HANDLER 56 /* MBX0A IRQ handler */ + IRQ_HANDLER 57 /* MBX0B IRQ handler */ + IRQ_HANDLER 58 /* MBX1A IRQ handler */ + IRQ_HANDLER 59 /* MBX1B IRQ handler */ + IRQ_HANDLER 60 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 61 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 62 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 63 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 64 /* GPTMR4 IRQ handler */ + IRQ_HANDLER 65 /* GPTMR5 IRQ handler */ + IRQ_HANDLER 66 /* GPTMR6 IRQ handler */ + IRQ_HANDLER 67 /* GPTMR7 IRQ handler */ + IRQ_HANDLER 68 /* I2C0 IRQ handler */ + IRQ_HANDLER 69 /* I2C1 IRQ handler */ + IRQ_HANDLER 70 /* I2C2 IRQ handler */ + IRQ_HANDLER 71 /* I2C3 IRQ handler */ + IRQ_HANDLER 72 /* PWM0 IRQ handler */ + IRQ_HANDLER 73 /* HALL0 IRQ handler */ + IRQ_HANDLER 74 /* QEI0 IRQ handler */ + IRQ_HANDLER 75 /* PWM1 IRQ handler */ + IRQ_HANDLER 76 /* HALL1 IRQ handler */ + IRQ_HANDLER 77 /* QEI1 IRQ handler */ + IRQ_HANDLER 78 /* PWM2 IRQ handler */ + IRQ_HANDLER 79 /* HALL2 IRQ handler */ + IRQ_HANDLER 80 /* QEI2 IRQ handler */ + IRQ_HANDLER 81 /* PWM3 IRQ handler */ + IRQ_HANDLER 82 /* HALL3 IRQ handler */ + IRQ_HANDLER 83 /* QEI3 IRQ handler */ + IRQ_HANDLER 84 /* SDP IRQ handler */ + IRQ_HANDLER 85 /* XPI0 IRQ handler */ + IRQ_HANDLER 86 /* XPI1 IRQ handler */ + IRQ_HANDLER 87 /* XDMA IRQ handler */ + IRQ_HANDLER 88 /* HDMA IRQ handler */ + IRQ_HANDLER 89 /* DRAM IRQ handler */ + IRQ_HANDLER 90 /* RNG IRQ handler */ + IRQ_HANDLER 91 /* I2S0 IRQ handler */ + IRQ_HANDLER 92 /* I2S1 IRQ handler */ + IRQ_HANDLER 93 /* I2S2 IRQ handler */ + IRQ_HANDLER 94 /* I2S3 IRQ handler */ + IRQ_HANDLER 95 /* DAO IRQ handler */ + IRQ_HANDLER 96 /* PDM IRQ handler */ + IRQ_HANDLER 97 /* CAM0 IRQ handler */ + IRQ_HANDLER 98 /* CAM1 IRQ handler */ + IRQ_HANDLER 99 /* LCDC_D0 IRQ handler */ + IRQ_HANDLER 100 /* LCDC_D1 IRQ handler */ + IRQ_HANDLER 101 /* PDMA_D0 IRQ handler */ + IRQ_HANDLER 102 /* PDMA_D1 IRQ handler */ + IRQ_HANDLER 103 /* JPEG IRQ handler */ + IRQ_HANDLER 104 /* NTMR0 IRQ handler */ + IRQ_HANDLER 105 /* NTMR1 IRQ handler */ + IRQ_HANDLER 106 /* USB0 IRQ handler */ + IRQ_HANDLER 107 /* USB1 IRQ handler */ + IRQ_HANDLER 108 /* ENET0 IRQ handler */ + IRQ_HANDLER 109 /* ENET1 IRQ handler */ + IRQ_HANDLER 110 /* SDXC0 IRQ handler */ + IRQ_HANDLER 111 /* SDXC1 IRQ handler */ + IRQ_HANDLER 112 /* PSEC IRQ handler */ + IRQ_HANDLER 113 /* PGPIO IRQ handler */ + IRQ_HANDLER 114 /* PWDG IRQ handler */ + IRQ_HANDLER 115 /* PTMR IRQ handler */ + IRQ_HANDLER 116 /* PUART IRQ handler */ + IRQ_HANDLER 117 /* VAD IRQ handler */ + IRQ_HANDLER 118 /* FUSE IRQ handler */ + IRQ_HANDLER 119 /* SECMON IRQ handler */ + IRQ_HANDLER 120 /* RTC IRQ handler */ + IRQ_HANDLER 121 /* BUTN IRQ handler */ + IRQ_HANDLER 122 /* BGPIO IRQ handler */ + IRQ_HANDLER 123 /* BVIO IRQ handler */ + IRQ_HANDLER 124 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 125 /* SYSCTL IRQ handler */ + IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_acmp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_acmp_regs.h new file mode 100644 index 0000000000..9b7f6a5149 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_acmp_regs.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_ACMP_H +#define HPM_ACMP_H + +typedef struct { + struct { + __RW uint32_t CFG; /* 0x0: Configure Register */ + __RW uint32_t DACCFG; /* 0x4: DAC configure register */ + __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ + __RW uint32_t SR; /* 0x10: Status register */ + __RW uint32_t IRQEN; /* 0x14: Interrupt request enable register */ + __RW uint32_t DMAEN; /* 0x18: DMA request enable register */ + __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ + } CHANNEL[4]; +} ACMP_Type; + + +/* Bitfield definition for register of struct array CHANNEL: CFG */ +/* + * HYST (RW) + * + * This bitfield configure the comparator hysteresis. + * 00: Hysteresis level 0 + * 01: Hysteresis level 1 + * 10: Hysteresis level 2 + * 11: Hysteresis level 3 + */ +#define ACMP_CHANNEL_CFG_HYST_MASK (0xC0000000UL) +#define ACMP_CHANNEL_CFG_HYST_SHIFT (30U) +#define ACMP_CHANNEL_CFG_HYST_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HYST_SHIFT) & ACMP_CHANNEL_CFG_HYST_MASK) +#define ACMP_CHANNEL_CFG_HYST_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HYST_MASK) >> ACMP_CHANNEL_CFG_HYST_SHIFT) + +/* + * DACEN (RW) + * + * This bit enable the comparator internal DAC + * 0: DAC disabled + * 1: DAC enabled + */ +#define ACMP_CHANNEL_CFG_DACEN_MASK (0x20000000UL) +#define ACMP_CHANNEL_CFG_DACEN_SHIFT (29U) +#define ACMP_CHANNEL_CFG_DACEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DACEN_SHIFT) & ACMP_CHANNEL_CFG_DACEN_MASK) +#define ACMP_CHANNEL_CFG_DACEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DACEN_MASK) >> ACMP_CHANNEL_CFG_DACEN_SHIFT) + +/* + * HPMODE (RW) + * + * This bit enable the comparator high performance mode. + * 0: HP mode disabled + * 1: HP mode enabled + */ +#define ACMP_CHANNEL_CFG_HPMODE_MASK (0x10000000UL) +#define ACMP_CHANNEL_CFG_HPMODE_SHIFT (28U) +#define ACMP_CHANNEL_CFG_HPMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HPMODE_SHIFT) & ACMP_CHANNEL_CFG_HPMODE_MASK) +#define ACMP_CHANNEL_CFG_HPMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HPMODE_MASK) >> ACMP_CHANNEL_CFG_HPMODE_SHIFT) + +/* + * CMPEN (RW) + * + * This bit enable the comparator. + * 0: ACMP disabled + * 1: ACMP enabled + */ +#define ACMP_CHANNEL_CFG_CMPEN_MASK (0x8000000UL) +#define ACMP_CHANNEL_CFG_CMPEN_SHIFT (27U) +#define ACMP_CHANNEL_CFG_CMPEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPEN_SHIFT) & ACMP_CHANNEL_CFG_CMPEN_MASK) +#define ACMP_CHANNEL_CFG_CMPEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPEN_MASK) >> ACMP_CHANNEL_CFG_CMPEN_SHIFT) + +/* + * MINSEL (RW) + * + * PIN select, from pad_ai_acmp[7:1] and dac_out + */ +#define ACMP_CHANNEL_CFG_MINSEL_MASK (0x7000000UL) +#define ACMP_CHANNEL_CFG_MINSEL_SHIFT (24U) +#define ACMP_CHANNEL_CFG_MINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_MINSEL_SHIFT) & ACMP_CHANNEL_CFG_MINSEL_MASK) +#define ACMP_CHANNEL_CFG_MINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_MINSEL_MASK) >> ACMP_CHANNEL_CFG_MINSEL_SHIFT) + +/* + * PINSEL (RW) + * + * MIN select, from pad_ai_acmp[7:1] and dac_out + */ +#define ACMP_CHANNEL_CFG_PINSEL_MASK (0x700000UL) +#define ACMP_CHANNEL_CFG_PINSEL_SHIFT (20U) +#define ACMP_CHANNEL_CFG_PINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_PINSEL_SHIFT) & ACMP_CHANNEL_CFG_PINSEL_MASK) +#define ACMP_CHANNEL_CFG_PINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_PINSEL_MASK) >> ACMP_CHANNEL_CFG_PINSEL_SHIFT) + +/* + * CMPOEN (RW) + * + * This bit enable the comparator output on pad. + * 0: ACMP output disabled + * 1: ACMP output enabled + */ +#define ACMP_CHANNEL_CFG_CMPOEN_MASK (0x80000UL) +#define ACMP_CHANNEL_CFG_CMPOEN_SHIFT (19U) +#define ACMP_CHANNEL_CFG_CMPOEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPOEN_SHIFT) & ACMP_CHANNEL_CFG_CMPOEN_MASK) +#define ACMP_CHANNEL_CFG_CMPOEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPOEN_MASK) >> ACMP_CHANNEL_CFG_CMPOEN_SHIFT) + +/* + * FLTBYPS (RW) + * + * This bit bypass the comparator output digital filter. + * 0: The ACMP output need pass digital filter + * 1: The ACMP output digital filter is bypassed. + */ +#define ACMP_CHANNEL_CFG_FLTBYPS_MASK (0x40000UL) +#define ACMP_CHANNEL_CFG_FLTBYPS_SHIFT (18U) +#define ACMP_CHANNEL_CFG_FLTBYPS_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) +#define ACMP_CHANNEL_CFG_FLTBYPS_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) >> ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) + +/* + * WINEN (RW) + * + * This bit enable the comparator window mode. + * 0: Window mode is disabled + * 1: Window mode is enabled + */ +#define ACMP_CHANNEL_CFG_WINEN_MASK (0x20000UL) +#define ACMP_CHANNEL_CFG_WINEN_SHIFT (17U) +#define ACMP_CHANNEL_CFG_WINEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_WINEN_SHIFT) & ACMP_CHANNEL_CFG_WINEN_MASK) +#define ACMP_CHANNEL_CFG_WINEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_WINEN_MASK) >> ACMP_CHANNEL_CFG_WINEN_SHIFT) + +/* + * OPOL (RW) + * + * The output polarity control bit. + * 0: The ACMP output remain un-changed. + * 1: The ACMP output is inverted. + */ +#define ACMP_CHANNEL_CFG_OPOL_MASK (0x10000UL) +#define ACMP_CHANNEL_CFG_OPOL_SHIFT (16U) +#define ACMP_CHANNEL_CFG_OPOL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_OPOL_SHIFT) & ACMP_CHANNEL_CFG_OPOL_MASK) +#define ACMP_CHANNEL_CFG_OPOL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_OPOL_MASK) >> ACMP_CHANNEL_CFG_OPOL_SHIFT) + +/* + * FLTMODE (RW) + * + * This bitfield define the ACMP output digital filter mode: + * 000-bypass + * 100-change immediately; + * 101-change after filter; + * 110-stalbe low; + * 111-stable high + */ +#define ACMP_CHANNEL_CFG_FLTMODE_MASK (0xE000U) +#define ACMP_CHANNEL_CFG_FLTMODE_SHIFT (13U) +#define ACMP_CHANNEL_CFG_FLTMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTMODE_SHIFT) & ACMP_CHANNEL_CFG_FLTMODE_MASK) +#define ACMP_CHANNEL_CFG_FLTMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTMODE_MASK) >> ACMP_CHANNEL_CFG_FLTMODE_SHIFT) + +/* + * SYNCEN (RW) + * + * This bit enable the comparator output synchronization. + * 0: ACMP output not synchronized with ACMP clock. + * 1: ACMP output synchronized with ACMP clock. + */ +#define ACMP_CHANNEL_CFG_SYNCEN_MASK (0x1000U) +#define ACMP_CHANNEL_CFG_SYNCEN_SHIFT (12U) +#define ACMP_CHANNEL_CFG_SYNCEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_SYNCEN_SHIFT) & ACMP_CHANNEL_CFG_SYNCEN_MASK) +#define ACMP_CHANNEL_CFG_SYNCEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_SYNCEN_MASK) >> ACMP_CHANNEL_CFG_SYNCEN_SHIFT) + +/* + * FLTLEN (RW) + * + * This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + */ +#define ACMP_CHANNEL_CFG_FLTLEN_MASK (0xFFFU) +#define ACMP_CHANNEL_CFG_FLTLEN_SHIFT (0U) +#define ACMP_CHANNEL_CFG_FLTLEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTLEN_SHIFT) & ACMP_CHANNEL_CFG_FLTLEN_MASK) +#define ACMP_CHANNEL_CFG_FLTLEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTLEN_MASK) >> ACMP_CHANNEL_CFG_FLTLEN_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: DACCFG */ +/* + * DACCFG (RW) + * + * 8bit DAC digital value + */ +#define ACMP_CHANNEL_DACCFG_DACCFG_MASK (0xFFU) +#define ACMP_CHANNEL_DACCFG_DACCFG_SHIFT (0U) +#define ACMP_CHANNEL_DACCFG_DACCFG_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) +#define ACMP_CHANNEL_DACCFG_DACCFG_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) >> ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: SR */ +/* + * FEDGF (RW) + * + * Output falling edge flag. Write 1 to clear this flag. + */ +#define ACMP_CHANNEL_SR_FEDGF_MASK (0x2U) +#define ACMP_CHANNEL_SR_FEDGF_SHIFT (1U) +#define ACMP_CHANNEL_SR_FEDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_FEDGF_SHIFT) & ACMP_CHANNEL_SR_FEDGF_MASK) +#define ACMP_CHANNEL_SR_FEDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_FEDGF_MASK) >> ACMP_CHANNEL_SR_FEDGF_SHIFT) + +/* + * REDGF (RW) + * + * Output rising edge flag. Write 1 to clear this flag. + */ +#define ACMP_CHANNEL_SR_REDGF_MASK (0x1U) +#define ACMP_CHANNEL_SR_REDGF_SHIFT (0U) +#define ACMP_CHANNEL_SR_REDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_REDGF_SHIFT) & ACMP_CHANNEL_SR_REDGF_MASK) +#define ACMP_CHANNEL_SR_REDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_REDGF_MASK) >> ACMP_CHANNEL_SR_REDGF_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: IRQEN */ +/* + * FEDGEN (RW) + * + * Output falling edge flag interrupt enable bit. + */ +#define ACMP_CHANNEL_IRQEN_FEDGEN_MASK (0x2U) +#define ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT (1U) +#define ACMP_CHANNEL_IRQEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) +#define ACMP_CHANNEL_IRQEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) >> ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) + +/* + * REDGEN (RW) + * + * Output rising edge flag interrupt enable bit. + */ +#define ACMP_CHANNEL_IRQEN_REDGEN_MASK (0x1U) +#define ACMP_CHANNEL_IRQEN_REDGEN_SHIFT (0U) +#define ACMP_CHANNEL_IRQEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) +#define ACMP_CHANNEL_IRQEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) >> ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: DMAEN */ +/* + * FEDGEN (RW) + * + * Output falling edge flag DMA request enable bit. + */ +#define ACMP_CHANNEL_DMAEN_FEDGEN_MASK (0x2U) +#define ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT (1U) +#define ACMP_CHANNEL_DMAEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) +#define ACMP_CHANNEL_DMAEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) >> ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) + +/* + * REDGEN (RW) + * + * Output rising edge flag DMA request enable bit. + */ +#define ACMP_CHANNEL_DMAEN_REDGEN_MASK (0x1U) +#define ACMP_CHANNEL_DMAEN_REDGEN_SHIFT (0U) +#define ACMP_CHANNEL_DMAEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) +#define ACMP_CHANNEL_DMAEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) >> ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) + + + +/* CHANNEL register group index macro definition */ +#define ACMP_CHANNEL_CHN0 (0UL) +#define ACMP_CHANNEL_CHN1 (1UL) +#define ACMP_CHANNEL_CHN2 (2UL) +#define ACMP_CHANNEL_CHN3 (3UL) + + +#endif /* HPM_ACMP_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h new file mode 100644 index 0000000000..4a1ff204b0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h @@ -0,0 +1,945 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_ADC12_H +#define HPM_ADC12_H + +typedef struct { + __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ + __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ + __R uint8_t RESERVED0[972]; /* 0x34 - 0x3FF: Reserved */ + __R uint32_t BUS_RESULT[19]; /* 0x400 - 0x448: */ + __R uint8_t RESERVED1[180]; /* 0x44C - 0x4FF: Reserved */ + __RW uint32_t BUF_CFG0; /* 0x500: */ + __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */ + __RW uint32_t SEQ_CFG0; /* 0x800: */ + __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */ + __R uint32_t SEQ_WR_ADDR; /* 0x808: */ + __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ + __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ + __R uint8_t RESERVED3[944]; /* 0x850 - 0xBFF: Reserved */ + struct { + __RW uint32_t PRD_CFG; /* 0xC00: */ + __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ + __R uint32_t PRD_RESULT; /* 0xC08: */ + __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */ + } PRD_CFG[19]; + __R uint8_t RESERVED4[720]; /* 0xD30 - 0xFFF: Reserved */ + __RW uint32_t SAMPLE_CFG[19]; /* 0x1000 - 0x1048: */ + __R uint8_t RESERVED5[184]; /* 0x104C - 0x1103: Reserved */ + __RW uint32_t CONV_CFG1; /* 0x1104: */ + __RW uint32_t ADC_CFG0; /* 0x1108: */ + __R uint8_t RESERVED6[4]; /* 0x110C - 0x110F: Reserved */ + __RW uint32_t INT_STS; /* 0x1110: */ + __RW uint32_t INT_EN; /* 0x1114: */ + __R uint8_t RESERVED7[232]; /* 0x1118 - 0x11FF: Reserved */ + __RW uint32_t ANA_CTRL0; /* 0x1200: */ + __RW uint32_t ANA_CTRL1; /* 0x1204: */ + __R uint8_t RESERVED8[8]; /* 0x1208 - 0x120F: Reserved */ + __RW uint32_t ANA_STATUS; /* 0x1210: */ +} ADC12_Type; + + +/* Bitfield definition for register array: CONFIG */ +/* + * TRIG_LEN (WO) + * + * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + */ +#define ADC12_CONFIG_TRIG_LEN_MASK (0xC0000000UL) +#define ADC12_CONFIG_TRIG_LEN_SHIFT (30U) +#define ADC12_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC12_CONFIG_TRIG_LEN_SHIFT) & ADC12_CONFIG_TRIG_LEN_MASK) +#define ADC12_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC12_CONFIG_TRIG_LEN_MASK) >> ADC12_CONFIG_TRIG_LEN_SHIFT) + +/* + * INTEN3 (RW) + * + * interupt enable for 4th conversion + */ +#define ADC12_CONFIG_INTEN3_MASK (0x20000000UL) +#define ADC12_CONFIG_INTEN3_SHIFT (29U) +#define ADC12_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN3_SHIFT) & ADC12_CONFIG_INTEN3_MASK) +#define ADC12_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN3_MASK) >> ADC12_CONFIG_INTEN3_SHIFT) + +/* + * CHAN3 (RW) + * + * channel number for 4th conversion + */ +#define ADC12_CONFIG_CHAN3_MASK (0x1F000000UL) +#define ADC12_CONFIG_CHAN3_SHIFT (24U) +#define ADC12_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN3_SHIFT) & ADC12_CONFIG_CHAN3_MASK) +#define ADC12_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN3_MASK) >> ADC12_CONFIG_CHAN3_SHIFT) + +/* + * INTEN2 (RW) + * + * interupt enable for 3rd conversion + */ +#define ADC12_CONFIG_INTEN2_MASK (0x200000UL) +#define ADC12_CONFIG_INTEN2_SHIFT (21U) +#define ADC12_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN2_SHIFT) & ADC12_CONFIG_INTEN2_MASK) +#define ADC12_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN2_MASK) >> ADC12_CONFIG_INTEN2_SHIFT) + +/* + * CHAN2 (RW) + * + * channel number for 3rd conversion + */ +#define ADC12_CONFIG_CHAN2_MASK (0x1F0000UL) +#define ADC12_CONFIG_CHAN2_SHIFT (16U) +#define ADC12_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN2_SHIFT) & ADC12_CONFIG_CHAN2_MASK) +#define ADC12_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN2_MASK) >> ADC12_CONFIG_CHAN2_SHIFT) + +/* + * INTEN1 (RW) + * + * interupt enable for 2nd conversion + */ +#define ADC12_CONFIG_INTEN1_MASK (0x2000U) +#define ADC12_CONFIG_INTEN1_SHIFT (13U) +#define ADC12_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN1_SHIFT) & ADC12_CONFIG_INTEN1_MASK) +#define ADC12_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN1_MASK) >> ADC12_CONFIG_INTEN1_SHIFT) + +/* + * CHAN1 (RW) + * + * channel number for 2nd conversion + */ +#define ADC12_CONFIG_CHAN1_MASK (0x1F00U) +#define ADC12_CONFIG_CHAN1_SHIFT (8U) +#define ADC12_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN1_SHIFT) & ADC12_CONFIG_CHAN1_MASK) +#define ADC12_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN1_MASK) >> ADC12_CONFIG_CHAN1_SHIFT) + +/* + * INTEN0 (RW) + * + * interupt enable for 1st conversion + */ +#define ADC12_CONFIG_INTEN0_MASK (0x20U) +#define ADC12_CONFIG_INTEN0_SHIFT (5U) +#define ADC12_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN0_SHIFT) & ADC12_CONFIG_INTEN0_MASK) +#define ADC12_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN0_MASK) >> ADC12_CONFIG_INTEN0_SHIFT) + +/* + * CHAN0 (RW) + * + * channel number for 1st conversion + */ +#define ADC12_CONFIG_CHAN0_MASK (0x1FU) +#define ADC12_CONFIG_CHAN0_SHIFT (0U) +#define ADC12_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN0_SHIFT) & ADC12_CONFIG_CHAN0_MASK) +#define ADC12_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN0_MASK) >> ADC12_CONFIG_CHAN0_SHIFT) + +/* Bitfield definition for register: TRG_DMA_ADDR */ +/* + * TRG_DMA_ADDR (RW) + * + * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + */ +#define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL) +#define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U) +#define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) +#define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) + +/* Bitfield definition for register array: BUS_RESULT */ +/* + * VALID (RO) + * + * set after conversion finished if wait_dis is set, cleared after software read. + * The first time read with 0 will trigger one new conversion. + * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. + * the result may not realtime if software read once and wait long time to read again + */ +#define ADC12_BUS_RESULT_VALID_MASK (0x10000UL) +#define ADC12_BUS_RESULT_VALID_SHIFT (16U) +#define ADC12_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC12_BUS_RESULT_VALID_MASK) >> ADC12_BUS_RESULT_VALID_SHIFT) + +/* + * CHAN_RESULT (RO) + * + * read this register will trigger one adc conversion. + * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result + * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + */ +#define ADC12_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU) +#define ADC12_BUS_RESULT_CHAN_RESULT_SHIFT (0U) +#define ADC12_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC12_BUS_RESULT_CHAN_RESULT_MASK) >> ADC12_BUS_RESULT_CHAN_RESULT_SHIFT) + +/* Bitfield definition for register: BUF_CFG0 */ +/* + * WAIT_DIS (RW) + * + * set to disable read waiting, get result immediately but maybe not current conversion result. + */ +#define ADC12_BUF_CFG0_WAIT_DIS_MASK (0x1U) +#define ADC12_BUF_CFG0_WAIT_DIS_SHIFT (0U) +#define ADC12_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC12_BUF_CFG0_WAIT_DIS_SHIFT) & ADC12_BUF_CFG0_WAIT_DIS_MASK) +#define ADC12_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC12_BUF_CFG0_WAIT_DIS_MASK) >> ADC12_BUF_CFG0_WAIT_DIS_SHIFT) + +/* Bitfield definition for register: SEQ_CFG0 */ +/* + * CYCLE (RO) + * + * current dma write cycle bit + */ +#define ADC12_SEQ_CFG0_CYCLE_MASK (0x80000000UL) +#define ADC12_SEQ_CFG0_CYCLE_SHIFT (31U) +#define ADC12_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_CYCLE_MASK) >> ADC12_SEQ_CFG0_CYCLE_SHIFT) + +/* + * SEQ_LEN (RW) + * + * sequence queue length, 0 for one, 0xF for 16 + */ +#define ADC12_SEQ_CFG0_SEQ_LEN_MASK (0xF00U) +#define ADC12_SEQ_CFG0_SEQ_LEN_SHIFT (8U) +#define ADC12_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC12_SEQ_CFG0_SEQ_LEN_MASK) +#define ADC12_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_SEQ_LEN_MASK) >> ADC12_SEQ_CFG0_SEQ_LEN_SHIFT) + +/* + * RESTART_EN (RW) + * + * if set together with cont_en, HW will continue process the whole queue after trigger once. + * If cont_en is 0, this bit is not used + */ +#define ADC12_SEQ_CFG0_RESTART_EN_MASK (0x10U) +#define ADC12_SEQ_CFG0_RESTART_EN_SHIFT (4U) +#define ADC12_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_RESTART_EN_SHIFT) & ADC12_SEQ_CFG0_RESTART_EN_MASK) +#define ADC12_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_RESTART_EN_MASK) >> ADC12_SEQ_CFG0_RESTART_EN_SHIFT) + +/* + * CONT_EN (RW) + * + * if set, HW will continue process the queue till end(seq_len) after trigger once + */ +#define ADC12_SEQ_CFG0_CONT_EN_MASK (0x8U) +#define ADC12_SEQ_CFG0_CONT_EN_SHIFT (3U) +#define ADC12_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_CONT_EN_SHIFT) & ADC12_SEQ_CFG0_CONT_EN_MASK) +#define ADC12_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_CONT_EN_MASK) >> ADC12_SEQ_CFG0_CONT_EN_SHIFT) + +/* + * SW_TRIG (WO) + * + * SW trigger, pulse signal, cleared by HW one cycle later + */ +#define ADC12_SEQ_CFG0_SW_TRIG_MASK (0x4U) +#define ADC12_SEQ_CFG0_SW_TRIG_SHIFT (2U) +#define ADC12_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_SW_TRIG_SHIFT) & ADC12_SEQ_CFG0_SW_TRIG_MASK) +#define ADC12_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_SW_TRIG_MASK) >> ADC12_SEQ_CFG0_SW_TRIG_SHIFT) + +/* + * SW_TRIG_EN (RW) + * + * set to enable SW trigger + */ +#define ADC12_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U) +#define ADC12_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U) +#define ADC12_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC12_SEQ_CFG0_SW_TRIG_EN_MASK) +#define ADC12_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC12_SEQ_CFG0_SW_TRIG_EN_SHIFT) + +/* + * HW_TRIG_EN (RW) + * + * set to enable external HW trigger, only trigger on posedge + */ +#define ADC12_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U) +#define ADC12_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U) +#define ADC12_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC12_SEQ_CFG0_HW_TRIG_EN_MASK) +#define ADC12_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC12_SEQ_CFG0_HW_TRIG_EN_SHIFT) + +/* Bitfield definition for register: SEQ_DMA_ADDR */ +/* + * TAR_ADDR (RW) + * + * dma target address, should be 4-byte aligned + */ +#define ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL) +#define ADC12_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U) +#define ADC12_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK) +#define ADC12_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC12_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) + +/* Bitfield definition for register: SEQ_WR_ADDR */ +/* + * SEQ_WR_POINTER (RO) + * + * HW update this field after each dma write, it indicate the next dma write pointer. + * dma write address is (tar_addr+seq_wr_pointer)*4 + */ +#define ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFU) +#define ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT (0U) +#define ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_GET(x) (((uint32_t)(x) & ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK) >> ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT) + +/* Bitfield definition for register: SEQ_DMA_CFG */ +/* + * STOP_POS (RW) + * + * if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet + */ +#define ADC12_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL) +#define ADC12_SEQ_DMA_CFG_STOP_POS_SHIFT (16U) +#define ADC12_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC12_SEQ_DMA_CFG_STOP_POS_MASK) +#define ADC12_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC12_SEQ_DMA_CFG_STOP_POS_SHIFT) + +/* + * DMA_RST (RW) + * + * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. + * SW should clear all cycle bit in buffer to 0 before clear dma_rst + */ +#define ADC12_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U) +#define ADC12_SEQ_DMA_CFG_DMA_RST_SHIFT (13U) +#define ADC12_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC12_SEQ_DMA_CFG_DMA_RST_MASK) +#define ADC12_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC12_SEQ_DMA_CFG_DMA_RST_SHIFT) + +/* + * STOP_EN (RW) + * + * set to stop dma if reach the stop_pos + */ +#define ADC12_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U) +#define ADC12_SEQ_DMA_CFG_STOP_EN_SHIFT (12U) +#define ADC12_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC12_SEQ_DMA_CFG_STOP_EN_MASK) +#define ADC12_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC12_SEQ_DMA_CFG_STOP_EN_SHIFT) + +/* + * BUF_LEN (RW) + * + * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 + * 0 for 4byte; + * 0xFFF for 16kbyte. + */ +#define ADC12_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU) +#define ADC12_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U) +#define ADC12_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC12_SEQ_DMA_CFG_BUF_LEN_MASK) +#define ADC12_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC12_SEQ_DMA_CFG_BUF_LEN_SHIFT) + +/* Bitfield definition for register array: SEQ_QUE */ +/* + * SEQ_INT_EN (RW) + * + * interrupt enable for current conversion + */ +#define ADC12_SEQ_QUE_SEQ_INT_EN_MASK (0x20U) +#define ADC12_SEQ_QUE_SEQ_INT_EN_SHIFT (5U) +#define ADC12_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC12_SEQ_QUE_SEQ_INT_EN_MASK) +#define ADC12_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC12_SEQ_QUE_SEQ_INT_EN_SHIFT) + +/* + * CHAN_NUM_4_0 (RW) + * + * channel number for current conversion + */ +#define ADC12_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU) +#define ADC12_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U) +#define ADC12_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC12_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC12_SEQ_QUE_CHAN_NUM_4_0_MASK) +#define ADC12_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC12_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC12_SEQ_QUE_CHAN_NUM_4_0_SHIFT) + +/* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ +/* + * PRESCALE (RW) + * + * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + */ +#define ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U) +#define ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U) +#define ADC12_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK) +#define ADC12_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) + +/* + * PRD (RW) + * + * conver period, with prescale. + * Set to 0 means disable current channel + */ +#define ADC12_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU) +#define ADC12_PRD_CFG_PRD_CFG_PRD_SHIFT (0U) +#define ADC12_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC12_PRD_CFG_PRD_CFG_PRD_MASK) +#define ADC12_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC12_PRD_CFG_PRD_CFG_PRD_SHIFT) + +/* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */ +/* + * THSHDH (RW) + * + * threshold high, assert interrupt(if enabled) if result exceed high or low. + */ +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) + +/* + * THSHDL (RW) + * + * threshold low + */ +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) + +/* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */ +/* + * CHAN_RESULT (RO) + * + * adc convert result, update after each valid conversion. + * it may be updated period according to config, also may be updated due to other queue convert the same channel + */ +#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU) +#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U) +#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) + +/* Bitfield definition for register array: SAMPLE_CFG */ +/* + * DIFF_SEL (RW) + * + * set to 1 to select differential channel + */ +#define ADC12_SAMPLE_CFG_DIFF_SEL_MASK (0x1000U) +#define ADC12_SAMPLE_CFG_DIFF_SEL_SHIFT (12U) +#define ADC12_SAMPLE_CFG_DIFF_SEL_SET(x) (((uint32_t)(x) << ADC12_SAMPLE_CFG_DIFF_SEL_SHIFT) & ADC12_SAMPLE_CFG_DIFF_SEL_MASK) +#define ADC12_SAMPLE_CFG_DIFF_SEL_GET(x) (((uint32_t)(x) & ADC12_SAMPLE_CFG_DIFF_SEL_MASK) >> ADC12_SAMPLE_CFG_DIFF_SEL_SHIFT) + +/* + * SAMPLE_CLOCK_NUMBER_SHIFT (RW) + * + * shift for sample_clock_number + */ +#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U) +#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U) +#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) +#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) + +/* + * SAMPLE_CLOCK_NUMBER (RW) + * + * sample clock number, base on clock_period, default one period + */ +#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU) +#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U) +#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) +#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) + +/* Bitfield definition for register: CONV_CFG1 */ +/* + * CONVERT_CLOCK_NUMBER (RW) + * + * convert clock numbers, set to 13 (0xD) for 12bit mode, which means convert need 14 adc clock cycles(based on clock after divider); + * set to 11 for 10bit mode; set to 9 for 8bit mode; set to 7 or 6bit mode; + * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 13 for 12bit mode, clock_divder to 2, then each ADC convertion(plus sample) need 18(14 convert, 4 sample) cycles(66MHz). + */ +#define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U) +#define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U) +#define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) +#define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) + +/* + * CLOCK_DIVIDER (RW) + * + * clock_period, N half clock cycle per half adc cycle + * 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. + * set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + */ +#define ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) +#define ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) +#define ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) +#define ADC12_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT) + +/* Bitfield definition for register: ADC_CFG0 */ +/* + * SEL_SYNC_AHB (RW) + * + * set to 1 will enable sync AHB bus, to get better bus performance. + * Adc_clk must to be set to same as bus clock at this mode + */ +#define ADC12_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL) +#define ADC12_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U) +#define ADC12_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC12_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC12_ADC_CFG0_SEL_SYNC_AHB_MASK) +#define ADC12_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC12_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC12_ADC_CFG0_SEL_SYNC_AHB_SHIFT) + +/* + * ADC_AHB_EN (RW) + * + * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + */ +#define ADC12_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL) +#define ADC12_ADC_CFG0_ADC_AHB_EN_SHIFT (29U) +#define ADC12_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC12_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC12_ADC_CFG0_ADC_AHB_EN_MASK) +#define ADC12_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC12_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC12_ADC_CFG0_ADC_AHB_EN_SHIFT) + +/* Bitfield definition for register: INT_STS */ +/* + * TRIG_CMPT (W1C) + * + * interrupt for one trigger conversion complete if enabled + */ +#define ADC12_INT_STS_TRIG_CMPT_MASK (0x80000000UL) +#define ADC12_INT_STS_TRIG_CMPT_SHIFT (31U) +#define ADC12_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_TRIG_CMPT_SHIFT) & ADC12_INT_STS_TRIG_CMPT_MASK) +#define ADC12_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_CMPT_MASK) >> ADC12_INT_STS_TRIG_CMPT_SHIFT) + +/* + * TRIG_SW_CFLCT (W1C) + * + */ +#define ADC12_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) +#define ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT (30U) +#define ADC12_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC12_INT_STS_TRIG_SW_CFLCT_MASK) +#define ADC12_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT) + +/* + * TRIG_HW_CFLCT (RW) + * + */ +#define ADC12_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) +#define ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT (29U) +#define ADC12_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC12_INT_STS_TRIG_HW_CFLCT_MASK) +#define ADC12_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT) + +/* + * READ_CFLCT (W1C) + * + * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + */ +#define ADC12_INT_STS_READ_CFLCT_MASK (0x10000000UL) +#define ADC12_INT_STS_READ_CFLCT_SHIFT (28U) +#define ADC12_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_READ_CFLCT_SHIFT) & ADC12_INT_STS_READ_CFLCT_MASK) +#define ADC12_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_READ_CFLCT_MASK) >> ADC12_INT_STS_READ_CFLCT_SHIFT) + +/* + * SEQ_SW_CFLCT (W1C) + * + * sequence queue conflict interrup, set if HW or SW trigger received during conversion + */ +#define ADC12_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL) +#define ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT (27U) +#define ADC12_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC12_INT_STS_SEQ_SW_CFLCT_MASK) +#define ADC12_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT) + +/* + * SEQ_HW_CFLCT (RW) + * + */ +#define ADC12_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) +#define ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT (26U) +#define ADC12_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC12_INT_STS_SEQ_HW_CFLCT_MASK) +#define ADC12_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT) + +/* + * SEQ_DMAABT (W1C) + * + * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + */ +#define ADC12_INT_STS_SEQ_DMAABT_MASK (0x2000000UL) +#define ADC12_INT_STS_SEQ_DMAABT_SHIFT (25U) +#define ADC12_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_DMAABT_SHIFT) & ADC12_INT_STS_SEQ_DMAABT_MASK) +#define ADC12_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_DMAABT_MASK) >> ADC12_INT_STS_SEQ_DMAABT_SHIFT) + +/* + * SEQ_CMPT (W1C) + * + * the whole sequence complete interrupt + */ +#define ADC12_INT_STS_SEQ_CMPT_MASK (0x1000000UL) +#define ADC12_INT_STS_SEQ_CMPT_SHIFT (24U) +#define ADC12_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_CMPT_SHIFT) & ADC12_INT_STS_SEQ_CMPT_MASK) +#define ADC12_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CMPT_MASK) >> ADC12_INT_STS_SEQ_CMPT_SHIFT) + +/* + * SEQ_CVC (W1C) + * + * one conversion complete in seq_queue if related seq_int_en is set + */ +#define ADC12_INT_STS_SEQ_CVC_MASK (0x800000UL) +#define ADC12_INT_STS_SEQ_CVC_SHIFT (23U) +#define ADC12_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_CVC_SHIFT) & ADC12_INT_STS_SEQ_CVC_MASK) +#define ADC12_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CVC_MASK) >> ADC12_INT_STS_SEQ_CVC_SHIFT) + +/* + * DMA_FIFO_FULL (RW) + * + */ +#define ADC12_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) +#define ADC12_INT_STS_DMA_FIFO_FULL_SHIFT (22U) +#define ADC12_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC12_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC12_INT_STS_DMA_FIFO_FULL_MASK) +#define ADC12_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_STS_DMA_FIFO_FULL_MASK) >> ADC12_INT_STS_DMA_FIFO_FULL_SHIFT) + +/* + * AHB_ERR (RW) + * + * set if got hresp=1 + */ +#define ADC12_INT_STS_AHB_ERR_MASK (0x200000UL) +#define ADC12_INT_STS_AHB_ERR_SHIFT (21U) +#define ADC12_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC12_INT_STS_AHB_ERR_SHIFT) & ADC12_INT_STS_AHB_ERR_MASK) +#define ADC12_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_STS_AHB_ERR_MASK) >> ADC12_INT_STS_AHB_ERR_SHIFT) + +/* + * WDOG (W1C) + * + * set if one chanel watch dog event triggered + */ +#define ADC12_INT_STS_WDOG_MASK (0x7FFFFUL) +#define ADC12_INT_STS_WDOG_SHIFT (0U) +#define ADC12_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC12_INT_STS_WDOG_SHIFT) & ADC12_INT_STS_WDOG_MASK) +#define ADC12_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC12_INT_STS_WDOG_MASK) >> ADC12_INT_STS_WDOG_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * TRIG_CMPT (W1C) + * + * interrupt for one trigger conversion complete if enabled + */ +#define ADC12_INT_EN_TRIG_CMPT_MASK (0x80000000UL) +#define ADC12_INT_EN_TRIG_CMPT_SHIFT (31U) +#define ADC12_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_TRIG_CMPT_SHIFT) & ADC12_INT_EN_TRIG_CMPT_MASK) +#define ADC12_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_CMPT_MASK) >> ADC12_INT_EN_TRIG_CMPT_SHIFT) + +/* + * TRIG_SW_CFLCT (W1C) + * + */ +#define ADC12_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) +#define ADC12_INT_EN_TRIG_SW_CFLCT_SHIFT (30U) +#define ADC12_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC12_INT_EN_TRIG_SW_CFLCT_MASK) +#define ADC12_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC12_INT_EN_TRIG_SW_CFLCT_SHIFT) + +/* + * TRIG_HW_CFLCT (RW) + * + */ +#define ADC12_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL) +#define ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT (29U) +#define ADC12_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC12_INT_EN_TRIG_HW_CFLCT_MASK) +#define ADC12_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT) + +/* + * READ_CFLCT (W1C) + * + * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + */ +#define ADC12_INT_EN_READ_CFLCT_MASK (0x10000000UL) +#define ADC12_INT_EN_READ_CFLCT_SHIFT (28U) +#define ADC12_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_READ_CFLCT_SHIFT) & ADC12_INT_EN_READ_CFLCT_MASK) +#define ADC12_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_READ_CFLCT_MASK) >> ADC12_INT_EN_READ_CFLCT_SHIFT) + +/* + * SEQ_SW_CFLCT (W1C) + * + * sequence queue conflict interrup, set if HW or SW trigger received during conversion + */ +#define ADC12_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL) +#define ADC12_INT_EN_SEQ_SW_CFLCT_SHIFT (27U) +#define ADC12_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC12_INT_EN_SEQ_SW_CFLCT_MASK) +#define ADC12_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC12_INT_EN_SEQ_SW_CFLCT_SHIFT) + +/* + * SEQ_HW_CFLCT (RW) + * + */ +#define ADC12_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL) +#define ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT (26U) +#define ADC12_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC12_INT_EN_SEQ_HW_CFLCT_MASK) +#define ADC12_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT) + +/* + * SEQ_DMAABT (W1C) + * + * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + */ +#define ADC12_INT_EN_SEQ_DMAABT_MASK (0x2000000UL) +#define ADC12_INT_EN_SEQ_DMAABT_SHIFT (25U) +#define ADC12_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_DMAABT_SHIFT) & ADC12_INT_EN_SEQ_DMAABT_MASK) +#define ADC12_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_DMAABT_MASK) >> ADC12_INT_EN_SEQ_DMAABT_SHIFT) + +/* + * SEQ_CMPT (W1C) + * + * the whole sequence complete interrupt + */ +#define ADC12_INT_EN_SEQ_CMPT_MASK (0x1000000UL) +#define ADC12_INT_EN_SEQ_CMPT_SHIFT (24U) +#define ADC12_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_CMPT_SHIFT) & ADC12_INT_EN_SEQ_CMPT_MASK) +#define ADC12_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CMPT_MASK) >> ADC12_INT_EN_SEQ_CMPT_SHIFT) + +/* + * SEQ_CVC (W1C) + * + * one conversion complete in seq_queue if related seq_int_en is set + */ +#define ADC12_INT_EN_SEQ_CVC_MASK (0x800000UL) +#define ADC12_INT_EN_SEQ_CVC_SHIFT (23U) +#define ADC12_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_CVC_SHIFT) & ADC12_INT_EN_SEQ_CVC_MASK) +#define ADC12_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CVC_MASK) >> ADC12_INT_EN_SEQ_CVC_SHIFT) + +/* + * DMA_FIFO_FULL (W1C) + * + * DMA fifo full interrupt, user need to check clock frequency if it's set. + */ +#define ADC12_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL) +#define ADC12_INT_EN_DMA_FIFO_FULL_SHIFT (22U) +#define ADC12_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC12_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC12_INT_EN_DMA_FIFO_FULL_MASK) +#define ADC12_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_EN_DMA_FIFO_FULL_MASK) >> ADC12_INT_EN_DMA_FIFO_FULL_SHIFT) + +/* + * AHB_ERR (W1C) + * + * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + */ +#define ADC12_INT_EN_AHB_ERR_MASK (0x200000UL) +#define ADC12_INT_EN_AHB_ERR_SHIFT (21U) +#define ADC12_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC12_INT_EN_AHB_ERR_SHIFT) & ADC12_INT_EN_AHB_ERR_MASK) +#define ADC12_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_EN_AHB_ERR_MASK) >> ADC12_INT_EN_AHB_ERR_SHIFT) + +/* + * WDOG (W1C) + * + * set if one chanel watch dog event triggered + */ +#define ADC12_INT_EN_WDOG_MASK (0x7FFFFUL) +#define ADC12_INT_EN_WDOG_SHIFT (0U) +#define ADC12_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC12_INT_EN_WDOG_SHIFT) & ADC12_INT_EN_WDOG_MASK) +#define ADC12_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC12_INT_EN_WDOG_MASK) >> ADC12_INT_EN_WDOG_SHIFT) + +/* Bitfield definition for register: ANA_CTRL0 */ +/* + * CAL_VAL_DIFF (RW) + * + * calibration value for differential mode + */ +#define ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK (0x7F000000UL) +#define ADC12_ANA_CTRL0_CAL_VAL_DIFF_SHIFT (24U) +#define ADC12_ANA_CTRL0_CAL_VAL_DIFF_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_CAL_VAL_DIFF_SHIFT) & ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK) +#define ADC12_ANA_CTRL0_CAL_VAL_DIFF_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK) >> ADC12_ANA_CTRL0_CAL_VAL_DIFF_SHIFT) + +/* + * CAL_VAL_SE (RW) + * + * calibration value for single-end mode + */ +#define ADC12_ANA_CTRL0_CAL_VAL_SE_MASK (0x7F0000UL) +#define ADC12_ANA_CTRL0_CAL_VAL_SE_SHIFT (16U) +#define ADC12_ANA_CTRL0_CAL_VAL_SE_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_CAL_VAL_SE_SHIFT) & ADC12_ANA_CTRL0_CAL_VAL_SE_MASK) +#define ADC12_ANA_CTRL0_CAL_VAL_SE_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_CAL_VAL_SE_MASK) >> ADC12_ANA_CTRL0_CAL_VAL_SE_SHIFT) + +/* + * REARM_EN (RW) + * + * set will insert one adc cycle rearm before sample, user need to increase one to sample_clock_number + */ +#define ADC12_ANA_CTRL0_REARM_EN_MASK (0x4000U) +#define ADC12_ANA_CTRL0_REARM_EN_SHIFT (14U) +#define ADC12_ANA_CTRL0_REARM_EN_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_REARM_EN_SHIFT) & ADC12_ANA_CTRL0_REARM_EN_MASK) +#define ADC12_ANA_CTRL0_REARM_EN_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_REARM_EN_MASK) >> ADC12_ANA_CTRL0_REARM_EN_SHIFT) + +/* + * SELRANGE_LDO (RW) + * + * Defines the range for the LDO reference (vdd_soc) + * selrange_ldo = 0: LDO reference dvdd or vref_ldo in range [0.81;0.99] + * selrange_ldo = 1: LDO reference dvdd or vref_ldo in range [0.99;1.21] + */ +#define ADC12_ANA_CTRL0_SELRANGE_LDO_MASK (0x800U) +#define ADC12_ANA_CTRL0_SELRANGE_LDO_SHIFT (11U) +#define ADC12_ANA_CTRL0_SELRANGE_LDO_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_SELRANGE_LDO_SHIFT) & ADC12_ANA_CTRL0_SELRANGE_LDO_MASK) +#define ADC12_ANA_CTRL0_SELRANGE_LDO_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_SELRANGE_LDO_MASK) >> ADC12_ANA_CTRL0_SELRANGE_LDO_SHIFT) + +/* + * ENLDO (RW) + * + * set to enable adc LDO, need at least 20us for LDO to be stable. + */ +#define ADC12_ANA_CTRL0_ENLDO_MASK (0x40U) +#define ADC12_ANA_CTRL0_ENLDO_SHIFT (6U) +#define ADC12_ANA_CTRL0_ENLDO_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_ENLDO_SHIFT) & ADC12_ANA_CTRL0_ENLDO_MASK) +#define ADC12_ANA_CTRL0_ENLDO_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_ENLDO_MASK) >> ADC12_ANA_CTRL0_ENLDO_SHIFT) + +/* + * ENADC (RW) + * + * set to enable adc analog function. user need set it after LDO stable, or wait at least 20us after setting enldo, then set this bit. + */ +#define ADC12_ANA_CTRL0_ENADC_MASK (0x20U) +#define ADC12_ANA_CTRL0_ENADC_SHIFT (5U) +#define ADC12_ANA_CTRL0_ENADC_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_ENADC_SHIFT) & ADC12_ANA_CTRL0_ENADC_MASK) +#define ADC12_ANA_CTRL0_ENADC_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_ENADC_MASK) >> ADC12_ANA_CTRL0_ENADC_SHIFT) + +/* + * RESETADC (RW) + * + * set to 1 to reset adc analog; default high. + */ +#define ADC12_ANA_CTRL0_RESETADC_MASK (0x10U) +#define ADC12_ANA_CTRL0_RESETADC_SHIFT (4U) +#define ADC12_ANA_CTRL0_RESETADC_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_RESETADC_SHIFT) & ADC12_ANA_CTRL0_RESETADC_MASK) +#define ADC12_ANA_CTRL0_RESETADC_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_RESETADC_MASK) >> ADC12_ANA_CTRL0_RESETADC_SHIFT) + +/* + * RESETCAL (RW) + * + * set to 1 to reset calibration logic; default high. + */ +#define ADC12_ANA_CTRL0_RESETCAL_MASK (0x8U) +#define ADC12_ANA_CTRL0_RESETCAL_SHIFT (3U) +#define ADC12_ANA_CTRL0_RESETCAL_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_RESETCAL_SHIFT) & ADC12_ANA_CTRL0_RESETCAL_MASK) +#define ADC12_ANA_CTRL0_RESETCAL_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_RESETCAL_MASK) >> ADC12_ANA_CTRL0_RESETCAL_SHIFT) + +/* + * STARTCAL (RW) + * + * set to start the offset calibration cycle (Active H). user need to clear it after setting it. + */ +#define ADC12_ANA_CTRL0_STARTCAL_MASK (0x4U) +#define ADC12_ANA_CTRL0_STARTCAL_SHIFT (2U) +#define ADC12_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_STARTCAL_SHIFT) & ADC12_ANA_CTRL0_STARTCAL_MASK) +#define ADC12_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_STARTCAL_MASK) >> ADC12_ANA_CTRL0_STARTCAL_SHIFT) + +/* + * LOADCAL (RW) + * + * Signal that loads the offset calibration word into the internal registers (Active H) + */ +#define ADC12_ANA_CTRL0_LOADCAL_MASK (0x2U) +#define ADC12_ANA_CTRL0_LOADCAL_SHIFT (1U) +#define ADC12_ANA_CTRL0_LOADCAL_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_LOADCAL_SHIFT) & ADC12_ANA_CTRL0_LOADCAL_MASK) +#define ADC12_ANA_CTRL0_LOADCAL_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_LOADCAL_MASK) >> ADC12_ANA_CTRL0_LOADCAL_SHIFT) + +/* Bitfield definition for register: ANA_CTRL1 */ +/* + * SELRES (RW) + * + * 11-12bit + * 10-10bit + * 01-8bit + * 00-6bit + */ +#define ADC12_ANA_CTRL1_SELRES_MASK (0xC0U) +#define ADC12_ANA_CTRL1_SELRES_SHIFT (6U) +#define ADC12_ANA_CTRL1_SELRES_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL1_SELRES_SHIFT) & ADC12_ANA_CTRL1_SELRES_MASK) +#define ADC12_ANA_CTRL1_SELRES_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL1_SELRES_MASK) >> ADC12_ANA_CTRL1_SELRES_SHIFT) + +/* Bitfield definition for register: ANA_STATUS */ +/* + * CALON (RW) + * + * Indicates if the ADC is in calibration mode (Active H). + */ +#define ADC12_ANA_STATUS_CALON_MASK (0x80U) +#define ADC12_ANA_STATUS_CALON_SHIFT (7U) +#define ADC12_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC12_ANA_STATUS_CALON_SHIFT) & ADC12_ANA_STATUS_CALON_MASK) +#define ADC12_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC12_ANA_STATUS_CALON_MASK) >> ADC12_ANA_STATUS_CALON_SHIFT) + +/* + * CAL_OUT (RW) + * + */ +#define ADC12_ANA_STATUS_CAL_OUT_MASK (0x7FU) +#define ADC12_ANA_STATUS_CAL_OUT_SHIFT (0U) +#define ADC12_ANA_STATUS_CAL_OUT_SET(x) (((uint32_t)(x) << ADC12_ANA_STATUS_CAL_OUT_SHIFT) & ADC12_ANA_STATUS_CAL_OUT_MASK) +#define ADC12_ANA_STATUS_CAL_OUT_GET(x) (((uint32_t)(x) & ADC12_ANA_STATUS_CAL_OUT_MASK) >> ADC12_ANA_STATUS_CAL_OUT_SHIFT) + + + +/* CONFIG register group index macro definition */ +#define ADC12_CONFIG_TRG0A (0UL) +#define ADC12_CONFIG_TRG0B (1UL) +#define ADC12_CONFIG_TRG0C (2UL) +#define ADC12_CONFIG_TRG1A (3UL) +#define ADC12_CONFIG_TRG1B (4UL) +#define ADC12_CONFIG_TRG1C (5UL) +#define ADC12_CONFIG_TRG2A (6UL) +#define ADC12_CONFIG_TRG2B (7UL) +#define ADC12_CONFIG_TRG2C (8UL) +#define ADC12_CONFIG_TRG3A (9UL) +#define ADC12_CONFIG_TRG3B (10UL) +#define ADC12_CONFIG_TRG3C (11UL) + +/* BUS_RESULT register group index macro definition */ +#define ADC12_BUS_RESULT_CHN0 (0UL) +#define ADC12_BUS_RESULT_CHN1 (1UL) +#define ADC12_BUS_RESULT_CHN2 (2UL) +#define ADC12_BUS_RESULT_CHN3 (3UL) +#define ADC12_BUS_RESULT_CHN4 (4UL) +#define ADC12_BUS_RESULT_CHN5 (5UL) +#define ADC12_BUS_RESULT_CHN6 (6UL) +#define ADC12_BUS_RESULT_CHN7 (7UL) +#define ADC12_BUS_RESULT_CHN8 (8UL) +#define ADC12_BUS_RESULT_CHN9 (9UL) +#define ADC12_BUS_RESULT_CHN10 (10UL) +#define ADC12_BUS_RESULT_CHN11 (11UL) +#define ADC12_BUS_RESULT_CHN12 (12UL) +#define ADC12_BUS_RESULT_CHN13 (13UL) +#define ADC12_BUS_RESULT_CHN14 (14UL) +#define ADC12_BUS_RESULT_CHN15 (15UL) +#define ADC12_BUS_RESULT_CHN16 (16UL) +#define ADC12_BUS_RESULT_CHN17 (17UL) +#define ADC12_BUS_RESULT_CHN18 (18UL) + +/* SEQ_QUE register group index macro definition */ +#define ADC12_SEQ_QUE_CFG0 (0UL) +#define ADC12_SEQ_QUE_CFG1 (1UL) +#define ADC12_SEQ_QUE_CFG2 (2UL) +#define ADC12_SEQ_QUE_CFG3 (3UL) +#define ADC12_SEQ_QUE_CFG4 (4UL) +#define ADC12_SEQ_QUE_CFG5 (5UL) +#define ADC12_SEQ_QUE_CFG6 (6UL) +#define ADC12_SEQ_QUE_CFG7 (7UL) +#define ADC12_SEQ_QUE_CFG8 (8UL) +#define ADC12_SEQ_QUE_CFG9 (9UL) +#define ADC12_SEQ_QUE_CFG10 (10UL) +#define ADC12_SEQ_QUE_CFG11 (11UL) +#define ADC12_SEQ_QUE_CFG12 (12UL) +#define ADC12_SEQ_QUE_CFG13 (13UL) +#define ADC12_SEQ_QUE_CFG14 (14UL) +#define ADC12_SEQ_QUE_CFG15 (15UL) + +/* PRD_CFG register group index macro definition */ +#define ADC12_PRD_CFG_CHN0 (0UL) +#define ADC12_PRD_CFG_CHN1 (1UL) +#define ADC12_PRD_CFG_CHN2 (2UL) +#define ADC12_PRD_CFG_CHN3 (3UL) +#define ADC12_PRD_CFG_CHN4 (4UL) +#define ADC12_PRD_CFG_CHN5 (5UL) +#define ADC12_PRD_CFG_CHN6 (6UL) +#define ADC12_PRD_CFG_CHN7 (7UL) +#define ADC12_PRD_CFG_CHN8 (8UL) +#define ADC12_PRD_CFG_CHN9 (9UL) +#define ADC12_PRD_CFG_CHN10 (10UL) +#define ADC12_PRD_CFG_CHN11 (11UL) +#define ADC12_PRD_CFG_CHN12 (12UL) +#define ADC12_PRD_CFG_CHN13 (13UL) +#define ADC12_PRD_CFG_CHN14 (14UL) +#define ADC12_PRD_CFG_CHN15 (15UL) +#define ADC12_PRD_CFG_CHN16 (16UL) +#define ADC12_PRD_CFG_CHN17 (17UL) +#define ADC12_PRD_CFG_CHN18 (18UL) + +/* SAMPLE_CFG register group index macro definition */ +#define ADC12_SAMPLE_CFG_CHN0 (0UL) +#define ADC12_SAMPLE_CFG_CHN1 (1UL) +#define ADC12_SAMPLE_CFG_CHN2 (2UL) +#define ADC12_SAMPLE_CFG_CHN3 (3UL) +#define ADC12_SAMPLE_CFG_CHN4 (4UL) +#define ADC12_SAMPLE_CFG_CHN5 (5UL) +#define ADC12_SAMPLE_CFG_CHN6 (6UL) +#define ADC12_SAMPLE_CFG_CHN7 (7UL) +#define ADC12_SAMPLE_CFG_CHN8 (8UL) +#define ADC12_SAMPLE_CFG_CHN9 (9UL) +#define ADC12_SAMPLE_CFG_CHN10 (10UL) +#define ADC12_SAMPLE_CFG_CHN11 (11UL) +#define ADC12_SAMPLE_CFG_CHN12 (12UL) +#define ADC12_SAMPLE_CFG_CHN13 (13UL) +#define ADC12_SAMPLE_CFG_CHN14 (14UL) +#define ADC12_SAMPLE_CFG_CHN15 (15UL) +#define ADC12_SAMPLE_CFG_CHN16 (16UL) +#define ADC12_SAMPLE_CFG_CHN17 (17UL) +#define ADC12_SAMPLE_CFG_CHN18 (18UL) + + +#endif /* HPM_ADC12_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h new file mode 100644 index 0000000000..c12798389c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h @@ -0,0 +1,978 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_ADC16_H +#define HPM_ADC16_H + +typedef struct { + __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ + __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ + __R uint8_t RESERVED0[972]; /* 0x34 - 0x3FF: Reserved */ + __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */ + __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */ + __RW uint32_t BUF_CFG0; /* 0x500: */ + __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */ + __RW uint32_t SEQ_CFG0; /* 0x800: */ + __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */ + __R uint32_t SEQ_WR_ADDR; /* 0x808: */ + __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ + __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ + __R uint8_t RESERVED3[944]; /* 0x850 - 0xBFF: Reserved */ + struct { + __RW uint32_t PRD_CFG; /* 0xC00: */ + __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ + __R uint32_t PRD_RESULT; /* 0xC08: */ + __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */ + } PRD_CFG[16]; + __R uint8_t RESERVED4[768]; /* 0xD00 - 0xFFF: Reserved */ + __RW uint32_t SAMPLE_CFG[16]; /* 0x1000 - 0x103C: */ + __R uint8_t RESERVED5[196]; /* 0x1040 - 0x1103: Reserved */ + __RW uint32_t CONV_CFG1; /* 0x1104: */ + __RW uint32_t ADC_CFG0; /* 0x1108: */ + __R uint8_t RESERVED6[4]; /* 0x110C - 0x110F: Reserved */ + __RW uint32_t INT_STS; /* 0x1110: */ + __RW uint32_t INT_EN; /* 0x1114: */ + __R uint8_t RESERVED7[232]; /* 0x1118 - 0x11FF: Reserved */ + __RW uint32_t ANA_CTRL0; /* 0x1200: */ + __R uint8_t RESERVED8[12]; /* 0x1204 - 0x120F: Reserved */ + __RW uint32_t ANA_STATUS; /* 0x1210: */ + __R uint8_t RESERVED9[492]; /* 0x1214 - 0x13FF: Reserved */ + __RW uint16_t ADC16_PARAMS[34]; /* 0x1400 - 0x1442: */ + __RW uint32_t ADC16_CONFIG0; /* 0x1444: */ + __R uint8_t RESERVED10[24]; /* 0x1448 - 0x145F: Reserved */ + __RW uint32_t ADC16_CONFIG1; /* 0x1460: */ +} ADC16_Type; + + +/* Bitfield definition for register array: CONFIG */ +/* + * TRIG_LEN (WO) + * + * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + */ +#define ADC16_CONFIG_TRIG_LEN_MASK (0xC0000000UL) +#define ADC16_CONFIG_TRIG_LEN_SHIFT (30U) +#define ADC16_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_TRIG_LEN_SHIFT) & ADC16_CONFIG_TRIG_LEN_MASK) +#define ADC16_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_TRIG_LEN_MASK) >> ADC16_CONFIG_TRIG_LEN_SHIFT) + +/* + * INTEN3 (RW) + * + * interupt enable for 4th conversion + */ +#define ADC16_CONFIG_INTEN3_MASK (0x20000000UL) +#define ADC16_CONFIG_INTEN3_SHIFT (29U) +#define ADC16_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN3_SHIFT) & ADC16_CONFIG_INTEN3_MASK) +#define ADC16_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN3_MASK) >> ADC16_CONFIG_INTEN3_SHIFT) + +/* + * CHAN3 (RW) + * + * channel number for 4th conversion + */ +#define ADC16_CONFIG_CHAN3_MASK (0x1F000000UL) +#define ADC16_CONFIG_CHAN3_SHIFT (24U) +#define ADC16_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN3_SHIFT) & ADC16_CONFIG_CHAN3_MASK) +#define ADC16_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN3_MASK) >> ADC16_CONFIG_CHAN3_SHIFT) + +/* + * INTEN2 (RW) + * + * interupt enable for 3rd conversion + */ +#define ADC16_CONFIG_INTEN2_MASK (0x200000UL) +#define ADC16_CONFIG_INTEN2_SHIFT (21U) +#define ADC16_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN2_SHIFT) & ADC16_CONFIG_INTEN2_MASK) +#define ADC16_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN2_MASK) >> ADC16_CONFIG_INTEN2_SHIFT) + +/* + * CHAN2 (RW) + * + * channel number for 3rd conversion + */ +#define ADC16_CONFIG_CHAN2_MASK (0x1F0000UL) +#define ADC16_CONFIG_CHAN2_SHIFT (16U) +#define ADC16_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN2_SHIFT) & ADC16_CONFIG_CHAN2_MASK) +#define ADC16_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN2_MASK) >> ADC16_CONFIG_CHAN2_SHIFT) + +/* + * INTEN1 (RW) + * + * interupt enable for 2nd conversion + */ +#define ADC16_CONFIG_INTEN1_MASK (0x2000U) +#define ADC16_CONFIG_INTEN1_SHIFT (13U) +#define ADC16_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN1_SHIFT) & ADC16_CONFIG_INTEN1_MASK) +#define ADC16_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN1_MASK) >> ADC16_CONFIG_INTEN1_SHIFT) + +/* + * CHAN1 (RW) + * + * channel number for 2nd conversion + */ +#define ADC16_CONFIG_CHAN1_MASK (0x1F00U) +#define ADC16_CONFIG_CHAN1_SHIFT (8U) +#define ADC16_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN1_SHIFT) & ADC16_CONFIG_CHAN1_MASK) +#define ADC16_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN1_MASK) >> ADC16_CONFIG_CHAN1_SHIFT) + +/* + * QUEUE_EN (RW) + * + * preemption queue enable control + */ +#define ADC16_CONFIG_QUEUE_EN_MASK (0x40U) +#define ADC16_CONFIG_QUEUE_EN_SHIFT (6U) +#define ADC16_CONFIG_QUEUE_EN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_QUEUE_EN_SHIFT) & ADC16_CONFIG_QUEUE_EN_MASK) +#define ADC16_CONFIG_QUEUE_EN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_QUEUE_EN_MASK) >> ADC16_CONFIG_QUEUE_EN_SHIFT) + +/* + * INTEN0 (RW) + * + * interupt enable for 1st conversion + */ +#define ADC16_CONFIG_INTEN0_MASK (0x20U) +#define ADC16_CONFIG_INTEN0_SHIFT (5U) +#define ADC16_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN0_SHIFT) & ADC16_CONFIG_INTEN0_MASK) +#define ADC16_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN0_MASK) >> ADC16_CONFIG_INTEN0_SHIFT) + +/* + * CHAN0 (RW) + * + * channel number for 1st conversion + */ +#define ADC16_CONFIG_CHAN0_MASK (0x1FU) +#define ADC16_CONFIG_CHAN0_SHIFT (0U) +#define ADC16_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN0_SHIFT) & ADC16_CONFIG_CHAN0_MASK) +#define ADC16_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN0_MASK) >> ADC16_CONFIG_CHAN0_SHIFT) + +/* Bitfield definition for register: TRG_DMA_ADDR */ +/* + * TRG_DMA_ADDR (RW) + * + * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + */ +#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL) +#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U) +#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) +#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) + +/* Bitfield definition for register array: BUS_RESULT */ +/* + * VALID (RO) + * + * set after conversion finished if wait_dis is set, cleared after software read. + * The first time read with 0 will trigger one new conversion. + * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. + * the result may not realtime if software read once and wait long time to read again + */ +#define ADC16_BUS_RESULT_VALID_MASK (0x10000UL) +#define ADC16_BUS_RESULT_VALID_SHIFT (16U) +#define ADC16_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_VALID_MASK) >> ADC16_BUS_RESULT_VALID_SHIFT) + +/* + * CHAN_RESULT (RO) + * + * read this register will trigger one adc conversion. + * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result + * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + */ +#define ADC16_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU) +#define ADC16_BUS_RESULT_CHAN_RESULT_SHIFT (0U) +#define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT) + +/* Bitfield definition for register: BUF_CFG0 */ +/* + * WAIT_DIS (RW) + * + * set to disable read waiting, get result immediately but maybe not current conversion result. + */ +#define ADC16_BUF_CFG0_WAIT_DIS_MASK (0x1U) +#define ADC16_BUF_CFG0_WAIT_DIS_SHIFT (0U) +#define ADC16_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_WAIT_DIS_SHIFT) & ADC16_BUF_CFG0_WAIT_DIS_MASK) +#define ADC16_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_WAIT_DIS_MASK) >> ADC16_BUF_CFG0_WAIT_DIS_SHIFT) + +/* Bitfield definition for register: SEQ_CFG0 */ +/* + * CYCLE (RO) + * + * current dma write cycle bit + */ +#define ADC16_SEQ_CFG0_CYCLE_MASK (0x80000000UL) +#define ADC16_SEQ_CFG0_CYCLE_SHIFT (31U) +#define ADC16_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CYCLE_MASK) >> ADC16_SEQ_CFG0_CYCLE_SHIFT) + +/* + * SEQ_LEN (RW) + * + * sequence queue length, 0 for one, 0xF for 16 + */ +#define ADC16_SEQ_CFG0_SEQ_LEN_MASK (0xF00U) +#define ADC16_SEQ_CFG0_SEQ_LEN_SHIFT (8U) +#define ADC16_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) +#define ADC16_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) >> ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) + +/* + * RESTART_EN (RW) + * + * if set together with cont_en, HW will continue process the whole queue after trigger once. + * If cont_en is 0, this bit is not used + */ +#define ADC16_SEQ_CFG0_RESTART_EN_MASK (0x10U) +#define ADC16_SEQ_CFG0_RESTART_EN_SHIFT (4U) +#define ADC16_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_RESTART_EN_SHIFT) & ADC16_SEQ_CFG0_RESTART_EN_MASK) +#define ADC16_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_RESTART_EN_MASK) >> ADC16_SEQ_CFG0_RESTART_EN_SHIFT) + +/* + * CONT_EN (RW) + * + * if set, HW will continue process the queue till end(seq_len) after trigger once + */ +#define ADC16_SEQ_CFG0_CONT_EN_MASK (0x8U) +#define ADC16_SEQ_CFG0_CONT_EN_SHIFT (3U) +#define ADC16_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_CONT_EN_SHIFT) & ADC16_SEQ_CFG0_CONT_EN_MASK) +#define ADC16_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CONT_EN_MASK) >> ADC16_SEQ_CFG0_CONT_EN_SHIFT) + +/* + * SW_TRIG (WO) + * + * SW trigger, pulse signal, cleared by HW one cycle later + */ +#define ADC16_SEQ_CFG0_SW_TRIG_MASK (0x4U) +#define ADC16_SEQ_CFG0_SW_TRIG_SHIFT (2U) +#define ADC16_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_MASK) +#define ADC16_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_SHIFT) + +/* + * SW_TRIG_EN (RW) + * + * set to enable SW trigger + */ +#define ADC16_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U) +#define ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U) +#define ADC16_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) +#define ADC16_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) + +/* + * HW_TRIG_EN (RW) + * + * set to enable external HW trigger, only trigger on posedge + */ +#define ADC16_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U) +#define ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U) +#define ADC16_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) +#define ADC16_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) + +/* Bitfield definition for register: SEQ_DMA_ADDR */ +/* + * TAR_ADDR (RW) + * + * dma target address, should be 4-byte aligned + */ +#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL) +#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U) +#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) +#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) + +/* Bitfield definition for register: SEQ_WR_ADDR */ +/* + * SEQ_WR_POINTER (RO) + * + * HW update this field after each dma write, it indicate the next dma write pointer. + * dma write address is (tar_addr+seq_wr_pointer)*4 + */ +#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFU) +#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT (0U) +#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_GET(x) (((uint32_t)(x) & ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK) >> ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT) + +/* Bitfield definition for register: SEQ_DMA_CFG */ +/* + * STOP_POS (RW) + * + * if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet + */ +#define ADC16_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL) +#define ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT (16U) +#define ADC16_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) +#define ADC16_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) + +/* + * DMA_RST (RW) + * + * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. + * SW should clear all cycle bit in buffer to 0 before clear dma_rst + */ +#define ADC16_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U) +#define ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT (13U) +#define ADC16_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) +#define ADC16_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) + +/* + * STOP_EN (RW) + * + * set to stop dma if reach the stop_pos + */ +#define ADC16_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U) +#define ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT (12U) +#define ADC16_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) +#define ADC16_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) + +/* + * BUF_LEN (RW) + * + * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 + * 0 for 4byte; + * 0xFFF for 16kbyte. + */ +#define ADC16_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU) +#define ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U) +#define ADC16_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) +#define ADC16_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) + +/* Bitfield definition for register array: SEQ_QUE */ +/* + * SEQ_INT_EN (RW) + * + * interrupt enable for current conversion + */ +#define ADC16_SEQ_QUE_SEQ_INT_EN_MASK (0x20U) +#define ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT (5U) +#define ADC16_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) +#define ADC16_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) + +/* + * CHAN_NUM_4_0 (RW) + * + * channel number for current conversion + */ +#define ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU) +#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U) +#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) +#define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) + +/* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ +/* + * PRESCALE (RW) + * + * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + */ +#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U) +#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U) +#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) +#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) + +/* + * PRD (RW) + * + * conver period, with prescale. + * Set to 0 means disable current channel + */ +#define ADC16_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU) +#define ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT (0U) +#define ADC16_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) +#define ADC16_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) + +/* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */ +/* + * THSHDH (RW) + * + * threshold high, assert interrupt(if enabled) if result exceed high or low. + */ +#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) +#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) +#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) +#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) + +/* + * THSHDL (RW) + * + * threshold low + */ +#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) +#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) +#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) +#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) + +/* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */ +/* + * CHAN_RESULT (RO) + * + * adc convert result, update after each valid conversion. + * it may be updated period according to config, also may be updated due to other queue convert the same channel + */ +#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU) +#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U) +#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) + +/* Bitfield definition for register array: SAMPLE_CFG */ +/* + * SAMPLE_CLOCK_NUMBER_SHIFT (RW) + * + * shift for sample clock number + */ +#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U) +#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U) +#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) +#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) + +/* + * SAMPLE_CLOCK_NUMBER (RW) + * + * sample clock number, base on clock_period, default one period + */ +#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU) +#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U) +#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) +#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) + +/* Bitfield definition for register: CONV_CFG1 */ +/* + * CONVERT_CLOCK_NUMBER (RW) + * + * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); + * user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. + * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). + */ +#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U) +#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U) +#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) +#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) + +/* + * CLOCK_DIVIDER (RW) + * + * clock_period, N half clock cycle per half adc cycle + * 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. + * set to 3 can genenerate 50MHz adc_clk at 200MHz bus_clk. + */ +#define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) +#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) +#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) +#define ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) + +/* Bitfield definition for register: ADC_CFG0 */ +/* + * SEL_SYNC_AHB (RW) + * + * set to 1 will enable sync AHB bus, to get better bus performance. + * Adc_clk must to be set to same as bus clock at this mode + */ +#define ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL) +#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U) +#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) +#define ADC16_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) + +/* + * ADC_AHB_EN (RW) + * + * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + */ +#define ADC16_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL) +#define ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT (29U) +#define ADC16_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) +#define ADC16_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) + +/* + * CONVERT_DURATION (RW) + * + * for trigger queue, from trg_sample_req to trg_convert_req + */ +#define ADC16_ADC_CFG0_CONVERT_DURATION_MASK (0xFFFF000UL) +#define ADC16_ADC_CFG0_CONVERT_DURATION_SHIFT (12U) +#define ADC16_ADC_CFG0_CONVERT_DURATION_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_CONVERT_DURATION_SHIFT) & ADC16_ADC_CFG0_CONVERT_DURATION_MASK) +#define ADC16_ADC_CFG0_CONVERT_DURATION_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_CONVERT_DURATION_MASK) >> ADC16_ADC_CFG0_CONVERT_DURATION_SHIFT) + +/* + * PORT3_REALTIME (RW) + * + * set to enable trg queue stop other queues + */ +#define ADC16_ADC_CFG0_PORT3_REALTIME_MASK (0x1U) +#define ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT (0U) +#define ADC16_ADC_CFG0_PORT3_REALTIME_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) +#define ADC16_ADC_CFG0_PORT3_REALTIME_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) >> ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) + +/* Bitfield definition for register: INT_STS */ +/* + * TRIG_CMPT (W1C) + * + * interrupt for one trigger conversion complete if enabled + */ +#define ADC16_INT_STS_TRIG_CMPT_MASK (0x80000000UL) +#define ADC16_INT_STS_TRIG_CMPT_SHIFT (31U) +#define ADC16_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_CMPT_SHIFT) & ADC16_INT_STS_TRIG_CMPT_MASK) +#define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT) + +/* + * TRIG_SW_CFLCT (W1C) + * + */ +#define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) +#define ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT (30U) +#define ADC16_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) +#define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) + +/* + * TRIG_HW_CFLCT (RW) + * + */ +#define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) +#define ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT (29U) +#define ADC16_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) +#define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) + +/* + * READ_CFLCT (W1C) + * + * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + */ +#define ADC16_INT_STS_READ_CFLCT_MASK (0x10000000UL) +#define ADC16_INT_STS_READ_CFLCT_SHIFT (28U) +#define ADC16_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_READ_CFLCT_SHIFT) & ADC16_INT_STS_READ_CFLCT_MASK) +#define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT) + +/* + * SEQ_SW_CFLCT (W1C) + * + * sequence queue conflict interrup, set if HW or SW trigger received during conversion + */ +#define ADC16_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL) +#define ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT (27U) +#define ADC16_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) +#define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) + +/* + * SEQ_HW_CFLCT (RW) + * + */ +#define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) +#define ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT (26U) +#define ADC16_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) +#define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) + +/* + * SEQ_DMAABT (W1C) + * + * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + */ +#define ADC16_INT_STS_SEQ_DMAABT_MASK (0x2000000UL) +#define ADC16_INT_STS_SEQ_DMAABT_SHIFT (25U) +#define ADC16_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_DMAABT_SHIFT) & ADC16_INT_STS_SEQ_DMAABT_MASK) +#define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT) + +/* + * SEQ_CMPT (W1C) + * + * the whole sequence complete interrupt + */ +#define ADC16_INT_STS_SEQ_CMPT_MASK (0x1000000UL) +#define ADC16_INT_STS_SEQ_CMPT_SHIFT (24U) +#define ADC16_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CMPT_SHIFT) & ADC16_INT_STS_SEQ_CMPT_MASK) +#define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT) + +/* + * SEQ_CVC (W1C) + * + * one conversion complete in seq_queue if related seq_int_en is set + */ +#define ADC16_INT_STS_SEQ_CVC_MASK (0x800000UL) +#define ADC16_INT_STS_SEQ_CVC_SHIFT (23U) +#define ADC16_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CVC_SHIFT) & ADC16_INT_STS_SEQ_CVC_MASK) +#define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT) + +/* + * DMA_FIFO_FULL (RW) + * + * DMA fifo full interrupt, user need to check clock frequency if it's set. + */ +#define ADC16_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) +#define ADC16_INT_STS_DMA_FIFO_FULL_SHIFT (22U) +#define ADC16_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) +#define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) + +/* + * AHB_ERR (RW) + * + * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + */ +#define ADC16_INT_STS_AHB_ERR_MASK (0x200000UL) +#define ADC16_INT_STS_AHB_ERR_SHIFT (21U) +#define ADC16_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_STS_AHB_ERR_SHIFT) & ADC16_INT_STS_AHB_ERR_MASK) +#define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT) + +/* + * WDOG (W1C) + * + * set if one chanel watch dog event triggered + */ +#define ADC16_INT_STS_WDOG_MASK (0x3FFFU) +#define ADC16_INT_STS_WDOG_SHIFT (0U) +#define ADC16_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_STS_WDOG_SHIFT) & ADC16_INT_STS_WDOG_MASK) +#define ADC16_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_STS_WDOG_MASK) >> ADC16_INT_STS_WDOG_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * TRIG_CMPT (W1C) + * + * interrupt for one trigger conversion complete if enabled + */ +#define ADC16_INT_EN_TRIG_CMPT_MASK (0x80000000UL) +#define ADC16_INT_EN_TRIG_CMPT_SHIFT (31U) +#define ADC16_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_CMPT_SHIFT) & ADC16_INT_EN_TRIG_CMPT_MASK) +#define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT) + +/* + * TRIG_SW_CFLCT (W1C) + * + */ +#define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) +#define ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT (30U) +#define ADC16_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) +#define ADC16_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) + +/* + * TRIG_HW_CFLCT (RW) + * + */ +#define ADC16_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL) +#define ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT (29U) +#define ADC16_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) +#define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) + +/* + * READ_CFLCT (W1C) + * + * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + */ +#define ADC16_INT_EN_READ_CFLCT_MASK (0x10000000UL) +#define ADC16_INT_EN_READ_CFLCT_SHIFT (28U) +#define ADC16_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_READ_CFLCT_SHIFT) & ADC16_INT_EN_READ_CFLCT_MASK) +#define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT) + +/* + * SEQ_SW_CFLCT (W1C) + * + * sequence queue conflict interrup, set if HW or SW trigger received during conversion + */ +#define ADC16_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL) +#define ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT (27U) +#define ADC16_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) +#define ADC16_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) + +/* + * SEQ_HW_CFLCT (RW) + * + */ +#define ADC16_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL) +#define ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT (26U) +#define ADC16_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) +#define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) + +/* + * SEQ_DMAABT (W1C) + * + * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + */ +#define ADC16_INT_EN_SEQ_DMAABT_MASK (0x2000000UL) +#define ADC16_INT_EN_SEQ_DMAABT_SHIFT (25U) +#define ADC16_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_DMAABT_SHIFT) & ADC16_INT_EN_SEQ_DMAABT_MASK) +#define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT) + +/* + * SEQ_CMPT (W1C) + * + * the whole sequence complete interrupt + */ +#define ADC16_INT_EN_SEQ_CMPT_MASK (0x1000000UL) +#define ADC16_INT_EN_SEQ_CMPT_SHIFT (24U) +#define ADC16_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CMPT_SHIFT) & ADC16_INT_EN_SEQ_CMPT_MASK) +#define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT) + +/* + * SEQ_CVC (W1C) + * + * one conversion complete in seq_queue if related seq_int_en is set + */ +#define ADC16_INT_EN_SEQ_CVC_MASK (0x800000UL) +#define ADC16_INT_EN_SEQ_CVC_SHIFT (23U) +#define ADC16_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CVC_SHIFT) & ADC16_INT_EN_SEQ_CVC_MASK) +#define ADC16_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CVC_MASK) >> ADC16_INT_EN_SEQ_CVC_SHIFT) + +/* + * DMA_FIFO_FULL (RW) + * + * DMA fifo full interrupt, user need to check clock frequency if it's set. + */ +#define ADC16_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL) +#define ADC16_INT_EN_DMA_FIFO_FULL_SHIFT (22U) +#define ADC16_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) +#define ADC16_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) >> ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) + +/* + * AHB_ERR (RW) + * + * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + */ +#define ADC16_INT_EN_AHB_ERR_MASK (0x200000UL) +#define ADC16_INT_EN_AHB_ERR_SHIFT (21U) +#define ADC16_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_EN_AHB_ERR_SHIFT) & ADC16_INT_EN_AHB_ERR_MASK) +#define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT) + +/* + * WDOG (W1C) + * + * set if one chanel watch dog event triggered + */ +#define ADC16_INT_EN_WDOG_MASK (0x3FFFU) +#define ADC16_INT_EN_WDOG_SHIFT (0U) +#define ADC16_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_EN_WDOG_SHIFT) & ADC16_INT_EN_WDOG_MASK) +#define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT) + +/* Bitfield definition for register: ANA_CTRL0 */ +/* + * ADC_CLK_ON (RW) + * + * set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. + * MUST set clock_period to 0 or 1 for adc16 reg access + */ +#define ADC16_ANA_CTRL0_ADC_CLK_ON_MASK (0x1000U) +#define ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT (12U) +#define ADC16_ANA_CTRL0_ADC_CLK_ON_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) +#define ADC16_ANA_CTRL0_ADC_CLK_ON_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) >> ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) + +/* + * STARTCAL (RW) + * + * set to start the offset calibration cycle (Active H). user need to clear it after setting it. + */ +#define ADC16_ANA_CTRL0_STARTCAL_MASK (0x4U) +#define ADC16_ANA_CTRL0_STARTCAL_SHIFT (2U) +#define ADC16_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_STARTCAL_SHIFT) & ADC16_ANA_CTRL0_STARTCAL_MASK) +#define ADC16_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_STARTCAL_MASK) >> ADC16_ANA_CTRL0_STARTCAL_SHIFT) + +/* Bitfield definition for register: ANA_STATUS */ +/* + * CALON (RW) + * + * Indicates if the ADC is in calibration mode (Active H). + */ +#define ADC16_ANA_STATUS_CALON_MASK (0x80U) +#define ADC16_ANA_STATUS_CALON_SHIFT (7U) +#define ADC16_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC16_ANA_STATUS_CALON_SHIFT) & ADC16_ANA_STATUS_CALON_MASK) +#define ADC16_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC16_ANA_STATUS_CALON_MASK) >> ADC16_ANA_STATUS_CALON_SHIFT) + +/* Bitfield definition for register array: ADC16_PARAMS */ +/* + * PARAM_VAL (RW) + * + */ +#define ADC16_ADC16_PARAMS_PARAM_VAL_MASK (0xFFFFU) +#define ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT (0U) +#define ADC16_ADC16_PARAMS_PARAM_VAL_SET(x) (((uint16_t)(x) << ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) +#define ADC16_ADC16_PARAMS_PARAM_VAL_GET(x) (((uint16_t)(x) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) >> ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) + +/* Bitfield definition for register: ADC16_CONFIG0 */ +/* + * TEMPSNS_EN (RW) + * + * set to enable temp senser + */ +#define ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK (0x2000000UL) +#define ADC16_ADC16_CONFIG0_TEMPSNS_EN_SHIFT (25U) +#define ADC16_ADC16_CONFIG0_TEMPSNS_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_TEMPSNS_EN_SHIFT) & ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK) +#define ADC16_ADC16_CONFIG0_TEMPSNS_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK) >> ADC16_ADC16_CONFIG0_TEMPSNS_EN_SHIFT) + +/* + * REG_EN (RW) + * + * set to enable regulator + */ +#define ADC16_ADC16_CONFIG0_REG_EN_MASK (0x1000000UL) +#define ADC16_ADC16_CONFIG0_REG_EN_SHIFT (24U) +#define ADC16_ADC16_CONFIG0_REG_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_REG_EN_SHIFT) & ADC16_ADC16_CONFIG0_REG_EN_MASK) +#define ADC16_ADC16_CONFIG0_REG_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_REG_EN_MASK) >> ADC16_ADC16_CONFIG0_REG_EN_SHIFT) + +/* + * BANDGAP_EN (RW) + * + * set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + */ +#define ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK (0x800000UL) +#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT (23U) +#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) +#define ADC16_ADC16_CONFIG0_BANDGAP_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) >> ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) + +/* + * CAL_AVG_CFG (RW) + * + * for average the calibration result. + * 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; + * 4- 16 loops; 5-32 loops; others reserved + */ +#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK (0x700000UL) +#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT (20U) +#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) +#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) >> ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) + +/* + * PREEMPT_EN (RW) + * + * set to enable preemption feature + */ +#define ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK (0x4000U) +#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT (14U) +#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) +#define ADC16_ADC16_CONFIG0_PREEMPT_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) >> ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) + +/* + * CONV_PARAM (RW) + * + * convertion parameter + */ +#define ADC16_ADC16_CONFIG0_CONV_PARAM_MASK (0x3FFFU) +#define ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT (0U) +#define ADC16_ADC16_CONFIG0_CONV_PARAM_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) +#define ADC16_ADC16_CONFIG0_CONV_PARAM_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) >> ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) + +/* Bitfield definition for register: ADC16_CONFIG1 */ +/* + * COV_END_CNT (RW) + * + * used for faster conversion, user can change it to get higher convert speed(but less accuracy). + * should set to (21-convert_clock_number). + */ +#define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U) +#define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U) +#define ADC16_ADC16_CONFIG1_COV_END_CNT_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) +#define ADC16_ADC16_CONFIG1_COV_END_CNT_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) >> ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) + + + +/* CONFIG register group index macro definition */ +#define ADC16_CONFIG_TRG0A (0UL) +#define ADC16_CONFIG_TRG0B (1UL) +#define ADC16_CONFIG_TRG0C (2UL) +#define ADC16_CONFIG_TRG1A (3UL) +#define ADC16_CONFIG_TRG1B (4UL) +#define ADC16_CONFIG_TRG1C (5UL) +#define ADC16_CONFIG_TRG2A (6UL) +#define ADC16_CONFIG_TRG2B (7UL) +#define ADC16_CONFIG_TRG2C (8UL) +#define ADC16_CONFIG_TRG3A (9UL) +#define ADC16_CONFIG_TRG3B (10UL) +#define ADC16_CONFIG_TRG3C (11UL) + +/* BUS_RESULT register group index macro definition */ +#define ADC16_BUS_RESULT_CHN0 (0UL) +#define ADC16_BUS_RESULT_CHN1 (1UL) +#define ADC16_BUS_RESULT_CHN2 (2UL) +#define ADC16_BUS_RESULT_CHN3 (3UL) +#define ADC16_BUS_RESULT_CHN4 (4UL) +#define ADC16_BUS_RESULT_CHN5 (5UL) +#define ADC16_BUS_RESULT_CHN6 (6UL) +#define ADC16_BUS_RESULT_CHN7 (7UL) +#define ADC16_BUS_RESULT_CHN8 (8UL) +#define ADC16_BUS_RESULT_CHN9 (9UL) +#define ADC16_BUS_RESULT_CHN10 (10UL) +#define ADC16_BUS_RESULT_CHN11 (11UL) +#define ADC16_BUS_RESULT_CHN12 (12UL) +#define ADC16_BUS_RESULT_CHN13 (13UL) +#define ADC16_BUS_RESULT_CHN14 (14UL) +#define ADC16_BUS_RESULT_CHN15 (15UL) + +/* SEQ_QUE register group index macro definition */ +#define ADC16_SEQ_QUE_CFG0 (0UL) +#define ADC16_SEQ_QUE_CFG1 (1UL) +#define ADC16_SEQ_QUE_CFG2 (2UL) +#define ADC16_SEQ_QUE_CFG3 (3UL) +#define ADC16_SEQ_QUE_CFG4 (4UL) +#define ADC16_SEQ_QUE_CFG5 (5UL) +#define ADC16_SEQ_QUE_CFG6 (6UL) +#define ADC16_SEQ_QUE_CFG7 (7UL) +#define ADC16_SEQ_QUE_CFG8 (8UL) +#define ADC16_SEQ_QUE_CFG9 (9UL) +#define ADC16_SEQ_QUE_CFG10 (10UL) +#define ADC16_SEQ_QUE_CFG11 (11UL) +#define ADC16_SEQ_QUE_CFG12 (12UL) +#define ADC16_SEQ_QUE_CFG13 (13UL) +#define ADC16_SEQ_QUE_CFG14 (14UL) +#define ADC16_SEQ_QUE_CFG15 (15UL) + +/* PRD_CFG register group index macro definition */ +#define ADC16_PRD_CFG_CHN0 (0UL) +#define ADC16_PRD_CFG_CHN1 (1UL) +#define ADC16_PRD_CFG_CHN2 (2UL) +#define ADC16_PRD_CFG_CHN3 (3UL) +#define ADC16_PRD_CFG_CHN4 (4UL) +#define ADC16_PRD_CFG_CHN5 (5UL) +#define ADC16_PRD_CFG_CHN6 (6UL) +#define ADC16_PRD_CFG_CHN7 (7UL) +#define ADC16_PRD_CFG_CHN8 (8UL) +#define ADC16_PRD_CFG_CHN9 (9UL) +#define ADC16_PRD_CFG_CHN10 (10UL) +#define ADC16_PRD_CFG_CHN11 (11UL) +#define ADC16_PRD_CFG_CHN12 (12UL) +#define ADC16_PRD_CFG_CHN13 (13UL) +#define ADC16_PRD_CFG_CHN14 (14UL) +#define ADC16_PRD_CFG_CHN15 (15UL) + +/* SAMPLE_CFG register group index macro definition */ +#define ADC16_SAMPLE_CFG_CHN0 (0UL) +#define ADC16_SAMPLE_CFG_CHN1 (1UL) +#define ADC16_SAMPLE_CFG_CHN2 (2UL) +#define ADC16_SAMPLE_CFG_CHN3 (3UL) +#define ADC16_SAMPLE_CFG_CHN4 (4UL) +#define ADC16_SAMPLE_CFG_CHN5 (5UL) +#define ADC16_SAMPLE_CFG_CHN6 (6UL) +#define ADC16_SAMPLE_CFG_CHN7 (7UL) +#define ADC16_SAMPLE_CFG_CHN8 (8UL) +#define ADC16_SAMPLE_CFG_CHN9 (9UL) +#define ADC16_SAMPLE_CFG_CHN10 (10UL) +#define ADC16_SAMPLE_CFG_CHN11 (11UL) +#define ADC16_SAMPLE_CFG_CHN12 (12UL) +#define ADC16_SAMPLE_CFG_CHN13 (13UL) +#define ADC16_SAMPLE_CFG_CHN14 (14UL) +#define ADC16_SAMPLE_CFG_CHN15 (15UL) + +/* ADC16_PARAMS register group index macro definition */ +#define ADC16_ADC16_PARAMS_ADC16_PARA00 (0UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA01 (1UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA02 (2UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA03 (3UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA04 (4UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA05 (5UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA06 (6UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA07 (7UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA08 (8UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA09 (9UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA10 (10UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA11 (11UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA12 (12UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA13 (13UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA14 (14UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA15 (15UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA16 (16UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA17 (17UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA18 (18UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA19 (19UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA20 (20UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA21 (21UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA22 (22UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA23 (23UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA24 (24UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA25 (25UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA26 (26UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA27 (27UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA28 (28UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA29 (29UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA30 (30UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA31 (31UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA32 (32UL) +#define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL) + + +#endif /* HPM_ADC16_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bacc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bacc_regs.h new file mode 100644 index 0000000000..e9ee8e040f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bacc_regs.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BACC_H +#define HPM_BACC_H + +typedef struct { + __RW uint32_t CONFIG; /* 0x0: Access timing for access */ + __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ + __RW uint32_t PRE_TIME; /* 0x8: Timing gap before rising edge */ + __RW uint32_t POST_TIME; /* 0xC: Timing gap after rising edge */ +} BACC_Type; + + +/* Bitfield definition for register: CONFIG */ +/* + * FAST_WRITE (RW) + * + * Use fast write + * 0: Write normally + * 1: boost write + */ +#define BACC_CONFIG_FAST_WRITE_MASK (0x20000000UL) +#define BACC_CONFIG_FAST_WRITE_SHIFT (29U) +#define BACC_CONFIG_FAST_WRITE_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_WRITE_SHIFT) & BACC_CONFIG_FAST_WRITE_MASK) +#define BACC_CONFIG_FAST_WRITE_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_WRITE_MASK) >> BACC_CONFIG_FAST_WRITE_SHIFT) + +/* + * FAST_READ (RW) + * + * Use fast read + * 0: Read normally + * 1: boost read + */ +#define BACC_CONFIG_FAST_READ_MASK (0x10000000UL) +#define BACC_CONFIG_FAST_READ_SHIFT (28U) +#define BACC_CONFIG_FAST_READ_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_READ_SHIFT) & BACC_CONFIG_FAST_READ_MASK) +#define BACC_CONFIG_FAST_READ_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_READ_MASK) >> BACC_CONFIG_FAST_READ_SHIFT) + +/* + * TIMING (RW) + * + * Time in APB clock cycles, for battery timing penerate + */ +#define BACC_CONFIG_TIMING_MASK (0xFFFFU) +#define BACC_CONFIG_TIMING_SHIFT (0U) +#define BACC_CONFIG_TIMING_SET(x) (((uint32_t)(x) << BACC_CONFIG_TIMING_SHIFT) & BACC_CONFIG_TIMING_MASK) +#define BACC_CONFIG_TIMING_GET(x) (((uint32_t)(x) & BACC_CONFIG_TIMING_MASK) >> BACC_CONFIG_TIMING_SHIFT) + +/* Bitfield definition for register: PRE_TIME */ +/* + * PRE_RATIO (RW) + * + * Ratio of guard band before rising edge + * 0: 0 + * 1: 1/32768 of low level width + * 2: 1/16384 of low level width + * 14: 1/4 of low level width + * 15: 1/2 of low level width + */ +#define BACC_PRE_TIME_PRE_RATIO_MASK (0xF0000UL) +#define BACC_PRE_TIME_PRE_RATIO_SHIFT (16U) +#define BACC_PRE_TIME_PRE_RATIO_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_RATIO_SHIFT) & BACC_PRE_TIME_PRE_RATIO_MASK) +#define BACC_PRE_TIME_PRE_RATIO_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_RATIO_MASK) >> BACC_PRE_TIME_PRE_RATIO_SHIFT) + +/* + * PRE_OFFSET (RW) + * + * guard band before rising edge + * this value will be added to ratio number + */ +#define BACC_PRE_TIME_PRE_OFFSET_MASK (0xFFFFU) +#define BACC_PRE_TIME_PRE_OFFSET_SHIFT (0U) +#define BACC_PRE_TIME_PRE_OFFSET_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_OFFSET_SHIFT) & BACC_PRE_TIME_PRE_OFFSET_MASK) +#define BACC_PRE_TIME_PRE_OFFSET_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_OFFSET_MASK) >> BACC_PRE_TIME_PRE_OFFSET_SHIFT) + +/* Bitfield definition for register: POST_TIME */ +/* + * POST_RATIO (RW) + * + * Ratio of guard band after rising edge + * 0: 0 + * 1: 1/32768 of high level width + * 2: 1/16384 of high level width + * 14: 1/4 of high level width + * 15: 1/2 of high level width + */ +#define BACC_POST_TIME_POST_RATIO_MASK (0xF0000UL) +#define BACC_POST_TIME_POST_RATIO_SHIFT (16U) +#define BACC_POST_TIME_POST_RATIO_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_RATIO_SHIFT) & BACC_POST_TIME_POST_RATIO_MASK) +#define BACC_POST_TIME_POST_RATIO_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_RATIO_MASK) >> BACC_POST_TIME_POST_RATIO_SHIFT) + +/* + * POST_OFFSET (RW) + * + * guard band after rising edge + * this value will be added to ratio number + */ +#define BACC_POST_TIME_POST_OFFSET_MASK (0xFFFFU) +#define BACC_POST_TIME_POST_OFFSET_SHIFT (0U) +#define BACC_POST_TIME_POST_OFFSET_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_OFFSET_SHIFT) & BACC_POST_TIME_POST_OFFSET_MASK) +#define BACC_POST_TIME_POST_OFFSET_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_OFFSET_MASK) >> BACC_POST_TIME_POST_OFFSET_SHIFT) + + + + +#endif /* HPM_BACC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h new file mode 100644 index 0000000000..69b89729ec --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BCFG_H +#define HPM_BCFG_H + +typedef struct { + __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ + __RW uint32_t LDO_CFG; /* 0x4: LDO config */ + __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ + __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ + __RW uint32_t CLK_CFG; /* 0x10: Clock config */ +} BCFG_Type; + + +/* Bitfield definition for register: VBG_CFG */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) +#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) +#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) +#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) + +/* + * LP_MODE (RW) + * + * Bandgap works in low power mode + * 0: not in low power mode + * 1: bandgap work in low power mode + */ +#define BCFG_VBG_CFG_LP_MODE_MASK (0x2000000UL) +#define BCFG_VBG_CFG_LP_MODE_SHIFT (25U) +#define BCFG_VBG_CFG_LP_MODE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK) +#define BCFG_VBG_CFG_LP_MODE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Bandgap works in power save mode + * 0: not in power save mode + * 1: bandgap work in power save mode + */ +#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) +#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) +#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) +#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) + +/* + * VBG_1P0 (RW) + * + * Bandgap 1.0V output trim + */ +#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) +#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) +#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) +#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) + +/* + * VBG_P65 (RW) + * + * Bandgap 0.65V output trim + */ +#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) +#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) +#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) +#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) + +/* + * VBG_P50 (RW) + * + * Bandgap 0.50V output trim + */ +#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) +#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) +#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) +#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) + +/* Bitfield definition for register: LDO_CFG */ +/* + * RES_TRIM (RW) + * + * Resistor trim + */ +#define BCFG_LDO_CFG_RES_TRIM_MASK (0x3000000UL) +#define BCFG_LDO_CFG_RES_TRIM_SHIFT (24U) +#define BCFG_LDO_CFG_RES_TRIM_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_RES_TRIM_SHIFT) & BCFG_LDO_CFG_RES_TRIM_MASK) +#define BCFG_LDO_CFG_RES_TRIM_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_RES_TRIM_MASK) >> BCFG_LDO_CFG_RES_TRIM_SHIFT) + +/* + * CP_TRIM (RW) + * + * Capacitor trim + */ +#define BCFG_LDO_CFG_CP_TRIM_MASK (0x300000UL) +#define BCFG_LDO_CFG_CP_TRIM_SHIFT (20U) +#define BCFG_LDO_CFG_CP_TRIM_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_CP_TRIM_SHIFT) & BCFG_LDO_CFG_CP_TRIM_MASK) +#define BCFG_LDO_CFG_CP_TRIM_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_CP_TRIM_MASK) >> BCFG_LDO_CFG_CP_TRIM_SHIFT) + +/* + * EN_SL (RW) + * + * enable selfload, this bit helps improve LDO performance when current less than 200nA + * 0: self load disabled + * 1: selfload enabled + */ +#define BCFG_LDO_CFG_EN_SL_MASK (0x40000UL) +#define BCFG_LDO_CFG_EN_SL_SHIFT (18U) +#define BCFG_LDO_CFG_EN_SL_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_EN_SL_SHIFT) & BCFG_LDO_CFG_EN_SL_MASK) +#define BCFG_LDO_CFG_EN_SL_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_EN_SL_MASK) >> BCFG_LDO_CFG_EN_SL_SHIFT) + +/* + * DIS_PD (RW) + * + * disable pull down resistor, enable pull down may lead to more power but better response + * 0: pulldown resistor enabled + * 1: pulldown resistor disabled + */ +#define BCFG_LDO_CFG_DIS_PD_MASK (0x20000UL) +#define BCFG_LDO_CFG_DIS_PD_SHIFT (17U) +#define BCFG_LDO_CFG_DIS_PD_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_DIS_PD_SHIFT) & BCFG_LDO_CFG_DIS_PD_MASK) +#define BCFG_LDO_CFG_DIS_PD_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_DIS_PD_MASK) >> BCFG_LDO_CFG_DIS_PD_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: LDO is disabled + * 1: LDO is enabled + */ +#define BCFG_LDO_CFG_ENABLE_MASK (0x10000UL) +#define BCFG_LDO_CFG_ENABLE_SHIFT (16U) +#define BCFG_LDO_CFG_ENABLE_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_ENABLE_SHIFT) & BCFG_LDO_CFG_ENABLE_MASK) +#define BCFG_LDO_CFG_ENABLE_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_ENABLE_MASK) >> BCFG_LDO_CFG_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO voltage setting in mV, valid range through 600mV to 1100mV, step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1100mV. + * 600: 600mV + * 620: 620mV + * . . . + * 1100:1100mV + */ +#define BCFG_LDO_CFG_VOLT_MASK (0xFFFU) +#define BCFG_LDO_CFG_VOLT_SHIFT (0U) +#define BCFG_LDO_CFG_VOLT_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_VOLT_SHIFT) & BCFG_LDO_CFG_VOLT_MASK) +#define BCFG_LDO_CFG_VOLT_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_VOLT_MASK) >> BCFG_LDO_CFG_VOLT_SHIFT) + +/* Bitfield definition for register: IRC32K_CFG */ +/* + * IRC_TRIMMED (RW) + * + * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: irc is not trimmed + * 1: irc is trimmed + */ +#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) + +/* + * CAPEX7_TRIM (RW) + * + * IRC32K bit 7 + */ +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) + +/* + * CAPEX6_TRIM (RW) + * + * IRC32K bit 6 + */ +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) + +/* + * CAP_TRIM (RW) + * + * capacitor trim bits + */ +#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) +#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) +#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) + +/* Bitfield definition for register: XTAL32K_CFG */ +/* + * HYST_EN (RW) + * + * crystal 32k hysteres enable + */ +#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) +#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) +#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) +#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) + +/* + * GMSEL (RW) + * + * crystal 32k gm selection + */ +#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) +#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) +#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) +#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) + +/* + * CFG (RW) + * + * crystal 32k config + */ +#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) +#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) +#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) +#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) + +/* + * AMP (RW) + * + * crystal 32k amplifier + */ +#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) +#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) +#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) +#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) + +/* Bitfield definition for register: CLK_CFG */ +/* + * XTAL_SEL (RO) + * + * crystal selected + */ +#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) +#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) +#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) + +/* + * KEEP_IRC (RW) + * + * force irc32k run + */ +#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) +#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) +#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) +#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) + +/* + * FORCE_XTAL (RW) + * + * force switch to crystal + */ +#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) +#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) +#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) +#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) + + + + +#endif /* HPM_BCFG_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h new file mode 100644 index 0000000000..613c35e96e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BGPR_H +#define HPM_BGPR_H + +typedef struct { + __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ + __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ + __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ + __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ + __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ + __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ + __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ + __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ +} BGPR_Type; + + +/* Bitfield definition for register: BATT_GPR0 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR0_GPR_SHIFT (0U) +#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) +#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR1 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR1_GPR_SHIFT (0U) +#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) +#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR2 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR2_GPR_SHIFT (0U) +#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) +#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR3 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR3_GPR_SHIFT (0U) +#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) +#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR4 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR4_GPR_SHIFT (0U) +#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) +#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR5 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR5_GPR_SHIFT (0U) +#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) +#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR6 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR6_GPR_SHIFT (0U) +#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) +#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR7 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR7_GPR_SHIFT (0U) +#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) +#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) + + + + +#endif /* HPM_BGPR_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bkey_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bkey_regs.h new file mode 100644 index 0000000000..1a2fa3b072 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bkey_regs.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BKEY_H +#define HPM_BKEY_H + +typedef struct { + struct { + __RW uint32_t DATA[8]; /* 0x0 - 0x1C: Key data */ + } KEY[2]; + __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ + __RW uint32_t SELECT; /* 0x48: Key selection */ +} BKEY_Type; + + +/* Bitfield definition for register of struct array KEY: 0 */ +/* + * DATA (RW) + * + * security key data + */ +#define BKEY_DATA_DATA_MASK (0xFFFFFFFFUL) +#define BKEY_DATA_DATA_SHIFT (0U) +#define BKEY_DATA_DATA_SET(x) (((uint32_t)(x) << BKEY_DATA_DATA_SHIFT) & BKEY_DATA_DATA_MASK) +#define BKEY_DATA_DATA_GET(x) (((uint32_t)(x) & BKEY_DATA_DATA_MASK) >> BKEY_DATA_DATA_SHIFT) + +/* Bitfield definition for register array: ECC */ +/* + * WLOCK (RW) + * + * write lock to key0 + * 0: write enable + * 1: write ignored + */ +#define BKEY_ECC_WLOCK_MASK (0x80000000UL) +#define BKEY_ECC_WLOCK_SHIFT (31U) +#define BKEY_ECC_WLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_WLOCK_SHIFT) & BKEY_ECC_WLOCK_MASK) +#define BKEY_ECC_WLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_WLOCK_MASK) >> BKEY_ECC_WLOCK_SHIFT) + +/* + * RLOCK (RW) + * + * read lock to key0 + * 0: key read enable + * 1: key always read as 0 + */ +#define BKEY_ECC_RLOCK_MASK (0x40000000UL) +#define BKEY_ECC_RLOCK_SHIFT (30U) +#define BKEY_ECC_RLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_RLOCK_SHIFT) & BKEY_ECC_RLOCK_MASK) +#define BKEY_ECC_RLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_RLOCK_MASK) >> BKEY_ECC_RLOCK_SHIFT) + +/* + * ECC (RW) + * + * Parity check bits for key0 + */ +#define BKEY_ECC_ECC_MASK (0xFFFFU) +#define BKEY_ECC_ECC_SHIFT (0U) +#define BKEY_ECC_ECC_SET(x) (((uint32_t)(x) << BKEY_ECC_ECC_SHIFT) & BKEY_ECC_ECC_MASK) +#define BKEY_ECC_ECC_GET(x) (((uint32_t)(x) & BKEY_ECC_ECC_MASK) >> BKEY_ECC_ECC_SHIFT) + +/* Bitfield definition for register: SELECT */ +/* + * SELECT (RW) + * + * select key, key0 treated as secure key, in non-scure mode, only key1 can be selected + * 0: select key0 in secure mode, key1 in non-secure mode + * 1: select key1 in secure or nonsecure mode + */ +#define BKEY_SELECT_SELECT_MASK (0x1U) +#define BKEY_SELECT_SELECT_SHIFT (0U) +#define BKEY_SELECT_SELECT_SET(x) (((uint32_t)(x) << BKEY_SELECT_SELECT_SHIFT) & BKEY_SELECT_SELECT_MASK) +#define BKEY_SELECT_SELECT_GET(x) (((uint32_t)(x) & BKEY_SELECT_SELECT_MASK) >> BKEY_SELECT_SELECT_SHIFT) + + + +/* DATA register group index macro definition */ +#define BKEY_KEY_DATA_0 (0UL) +#define BKEY_KEY_DATA_1 (1UL) +#define BKEY_KEY_DATA_2 (2UL) +#define BKEY_KEY_DATA_3 (3UL) +#define BKEY_KEY_DATA_4 (4UL) +#define BKEY_KEY_DATA_5 (5UL) +#define BKEY_KEY_DATA_6 (6UL) +#define BKEY_KEY_DATA_7 (7UL) + +/* KEY register group index macro definition */ +#define BKEY_KEY_0 (0UL) +#define BKEY_KEY_1 (1UL) + +/* ECC register group index macro definition */ +#define BKEY_ECC_KEY0 (0UL) +#define BKEY_ECC_KEY1 (1UL) + + +#endif /* HPM_BKEY_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bmon_regs.h new file mode 100644 index 0000000000..22df7ec6d8 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bmon_regs.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BMON_H +#define HPM_BMON_H + +typedef struct { + struct { + __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ + __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ + } MONITOR[3]; +} BMON_Type; + + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * ACTIVE (RW) + * + * select glitch works in active mode or passve mode. + * 0: passive mode, depends on power glitch destory DFF value + * 1: active mode, check glitch by DFF chain + */ +#define BMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) +#define BMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) +#define BMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ACTIVE_SHIFT) & BMON_MONITOR_CONTROL_ACTIVE_MASK) +#define BMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ACTIVE_MASK) >> BMON_MONITOR_CONTROL_ACTIVE_SHIFT) + +/* + * ENABLE (RW) + * + * enable glitch detector + * 0: detector disabled + * 1: detector enabled + */ +#define BMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) +#define BMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) +#define BMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ENABLE_SHIFT) & BMON_MONITOR_CONTROL_ENABLE_MASK) +#define BMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ENABLE_MASK) >> BMON_MONITOR_CONTROL_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: STATUS */ +/* + * FLAG (RW) + * + * flag for glitch detected, write 1 to clear this flag + * 0: glitch not detected + * 1: glitch detected + */ +#define BMON_MONITOR_STATUS_FLAG_MASK (0x1U) +#define BMON_MONITOR_STATUS_FLAG_SHIFT (0U) +#define BMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << BMON_MONITOR_STATUS_FLAG_SHIFT) & BMON_MONITOR_STATUS_FLAG_MASK) +#define BMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & BMON_MONITOR_STATUS_FLAG_MASK) >> BMON_MONITOR_STATUS_FLAG_SHIFT) + + + +/* MONITOR register group index macro definition */ +#define BMON_MONITOR_GLITCH0 (0UL) +#define BMON_MONITOR_CLOCK0 (2UL) + + +#endif /* HPM_BMON_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h new file mode 100644 index 0000000000..36daa1f041 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BPOR_H +#define HPM_BPOR_H + +typedef struct { + __RW uint32_t POR_CAUSE; /* 0x0: Power on cause */ + __RW uint32_t POR_SELECT; /* 0x4: Power on select */ + __RW uint32_t POR_CONFIG; /* 0x8: Power on reset config */ + __RW uint32_t POR_CONTROL; /* 0xC: Power down control */ +} BPOR_Type; + + +/* Bitfield definition for register: POR_CAUSE */ +/* + * CAUSE (RW) + * + * Power on cause, each bit represnts one cause, write 1 to clear each bit + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_CAUSE_CAUSE_MASK (0x1FU) +#define BPOR_POR_CAUSE_CAUSE_SHIFT (0U) +#define BPOR_POR_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << BPOR_POR_CAUSE_CAUSE_SHIFT) & BPOR_POR_CAUSE_CAUSE_MASK) +#define BPOR_POR_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & BPOR_POR_CAUSE_CAUSE_MASK) >> BPOR_POR_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: POR_SELECT */ +/* + * SELECT (RW) + * + * Power on cause select, each bit represnts one cause, value 1 enables corresponding cause + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_SELECT_SELECT_MASK (0x1FU) +#define BPOR_POR_SELECT_SELECT_SHIFT (0U) +#define BPOR_POR_SELECT_SELECT_SET(x) (((uint32_t)(x) << BPOR_POR_SELECT_SELECT_SHIFT) & BPOR_POR_SELECT_SELECT_MASK) +#define BPOR_POR_SELECT_SELECT_GET(x) (((uint32_t)(x) & BPOR_POR_SELECT_SELECT_MASK) >> BPOR_POR_SELECT_SELECT_SHIFT) + +/* Bitfield definition for register: POR_CONFIG */ +/* + * RETENTION (RW) + * + * retention battery domain setting + * 0: battery reset on reset pin reset happen + * 1: battery domain retention when reset pin reset happen + */ +#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) +#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) +#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) +#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) + +/* Bitfield definition for register: POR_CONTROL */ +/* + * COUNTER (RW) + * + * Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + */ +#define BPOR_POR_CONTROL_COUNTER_MASK (0xFFFFU) +#define BPOR_POR_CONTROL_COUNTER_SHIFT (0U) +#define BPOR_POR_CONTROL_COUNTER_SET(x) (((uint32_t)(x) << BPOR_POR_CONTROL_COUNTER_SHIFT) & BPOR_POR_CONTROL_COUNTER_MASK) +#define BPOR_POR_CONTROL_COUNTER_GET(x) (((uint32_t)(x) & BPOR_POR_CONTROL_COUNTER_MASK) >> BPOR_POR_CONTROL_COUNTER_SHIFT) + + + + +#endif /* HPM_BPOR_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bsec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bsec_regs.h new file mode 100644 index 0000000000..c7af45067b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_bsec_regs.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BSEC_H +#define HPM_BSEC_H + +typedef struct { + __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ + __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ + __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ + __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ + __R uint32_t EVENT; /* 0x10: Event and escalate status */ +} BSEC_Type; + + +/* Bitfield definition for register: SECURE_STATE */ +/* + * ALLOW_NSC (RO) + * + * Non-secure state allow + * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state + * 1: system is healthy to enter non-secure state + */ +#define BSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) +#define BSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) +#define BSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_NSC_MASK) >> BSEC_SECURE_STATE_ALLOW_NSC_SHIFT) + +/* + * ALLOW_SEC (RO) + * + * Secure state allow + * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state + * 1: system is healthy to enter secure state + */ +#define BSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) +#define BSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) +#define BSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_SEC_MASK) >> BSEC_SECURE_STATE_ALLOW_SEC_SHIFT) + +/* + * BATT_FAIL (RW) + * + * BATT secure state one hot indicator + * 0: secure state is not in fail state + * 1: secure state is in fail state + */ +#define BSEC_SECURE_STATE_BATT_FAIL_MASK (0x8U) +#define BSEC_SECURE_STATE_BATT_FAIL_SHIFT (3U) +#define BSEC_SECURE_STATE_BATT_FAIL_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_FAIL_SHIFT) & BSEC_SECURE_STATE_BATT_FAIL_MASK) +#define BSEC_SECURE_STATE_BATT_FAIL_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_FAIL_MASK) >> BSEC_SECURE_STATE_BATT_FAIL_SHIFT) + +/* + * BATT_NSC (RW) + * + * BATT secure state one hot indicator + * 0: secure state is not in non-secure state + * 1: secure state is in non-secure state + */ +#define BSEC_SECURE_STATE_BATT_NSC_MASK (0x4U) +#define BSEC_SECURE_STATE_BATT_NSC_SHIFT (2U) +#define BSEC_SECURE_STATE_BATT_NSC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_NSC_SHIFT) & BSEC_SECURE_STATE_BATT_NSC_MASK) +#define BSEC_SECURE_STATE_BATT_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_NSC_MASK) >> BSEC_SECURE_STATE_BATT_NSC_SHIFT) + +/* + * BATT_SEC (RW) + * + * BATT secure state one hot indicator + * 0: secure state is not in secure state + * 1: secure state is in secure state + */ +#define BSEC_SECURE_STATE_BATT_SEC_MASK (0x2U) +#define BSEC_SECURE_STATE_BATT_SEC_SHIFT (1U) +#define BSEC_SECURE_STATE_BATT_SEC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_SEC_SHIFT) & BSEC_SECURE_STATE_BATT_SEC_MASK) +#define BSEC_SECURE_STATE_BATT_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_SEC_MASK) >> BSEC_SECURE_STATE_BATT_SEC_SHIFT) + +/* + * BATT_INS (RW) + * + * BATT secure state one hot indicator + * 0: secure state is not in inspect state + * 1: secure state is in inspect state + */ +#define BSEC_SECURE_STATE_BATT_INS_MASK (0x1U) +#define BSEC_SECURE_STATE_BATT_INS_SHIFT (0U) +#define BSEC_SECURE_STATE_BATT_INS_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_INS_SHIFT) & BSEC_SECURE_STATE_BATT_INS_MASK) +#define BSEC_SECURE_STATE_BATT_INS_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_INS_MASK) >> BSEC_SECURE_STATE_BATT_INS_SHIFT) + +/* Bitfield definition for register: SECURE_STATE_CONFIG */ +/* + * LOCK (RW) + * + * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset + * 0: not locked, register can be modified + * 1: register locked, write access to the register is ignored + */ +#define BSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) +#define BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) +#define BSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) +#define BSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) + +/* + * ALLOW_RESTART (RW) + * + * allow secure state restart from fail state + * 0: restart is not allowed, only hardware reset can recover secure state + * 1: software is allowed to switch to inspect state from fail state + */ +#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) +#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) +#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) +#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) + +/* Bitfield definition for register: VIOLATION_CONFIG */ +/* + * LOCK_NSC (RW) + * + * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) +#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) +#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) +#define BSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) + +/* + * NSC_VIO_CFG (RW) + * + * configuration of non-secure state violations, each bit represents one security event + * 0: event is not a security violation + * 1: event is a security violation + */ +#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) +#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) +#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) +#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) + +/* + * LOCK_SEC (RW) + * + * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) +#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) +#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) +#define BSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) + +/* + * SEC_VIO_CFG (RW) + * + * configuration of secure state violations, each bit represents one security event + * 0: event is not a security violation + * 1: event is a security violation + */ +#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) +#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) +#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) +#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) + +/* Bitfield definition for register: ESCALATE_CONFIG */ +/* + * LOCK_NSC (RW) + * + * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) +#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) +#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) +#define BSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) + +/* + * NSC_VIO_CFG (RW) + * + * configuration of non-secure state escalates, each bit represents one security event + * 0: event is not a security escalate + * 1: event is a security escalate + */ +#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) +#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) +#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) +#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) + +/* + * LOCK_SEC (RW) + * + * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored + */ +#define BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) +#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) +#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) +#define BSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) + +/* + * SEC_VIO_CFG (RW) + * + * configuration of secure state escalates, each bit represents one security event + * 0: event is not a security escalate + * 1: event is a security escalate + */ +#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) +#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) +#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) +#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) + +/* Bitfield definition for register: EVENT */ +/* + * EVENT (RO) + * + * local event statue, each bit represents one security event + */ +#define BSEC_EVENT_EVENT_MASK (0xFFFF0000UL) +#define BSEC_EVENT_EVENT_SHIFT (16U) +#define BSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & BSEC_EVENT_EVENT_MASK) >> BSEC_EVENT_EVENT_SHIFT) + +/* + * BATT_ESC_NSC (RO) + * + * BATT is escalating non-secure event + */ +#define BSEC_EVENT_BATT_ESC_NSC_MASK (0x2U) +#define BSEC_EVENT_BATT_ESC_NSC_SHIFT (1U) +#define BSEC_EVENT_BATT_ESC_NSC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_NSC_MASK) >> BSEC_EVENT_BATT_ESC_NSC_SHIFT) + +/* + * BATT_ESC_SEC (RO) + * + * BATT is escalting ssecure event + */ +#define BSEC_EVENT_BATT_ESC_SEC_MASK (0x1U) +#define BSEC_EVENT_BATT_ESC_SEC_SHIFT (0U) +#define BSEC_EVENT_BATT_ESC_SEC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_SEC_MASK) >> BSEC_EVENT_BATT_ESC_SEC_SHIFT) + + + + +#endif /* HPM_BSEC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_butn_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_butn_regs.h new file mode 100644 index 0000000000..0eeb899ec9 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_butn_regs.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BUTN_H +#define HPM_BUTN_H + +typedef struct { + __RW uint32_t BTN_STATUS; /* 0x0: Button status */ + __RW uint32_t BTN_IRQ_MASK; /* 0x4: Button interrupt mask */ + __RW uint32_t LED_INTENSE; /* 0x8: Debounce setting */ +} BUTN_Type; + + +/* Bitfield definition for register: BTN_STATUS */ +/* + * XWCLICK (RW) + * + * wake button click status when power button held, write 1 to clear flag + * bit0: clicked + * bit1: double clicked + * bit2: tripple clicked + */ +#define BUTN_BTN_STATUS_XWCLICK_MASK (0x70000000UL) +#define BUTN_BTN_STATUS_XWCLICK_SHIFT (28U) +#define BUTN_BTN_STATUS_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XWCLICK_SHIFT) & BUTN_BTN_STATUS_XWCLICK_MASK) +#define BUTN_BTN_STATUS_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XWCLICK_MASK) >> BUTN_BTN_STATUS_XWCLICK_SHIFT) + +/* + * WCLICK (RW) + * + * wake button click status, write 1 to clear flag + * bit0: clicked + * bit1: double clicked + * bit2: tripple clicked + */ +#define BUTN_BTN_STATUS_WCLICK_MASK (0x7000000UL) +#define BUTN_BTN_STATUS_WCLICK_SHIFT (24U) +#define BUTN_BTN_STATUS_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WCLICK_SHIFT) & BUTN_BTN_STATUS_WCLICK_MASK) +#define BUTN_BTN_STATUS_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WCLICK_MASK) >> BUTN_BTN_STATUS_WCLICK_SHIFT) + +/* + * XPCLICK (RW) + * + * power button click status when wake button held, write 1 to clear flag + * bit0: clicked + * bit1: double clicked + * bit2: tripple clicked + */ +#define BUTN_BTN_STATUS_XPCLICK_MASK (0x700000UL) +#define BUTN_BTN_STATUS_XPCLICK_SHIFT (20U) +#define BUTN_BTN_STATUS_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XPCLICK_SHIFT) & BUTN_BTN_STATUS_XPCLICK_MASK) +#define BUTN_BTN_STATUS_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XPCLICK_MASK) >> BUTN_BTN_STATUS_XPCLICK_SHIFT) + +/* + * PCLICK (RW) + * + * power button click status, write 1 to clear flag + * bit0: clicked + * bit1: double clicked + * bit2: tripple clicked + */ +#define BUTN_BTN_STATUS_PCLICK_MASK (0x70000UL) +#define BUTN_BTN_STATUS_PCLICK_SHIFT (16U) +#define BUTN_BTN_STATUS_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PCLICK_SHIFT) & BUTN_BTN_STATUS_PCLICK_MASK) +#define BUTN_BTN_STATUS_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PCLICK_MASK) >> BUTN_BTN_STATUS_PCLICK_SHIFT) + +/* + * DBTN (RW) + * + * Dual button press status, write 1 to clear flag + * bit0: button pressed + * bit1: button confirmd + * bit2: button long pressed + * bit3: button long long pressed + */ +#define BUTN_BTN_STATUS_DBTN_MASK (0xF00U) +#define BUTN_BTN_STATUS_DBTN_SHIFT (8U) +#define BUTN_BTN_STATUS_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_DBTN_SHIFT) & BUTN_BTN_STATUS_DBTN_MASK) +#define BUTN_BTN_STATUS_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_DBTN_MASK) >> BUTN_BTN_STATUS_DBTN_SHIFT) + +/* + * WBTN (RW) + * + * Wake button press status, write 1 to clear flag + * bit0: button pressed + * bit1: button confirmd + * bit2: button long pressed + * bit3: button long long pressed + */ +#define BUTN_BTN_STATUS_WBTN_MASK (0xF0U) +#define BUTN_BTN_STATUS_WBTN_SHIFT (4U) +#define BUTN_BTN_STATUS_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WBTN_SHIFT) & BUTN_BTN_STATUS_WBTN_MASK) +#define BUTN_BTN_STATUS_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WBTN_MASK) >> BUTN_BTN_STATUS_WBTN_SHIFT) + +/* + * PBTN (RW) + * + * Power button press status, write 1 to clear flag + * bit0: button pressed + * bit1: button confirmd + * bit2: button long pressed + * bit3: button long long pressed + */ +#define BUTN_BTN_STATUS_PBTN_MASK (0xFU) +#define BUTN_BTN_STATUS_PBTN_SHIFT (0U) +#define BUTN_BTN_STATUS_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PBTN_SHIFT) & BUTN_BTN_STATUS_PBTN_MASK) +#define BUTN_BTN_STATUS_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PBTN_MASK) >> BUTN_BTN_STATUS_PBTN_SHIFT) + +/* Bitfield definition for register: BTN_IRQ_MASK */ +/* + * XWCLICK (RW) + * + * wake button click status when power button held interrupt enable + * bit0: clicked + * bit1: double clicked + * bit2: tripple clicked + */ +#define BUTN_BTN_IRQ_MASK_XWCLICK_MASK (0x70000000UL) +#define BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT (28U) +#define BUTN_BTN_IRQ_MASK_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) +#define BUTN_BTN_IRQ_MASK_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) + +/* + * WCLICK (RW) + * + * wake button click interrupt enable + * bit0: clicked + * bit1: double clicked + * bit2: tripple clicked + */ +#define BUTN_BTN_IRQ_MASK_WCLICK_MASK (0x7000000UL) +#define BUTN_BTN_IRQ_MASK_WCLICK_SHIFT (24U) +#define BUTN_BTN_IRQ_MASK_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) +#define BUTN_BTN_IRQ_MASK_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) >> BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) + +/* + * XPCLICK (RW) + * + * power button click status when wake button held interrupt enable + * bit0: clicked + * bit1: double clicked + * bit2: tripple clicked + */ +#define BUTN_BTN_IRQ_MASK_XPCLICK_MASK (0x700000UL) +#define BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT (20U) +#define BUTN_BTN_IRQ_MASK_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) +#define BUTN_BTN_IRQ_MASK_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) + +/* + * PCLICK (RW) + * + * power button click interrupt enable + * bit0: clicked + * bit1: double clicked + * bit2: tripple clicked + */ +#define BUTN_BTN_IRQ_MASK_PCLICK_MASK (0x70000UL) +#define BUTN_BTN_IRQ_MASK_PCLICK_SHIFT (16U) +#define BUTN_BTN_IRQ_MASK_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) +#define BUTN_BTN_IRQ_MASK_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) >> BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) + +/* + * DBTN (RW) + * + * Dual button press interrupt enable + * bit0: button pressed + * bit1: button confirmd + * bit2: button long pressed + * bit3: button long long pressed + */ +#define BUTN_BTN_IRQ_MASK_DBTN_MASK (0xF00U) +#define BUTN_BTN_IRQ_MASK_DBTN_SHIFT (8U) +#define BUTN_BTN_IRQ_MASK_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_DBTN_SHIFT) & BUTN_BTN_IRQ_MASK_DBTN_MASK) +#define BUTN_BTN_IRQ_MASK_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_DBTN_MASK) >> BUTN_BTN_IRQ_MASK_DBTN_SHIFT) + +/* + * WBTN (RW) + * + * Wake button press interrupt enable + * bit0: button pressed + * bit1: button confirmd + * bit2: button long pressed + * bit3: button long long pressed + */ +#define BUTN_BTN_IRQ_MASK_WBTN_MASK (0xF0U) +#define BUTN_BTN_IRQ_MASK_WBTN_SHIFT (4U) +#define BUTN_BTN_IRQ_MASK_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WBTN_SHIFT) & BUTN_BTN_IRQ_MASK_WBTN_MASK) +#define BUTN_BTN_IRQ_MASK_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WBTN_MASK) >> BUTN_BTN_IRQ_MASK_WBTN_SHIFT) + +/* + * PBTN (RW) + * + * Power button press interrupt enable + * bit0: button pressed + * bit1: button confirmd + * bit2: button long pressed + * bit3: button long long pressed + */ +#define BUTN_BTN_IRQ_MASK_PBTN_MASK (0xFU) +#define BUTN_BTN_IRQ_MASK_PBTN_SHIFT (0U) +#define BUTN_BTN_IRQ_MASK_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PBTN_SHIFT) & BUTN_BTN_IRQ_MASK_PBTN_MASK) +#define BUTN_BTN_IRQ_MASK_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PBTN_MASK) >> BUTN_BTN_IRQ_MASK_PBTN_SHIFT) + +/* Bitfield definition for register: LED_INTENSE */ +/* + * RLED (RW) + * + * Rbutton brightness 0 + */ +#define BUTN_LED_INTENSE_RLED_MASK (0xF0000UL) +#define BUTN_LED_INTENSE_RLED_SHIFT (16U) +#define BUTN_LED_INTENSE_RLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_RLED_SHIFT) & BUTN_LED_INTENSE_RLED_MASK) +#define BUTN_LED_INTENSE_RLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_RLED_MASK) >> BUTN_LED_INTENSE_RLED_SHIFT) + +/* + * PLED (RW) + * + * Pbutton brightness 0 + */ +#define BUTN_LED_INTENSE_PLED_MASK (0xFU) +#define BUTN_LED_INTENSE_PLED_SHIFT (0U) +#define BUTN_LED_INTENSE_PLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_PLED_SHIFT) & BUTN_LED_INTENSE_PLED_MASK) +#define BUTN_LED_INTENSE_PLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_PLED_MASK) >> BUTN_LED_INTENSE_PLED_SHIFT) + + + + +#endif /* HPM_BUTN_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h new file mode 100644 index 0000000000..0a3a034d98 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h @@ -0,0 +1,1022 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CAM_H +#define HPM_CAM_H + +typedef struct { + __RW uint32_t CR1; /* 0x0: Control Register */ + __RW uint32_t INT_EN; /* 0x4: Interrupt Enable Register */ + __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ + __RW uint32_t CR2; /* 0x10: Control 2 Register */ + __R uint8_t RESERVED1[16]; /* 0x14 - 0x23: Reserved */ + __W uint32_t STA; /* 0x24: Status Register */ + __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ + __RW uint32_t DMASA_FB1; /* 0x30: Pixel DMA Frame Buffer 1 Address */ + __RW uint32_t DMASA_FB2; /* 0x34: Pixel DMA Frame Buffer 2 Address */ + __RW uint32_t BUF_PARA; /* 0x38: Buffer Parameters Register */ + __RW uint32_t IDEAL_WN_SIZE; /* 0x3C: Ideal Image Size Register */ + __R uint8_t RESERVED3[12]; /* 0x40 - 0x4B: Reserved */ + __RW uint32_t CR18; /* 0x4C: Control CR18 Register */ + __RW uint32_t DMASA_UV1; /* 0x50: Pixel UV DMA Frame Buffer 1 Address */ + __RW uint32_t DMASA_UV2; /* 0x54: Pixel UV DMA Frame Buffer 2 Address */ + __RW uint32_t CR20; /* 0x58: Control CR20 Register */ + __RW uint32_t MAX_WN_CYCLE; /* 0x5C: Max Window Size Register */ + __R uint8_t RESERVED4[16]; /* 0x60 - 0x6F: Reserved */ + __RW uint32_t CSC_COEF0; /* 0x70: Color Space Conversion Config Register 0 */ + __RW uint32_t CSC_COEF1; /* 0x74: Color Space Conversion Config Register 1 */ + __RW uint32_t CSC_COEF2; /* 0x78: Color Space Conversion Config Register 2 */ + __RW uint32_t CLRKEY_LOW; /* 0x7C: Low Color Key Register */ + __RW uint32_t CLRKEY_HIGH; /* 0x80: High Color Key Register */ + __R uint8_t RESERVED5[12]; /* 0x84 - 0x8F: Reserved */ + __R uint32_t HISTOGRAM_FIFO[256]; /* 0x90 - 0x48C: Histogram Registers */ +} CAM_Type; + + +/* Bitfield definition for register: CR1 */ +/* + * COLOR_EXT (RW) + * + * If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. + * The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. + */ +#define CAM_CR1_COLOR_EXT_MASK (0x20000000UL) +#define CAM_CR1_COLOR_EXT_SHIFT (29U) +#define CAM_CR1_COLOR_EXT_SET(x) (((uint32_t)(x) << CAM_CR1_COLOR_EXT_SHIFT) & CAM_CR1_COLOR_EXT_MASK) +#define CAM_CR1_COLOR_EXT_GET(x) (((uint32_t)(x) & CAM_CR1_COLOR_EXT_MASK) >> CAM_CR1_COLOR_EXT_SHIFT) + +/* + * INV_PIXCLK (RW) + * + * invert pixclk pad input before it is used + */ +#define CAM_CR1_INV_PIXCLK_MASK (0x10000000UL) +#define CAM_CR1_INV_PIXCLK_SHIFT (28U) +#define CAM_CR1_INV_PIXCLK_SET(x) (((uint32_t)(x) << CAM_CR1_INV_PIXCLK_SHIFT) & CAM_CR1_INV_PIXCLK_MASK) +#define CAM_CR1_INV_PIXCLK_GET(x) (((uint32_t)(x) & CAM_CR1_INV_PIXCLK_MASK) >> CAM_CR1_INV_PIXCLK_SHIFT) + +/* + * INV_HSYNC (RW) + * + * invert hsync pad input before it is used + */ +#define CAM_CR1_INV_HSYNC_MASK (0x8000000UL) +#define CAM_CR1_INV_HSYNC_SHIFT (27U) +#define CAM_CR1_INV_HSYNC_SET(x) (((uint32_t)(x) << CAM_CR1_INV_HSYNC_SHIFT) & CAM_CR1_INV_HSYNC_MASK) +#define CAM_CR1_INV_HSYNC_GET(x) (((uint32_t)(x) & CAM_CR1_INV_HSYNC_MASK) >> CAM_CR1_INV_HSYNC_SHIFT) + +/* + * INV_VSYNC (RW) + * + * invert vsync pad input before it is used + */ +#define CAM_CR1_INV_VSYNC_MASK (0x4000000UL) +#define CAM_CR1_INV_VSYNC_SHIFT (26U) +#define CAM_CR1_INV_VSYNC_SET(x) (((uint32_t)(x) << CAM_CR1_INV_VSYNC_SHIFT) & CAM_CR1_INV_VSYNC_MASK) +#define CAM_CR1_INV_VSYNC_GET(x) (((uint32_t)(x) & CAM_CR1_INV_VSYNC_MASK) >> CAM_CR1_INV_VSYNC_SHIFT) + +/* + * SWAP16_EN (RW) + * + * SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. + * NOTE: Example of swapping enabled: + * Data input to FIFO = 0x11223344 + * Data in RX FIFO = 0x 33441122 + * NOTE: Example of swapping disabled: + * Data input to FIFO = 0x11223344 + * Data in RX FIFO = 0x11223344 + * 0 Disable swapping + * 1 Enable swapping + */ +#define CAM_CR1_SWAP16_EN_MASK (0x2000000UL) +#define CAM_CR1_SWAP16_EN_SHIFT (25U) +#define CAM_CR1_SWAP16_EN_SET(x) (((uint32_t)(x) << CAM_CR1_SWAP16_EN_SHIFT) & CAM_CR1_SWAP16_EN_MASK) +#define CAM_CR1_SWAP16_EN_GET(x) (((uint32_t)(x) & CAM_CR1_SWAP16_EN_MASK) >> CAM_CR1_SWAP16_EN_SHIFT) + +/* + * PACK_DIR (RW) + * + * Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. + * 0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. + * 1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. + */ +#define CAM_CR1_PACK_DIR_MASK (0x1000000UL) +#define CAM_CR1_PACK_DIR_SHIFT (24U) +#define CAM_CR1_PACK_DIR_SET(x) (((uint32_t)(x) << CAM_CR1_PACK_DIR_SHIFT) & CAM_CR1_PACK_DIR_MASK) +#define CAM_CR1_PACK_DIR_GET(x) (((uint32_t)(x) & CAM_CR1_PACK_DIR_MASK) >> CAM_CR1_PACK_DIR_SHIFT) + +/* + * RESTART_BUSPTR (RW) + * + * force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer + */ +#define CAM_CR1_RESTART_BUSPTR_MASK (0x800000UL) +#define CAM_CR1_RESTART_BUSPTR_SHIFT (23U) +#define CAM_CR1_RESTART_BUSPTR_SET(x) (((uint32_t)(x) << CAM_CR1_RESTART_BUSPTR_SHIFT) & CAM_CR1_RESTART_BUSPTR_MASK) +#define CAM_CR1_RESTART_BUSPTR_GET(x) (((uint32_t)(x) & CAM_CR1_RESTART_BUSPTR_MASK) >> CAM_CR1_RESTART_BUSPTR_SHIFT) + +/* + * ASYNC_RXFIFO_CLR (RW) + * + * ASynchronous Rx FIFO Clear. + * When asserted, this bit clears RXFIFO immediately. + * It will be auto-cleared. + */ +#define CAM_CR1_ASYNC_RXFIFO_CLR_MASK (0x100000UL) +#define CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT (20U) +#define CAM_CR1_ASYNC_RXFIFO_CLR_SET(x) (((uint32_t)(x) << CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT) & CAM_CR1_ASYNC_RXFIFO_CLR_MASK) +#define CAM_CR1_ASYNC_RXFIFO_CLR_GET(x) (((uint32_t)(x) & CAM_CR1_ASYNC_RXFIFO_CLR_MASK) >> CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT) + +/* + * SYNC_RXFIFO_CLR (RW) + * + * Synchronous Rx FIFO Clear. + * When asserted, this bit clears RXFIFO on every SOF. + */ +#define CAM_CR1_SYNC_RXFIFO_CLR_MASK (0x80000UL) +#define CAM_CR1_SYNC_RXFIFO_CLR_SHIFT (19U) +#define CAM_CR1_SYNC_RXFIFO_CLR_SET(x) (((uint32_t)(x) << CAM_CR1_SYNC_RXFIFO_CLR_SHIFT) & CAM_CR1_SYNC_RXFIFO_CLR_MASK) +#define CAM_CR1_SYNC_RXFIFO_CLR_GET(x) (((uint32_t)(x) & CAM_CR1_SYNC_RXFIFO_CLR_MASK) >> CAM_CR1_SYNC_RXFIFO_CLR_SHIFT) + +/* + * SOF_INT_POL (RW) + * + * SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. + * 0 SOF interrupt is generated on SOF falling edge + * 1 SOF interrupt is generated on SOF rising edge + */ +#define CAM_CR1_SOF_INT_POL_MASK (0x20000UL) +#define CAM_CR1_SOF_INT_POL_SHIFT (17U) +#define CAM_CR1_SOF_INT_POL_SET(x) (((uint32_t)(x) << CAM_CR1_SOF_INT_POL_SHIFT) & CAM_CR1_SOF_INT_POL_MASK) +#define CAM_CR1_SOF_INT_POL_GET(x) (((uint32_t)(x) & CAM_CR1_SOF_INT_POL_MASK) >> CAM_CR1_SOF_INT_POL_SHIFT) + +/* + * INV_DATA (RW) + * + * Invert Data Input. This bit enables or disables internal inverters on the data lines. + * 0 CAM_D data lines are directly applied to internal circuitry + * 1 CAM_D data lines are inverted before applied to internal circuitry + */ +#define CAM_CR1_INV_DATA_MASK (0x8000U) +#define CAM_CR1_INV_DATA_SHIFT (15U) +#define CAM_CR1_INV_DATA_SET(x) (((uint32_t)(x) << CAM_CR1_INV_DATA_SHIFT) & CAM_CR1_INV_DATA_MASK) +#define CAM_CR1_INV_DATA_GET(x) (((uint32_t)(x) & CAM_CR1_INV_DATA_MASK) >> CAM_CR1_INV_DATA_SHIFT) + +/* + * STORAGE_MODE (RW) + * + * 00: Normal Mode (one plane mode) + * 01: Two Plane Mode (Y, UV plane) + * 10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 + * 11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 + */ +#define CAM_CR1_STORAGE_MODE_MASK (0xC00U) +#define CAM_CR1_STORAGE_MODE_SHIFT (10U) +#define CAM_CR1_STORAGE_MODE_SET(x) (((uint32_t)(x) << CAM_CR1_STORAGE_MODE_SHIFT) & CAM_CR1_STORAGE_MODE_MASK) +#define CAM_CR1_STORAGE_MODE_GET(x) (((uint32_t)(x) & CAM_CR1_STORAGE_MODE_MASK) >> CAM_CR1_STORAGE_MODE_SHIFT) + +/* + * COLOR_FORMATS (RW) + * + * input color formats: + * 0010b: 24bit: RGB888 + * 0100b: 16bit: RGB565 + * 0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) + * YUV + * YCrCb + * Note: YUV420 is not supported. + * 1000b: 24bit: YUV444 + */ +#define CAM_CR1_COLOR_FORMATS_MASK (0x78U) +#define CAM_CR1_COLOR_FORMATS_SHIFT (3U) +#define CAM_CR1_COLOR_FORMATS_SET(x) (((uint32_t)(x) << CAM_CR1_COLOR_FORMATS_SHIFT) & CAM_CR1_COLOR_FORMATS_MASK) +#define CAM_CR1_COLOR_FORMATS_GET(x) (((uint32_t)(x) & CAM_CR1_COLOR_FORMATS_MASK) >> CAM_CR1_COLOR_FORMATS_SHIFT) + +/* + * SENSOR_BIT_WIDTH (RW) + * + * the bit width of the sensor + * 0: 8 bits + * 1: 10 bits + * Others: Undefined + */ +#define CAM_CR1_SENSOR_BIT_WIDTH_MASK (0x7U) +#define CAM_CR1_SENSOR_BIT_WIDTH_SHIFT (0U) +#define CAM_CR1_SENSOR_BIT_WIDTH_SET(x) (((uint32_t)(x) << CAM_CR1_SENSOR_BIT_WIDTH_SHIFT) & CAM_CR1_SENSOR_BIT_WIDTH_MASK) +#define CAM_CR1_SENSOR_BIT_WIDTH_GET(x) (((uint32_t)(x) & CAM_CR1_SENSOR_BIT_WIDTH_MASK) >> CAM_CR1_SENSOR_BIT_WIDTH_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * ERR_CL_BWID_CFG_INT_EN (RW) + * + * The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable + */ +#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK (0x2000U) +#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT (13U) +#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT) & CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) +#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) >> CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT) + +/* + * HIST_DONE_INT_EN (RW) + * + * Enable hist done int + */ +#define CAM_INT_EN_HIST_DONE_INT_EN_MASK (0x1000U) +#define CAM_INT_EN_HIST_DONE_INT_EN_SHIFT (12U) +#define CAM_INT_EN_HIST_DONE_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_HIST_DONE_INT_EN_SHIFT) & CAM_INT_EN_HIST_DONE_INT_EN_MASK) +#define CAM_INT_EN_HIST_DONE_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_HIST_DONE_INT_EN_MASK) >> CAM_INT_EN_HIST_DONE_INT_EN_SHIFT) + +/* + * HRESP_ERR_EN (RW) + * + * Hresponse Error Enable. This bit enables the hresponse error interrupt. + * 0 Disable hresponse error interrupt + * 1 Enable hresponse error interrupt + */ +#define CAM_INT_EN_HRESP_ERR_EN_MASK (0x800U) +#define CAM_INT_EN_HRESP_ERR_EN_SHIFT (11U) +#define CAM_INT_EN_HRESP_ERR_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_HRESP_ERR_EN_SHIFT) & CAM_INT_EN_HRESP_ERR_EN_MASK) +#define CAM_INT_EN_HRESP_ERR_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_HRESP_ERR_EN_MASK) >> CAM_INT_EN_HRESP_ERR_EN_SHIFT) + +/* + * EOF_INT_EN (RW) + * + * End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. + * 0 EOF interrupt is disabled. + * 1 EOF interrupt is generated when RX count value is reached. + */ +#define CAM_INT_EN_EOF_INT_EN_MASK (0x200U) +#define CAM_INT_EN_EOF_INT_EN_SHIFT (9U) +#define CAM_INT_EN_EOF_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_EOF_INT_EN_SHIFT) & CAM_INT_EN_EOF_INT_EN_MASK) +#define CAM_INT_EN_EOF_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_EOF_INT_EN_MASK) >> CAM_INT_EN_EOF_INT_EN_SHIFT) + +/* + * RF_OR_INTEN (RW) + * + * RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. + * 0 RxFIFO overrun interrupt is disabled + * 1 RxFIFO overrun interrupt is enabled + */ +#define CAM_INT_EN_RF_OR_INTEN_MASK (0x40U) +#define CAM_INT_EN_RF_OR_INTEN_SHIFT (6U) +#define CAM_INT_EN_RF_OR_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_RF_OR_INTEN_SHIFT) & CAM_INT_EN_RF_OR_INTEN_MASK) +#define CAM_INT_EN_RF_OR_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_RF_OR_INTEN_MASK) >> CAM_INT_EN_RF_OR_INTEN_SHIFT) + +/* + * FB2_DMA_DONE_INTEN (RW) + * + * Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA + * transfer done. + * 0 Frame Buffer2 DMA Transfer Done interrupt disable + * 1 Frame Buffer2 DMA Transfer Done interrupt enable + */ +#define CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK (0x8U) +#define CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT (3U) +#define CAM_INT_EN_FB2_DMA_DONE_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT) & CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK) +#define CAM_INT_EN_FB2_DMA_DONE_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK) >> CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT) + +/* + * FB1_DMA_DONE_INTEN (RW) + * + * Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA + * transfer done. + * 0 Frame Buffer1 DMA Transfer Done interrupt disable + * 1 Frame Buffer1 DMA Transfer Done interrupt enable + */ +#define CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK (0x4U) +#define CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT (2U) +#define CAM_INT_EN_FB1_DMA_DONE_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT) & CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK) +#define CAM_INT_EN_FB1_DMA_DONE_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK) >> CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT) + +/* + * SOF_INT_EN (RW) + * + * Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. + * 0 SOF interrupt disable + * 1 SOF interrupt enable + */ +#define CAM_INT_EN_SOF_INT_EN_MASK (0x1U) +#define CAM_INT_EN_SOF_INT_EN_SHIFT (0U) +#define CAM_INT_EN_SOF_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_SOF_INT_EN_SHIFT) & CAM_INT_EN_SOF_INT_EN_MASK) +#define CAM_INT_EN_SOF_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_SOF_INT_EN_MASK) >> CAM_INT_EN_SOF_INT_EN_SHIFT) + +/* Bitfield definition for register: CR2 */ +/* + * FRMCNT_15_0 (ROI) + * + * Frame Counter. This is a 16-bit Frame Counter + * (Wraps around automatically after reaching the maximum) + */ +#define CAM_CR2_FRMCNT_15_0_MASK (0xFFFF0000UL) +#define CAM_CR2_FRMCNT_15_0_SHIFT (16U) +#define CAM_CR2_FRMCNT_15_0_GET(x) (((uint32_t)(x) & CAM_CR2_FRMCNT_15_0_MASK) >> CAM_CR2_FRMCNT_15_0_SHIFT) + +/* + * FRMCNT_RST (RW) + * + * Frame Count Reset. Resets the Frame Counter. + * 0 Do not reset + * 1 Reset frame counter immediately + */ +#define CAM_CR2_FRMCNT_RST_MASK (0x8000U) +#define CAM_CR2_FRMCNT_RST_SHIFT (15U) +#define CAM_CR2_FRMCNT_RST_SET(x) (((uint32_t)(x) << CAM_CR2_FRMCNT_RST_SHIFT) & CAM_CR2_FRMCNT_RST_MASK) +#define CAM_CR2_FRMCNT_RST_GET(x) (((uint32_t)(x) & CAM_CR2_FRMCNT_RST_MASK) >> CAM_CR2_FRMCNT_RST_SHIFT) + +/* + * RXFF_LEVEL (RW) + * + * RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. + * 000 4 Double words + * 001 8 Double words + * 010 16 Double words + * 011 24 Double words + * 100 32 Double words + * 101 48 Double words + * 110 64 Double words + * 111 96 Double words + */ +#define CAM_CR2_RXFF_LEVEL_MASK (0xE00U) +#define CAM_CR2_RXFF_LEVEL_SHIFT (9U) +#define CAM_CR2_RXFF_LEVEL_SET(x) (((uint32_t)(x) << CAM_CR2_RXFF_LEVEL_SHIFT) & CAM_CR2_RXFF_LEVEL_MASK) +#define CAM_CR2_RXFF_LEVEL_GET(x) (((uint32_t)(x) & CAM_CR2_RXFF_LEVEL_MASK) >> CAM_CR2_RXFF_LEVEL_SHIFT) + +/* + * DMA_REQ_EN_RFF (RW) + * + * DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. + * 0 Disable the dma request + * 1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. + */ +#define CAM_CR2_DMA_REQ_EN_RFF_MASK (0x20U) +#define CAM_CR2_DMA_REQ_EN_RFF_SHIFT (5U) +#define CAM_CR2_DMA_REQ_EN_RFF_SET(x) (((uint32_t)(x) << CAM_CR2_DMA_REQ_EN_RFF_SHIFT) & CAM_CR2_DMA_REQ_EN_RFF_MASK) +#define CAM_CR2_DMA_REQ_EN_RFF_GET(x) (((uint32_t)(x) & CAM_CR2_DMA_REQ_EN_RFF_MASK) >> CAM_CR2_DMA_REQ_EN_RFF_SHIFT) + +/* + * CLRBITFORMAT (RW) + * + * Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. + */ +#define CAM_CR2_CLRBITFORMAT_MASK (0xFU) +#define CAM_CR2_CLRBITFORMAT_SHIFT (0U) +#define CAM_CR2_CLRBITFORMAT_SET(x) (((uint32_t)(x) << CAM_CR2_CLRBITFORMAT_SHIFT) & CAM_CR2_CLRBITFORMAT_MASK) +#define CAM_CR2_CLRBITFORMAT_GET(x) (((uint32_t)(x) & CAM_CR2_CLRBITFORMAT_MASK) >> CAM_CR2_CLRBITFORMAT_SHIFT) + +/* Bitfield definition for register: STA */ +/* + * ERR_CL_BWID_CFG (W1C) + * + * The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found + */ +#define CAM_STA_ERR_CL_BWID_CFG_MASK (0x80000UL) +#define CAM_STA_ERR_CL_BWID_CFG_SHIFT (19U) +#define CAM_STA_ERR_CL_BWID_CFG_SET(x) (((uint32_t)(x) << CAM_STA_ERR_CL_BWID_CFG_SHIFT) & CAM_STA_ERR_CL_BWID_CFG_MASK) +#define CAM_STA_ERR_CL_BWID_CFG_GET(x) (((uint32_t)(x) & CAM_STA_ERR_CL_BWID_CFG_MASK) >> CAM_STA_ERR_CL_BWID_CFG_SHIFT) + +/* + * HIST_DONE (W1C) + * + * hist cal done + */ +#define CAM_STA_HIST_DONE_MASK (0x40000UL) +#define CAM_STA_HIST_DONE_SHIFT (18U) +#define CAM_STA_HIST_DONE_SET(x) (((uint32_t)(x) << CAM_STA_HIST_DONE_SHIFT) & CAM_STA_HIST_DONE_MASK) +#define CAM_STA_HIST_DONE_GET(x) (((uint32_t)(x) & CAM_STA_HIST_DONE_MASK) >> CAM_STA_HIST_DONE_SHIFT) + +/* + * RF_OR_INT (W1C) + * + * RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing + * 1) + * 0 RXFIFO has not overflowed. + * 1 RXFIFO has overflowed. + */ +#define CAM_STA_RF_OR_INT_MASK (0x2000U) +#define CAM_STA_RF_OR_INT_SHIFT (13U) +#define CAM_STA_RF_OR_INT_SET(x) (((uint32_t)(x) << CAM_STA_RF_OR_INT_SHIFT) & CAM_STA_RF_OR_INT_MASK) +#define CAM_STA_RF_OR_INT_GET(x) (((uint32_t)(x) & CAM_STA_RF_OR_INT_MASK) >> CAM_STA_RF_OR_INT_SHIFT) + +/* + * DMA_TSF_DONE_FB2 (W1C) + * + * DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writting 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) + * 0 DMA transfer is not completed. + * 1 DMA transfer is completed. + */ +#define CAM_STA_DMA_TSF_DONE_FB2_MASK (0x400U) +#define CAM_STA_DMA_TSF_DONE_FB2_SHIFT (10U) +#define CAM_STA_DMA_TSF_DONE_FB2_SET(x) (((uint32_t)(x) << CAM_STA_DMA_TSF_DONE_FB2_SHIFT) & CAM_STA_DMA_TSF_DONE_FB2_MASK) +#define CAM_STA_DMA_TSF_DONE_FB2_GET(x) (((uint32_t)(x) & CAM_STA_DMA_TSF_DONE_FB2_MASK) >> CAM_STA_DMA_TSF_DONE_FB2_SHIFT) + +/* + * DMA_TSF_DONE_FB1 (W1C) + * + * DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writting 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) + * 0 DMA transfer is not completed. + * 1 DMA transfer is completed. + */ +#define CAM_STA_DMA_TSF_DONE_FB1_MASK (0x200U) +#define CAM_STA_DMA_TSF_DONE_FB1_SHIFT (9U) +#define CAM_STA_DMA_TSF_DONE_FB1_SET(x) (((uint32_t)(x) << CAM_STA_DMA_TSF_DONE_FB1_SHIFT) & CAM_STA_DMA_TSF_DONE_FB1_MASK) +#define CAM_STA_DMA_TSF_DONE_FB1_GET(x) (((uint32_t)(x) & CAM_STA_DMA_TSF_DONE_FB1_MASK) >> CAM_STA_DMA_TSF_DONE_FB1_SHIFT) + +/* + * EOF_INT (W1C) + * + * End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) + * 0 EOF is not detected. + * 1 EOF is detected. + */ +#define CAM_STA_EOF_INT_MASK (0x80U) +#define CAM_STA_EOF_INT_SHIFT (7U) +#define CAM_STA_EOF_INT_SET(x) (((uint32_t)(x) << CAM_STA_EOF_INT_SHIFT) & CAM_STA_EOF_INT_MASK) +#define CAM_STA_EOF_INT_GET(x) (((uint32_t)(x) & CAM_STA_EOF_INT_MASK) >> CAM_STA_EOF_INT_SHIFT) + +/* + * SOF_INT (W1C) + * + * Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) + * 0 SOF is not detected. + * 1 SOF is detected. + */ +#define CAM_STA_SOF_INT_MASK (0x40U) +#define CAM_STA_SOF_INT_SHIFT (6U) +#define CAM_STA_SOF_INT_SET(x) (((uint32_t)(x) << CAM_STA_SOF_INT_SHIFT) & CAM_STA_SOF_INT_MASK) +#define CAM_STA_SOF_INT_GET(x) (((uint32_t)(x) & CAM_STA_SOF_INT_MASK) >> CAM_STA_SOF_INT_SHIFT) + +/* + * HRESP_ERR_INT (W1C) + * + * Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing + * 1) + * 0 No hresponse error. + * 1 Hresponse error is detected. + */ +#define CAM_STA_HRESP_ERR_INT_MASK (0x4U) +#define CAM_STA_HRESP_ERR_INT_SHIFT (2U) +#define CAM_STA_HRESP_ERR_INT_SET(x) (((uint32_t)(x) << CAM_STA_HRESP_ERR_INT_SHIFT) & CAM_STA_HRESP_ERR_INT_MASK) +#define CAM_STA_HRESP_ERR_INT_GET(x) (((uint32_t)(x) & CAM_STA_HRESP_ERR_INT_MASK) >> CAM_STA_HRESP_ERR_INT_SHIFT) + +/* Bitfield definition for register: DMASA_FB1 */ +/* + * PTR (RW) + * + * DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. + * In Two-Plane Mode, Y buffer1 + */ +#define CAM_DMASA_FB1_PTR_MASK (0xFFFFFFFCUL) +#define CAM_DMASA_FB1_PTR_SHIFT (2U) +#define CAM_DMASA_FB1_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_FB1_PTR_SHIFT) & CAM_DMASA_FB1_PTR_MASK) +#define CAM_DMASA_FB1_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_FB1_PTR_MASK) >> CAM_DMASA_FB1_PTR_SHIFT) + +/* Bitfield definition for register: DMASA_FB2 */ +/* + * PTR (RW) + * + * DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. + * In Two-Plane Mode, Y buffer2 + */ +#define CAM_DMASA_FB2_PTR_MASK (0xFFFFFFFCUL) +#define CAM_DMASA_FB2_PTR_SHIFT (2U) +#define CAM_DMASA_FB2_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_FB2_PTR_SHIFT) & CAM_DMASA_FB2_PTR_MASK) +#define CAM_DMASA_FB2_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_FB2_PTR_MASK) >> CAM_DMASA_FB2_PTR_SHIFT) + +/* Bitfield definition for register: BUF_PARA */ +/* + * LINEBSP_STRIDE (RW) + * + * Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. + * The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. + */ +#define CAM_BUF_PARA_LINEBSP_STRIDE_MASK (0xFFFFU) +#define CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT (0U) +#define CAM_BUF_PARA_LINEBSP_STRIDE_SET(x) (((uint32_t)(x) << CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT) & CAM_BUF_PARA_LINEBSP_STRIDE_MASK) +#define CAM_BUF_PARA_LINEBSP_STRIDE_GET(x) (((uint32_t)(x) & CAM_BUF_PARA_LINEBSP_STRIDE_MASK) >> CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT) + +/* Bitfield definition for register: IDEAL_WN_SIZE */ +/* + * HEIGHT (RW) + * + * Image Height. Indicates how many active pixels in a column of the image from the sensor. + */ +#define CAM_IDEAL_WN_SIZE_HEIGHT_MASK (0xFFFF0000UL) +#define CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT (16U) +#define CAM_IDEAL_WN_SIZE_HEIGHT_SET(x) (((uint32_t)(x) << CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT) & CAM_IDEAL_WN_SIZE_HEIGHT_MASK) +#define CAM_IDEAL_WN_SIZE_HEIGHT_GET(x) (((uint32_t)(x) & CAM_IDEAL_WN_SIZE_HEIGHT_MASK) >> CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT) + +/* + * WIDTH (RW) + * + * Image Width. Indicates how many active pixels in a line of the image from the sensor. + * The number of bytes to be transfered is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. + * As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. + */ +#define CAM_IDEAL_WN_SIZE_WIDTH_MASK (0xFFFFU) +#define CAM_IDEAL_WN_SIZE_WIDTH_SHIFT (0U) +#define CAM_IDEAL_WN_SIZE_WIDTH_SET(x) (((uint32_t)(x) << CAM_IDEAL_WN_SIZE_WIDTH_SHIFT) & CAM_IDEAL_WN_SIZE_WIDTH_MASK) +#define CAM_IDEAL_WN_SIZE_WIDTH_GET(x) (((uint32_t)(x) & CAM_IDEAL_WN_SIZE_WIDTH_MASK) >> CAM_IDEAL_WN_SIZE_WIDTH_SHIFT) + +/* Bitfield definition for register: CR18 */ +/* + * CAM_ENABLE (RW) + * + * CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. + */ +#define CAM_CR18_CAM_ENABLE_MASK (0x80000000UL) +#define CAM_CR18_CAM_ENABLE_SHIFT (31U) +#define CAM_CR18_CAM_ENABLE_SET(x) (((uint32_t)(x) << CAM_CR18_CAM_ENABLE_SHIFT) & CAM_CR18_CAM_ENABLE_MASK) +#define CAM_CR18_CAM_ENABLE_GET(x) (((uint32_t)(x) & CAM_CR18_CAM_ENABLE_MASK) >> CAM_CR18_CAM_ENABLE_SHIFT) + +/* + * AWQOS (RW) + * + * AWQOS for bus fabric arbitration + */ +#define CAM_CR18_AWQOS_MASK (0x780U) +#define CAM_CR18_AWQOS_SHIFT (7U) +#define CAM_CR18_AWQOS_SET(x) (((uint32_t)(x) << CAM_CR18_AWQOS_SHIFT) & CAM_CR18_AWQOS_MASK) +#define CAM_CR18_AWQOS_GET(x) (((uint32_t)(x) & CAM_CR18_AWQOS_MASK) >> CAM_CR18_AWQOS_SHIFT) + +/* Bitfield definition for register: DMASA_UV1 */ +/* + * PTR (RW) + * + * Two Plane UV Buffer Start Address 1 + */ +#define CAM_DMASA_UV1_PTR_MASK (0xFFFFFFFCUL) +#define CAM_DMASA_UV1_PTR_SHIFT (2U) +#define CAM_DMASA_UV1_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_UV1_PTR_SHIFT) & CAM_DMASA_UV1_PTR_MASK) +#define CAM_DMASA_UV1_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_UV1_PTR_MASK) >> CAM_DMASA_UV1_PTR_SHIFT) + +/* Bitfield definition for register: DMASA_UV2 */ +/* + * PTR (RW) + * + * Two Plane UV Buffer Start Address 2 + */ +#define CAM_DMASA_UV2_PTR_MASK (0xFFFFFFFCUL) +#define CAM_DMASA_UV2_PTR_SHIFT (2U) +#define CAM_DMASA_UV2_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_UV2_PTR_SHIFT) & CAM_DMASA_UV2_PTR_MASK) +#define CAM_DMASA_UV2_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_UV2_PTR_MASK) >> CAM_DMASA_UV2_PTR_SHIFT) + +/* Bitfield definition for register: CR20 */ +/* + * BINARY_EN (RW) + * + * binary picture output enable + */ +#define CAM_CR20_BINARY_EN_MASK (0x80000000UL) +#define CAM_CR20_BINARY_EN_SHIFT (31U) +#define CAM_CR20_BINARY_EN_SET(x) (((uint32_t)(x) << CAM_CR20_BINARY_EN_SHIFT) & CAM_CR20_BINARY_EN_MASK) +#define CAM_CR20_BINARY_EN_GET(x) (((uint32_t)(x) & CAM_CR20_BINARY_EN_MASK) >> CAM_CR20_BINARY_EN_SHIFT) + +/* + * HISTOGRAM_EN (RW) + * + * histogarm enable + */ +#define CAM_CR20_HISTOGRAM_EN_MASK (0x40000000UL) +#define CAM_CR20_HISTOGRAM_EN_SHIFT (30U) +#define CAM_CR20_HISTOGRAM_EN_SET(x) (((uint32_t)(x) << CAM_CR20_HISTOGRAM_EN_SHIFT) & CAM_CR20_HISTOGRAM_EN_MASK) +#define CAM_CR20_HISTOGRAM_EN_GET(x) (((uint32_t)(x) & CAM_CR20_HISTOGRAM_EN_MASK) >> CAM_CR20_HISTOGRAM_EN_SHIFT) + +/* + * BIG_END (RW) + * + * Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. + */ +#define CAM_CR20_BIG_END_MASK (0x100U) +#define CAM_CR20_BIG_END_SHIFT (8U) +#define CAM_CR20_BIG_END_SET(x) (((uint32_t)(x) << CAM_CR20_BIG_END_SHIFT) & CAM_CR20_BIG_END_MASK) +#define CAM_CR20_BIG_END_GET(x) (((uint32_t)(x) & CAM_CR20_BIG_END_MASK) >> CAM_CR20_BIG_END_SHIFT) + +/* + * THRESHOLD (RW) + * + * Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. + */ +#define CAM_CR20_THRESHOLD_MASK (0xFFU) +#define CAM_CR20_THRESHOLD_SHIFT (0U) +#define CAM_CR20_THRESHOLD_SET(x) (((uint32_t)(x) << CAM_CR20_THRESHOLD_SHIFT) & CAM_CR20_THRESHOLD_MASK) +#define CAM_CR20_THRESHOLD_GET(x) (((uint32_t)(x) & CAM_CR20_THRESHOLD_MASK) >> CAM_CR20_THRESHOLD_SHIFT) + +/* Bitfield definition for register: MAX_WN_CYCLE */ +/* + * ROW (RW) + * + * Max Width-1 + */ +#define CAM_MAX_WN_CYCLE_ROW_MASK (0xFFFF0000UL) +#define CAM_MAX_WN_CYCLE_ROW_SHIFT (16U) +#define CAM_MAX_WN_CYCLE_ROW_SET(x) (((uint32_t)(x) << CAM_MAX_WN_CYCLE_ROW_SHIFT) & CAM_MAX_WN_CYCLE_ROW_MASK) +#define CAM_MAX_WN_CYCLE_ROW_GET(x) (((uint32_t)(x) & CAM_MAX_WN_CYCLE_ROW_MASK) >> CAM_MAX_WN_CYCLE_ROW_SHIFT) + +/* + * COL (RW) + * + * Max Height-1 + */ +#define CAM_MAX_WN_CYCLE_COL_MASK (0xFFFFU) +#define CAM_MAX_WN_CYCLE_COL_SHIFT (0U) +#define CAM_MAX_WN_CYCLE_COL_SET(x) (((uint32_t)(x) << CAM_MAX_WN_CYCLE_COL_SHIFT) & CAM_MAX_WN_CYCLE_COL_MASK) +#define CAM_MAX_WN_CYCLE_COL_GET(x) (((uint32_t)(x) & CAM_MAX_WN_CYCLE_COL_MASK) >> CAM_MAX_WN_CYCLE_COL_SHIFT) + +/* Bitfield definition for register: CSC_COEF0 */ +/* + * YCBCR_MODE (RW) + * + * This bit changes the behavior when performing U/V converting. + * 0b - Converting YUV to RGB data + * 1b - Converting YCbCr to RGB data + */ +#define CAM_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) +#define CAM_CSC_COEF0_YCBCR_MODE_SHIFT (31U) +#define CAM_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_YCBCR_MODE_SHIFT) & CAM_CSC_COEF0_YCBCR_MODE_MASK) +#define CAM_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_YCBCR_MODE_MASK) >> CAM_CSC_COEF0_YCBCR_MODE_SHIFT) + +/* + * ENABLE (RW) + * + * Enable the CSC unit + * 0b - The CSC is bypassed and the input pixels are RGB data already + * 1b - The CSC is enabled and the pixels will be converted to RGB data + */ +#define CAM_CSC_COEF0_ENABLE_MASK (0x40000000UL) +#define CAM_CSC_COEF0_ENABLE_SHIFT (30U) +#define CAM_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_ENABLE_SHIFT) & CAM_CSC_COEF0_ENABLE_MASK) +#define CAM_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_ENABLE_MASK) >> CAM_CSC_COEF0_ENABLE_SHIFT) + +/* + * C0 (RW) + * + * Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + */ +#define CAM_CSC_COEF0_C0_MASK (0x1FFC0000UL) +#define CAM_CSC_COEF0_C0_SHIFT (18U) +#define CAM_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_C0_SHIFT) & CAM_CSC_COEF0_C0_MASK) +#define CAM_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_C0_MASK) >> CAM_CSC_COEF0_C0_SHIFT) + +/* + * UV_OFFSET (RW) + * + * Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. + * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + */ +#define CAM_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) +#define CAM_CSC_COEF0_UV_OFFSET_SHIFT (9U) +#define CAM_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_UV_OFFSET_SHIFT) & CAM_CSC_COEF0_UV_OFFSET_MASK) +#define CAM_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_UV_OFFSET_MASK) >> CAM_CSC_COEF0_UV_OFFSET_SHIFT) + +/* + * Y_OFFSET (RW) + * + * Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is + * typically -16 (0x1F0). + */ +#define CAM_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) +#define CAM_CSC_COEF0_Y_OFFSET_SHIFT (0U) +#define CAM_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_Y_OFFSET_SHIFT) & CAM_CSC_COEF0_Y_OFFSET_MASK) +#define CAM_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_Y_OFFSET_MASK) >> CAM_CSC_COEF0_Y_OFFSET_SHIFT) + +/* Bitfield definition for register: CSC_COEF1 */ +/* + * C1 (RW) + * + * Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + */ +#define CAM_CSC_COEF1_C1_MASK (0x7FF0000UL) +#define CAM_CSC_COEF1_C1_SHIFT (16U) +#define CAM_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << CAM_CSC_COEF1_C1_SHIFT) & CAM_CSC_COEF1_C1_MASK) +#define CAM_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & CAM_CSC_COEF1_C1_MASK) >> CAM_CSC_COEF1_C1_SHIFT) + +/* + * C4 (RW) + * + * Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + */ +#define CAM_CSC_COEF1_C4_MASK (0x7FFU) +#define CAM_CSC_COEF1_C4_SHIFT (0U) +#define CAM_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << CAM_CSC_COEF1_C4_SHIFT) & CAM_CSC_COEF1_C4_MASK) +#define CAM_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & CAM_CSC_COEF1_C4_MASK) >> CAM_CSC_COEF1_C4_SHIFT) + +/* Bitfield definition for register: CSC_COEF2 */ +/* + * C2 (RW) + * + * Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + */ +#define CAM_CSC_COEF2_C2_MASK (0x7FF0000UL) +#define CAM_CSC_COEF2_C2_SHIFT (16U) +#define CAM_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << CAM_CSC_COEF2_C2_SHIFT) & CAM_CSC_COEF2_C2_MASK) +#define CAM_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & CAM_CSC_COEF2_C2_MASK) >> CAM_CSC_COEF2_C2_SHIFT) + +/* + * C3 (RW) + * + * Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + */ +#define CAM_CSC_COEF2_C3_MASK (0x7FFU) +#define CAM_CSC_COEF2_C3_SHIFT (0U) +#define CAM_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << CAM_CSC_COEF2_C3_SHIFT) & CAM_CSC_COEF2_C3_MASK) +#define CAM_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & CAM_CSC_COEF2_C3_MASK) >> CAM_CSC_COEF2_C3_SHIFT) + +/* Bitfield definition for register: CLRKEY_LOW */ +/* + * LIMIT (RW) + * + * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + */ +#define CAM_CLRKEY_LOW_LIMIT_MASK (0xFFFFFFUL) +#define CAM_CLRKEY_LOW_LIMIT_SHIFT (0U) +#define CAM_CLRKEY_LOW_LIMIT_SET(x) (((uint32_t)(x) << CAM_CLRKEY_LOW_LIMIT_SHIFT) & CAM_CLRKEY_LOW_LIMIT_MASK) +#define CAM_CLRKEY_LOW_LIMIT_GET(x) (((uint32_t)(x) & CAM_CLRKEY_LOW_LIMIT_MASK) >> CAM_CLRKEY_LOW_LIMIT_SHIFT) + +/* Bitfield definition for register: CLRKEY_HIGH */ +/* + * LIMIT (RW) + * + * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + */ +#define CAM_CLRKEY_HIGH_LIMIT_MASK (0xFFFFFFUL) +#define CAM_CLRKEY_HIGH_LIMIT_SHIFT (0U) +#define CAM_CLRKEY_HIGH_LIMIT_SET(x) (((uint32_t)(x) << CAM_CLRKEY_HIGH_LIMIT_SHIFT) & CAM_CLRKEY_HIGH_LIMIT_MASK) +#define CAM_CLRKEY_HIGH_LIMIT_GET(x) (((uint32_t)(x) & CAM_CLRKEY_HIGH_LIMIT_MASK) >> CAM_CLRKEY_HIGH_LIMIT_SHIFT) + +/* Bitfield definition for register array: HISTOGRAM_FIFO */ +/* + * HIST_Y (ROI) + * + * the appearance of bin x (x=(address-DATA0)/4) + */ +#define CAM_HISTOGRAM_FIFO_HIST_Y_MASK (0xFFFFFFUL) +#define CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT (0U) +#define CAM_HISTOGRAM_FIFO_HIST_Y_GET(x) (((uint32_t)(x) & CAM_HISTOGRAM_FIFO_HIST_Y_MASK) >> CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT) + + + +/* HISTOGRAM_FIFO register group index macro definition */ +#define CAM_HISTOGRAM_FIFO_DATA0 (0UL) +#define CAM_HISTOGRAM_FIFO_DATA1 (1UL) +#define CAM_HISTOGRAM_FIFO_DATA2 (2UL) +#define CAM_HISTOGRAM_FIFO_DATA3 (3UL) +#define CAM_HISTOGRAM_FIFO_DATA4 (4UL) +#define CAM_HISTOGRAM_FIFO_DATA5 (5UL) +#define CAM_HISTOGRAM_FIFO_DATA6 (6UL) +#define CAM_HISTOGRAM_FIFO_DATA7 (7UL) +#define CAM_HISTOGRAM_FIFO_DATA8 (8UL) +#define CAM_HISTOGRAM_FIFO_DATA9 (9UL) +#define CAM_HISTOGRAM_FIFO_DATA10 (10UL) +#define CAM_HISTOGRAM_FIFO_DATA11 (11UL) +#define CAM_HISTOGRAM_FIFO_DATA12 (12UL) +#define CAM_HISTOGRAM_FIFO_DATA13 (13UL) +#define CAM_HISTOGRAM_FIFO_DATA14 (14UL) +#define CAM_HISTOGRAM_FIFO_DATA15 (15UL) +#define CAM_HISTOGRAM_FIFO_DATA16 (16UL) +#define CAM_HISTOGRAM_FIFO_DATA17 (17UL) +#define CAM_HISTOGRAM_FIFO_DATA18 (18UL) +#define CAM_HISTOGRAM_FIFO_DATA19 (19UL) +#define CAM_HISTOGRAM_FIFO_DATA20 (20UL) +#define CAM_HISTOGRAM_FIFO_DATA21 (21UL) +#define CAM_HISTOGRAM_FIFO_DATA22 (22UL) +#define CAM_HISTOGRAM_FIFO_DATA23 (23UL) +#define CAM_HISTOGRAM_FIFO_DATA24 (24UL) +#define CAM_HISTOGRAM_FIFO_DATA25 (25UL) +#define CAM_HISTOGRAM_FIFO_DATA26 (26UL) +#define CAM_HISTOGRAM_FIFO_DATA27 (27UL) +#define CAM_HISTOGRAM_FIFO_DATA28 (28UL) +#define CAM_HISTOGRAM_FIFO_DATA29 (29UL) +#define CAM_HISTOGRAM_FIFO_DATA30 (30UL) +#define CAM_HISTOGRAM_FIFO_DATA31 (31UL) +#define CAM_HISTOGRAM_FIFO_DATA32 (32UL) +#define CAM_HISTOGRAM_FIFO_DATA33 (33UL) +#define CAM_HISTOGRAM_FIFO_DATA34 (34UL) +#define CAM_HISTOGRAM_FIFO_DATA35 (35UL) +#define CAM_HISTOGRAM_FIFO_DATA36 (36UL) +#define CAM_HISTOGRAM_FIFO_DATA37 (37UL) +#define CAM_HISTOGRAM_FIFO_DATA38 (38UL) +#define CAM_HISTOGRAM_FIFO_DATA39 (39UL) +#define CAM_HISTOGRAM_FIFO_DATA40 (40UL) +#define CAM_HISTOGRAM_FIFO_DATA41 (41UL) +#define CAM_HISTOGRAM_FIFO_DATA42 (42UL) +#define CAM_HISTOGRAM_FIFO_DATA43 (43UL) +#define CAM_HISTOGRAM_FIFO_DATA44 (44UL) +#define CAM_HISTOGRAM_FIFO_DATA45 (45UL) +#define CAM_HISTOGRAM_FIFO_DATA46 (46UL) +#define CAM_HISTOGRAM_FIFO_DATA47 (47UL) +#define CAM_HISTOGRAM_FIFO_DATA48 (48UL) +#define CAM_HISTOGRAM_FIFO_DATA49 (49UL) +#define CAM_HISTOGRAM_FIFO_DATA50 (50UL) +#define CAM_HISTOGRAM_FIFO_DATA51 (51UL) +#define CAM_HISTOGRAM_FIFO_DATA52 (52UL) +#define CAM_HISTOGRAM_FIFO_DATA53 (53UL) +#define CAM_HISTOGRAM_FIFO_DATA54 (54UL) +#define CAM_HISTOGRAM_FIFO_DATA55 (55UL) +#define CAM_HISTOGRAM_FIFO_DATA56 (56UL) +#define CAM_HISTOGRAM_FIFO_DATA57 (57UL) +#define CAM_HISTOGRAM_FIFO_DATA58 (58UL) +#define CAM_HISTOGRAM_FIFO_DATA59 (59UL) +#define CAM_HISTOGRAM_FIFO_DATA60 (60UL) +#define CAM_HISTOGRAM_FIFO_DATA61 (61UL) +#define CAM_HISTOGRAM_FIFO_DATA62 (62UL) +#define CAM_HISTOGRAM_FIFO_DATA63 (63UL) +#define CAM_HISTOGRAM_FIFO_DATA64 (64UL) +#define CAM_HISTOGRAM_FIFO_DATA65 (65UL) +#define CAM_HISTOGRAM_FIFO_DATA66 (66UL) +#define CAM_HISTOGRAM_FIFO_DATA67 (67UL) +#define CAM_HISTOGRAM_FIFO_DATA68 (68UL) +#define CAM_HISTOGRAM_FIFO_DATA69 (69UL) +#define CAM_HISTOGRAM_FIFO_DATA70 (70UL) +#define CAM_HISTOGRAM_FIFO_DATA71 (71UL) +#define CAM_HISTOGRAM_FIFO_DATA72 (72UL) +#define CAM_HISTOGRAM_FIFO_DATA73 (73UL) +#define CAM_HISTOGRAM_FIFO_DATA74 (74UL) +#define CAM_HISTOGRAM_FIFO_DATA75 (75UL) +#define CAM_HISTOGRAM_FIFO_DATA76 (76UL) +#define CAM_HISTOGRAM_FIFO_DATA77 (77UL) +#define CAM_HISTOGRAM_FIFO_DATA78 (78UL) +#define CAM_HISTOGRAM_FIFO_DATA79 (79UL) +#define CAM_HISTOGRAM_FIFO_DATA80 (80UL) +#define CAM_HISTOGRAM_FIFO_DATA81 (81UL) +#define CAM_HISTOGRAM_FIFO_DATA82 (82UL) +#define CAM_HISTOGRAM_FIFO_DATA83 (83UL) +#define CAM_HISTOGRAM_FIFO_DATA84 (84UL) +#define CAM_HISTOGRAM_FIFO_DATA85 (85UL) +#define CAM_HISTOGRAM_FIFO_DATA86 (86UL) +#define CAM_HISTOGRAM_FIFO_DATA87 (87UL) +#define CAM_HISTOGRAM_FIFO_DATA88 (88UL) +#define CAM_HISTOGRAM_FIFO_DATA89 (89UL) +#define CAM_HISTOGRAM_FIFO_DATA90 (90UL) +#define CAM_HISTOGRAM_FIFO_DATA91 (91UL) +#define CAM_HISTOGRAM_FIFO_DATA92 (92UL) +#define CAM_HISTOGRAM_FIFO_DATA93 (93UL) +#define CAM_HISTOGRAM_FIFO_DATA94 (94UL) +#define CAM_HISTOGRAM_FIFO_DATA95 (95UL) +#define CAM_HISTOGRAM_FIFO_DATA96 (96UL) +#define CAM_HISTOGRAM_FIFO_DATA97 (97UL) +#define CAM_HISTOGRAM_FIFO_DATA98 (98UL) +#define CAM_HISTOGRAM_FIFO_DATA99 (99UL) +#define CAM_HISTOGRAM_FIFO_DATA100 (100UL) +#define CAM_HISTOGRAM_FIFO_DATA101 (101UL) +#define CAM_HISTOGRAM_FIFO_DATA102 (102UL) +#define CAM_HISTOGRAM_FIFO_DATA103 (103UL) +#define CAM_HISTOGRAM_FIFO_DATA104 (104UL) +#define CAM_HISTOGRAM_FIFO_DATA105 (105UL) +#define CAM_HISTOGRAM_FIFO_DATA106 (106UL) +#define CAM_HISTOGRAM_FIFO_DATA107 (107UL) +#define CAM_HISTOGRAM_FIFO_DATA108 (108UL) +#define CAM_HISTOGRAM_FIFO_DATA109 (109UL) +#define CAM_HISTOGRAM_FIFO_DATA110 (110UL) +#define CAM_HISTOGRAM_FIFO_DATA111 (111UL) +#define CAM_HISTOGRAM_FIFO_DATA112 (112UL) +#define CAM_HISTOGRAM_FIFO_DATA113 (113UL) +#define CAM_HISTOGRAM_FIFO_DATA114 (114UL) +#define CAM_HISTOGRAM_FIFO_DATA115 (115UL) +#define CAM_HISTOGRAM_FIFO_DATA116 (116UL) +#define CAM_HISTOGRAM_FIFO_DATA117 (117UL) +#define CAM_HISTOGRAM_FIFO_DATA118 (118UL) +#define CAM_HISTOGRAM_FIFO_DATA119 (119UL) +#define CAM_HISTOGRAM_FIFO_DATA120 (120UL) +#define CAM_HISTOGRAM_FIFO_DATA121 (121UL) +#define CAM_HISTOGRAM_FIFO_DATA122 (122UL) +#define CAM_HISTOGRAM_FIFO_DATA123 (123UL) +#define CAM_HISTOGRAM_FIFO_DATA124 (124UL) +#define CAM_HISTOGRAM_FIFO_DATA125 (125UL) +#define CAM_HISTOGRAM_FIFO_DATA126 (126UL) +#define CAM_HISTOGRAM_FIFO_DATA127 (127UL) +#define CAM_HISTOGRAM_FIFO_DATA128 (128UL) +#define CAM_HISTOGRAM_FIFO_DATA129 (129UL) +#define CAM_HISTOGRAM_FIFO_DATA130 (130UL) +#define CAM_HISTOGRAM_FIFO_DATA131 (131UL) +#define CAM_HISTOGRAM_FIFO_DATA132 (132UL) +#define CAM_HISTOGRAM_FIFO_DATA133 (133UL) +#define CAM_HISTOGRAM_FIFO_DATA134 (134UL) +#define CAM_HISTOGRAM_FIFO_DATA135 (135UL) +#define CAM_HISTOGRAM_FIFO_DATA136 (136UL) +#define CAM_HISTOGRAM_FIFO_DATA137 (137UL) +#define CAM_HISTOGRAM_FIFO_DATA138 (138UL) +#define CAM_HISTOGRAM_FIFO_DATA139 (139UL) +#define CAM_HISTOGRAM_FIFO_DATA140 (140UL) +#define CAM_HISTOGRAM_FIFO_DATA141 (141UL) +#define CAM_HISTOGRAM_FIFO_DATA142 (142UL) +#define CAM_HISTOGRAM_FIFO_DATA143 (143UL) +#define CAM_HISTOGRAM_FIFO_DATA144 (144UL) +#define CAM_HISTOGRAM_FIFO_DATA145 (145UL) +#define CAM_HISTOGRAM_FIFO_DATA146 (146UL) +#define CAM_HISTOGRAM_FIFO_DATA147 (147UL) +#define CAM_HISTOGRAM_FIFO_DATA148 (148UL) +#define CAM_HISTOGRAM_FIFO_DATA149 (149UL) +#define CAM_HISTOGRAM_FIFO_DATA150 (150UL) +#define CAM_HISTOGRAM_FIFO_DATA151 (151UL) +#define CAM_HISTOGRAM_FIFO_DATA152 (152UL) +#define CAM_HISTOGRAM_FIFO_DATA153 (153UL) +#define CAM_HISTOGRAM_FIFO_DATA154 (154UL) +#define CAM_HISTOGRAM_FIFO_DATA155 (155UL) +#define CAM_HISTOGRAM_FIFO_DATA156 (156UL) +#define CAM_HISTOGRAM_FIFO_DATA157 (157UL) +#define CAM_HISTOGRAM_FIFO_DATA158 (158UL) +#define CAM_HISTOGRAM_FIFO_DATA159 (159UL) +#define CAM_HISTOGRAM_FIFO_DATA160 (160UL) +#define CAM_HISTOGRAM_FIFO_DATA161 (161UL) +#define CAM_HISTOGRAM_FIFO_DATA162 (162UL) +#define CAM_HISTOGRAM_FIFO_DATA163 (163UL) +#define CAM_HISTOGRAM_FIFO_DATA164 (164UL) +#define CAM_HISTOGRAM_FIFO_DATA165 (165UL) +#define CAM_HISTOGRAM_FIFO_DATA166 (166UL) +#define CAM_HISTOGRAM_FIFO_DATA167 (167UL) +#define CAM_HISTOGRAM_FIFO_DATA168 (168UL) +#define CAM_HISTOGRAM_FIFO_DATA169 (169UL) +#define CAM_HISTOGRAM_FIFO_DATA170 (170UL) +#define CAM_HISTOGRAM_FIFO_DATA171 (171UL) +#define CAM_HISTOGRAM_FIFO_DATA172 (172UL) +#define CAM_HISTOGRAM_FIFO_DATA173 (173UL) +#define CAM_HISTOGRAM_FIFO_DATA174 (174UL) +#define CAM_HISTOGRAM_FIFO_DATA175 (175UL) +#define CAM_HISTOGRAM_FIFO_DATA176 (176UL) +#define CAM_HISTOGRAM_FIFO_DATA177 (177UL) +#define CAM_HISTOGRAM_FIFO_DATA178 (178UL) +#define CAM_HISTOGRAM_FIFO_DATA179 (179UL) +#define CAM_HISTOGRAM_FIFO_DATA180 (180UL) +#define CAM_HISTOGRAM_FIFO_DATA181 (181UL) +#define CAM_HISTOGRAM_FIFO_DATA182 (182UL) +#define CAM_HISTOGRAM_FIFO_DATA183 (183UL) +#define CAM_HISTOGRAM_FIFO_DATA184 (184UL) +#define CAM_HISTOGRAM_FIFO_DATA185 (185UL) +#define CAM_HISTOGRAM_FIFO_DATA186 (186UL) +#define CAM_HISTOGRAM_FIFO_DATA187 (187UL) +#define CAM_HISTOGRAM_FIFO_DATA188 (188UL) +#define CAM_HISTOGRAM_FIFO_DATA189 (189UL) +#define CAM_HISTOGRAM_FIFO_DATA190 (190UL) +#define CAM_HISTOGRAM_FIFO_DATA191 (191UL) +#define CAM_HISTOGRAM_FIFO_DATA192 (192UL) +#define CAM_HISTOGRAM_FIFO_DATA193 (193UL) +#define CAM_HISTOGRAM_FIFO_DATA194 (194UL) +#define CAM_HISTOGRAM_FIFO_DATA195 (195UL) +#define CAM_HISTOGRAM_FIFO_DATA196 (196UL) +#define CAM_HISTOGRAM_FIFO_DATA197 (197UL) +#define CAM_HISTOGRAM_FIFO_DATA198 (198UL) +#define CAM_HISTOGRAM_FIFO_DATA199 (199UL) +#define CAM_HISTOGRAM_FIFO_DATA200 (200UL) +#define CAM_HISTOGRAM_FIFO_DATA201 (201UL) +#define CAM_HISTOGRAM_FIFO_DATA202 (202UL) +#define CAM_HISTOGRAM_FIFO_DATA203 (203UL) +#define CAM_HISTOGRAM_FIFO_DATA204 (204UL) +#define CAM_HISTOGRAM_FIFO_DATA205 (205UL) +#define CAM_HISTOGRAM_FIFO_DATA206 (206UL) +#define CAM_HISTOGRAM_FIFO_DATA207 (207UL) +#define CAM_HISTOGRAM_FIFO_DATA208 (208UL) +#define CAM_HISTOGRAM_FIFO_DATA209 (209UL) +#define CAM_HISTOGRAM_FIFO_DATA210 (210UL) +#define CAM_HISTOGRAM_FIFO_DATA211 (211UL) +#define CAM_HISTOGRAM_FIFO_DATA212 (212UL) +#define CAM_HISTOGRAM_FIFO_DATA213 (213UL) +#define CAM_HISTOGRAM_FIFO_DATA214 (214UL) +#define CAM_HISTOGRAM_FIFO_DATA215 (215UL) +#define CAM_HISTOGRAM_FIFO_DATA216 (216UL) +#define CAM_HISTOGRAM_FIFO_DATA217 (217UL) +#define CAM_HISTOGRAM_FIFO_DATA218 (218UL) +#define CAM_HISTOGRAM_FIFO_DATA219 (219UL) +#define CAM_HISTOGRAM_FIFO_DATA220 (220UL) +#define CAM_HISTOGRAM_FIFO_DATA221 (221UL) +#define CAM_HISTOGRAM_FIFO_DATA222 (222UL) +#define CAM_HISTOGRAM_FIFO_DATA223 (223UL) +#define CAM_HISTOGRAM_FIFO_DATA224 (224UL) +#define CAM_HISTOGRAM_FIFO_DATA225 (225UL) +#define CAM_HISTOGRAM_FIFO_DATA226 (226UL) +#define CAM_HISTOGRAM_FIFO_DATA227 (227UL) +#define CAM_HISTOGRAM_FIFO_DATA228 (228UL) +#define CAM_HISTOGRAM_FIFO_DATA229 (229UL) +#define CAM_HISTOGRAM_FIFO_DATA230 (230UL) +#define CAM_HISTOGRAM_FIFO_DATA231 (231UL) +#define CAM_HISTOGRAM_FIFO_DATA232 (232UL) +#define CAM_HISTOGRAM_FIFO_DATA233 (233UL) +#define CAM_HISTOGRAM_FIFO_DATA234 (234UL) +#define CAM_HISTOGRAM_FIFO_DATA235 (235UL) +#define CAM_HISTOGRAM_FIFO_DATA236 (236UL) +#define CAM_HISTOGRAM_FIFO_DATA237 (237UL) +#define CAM_HISTOGRAM_FIFO_DATA238 (238UL) +#define CAM_HISTOGRAM_FIFO_DATA239 (239UL) +#define CAM_HISTOGRAM_FIFO_DATA240 (240UL) +#define CAM_HISTOGRAM_FIFO_DATA241 (241UL) +#define CAM_HISTOGRAM_FIFO_DATA242 (242UL) +#define CAM_HISTOGRAM_FIFO_DATA243 (243UL) +#define CAM_HISTOGRAM_FIFO_DATA244 (244UL) +#define CAM_HISTOGRAM_FIFO_DATA245 (245UL) +#define CAM_HISTOGRAM_FIFO_DATA246 (246UL) +#define CAM_HISTOGRAM_FIFO_DATA247 (247UL) +#define CAM_HISTOGRAM_FIFO_DATA248 (248UL) +#define CAM_HISTOGRAM_FIFO_DATA249 (249UL) +#define CAM_HISTOGRAM_FIFO_DATA250 (250UL) +#define CAM_HISTOGRAM_FIFO_DATA251 (251UL) +#define CAM_HISTOGRAM_FIFO_DATA252 (252UL) +#define CAM_HISTOGRAM_FIFO_DATA253 (253UL) +#define CAM_HISTOGRAM_FIFO_DATA254 (254UL) +#define CAM_HISTOGRAM_FIFO_DATA255 (255UL) + + +#endif /* HPM_CAM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_can_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_can_regs.h new file mode 100644 index 0000000000..7395c8d908 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_can_regs.h @@ -0,0 +1,1402 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CAN_H +#define HPM_CAN_H + +typedef struct { + __RW uint32_t RBUF[20]; /* 0x0 - 0x4C: receive buffer registers and reception time stamp */ + __RW uint32_t TBUF[18]; /* 0x50 - 0x94: transmit buffer register */ + __R uint32_t TTS[2]; /* 0x98 - 0x9C: transmission time stamp, LSB 32bit */ + __RW uint32_t CMD_STA_CMD_CTRL; /* 0xA0: config, status, command and control bits */ + __RW uint8_t RTIE; /* 0xA4: Receive and Transmit Interrupt Enable Register RTIE */ + __W uint8_t RTIF; /* 0xA5: Receive and Transmit Interrupt Flag Register RTIF (0xa5) */ + __RW uint8_t ERRINT; /* 0xA6: ERRor INTerrupt Enable and Flag Register ERRINT */ + __RW uint8_t LIMIT; /* 0xA7: Warning Limits Register LIMIT */ + __RW uint32_t S_PRESC; /* 0xA8: Bit Timing Register(Slow Speed) */ + __RW uint32_t F_PRESC; /* 0xAC: Bit Timing Register(Fast Speed) */ + __R uint8_t EALCAP; /* 0xB0: Error and Arbitration Lost Capture Register EALCAP */ + __RW uint8_t TDC; /* 0xB1: Transmitter Delay Compensation Register TDC */ + __R uint8_t RECNT; /* 0xB2: Error Counter Registers RECNT */ + __R uint8_t TECNT; /* 0xB3: Error Counter Registers TECNT */ + __RW uint8_t ACFCTRL; /* 0xB4: Acceptance Filter Control Register ACFCTRL */ + __RW uint8_t TIMECFG; /* 0xB5: CiA 603 Time-Stamping TIMECFG */ + __RW uint16_t ACF_EN; /* 0xB6: Acceptance Filter Enable ACF_EN */ + __RW uint32_t ACF; /* 0xB8: Acceptance CODE ACODE or ACMASK */ + __RW uint16_t VER; /* 0xBC: Version Information VER */ + __RW uint8_t TBSLOT; /* 0xBE: TTCAN: TB Slot Pointer TBSLOT */ + __RW uint8_t TTCFG; /* 0xBF: TTCAN: Time Trigger Configuration TTCFG */ + __RW uint32_t REF_MSG; /* 0xC0: TTCAN: Reference Message REF_MSG */ + __RW uint16_t TRIG_CFG; /* 0xC4: TTCAN: Trigger Configuration TRIG_CFG */ + __RW uint16_t TT_TRIG; /* 0xC6: TTCAN: Trigger Time TT_TRIG */ + __RW uint16_t TT_WTRIG; /* 0xC8: TTCAN: Watch Trigger Time TT_WTRIG */ +} CAN_Type; + + +/* Bitfield definition for register array: RBUF */ +/* + * RBUF (RW) + * + * receive buffer + */ +#define CAN_RBUF_RBUF_MASK (0xFFFFFFFFUL) +#define CAN_RBUF_RBUF_SHIFT (0U) +#define CAN_RBUF_RBUF_SET(x) (((uint32_t)(x) << CAN_RBUF_RBUF_SHIFT) & CAN_RBUF_RBUF_MASK) +#define CAN_RBUF_RBUF_GET(x) (((uint32_t)(x) & CAN_RBUF_RBUF_MASK) >> CAN_RBUF_RBUF_SHIFT) + +/* Bitfield definition for register array: TBUF */ +/* + * TBUF (RW) + * + * transmit buffer + */ +#define CAN_TBUF_TBUF_MASK (0xFFFFFFFFUL) +#define CAN_TBUF_TBUF_SHIFT (0U) +#define CAN_TBUF_TBUF_SET(x) (((uint32_t)(x) << CAN_TBUF_TBUF_SHIFT) & CAN_TBUF_TBUF_MASK) +#define CAN_TBUF_TBUF_GET(x) (((uint32_t)(x) & CAN_TBUF_TBUF_MASK) >> CAN_TBUF_TBUF_SHIFT) + +/* Bitfield definition for register array: TTS */ +/* + * TTS_WRD0 (RO) + * + * transmission time stamp, word 0, LSB 32bit + */ +#define CAN_TTS_TTS_WRD0_MASK (0xFFFFFFFFUL) +#define CAN_TTS_TTS_WRD0_SHIFT (0U) +#define CAN_TTS_TTS_WRD0_GET(x) (((uint32_t)(x) & CAN_TTS_TTS_WRD0_MASK) >> CAN_TTS_TTS_WRD0_SHIFT) + +/* Bitfield definition for register: CMD_STA_CMD_CTRL */ +/* + * SACK (RW) + * + * Self-ACKnowledge + * 0 – no self-ACK + * 1 – self-ACK when LBME=1 + */ +#define CAN_CMD_STA_CMD_CTRL_SACK_MASK (0x80000000UL) +#define CAN_CMD_STA_CMD_CTRL_SACK_SHIFT (31U) +#define CAN_CMD_STA_CMD_CTRL_SACK_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_SACK_SHIFT) & CAN_CMD_STA_CMD_CTRL_SACK_MASK) +#define CAN_CMD_STA_CMD_CTRL_SACK_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_SACK_MASK) >> CAN_CMD_STA_CMD_CTRL_SACK_SHIFT) + +/* + * ROM (RW) + * + * Receive buffer Overflow Mode + * In case of a full RBUF when a new message is received, then ROM selects the following: + * 1 – The new message will not be stored. + * 0 – The oldest message will be overwritten. + */ +#define CAN_CMD_STA_CMD_CTRL_ROM_MASK (0x40000000UL) +#define CAN_CMD_STA_CMD_CTRL_ROM_SHIFT (30U) +#define CAN_CMD_STA_CMD_CTRL_ROM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_ROM_SHIFT) & CAN_CMD_STA_CMD_CTRL_ROM_MASK) +#define CAN_CMD_STA_CMD_CTRL_ROM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_ROM_MASK) >> CAN_CMD_STA_CMD_CTRL_ROM_SHIFT) + +/* + * ROV (RO) + * + * Receive buffer OVerflow + * 1 – Overflow. At least one message is lost. + * 0 – No Overflow. + * ROV is cleared by setting RREL=1. + */ +#define CAN_CMD_STA_CMD_CTRL_ROV_MASK (0x20000000UL) +#define CAN_CMD_STA_CMD_CTRL_ROV_SHIFT (29U) +#define CAN_CMD_STA_CMD_CTRL_ROV_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_ROV_MASK) >> CAN_CMD_STA_CMD_CTRL_ROV_SHIFT) + +/* + * RREL (RW) + * + * Receive buffer RELease + * The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL + * core points to the next RB slot. RSTAT gets updated. + * 1 – Release: The host has read the RB. + * 0 – No release + */ +#define CAN_CMD_STA_CMD_CTRL_RREL_MASK (0x10000000UL) +#define CAN_CMD_STA_CMD_CTRL_RREL_SHIFT (28U) +#define CAN_CMD_STA_CMD_CTRL_RREL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RREL_SHIFT) & CAN_CMD_STA_CMD_CTRL_RREL_MASK) +#define CAN_CMD_STA_CMD_CTRL_RREL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RREL_MASK) >> CAN_CMD_STA_CMD_CTRL_RREL_SHIFT) + +/* + * RBALL (RW) + * + * Receive Buffer stores ALL data frames + * 0 – normal operation + * 1 – RB stores correct data frames as well as data frames with error + */ +#define CAN_CMD_STA_CMD_CTRL_RBALL_MASK (0x8000000UL) +#define CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT (27U) +#define CAN_CMD_STA_CMD_CTRL_RBALL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT) & CAN_CMD_STA_CMD_CTRL_RBALL_MASK) +#define CAN_CMD_STA_CMD_CTRL_RBALL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RBALL_MASK) >> CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT) + +/* + * RSTAT (RO) + * + * Receive buffer STATus + * 00 - empty + * 01 - > empty and < almost full (AFWL) + * 10 -  almost full (programmable threshold by AFWL) but not full and no overflow + * 11 - full (stays set in case of overflow – for overflow signaling see ROV) + */ +#define CAN_CMD_STA_CMD_CTRL_RSTAT_MASK (0x3000000UL) +#define CAN_CMD_STA_CMD_CTRL_RSTAT_SHIFT (24U) +#define CAN_CMD_STA_CMD_CTRL_RSTAT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RSTAT_MASK) >> CAN_CMD_STA_CMD_CTRL_RSTAT_SHIFT) + +/* + * FD_ISO (RW) + * + * CAN FD ISO mode + * 0 - Bosch CAN FD (non-ISO) mode + * 1 - ISO CAN FD mode (ISO 11898-1:2015) + * ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. + * Both modes are incompatible and must not be mixed in one CAN network. + * This bit has no impact to CAN 2.0B. + * This bit is only writeable if RESET=1. + */ +#define CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK (0x800000UL) +#define CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT (23U) +#define CAN_CMD_STA_CMD_CTRL_FD_ISO_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT) & CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK) +#define CAN_CMD_STA_CMD_CTRL_FD_ISO_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK) >> CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT) + +/* + * TSNEXT (RW) + * + * Transmit buffer Secondary NEXT + * 0 - no action + * 1 - STB slot filled, select next slot. + * After all frame bytes are written to the TBUF registers, the host controller has to set + * TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF + * registers to the next slot. Once a slot is marked as filled a transmission can be started + * using TSONE or TSALL. + * It is possible to set TSNEXT and TSONE or TSALL together in one write access. + * TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL + * core immediately after it was set. + * Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and + * automatically cleared. It does not do any harm. + * If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. + * TSNEXT has no meaning in TTCAN mode and is fixed to 0. + */ +#define CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK (0x400000UL) +#define CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT (22U) +#define CAN_CMD_STA_CMD_CTRL_TSNEXT_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK) +#define CAN_CMD_STA_CMD_CTRL_TSNEXT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK) >> CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT) + +/* + * TSMODE (RW) + * + * Transmit buffer Secondary operation MODE + * 0 - FIFO mode + * 1 - priority decision mode + * In FIFO mode frames are transmitted in the order in that they are written into the STB. + * In priority decision mode the frame with the highest priority in the STB is automatically + * transmitted first. The ID of a frame is used for the priority decision. A lower ID means a + * higher priority of a frame. A frame in the PTB has always the highest priority regardless of + * the ID. + * TSMODE shall be switched only if the STB if empty + */ +#define CAN_CMD_STA_CMD_CTRL_TSMODE_MASK (0x200000UL) +#define CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT (21U) +#define CAN_CMD_STA_CMD_CTRL_TSMODE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSMODE_MASK) +#define CAN_CMD_STA_CMD_CTRL_TSMODE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSMODE_MASK) >> CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT) + +/* + * TTTBM (RW) + * + * TTCAN Transmit Buffer Mode + * If TTEN=0 then TTTBM is ignored, otherwise the following is valid: + * 0 - separate PTB and STB, behavior defined by TSMODE + * 1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR + * For event-driven CAN communication (TTEN=0), the system provides PTB and STB and + * the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. + * For time-triggered CAN communication (TTEN=1) with full support of all features including + * time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are + * addressable using TTPTR and TBPTR. + * For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode + * and the behavior can be selected by TSMODE. + * TTTBM shall be switched only if the TBUF is empty. + */ +#define CAN_CMD_STA_CMD_CTRL_TTTBM_MASK (0x100000UL) +#define CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT (20U) +#define CAN_CMD_STA_CMD_CTRL_TTTBM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT) & CAN_CMD_STA_CMD_CTRL_TTTBM_MASK) +#define CAN_CMD_STA_CMD_CTRL_TTTBM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TTTBM_MASK) >> CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT) + +/* + * TSSTAT (RO) + * + * Transmission Secondary STATus bits + * If TTEN=0 or TTTBM=0: + * 00 – STB is empty + * 01 – STB is less than or equal to half full + * 10 – STB is more than half full + * 11 – STB is full + * If the STB is disabled using STB_DISABLE, then TSSTAT=00. + * If TTEN=1 and TTTBM=1: + * 00 – PTB and STB are empty + * 01 – PTB and STB are not empty and not full + * 11 – PTB and STB are full + */ +#define CAN_CMD_STA_CMD_CTRL_TSSTAT_MASK (0x30000UL) +#define CAN_CMD_STA_CMD_CTRL_TSSTAT_SHIFT (16U) +#define CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSSTAT_MASK) >> CAN_CMD_STA_CMD_CTRL_TSSTAT_SHIFT) + +/* + * TBSEL (RW) + * + * Transmit Buffer Select + * Selects the transmit buffer to be loaded with a message. Use the TBUF registers for + * access. TBSEL needs to be stable all the time the TBUF registers are written and when + * TSNEXT is set. + * 0 - PTB (high-priority buffer) + * 1 - STB + * The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) + */ +#define CAN_CMD_STA_CMD_CTRL_TBSEL_MASK (0x8000U) +#define CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT (15U) +#define CAN_CMD_STA_CMD_CTRL_TBSEL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT) & CAN_CMD_STA_CMD_CTRL_TBSEL_MASK) +#define CAN_CMD_STA_CMD_CTRL_TBSEL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TBSEL_MASK) >> CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT) + +/* + * LOM (RW) + * + * Listen Only Mode + * 0 - Disabled + * 1 - Enabled + * LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM + * is enabled and LBME is disabled. + * LOM=1 and LBME=0 disables all transmissions. + * LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables + * the transmission of own frames. + */ +#define CAN_CMD_STA_CMD_CTRL_LOM_MASK (0x4000U) +#define CAN_CMD_STA_CMD_CTRL_LOM_SHIFT (14U) +#define CAN_CMD_STA_CMD_CTRL_LOM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LOM_SHIFT) & CAN_CMD_STA_CMD_CTRL_LOM_MASK) +#define CAN_CMD_STA_CMD_CTRL_LOM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LOM_MASK) >> CAN_CMD_STA_CMD_CTRL_LOM_SHIFT) + +/* + * STBY (RW) + * + * Transceiver Standby Mode + * 0 - Disabled + * 1 - Enabled + * This register bit is connected to the output signal stby which can be used to control a + * standby mode of a transceiver. + * STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. + * If the host sets STBY to 0 then the host needs to wait for the time required by the + * transceiver to start up before the host requests a new transmission. + */ +#define CAN_CMD_STA_CMD_CTRL_STBY_MASK (0x2000U) +#define CAN_CMD_STA_CMD_CTRL_STBY_SHIFT (13U) +#define CAN_CMD_STA_CMD_CTRL_STBY_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_STBY_SHIFT) & CAN_CMD_STA_CMD_CTRL_STBY_MASK) +#define CAN_CMD_STA_CMD_CTRL_STBY_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_STBY_MASK) >> CAN_CMD_STA_CMD_CTRL_STBY_SHIFT) + +/* + * TPE (RW) + * + * Transmit Primary Enable + * 1 - Transmission enable for the message in the high-priority PTB + * 0 - No transmission for the PTB + * If TPE is set, the message from the PTB will be transmitted at the next possible transmit + * position. A started transmission from the STB will be completed before, but pending new + * messages are delayed until the PTB message has been transmitted. + * TPE stays set until the message has been transmitted successfully or it is aborted using + * TPA. + * The host controller can set TPE to 1 but can not reset it to 0. This would only be possible + * using TPA and aborting the message. + * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and + * LBME=0) or (TTEN=1 and TTTBM=1). + */ +#define CAN_CMD_STA_CMD_CTRL_TPE_MASK (0x1000U) +#define CAN_CMD_STA_CMD_CTRL_TPE_SHIFT (12U) +#define CAN_CMD_STA_CMD_CTRL_TPE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPE_MASK) +#define CAN_CMD_STA_CMD_CTRL_TPE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPE_MASK) >> CAN_CMD_STA_CMD_CTRL_TPE_SHIFT) + +/* + * TPA (RW) + * + * Transmit Primary Abort + * 1 – Aborts a transmission from PTB which has been requested by TPE=1 but not + * started yet. (The data bytes of the message remains in the PTB.) + * 0 – no abort + * The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA + * automatically de-asserts TPE. + * The host controller can set TPA to 1 but can not reset it to 0. + * During the short time while the CAN-CTRL core resets the bit, it cannot be set by the + * host. + * The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). + * TPA should not be set simultaneously with TPE. + */ +#define CAN_CMD_STA_CMD_CTRL_TPA_MASK (0x800U) +#define CAN_CMD_STA_CMD_CTRL_TPA_SHIFT (11U) +#define CAN_CMD_STA_CMD_CTRL_TPA_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPA_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPA_MASK) +#define CAN_CMD_STA_CMD_CTRL_TPA_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPA_MASK) >> CAN_CMD_STA_CMD_CTRL_TPA_SHIFT) + +/* + * TSONE (RW) + * + * Transmit Secondary ONE frame + * 1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message + * and in priority mode this is the one with the highest priority. + * TSONE in priority mode is difficult to handle, because it is not always clear which + * message will be transmitted if new messages are written to the STB meanwhile. + * The controller starts the transmission as soon as the bus becomes vacant and + * no request of the PTB (bit TPE) is pending. + * 0 – No transmission for the STB. + * TSONE stays set until the message has been transmitted successfully or it is aborted + * using TSA. + * The host controller can set TSONE to 1 but can not reset it to 0. This would only be + * possible using TSA and aborting the message. + * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and + * LBME=0) or (TTEN=1 and TTTBM=1). + */ +#define CAN_CMD_STA_CMD_CTRL_TSONE_MASK (0x400U) +#define CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT (10U) +#define CAN_CMD_STA_CMD_CTRL_TSONE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSONE_MASK) +#define CAN_CMD_STA_CMD_CTRL_TSONE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSONE_MASK) >> CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT) + +/* + * TSALL (RW) + * + * Transmit Secondary ALL frames + * 1 – Transmission enable of all messages in the STB. + * The controller starts the transmission as soon as the bus becomes vacant and + * no request of the PTB (bit TPE) is pending. + * 0 – No transmission for the STB. + * TSALL stays set until all messages have been transmitted successfully or they are aborted + * using TSA. + * The host controller can set TSALL to 1 but can not reset it to 0. This would only be + * possible using TSA and aborting the messages. + * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and + * LBME=0) or (TTEN=1 and TTTBM=1). + * If during a transmission the STB is loaded with a new frame then the new frame will be + * transmitted too. In other words: a transmission initiated by TSALL is finished when the + * STB becomes empty. + */ +#define CAN_CMD_STA_CMD_CTRL_TSALL_MASK (0x200U) +#define CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT (9U) +#define CAN_CMD_STA_CMD_CTRL_TSALL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSALL_MASK) +#define CAN_CMD_STA_CMD_CTRL_TSALL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSALL_MASK) >> CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT) + +/* + * TSA (RW) + * + * Transmit Secondary Abort + * 1 – Aborts a transmission from STB which has been requested but not started yet. + * For a TSONE transmission, only one frame is aborted while for a TSALL + * Transmission, all frames are aborted. + * One or all message slots will be released which updates TSSTAT. + * All aborted messages are lost because they are not accessible any more. + * If in priority mode a TSONE transmission is aborted, then it is not clear which + * frame will be aborted if new frames are written to the STB meanwhile. + * 0 – no abort + * The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. + * The host controller can set TSA to 1 but can not reset it to 0. + * The bit will be reset to the hardware reset value if RESET=1. + * TSA should not be set simultaneously with TSONE or TSALL. + */ +#define CAN_CMD_STA_CMD_CTRL_TSA_MASK (0x100U) +#define CAN_CMD_STA_CMD_CTRL_TSA_SHIFT (8U) +#define CAN_CMD_STA_CMD_CTRL_TSA_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSA_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSA_MASK) +#define CAN_CMD_STA_CMD_CTRL_TSA_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSA_MASK) >> CAN_CMD_STA_CMD_CTRL_TSA_SHIFT) + +/* + * RESET (RW) + * + * RESET request bit + * 1 - The host controller performs a local reset of CAN-CTRL. + * 0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. + * Bit RESET forces several components to a reset state. + * RESET is automatically set if the node enters “bus off” state. + * Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. + * This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. + * The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. + */ +#define CAN_CMD_STA_CMD_CTRL_RESET_MASK (0x80U) +#define CAN_CMD_STA_CMD_CTRL_RESET_SHIFT (7U) +#define CAN_CMD_STA_CMD_CTRL_RESET_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RESET_SHIFT) & CAN_CMD_STA_CMD_CTRL_RESET_MASK) +#define CAN_CMD_STA_CMD_CTRL_RESET_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RESET_MASK) >> CAN_CMD_STA_CMD_CTRL_RESET_SHIFT) + +/* + * LBME (RW) + * + * Loop Back Mode, External + * 0 - Disabled + * 1 - EnabledLBME should not be enabled while a transmission is active + */ +#define CAN_CMD_STA_CMD_CTRL_LBME_MASK (0x40U) +#define CAN_CMD_STA_CMD_CTRL_LBME_SHIFT (6U) +#define CAN_CMD_STA_CMD_CTRL_LBME_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LBME_SHIFT) & CAN_CMD_STA_CMD_CTRL_LBME_MASK) +#define CAN_CMD_STA_CMD_CTRL_LBME_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LBME_MASK) >> CAN_CMD_STA_CMD_CTRL_LBME_SHIFT) + +/* + * LBMI (RW) + * + * Loop Back Mode, Internal + * 0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. + */ +#define CAN_CMD_STA_CMD_CTRL_LBMI_MASK (0x20U) +#define CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT (5U) +#define CAN_CMD_STA_CMD_CTRL_LBMI_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT) & CAN_CMD_STA_CMD_CTRL_LBMI_MASK) +#define CAN_CMD_STA_CMD_CTRL_LBMI_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LBMI_MASK) >> CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT) + +/* + * TPSS (RW) + * + * Transmission Primary Single Shot mode for PTB + * 0 - Disabled + * 1 - Enabled + */ +#define CAN_CMD_STA_CMD_CTRL_TPSS_MASK (0x10U) +#define CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT (4U) +#define CAN_CMD_STA_CMD_CTRL_TPSS_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) +#define CAN_CMD_STA_CMD_CTRL_TPSS_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) >> CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT) + +/* + * TSSS (RW) + * + * Transmission Secondary Single Shot mode for STB + * 0 - Disabled + * 1 - Enabled + */ +#define CAN_CMD_STA_CMD_CTRL_TSSS_MASK (0x8U) +#define CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT (3U) +#define CAN_CMD_STA_CMD_CTRL_TSSS_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) +#define CAN_CMD_STA_CMD_CTRL_TSSS_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) >> CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT) + +/* + * RACTIVE (RO) + * + * Reception ACTIVE (Receive Status bit) + * 1 - The controller is currently receiving a frame. + * 0 - No receive activity. + */ +#define CAN_CMD_STA_CMD_CTRL_RACTIVE_MASK (0x4U) +#define CAN_CMD_STA_CMD_CTRL_RACTIVE_SHIFT (2U) +#define CAN_CMD_STA_CMD_CTRL_RACTIVE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RACTIVE_MASK) >> CAN_CMD_STA_CMD_CTRL_RACTIVE_SHIFT) + +/* + * TACTIVE (RO) + * + * Transmission ACTIVE (Transmit Status bit) + * 1 - The controller is currently transmitting a frame. + * 0 - No transmit activity. + */ +#define CAN_CMD_STA_CMD_CTRL_TACTIVE_MASK (0x2U) +#define CAN_CMD_STA_CMD_CTRL_TACTIVE_SHIFT (1U) +#define CAN_CMD_STA_CMD_CTRL_TACTIVE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TACTIVE_MASK) >> CAN_CMD_STA_CMD_CTRL_TACTIVE_SHIFT) + +/* + * BUSOFF (RW) + * + * Bus Off (Bus Status bit) + * 1 - The controller status is “bus off”. + * 0 - The controller status is “bus on”. + * Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. + * See Chapter 3.9.10.6 for details. + */ +#define CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK (0x1U) +#define CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT (0U) +#define CAN_CMD_STA_CMD_CTRL_BUSOFF_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT) & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) +#define CAN_CMD_STA_CMD_CTRL_BUSOFF_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) >> CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT) + +/* Bitfield definition for register: RTIE */ +/* + * RIE (RW) + * + * Receive Interrupt Enable + * 0 – Disabled, 1 – Enabled + */ +#define CAN_RTIE_RIE_MASK (0x80U) +#define CAN_RTIE_RIE_SHIFT (7U) +#define CAN_RTIE_RIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RIE_SHIFT) & CAN_RTIE_RIE_MASK) +#define CAN_RTIE_RIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RIE_MASK) >> CAN_RTIE_RIE_SHIFT) + +/* + * ROIE (RW) + * + * RB Overrun Interrupt Enable + * 0 – Disabled, 1 – Enabled + */ +#define CAN_RTIE_ROIE_MASK (0x40U) +#define CAN_RTIE_ROIE_SHIFT (6U) +#define CAN_RTIE_ROIE_SET(x) (((uint8_t)(x) << CAN_RTIE_ROIE_SHIFT) & CAN_RTIE_ROIE_MASK) +#define CAN_RTIE_ROIE_GET(x) (((uint8_t)(x) & CAN_RTIE_ROIE_MASK) >> CAN_RTIE_ROIE_SHIFT) + +/* + * RFIE (RW) + * + * RB Full Interrupt Enable + * 0 – Disabled, 1 – Enabled + */ +#define CAN_RTIE_RFIE_MASK (0x20U) +#define CAN_RTIE_RFIE_SHIFT (5U) +#define CAN_RTIE_RFIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RFIE_SHIFT) & CAN_RTIE_RFIE_MASK) +#define CAN_RTIE_RFIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RFIE_MASK) >> CAN_RTIE_RFIE_SHIFT) + +/* + * RAFIE (RW) + * + * RB Almost Full Interrupt Enable + * 0 – Disabled, 1 – Enabled + */ +#define CAN_RTIE_RAFIE_MASK (0x10U) +#define CAN_RTIE_RAFIE_SHIFT (4U) +#define CAN_RTIE_RAFIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RAFIE_SHIFT) & CAN_RTIE_RAFIE_MASK) +#define CAN_RTIE_RAFIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RAFIE_MASK) >> CAN_RTIE_RAFIE_SHIFT) + +/* + * TPIE (RW) + * + * Transmission Primary Interrupt Enable + * 0 – Disabled, 1 – Enabled + */ +#define CAN_RTIE_TPIE_MASK (0x8U) +#define CAN_RTIE_TPIE_SHIFT (3U) +#define CAN_RTIE_TPIE_SET(x) (((uint8_t)(x) << CAN_RTIE_TPIE_SHIFT) & CAN_RTIE_TPIE_MASK) +#define CAN_RTIE_TPIE_GET(x) (((uint8_t)(x) & CAN_RTIE_TPIE_MASK) >> CAN_RTIE_TPIE_SHIFT) + +/* + * TSIE (RW) + * + * Transmission Secondary Interrupt Enable + * 0 – Disabled, 1 – Enabled + */ +#define CAN_RTIE_TSIE_MASK (0x4U) +#define CAN_RTIE_TSIE_SHIFT (2U) +#define CAN_RTIE_TSIE_SET(x) (((uint8_t)(x) << CAN_RTIE_TSIE_SHIFT) & CAN_RTIE_TSIE_MASK) +#define CAN_RTIE_TSIE_GET(x) (((uint8_t)(x) & CAN_RTIE_TSIE_MASK) >> CAN_RTIE_TSIE_SHIFT) + +/* + * EIE (RW) + * + * Error Interrupt Enable + * 0 – Disabled, 1 – Enabled + */ +#define CAN_RTIE_EIE_MASK (0x2U) +#define CAN_RTIE_EIE_SHIFT (1U) +#define CAN_RTIE_EIE_SET(x) (((uint8_t)(x) << CAN_RTIE_EIE_SHIFT) & CAN_RTIE_EIE_MASK) +#define CAN_RTIE_EIE_GET(x) (((uint8_t)(x) & CAN_RTIE_EIE_MASK) >> CAN_RTIE_EIE_SHIFT) + +/* + * TSFF (RO) + * + * If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag + * 1 - The STB is filled with the maximal number of messages. + * 0 - The STB is not filled with the maximal number of messages. + * If the STB is disabled using STB_DISABLE, then TSFF=0. + * If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag + * 1 - The buffer slot selected by TBPTR is filled. + * 0 - The buffer slot selected by TBPTR is empty. + */ +#define CAN_RTIE_TSFF_MASK (0x1U) +#define CAN_RTIE_TSFF_SHIFT (0U) +#define CAN_RTIE_TSFF_GET(x) (((uint8_t)(x) & CAN_RTIE_TSFF_MASK) >> CAN_RTIE_TSFF_SHIFT) + +/* Bitfield definition for register: RTIF */ +/* + * RIF (W1C) + * + * Receive Interrupt Flag + * 1 - Data or a remote frame has been received and is available in the receive buffer. + * 0 - No frame has been received. + */ +#define CAN_RTIF_RIF_MASK (0x80U) +#define CAN_RTIF_RIF_SHIFT (7U) +#define CAN_RTIF_RIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RIF_SHIFT) & CAN_RTIF_RIF_MASK) +#define CAN_RTIF_RIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RIF_MASK) >> CAN_RTIF_RIF_SHIFT) + +/* + * ROIF (W1C) + * + * RB Overrun Interrupt Flag + * 1 - At least one received message has been overwritten in the RB. + * 0 - No RB overwritten. + * In case of an overrun both ROIF and RFIF will be set. + */ +#define CAN_RTIF_ROIF_MASK (0x40U) +#define CAN_RTIF_ROIF_SHIFT (6U) +#define CAN_RTIF_ROIF_SET(x) (((uint8_t)(x) << CAN_RTIF_ROIF_SHIFT) & CAN_RTIF_ROIF_MASK) +#define CAN_RTIF_ROIF_GET(x) (((uint8_t)(x) & CAN_RTIF_ROIF_MASK) >> CAN_RTIF_ROIF_SHIFT) + +/* + * RFIF (W1C) + * + * RB Full Interrupt Flag + * 1 - All RBs are full. If no RB will be released until the next valid message is received, + * the oldest message will be lost. + * 0 - The RB FIFO is not full. + */ +#define CAN_RTIF_RFIF_MASK (0x20U) +#define CAN_RTIF_RFIF_SHIFT (5U) +#define CAN_RTIF_RFIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RFIF_SHIFT) & CAN_RTIF_RFIF_MASK) +#define CAN_RTIF_RFIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RFIF_MASK) >> CAN_RTIF_RFIF_SHIFT) + +/* + * RAFIF (W1C) + * + * RB Almost Full Interrupt Flag + * 1 - number of filled RB slots >= AFWL_i + * 0 - number of filled RB slots < AFWL_i + */ +#define CAN_RTIF_RAFIF_MASK (0x10U) +#define CAN_RTIF_RAFIF_SHIFT (4U) +#define CAN_RTIF_RAFIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RAFIF_SHIFT) & CAN_RTIF_RAFIF_MASK) +#define CAN_RTIF_RAFIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RAFIF_MASK) >> CAN_RTIF_RAFIF_SHIFT) + +/* + * TPIF (W1C) + * + * Transmission Primary Interrupt Flag + * 1 - The requested transmission of the PTB has been successfully completed. + * 0 - No transmission of the PTB has been completed. + * In TTCAN mode, TPIF will never be set. Then only TSIF is valid. + */ +#define CAN_RTIF_TPIF_MASK (0x8U) +#define CAN_RTIF_TPIF_SHIFT (3U) +#define CAN_RTIF_TPIF_SET(x) (((uint8_t)(x) << CAN_RTIF_TPIF_SHIFT) & CAN_RTIF_TPIF_MASK) +#define CAN_RTIF_TPIF_GET(x) (((uint8_t)(x) & CAN_RTIF_TPIF_MASK) >> CAN_RTIF_TPIF_SHIFT) + +/* + * TSIF (W1C) + * + * Transmission Secondary Interrupt Flag + * 1 - The requested transmission of the STB has been successfully completed. + * 0 - No transmission of the STB has been completed successfully. + * In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of + * the message. + */ +#define CAN_RTIF_TSIF_MASK (0x4U) +#define CAN_RTIF_TSIF_SHIFT (2U) +#define CAN_RTIF_TSIF_SET(x) (((uint8_t)(x) << CAN_RTIF_TSIF_SHIFT) & CAN_RTIF_TSIF_MASK) +#define CAN_RTIF_TSIF_GET(x) (((uint8_t)(x) & CAN_RTIF_TSIF_MASK) >> CAN_RTIF_TSIF_SHIFT) + +/* + * EIF (W1C) + * + * Error Interrupt Flag + * 1 - The border of the error warning limit has been crossed in either direction, + * or the BUSOFF bit has been changed in either direction. + * 0 - There has been no change. + */ +#define CAN_RTIF_EIF_MASK (0x2U) +#define CAN_RTIF_EIF_SHIFT (1U) +#define CAN_RTIF_EIF_SET(x) (((uint8_t)(x) << CAN_RTIF_EIF_SHIFT) & CAN_RTIF_EIF_MASK) +#define CAN_RTIF_EIF_GET(x) (((uint8_t)(x) & CAN_RTIF_EIF_MASK) >> CAN_RTIF_EIF_SHIFT) + +/* + * AIF (W1C) + * + * Abort Interrupt Flag + * 1 - After setting TPA or TSA the appropriated message(s) have been aborted. + * It is recommended to not set both TPA and TSA simultaneously because both + * source AIF. + * 0 - No abort has been executed. + * The AIF does not have an associated enable register. + */ +#define CAN_RTIF_AIF_MASK (0x1U) +#define CAN_RTIF_AIF_SHIFT (0U) +#define CAN_RTIF_AIF_SET(x) (((uint8_t)(x) << CAN_RTIF_AIF_SHIFT) & CAN_RTIF_AIF_MASK) +#define CAN_RTIF_AIF_GET(x) (((uint8_t)(x) & CAN_RTIF_AIF_MASK) >> CAN_RTIF_AIF_SHIFT) + +/* Bitfield definition for register: ERRINT */ +/* + * EWARN (RO) + * + * Error WARNing limit reached + * 1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. + */ +#define CAN_ERRINT_EWARN_MASK (0x80U) +#define CAN_ERRINT_EWARN_SHIFT (7U) +#define CAN_ERRINT_EWARN_GET(x) (((uint8_t)(x) & CAN_ERRINT_EWARN_MASK) >> CAN_ERRINT_EWARN_SHIFT) + +/* + * EPASS (RO) + * + * Error Passive mode active + * 0 - not active (node is error active) + * 1 - active (node is error passive) + */ +#define CAN_ERRINT_EPASS_MASK (0x40U) +#define CAN_ERRINT_EPASS_SHIFT (6U) +#define CAN_ERRINT_EPASS_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPASS_MASK) >> CAN_ERRINT_EPASS_SHIFT) + +/* + * EPIE (RW) + * + * Error Passive Interrupt Enable + */ +#define CAN_ERRINT_EPIE_MASK (0x20U) +#define CAN_ERRINT_EPIE_SHIFT (5U) +#define CAN_ERRINT_EPIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_EPIE_SHIFT) & CAN_ERRINT_EPIE_MASK) +#define CAN_ERRINT_EPIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPIE_MASK) >> CAN_ERRINT_EPIE_SHIFT) + +/* + * EPIF (W1C) + * + * Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error + * active to error passive or vice versa and if this interrupt is enabled. + */ +#define CAN_ERRINT_EPIF_MASK (0x10U) +#define CAN_ERRINT_EPIF_SHIFT (4U) +#define CAN_ERRINT_EPIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_EPIF_SHIFT) & CAN_ERRINT_EPIF_MASK) +#define CAN_ERRINT_EPIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPIF_MASK) >> CAN_ERRINT_EPIF_SHIFT) + +/* + * ALIE (RW) + * + * Arbitration Lost Interrupt Enable + */ +#define CAN_ERRINT_ALIE_MASK (0x8U) +#define CAN_ERRINT_ALIE_SHIFT (3U) +#define CAN_ERRINT_ALIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_ALIE_SHIFT) & CAN_ERRINT_ALIE_MASK) +#define CAN_ERRINT_ALIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_ALIE_MASK) >> CAN_ERRINT_ALIE_SHIFT) + +/* + * ALIF (W1C) + * + * Arbitration Lost Interrupt Flag + */ +#define CAN_ERRINT_ALIF_MASK (0x4U) +#define CAN_ERRINT_ALIF_SHIFT (2U) +#define CAN_ERRINT_ALIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_ALIF_SHIFT) & CAN_ERRINT_ALIF_MASK) +#define CAN_ERRINT_ALIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_ALIF_MASK) >> CAN_ERRINT_ALIF_SHIFT) + +/* + * BEIE (RW) + * + * Bus Error Interrupt Enable + */ +#define CAN_ERRINT_BEIE_MASK (0x2U) +#define CAN_ERRINT_BEIE_SHIFT (1U) +#define CAN_ERRINT_BEIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_BEIE_SHIFT) & CAN_ERRINT_BEIE_MASK) +#define CAN_ERRINT_BEIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_BEIE_MASK) >> CAN_ERRINT_BEIE_SHIFT) + +/* + * BEIF (W1C) + * + * Bus Error Interrupt Flag + */ +#define CAN_ERRINT_BEIF_MASK (0x1U) +#define CAN_ERRINT_BEIF_SHIFT (0U) +#define CAN_ERRINT_BEIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_BEIF_SHIFT) & CAN_ERRINT_BEIF_MASK) +#define CAN_ERRINT_BEIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_BEIF_MASK) >> CAN_ERRINT_BEIF_SHIFT) + +/* Bitfield definition for register: LIMIT */ +/* + * AFWL (RW) + * + * receive buffer Almost Full Warning Limit + * AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. + * AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . + * AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) + * AFWL_i > nRB is meaningless and automatically treated as nRB. + * AFWL_i = nRB is a valid value, but note that RFIF also exists. + */ +#define CAN_LIMIT_AFWL_MASK (0xF0U) +#define CAN_LIMIT_AFWL_SHIFT (4U) +#define CAN_LIMIT_AFWL_SET(x) (((uint8_t)(x) << CAN_LIMIT_AFWL_SHIFT) & CAN_LIMIT_AFWL_MASK) +#define CAN_LIMIT_AFWL_GET(x) (((uint8_t)(x) & CAN_LIMIT_AFWL_MASK) >> CAN_LIMIT_AFWL_SHIFT) + +/* + * EWL (RW) + * + * Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. + * The value of EWL controls EIF. + */ +#define CAN_LIMIT_EWL_MASK (0xFU) +#define CAN_LIMIT_EWL_SHIFT (0U) +#define CAN_LIMIT_EWL_SET(x) (((uint8_t)(x) << CAN_LIMIT_EWL_SHIFT) & CAN_LIMIT_EWL_MASK) +#define CAN_LIMIT_EWL_GET(x) (((uint8_t)(x) & CAN_LIMIT_EWL_MASK) >> CAN_LIMIT_EWL_SHIFT) + +/* Bitfield definition for register: S_PRESC */ +/* + * S_PRESC (RW) + * + * Prescaler (slow speed) + * The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + */ +#define CAN_S_PRESC_S_PRESC_MASK (0xFF000000UL) +#define CAN_S_PRESC_S_PRESC_SHIFT (24U) +#define CAN_S_PRESC_S_PRESC_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_PRESC_SHIFT) & CAN_S_PRESC_S_PRESC_MASK) +#define CAN_S_PRESC_S_PRESC_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_PRESC_MASK) >> CAN_S_PRESC_S_PRESC_SHIFT) + +/* + * S_SJW (RW) + * + * Synchronization Jump Width (slow speed) + * The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + */ +#define CAN_S_PRESC_S_SJW_MASK (0x7F0000UL) +#define CAN_S_PRESC_S_SJW_SHIFT (16U) +#define CAN_S_PRESC_S_SJW_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SJW_SHIFT) & CAN_S_PRESC_S_SJW_MASK) +#define CAN_S_PRESC_S_SJW_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SJW_MASK) >> CAN_S_PRESC_S_SJW_SHIFT) + +/* + * S_SEG_2 (RW) + * + * Bit Timing Segment 2 (slow speed) + * Time after the sample point. + */ +#define CAN_S_PRESC_S_SEG_2_MASK (0x7F00U) +#define CAN_S_PRESC_S_SEG_2_SHIFT (8U) +#define CAN_S_PRESC_S_SEG_2_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SEG_2_SHIFT) & CAN_S_PRESC_S_SEG_2_MASK) +#define CAN_S_PRESC_S_SEG_2_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SEG_2_MASK) >> CAN_S_PRESC_S_SEG_2_SHIFT) + +/* + * S_SEG_1 (RW) + * + * Bit Timing Segment 1 (slow speed) + * The sample point will be set to after start of bit time. + */ +#define CAN_S_PRESC_S_SEG_1_MASK (0xFFU) +#define CAN_S_PRESC_S_SEG_1_SHIFT (0U) +#define CAN_S_PRESC_S_SEG_1_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SEG_1_SHIFT) & CAN_S_PRESC_S_SEG_1_MASK) +#define CAN_S_PRESC_S_SEG_1_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SEG_1_MASK) >> CAN_S_PRESC_S_SEG_1_SHIFT) + +/* Bitfield definition for register: F_PRESC */ +/* + * F_PRESC (RW) + * + * Prescaler (fast speed) + * The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. + */ +#define CAN_F_PRESC_F_PRESC_MASK (0xFF000000UL) +#define CAN_F_PRESC_F_PRESC_SHIFT (24U) +#define CAN_F_PRESC_F_PRESC_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_PRESC_SHIFT) & CAN_F_PRESC_F_PRESC_MASK) +#define CAN_F_PRESC_F_PRESC_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_PRESC_MASK) >> CAN_F_PRESC_F_PRESC_SHIFT) + +/* + * F_SJW (RW) + * + * Synchronization Jump Width (fast speed) + * The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. + */ +#define CAN_F_PRESC_F_SJW_MASK (0xF0000UL) +#define CAN_F_PRESC_F_SJW_SHIFT (16U) +#define CAN_F_PRESC_F_SJW_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SJW_SHIFT) & CAN_F_PRESC_F_SJW_MASK) +#define CAN_F_PRESC_F_SJW_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SJW_MASK) >> CAN_F_PRESC_F_SJW_SHIFT) + +/* + * F_SEG_2 (RW) + * + * Bit Timing Segment 2 (fast speed) + * Time after the sample point + */ +#define CAN_F_PRESC_F_SEG_2_MASK (0xF00U) +#define CAN_F_PRESC_F_SEG_2_SHIFT (8U) +#define CAN_F_PRESC_F_SEG_2_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SEG_2_SHIFT) & CAN_F_PRESC_F_SEG_2_MASK) +#define CAN_F_PRESC_F_SEG_2_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SEG_2_MASK) >> CAN_F_PRESC_F_SEG_2_SHIFT) + +/* + * F_SEG_1 (RW) + * + * Bit Timing Segment 1 (fast speed) + * The sample point will be set to after start of bit time. + */ +#define CAN_F_PRESC_F_SEG_1_MASK (0xFU) +#define CAN_F_PRESC_F_SEG_1_SHIFT (0U) +#define CAN_F_PRESC_F_SEG_1_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SEG_1_SHIFT) & CAN_F_PRESC_F_SEG_1_MASK) +#define CAN_F_PRESC_F_SEG_1_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SEG_1_MASK) >> CAN_F_PRESC_F_SEG_1_SHIFT) + +/* Bitfield definition for register: EALCAP */ +/* + * KOER (RO) + * + * Kind Of ERror (Error code) + * 000 - no error + * 001 - BIT ERROR + * 010 - FORM ERROR + * 011 - STUFF ERROR + * 100 - ACKNOWLEDGEMENT ERROR + * 101 - CRC ERROR + * 110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) + * 111 - not used + * KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. + */ +#define CAN_EALCAP_KOER_MASK (0xE0U) +#define CAN_EALCAP_KOER_SHIFT (5U) +#define CAN_EALCAP_KOER_GET(x) (((uint8_t)(x) & CAN_EALCAP_KOER_MASK) >> CAN_EALCAP_KOER_SHIFT) + +/* + * ALC (RO) + * + * Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) + */ +#define CAN_EALCAP_ALC_MASK (0x1FU) +#define CAN_EALCAP_ALC_SHIFT (0U) +#define CAN_EALCAP_ALC_GET(x) (((uint8_t)(x) & CAN_EALCAP_ALC_MASK) >> CAN_EALCAP_ALC_SHIFT) + +/* Bitfield definition for register: TDC */ +/* + * TDCEN (RW) + * + * Transmitter Delay Compensation ENable + * TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. + */ +#define CAN_TDC_TDCEN_MASK (0x80U) +#define CAN_TDC_TDCEN_SHIFT (7U) +#define CAN_TDC_TDCEN_SET(x) (((uint8_t)(x) << CAN_TDC_TDCEN_SHIFT) & CAN_TDC_TDCEN_MASK) +#define CAN_TDC_TDCEN_GET(x) (((uint8_t)(x) & CAN_TDC_TDCEN_MASK) >> CAN_TDC_TDCEN_SHIFT) + +/* + * SSPOFF (RW) + * + * Secondary Sample Point OFFset + * The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. + * SSPOFF is given as a number of TQ. + */ +#define CAN_TDC_SSPOFF_MASK (0x7FU) +#define CAN_TDC_SSPOFF_SHIFT (0U) +#define CAN_TDC_SSPOFF_SET(x) (((uint8_t)(x) << CAN_TDC_SSPOFF_SHIFT) & CAN_TDC_SSPOFF_MASK) +#define CAN_TDC_SSPOFF_GET(x) (((uint8_t)(x) & CAN_TDC_SSPOFF_MASK) >> CAN_TDC_SSPOFF_SHIFT) + +/* Bitfield definition for register: RECNT */ +/* + * RECNT (RO) + * + * Receive Error CouNT (number of errors during reception) + * RECNT is incremented and decremented as defined in the CAN specification. + * RECNT does not overflow. + * If TXB=1, then the error counters are frozen. + */ +#define CAN_RECNT_RECNT_MASK (0xFFU) +#define CAN_RECNT_RECNT_SHIFT (0U) +#define CAN_RECNT_RECNT_GET(x) (((uint8_t)(x) & CAN_RECNT_RECNT_MASK) >> CAN_RECNT_RECNT_SHIFT) + +/* Bitfield definition for register: TECNT */ +/* + * TECNT (RO) + * + * Transmit Error CouNT (number of errors during transmission) + * TECNT is incremented and decremented as defined in the CAN specification. + * In case of the “bus off state” TECNT may overflow. + * If TXB=1, then the error counters are frozen. + */ +#define CAN_TECNT_TECNT_MASK (0xFFU) +#define CAN_TECNT_TECNT_SHIFT (0U) +#define CAN_TECNT_TECNT_GET(x) (((uint8_t)(x) & CAN_TECNT_TECNT_MASK) >> CAN_TECNT_TECNT_SHIFT) + +/* Bitfield definition for register: ACFCTRL */ +/* + * SELMASK (RW) + * + * SELect acceptance MASK + * 0 - Registers ACF_x point to acceptance code + * 1 - Registers ACF_x point to acceptance mask. + * ACFADR selects one specific acceptance filter. + */ +#define CAN_ACFCTRL_SELMASK_MASK (0x20U) +#define CAN_ACFCTRL_SELMASK_SHIFT (5U) +#define CAN_ACFCTRL_SELMASK_SET(x) (((uint8_t)(x) << CAN_ACFCTRL_SELMASK_SHIFT) & CAN_ACFCTRL_SELMASK_MASK) +#define CAN_ACFCTRL_SELMASK_GET(x) (((uint8_t)(x) & CAN_ACFCTRL_SELMASK_MASK) >> CAN_ACFCTRL_SELMASK_SHIFT) + +/* + * ACFADR (RW) + * + * acceptance filter address + * ACFADR points to a specific acceptance filter. + * The selected filter is accessible using theregisters ACF_x. + * Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. + * A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. + * ACF_NUMBER = 16. + */ +#define CAN_ACFCTRL_ACFADR_MASK (0xFU) +#define CAN_ACFCTRL_ACFADR_SHIFT (0U) +#define CAN_ACFCTRL_ACFADR_SET(x) (((uint8_t)(x) << CAN_ACFCTRL_ACFADR_SHIFT) & CAN_ACFCTRL_ACFADR_MASK) +#define CAN_ACFCTRL_ACFADR_GET(x) (((uint8_t)(x) & CAN_ACFCTRL_ACFADR_MASK) >> CAN_ACFCTRL_ACFADR_SHIFT) + +/* Bitfield definition for register: TIMECFG */ +/* + * TIMEPOS (RW) + * + * TIME-stamping POSition + * 0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. + */ +#define CAN_TIMECFG_TIMEPOS_MASK (0x2U) +#define CAN_TIMECFG_TIMEPOS_SHIFT (1U) +#define CAN_TIMECFG_TIMEPOS_SET(x) (((uint8_t)(x) << CAN_TIMECFG_TIMEPOS_SHIFT) & CAN_TIMECFG_TIMEPOS_MASK) +#define CAN_TIMECFG_TIMEPOS_GET(x) (((uint8_t)(x) & CAN_TIMECFG_TIMEPOS_MASK) >> CAN_TIMECFG_TIMEPOS_SHIFT) + +/* + * TIMEEN (RW) + * + * TIME-stamping ENable + * 0 – disabled + * 1 – enabled + */ +#define CAN_TIMECFG_TIMEEN_MASK (0x1U) +#define CAN_TIMECFG_TIMEEN_SHIFT (0U) +#define CAN_TIMECFG_TIMEEN_SET(x) (((uint8_t)(x) << CAN_TIMECFG_TIMEEN_SHIFT) & CAN_TIMECFG_TIMEEN_MASK) +#define CAN_TIMECFG_TIMEEN_GET(x) (((uint8_t)(x) & CAN_TIMECFG_TIMEEN_MASK) >> CAN_TIMECFG_TIMEEN_SHIFT) + +/* Bitfield definition for register: ACF_EN */ +/* + * ACF_EN (RW) + * + * Acceptance filter Enable + * 1 - acceptance filter enabled + * 0 - acceptance filter disable + * Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. + * Disabled filters reject a message. Only enabled filters can accept a message if the + * appropriate AMASK / ACODE configuration matches. + */ +#define CAN_ACF_EN_ACF_EN_MASK (0xFFFFU) +#define CAN_ACF_EN_ACF_EN_SHIFT (0U) +#define CAN_ACF_EN_ACF_EN_SET(x) (((uint16_t)(x) << CAN_ACF_EN_ACF_EN_SHIFT) & CAN_ACF_EN_ACF_EN_MASK) +#define CAN_ACF_EN_ACF_EN_GET(x) (((uint16_t)(x) & CAN_ACF_EN_ACF_EN_MASK) >> CAN_ACF_EN_ACF_EN_SHIFT) + +/* Bitfield definition for register: ACF */ +/* + * AIDEE (RW) + * + * Acceptance mask IDE bit check enable + * 1 - acceptance filter accepts either standard or extended as defined by AIDE + * 0 - acceptance filter accepts both standard or extended frames + * Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + */ +#define CAN_ACF_AIDEE_MASK (0x40000000UL) +#define CAN_ACF_AIDEE_SHIFT (30U) +#define CAN_ACF_AIDEE_SET(x) (((uint32_t)(x) << CAN_ACF_AIDEE_SHIFT) & CAN_ACF_AIDEE_MASK) +#define CAN_ACF_AIDEE_GET(x) (((uint32_t)(x) & CAN_ACF_AIDEE_MASK) >> CAN_ACF_AIDEE_SHIFT) + +/* + * AIDE (RW) + * + * Acceptance mask IDE bit value + * If AIDEE=1 then: + * 1 - acceptance filter accepts only extended frames + * 0 - acceptance filter accepts only standard frames + * Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. + */ +#define CAN_ACF_AIDE_MASK (0x20000000UL) +#define CAN_ACF_AIDE_SHIFT (29U) +#define CAN_ACF_AIDE_SET(x) (((uint32_t)(x) << CAN_ACF_AIDE_SHIFT) & CAN_ACF_AIDE_MASK) +#define CAN_ACF_AIDE_GET(x) (((uint32_t)(x) & CAN_ACF_AIDE_MASK) >> CAN_ACF_AIDE_SHIFT) + +/* + * CODE_MASK (RW) + * + * Acceptance CODE + * 1 - ACC bit value to compare with ID bit of the received message + * 0 - ACC bit value to compare with ID bit of the received message + * ACODE_x(10:0) will be used for extended frames. + * ACODE_x(28:0) will be used for extended frames. + * Only filter 0 is affected by the power-on reset. + * Acceptance MASK(if SELMASK ==1 ) + * 1 - acceptance check for these bits of receive identifier disabled + * 0 - acceptance check for these bits of receive identifier enable + * AMASK_x(10:0) will be used for extended frames. + * AMASK_x(28:0) will be used for extended frames. + * Disabled bits result in accepting the message. Therefore the default configuration after + * reset for filter 0 accepts all messages. + * Only filter 0 is affected by the power-on reset. + */ +#define CAN_ACF_CODE_MASK_MASK (0x1FFFFFFFUL) +#define CAN_ACF_CODE_MASK_SHIFT (0U) +#define CAN_ACF_CODE_MASK_SET(x) (((uint32_t)(x) << CAN_ACF_CODE_MASK_SHIFT) & CAN_ACF_CODE_MASK_MASK) +#define CAN_ACF_CODE_MASK_GET(x) (((uint32_t)(x) & CAN_ACF_CODE_MASK_MASK) >> CAN_ACF_CODE_MASK_SHIFT) + +/* Bitfield definition for register: VER */ +/* + * VERSION (RW) + * + * Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and + * VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 + */ +#define CAN_VER_VERSION_MASK (0xFFFFU) +#define CAN_VER_VERSION_SHIFT (0U) +#define CAN_VER_VERSION_SET(x) (((uint16_t)(x) << CAN_VER_VERSION_SHIFT) & CAN_VER_VERSION_MASK) +#define CAN_VER_VERSION_GET(x) (((uint16_t)(x) & CAN_VER_VERSION_MASK) >> CAN_VER_VERSION_SHIFT) + +/* Bitfield definition for register: TBSLOT */ +/* + * TBE (RW) + * + * set TB slot to “Empty” + * 1 - slot selected by TBPTR shall be marked as “empty” + * 0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. + * If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the + * transmissionis not active any more. + * If both TBF and TBE are set, then TBE wins + */ +#define CAN_TBSLOT_TBE_MASK (0x80U) +#define CAN_TBSLOT_TBE_SHIFT (7U) +#define CAN_TBSLOT_TBE_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBE_SHIFT) & CAN_TBSLOT_TBE_MASK) +#define CAN_TBSLOT_TBE_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBE_MASK) >> CAN_TBSLOT_TBE_SHIFT) + +/* + * TBF (RW) + * + * set TB slot to “Filled” + * 1 - slot selected by TBPTR shall be marked as “filled” + * 0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. + * If both TBF and TBE are set, then TBE wins. + */ +#define CAN_TBSLOT_TBF_MASK (0x40U) +#define CAN_TBSLOT_TBF_SHIFT (6U) +#define CAN_TBSLOT_TBF_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBF_SHIFT) & CAN_TBSLOT_TBF_MASK) +#define CAN_TBSLOT_TBF_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBF_MASK) >> CAN_TBSLOT_TBF_SHIFT) + +/* + * TBPTR (RW) + * + * Pointer to a TB message slot. + * 0x00 - Pointer to the PTB + * others - Pointer to a slot in the STB + * The message slot pointed to by TBPTR is readable / writable using the TBUF registers. + * Write access is only possible if TSFF=0. + * Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. + * TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. + * TBPTR can only point to buffer slots, that exist in the hardware. + * Unusable bits ofTBPTR are fixed to 0. + * TBPTR is limited to the PTB and 63 STB slots. + * More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. + */ +#define CAN_TBSLOT_TBPTR_MASK (0x3FU) +#define CAN_TBSLOT_TBPTR_SHIFT (0U) +#define CAN_TBSLOT_TBPTR_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBPTR_SHIFT) & CAN_TBSLOT_TBPTR_MASK) +#define CAN_TBSLOT_TBPTR_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBPTR_MASK) >> CAN_TBSLOT_TBPTR_SHIFT) + +/* Bitfield definition for register: TTCFG */ +/* + * WTIE (RW) + * + * Watch Trigger Interrupt Enable + */ +#define CAN_TTCFG_WTIE_MASK (0x80U) +#define CAN_TTCFG_WTIE_SHIFT (7U) +#define CAN_TTCFG_WTIE_SET(x) (((uint8_t)(x) << CAN_TTCFG_WTIE_SHIFT) & CAN_TTCFG_WTIE_MASK) +#define CAN_TTCFG_WTIE_GET(x) (((uint8_t)(x) & CAN_TTCFG_WTIE_MASK) >> CAN_TTCFG_WTIE_SHIFT) + +/* + * WTIF (RW) + * + * Watch Trigger Interrupt Flag + * WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. + */ +#define CAN_TTCFG_WTIF_MASK (0x40U) +#define CAN_TTCFG_WTIF_SHIFT (6U) +#define CAN_TTCFG_WTIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_WTIF_SHIFT) & CAN_TTCFG_WTIF_MASK) +#define CAN_TTCFG_WTIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_WTIF_MASK) >> CAN_TTCFG_WTIF_SHIFT) + +/* + * TEIF (RW) + * + * Trigger Error Interrupt Flag + * The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF + */ +#define CAN_TTCFG_TEIF_MASK (0x20U) +#define CAN_TTCFG_TEIF_SHIFT (5U) +#define CAN_TTCFG_TEIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_TEIF_SHIFT) & CAN_TTCFG_TEIF_MASK) +#define CAN_TTCFG_TEIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_TEIF_MASK) >> CAN_TTCFG_TEIF_SHIFT) + +/* + * TTIE (RW) + * + * Time Trigger Interrupt Enable + * If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. + */ +#define CAN_TTCFG_TTIE_MASK (0x10U) +#define CAN_TTCFG_TTIE_SHIFT (4U) +#define CAN_TTCFG_TTIE_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTIE_SHIFT) & CAN_TTCFG_TTIE_MASK) +#define CAN_TTCFG_TTIE_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTIE_MASK) >> CAN_TTCFG_TTIE_SHIFT) + +/* + * TTIF (RW) + * + * Time Trigger Interrupt Flag + * TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. + * Writing an one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. + * If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. + */ +#define CAN_TTCFG_TTIF_MASK (0x8U) +#define CAN_TTCFG_TTIF_SHIFT (3U) +#define CAN_TTCFG_TTIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTIF_SHIFT) & CAN_TTCFG_TTIF_MASK) +#define CAN_TTCFG_TTIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTIF_MASK) >> CAN_TTCFG_TTIF_SHIFT) + +/* + * T_PRESC (RW) + * + * TTCAN Timer PRESCaler + * 00b - 1 + * 01b - 2 + * 10b - 4 + * 11b - 8 + * The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. + * T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. + */ +#define CAN_TTCFG_T_PRESC_MASK (0x6U) +#define CAN_TTCFG_T_PRESC_SHIFT (1U) +#define CAN_TTCFG_T_PRESC_SET(x) (((uint8_t)(x) << CAN_TTCFG_T_PRESC_SHIFT) & CAN_TTCFG_T_PRESC_MASK) +#define CAN_TTCFG_T_PRESC_GET(x) (((uint8_t)(x) & CAN_TTCFG_T_PRESC_MASK) >> CAN_TTCFG_T_PRESC_SHIFT) + +/* + * TTEN (RW) + * + * Time Trigger Enable + * 1 - TTCAN enabled, timer is running0 - disabled + */ +#define CAN_TTCFG_TTEN_MASK (0x1U) +#define CAN_TTCFG_TTEN_SHIFT (0U) +#define CAN_TTCFG_TTEN_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTEN_SHIFT) & CAN_TTCFG_TTEN_MASK) +#define CAN_TTCFG_TTEN_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTEN_MASK) >> CAN_TTCFG_TTEN_SHIFT) + +/* Bitfield definition for register: REF_MSG */ +/* + * REF_IDE (RW) + * + * REFerence message IDE bit. + */ +#define CAN_REF_MSG_REF_IDE_MASK (0x80000000UL) +#define CAN_REF_MSG_REF_IDE_SHIFT (31U) +#define CAN_REF_MSG_REF_IDE_SET(x) (((uint32_t)(x) << CAN_REF_MSG_REF_IDE_SHIFT) & CAN_REF_MSG_REF_IDE_MASK) +#define CAN_REF_MSG_REF_IDE_GET(x) (((uint32_t)(x) & CAN_REF_MSG_REF_IDE_MASK) >> CAN_REF_MSG_REF_IDE_SHIFT) + +/* + * REF_MSG (RW) + * + * REFerence message IDentifier. + * If REF_IDE is + * 1 - REF_ID(28:0) is valid (extended ID) + * 0 - REF_ID(10:0) is valid (standard ID) + * REF_ID is used in TTCAN mode to detect a reference message. This holds for time + * slaves (reception) as well as for the time master (transmission). If the reference + * message is detected and there are no errors, then the Sync_Mark of this frame will + * become the Ref_Mark. + * REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. + * These bits are used for up to 8 potential time masters. + * CAN-CTRL recognizes the reference message only by ID. The payload is not tested. + * Additional note: A time master will transmit a reference message in the same way as a + * normal frame. REF_ID is intended for detection of a successful transmission of a + * reference message. + */ +#define CAN_REF_MSG_REF_MSG_MASK (0x1FFFFFFFUL) +#define CAN_REF_MSG_REF_MSG_SHIFT (0U) +#define CAN_REF_MSG_REF_MSG_SET(x) (((uint32_t)(x) << CAN_REF_MSG_REF_MSG_SHIFT) & CAN_REF_MSG_REF_MSG_MASK) +#define CAN_REF_MSG_REF_MSG_GET(x) (((uint32_t)(x) & CAN_REF_MSG_REF_MSG_MASK) >> CAN_REF_MSG_REF_MSG_SHIFT) + +/* Bitfield definition for register: TRIG_CFG */ +/* + * TEW (RW) + * + * Transmit Enable Window + * For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time + * where the frame is allowed to start. TWE+1 defines the number of ticks. + * TEW=0 is a valid setting and shortens the transmit enable window to 1 tick + */ +#define CAN_TRIG_CFG_TEW_MASK (0xF000U) +#define CAN_TRIG_CFG_TEW_SHIFT (12U) +#define CAN_TRIG_CFG_TEW_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TEW_SHIFT) & CAN_TRIG_CFG_TEW_MASK) +#define CAN_TRIG_CFG_TEW_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TEW_MASK) >> CAN_TRIG_CFG_TEW_SHIFT) + +/* + * TTYPE (RW) + * + * Trigger Type + * 000b - Immediate Trigger for immediate transmission + * 001b - Time Trigger for receive triggers + * 010b - Single Shot Transmit Trigger for exclusive time windows + * 011b - Transmit Start Trigger for merged arbitrating time windows + * 100b - Transmit Stop Trigger for merged arbitrating time windows + * others - no action + * The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the + * transmit triggers. See Chapter 6.4 for more details. + */ +#define CAN_TRIG_CFG_TTYPE_MASK (0x700U) +#define CAN_TRIG_CFG_TTYPE_SHIFT (8U) +#define CAN_TRIG_CFG_TTYPE_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TTYPE_SHIFT) & CAN_TRIG_CFG_TTYPE_MASK) +#define CAN_TRIG_CFG_TTYPE_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TTYPE_MASK) >> CAN_TRIG_CFG_TTYPE_SHIFT) + +/* + * TTPTR (RW) + * + * Transmit Trigger TB slot Pointer + * If TTPTR is too big and points to a slot that is not available, then TEIF is set and no + * new trigger can be activated after a write access to TT_TRIG_1. + * If TTPTR points to an empty slot, then TEIF will be set at the moment, when the + * trigger time is reached. + */ +#define CAN_TRIG_CFG_TTPTR_MASK (0x3FU) +#define CAN_TRIG_CFG_TTPTR_SHIFT (0U) +#define CAN_TRIG_CFG_TTPTR_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TTPTR_SHIFT) & CAN_TRIG_CFG_TTPTR_MASK) +#define CAN_TRIG_CFG_TTPTR_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TTPTR_MASK) >> CAN_TRIG_CFG_TTPTR_SHIFT) + +/* Bitfield definition for register: TT_TRIG */ +/* + * TT_TRIG (RW) + * + * Trigger Time + * TT_TRIG(15:0) defines the cycle time for a trigger. + * For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. + */ +#define CAN_TT_TRIG_TT_TRIG_MASK (0xFFFFU) +#define CAN_TT_TRIG_TT_TRIG_SHIFT (0U) +#define CAN_TT_TRIG_TT_TRIG_SET(x) (((uint16_t)(x) << CAN_TT_TRIG_TT_TRIG_SHIFT) & CAN_TT_TRIG_TT_TRIG_MASK) +#define CAN_TT_TRIG_TT_TRIG_GET(x) (((uint16_t)(x) & CAN_TT_TRIG_TT_TRIG_MASK) >> CAN_TT_TRIG_TT_TRIG_SHIFT) + +/* Bitfield definition for register: TT_WTRIG */ +/* + * TT_WTRIG (RW) + * + * Watch Trigger Time + * TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. + */ +#define CAN_TT_WTRIG_TT_WTRIG_MASK (0xFFFFU) +#define CAN_TT_WTRIG_TT_WTRIG_SHIFT (0U) +#define CAN_TT_WTRIG_TT_WTRIG_SET(x) (((uint16_t)(x) << CAN_TT_WTRIG_TT_WTRIG_SHIFT) & CAN_TT_WTRIG_TT_WTRIG_MASK) +#define CAN_TT_WTRIG_TT_WTRIG_GET(x) (((uint16_t)(x) & CAN_TT_WTRIG_TT_WTRIG_MASK) >> CAN_TT_WTRIG_TT_WTRIG_SHIFT) + + + +/* RBUF register group index macro definition */ +#define CAN_RBUF_BUF0 (0UL) +#define CAN_RBUF_BUF1 (1UL) +#define CAN_RBUF_BUF2 (2UL) +#define CAN_RBUF_BUF3 (3UL) +#define CAN_RBUF_BUF4 (4UL) +#define CAN_RBUF_BUF5 (5UL) +#define CAN_RBUF_BUF6 (6UL) +#define CAN_RBUF_BUF7 (7UL) +#define CAN_RBUF_BUF8 (8UL) +#define CAN_RBUF_BUF9 (9UL) +#define CAN_RBUF_BUF10 (10UL) +#define CAN_RBUF_BUF11 (11UL) +#define CAN_RBUF_BUF12 (12UL) +#define CAN_RBUF_BUF13 (13UL) +#define CAN_RBUF_BUF14 (14UL) +#define CAN_RBUF_BUF15 (15UL) +#define CAN_RBUF_BUF16 (16UL) +#define CAN_RBUF_BUF17 (17UL) +#define CAN_RBUF_BUF18 (18UL) +#define CAN_RBUF_BUF19 (19UL) + +/* TBUF register group index macro definition */ +#define CAN_TBUF_BUF0 (0UL) +#define CAN_TBUF_BUF1 (1UL) +#define CAN_TBUF_BUF2 (2UL) +#define CAN_TBUF_BUF3 (3UL) +#define CAN_TBUF_BUF4 (4UL) +#define CAN_TBUF_BUF5 (5UL) +#define CAN_TBUF_BUF6 (6UL) +#define CAN_TBUF_BUF7 (7UL) +#define CAN_TBUF_BUF8 (8UL) +#define CAN_TBUF_BUF9 (9UL) +#define CAN_TBUF_BUF10 (10UL) +#define CAN_TBUF_BUF11 (11UL) +#define CAN_TBUF_BUF12 (12UL) +#define CAN_TBUF_BUF13 (13UL) +#define CAN_TBUF_BUF14 (14UL) +#define CAN_TBUF_BUF15 (15UL) +#define CAN_TBUF_BUF16 (16UL) +#define CAN_TBUF_BUF17 (17UL) + +/* TTS register group index macro definition */ +#define CAN_TTS_WRD0 (0UL) +#define CAN_TTS_WRD1 (1UL) + + +#endif /* HPM_CAN_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_conctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_conctl_regs.h new file mode 100644 index 0000000000..d3ab74834e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_conctl_regs.h @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CONCTL_H +#define HPM_CONCTL_H + +typedef struct { + __RW uint32_t CTRL0; /* 0x0: */ + __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ + __RW uint32_t CTRL2; /* 0x8: */ + __RW uint32_t CTRL3; /* 0xC: */ + __RW uint32_t CTRL4; /* 0x10: */ + __RW uint32_t CTRL5; /* 0x14: */ +} CONCTL_Type; + + +/* Bitfield definition for register: CTRL0 */ +/* + * ENET1_RXCLK_DLY_SEL (RW) + * + */ +#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK (0xF8000UL) +#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT (15U) +#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK) +#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT) + +/* + * ENET1_TXCLK_DLY_SEL (RW) + * + */ +#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK (0x7C00U) +#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT (10U) +#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK) +#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT) + +/* + * ENET0_RXCLK_DLY_SEL (RW) + * + */ +#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3E0U) +#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (5U) +#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) +#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) + +/* + * ENET0_TXCLK_DLY_SEL (RW) + * + */ +#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x1FU) +#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT (0U) +#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) +#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) + +/* Bitfield definition for register: CTRL2 */ +/* + * ENET0_REFCLK_OE (RW) + * + */ +#define CONCTL_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL) +#define CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT (19U) +#define CONCTL_CTRL2_ENET0_REFCLK_OE_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK) +#define CONCTL_CTRL2_ENET0_REFCLK_OE_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK) >> CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT) + +/* + * ENET0_PHY_INTF_SEL (RW) + * + * 000:Reserved + * 001:RGMII + * 100:RMII + * 111:Reserved + */ +#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK (0xE000U) +#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT (13U) +#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK) +#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK) >> CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT) + +/* + * ENET0_FLOWCTRL (RW) + * + */ +#define CONCTL_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U) +#define CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT (12U) +#define CONCTL_CTRL2_ENET0_FLOWCTRL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK) +#define CONCTL_CTRL2_ENET0_FLOWCTRL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK) >> CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT) + +/* + * ENET0_RMII_TXCLK_SEL (RW) + * + * default to use internal clk. + * set from pad， two option here: + * internal 50MHz clock out to pad then in; + * use external clock; + */ +#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U) +#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U) +#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) +#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) + +/* Bitfield definition for register: CTRL3 */ +/* + * ENET1_REFCLK_OE (RW) + * + */ +#define CONCTL_CTRL3_ENET1_REFCLK_OE_MASK (0x80000UL) +#define CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT (19U) +#define CONCTL_CTRL3_ENET1_REFCLK_OE_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK) +#define CONCTL_CTRL3_ENET1_REFCLK_OE_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK) >> CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT) + +/* + * ENET1_PHY_INTF_SEL (RW) + * + */ +#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK (0xE000U) +#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT (13U) +#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK) +#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK) >> CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT) + +/* + * ENET1_FLOWCTRL (RW) + * + */ +#define CONCTL_CTRL3_ENET1_FLOWCTRL_MASK (0x1000U) +#define CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT (12U) +#define CONCTL_CTRL3_ENET1_FLOWCTRL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK) +#define CONCTL_CTRL3_ENET1_FLOWCTRL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK) >> CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT) + +/* + * ENET1_RMII_TXCLK_SEL (RW) + * + */ +#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK (0x400U) +#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT (10U) +#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK) +#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT) + +/* Bitfield definition for register: CTRL4 */ +/* + * SDXC0_SYS_IRQ_EN (RW) + * + * system irq enable + */ +#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK (0x80000000UL) +#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT (31U) +#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK) +#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT) + +/* + * SDXC0_WKP_IRQ_EN (RW) + * + * wakeup irq enable + */ +#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK (0x40000000UL) +#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT (30U) +#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK) +#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT) + +/* + * SDXC0_CARDCLK_INV_EN (RW) + * + * card clock inverter enable + */ +#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK (0x10000000UL) +#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT (28U) +#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK) +#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT) + +/* + * SDXC0_GPR_TUNING_CARD_CLK_SEL (RW) + * + * for card clock DLL, default 0 + */ +#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK (0xF800000UL) +#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT (23U) +#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) +#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT) + +/* + * SDXC0_GPR_TUNING_STROBE_SEL (RW) + * + * for strobe DLL, default 7taps(1ns) + */ +#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK (0x7C0000UL) +#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT (18U) +#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) +#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT) + +/* + * SDXC0_GPR_STROBE_IN_ENABLE (RW) + * + * enable strobe clock, maybe used when update strobe DLL + */ +#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK (0x20000UL) +#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT (17U) +#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) +#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) + +/* Bitfield definition for register: CTRL5 */ +/* + * SDXC1_SYS_IRQ_EN (RW) + * + * system irq enable + */ +#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK (0x80000000UL) +#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT (31U) +#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK) +#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT) + +/* + * SDXC1_WKP_IRQ_EN (RW) + * + * wakeup irq enable + */ +#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK (0x40000000UL) +#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT (30U) +#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK) +#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT) + +/* + * SDXC1_CARDCLK_INV_EN (RW) + * + * card clock inverter enable + */ +#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK (0x10000000UL) +#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT (28U) +#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK) +#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT) + +/* + * SDXC1_GPR_TUNING_CARD_CLK_SEL (RW) + * + */ +#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK (0xF800000UL) +#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT (23U) +#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK) +#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT) + +/* + * SDXC1_GPR_TUNING_STROBE_SEL (RW) + * + */ +#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK (0x7C0000UL) +#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT (18U) +#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK) +#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT) + +/* + * SDXC1_GPR_STROBE_IN_ENABLE (RW) + * + */ +#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK (0x20000UL) +#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT (17U) +#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) +#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) + + + + +#endif /* HPM_CONCTL_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h new file mode 100644 index 0000000000..ffab52c9fa --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h @@ -0,0 +1,510 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DAC_H +#define HPM_DAC_H + +typedef struct { + __W uint32_t CFG0; /* 0x0: */ + __RW uint32_t CFG1; /* 0x4: */ + __RW uint32_t CFG2; /* 0x8: */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t STEP_CFG[4]; /* 0x10 - 0x1C: */ + __RW uint32_t BUF_ADDR[2]; /* 0x20 - 0x24: */ + __RW uint32_t BUF_LENGTH; /* 0x28: */ + __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ + __W uint32_t IRQ_STS; /* 0x30: */ + __RW uint32_t IRQ_EN; /* 0x34: */ + __RW uint32_t DMA_EN; /* 0x38: */ + __R uint8_t RESERVED2[4]; /* 0x3C - 0x3F: Reserved */ + __RW uint32_t ANA_CFG0; /* 0x40: */ + __R uint8_t RESERVED3[4]; /* 0x44 - 0x47: Reserved */ + __RW uint32_t STATUS0; /* 0x48: */ +} DAC_Type; + + +/* Bitfield definition for register: CFG0 */ +/* + * SW_DAC_DATA (WO) + * + * dac data used in direct mode(dac_mode==2'b10) + */ +#define DAC_CFG0_SW_DAC_DATA_MASK (0xFFF0000UL) +#define DAC_CFG0_SW_DAC_DATA_SHIFT (16U) +#define DAC_CFG0_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_SW_DAC_DATA_SHIFT) & DAC_CFG0_SW_DAC_DATA_MASK) +#define DAC_CFG0_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_SW_DAC_DATA_MASK) >> DAC_CFG0_SW_DAC_DATA_SHIFT) + +/* + * DMA_AHB_EN (WO) + * + * set to enable internal DMA, it will read one burst if enough space in FIFO. + * Should only be used in buffer mode. + */ +#define DAC_CFG0_DMA_AHB_EN_MASK (0x200U) +#define DAC_CFG0_DMA_AHB_EN_SHIFT (9U) +#define DAC_CFG0_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_DMA_AHB_EN_SHIFT) & DAC_CFG0_DMA_AHB_EN_MASK) +#define DAC_CFG0_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_DMA_AHB_EN_MASK) >> DAC_CFG0_DMA_AHB_EN_SHIFT) + +/* + * SYNC_MODE (WO) + * + * 1: sync dac clock and ahb clock. + * all HW trigger signals are pulse in sync mode, can get faster response; + * 0: async dac clock and ahb_clock + * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + */ +#define DAC_CFG0_SYNC_MODE_MASK (0x100U) +#define DAC_CFG0_SYNC_MODE_SHIFT (8U) +#define DAC_CFG0_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_SYNC_MODE_SHIFT) & DAC_CFG0_SYNC_MODE_MASK) +#define DAC_CFG0_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_SYNC_MODE_MASK) >> DAC_CFG0_SYNC_MODE_SHIFT) + +/* + * TRIG_MODE (WO) + * + * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; + * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + */ +#define DAC_CFG0_TRIG_MODE_MASK (0x80U) +#define DAC_CFG0_TRIG_MODE_SHIFT (7U) +#define DAC_CFG0_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_TRIG_MODE_SHIFT) & DAC_CFG0_TRIG_MODE_MASK) +#define DAC_CFG0_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_TRIG_MODE_MASK) >> DAC_CFG0_TRIG_MODE_SHIFT) + +/* + * HW_TRIG_EN (WO) + * + * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + */ +#define DAC_CFG0_HW_TRIG_EN_MASK (0x40U) +#define DAC_CFG0_HW_TRIG_EN_SHIFT (6U) +#define DAC_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_HW_TRIG_EN_SHIFT) & DAC_CFG0_HW_TRIG_EN_MASK) +#define DAC_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_HW_TRIG_EN_MASK) >> DAC_CFG0_HW_TRIG_EN_SHIFT) + +/* + * DAC_MODE (WO) + * + * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) + * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down + * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + */ +#define DAC_CFG0_DAC_MODE_MASK (0x30U) +#define DAC_CFG0_DAC_MODE_SHIFT (4U) +#define DAC_CFG0_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_DAC_MODE_SHIFT) & DAC_CFG0_DAC_MODE_MASK) +#define DAC_CFG0_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_DAC_MODE_MASK) >> DAC_CFG0_DAC_MODE_SHIFT) + +/* + * BUF_DATA_MODE (WO) + * + * data structure for buffer mode, + * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. + * 1: each 32-bit data contains 1 point, b11:0 for first + */ +#define DAC_CFG0_BUF_DATA_MODE_MASK (0x8U) +#define DAC_CFG0_BUF_DATA_MODE_SHIFT (3U) +#define DAC_CFG0_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BUF_DATA_MODE_MASK) +#define DAC_CFG0_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BUF_DATA_MODE_MASK) >> DAC_CFG0_BUF_DATA_MODE_SHIFT) + +/* + * HBURST_CFG (WO) + * + * DAC support following fixed burst only + * 000-SINGLE; 011-INCR4; 101: INCR8 + * others are reserved + */ +#define DAC_CFG0_HBURST_CFG_MASK (0x7U) +#define DAC_CFG0_HBURST_CFG_SHIFT (0U) +#define DAC_CFG0_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_HBURST_CFG_SHIFT) & DAC_CFG0_HBURST_CFG_MASK) +#define DAC_CFG0_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_HBURST_CFG_MASK) >> DAC_CFG0_HBURST_CFG_SHIFT) + +/* Bitfield definition for register: CFG1 */ +/* + * ANA_CLK_EN (RW) + * + * set to enable analog clock(divided by ana_div_cfg) + */ +#define DAC_CFG1_ANA_CLK_EN_MASK (0x40000UL) +#define DAC_CFG1_ANA_CLK_EN_SHIFT (18U) +#define DAC_CFG1_ANA_CLK_EN_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_CLK_EN_SHIFT) & DAC_CFG1_ANA_CLK_EN_MASK) +#define DAC_CFG1_ANA_CLK_EN_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_CLK_EN_MASK) >> DAC_CFG1_ANA_CLK_EN_SHIFT) + +/* + * ANA_DIV_CFG (RW) + * + * clock divider config for ana_clk to dac analog; + * 00: div2 + * 01: div4 + * 10: div6 + * 11: div8 + */ +#define DAC_CFG1_ANA_DIV_CFG_MASK (0x30000UL) +#define DAC_CFG1_ANA_DIV_CFG_SHIFT (16U) +#define DAC_CFG1_ANA_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_DIV_CFG_SHIFT) & DAC_CFG1_ANA_DIV_CFG_MASK) +#define DAC_CFG1_ANA_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_DIV_CFG_MASK) >> DAC_CFG1_ANA_DIV_CFG_SHIFT) + +/* + * DIV_CFG (RW) + * + * how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. + * Used for step mode and buffer mode, if set to continual trigger mode + */ +#define DAC_CFG1_DIV_CFG_MASK (0xFFFFU) +#define DAC_CFG1_DIV_CFG_SHIFT (0U) +#define DAC_CFG1_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_DIV_CFG_SHIFT) & DAC_CFG1_DIV_CFG_MASK) +#define DAC_CFG1_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_DIV_CFG_MASK) >> DAC_CFG1_DIV_CFG_SHIFT) + +/* Bitfield definition for register: CFG2 */ +/* + * DMA_RST1 (WO) + * + * set to reset dma read pointer to buf1_start_addr; + * if set both dma_rst0&dma_rst1, will set to buf0_start_addr + * user can set fifo_clr bit when use dma_rst* + */ +#define DAC_CFG2_DMA_RST1_MASK (0x80U) +#define DAC_CFG2_DMA_RST1_SHIFT (7U) +#define DAC_CFG2_DMA_RST1_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST1_SHIFT) & DAC_CFG2_DMA_RST1_MASK) +#define DAC_CFG2_DMA_RST1_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST1_MASK) >> DAC_CFG2_DMA_RST1_SHIFT) + +/* + * DMA_RST0 (WO) + * + * set to reset dma read pointer to buf0_start_addr + */ +#define DAC_CFG2_DMA_RST0_MASK (0x40U) +#define DAC_CFG2_DMA_RST0_SHIFT (6U) +#define DAC_CFG2_DMA_RST0_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST0_SHIFT) & DAC_CFG2_DMA_RST0_MASK) +#define DAC_CFG2_DMA_RST0_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST0_MASK) >> DAC_CFG2_DMA_RST0_SHIFT) + +/* + * FIFO_CLR (WO) + * + * set to clear FIFO content(set both read/write pointer to 0) + */ +#define DAC_CFG2_FIFO_CLR_MASK (0x20U) +#define DAC_CFG2_FIFO_CLR_SHIFT (5U) +#define DAC_CFG2_FIFO_CLR_SET(x) (((uint32_t)(x) << DAC_CFG2_FIFO_CLR_SHIFT) & DAC_CFG2_FIFO_CLR_MASK) +#define DAC_CFG2_FIFO_CLR_GET(x) (((uint32_t)(x) & DAC_CFG2_FIFO_CLR_MASK) >> DAC_CFG2_FIFO_CLR_SHIFT) + +/* + * BUF_SW_TRIG (RW) + * + * software trigger for buffer mode, + * W1C in single mode. + * RW in continual mode + */ +#define DAC_CFG2_BUF_SW_TRIG_MASK (0x10U) +#define DAC_CFG2_BUF_SW_TRIG_SHIFT (4U) +#define DAC_CFG2_BUF_SW_TRIG_SET(x) (((uint32_t)(x) << DAC_CFG2_BUF_SW_TRIG_SHIFT) & DAC_CFG2_BUF_SW_TRIG_MASK) +#define DAC_CFG2_BUF_SW_TRIG_GET(x) (((uint32_t)(x) & DAC_CFG2_BUF_SW_TRIG_MASK) >> DAC_CFG2_BUF_SW_TRIG_SHIFT) + +/* + * STEP_SW_TRIG3 (RW) + * + */ +#define DAC_CFG2_STEP_SW_TRIG3_MASK (0x8U) +#define DAC_CFG2_STEP_SW_TRIG3_SHIFT (3U) +#define DAC_CFG2_STEP_SW_TRIG3_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG3_SHIFT) & DAC_CFG2_STEP_SW_TRIG3_MASK) +#define DAC_CFG2_STEP_SW_TRIG3_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG3_MASK) >> DAC_CFG2_STEP_SW_TRIG3_SHIFT) + +/* + * STEP_SW_TRIG2 (RW) + * + */ +#define DAC_CFG2_STEP_SW_TRIG2_MASK (0x4U) +#define DAC_CFG2_STEP_SW_TRIG2_SHIFT (2U) +#define DAC_CFG2_STEP_SW_TRIG2_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG2_SHIFT) & DAC_CFG2_STEP_SW_TRIG2_MASK) +#define DAC_CFG2_STEP_SW_TRIG2_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG2_MASK) >> DAC_CFG2_STEP_SW_TRIG2_SHIFT) + +/* + * STEP_SW_TRIG1 (RW) + * + */ +#define DAC_CFG2_STEP_SW_TRIG1_MASK (0x2U) +#define DAC_CFG2_STEP_SW_TRIG1_SHIFT (1U) +#define DAC_CFG2_STEP_SW_TRIG1_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG1_SHIFT) & DAC_CFG2_STEP_SW_TRIG1_MASK) +#define DAC_CFG2_STEP_SW_TRIG1_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG1_MASK) >> DAC_CFG2_STEP_SW_TRIG1_SHIFT) + +/* + * STEP_SW_TRIG0 (RW) + * + * software trigger0 for step mode, + * W1C in single mode. + * RW in continual mode + */ +#define DAC_CFG2_STEP_SW_TRIG0_MASK (0x1U) +#define DAC_CFG2_STEP_SW_TRIG0_SHIFT (0U) +#define DAC_CFG2_STEP_SW_TRIG0_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG0_SHIFT) & DAC_CFG2_STEP_SW_TRIG0_MASK) +#define DAC_CFG2_STEP_SW_TRIG0_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG0_MASK) >> DAC_CFG2_STEP_SW_TRIG0_SHIFT) + +/* Bitfield definition for register array: STEP_CFG */ +/* + * ROUND_MODE (RW) + * + * 0: stop at end point; + * 1: reload start point, step again + */ +#define DAC_STEP_CFG_ROUND_MODE_MASK (0x20000000UL) +#define DAC_STEP_CFG_ROUND_MODE_SHIFT (29U) +#define DAC_STEP_CFG_ROUND_MODE_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_ROUND_MODE_SHIFT) & DAC_STEP_CFG_ROUND_MODE_MASK) +#define DAC_STEP_CFG_ROUND_MODE_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_ROUND_MODE_MASK) >> DAC_STEP_CFG_ROUND_MODE_SHIFT) + +/* + * UP_DOWN (RW) + * + * 0 for up, 1 for down + */ +#define DAC_STEP_CFG_UP_DOWN_MASK (0x10000000UL) +#define DAC_STEP_CFG_UP_DOWN_SHIFT (28U) +#define DAC_STEP_CFG_UP_DOWN_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_UP_DOWN_SHIFT) & DAC_STEP_CFG_UP_DOWN_MASK) +#define DAC_STEP_CFG_UP_DOWN_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_UP_DOWN_MASK) >> DAC_STEP_CFG_UP_DOWN_SHIFT) + +/* + * END_POINT (RW) + * + */ +#define DAC_STEP_CFG_END_POINT_MASK (0xFFF0000UL) +#define DAC_STEP_CFG_END_POINT_SHIFT (16U) +#define DAC_STEP_CFG_END_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_END_POINT_SHIFT) & DAC_STEP_CFG_END_POINT_MASK) +#define DAC_STEP_CFG_END_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_END_POINT_MASK) >> DAC_STEP_CFG_END_POINT_SHIFT) + +/* + * STEP_NUM (RW) + * + * output data change step_num each DAC clock cycle. + * Ex: if step_num=3, output data sequence is 0,3,6,9 + * NOTE: user should make sure end_point can be reached if step_num is not 1 + * if step_num is 0, output data will always at start point + */ +#define DAC_STEP_CFG_STEP_NUM_MASK (0xF000U) +#define DAC_STEP_CFG_STEP_NUM_SHIFT (12U) +#define DAC_STEP_CFG_STEP_NUM_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_STEP_NUM_SHIFT) & DAC_STEP_CFG_STEP_NUM_MASK) +#define DAC_STEP_CFG_STEP_NUM_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_STEP_NUM_MASK) >> DAC_STEP_CFG_STEP_NUM_SHIFT) + +/* + * START_POINT (RW) + * + */ +#define DAC_STEP_CFG_START_POINT_MASK (0xFFFU) +#define DAC_STEP_CFG_START_POINT_SHIFT (0U) +#define DAC_STEP_CFG_START_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_START_POINT_SHIFT) & DAC_STEP_CFG_START_POINT_MASK) +#define DAC_STEP_CFG_START_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_START_POINT_MASK) >> DAC_STEP_CFG_START_POINT_SHIFT) + +/* Bitfield definition for register array: BUF_ADDR */ +/* + * BUF_START_ADDR (RW) + * + * buffer start address, should be 4-byte aligned + * AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. + */ +#define DAC_BUF_ADDR_BUF_START_ADDR_MASK (0xFFFFFFFCUL) +#define DAC_BUF_ADDR_BUF_START_ADDR_SHIFT (2U) +#define DAC_BUF_ADDR_BUF_START_ADDR_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) +#define DAC_BUF_ADDR_BUF_START_ADDR_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) >> DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) + +/* + * BUF_STOP (RW) + * + * set to stop read point at end of bufffer0 + */ +#define DAC_BUF_ADDR_BUF_STOP_MASK (0x1U) +#define DAC_BUF_ADDR_BUF_STOP_SHIFT (0U) +#define DAC_BUF_ADDR_BUF_STOP_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_STOP_SHIFT) & DAC_BUF_ADDR_BUF_STOP_MASK) +#define DAC_BUF_ADDR_BUF_STOP_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_STOP_MASK) >> DAC_BUF_ADDR_BUF_STOP_SHIFT) + +/* Bitfield definition for register: BUF_LENGTH */ +/* + * BUF1_LEN (RW) + * + * buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer + */ +#define DAC_BUF_LENGTH_BUF1_LEN_MASK (0xFFFF0000UL) +#define DAC_BUF_LENGTH_BUF1_LEN_SHIFT (16U) +#define DAC_BUF_LENGTH_BUF1_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF1_LEN_SHIFT) & DAC_BUF_LENGTH_BUF1_LEN_MASK) +#define DAC_BUF_LENGTH_BUF1_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF1_LEN_MASK) >> DAC_BUF_LENGTH_BUF1_LEN_SHIFT) + +/* + * BUF0_LEN (RW) + * + */ +#define DAC_BUF_LENGTH_BUF0_LEN_MASK (0xFFFFU) +#define DAC_BUF_LENGTH_BUF0_LEN_SHIFT (0U) +#define DAC_BUF_LENGTH_BUF0_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF0_LEN_SHIFT) & DAC_BUF_LENGTH_BUF0_LEN_MASK) +#define DAC_BUF_LENGTH_BUF0_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF0_LEN_MASK) >> DAC_BUF_LENGTH_BUF0_LEN_SHIFT) + +/* Bitfield definition for register: IRQ_STS */ +/* + * AHB_ERROR (W1C) + * + * set if hresp==2'b01(ERROR) + */ +#define DAC_IRQ_STS_AHB_ERROR_MASK (0x8U) +#define DAC_IRQ_STS_AHB_ERROR_SHIFT (3U) +#define DAC_IRQ_STS_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_AHB_ERROR_SHIFT) & DAC_IRQ_STS_AHB_ERROR_MASK) +#define DAC_IRQ_STS_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_AHB_ERROR_MASK) >> DAC_IRQ_STS_AHB_ERROR_SHIFT) + +/* + * FIFO_EMPTY (W1C) + * + */ +#define DAC_IRQ_STS_FIFO_EMPTY_MASK (0x4U) +#define DAC_IRQ_STS_FIFO_EMPTY_SHIFT (2U) +#define DAC_IRQ_STS_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_FIFO_EMPTY_SHIFT) & DAC_IRQ_STS_FIFO_EMPTY_MASK) +#define DAC_IRQ_STS_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_FIFO_EMPTY_MASK) >> DAC_IRQ_STS_FIFO_EMPTY_SHIFT) + +/* + * BUF1_CMPT (W1C) + * + */ +#define DAC_IRQ_STS_BUF1_CMPT_MASK (0x2U) +#define DAC_IRQ_STS_BUF1_CMPT_SHIFT (1U) +#define DAC_IRQ_STS_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF1_CMPT_SHIFT) & DAC_IRQ_STS_BUF1_CMPT_MASK) +#define DAC_IRQ_STS_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF1_CMPT_MASK) >> DAC_IRQ_STS_BUF1_CMPT_SHIFT) + +/* + * BUF0_CMPT (W1C) + * + */ +#define DAC_IRQ_STS_BUF0_CMPT_MASK (0x1U) +#define DAC_IRQ_STS_BUF0_CMPT_SHIFT (0U) +#define DAC_IRQ_STS_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF0_CMPT_SHIFT) & DAC_IRQ_STS_BUF0_CMPT_MASK) +#define DAC_IRQ_STS_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF0_CMPT_MASK) >> DAC_IRQ_STS_BUF0_CMPT_SHIFT) + +/* Bitfield definition for register: IRQ_EN */ +/* + * AHB_ERROR (RW) + * + */ +#define DAC_IRQ_EN_AHB_ERROR_MASK (0x8U) +#define DAC_IRQ_EN_AHB_ERROR_SHIFT (3U) +#define DAC_IRQ_EN_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_AHB_ERROR_SHIFT) & DAC_IRQ_EN_AHB_ERROR_MASK) +#define DAC_IRQ_EN_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_AHB_ERROR_MASK) >> DAC_IRQ_EN_AHB_ERROR_SHIFT) + +/* + * FIFO_EMPTY (RW) + * + */ +#define DAC_IRQ_EN_FIFO_EMPTY_MASK (0x4U) +#define DAC_IRQ_EN_FIFO_EMPTY_SHIFT (2U) +#define DAC_IRQ_EN_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_FIFO_EMPTY_SHIFT) & DAC_IRQ_EN_FIFO_EMPTY_MASK) +#define DAC_IRQ_EN_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_FIFO_EMPTY_MASK) >> DAC_IRQ_EN_FIFO_EMPTY_SHIFT) + +/* + * BUF1_CMPT (RW) + * + */ +#define DAC_IRQ_EN_BUF1_CMPT_MASK (0x2U) +#define DAC_IRQ_EN_BUF1_CMPT_SHIFT (1U) +#define DAC_IRQ_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF1_CMPT_SHIFT) & DAC_IRQ_EN_BUF1_CMPT_MASK) +#define DAC_IRQ_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF1_CMPT_MASK) >> DAC_IRQ_EN_BUF1_CMPT_SHIFT) + +/* + * BUF0_CMPT (RW) + * + */ +#define DAC_IRQ_EN_BUF0_CMPT_MASK (0x1U) +#define DAC_IRQ_EN_BUF0_CMPT_SHIFT (0U) +#define DAC_IRQ_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF0_CMPT_SHIFT) & DAC_IRQ_EN_BUF0_CMPT_MASK) +#define DAC_IRQ_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF0_CMPT_MASK) >> DAC_IRQ_EN_BUF0_CMPT_SHIFT) + +/* Bitfield definition for register: DMA_EN */ +/* + * BUF1_CMPT (RW) + * + */ +#define DAC_DMA_EN_BUF1_CMPT_MASK (0x2U) +#define DAC_DMA_EN_BUF1_CMPT_SHIFT (1U) +#define DAC_DMA_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF1_CMPT_SHIFT) & DAC_DMA_EN_BUF1_CMPT_MASK) +#define DAC_DMA_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF1_CMPT_MASK) >> DAC_DMA_EN_BUF1_CMPT_SHIFT) + +/* + * BUF0_CMPT (RW) + * + */ +#define DAC_DMA_EN_BUF0_CMPT_MASK (0x1U) +#define DAC_DMA_EN_BUF0_CMPT_SHIFT (0U) +#define DAC_DMA_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF0_CMPT_SHIFT) & DAC_DMA_EN_BUF0_CMPT_MASK) +#define DAC_DMA_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF0_CMPT_MASK) >> DAC_DMA_EN_BUF0_CMPT_SHIFT) + +/* Bitfield definition for register: ANA_CFG0 */ +/* + * DAC12BIT_LP_MODE (RW) + * + */ +#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK (0x100U) +#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT (8U) +#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) +#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) >> DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) + +/* + * DAC_CONFIG (RW) + * + */ +#define DAC_ANA_CFG0_DAC_CONFIG_MASK (0xF0U) +#define DAC_ANA_CFG0_DAC_CONFIG_SHIFT (4U) +#define DAC_ANA_CFG0_DAC_CONFIG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC_CONFIG_SHIFT) & DAC_ANA_CFG0_DAC_CONFIG_MASK) +#define DAC_ANA_CFG0_DAC_CONFIG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC_CONFIG_MASK) >> DAC_ANA_CFG0_DAC_CONFIG_SHIFT) + +/* + * CALI_DELTA_V_CFG (RW) + * + */ +#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK (0xCU) +#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT (2U) +#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) +#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) >> DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) + +/* + * BYPASS_CALI_GM (RW) + * + */ +#define DAC_ANA_CFG0_BYPASS_CALI_GM_MASK (0x2U) +#define DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT (1U) +#define DAC_ANA_CFG0_BYPASS_CALI_GM_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) +#define DAC_ANA_CFG0_BYPASS_CALI_GM_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) >> DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) + +/* + * DAC12BIT_EN (RW) + * + */ +#define DAC_ANA_CFG0_DAC12BIT_EN_MASK (0x1U) +#define DAC_ANA_CFG0_DAC12BIT_EN_SHIFT (0U) +#define DAC_ANA_CFG0_DAC12BIT_EN_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) +#define DAC_ANA_CFG0_DAC12BIT_EN_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) >> DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) + +/* Bitfield definition for register: STATUS0 */ +/* + * CUR_BUF_OFFSET (RW) + * + */ +#define DAC_STATUS0_CUR_BUF_OFFSET_MASK (0xFFFF00UL) +#define DAC_STATUS0_CUR_BUF_OFFSET_SHIFT (8U) +#define DAC_STATUS0_CUR_BUF_OFFSET_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) +#define DAC_STATUS0_CUR_BUF_OFFSET_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) >> DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) + +/* + * CUR_BUF_INDEX (RW) + * + */ +#define DAC_STATUS0_CUR_BUF_INDEX_MASK (0x80U) +#define DAC_STATUS0_CUR_BUF_INDEX_SHIFT (7U) +#define DAC_STATUS0_CUR_BUF_INDEX_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_INDEX_SHIFT) & DAC_STATUS0_CUR_BUF_INDEX_MASK) +#define DAC_STATUS0_CUR_BUF_INDEX_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_INDEX_MASK) >> DAC_STATUS0_CUR_BUF_INDEX_SHIFT) + + + +/* STEP_CFG register group index macro definition */ +#define DAC_STEP_CFG_STEP0 (0UL) +#define DAC_STEP_CFG_STEP1 (1UL) +#define DAC_STEP_CFG_STEP2 (2UL) +#define DAC_STEP_CFG_STEP3 (3UL) + +/* BUF_ADDR register group index macro definition */ +#define DAC_BUF_ADDR_BUF0 (0UL) +#define DAC_BUF_ADDR_BUF1 (1UL) + + +#endif /* HPM_DAC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h new file mode 100644 index 0000000000..321b839983 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DAO_H +#define HPM_DAO_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: Control Register */ + __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ + __RW uint32_t CMD; /* 0x8: Command Register */ + __RW uint32_t RX_CFGR; /* 0xC: Configuration Register */ + __RW uint32_t RXSLT; /* 0x10: RX Slot Control Register */ + __RW uint32_t HPF_MA; /* 0x14: HPF A Coef Register */ + __RW uint32_t HPF_B; /* 0x18: HPF B Coef Register */ +} DAO_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * HPF_EN (RW) + * + * Whether HPF is enabled. This HPF is used to filter out the DC part. + */ +#define DAO_CTRL_HPF_EN_MASK (0x20000UL) +#define DAO_CTRL_HPF_EN_SHIFT (17U) +#define DAO_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_HPF_EN_SHIFT) & DAO_CTRL_HPF_EN_MASK) +#define DAO_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_HPF_EN_MASK) >> DAO_CTRL_HPF_EN_SHIFT) + +/* + * SAT_ERR_IE (RW) + * + * Error interrupt enable + * This bit controls the generation of an interrupt when an error condition (saturation) occurs. + * 0: Error interrupt is masked + * 1: Error interrupt is enabled + */ +#define DAO_CTRL_SAT_ERR_IE_MASK (0x10000UL) +#define DAO_CTRL_SAT_ERR_IE_SHIFT (16U) +#define DAO_CTRL_SAT_ERR_IE_SET(x) (((uint32_t)(x) << DAO_CTRL_SAT_ERR_IE_SHIFT) & DAO_CTRL_SAT_ERR_IE_MASK) +#define DAO_CTRL_SAT_ERR_IE_GET(x) (((uint32_t)(x) & DAO_CTRL_SAT_ERR_IE_MASK) >> DAO_CTRL_SAT_ERR_IE_SHIFT) + +/* + * MONO (RW) + * + * Asserted to let the left and right channel output the same value. + */ +#define DAO_CTRL_MONO_MASK (0x80U) +#define DAO_CTRL_MONO_SHIFT (7U) +#define DAO_CTRL_MONO_SET(x) (((uint32_t)(x) << DAO_CTRL_MONO_SHIFT) & DAO_CTRL_MONO_MASK) +#define DAO_CTRL_MONO_GET(x) (((uint32_t)(x) & DAO_CTRL_MONO_MASK) >> DAO_CTRL_MONO_SHIFT) + +/* + * RIGHT_EN (RW) + * + * Asserted to enable the right channel + */ +#define DAO_CTRL_RIGHT_EN_MASK (0x40U) +#define DAO_CTRL_RIGHT_EN_SHIFT (6U) +#define DAO_CTRL_RIGHT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_RIGHT_EN_SHIFT) & DAO_CTRL_RIGHT_EN_MASK) +#define DAO_CTRL_RIGHT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_RIGHT_EN_MASK) >> DAO_CTRL_RIGHT_EN_SHIFT) + +/* + * LEFT_EN (RW) + * + * Asserted to enable the left channel + */ +#define DAO_CTRL_LEFT_EN_MASK (0x20U) +#define DAO_CTRL_LEFT_EN_SHIFT (5U) +#define DAO_CTRL_LEFT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_LEFT_EN_SHIFT) & DAO_CTRL_LEFT_EN_MASK) +#define DAO_CTRL_LEFT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_LEFT_EN_MASK) >> DAO_CTRL_LEFT_EN_SHIFT) + +/* + * REMAP (RW) + * + * 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative + * 0: Don't use remap pwm version + */ +#define DAO_CTRL_REMAP_MASK (0x10U) +#define DAO_CTRL_REMAP_SHIFT (4U) +#define DAO_CTRL_REMAP_SET(x) (((uint32_t)(x) << DAO_CTRL_REMAP_SHIFT) & DAO_CTRL_REMAP_MASK) +#define DAO_CTRL_REMAP_GET(x) (((uint32_t)(x) & DAO_CTRL_REMAP_MASK) >> DAO_CTRL_REMAP_SHIFT) + +/* + * INVERT (RW) + * + * all the outputs are inverted before sending to pad + */ +#define DAO_CTRL_INVERT_MASK (0x8U) +#define DAO_CTRL_INVERT_SHIFT (3U) +#define DAO_CTRL_INVERT_SET(x) (((uint32_t)(x) << DAO_CTRL_INVERT_SHIFT) & DAO_CTRL_INVERT_MASK) +#define DAO_CTRL_INVERT_GET(x) (((uint32_t)(x) & DAO_CTRL_INVERT_MASK) >> DAO_CTRL_INVERT_SHIFT) + +/* + * FALSE_LEVEL (RW) + * + * the pad output in False run mode, or when the module is disabled + * 0: all low + * 1: all high + * 2: P-high, N-low + * 3. output is not enabled + */ +#define DAO_CTRL_FALSE_LEVEL_MASK (0x6U) +#define DAO_CTRL_FALSE_LEVEL_SHIFT (1U) +#define DAO_CTRL_FALSE_LEVEL_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_LEVEL_SHIFT) & DAO_CTRL_FALSE_LEVEL_MASK) +#define DAO_CTRL_FALSE_LEVEL_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_LEVEL_MASK) >> DAO_CTRL_FALSE_LEVEL_SHIFT) + +/* + * FALSE_RUN (RW) + * + * the module continues to comsume data, but all the pads are constant, thus no audio out + */ +#define DAO_CTRL_FALSE_RUN_MASK (0x1U) +#define DAO_CTRL_FALSE_RUN_SHIFT (0U) +#define DAO_CTRL_FALSE_RUN_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_RUN_SHIFT) & DAO_CTRL_FALSE_RUN_MASK) +#define DAO_CTRL_FALSE_RUN_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_RUN_MASK) >> DAO_CTRL_FALSE_RUN_SHIFT) + +/* Bitfield definition for register: CMD */ +/* + * SFTRST (RW) + * + * Self-clear + */ +#define DAO_CMD_SFTRST_MASK (0x2U) +#define DAO_CMD_SFTRST_SHIFT (1U) +#define DAO_CMD_SFTRST_SET(x) (((uint32_t)(x) << DAO_CMD_SFTRST_SHIFT) & DAO_CMD_SFTRST_MASK) +#define DAO_CMD_SFTRST_GET(x) (((uint32_t)(x) & DAO_CMD_SFTRST_MASK) >> DAO_CMD_SFTRST_SHIFT) + +/* + * RUN (RW) + * + * Enable this module to run. + */ +#define DAO_CMD_RUN_MASK (0x1U) +#define DAO_CMD_RUN_SHIFT (0U) +#define DAO_CMD_RUN_SET(x) (((uint32_t)(x) << DAO_CMD_RUN_SHIFT) & DAO_CMD_RUN_MASK) +#define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT) + +/* Bitfield definition for register: RX_CFGR */ +/* + * CH_MAX (RW) + * + * CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. + * It must be an even number, so CH_MAX[0] is always 0. + * 4'h2: 2 channels + * 4'h4: 4 channels + * etc + */ +#define DAO_RX_CFGR_CH_MAX_MASK (0x7C0U) +#define DAO_RX_CFGR_CH_MAX_SHIFT (6U) +#define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK) +#define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT) + +/* Bitfield definition for register: RXSLT */ +/* + * EN (RW) + * + * Slot enable for the channels. + */ +#define DAO_RXSLT_EN_MASK (0xFFFFFFFFUL) +#define DAO_RXSLT_EN_SHIFT (0U) +#define DAO_RXSLT_EN_SET(x) (((uint32_t)(x) << DAO_RXSLT_EN_SHIFT) & DAO_RXSLT_EN_MASK) +#define DAO_RXSLT_EN_GET(x) (((uint32_t)(x) & DAO_RXSLT_EN_MASK) >> DAO_RXSLT_EN_SHIFT) + +/* Bitfield definition for register: HPF_MA */ +/* + * COEF (RW) + * + * Composite value of coef A of the Order-1 HPF + */ +#define DAO_HPF_MA_COEF_MASK (0xFFFFFFFFUL) +#define DAO_HPF_MA_COEF_SHIFT (0U) +#define DAO_HPF_MA_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_MA_COEF_SHIFT) & DAO_HPF_MA_COEF_MASK) +#define DAO_HPF_MA_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_MA_COEF_MASK) >> DAO_HPF_MA_COEF_SHIFT) + +/* Bitfield definition for register: HPF_B */ +/* + * COEF (RW) + * + * coef B of the Order-1 HPF + */ +#define DAO_HPF_B_COEF_MASK (0xFFFFFFFFUL) +#define DAO_HPF_B_COEF_SHIFT (0U) +#define DAO_HPF_B_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_B_COEF_SHIFT) & DAO_HPF_B_COEF_MASK) +#define DAO_HPF_B_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_B_COEF_MASK) >> DAO_HPF_B_COEF_SHIFT) + + + + +#endif /* HPM_DAO_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h new file mode 100644 index 0000000000..a4e47861ba --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h @@ -0,0 +1,547 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMA_H +#define HPM_DMA_H + +typedef struct { + __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ + __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ + __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */ + __W uint32_t CHABORT; /* 0x24: Channel Abort Register */ + __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ + __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ + __R uint32_t CHEN; /* 0x34: Channel Enable Register */ + __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ + struct { + __RW uint32_t CTRL; /* 0x40: Channel n Control Register */ + __RW uint32_t TRANSIZE; /* 0x44: Channel n Transfer Size Register */ + __RW uint32_t SRCADDR; /* 0x48: Channel n Source Address Low Part Register */ + __RW uint32_t SRCADDRH; /* 0x4C: Channel n Source Address High Part Register */ + __RW uint32_t DSTADDR; /* 0x50: Channel n Destination Address Low Part Register */ + __RW uint32_t DSTADDRH; /* 0x54: Channel n Destination Address High Part Register */ + __RW uint32_t LLPOINTER; /* 0x58: Channel n Linked List Pointer Low Part Register */ + __RW uint32_t LLPOINTERH; /* 0x5C: Channel n Linked List Pointer High Part Register */ + } CHCTRL[8]; +} DMA_Type; + + +/* Bitfield definition for register: DMACFG */ +/* + * CHAINXFR (RO) + * + * Chain transfer + * 0x0: Chain transfer is not configured + * 0x1: Chain transfer is configured + */ +#define DMA_DMACFG_CHAINXFR_MASK (0x80000000UL) +#define DMA_DMACFG_CHAINXFR_SHIFT (31U) +#define DMA_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHAINXFR_MASK) >> DMA_DMACFG_CHAINXFR_SHIFT) + +/* + * REQSYNC (RO) + * + * DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. + * 0x0: Request synchronization is not configured + * 0x1: Request synchronization is configured + */ +#define DMA_DMACFG_REQSYNC_MASK (0x40000000UL) +#define DMA_DMACFG_REQSYNC_SHIFT (30U) +#define DMA_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQSYNC_MASK) >> DMA_DMACFG_REQSYNC_SHIFT) + +/* + * DATAWIDTH (RO) + * + * AXI bus data width + * 0x0: 32 bits + * 0x1: 64 bits + * 0x2: 128 bits + * 0x3: 256 bits + */ +#define DMA_DMACFG_DATAWIDTH_MASK (0x3000000UL) +#define DMA_DMACFG_DATAWIDTH_SHIFT (24U) +#define DMA_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_DATAWIDTH_MASK) >> DMA_DMACFG_DATAWIDTH_SHIFT) + +/* + * ADDRWIDTH (RO) + * + * AXI bus address width + * 0x18: 24 bits + * 0x19: 25 bits + * ... + * 0x40: 64 bits + * Others: Invalid + */ +#define DMA_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) +#define DMA_DMACFG_ADDRWIDTH_SHIFT (17U) +#define DMA_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_ADDRWIDTH_MASK) >> DMA_DMACFG_ADDRWIDTH_SHIFT) + +/* + * CORENUM (RO) + * + * DMA core number + * 0x0: 1 core + * 0x1: 2 cores + */ +#define DMA_DMACFG_CORENUM_MASK (0x10000UL) +#define DMA_DMACFG_CORENUM_SHIFT (16U) +#define DMA_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CORENUM_MASK) >> DMA_DMACFG_CORENUM_SHIFT) + +/* + * BUSNUM (RO) + * + * AXI bus interface number + * 0x0: 1 AXI bus + * 0x1: 2 AXI busses + */ +#define DMA_DMACFG_BUSNUM_MASK (0x8000U) +#define DMA_DMACFG_BUSNUM_SHIFT (15U) +#define DMA_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_BUSNUM_MASK) >> DMA_DMACFG_BUSNUM_SHIFT) + +/* + * REQNUM (RO) + * + * Request/acknowledge pair number + * 0x0: 0 pair + * 0x1: 1 pair + * 0x2: 2 pairs + * ... + * 0x10: 16 pairs + */ +#define DMA_DMACFG_REQNUM_MASK (0x7C00U) +#define DMA_DMACFG_REQNUM_SHIFT (10U) +#define DMA_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQNUM_MASK) >> DMA_DMACFG_REQNUM_SHIFT) + +/* + * FIFODEPTH (RO) + * + * FIFO depth + * 0x4: 4 entries + * 0x8: 8 entries + * 0x10: 16 entries + * 0x20: 32 entries + * Others: Invalid + */ +#define DMA_DMACFG_FIFODEPTH_MASK (0x3F0U) +#define DMA_DMACFG_FIFODEPTH_SHIFT (4U) +#define DMA_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_FIFODEPTH_MASK) >> DMA_DMACFG_FIFODEPTH_SHIFT) + +/* + * CHANNELNUM (RO) + * + * Channel number + * 0x1: 1 channel + * 0x2: 2 channels + * ... + * 0x8: 8 channels + * Others: Invalid + */ +#define DMA_DMACFG_CHANNELNUM_MASK (0xFU) +#define DMA_DMACFG_CHANNELNUM_SHIFT (0U) +#define DMA_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHANNELNUM_MASK) >> DMA_DMACFG_CHANNELNUM_SHIFT) + +/* Bitfield definition for register: DMACTRL */ +/* + * RESET (WO) + * + * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. + * Note: The software reset may cause the in-completion of AXI transaction. + */ +#define DMA_DMACTRL_RESET_MASK (0x1U) +#define DMA_DMACTRL_RESET_SHIFT (0U) +#define DMA_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMA_DMACTRL_RESET_SHIFT) & DMA_DMACTRL_RESET_MASK) +#define DMA_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMA_DMACTRL_RESET_MASK) >> DMA_DMACTRL_RESET_SHIFT) + +/* Bitfield definition for register: CHABORT */ +/* + * CHABORT (WO) + * + * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + */ +#define DMA_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) +#define DMA_CHABORT_CHABORT_SHIFT (0U) +#define DMA_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMA_CHABORT_CHABORT_SHIFT) & DMA_CHABORT_CHABORT_MASK) +#define DMA_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMA_CHABORT_CHABORT_MASK) >> DMA_CHABORT_CHABORT_SHIFT) + +/* Bitfield definition for register: INTSTATUS */ +/* + * TC (W1C) + * + * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. + * 0x0: Channel n has no terminal count status + * 0x1: Channel n has terminal count status + */ +#define DMA_INTSTATUS_TC_MASK (0xFF0000UL) +#define DMA_INTSTATUS_TC_SHIFT (16U) +#define DMA_INTSTATUS_TC_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_TC_SHIFT) & DMA_INTSTATUS_TC_MASK) +#define DMA_INTSTATUS_TC_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_TC_MASK) >> DMA_INTSTATUS_TC_SHIFT) + +/* + * ABORT (W1C) + * + * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. + * 0x0: Channel n has no abort status + * 0x1: Channel n has abort status + */ +#define DMA_INTSTATUS_ABORT_MASK (0xFF00U) +#define DMA_INTSTATUS_ABORT_SHIFT (8U) +#define DMA_INTSTATUS_ABORT_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ABORT_SHIFT) & DMA_INTSTATUS_ABORT_MASK) +#define DMA_INTSTATUS_ABORT_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ABORT_MASK) >> DMA_INTSTATUS_ABORT_SHIFT) + +/* + * ERROR (W1C) + * + * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: + * - Bus error + * - Unaligned address + * - Unaligned transfer width + * - Reserved configuration + * 0x0: Channel n has no error status + * 0x1: Channel n has error status + */ +#define DMA_INTSTATUS_ERROR_MASK (0xFFU) +#define DMA_INTSTATUS_ERROR_SHIFT (0U) +#define DMA_INTSTATUS_ERROR_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ERROR_SHIFT) & DMA_INTSTATUS_ERROR_MASK) +#define DMA_INTSTATUS_ERROR_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ERROR_MASK) >> DMA_INTSTATUS_ERROR_SHIFT) + +/* Bitfield definition for register: CHEN */ +/* + * CHEN (RO) + * + * Alias of the Enable field of all ChnCtrl registers + */ +#define DMA_CHEN_CHEN_MASK (0xFFFFFFFFUL) +#define DMA_CHEN_CHEN_SHIFT (0U) +#define DMA_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMA_CHEN_CHEN_MASK) >> DMA_CHEN_CHEN_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: CTRL */ +/* + * SRCBUSINFIDX (RW) + * + * Bus interface index that source data is read from + * 0x0: Data is read from bus interface 0 + * 0x1: Data is read from bus interface + */ +#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK (0x80000000UL) +#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT (31U) +#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) +#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) + +/* + * DSTBUSINFIDX (RW) + * + * Bus interface index that destination data is written to + * 0x0: Data is written to bus interface 0 + * 0x1: Data is written to bus interface 1 + */ +#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK (0x40000000UL) +#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT (30U) +#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) +#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) + +/* + * PRIORITY (RW) + * + * Channel priority level + * 0x0: Lower priority + * 0x1: Higher priority + */ +#define DMA_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) +#define DMA_CHCTRL_CTRL_PRIORITY_SHIFT (29U) +#define DMA_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_PRIORITY_SHIFT) & DMA_CHCTRL_CTRL_PRIORITY_MASK) +#define DMA_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_PRIORITY_MASK) >> DMA_CHCTRL_CTRL_PRIORITY_SHIFT) + +/* + * SRCBURSTSIZE (RW) + * + * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. + * The burst transfer byte number is (SrcBurstSize * SrcWidth). + * 0x0: 1 transfer + * 0x1: 2 transfers + * 0x2: 4 transfers + * 0x3: 8 transfers + * 0x4: 16 transfers + * 0x5: 32 transfers + * 0x6: 64 transfers + * 0x7: 128 transfers + * 0x8: 256 transfers + * 0x9:512 transfers + * 0xa: 1024 transfers + * 0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + */ +#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) +#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) +#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) +#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) + +/* + * SRCWIDTH (RW) + * + * Source transfer width + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + * 0x3: Double word transfer + * 0x4: Quad word transfer + * 0x5: Eight word transfer + * 0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + */ +#define DMA_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) +#define DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) +#define DMA_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) +#define DMA_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) + +/* + * DSTWIDTH (RW) + * + * Destination transfer width. + * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. + * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + * 0x3: Double word transfer + * 0x4: Quad word transfer + * 0x5: Eight word transfer + * 0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + */ +#define DMA_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) +#define DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) +#define DMA_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) +#define DMA_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) + +/* + * SRCMODE (RW) + * + * Source DMA handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + */ +#define DMA_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) +#define DMA_CHCTRL_CTRL_SRCMODE_SHIFT (17U) +#define DMA_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCMODE_SHIFT) & DMA_CHCTRL_CTRL_SRCMODE_MASK) +#define DMA_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCMODE_MASK) >> DMA_CHCTRL_CTRL_SRCMODE_SHIFT) + +/* + * DSTMODE (RW) + * + * Destination DMA handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + */ +#define DMA_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) +#define DMA_CHCTRL_CTRL_DSTMODE_SHIFT (16U) +#define DMA_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTMODE_SHIFT) & DMA_CHCTRL_CTRL_DSTMODE_MASK) +#define DMA_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTMODE_MASK) >> DMA_CHCTRL_CTRL_DSTMODE_SHIFT) + +/* + * SRCADDRCTRL (RW) + * + * Source address control + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers the error exception + */ +#define DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) +#define DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) +#define DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) +#define DMA_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) + +/* + * DSTADDRCTRL (RW) + * + * Destination address control + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers the error exception + */ +#define DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) +#define DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) +#define DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) +#define DMA_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) + +/* + * SRCREQSEL (RW) + * + * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + */ +#define DMA_CHCTRL_CTRL_SRCREQSEL_MASK (0xF00U) +#define DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT (8U) +#define DMA_CHCTRL_CTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) +#define DMA_CHCTRL_CTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) >> DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) + +/* + * DSTREQSEL (RW) + * + * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + */ +#define DMA_CHCTRL_CTRL_DSTREQSEL_MASK (0xF0U) +#define DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT (4U) +#define DMA_CHCTRL_CTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) +#define DMA_CHCTRL_CTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) >> DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) + +/* + * INTABTMASK (RW) + * + * Channel abort interrupt mask + * 0x0: Allow the abort interrupt to be triggered + * 0x1: Disable the abort interrupt + */ +#define DMA_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) +#define DMA_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) +#define DMA_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) +#define DMA_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) >> DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) + +/* + * INTERRMASK (RW) + * + * Channel error interrupt mask + * 0x0: Allow the error interrupt to be triggered + * 0x1: Disable the error interrupt + */ +#define DMA_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) +#define DMA_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) +#define DMA_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) +#define DMA_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) >> DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) + +/* + * INTTCMASK (RW) + * + * Channel terminal count interrupt mask + * 0x0: Allow the terminal count interrupt to be triggered + * 0x1: Disable the terminal count interrupt + */ +#define DMA_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) +#define DMA_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) +#define DMA_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) +#define DMA_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) >> DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) + +/* + * ENABLE (RW) + * + * Channel enable bit + * 0x0: Disable + * 0x1: Enable + */ +#define DMA_CHCTRL_CTRL_ENABLE_MASK (0x1U) +#define DMA_CHCTRL_CTRL_ENABLE_SHIFT (0U) +#define DMA_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_ENABLE_SHIFT) & DMA_CHCTRL_CTRL_ENABLE_MASK) +#define DMA_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_ENABLE_MASK) >> DMA_CHCTRL_CTRL_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ +/* + * TRANSIZE (RW) + * + * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. + * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + */ +#define DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFFUL) +#define DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) +#define DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) +#define DMA_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: SRCADDR */ +/* + * SRCADDRL (RW) + * + * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. + * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + */ +#define DMA_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) +#define DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) +#define DMA_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) +#define DMA_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: SRCADDRH */ +/* + * SRCADDRH (RW) + * + * High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. + * This register exists only when the address bus width is wider than 32 bits. + */ +#define DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK (0xFFFFFFFFUL) +#define DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT (0U) +#define DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) +#define DMA_CHCTRL_SRCADDRH_SRCADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) >> DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: DSTADDR */ +/* + * DSTADDRL (RW) + * + * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. + * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + */ +#define DMA_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) +#define DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) +#define DMA_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) +#define DMA_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: DSTADDRH */ +/* + * DSTADDRH (RW) + * + * High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. + * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + * This register exists only when the address bus width is wider than 32 bits. + */ +#define DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK (0xFFFFFFFFUL) +#define DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT (0U) +#define DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) +#define DMA_CHCTRL_DSTADDRH_DSTADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) >> DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ +/* + * LLPOINTERL (RW) + * + * Low part of the pointer to the next descriptor. The pointer must be double word aligned. + */ +#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) +#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) +#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) +#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) + +/* + * LLDBUSINFIDX (RW) + * + * Bus interface index that the next descriptor is read from + * 0x0: The next descriptor is read from bus interface 0 + */ +#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK (0x1U) +#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT (0U) +#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) +#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) >> DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: LLPOINTERH */ +/* + * LLPOINTERH (RW) + * + * High part of the pointer to the next descriptor. + * This register exists only when the address bus width is wider than 32 bits. + */ +#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK (0xFFFFFFFFUL) +#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT (0U) +#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) +#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) >> DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) + + + +/* CHCTRL register group index macro definition */ +#define DMA_CHCTRL_CH0 (0UL) +#define DMA_CHCTRL_CH1 (1UL) +#define DMA_CHCTRL_CH2 (2UL) +#define DMA_CHCTRL_CH3 (3UL) +#define DMA_CHCTRL_CH4 (4UL) +#define DMA_CHCTRL_CH5 (5UL) +#define DMA_CHCTRL_CH6 (6UL) +#define DMA_CHCTRL_CH7 (7UL) + + +#endif /* HPM_DMA_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmamux_regs.h new file mode 100644 index 0000000000..25ccad5e55 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmamux_regs.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_H +#define HPM_DMAMUX_H + +typedef struct { + __RW uint32_t MUXCFG[16]; /* 0x0 - 0x3C: HDMA MUX0 Configuration */ +} DMAMUX_Type; + + +/* Bitfield definition for register array: MUXCFG */ +/* + * ENABLE (RW) + * + * DMA Mux Channel Enable + * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be + * used to disable or reconfigure a DMA channel. + * 0b - DMA Mux channel is disabled + * 1b - DMA Mux channel is enabled + */ +#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) +#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) +#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) +#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) + +/* + * SOURCE (RW) + * + * DMA Channel Source + * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + */ +#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) +#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) +#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) + + + +/* MUXCFG register group index macro definition */ +#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) +#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) +#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) +#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) +#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) +#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) +#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) +#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) +#define DMAMUX_MUXCFG_XDMA_MUX0 (8UL) +#define DMAMUX_MUXCFG_XDMA_MUX1 (9UL) +#define DMAMUX_MUXCFG_XDMA_MUX2 (10UL) +#define DMAMUX_MUXCFG_XDMA_MUX3 (11UL) +#define DMAMUX_MUXCFG_XDMA_MUX4 (12UL) +#define DMAMUX_MUXCFG_XDMA_MUX5 (13UL) +#define DMAMUX_MUXCFG_XDMA_MUX6 (14UL) +#define DMAMUX_MUXCFG_XDMA_MUX7 (15UL) + + +#endif /* HPM_DMAMUX_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h new file mode 100644 index 0000000000..1adf537812 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h @@ -0,0 +1,834 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DRAM_H +#define HPM_DRAM_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: Control Register */ + __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ + __RW uint32_t BMW0; /* 0x8: Bus (AXI) Weight Control Register 0 */ + __RW uint32_t BMW1; /* 0xC: Bus (AXI) Weight Control Register 1 */ + __RW uint32_t BR[2]; /* 0x10 - 0x14: Base Register 0 (for SDRAM CS0 device) */ + __R uint8_t RESERVED1[32]; /* 0x18 - 0x37: Reserved */ + __RW uint32_t INTEN; /* 0x38: Interrupt Enable Register */ + __W uint32_t INTR; /* 0x3C: Interrupt Status Register */ + __RW uint32_t SDRCTRL0; /* 0x40: SDRAM Control Register 0 */ + __RW uint32_t SDRCTRL1; /* 0x44: SDRAM Control Register 1 */ + __RW uint32_t SDRCTRL2; /* 0x48: SDRAM Control Register 2 */ + __RW uint32_t SDRCTRL3; /* 0x4C: SDRAM Control Register 3 */ + __R uint8_t RESERVED2[64]; /* 0x50 - 0x8F: Reserved */ + __RW uint32_t SADDR; /* 0x90: IP Command Control Register 0 */ + __RW uint32_t DATSZ; /* 0x94: IP Command Control Register 1 */ + __RW uint32_t BYTEMSK; /* 0x98: IP Command Control Register 2 */ + __RW uint32_t IPCMD; /* 0x9C: IP Command Register */ + __RW uint32_t IPTX; /* 0xA0: TX DATA Register */ + __R uint8_t RESERVED3[12]; /* 0xA4 - 0xAF: Reserved */ + __RW uint32_t IPRX; /* 0xB0: RX DATA Register */ + __R uint8_t RESERVED4[12]; /* 0xB4 - 0xBF: Reserved */ + __R uint32_t STAT0; /* 0xC0: Status Register 0 */ + __R uint8_t RESERVED5[140]; /* 0xC4 - 0x14F: Reserved */ + __RW uint32_t DLYCFG; /* 0x150: Delay Line Config Register */ +} DRAM_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * BTO (RW) + * + * Bus timeout cycles + * AXI Bus timeout cycle is as following (255*(2^BTO)): + * 00000b - 255*1 + * 00001-11110b - 255*2 - 255*2^30 + * 11111b - 255*2^31 + */ +#define DRAM_CTRL_BTO_MASK (0x1F000000UL) +#define DRAM_CTRL_BTO_SHIFT (24U) +#define DRAM_CTRL_BTO_SET(x) (((uint32_t)(x) << DRAM_CTRL_BTO_SHIFT) & DRAM_CTRL_BTO_MASK) +#define DRAM_CTRL_BTO_GET(x) (((uint32_t)(x) & DRAM_CTRL_BTO_MASK) >> DRAM_CTRL_BTO_SHIFT) + +/* + * CTO (RW) + * + * Command Execution timeout cycles + * When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is + * generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is + * CTO*1024 cycle. + */ +#define DRAM_CTRL_CTO_MASK (0xFF0000UL) +#define DRAM_CTRL_CTO_SHIFT (16U) +#define DRAM_CTRL_CTO_SET(x) (((uint32_t)(x) << DRAM_CTRL_CTO_SHIFT) & DRAM_CTRL_CTO_MASK) +#define DRAM_CTRL_CTO_GET(x) (((uint32_t)(x) & DRAM_CTRL_CTO_MASK) >> DRAM_CTRL_CTO_SHIFT) + +/* + * DQS (RW) + * + * DQS (read strobe) mode + * 0b - Dummy read strobe loopbacked internally + * 1b - Dummy read strobe loopbacked from DQS pad + */ +#define DRAM_CTRL_DQS_MASK (0x4U) +#define DRAM_CTRL_DQS_SHIFT (2U) +#define DRAM_CTRL_DQS_SET(x) (((uint32_t)(x) << DRAM_CTRL_DQS_SHIFT) & DRAM_CTRL_DQS_MASK) +#define DRAM_CTRL_DQS_GET(x) (((uint32_t)(x) & DRAM_CTRL_DQS_MASK) >> DRAM_CTRL_DQS_SHIFT) + +/* + * DIS (RW) + * + * Module Disable + * 0b - Module enabled + * 1b - Module disabled + */ +#define DRAM_CTRL_DIS_MASK (0x2U) +#define DRAM_CTRL_DIS_SHIFT (1U) +#define DRAM_CTRL_DIS_SET(x) (((uint32_t)(x) << DRAM_CTRL_DIS_SHIFT) & DRAM_CTRL_DIS_MASK) +#define DRAM_CTRL_DIS_GET(x) (((uint32_t)(x) & DRAM_CTRL_DIS_MASK) >> DRAM_CTRL_DIS_SHIFT) + +/* + * RST (RW) + * + * Software Reset + * Reset all internal logic in SEMC except configuration register + */ +#define DRAM_CTRL_RST_MASK (0x1U) +#define DRAM_CTRL_RST_SHIFT (0U) +#define DRAM_CTRL_RST_SET(x) (((uint32_t)(x) << DRAM_CTRL_RST_SHIFT) & DRAM_CTRL_RST_MASK) +#define DRAM_CTRL_RST_GET(x) (((uint32_t)(x) & DRAM_CTRL_RST_MASK) >> DRAM_CTRL_RST_SHIFT) + +/* Bitfield definition for register: BMW0 */ +/* + * RWS (RW) + * + * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is + * same as current executing command with read/write operation switch. + */ +#define DRAM_BMW0_RWS_MASK (0xFF0000UL) +#define DRAM_BMW0_RWS_SHIFT (16U) +#define DRAM_BMW0_RWS_SET(x) (((uint32_t)(x) << DRAM_BMW0_RWS_SHIFT) & DRAM_BMW0_RWS_MASK) +#define DRAM_BMW0_RWS_GET(x) (((uint32_t)(x) & DRAM_BMW0_RWS_MASK) >> DRAM_BMW0_RWS_SHIFT) + +/* + * SH (RW) + * + * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is + * same as current executing command without read/write operation switch. + */ +#define DRAM_BMW0_SH_MASK (0xFF00U) +#define DRAM_BMW0_SH_SHIFT (8U) +#define DRAM_BMW0_SH_SET(x) (((uint32_t)(x) << DRAM_BMW0_SH_SHIFT) & DRAM_BMW0_SH_MASK) +#define DRAM_BMW0_SH_GET(x) (((uint32_t)(x) & DRAM_BMW0_SH_MASK) >> DRAM_BMW0_SH_SHIFT) + +/* + * AGE (RW) + * + * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is + * multiplied by WAGE to get weight score. + */ +#define DRAM_BMW0_AGE_MASK (0xF0U) +#define DRAM_BMW0_AGE_SHIFT (4U) +#define DRAM_BMW0_AGE_SET(x) (((uint32_t)(x) << DRAM_BMW0_AGE_SHIFT) & DRAM_BMW0_AGE_MASK) +#define DRAM_BMW0_AGE_GET(x) (((uint32_t)(x) & DRAM_BMW0_AGE_MASK) >> DRAM_BMW0_AGE_SHIFT) + +/* + * QOS (RW) + * + * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator + * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS + * is multiplied by WQOS to get weight score. + */ +#define DRAM_BMW0_QOS_MASK (0xFU) +#define DRAM_BMW0_QOS_SHIFT (0U) +#define DRAM_BMW0_QOS_SET(x) (((uint32_t)(x) << DRAM_BMW0_QOS_SHIFT) & DRAM_BMW0_QOS_MASK) +#define DRAM_BMW0_QOS_GET(x) (((uint32_t)(x) & DRAM_BMW0_QOS_MASK) >> DRAM_BMW0_QOS_SHIFT) + +/* Bitfield definition for register: BMW1 */ +/* + * BR (RW) + * + * Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current + * executing command. + */ +#define DRAM_BMW1_BR_MASK (0xFF000000UL) +#define DRAM_BMW1_BR_SHIFT (24U) +#define DRAM_BMW1_BR_SET(x) (((uint32_t)(x) << DRAM_BMW1_BR_SHIFT) & DRAM_BMW1_BR_MASK) +#define DRAM_BMW1_BR_GET(x) (((uint32_t)(x) & DRAM_BMW1_BR_MASK) >> DRAM_BMW1_BR_SHIFT) + +/* + * RWS (RW) + * + * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is + * same as current executing command with read/write operation switch. + */ +#define DRAM_BMW1_RWS_MASK (0xFF0000UL) +#define DRAM_BMW1_RWS_SHIFT (16U) +#define DRAM_BMW1_RWS_SET(x) (((uint32_t)(x) << DRAM_BMW1_RWS_SHIFT) & DRAM_BMW1_RWS_MASK) +#define DRAM_BMW1_RWS_GET(x) (((uint32_t)(x) & DRAM_BMW1_RWS_MASK) >> DRAM_BMW1_RWS_SHIFT) + +/* + * PH (RW) + * + * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is + * same as current executing command without read/write operation switch. + */ +#define DRAM_BMW1_PH_MASK (0xFF00U) +#define DRAM_BMW1_PH_SHIFT (8U) +#define DRAM_BMW1_PH_SET(x) (((uint32_t)(x) << DRAM_BMW1_PH_SHIFT) & DRAM_BMW1_PH_MASK) +#define DRAM_BMW1_PH_GET(x) (((uint32_t)(x) & DRAM_BMW1_PH_MASK) >> DRAM_BMW1_PH_SHIFT) + +/* + * AGE (RW) + * + * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is + * multiplied by WAGE to get weight score. + */ +#define DRAM_BMW1_AGE_MASK (0xF0U) +#define DRAM_BMW1_AGE_SHIFT (4U) +#define DRAM_BMW1_AGE_SET(x) (((uint32_t)(x) << DRAM_BMW1_AGE_SHIFT) & DRAM_BMW1_AGE_MASK) +#define DRAM_BMW1_AGE_GET(x) (((uint32_t)(x) & DRAM_BMW1_AGE_MASK) >> DRAM_BMW1_AGE_SHIFT) + +/* + * QOS (RW) + * + * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator + * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS + * is multiplied by WQOS to get weight score. + */ +#define DRAM_BMW1_QOS_MASK (0xFU) +#define DRAM_BMW1_QOS_SHIFT (0U) +#define DRAM_BMW1_QOS_SET(x) (((uint32_t)(x) << DRAM_BMW1_QOS_SHIFT) & DRAM_BMW1_QOS_MASK) +#define DRAM_BMW1_QOS_GET(x) (((uint32_t)(x) & DRAM_BMW1_QOS_MASK) >> DRAM_BMW1_QOS_SHIFT) + +/* Bitfield definition for register array: BR */ +/* + * BASE (RW) + * + * Base Address + * This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low + * position 12 bits are all zero. + */ +#define DRAM_BR_BASE_MASK (0xFFFFF000UL) +#define DRAM_BR_BASE_SHIFT (12U) +#define DRAM_BR_BASE_SET(x) (((uint32_t)(x) << DRAM_BR_BASE_SHIFT) & DRAM_BR_BASE_MASK) +#define DRAM_BR_BASE_GET(x) (((uint32_t)(x) & DRAM_BR_BASE_MASK) >> DRAM_BR_BASE_SHIFT) + +/* + * SIZE (RW) + * + * Memory size + * 00000b - 4KB + * 00001b - 8KB + * 00010b - 16KB + * 00011b - 32KB + * 00100b - 64KB + * 00101b - 128KB + * 00110b - 256KB + * 00111b - 512KB + * 01000b - 1MB + * 01001b - 2MB + * 01010b - 4MB + * 01011b - 8MB + * 01100b - 16MB + * 01101b - 32MB + * 01110b - 64MB + * 01111b - 128MB + * 10000b - 256MB + * 10001b - 512MB + * 10010b - 1GB + * 10011b - 2GB + * 10100-11111b - 4GB + */ +#define DRAM_BR_SIZE_MASK (0x3EU) +#define DRAM_BR_SIZE_SHIFT (1U) +#define DRAM_BR_SIZE_SET(x) (((uint32_t)(x) << DRAM_BR_SIZE_SHIFT) & DRAM_BR_SIZE_MASK) +#define DRAM_BR_SIZE_GET(x) (((uint32_t)(x) & DRAM_BR_SIZE_MASK) >> DRAM_BR_SIZE_SHIFT) + +/* + * VLD (RW) + * + * Valid + */ +#define DRAM_BR_VLD_MASK (0x1U) +#define DRAM_BR_VLD_SHIFT (0U) +#define DRAM_BR_VLD_SET(x) (((uint32_t)(x) << DRAM_BR_VLD_SHIFT) & DRAM_BR_VLD_MASK) +#define DRAM_BR_VLD_GET(x) (((uint32_t)(x) & DRAM_BR_VLD_MASK) >> DRAM_BR_VLD_SHIFT) + +/* Bitfield definition for register: INTEN */ +/* + * AXIBUSERR (RW) + * + * AXI BUS error interrupt enable + * 0b - Interrupt is disabled + * 1b - Interrupt is enabled + */ +#define DRAM_INTEN_AXIBUSERR_MASK (0x8U) +#define DRAM_INTEN_AXIBUSERR_SHIFT (3U) +#define DRAM_INTEN_AXIBUSERR_SET(x) (((uint32_t)(x) << DRAM_INTEN_AXIBUSERR_SHIFT) & DRAM_INTEN_AXIBUSERR_MASK) +#define DRAM_INTEN_AXIBUSERR_GET(x) (((uint32_t)(x) & DRAM_INTEN_AXIBUSERR_MASK) >> DRAM_INTEN_AXIBUSERR_SHIFT) + +/* + * AXICMDERR (RW) + * + * AXI command error interrupt enable + * 0b - Interrupt is disabled + * 1b - Interrupt is enabled + */ +#define DRAM_INTEN_AXICMDERR_MASK (0x4U) +#define DRAM_INTEN_AXICMDERR_SHIFT (2U) +#define DRAM_INTEN_AXICMDERR_SET(x) (((uint32_t)(x) << DRAM_INTEN_AXICMDERR_SHIFT) & DRAM_INTEN_AXICMDERR_MASK) +#define DRAM_INTEN_AXICMDERR_GET(x) (((uint32_t)(x) & DRAM_INTEN_AXICMDERR_MASK) >> DRAM_INTEN_AXICMDERR_SHIFT) + +/* + * IPCMDERR (RW) + * + * IP command error interrupt enable + * 0b - Interrupt is disabled + * 1b - Interrupt is enabled + */ +#define DRAM_INTEN_IPCMDERR_MASK (0x2U) +#define DRAM_INTEN_IPCMDERR_SHIFT (1U) +#define DRAM_INTEN_IPCMDERR_SET(x) (((uint32_t)(x) << DRAM_INTEN_IPCMDERR_SHIFT) & DRAM_INTEN_IPCMDERR_MASK) +#define DRAM_INTEN_IPCMDERR_GET(x) (((uint32_t)(x) & DRAM_INTEN_IPCMDERR_MASK) >> DRAM_INTEN_IPCMDERR_SHIFT) + +/* + * IPCMDDONE (RW) + * + * IP command done interrupt enable + * 0b - Interrupt is disabled + * 1b - Interrupt is enabled + */ +#define DRAM_INTEN_IPCMDDONE_MASK (0x1U) +#define DRAM_INTEN_IPCMDDONE_SHIFT (0U) +#define DRAM_INTEN_IPCMDDONE_SET(x) (((uint32_t)(x) << DRAM_INTEN_IPCMDDONE_SHIFT) & DRAM_INTEN_IPCMDDONE_MASK) +#define DRAM_INTEN_IPCMDDONE_GET(x) (((uint32_t)(x) & DRAM_INTEN_IPCMDDONE_MASK) >> DRAM_INTEN_IPCMDDONE_SHIFT) + +/* Bitfield definition for register: INTR */ +/* + * AXIBUSERR (W1C) + * + * AXI bus error interrupt + * AXI Bus error interrupt is generated in following cases: + * • AXI address is invalid + * • AXI 8-bit or 16-bit WRAP write/read + */ +#define DRAM_INTR_AXIBUSERR_MASK (0x8U) +#define DRAM_INTR_AXIBUSERR_SHIFT (3U) +#define DRAM_INTR_AXIBUSERR_SET(x) (((uint32_t)(x) << DRAM_INTR_AXIBUSERR_SHIFT) & DRAM_INTR_AXIBUSERR_MASK) +#define DRAM_INTR_AXIBUSERR_GET(x) (((uint32_t)(x) & DRAM_INTR_AXIBUSERR_MASK) >> DRAM_INTR_AXIBUSERR_SHIFT) + +/* + * AXICMDERR (W1C) + * + * AXI command error interrupt + * AXI command error interrupt is generated when AXI command execution timeout. + */ +#define DRAM_INTR_AXICMDERR_MASK (0x4U) +#define DRAM_INTR_AXICMDERR_SHIFT (2U) +#define DRAM_INTR_AXICMDERR_SET(x) (((uint32_t)(x) << DRAM_INTR_AXICMDERR_SHIFT) & DRAM_INTR_AXICMDERR_MASK) +#define DRAM_INTR_AXICMDERR_GET(x) (((uint32_t)(x) & DRAM_INTR_AXICMDERR_MASK) >> DRAM_INTR_AXICMDERR_SHIFT) + +/* + * IPCMDERR (W1C) + * + * IP command error done interrupt + * IP command error interrupt is generated in following case: + * • IP Command Address target invalid device space + * • IP Command Code unsupported + * • IP Command triggered when previous command + */ +#define DRAM_INTR_IPCMDERR_MASK (0x2U) +#define DRAM_INTR_IPCMDERR_SHIFT (1U) +#define DRAM_INTR_IPCMDERR_SET(x) (((uint32_t)(x) << DRAM_INTR_IPCMDERR_SHIFT) & DRAM_INTR_IPCMDERR_MASK) +#define DRAM_INTR_IPCMDERR_GET(x) (((uint32_t)(x) & DRAM_INTR_IPCMDERR_MASK) >> DRAM_INTR_IPCMDERR_SHIFT) + +/* + * IPCMDDONE (W1C) + * + * IP command normal done interrupt + */ +#define DRAM_INTR_IPCMDDONE_MASK (0x1U) +#define DRAM_INTR_IPCMDDONE_SHIFT (0U) +#define DRAM_INTR_IPCMDDONE_SET(x) (((uint32_t)(x) << DRAM_INTR_IPCMDDONE_SHIFT) & DRAM_INTR_IPCMDDONE_MASK) +#define DRAM_INTR_IPCMDDONE_GET(x) (((uint32_t)(x) & DRAM_INTR_IPCMDDONE_MASK) >> DRAM_INTR_IPCMDDONE_SHIFT) + +/* Bitfield definition for register: SDRCTRL0 */ +/* + * BANK2 (RW) + * + * 2 Bank selection bit + * 0b - SDRAM device has 4 banks. + * 1b - SDRAM device has 2 banks. + */ +#define DRAM_SDRCTRL0_BANK2_MASK (0x4000U) +#define DRAM_SDRCTRL0_BANK2_SHIFT (14U) +#define DRAM_SDRCTRL0_BANK2_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_BANK2_SHIFT) & DRAM_SDRCTRL0_BANK2_MASK) +#define DRAM_SDRCTRL0_BANK2_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_BANK2_MASK) >> DRAM_SDRCTRL0_BANK2_SHIFT) + +/* + * CAS (RW) + * + * CAS Latency + * 00b - 1 + * 01b - 1 + * 10b - 2 + * 11b - 3 + */ +#define DRAM_SDRCTRL0_CAS_MASK (0xC00U) +#define DRAM_SDRCTRL0_CAS_SHIFT (10U) +#define DRAM_SDRCTRL0_CAS_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_CAS_SHIFT) & DRAM_SDRCTRL0_CAS_MASK) +#define DRAM_SDRCTRL0_CAS_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_CAS_MASK) >> DRAM_SDRCTRL0_CAS_SHIFT) + +/* + * COL (RW) + * + * Column address bit number + * 00b - 12 bit + * 01b - 11 bit + * 10b - 10 bit + * 11b - 9 bit + */ +#define DRAM_SDRCTRL0_COL_MASK (0x300U) +#define DRAM_SDRCTRL0_COL_SHIFT (8U) +#define DRAM_SDRCTRL0_COL_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_COL_SHIFT) & DRAM_SDRCTRL0_COL_MASK) +#define DRAM_SDRCTRL0_COL_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_COL_MASK) >> DRAM_SDRCTRL0_COL_SHIFT) + +/* + * COL8 (RW) + * + * Column 8 selection bit + * 0b - Column address bit number is decided by COL field. + * 1b - Column address bit number is 8. COL field is ignored. + */ +#define DRAM_SDRCTRL0_COL8_MASK (0x80U) +#define DRAM_SDRCTRL0_COL8_SHIFT (7U) +#define DRAM_SDRCTRL0_COL8_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_COL8_SHIFT) & DRAM_SDRCTRL0_COL8_MASK) +#define DRAM_SDRCTRL0_COL8_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_COL8_MASK) >> DRAM_SDRCTRL0_COL8_SHIFT) + +/* + * BURSTLEN (RW) + * + * Burst Length + * 000b - 1 + * 001b - 2 + * 010b - 4 + * 011b - 8 + * 100b - 8 + * 101b - 8 + * 110b - 8 + * 111b - 8 + */ +#define DRAM_SDRCTRL0_BURSTLEN_MASK (0x70U) +#define DRAM_SDRCTRL0_BURSTLEN_SHIFT (4U) +#define DRAM_SDRCTRL0_BURSTLEN_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_BURSTLEN_SHIFT) & DRAM_SDRCTRL0_BURSTLEN_MASK) +#define DRAM_SDRCTRL0_BURSTLEN_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_BURSTLEN_MASK) >> DRAM_SDRCTRL0_BURSTLEN_SHIFT) + +/* + * HIGHBAND (RW) + * + * high band select + * 0: use data[15:0] for 16bit SDRAM; + * 1: use data[31:16] for 16bit SDRAM; + * only used when Port Size is 16bit(PORTSZ=01b) + */ +#define DRAM_SDRCTRL0_HIGHBAND_MASK (0x8U) +#define DRAM_SDRCTRL0_HIGHBAND_SHIFT (3U) +#define DRAM_SDRCTRL0_HIGHBAND_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_HIGHBAND_SHIFT) & DRAM_SDRCTRL0_HIGHBAND_MASK) +#define DRAM_SDRCTRL0_HIGHBAND_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_HIGHBAND_MASK) >> DRAM_SDRCTRL0_HIGHBAND_SHIFT) + +/* + * PORTSZ (RW) + * + * Port Size + * 00b - 8bit + * 01b - 16bit + * 10b - 32bit + */ +#define DRAM_SDRCTRL0_PORTSZ_MASK (0x3U) +#define DRAM_SDRCTRL0_PORTSZ_SHIFT (0U) +#define DRAM_SDRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_PORTSZ_SHIFT) & DRAM_SDRCTRL0_PORTSZ_MASK) +#define DRAM_SDRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_PORTSZ_MASK) >> DRAM_SDRCTRL0_PORTSZ_SHIFT) + +/* Bitfield definition for register: SDRCTRL1 */ +/* + * ACT2PRE (RW) + * + * ACT to Precharge minimum time + * It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. + */ +#define DRAM_SDRCTRL1_ACT2PRE_MASK (0xF00000UL) +#define DRAM_SDRCTRL1_ACT2PRE_SHIFT (20U) +#define DRAM_SDRCTRL1_ACT2PRE_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_ACT2PRE_SHIFT) & DRAM_SDRCTRL1_ACT2PRE_MASK) +#define DRAM_SDRCTRL1_ACT2PRE_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_ACT2PRE_MASK) >> DRAM_SDRCTRL1_ACT2PRE_SHIFT) + +/* + * CKEOFF (RW) + * + * CKE OFF minimum time + * It is promised clock suspend last at leat CKEOFF+1 clock cycles. + */ +#define DRAM_SDRCTRL1_CKEOFF_MASK (0xF0000UL) +#define DRAM_SDRCTRL1_CKEOFF_SHIFT (16U) +#define DRAM_SDRCTRL1_CKEOFF_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_CKEOFF_SHIFT) & DRAM_SDRCTRL1_CKEOFF_MASK) +#define DRAM_SDRCTRL1_CKEOFF_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_CKEOFF_MASK) >> DRAM_SDRCTRL1_CKEOFF_SHIFT) + +/* + * WRC (RW) + * + * Write recovery time + * It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. + */ +#define DRAM_SDRCTRL1_WRC_MASK (0xE000U) +#define DRAM_SDRCTRL1_WRC_SHIFT (13U) +#define DRAM_SDRCTRL1_WRC_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_WRC_SHIFT) & DRAM_SDRCTRL1_WRC_MASK) +#define DRAM_SDRCTRL1_WRC_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_WRC_MASK) >> DRAM_SDRCTRL1_WRC_SHIFT) + +/* + * RFRC (RW) + * + * Refresh recovery time + * It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. + */ +#define DRAM_SDRCTRL1_RFRC_MASK (0x1F00U) +#define DRAM_SDRCTRL1_RFRC_SHIFT (8U) +#define DRAM_SDRCTRL1_RFRC_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_RFRC_SHIFT) & DRAM_SDRCTRL1_RFRC_MASK) +#define DRAM_SDRCTRL1_RFRC_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_RFRC_MASK) >> DRAM_SDRCTRL1_RFRC_SHIFT) + +/* + * ACT2RW (RW) + * + * ACT to Read/Write wait time + * It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. + */ +#define DRAM_SDRCTRL1_ACT2RW_MASK (0xF0U) +#define DRAM_SDRCTRL1_ACT2RW_SHIFT (4U) +#define DRAM_SDRCTRL1_ACT2RW_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_ACT2RW_SHIFT) & DRAM_SDRCTRL1_ACT2RW_MASK) +#define DRAM_SDRCTRL1_ACT2RW_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_ACT2RW_MASK) >> DRAM_SDRCTRL1_ACT2RW_SHIFT) + +/* + * PRE2ACT (RW) + * + * PRECHARGE to ACT/Refresh wait time + * It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. + */ +#define DRAM_SDRCTRL1_PRE2ACT_MASK (0xFU) +#define DRAM_SDRCTRL1_PRE2ACT_SHIFT (0U) +#define DRAM_SDRCTRL1_PRE2ACT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_PRE2ACT_SHIFT) & DRAM_SDRCTRL1_PRE2ACT_MASK) +#define DRAM_SDRCTRL1_PRE2ACT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_PRE2ACT_MASK) >> DRAM_SDRCTRL1_PRE2ACT_SHIFT) + +/* Bitfield definition for register: SDRCTRL2 */ +/* + * ITO (RW) + * + * SDRAM Idle timeout + * It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is + * considered idle when there is no AXI Bus transfer and no SDRAM command pending. + * 00000000b - IDLE timeout period is 256*Prescale period. + * 00000001-11111111b - IDLE timeout period is ITO*Prescale period. + */ +#define DRAM_SDRCTRL2_ITO_MASK (0xFF000000UL) +#define DRAM_SDRCTRL2_ITO_SHIFT (24U) +#define DRAM_SDRCTRL2_ITO_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_ITO_SHIFT) & DRAM_SDRCTRL2_ITO_MASK) +#define DRAM_SDRCTRL2_ITO_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_ITO_MASK) >> DRAM_SDRCTRL2_ITO_SHIFT) + +/* + * ACT2ACT (RW) + * + * ACT to ACT wait time + * It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This + * could help to meet tRRD timing requirement by SDRAM device. + */ +#define DRAM_SDRCTRL2_ACT2ACT_MASK (0xFF0000UL) +#define DRAM_SDRCTRL2_ACT2ACT_SHIFT (16U) +#define DRAM_SDRCTRL2_ACT2ACT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_ACT2ACT_SHIFT) & DRAM_SDRCTRL2_ACT2ACT_MASK) +#define DRAM_SDRCTRL2_ACT2ACT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_ACT2ACT_MASK) >> DRAM_SDRCTRL2_ACT2ACT_SHIFT) + +/* + * REF2REF (RW) + * + * Refresh to Refresh wait time + * It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. + * This could help to meet tRFC timing requirement by SDRAM device. + */ +#define DRAM_SDRCTRL2_REF2REF_MASK (0xFF00U) +#define DRAM_SDRCTRL2_REF2REF_SHIFT (8U) +#define DRAM_SDRCTRL2_REF2REF_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_REF2REF_SHIFT) & DRAM_SDRCTRL2_REF2REF_MASK) +#define DRAM_SDRCTRL2_REF2REF_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_REF2REF_MASK) >> DRAM_SDRCTRL2_REF2REF_SHIFT) + +/* + * SRRC (RW) + * + * Self Refresh Recovery time + * It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. + */ +#define DRAM_SDRCTRL2_SRRC_MASK (0xFFU) +#define DRAM_SDRCTRL2_SRRC_SHIFT (0U) +#define DRAM_SDRCTRL2_SRRC_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_SRRC_SHIFT) & DRAM_SDRCTRL2_SRRC_MASK) +#define DRAM_SDRCTRL2_SRRC_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_SRRC_MASK) >> DRAM_SDRCTRL2_SRRC_SHIFT) + +/* Bitfield definition for register: SDRCTRL3 */ +/* + * UT (RW) + * + * Refresh urgent threshold + * Internal refresh request is generated on every Refresh period. Before internal request timer count up to + * urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh + * request is handled in lower priority than any pending AXI command or IP command to SDRAM device. + * When internal request timer count up to this urgent threshold, refresh request is considered as urgent + * refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP + * command to SDRAM device. + * NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as + * urgent refresh request. + * Refresh urgent threshold is as follwoing: + * 00000000b - 256*Prescaler period + * 00000001-11111111b - UT*Prescaler period + */ +#define DRAM_SDRCTRL3_UT_MASK (0xFF000000UL) +#define DRAM_SDRCTRL3_UT_SHIFT (24U) +#define DRAM_SDRCTRL3_UT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_UT_SHIFT) & DRAM_SDRCTRL3_UT_MASK) +#define DRAM_SDRCTRL3_UT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_UT_MASK) >> DRAM_SDRCTRL3_UT_SHIFT) + +/* + * RT (RW) + * + * Refresh timer period + * Refresh timer period is as following: + * 00000000b - 256*Prescaler period + * 00000001-11111111b - RT*Prescaler period + */ +#define DRAM_SDRCTRL3_RT_MASK (0xFF0000UL) +#define DRAM_SDRCTRL3_RT_SHIFT (16U) +#define DRAM_SDRCTRL3_RT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_RT_SHIFT) & DRAM_SDRCTRL3_RT_MASK) +#define DRAM_SDRCTRL3_RT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_RT_MASK) >> DRAM_SDRCTRL3_RT_SHIFT) + +/* + * PRESCALE (RW) + * + * Prescaler timer period + * Prescaler timer period is as following: + * 00000000b - 256*16 clock cycles + * 00000001-11111111b - PRESCALE*16 clock cycles + */ +#define DRAM_SDRCTRL3_PRESCALE_MASK (0xFF00U) +#define DRAM_SDRCTRL3_PRESCALE_SHIFT (8U) +#define DRAM_SDRCTRL3_PRESCALE_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_PRESCALE_SHIFT) & DRAM_SDRCTRL3_PRESCALE_MASK) +#define DRAM_SDRCTRL3_PRESCALE_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_PRESCALE_MASK) >> DRAM_SDRCTRL3_PRESCALE_SHIFT) + +/* + * REBL (RW) + * + * Refresh burst length + * It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The + * number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. + * 000b - 1 + * 001b - 2 + * 010b - 3 + * 011b - 4 + * 100b - 5 + * 101b - 6 + * 110b - 7 + * 111b - 8 + */ +#define DRAM_SDRCTRL3_REBL_MASK (0xEU) +#define DRAM_SDRCTRL3_REBL_SHIFT (1U) +#define DRAM_SDRCTRL3_REBL_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_REBL_SHIFT) & DRAM_SDRCTRL3_REBL_MASK) +#define DRAM_SDRCTRL3_REBL_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_REBL_MASK) >> DRAM_SDRCTRL3_REBL_SHIFT) + +/* + * REN (RW) + * + * Refresh enable + */ +#define DRAM_SDRCTRL3_REN_MASK (0x1U) +#define DRAM_SDRCTRL3_REN_SHIFT (0U) +#define DRAM_SDRCTRL3_REN_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_REN_SHIFT) & DRAM_SDRCTRL3_REN_MASK) +#define DRAM_SDRCTRL3_REN_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_REN_MASK) >> DRAM_SDRCTRL3_REN_SHIFT) + +/* Bitfield definition for register: SADDR */ +/* + * SA (RW) + * + * Slave address + */ +#define DRAM_SADDR_SA_MASK (0xFFFFFFFFUL) +#define DRAM_SADDR_SA_SHIFT (0U) +#define DRAM_SADDR_SA_SET(x) (((uint32_t)(x) << DRAM_SADDR_SA_SHIFT) & DRAM_SADDR_SA_MASK) +#define DRAM_SADDR_SA_GET(x) (((uint32_t)(x) & DRAM_SADDR_SA_MASK) >> DRAM_SADDR_SA_SHIFT) + +/* Bitfield definition for register: DATSZ */ +/* + * DATSZ (RW) + * + * Data Size in Byte + * When IP command is not a write/read operation, DATSZ field would be ignored. + * 000b - 4 + * 001b - 1 + * 010b - 2 + * 011b - 3 + * 100b - 4 + * 101b - 4 + * 110b - 4 + * 111b - 4 + */ +#define DRAM_DATSZ_DATSZ_MASK (0x7U) +#define DRAM_DATSZ_DATSZ_SHIFT (0U) +#define DRAM_DATSZ_DATSZ_SET(x) (((uint32_t)(x) << DRAM_DATSZ_DATSZ_SHIFT) & DRAM_DATSZ_DATSZ_MASK) +#define DRAM_DATSZ_DATSZ_GET(x) (((uint32_t)(x) & DRAM_DATSZ_DATSZ_MASK) >> DRAM_DATSZ_DATSZ_SHIFT) + +/* Bitfield definition for register: BYTEMSK */ +/* + * BM3 (RW) + * + * Byte Mask for Byte 3 (IPTXD bit 31:24) + * 0b - Byte Unmasked + * 1b - Byte Masked + */ +#define DRAM_BYTEMSK_BM3_MASK (0x8U) +#define DRAM_BYTEMSK_BM3_SHIFT (3U) +#define DRAM_BYTEMSK_BM3_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM3_SHIFT) & DRAM_BYTEMSK_BM3_MASK) +#define DRAM_BYTEMSK_BM3_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM3_MASK) >> DRAM_BYTEMSK_BM3_SHIFT) + +/* + * BM2 (RW) + * + * Byte Mask for Byte 2 (IPTXD bit 23:16) + * 0b - Byte Unmasked + * 1b - Byte Masked + */ +#define DRAM_BYTEMSK_BM2_MASK (0x4U) +#define DRAM_BYTEMSK_BM2_SHIFT (2U) +#define DRAM_BYTEMSK_BM2_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM2_SHIFT) & DRAM_BYTEMSK_BM2_MASK) +#define DRAM_BYTEMSK_BM2_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM2_MASK) >> DRAM_BYTEMSK_BM2_SHIFT) + +/* + * BM1 (RW) + * + * Byte Mask for Byte 1 (IPTXD bit 15:8) + * 0b - Byte Unmasked + * 1b - Byte Masked + */ +#define DRAM_BYTEMSK_BM1_MASK (0x2U) +#define DRAM_BYTEMSK_BM1_SHIFT (1U) +#define DRAM_BYTEMSK_BM1_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM1_SHIFT) & DRAM_BYTEMSK_BM1_MASK) +#define DRAM_BYTEMSK_BM1_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM1_MASK) >> DRAM_BYTEMSK_BM1_SHIFT) + +/* + * BM0 (RW) + * + * Byte Mask for Byte 0 (IPTXD bit 7:0) + * 0b - Byte Unmasked + * 1b - Byte Masked + */ +#define DRAM_BYTEMSK_BM0_MASK (0x1U) +#define DRAM_BYTEMSK_BM0_SHIFT (0U) +#define DRAM_BYTEMSK_BM0_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM0_SHIFT) & DRAM_BYTEMSK_BM0_MASK) +#define DRAM_BYTEMSK_BM0_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM0_MASK) >> DRAM_BYTEMSK_BM0_SHIFT) + +/* Bitfield definition for register: IPCMD */ +/* + * KEY (WO) + * + * This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory + * device is selected by BRx settings and IPCR0 registers. + */ +#define DRAM_IPCMD_KEY_MASK (0xFFFF0000UL) +#define DRAM_IPCMD_KEY_SHIFT (16U) +#define DRAM_IPCMD_KEY_SET(x) (((uint32_t)(x) << DRAM_IPCMD_KEY_SHIFT) & DRAM_IPCMD_KEY_MASK) +#define DRAM_IPCMD_KEY_GET(x) (((uint32_t)(x) & DRAM_IPCMD_KEY_MASK) >> DRAM_IPCMD_KEY_SHIFT) + +/* + * CMD (RW) + * + * SDRAM Commands: + * • 0x8: READ + * • 0x9: WRITE + * • 0xA: MODESET + * • 0xB: ACTIVE + * • 0xC: AUTO REFRESH + * • 0xD: SELF REFRESH + * • 0xE: PRECHARGE + * • 0xF: PRECHARGE ALL + * • Others: RSVD + * NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. + */ +#define DRAM_IPCMD_CMD_MASK (0xFFFFU) +#define DRAM_IPCMD_CMD_SHIFT (0U) +#define DRAM_IPCMD_CMD_SET(x) (((uint32_t)(x) << DRAM_IPCMD_CMD_SHIFT) & DRAM_IPCMD_CMD_MASK) +#define DRAM_IPCMD_CMD_GET(x) (((uint32_t)(x) & DRAM_IPCMD_CMD_MASK) >> DRAM_IPCMD_CMD_SHIFT) + +/* Bitfield definition for register: IPTX */ +/* + * DAT (RW) + * + * Data + */ +#define DRAM_IPTX_DAT_MASK (0xFFFFFFFFUL) +#define DRAM_IPTX_DAT_SHIFT (0U) +#define DRAM_IPTX_DAT_SET(x) (((uint32_t)(x) << DRAM_IPTX_DAT_SHIFT) & DRAM_IPTX_DAT_MASK) +#define DRAM_IPTX_DAT_GET(x) (((uint32_t)(x) & DRAM_IPTX_DAT_MASK) >> DRAM_IPTX_DAT_SHIFT) + +/* Bitfield definition for register: IPRX */ +/* + * DAT (RW) + * + * Data + */ +#define DRAM_IPRX_DAT_MASK (0xFFFFFFFFUL) +#define DRAM_IPRX_DAT_SHIFT (0U) +#define DRAM_IPRX_DAT_SET(x) (((uint32_t)(x) << DRAM_IPRX_DAT_SHIFT) & DRAM_IPRX_DAT_MASK) +#define DRAM_IPRX_DAT_GET(x) (((uint32_t)(x) & DRAM_IPRX_DAT_MASK) >> DRAM_IPRX_DAT_SHIFT) + +/* Bitfield definition for register: STAT0 */ +/* + * IDLE (RO) + * + * Indicating whether it is in IDLE state. + * When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no + * pending device access. + */ +#define DRAM_STAT0_IDLE_MASK (0x1U) +#define DRAM_STAT0_IDLE_SHIFT (0U) +#define DRAM_STAT0_IDLE_GET(x) (((uint32_t)(x) & DRAM_STAT0_IDLE_MASK) >> DRAM_STAT0_IDLE_SHIFT) + +/* Bitfield definition for register: DLYCFG */ +/* + * OE (RW) + * + * delay clock output enable, should be set after setting DLYEN and DLYSEL + */ +#define DRAM_DLYCFG_OE_MASK (0x2000U) +#define DRAM_DLYCFG_OE_SHIFT (13U) +#define DRAM_DLYCFG_OE_SET(x) (((uint32_t)(x) << DRAM_DLYCFG_OE_SHIFT) & DRAM_DLYCFG_OE_MASK) +#define DRAM_DLYCFG_OE_GET(x) (((uint32_t)(x) & DRAM_DLYCFG_OE_MASK) >> DRAM_DLYCFG_OE_SHIFT) + +/* + * DLYSEL (RW) + * + * delay line select, 0 for 1 cell, 31 for all 32 cells + */ +#define DRAM_DLYCFG_DLYSEL_MASK (0x3EU) +#define DRAM_DLYCFG_DLYSEL_SHIFT (1U) +#define DRAM_DLYCFG_DLYSEL_SET(x) (((uint32_t)(x) << DRAM_DLYCFG_DLYSEL_SHIFT) & DRAM_DLYCFG_DLYSEL_MASK) +#define DRAM_DLYCFG_DLYSEL_GET(x) (((uint32_t)(x) & DRAM_DLYCFG_DLYSEL_MASK) >> DRAM_DLYCFG_DLYSEL_SHIFT) + +/* + * DLYEN (RW) + * + * delay line enable + */ +#define DRAM_DLYCFG_DLYEN_MASK (0x1U) +#define DRAM_DLYCFG_DLYEN_SHIFT (0U) +#define DRAM_DLYCFG_DLYEN_SET(x) (((uint32_t)(x) << DRAM_DLYCFG_DLYEN_SHIFT) & DRAM_DLYCFG_DLYEN_MASK) +#define DRAM_DLYCFG_DLYEN_GET(x) (((uint32_t)(x) & DRAM_DLYCFG_DLYEN_MASK) >> DRAM_DLYCFG_DLYEN_SHIFT) + + + +/* BR register group index macro definition */ +#define DRAM_BR_BASE0 (0UL) +#define DRAM_BR_BASE1 (1UL) + + +#endif /* HPM_DRAM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h new file mode 100644 index 0000000000..82508381de --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h @@ -0,0 +1,7008 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_ENET_H +#define HPM_ENET_H + +typedef struct { + __RW uint32_t MACCFG; /* 0x0: MAC Configuration Register */ + __RW uint32_t MACFF; /* 0x4: MAC Frame Filter */ + __RW uint32_t HASH_H; /* 0x8: Hash Table High Register */ + __RW uint32_t HASH_L; /* 0xC: Hash Table Low Register */ + __RW uint32_t GMII_ADDR; /* 0x10: GMII Address Register */ + __RW uint32_t GMII_DATA; /* 0x14: GMII Data Register */ + __RW uint32_t FLOWCTRL; /* 0x18: Flow Control Register */ + __RW uint32_t VLAN_TAG; /* 0x1C: VLAN Tag Register */ + __R uint32_t VERSION; /* 0x20: Version Register */ + __R uint32_t DEBUGGING; /* 0x24: Debug Register */ + __RW uint32_t RWKFRMFILT; /* 0x28: Remote Wake-Up Frame Filter Register */ + __RW uint32_t PMT_CSR; /* 0x2C: PMT Control and Status Register */ + __RW uint32_t LPI_CSR; /* 0x30: LPI Control and Status Regsiter */ + __RW uint32_t LPI_TCR; /* 0x34: LPI Timers Control Register */ + __R uint32_t INTR_STATUS; /* 0x38: Interrupt Status Register */ + __RW uint32_t INTR_MASK; /* 0x3C: Interrupt Mask Register */ + __RW uint32_t MAC_ADDR_0_HIGH; /* 0x40: MAC Address 0 High Register */ + __RW uint32_t MAC_ADDR_0_LOW; /* 0x44: MAC Address 0 Low Register */ + struct { + __RW uint32_t HIGH; /* 0x48: MAC Address High Register */ + __RW uint32_t LOW; /* 0x4C: MAC Address Low Register */ + } MAC_ADDR[4]; + __R uint8_t RESERVED0[112]; /* 0x68 - 0xD7: Reserved */ + __RW uint32_t XMII_CSR; /* 0xD8: SGMII/RGMII/SMII Control and Status Register */ + __RW uint32_t WDOG_WTO; /* 0xDC: Watchdog Timeout Register */ + __RW uint32_t GPIO; /* 0xE0: General Purpose IO Register */ + __R uint8_t RESERVED1[28]; /* 0xE4 - 0xFF: Reserved */ + __RW uint32_t MMC_CNTRL; /* 0x100: MMC Control establishes the operating mode of MMC. */ + __RW uint32_t MMC_INTR_RX; /* 0x104: MMC Receive Interrupt maintains the interrupt generated from all +of the receive statistic counters. */ + __RW uint32_t MMC_INTR_TX; /* 0x108: MMC Transmit Interrupt maintains the interrupt generated from all +of the transmit statistic counters */ + __RW uint32_t MMC_INTR_MASK_RX; /* 0x10C: MMC Receive Interrupt mask maintains the mask for the interrupt +generated from all of the receive statistic counters */ + __RW uint32_t MMC_INTR_MASK_TX; /* 0x110: MMC Transmit Interrupt Mask */ + __RW uint32_t TXOCTETCOUNT_GB; /* 0x114: Number of bytes transmitted, exclusive of preamble and retried +bytes, in good and bad frames. */ + __RW uint32_t TXFRAMECOUNT_GB; /* 0x118: Number of good and bad frames transmitted, exclusive of retried +frames. */ + __RW uint32_t TXBROADCASTFRAMES_G; /* 0x11C: Number of good broadcast frames transmitted */ + __RW uint32_t TXMLTICASTFRAMES_G; /* 0x120: Number of good multicast frames transmitted */ + __RW uint32_t TX64OCTETS_GB; /* 0x124: Number of good and bad frames transmitted with length 64 bytes, +exclusive of preamble and retried frames. */ + __RW uint32_t TX65TO127OCTETS_GB; /* 0x128: Number of good and bad frames transmitted with length between +65 and 127 (inclusive) bytes, exclusive of preamble and retried +frames. */ + __RW uint32_t TX128TO255OCTETS_GB; /* 0x12C: Number of good and bad frames transmitted with length between +128 and 255 (inclusive) bytes, exclusive of preamble and retried +frames. */ + __RW uint32_t TX256TO511OCTETS_GB; /* 0x130: Number of good and bad frames transmitted with length between +256 and 511 (inclusive) bytes, exclusive of preamble and retried +frames. */ + __RW uint32_t TX512TO1023OCTETS_GB; /* 0x134: Number of good and bad frames transmitted with length between +512 and 1,023 (inclusive) bytes, exclusive of preamble and retried +frames. */ + __RW uint32_t TX1024TOMAXOCTETS_GB; /* 0x138: Number of good and bad frames transmitted with length between +1,024 and maxsize (inclusive) bytes, exclusive of preamble and +retried frames. */ + __RW uint32_t TXUNICASTFRAMES_GB; /* 0x13C: Number of good and bad unicast frames transmitted. */ + __RW uint32_t TXMULTICASTFRAMES_GB; /* 0x140: Number of good and bad multicast frames transmitted. */ + __RW uint32_t TXBROADCASTFRAMES_GB; /* 0x144: Number of good and bad broadcast frames transmitted. */ + __RW uint32_t TXUNDERFLOWERROR; /* 0x148: Number of frames aborted because of frame underflow error. */ + __RW uint32_t TXSINGLECOL_G; /* 0x14C: Number of successfully transmitted frames after a single collision +in the half-duplex mode. */ + __RW uint32_t TXMULTICOL_G; /* 0x150: Number of successfully transmitted frames after multiple collisions +in the half-duplex mode. */ + __RW uint32_t TXDEFERRED; /* 0x154: Number of successfully transmitted frames after a deferral in the +half-duplex mode. */ + __RW uint32_t TXLATECOL; /* 0x158: Number of frames aborted because of late collision error */ + __RW uint32_t TXEXESSCOL; /* 0x15C: Number of frames aborted because of excessive (16) collision +errors */ + __RW uint32_t TXCARRIERERROR; /* 0x160: Number of frames aborted because of carrier sense error (no +carrier or loss of carrier). */ + __RW uint32_t TXOCTETCOUNT_G; /* 0x164: Number of bytes transmitted, exclusive of preamble, only in good +frames. */ + __RW uint32_t TXFRAMECOUNT_G; /* 0x168: Number of good frames transmitted */ + __RW uint32_t TXEXCESSDEF; /* 0x16C: Number of frames aborted because of excessive deferral error +(deferred for more than two max-sized frame times). */ + __RW uint32_t TXPAUSEFRAMES; /* 0x170: Number of good Pause frames transmitted */ + __RW uint32_t TXVLANFRAMES_G; /* 0x174: Number of good VLAN frames transmitted, exclusive of retried +frames. */ + __RW uint32_t TXOVERSIZE_G; /* 0x178: Number of frames transmitted without errors and with length +greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged +frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC +Configuration Register)). */ + __R uint8_t RESERVED2[4]; /* 0x17C - 0x17F: Reserved */ + __RW uint32_t RXFRAMECOUNT_GB; /* 0x180: Number of good and bad frames received */ + __RW uint32_t RXOCTETCOUNT_G; /* 0x184: Number of bytes received, exclusive of preamble, only in good +frames. */ + __RW uint32_t RXOCTETCOUNT_GB; /* 0x188: Number of bytes received, exclusive of preamble, in good and bad +frames. */ + __RW uint32_t RXBROADCASTFRAMES_G; /* 0x18C: Number of good broadcast frames received */ + __RW uint32_t RXMULTICASTFRAMES_G; /* 0x190: Number of good multicast frames received */ + __RW uint32_t RXCRCERROR; /* 0x194: Number of frames received with CRC error */ + __RW uint32_t RXALIGNMENTERROR; /* 0x198: Number of frames received with alignment (dribble) error. Valid +only in 10/100 mode */ + __RW uint32_t RXRUNTERROR; /* 0x19C: Number of frames received with runt (<64 bytes and CRC error) +error. */ + __RW uint32_t RXJABBERERROR; /* 0x1A0: Number of giant frames received with length (including CRC) +greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with +CRC error. If Jumbo Frame mode is enabled, then frames of +length greater than 9,018 bytes (9,022 for VLAN tagged) are +considered as giant frames. */ + __RW uint32_t RXUNDERSIZE_G; /* 0x1A4: Number of frames received with length less than 64 bytes, without +any errors. */ + __RW uint32_t RXOVERSIZE_G; /* 0x1A8: Number of frames received without errors, with length greater +than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 +bytes if enabled in Bit 27 of Register 0 (MAC Configuration +Register)) */ + __RW uint32_t RX64OCTETS_GB; /* 0x1AC: Number of good and bad frames received with length 64 bytes, +exclusive of preamble. */ + __RW uint32_t RX65TO127OCTETS_GB; /* 0x1B0: */ + __RW uint32_t RX128TO255OCTETS_GB; /* 0x1B4: */ + __RW uint32_t RX256TO511OCTETS_GB; /* 0x1B8: Number of good and bad frames received with length between +256 and 511 (inclusive) bytes, exclusive of preamble. */ + __RW uint32_t RX512TO1023OCTETS_GB; /* 0x1BC: Number of good and bad frames received with length between +512 and 1023 (inclusive) bytes, exclusive of preamble. */ + __RW uint32_t RX1024TOMAXOCTETS_GB; /* 0x1C0: Number of good and bad frames received with length between +1024 and maxsize (inclusive) bytes, exclusive of preamble. */ + __RW uint32_t RXUNICASTFRAMES_G; /* 0x1C4: Number of received good unicast frames. */ + __RW uint32_t RXLENGTHERROR; /* 0x1C8: Number of frames received with length error (Length type field ≠ +frame size), for all frames with valid length field. */ + __RW uint32_t RXOUTOFRANGETYPE; /* 0x1CC: Number of frames received with length field not equal to the valid +frame size (greater than 1,500 but less than 1,536). */ + __RW uint32_t RXPAUSEFRAMES; /* 0x1D0: Number of good and valid Pause frames received. */ + __RW uint32_t RXFIFOOVERFLOW; /* 0x1D4: Number of missed received frames because of FIFO overflow. +This counter is not present in the GMAC-CORE configuration. */ + __RW uint32_t RXVLANFRAMES_GB; /* 0x1D8: Number of good and bad VLAN frames received. */ + __RW uint32_t RXWATCHDOGERROR; /* 0x1DC: Number of frames received with error because of watchdog +timeout error (frames with a data load larger than 2,048 bytes or +the value programmed in Register 55 (Watchdog Timeout +Register)). */ + __RW uint32_t RXRCVERROR; /* 0x1E0: Number of frames received with Receive error or Frame Extension +error on the GMII or MII interface. */ + __RW uint32_t RXCTRLFRAMES_G; /* 0x1E4: Number of received good control frames */ + __R uint8_t RESERVED3[24]; /* 0x1E8 - 0x1FF: Reserved */ + __RW uint32_t MMC_IPC_INTR_MASK_RX; /* 0x200: MMC IPC Receive Checksum Offload Interrupt Mask maintains +the mask for the interrupt generated from the receive IPC statistic +counters. */ + __R uint8_t RESERVED4[4]; /* 0x204 - 0x207: Reserved */ + __RW uint32_t MMC_IPC_INTR_RX; /* 0x208: MMC Receive Checksum Offload Interrupt maintains the interrupt +that the receive IPC statistic counters generate. See Table 4-25 +for further detail. */ + __R uint8_t RESERVED5[4]; /* 0x20C - 0x20F: Reserved */ + __RW uint32_t RXIPV4_GD_FMS; /* 0x210: Number of good IPv4 datagrams received with the TCP, UDP, or +ICMP payload */ + __RW uint32_t RXIPV4_HDRERR_FRMS; /* 0x214: Number of IPv4 datagrams received with header (checksum, +length, or version mismatch) errors */ + __RW uint32_t RXIPV4_NOPAY_FRMS; /* 0x218: Number of IPv4 datagram frames received that did not have a +TCP, UDP, or ICMP payload processed by the Checksum engine */ + __RW uint32_t RXIPV4_FRAG_FRMS; /* 0x21C: Number of good IPv4 datagrams with fragmentation */ + __RW uint32_t RXIPV4_UDSBL_FRMS; /* 0x220: Number of good IPv4 datagrams received that had a UDP +payload with checksum disabled */ + __RW uint32_t RXIPV6_GD_FRMS; /* 0x224: Number of good IPv6 datagrams received with TCP, UDP, or +ICMP payloads */ + __RW uint32_t RXIPV6_HDRERR_FRMS; /* 0x228: Number of IPv6 datagrams received with header errors (length or +version mismatch) */ + __RW uint32_t RXIPV6_NOPAY_FRMS; /* 0x22C: Number of IPv6 datagram frames received that did not have a +TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with +fragmentation or security extension headers */ + __RW uint32_t RXUDP_GD_FRMS; /* 0x230: Number of good IP datagrams with a good UDP payload. This +counter is not updated when the rxipv4_udsbl_frms counter is +incremented. */ + __RW uint32_t RXUDP_ERR_FRMS; /* 0x234: Number of good IP datagrams whose UDP payload has a +checksum error */ + __RW uint32_t RXTCP_GD_FRMS; /* 0x238: Number of good IP datagrams with a good TCP payload */ + __RW uint32_t RXTCP_ERR_FRMS; /* 0x23C: Number of good IP datagrams whose TCP payload has a +checksum error */ + __RW uint32_t RXICMP_GD_FRMS; /* 0x240: Number of good IP datagrams with a good ICMP payload */ + __RW uint32_t RXICMP_ERR_FRMS; /* 0x244: Number of good IP datagrams whose ICMP payload has a +checksum error */ + __R uint8_t RESERVED6[8]; /* 0x248 - 0x24F: Reserved */ + __RW uint32_t RXIPV4_GD_OCTETS; /* 0x250: Number of bytes received in good IPv4 datagrams encapsulating +TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad +bytes are not included in this counter or in the octet counters listed +below). */ + __RW uint32_t RXIPV4_HDRERR_OCTETS; /* 0x254: Number of bytes received in IPv4 datagrams with header errors +(checksum, length, version mismatch). The value in the Length +field of IPv4 header is used to update this counter. */ + __RW uint32_t RXIPV4_NOPAY_OCTETS; /* 0x258: Number of bytes received in IPv4 datagrams that did not have a +TCP, UDP, or ICMP payload. The value in the IPv4 header’s +Length field is used to update this counter. */ + __RW uint32_t RXIPV4_FRAG_OCTETS; /* 0x25C: Number of bytes received in fragmented IPv4 datagrams. The +value in the IPv4 header’s Length field is used to update this +counter */ + __RW uint32_t RXIPV4_UDSBL_OCTETS; /* 0x260: Number of bytes received in a UDP segment that had the UDP +checksum disabled. This counter does not count IP Header bytes. */ + __RW uint32_t RXIPV6_GD_OCTETS; /* 0x264: Number of bytes received in good IPv6 datagrams encapsulating +TCP, UDP or ICMPv6 data */ + __RW uint32_t RXIPV6_HDRERR_OCTETS; /* 0x268: Number of bytes received in IPv6 datagrams with header errors +(length, version mismatch). The value in the IPv6 header’s Length +field is used to update this counter. */ + __RW uint32_t RXIPV6_NOPAY_OCTETS; /* 0x26C: Number of bytes received in IPv6 datagrams that did not have a +TCP, UDP, or ICMP payload. The value in the IPv6 header’s +Length field is used to update this counter. */ + __RW uint32_t RXUDP_GD_OCTETS; /* 0x270: Number of bytes received in a good UDP segment. This counter +(and the counters below) does not count IP header bytes. */ + __RW uint32_t RXUDP_ERR_OCTETS; /* 0x274: Number of bytes received in a UDP segment that had checksum +errors */ + __RW uint32_t RXTCP_GD_OCTETS; /* 0x278: Number of bytes received in a good TCP segment */ + __RW uint32_t RXTCP_ERR_OCTETS; /* 0x27C: Number of bytes received in a TCP segment with checksum +errors */ + __RW uint32_t RXICMP_GD_OCTETS; /* 0x280: Number of bytes received in a good ICMP segment */ + __R uint8_t RESERVED7[380]; /* 0x284 - 0x3FF: Reserved */ + struct { + __RW uint32_t L3_L4_CTRL; /* 0x400: Layer 3 and Layer 4 Control Register */ + __RW uint32_t L4_ADDR; /* 0x404: Layer 4 Address Register */ + __R uint8_t RESERVED0[8]; /* 0x408 - 0x40F: Reserved */ + __RW uint32_t L3_ADDR_0; /* 0x410: Layer 3 Address 0 Register */ + __RW uint32_t L3_ADDR_1; /* 0x414: Layer 3 Address 1 Register */ + __RW uint32_t L3_ADDR_2; /* 0x418: Layer 3 Address 2 Register */ + __RW uint32_t L3_ADDR_3; /* 0x41C: Layer 3 Address 3 Register */ + __R uint8_t RESERVED1[16]; /* 0x420 - 0x42F: Reserved */ + } L3_L4_CFG[4]; + __R uint8_t RESERVED8[64]; /* 0x4C0 - 0x4FF: Reserved */ + __RW uint32_t HASH_TABLE[8]; /* 0x500 - 0x51C: Hash Table Register 0 */ + __R uint8_t RESERVED9[100]; /* 0x520 - 0x583: Reserved */ + __RW uint32_t VLAN_TAG_INC_RPL; /* 0x584: VLAN Tag Inclusion or Replacement Register */ + __RW uint32_t VLAN_HASH; /* 0x588: VLAN Hash Table Register */ + __R uint8_t RESERVED10[372]; /* 0x58C - 0x6FF: Reserved */ + __RW uint32_t TS_CTRL; /* 0x700: Timestamp Control Register */ + __RW uint32_t SUB_SEC_INCR; /* 0x704: Sub-Second Increment Register */ + __RW uint32_t SYST_SEC; /* 0x708: System Time - Seconds Register */ + __RW uint32_t SYST_NSEC; /* 0x70C: System Time - Nanoseconds Register */ + __RW uint32_t SYST_SEC_UPD; /* 0x710: System Time - Seconds Update Register */ + __RW uint32_t SYST_NSEC_UPD; /* 0x714: System Time - Nanoseconds Update Register */ + __RW uint32_t TS_ADDEND; /* 0x718: Timestamp Addend Register */ + __RW uint32_t TGTTM_SEC; /* 0x71C: Target Time Seconds Register */ + __RW uint32_t TGTTM_NSEC; /* 0x720: Target Time Nanoseconds Register */ + __RW uint32_t SYSTM_H_SEC; /* 0x724: System Time - Higher Word Seconds Register */ + __R uint32_t TS_STATUS; /* 0x728: Timestamp Status Register */ + __RW uint32_t PPS_CTRL; /* 0x72C: PPS Control Register */ + __RW uint32_t AUX_TS_NSEC; /* 0x730: Auxiliary Timestamp - Nanoseconds Register */ + __RW uint32_t AUX_TS_SEC; /* 0x734: Auxiliary Timestamp - Seconds Register */ + __R uint8_t RESERVED11[40]; /* 0x738 - 0x75F: Reserved */ + __RW uint32_t PPS0_INTERVAL; /* 0x760: PPS0 Interval Register */ + __RW uint32_t PPS0_WIDTH; /* 0x764: PPS0 Width Register */ + __R uint8_t RESERVED12[24]; /* 0x768 - 0x77F: Reserved */ + struct { + __RW uint32_t TGTTM_SEC; /* 0x780: PPS Target Time Seconds Register */ + __RW uint32_t TGTTM_NSEC; /* 0x784: PPS Target Time Nanoseconds Register */ + __RW uint32_t INTERVAL; /* 0x788: PPS Interval Register */ + __RW uint32_t WIDTH; /* 0x78C: PPS Width Register */ + __R uint8_t RESERVED0[16]; /* 0x790 - 0x79F: Reserved */ + } PPS[3]; + __R uint8_t RESERVED13[2080]; /* 0x7E0 - 0xFFF: Reserved */ + __RW uint32_t DMA_BUS_MODE; /* 0x1000: Bus Mode Register */ + __RW uint32_t DMA_TX_POLL_DEMAND; /* 0x1004: Transmit Poll Demand Register */ + __RW uint32_t DMA_RX_POLL_DEMAND; /* 0x1008: Receive Poll Demand Register */ + __RW uint32_t DMA_RX_DESC_LIST_ADDR; /* 0x100C: Receive Descriptor List Address Register */ + __RW uint32_t DMA_TX_DESC_LIST_ADDR; /* 0x1010: Transmit Descriptor List Address Register */ + __RW uint32_t DMA_STATUS; /* 0x1014: Status Register */ + __RW uint32_t DMA_OP_MODE; /* 0x1018: Operation Mode Register */ + __RW uint32_t DMA_INTR_EN; /* 0x101C: Interrupt Enable Register */ + __RW uint32_t DMA_MISS_OVF_CNT; /* 0x1020: Missed Frame And Buffer Overflow Counter Register */ + __RW uint32_t DMA_RX_INTR_WDOG; /* 0x1024: Receive Interrupt Watchdog Timer Register */ + __RW uint32_t DMA_AXI_MODE; /* 0x1028: AXI Bus Mode Register */ + __RW uint32_t DMA_BUS_STATUS; /* 0x102C: AHB or AXI Status Register */ + __R uint8_t RESERVED14[24]; /* 0x1030 - 0x1047: Reserved */ + __RW uint32_t DMA_CURR_HOST_TX_DESC; /* 0x1048: Current Host Transmit Descriptor Register */ + __RW uint32_t DMA_CURR_HOST_RX_DESC; /* 0x104C: Current Host Receive Descriptor Register */ + __RW uint32_t DMA_CURR_HOST_TX_BUF; /* 0x1050: Current Host Transmit Buffer Address Register */ + __RW uint32_t DMA_CURR_HOST_RX_BUF; /* 0x1054: Current Host Receive Buffer Address Register */ + __RW uint32_t DMA_HW_FEATURE; /* 0x1058: HW Feature Register */ + __R uint8_t RESERVED15[8100]; /* 0x105C - 0x2FFF: Reserved */ + __RW uint32_t CTRL0; /* 0x3000: Control Register 0 */ + __R uint8_t RESERVED16[4]; /* 0x3004 - 0x3007: Reserved */ + __RW uint32_t CTRL2; /* 0x3008: Control Register 1 */ + __R uint8_t RESERVED17[28]; /* 0x300C - 0x3027: Reserved */ +} ENET_Type; + + +/* Bitfield definition for register: MACCFG */ +/* + * SARC (RW) + * + * Source Address Insertion or Replacement Control + * This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: + * - 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. + * - 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. + * - 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. Note: - Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. + */ +#define ENET_MACCFG_SARC_MASK (0x70000000UL) +#define ENET_MACCFG_SARC_SHIFT (28U) +#define ENET_MACCFG_SARC_SET(x) (((uint32_t)(x) << ENET_MACCFG_SARC_SHIFT) & ENET_MACCFG_SARC_MASK) +#define ENET_MACCFG_SARC_GET(x) (((uint32_t)(x) & ENET_MACCFG_SARC_MASK) >> ENET_MACCFG_SARC_SHIFT) + +/* + * TWOKPE (RW) + * + * IEEE 802.3as Support for 2K Packets + * When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status. + */ +#define ENET_MACCFG_TWOKPE_MASK (0x8000000UL) +#define ENET_MACCFG_TWOKPE_SHIFT (27U) +#define ENET_MACCFG_TWOKPE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TWOKPE_SHIFT) & ENET_MACCFG_TWOKPE_MASK) +#define ENET_MACCFG_TWOKPE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TWOKPE_MASK) >> ENET_MACCFG_TWOKPE_SHIFT) + +/* + * SFTERR (RW) + * + * SMII Force Transmit Error + * When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. + */ +#define ENET_MACCFG_SFTERR_MASK (0x4000000UL) +#define ENET_MACCFG_SFTERR_SHIFT (26U) +#define ENET_MACCFG_SFTERR_SET(x) (((uint32_t)(x) << ENET_MACCFG_SFTERR_SHIFT) & ENET_MACCFG_SFTERR_MASK) +#define ENET_MACCFG_SFTERR_GET(x) (((uint32_t)(x) & ENET_MACCFG_SFTERR_MASK) >> ENET_MACCFG_SFTERR_SHIFT) + +/* + * CST (RW) + * + * CRC Stripping for Type Frames + * When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. + */ +#define ENET_MACCFG_CST_MASK (0x2000000UL) +#define ENET_MACCFG_CST_SHIFT (25U) +#define ENET_MACCFG_CST_SET(x) (((uint32_t)(x) << ENET_MACCFG_CST_SHIFT) & ENET_MACCFG_CST_MASK) +#define ENET_MACCFG_CST_GET(x) (((uint32_t)(x) & ENET_MACCFG_CST_MASK) >> ENET_MACCFG_CST_SHIFT) + +/* + * TC (RW) + * + * Transmit Configuration in RGMII, SGMII, or SMII + * When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. + */ +#define ENET_MACCFG_TC_MASK (0x1000000UL) +#define ENET_MACCFG_TC_SHIFT (24U) +#define ENET_MACCFG_TC_SET(x) (((uint32_t)(x) << ENET_MACCFG_TC_SHIFT) & ENET_MACCFG_TC_MASK) +#define ENET_MACCFG_TC_GET(x) (((uint32_t)(x) & ENET_MACCFG_TC_MASK) >> ENET_MACCFG_TC_SHIFT) + +/* + * WD (RW) + * + * Watchdog Disable + * When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. + */ +#define ENET_MACCFG_WD_MASK (0x800000UL) +#define ENET_MACCFG_WD_SHIFT (23U) +#define ENET_MACCFG_WD_SET(x) (((uint32_t)(x) << ENET_MACCFG_WD_SHIFT) & ENET_MACCFG_WD_MASK) +#define ENET_MACCFG_WD_GET(x) (((uint32_t)(x) & ENET_MACCFG_WD_MASK) >> ENET_MACCFG_WD_SHIFT) + +/* + * JD (RW) + * + * Jabber Disable + * When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. + */ +#define ENET_MACCFG_JD_MASK (0x400000UL) +#define ENET_MACCFG_JD_SHIFT (22U) +#define ENET_MACCFG_JD_SET(x) (((uint32_t)(x) << ENET_MACCFG_JD_SHIFT) & ENET_MACCFG_JD_MASK) +#define ENET_MACCFG_JD_GET(x) (((uint32_t)(x) & ENET_MACCFG_JD_MASK) >> ENET_MACCFG_JD_SHIFT) + +/* + * BE (RW) + * + * Frame Burst Enable + * When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. + */ +#define ENET_MACCFG_BE_MASK (0x200000UL) +#define ENET_MACCFG_BE_SHIFT (21U) +#define ENET_MACCFG_BE_SET(x) (((uint32_t)(x) << ENET_MACCFG_BE_SHIFT) & ENET_MACCFG_BE_MASK) +#define ENET_MACCFG_BE_GET(x) (((uint32_t)(x) & ENET_MACCFG_BE_MASK) >> ENET_MACCFG_BE_SHIFT) + +/* + * JE (RW) + * + * Jumbo Frame Enable + * When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. + */ +#define ENET_MACCFG_JE_MASK (0x100000UL) +#define ENET_MACCFG_JE_SHIFT (20U) +#define ENET_MACCFG_JE_SET(x) (((uint32_t)(x) << ENET_MACCFG_JE_SHIFT) & ENET_MACCFG_JE_MASK) +#define ENET_MACCFG_JE_GET(x) (((uint32_t)(x) & ENET_MACCFG_JE_MASK) >> ENET_MACCFG_JE_SHIFT) + +/* + * IFG (RW) + * + * Inter-Frame Gap + * These bits control the minimum IFG between frames during transmission. + * - 000: 96 bit times + * - 001: 88 bit times + * - 010: 80 bit times - ... + * - 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. + */ +#define ENET_MACCFG_IFG_MASK (0xE0000UL) +#define ENET_MACCFG_IFG_SHIFT (17U) +#define ENET_MACCFG_IFG_SET(x) (((uint32_t)(x) << ENET_MACCFG_IFG_SHIFT) & ENET_MACCFG_IFG_MASK) +#define ENET_MACCFG_IFG_GET(x) (((uint32_t)(x) & ENET_MACCFG_IFG_MASK) >> ENET_MACCFG_IFG_SHIFT) + +/* + * DCRS (RW) + * + * Disable Carrier Sense During Transmission + * When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. + */ +#define ENET_MACCFG_DCRS_MASK (0x10000UL) +#define ENET_MACCFG_DCRS_SHIFT (16U) +#define ENET_MACCFG_DCRS_SET(x) (((uint32_t)(x) << ENET_MACCFG_DCRS_SHIFT) & ENET_MACCFG_DCRS_MASK) +#define ENET_MACCFG_DCRS_GET(x) (((uint32_t)(x) & ENET_MACCFG_DCRS_MASK) >> ENET_MACCFG_DCRS_SHIFT) + +/* + * PS (RW) + * + * Port Select + * This bit selects the Ethernet line speed. + * - 0: For 1000 Mbps operations + * - 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. + */ +#define ENET_MACCFG_PS_MASK (0x8000U) +#define ENET_MACCFG_PS_SHIFT (15U) +#define ENET_MACCFG_PS_SET(x) (((uint32_t)(x) << ENET_MACCFG_PS_SHIFT) & ENET_MACCFG_PS_MASK) +#define ENET_MACCFG_PS_GET(x) (((uint32_t)(x) & ENET_MACCFG_PS_MASK) >> ENET_MACCFG_PS_SHIFT) + +/* + * FES (RW) + * + * Speed + * This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: + * - 0: 10 Mbps + * - 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. + */ +#define ENET_MACCFG_FES_MASK (0x4000U) +#define ENET_MACCFG_FES_SHIFT (14U) +#define ENET_MACCFG_FES_SET(x) (((uint32_t)(x) << ENET_MACCFG_FES_SHIFT) & ENET_MACCFG_FES_MASK) +#define ENET_MACCFG_FES_GET(x) (((uint32_t)(x) & ENET_MACCFG_FES_MASK) >> ENET_MACCFG_FES_SHIFT) + +/* + * DO (RW) + * + * Disable Receive Own + * When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. + */ +#define ENET_MACCFG_DO_MASK (0x2000U) +#define ENET_MACCFG_DO_SHIFT (13U) +#define ENET_MACCFG_DO_SET(x) (((uint32_t)(x) << ENET_MACCFG_DO_SHIFT) & ENET_MACCFG_DO_MASK) +#define ENET_MACCFG_DO_GET(x) (((uint32_t)(x) & ENET_MACCFG_DO_MASK) >> ENET_MACCFG_DO_SHIFT) + +/* + * LM (RW) + * + * Loopback Mode + * When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. + */ +#define ENET_MACCFG_LM_MASK (0x1000U) +#define ENET_MACCFG_LM_SHIFT (12U) +#define ENET_MACCFG_LM_SET(x) (((uint32_t)(x) << ENET_MACCFG_LM_SHIFT) & ENET_MACCFG_LM_MASK) +#define ENET_MACCFG_LM_GET(x) (((uint32_t)(x) & ENET_MACCFG_LM_MASK) >> ENET_MACCFG_LM_SHIFT) + +/* + * DM (RW) + * + * Duplex Mode + * When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configuration. + */ +#define ENET_MACCFG_DM_MASK (0x800U) +#define ENET_MACCFG_DM_SHIFT (11U) +#define ENET_MACCFG_DM_SET(x) (((uint32_t)(x) << ENET_MACCFG_DM_SHIFT) & ENET_MACCFG_DM_MASK) +#define ENET_MACCFG_DM_GET(x) (((uint32_t)(x) & ENET_MACCFG_DM_MASK) >> ENET_MACCFG_DM_SHIFT) + +/* + * IPC (RW) + * + * Checksum Offload + * When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. + */ +#define ENET_MACCFG_IPC_MASK (0x400U) +#define ENET_MACCFG_IPC_SHIFT (10U) +#define ENET_MACCFG_IPC_SET(x) (((uint32_t)(x) << ENET_MACCFG_IPC_SHIFT) & ENET_MACCFG_IPC_MASK) +#define ENET_MACCFG_IPC_GET(x) (((uint32_t)(x) & ENET_MACCFG_IPC_MASK) >> ENET_MACCFG_IPC_SHIFT) + +/* + * DR (RW) + * + * Disable Retry + * When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). + */ +#define ENET_MACCFG_DR_MASK (0x200U) +#define ENET_MACCFG_DR_SHIFT (9U) +#define ENET_MACCFG_DR_SET(x) (((uint32_t)(x) << ENET_MACCFG_DR_SHIFT) & ENET_MACCFG_DR_MASK) +#define ENET_MACCFG_DR_GET(x) (((uint32_t)(x) & ENET_MACCFG_DR_MASK) >> ENET_MACCFG_DR_SHIFT) + +/* + * LUD (RW) + * + * Link Up or Down + * This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: + * - 0: Link Down + * - 1: Link Up + */ +#define ENET_MACCFG_LUD_MASK (0x100U) +#define ENET_MACCFG_LUD_SHIFT (8U) +#define ENET_MACCFG_LUD_SET(x) (((uint32_t)(x) << ENET_MACCFG_LUD_SHIFT) & ENET_MACCFG_LUD_MASK) +#define ENET_MACCFG_LUD_GET(x) (((uint32_t)(x) & ENET_MACCFG_LUD_MASK) >> ENET_MACCFG_LUD_SHIFT) + +/* + * ACS (RW) + * + * Automatic Pad or CRC Stripping + * When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. + */ +#define ENET_MACCFG_ACS_MASK (0x80U) +#define ENET_MACCFG_ACS_SHIFT (7U) +#define ENET_MACCFG_ACS_SET(x) (((uint32_t)(x) << ENET_MACCFG_ACS_SHIFT) & ENET_MACCFG_ACS_MASK) +#define ENET_MACCFG_ACS_GET(x) (((uint32_t)(x) & ENET_MACCFG_ACS_MASK) >> ENET_MACCFG_ACS_SHIFT) + +/* + * BL (RW) + * + * Back-Off Limit + * The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. + * - 00: k= min (n, 10) + * - 01: k = min (n, 8) + * - 10: k = min (n, 4) + * - 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k + */ +#define ENET_MACCFG_BL_MASK (0x60U) +#define ENET_MACCFG_BL_SHIFT (5U) +#define ENET_MACCFG_BL_SET(x) (((uint32_t)(x) << ENET_MACCFG_BL_SHIFT) & ENET_MACCFG_BL_MASK) +#define ENET_MACCFG_BL_GET(x) (((uint32_t)(x) & ENET_MACCFG_BL_MASK) >> ENET_MACCFG_BL_SHIFT) + +/* + * DC (RW) + * + * Deferral Check + * When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. + */ +#define ENET_MACCFG_DC_MASK (0x10U) +#define ENET_MACCFG_DC_SHIFT (4U) +#define ENET_MACCFG_DC_SET(x) (((uint32_t)(x) << ENET_MACCFG_DC_SHIFT) & ENET_MACCFG_DC_MASK) +#define ENET_MACCFG_DC_GET(x) (((uint32_t)(x) & ENET_MACCFG_DC_MASK) >> ENET_MACCFG_DC_SHIFT) + +/* + * TE (RW) + * + * Transmitter Enable + * When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. + */ +#define ENET_MACCFG_TE_MASK (0x8U) +#define ENET_MACCFG_TE_SHIFT (3U) +#define ENET_MACCFG_TE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TE_SHIFT) & ENET_MACCFG_TE_MASK) +#define ENET_MACCFG_TE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TE_MASK) >> ENET_MACCFG_TE_SHIFT) + +/* + * RE (RW) + * + * Receiver Enable + * When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. + */ +#define ENET_MACCFG_RE_MASK (0x4U) +#define ENET_MACCFG_RE_SHIFT (2U) +#define ENET_MACCFG_RE_SET(x) (((uint32_t)(x) << ENET_MACCFG_RE_SHIFT) & ENET_MACCFG_RE_MASK) +#define ENET_MACCFG_RE_GET(x) (((uint32_t)(x) & ENET_MACCFG_RE_MASK) >> ENET_MACCFG_RE_SHIFT) + +/* + * PRELEN (RW) + * + * Preamble Length for Transmit frames + * These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. + * - 2'b00: 7 bytes of preamble + * - 2'b01: 5 bytes of preamble + * - 2'b10: 3 bytes of preamble + * - 2'b11: Reserved + */ +#define ENET_MACCFG_PRELEN_MASK (0x3U) +#define ENET_MACCFG_PRELEN_SHIFT (0U) +#define ENET_MACCFG_PRELEN_SET(x) (((uint32_t)(x) << ENET_MACCFG_PRELEN_SHIFT) & ENET_MACCFG_PRELEN_MASK) +#define ENET_MACCFG_PRELEN_GET(x) (((uint32_t)(x) & ENET_MACCFG_PRELEN_MASK) >> ENET_MACCFG_PRELEN_SHIFT) + +/* Bitfield definition for register: MACFF */ +/* + * RA (RW) + * + * Receive All + * When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. + */ +#define ENET_MACFF_RA_MASK (0x80000000UL) +#define ENET_MACFF_RA_SHIFT (31U) +#define ENET_MACFF_RA_SET(x) (((uint32_t)(x) << ENET_MACFF_RA_SHIFT) & ENET_MACFF_RA_MASK) +#define ENET_MACFF_RA_GET(x) (((uint32_t)(x) & ENET_MACFF_RA_MASK) >> ENET_MACFF_RA_SHIFT) + +/* + * DNTU (RW) + * + * Drop non-TCP/UDP over IP Frames + * When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. + */ +#define ENET_MACFF_DNTU_MASK (0x200000UL) +#define ENET_MACFF_DNTU_SHIFT (21U) +#define ENET_MACFF_DNTU_SET(x) (((uint32_t)(x) << ENET_MACFF_DNTU_SHIFT) & ENET_MACFF_DNTU_MASK) +#define ENET_MACFF_DNTU_GET(x) (((uint32_t)(x) & ENET_MACFF_DNTU_MASK) >> ENET_MACFF_DNTU_SHIFT) + +/* + * IPFE (RW) + * + * Layer 3 and Layer 4 Filter Enable + * When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. + */ +#define ENET_MACFF_IPFE_MASK (0x100000UL) +#define ENET_MACFF_IPFE_SHIFT (20U) +#define ENET_MACFF_IPFE_SET(x) (((uint32_t)(x) << ENET_MACFF_IPFE_SHIFT) & ENET_MACFF_IPFE_MASK) +#define ENET_MACFF_IPFE_GET(x) (((uint32_t)(x) & ENET_MACFF_IPFE_MASK) >> ENET_MACFF_IPFE_SHIFT) + +/* + * VTFE (RW) + * + * VLAN Tag Filter Enable + * When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. + */ +#define ENET_MACFF_VTFE_MASK (0x8000U) +#define ENET_MACFF_VTFE_SHIFT (15U) +#define ENET_MACFF_VTFE_SET(x) (((uint32_t)(x) << ENET_MACFF_VTFE_SHIFT) & ENET_MACFF_VTFE_MASK) +#define ENET_MACFF_VTFE_GET(x) (((uint32_t)(x) & ENET_MACFF_VTFE_MASK) >> ENET_MACFF_VTFE_SHIFT) + +/* + * HPF (RW) + * + * Hash or Perfect Filter + * When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. + */ +#define ENET_MACFF_HPF_MASK (0x400U) +#define ENET_MACFF_HPF_SHIFT (10U) +#define ENET_MACFF_HPF_SET(x) (((uint32_t)(x) << ENET_MACFF_HPF_SHIFT) & ENET_MACFF_HPF_MASK) +#define ENET_MACFF_HPF_GET(x) (((uint32_t)(x) & ENET_MACFF_HPF_MASK) >> ENET_MACFF_HPF_SHIFT) + +/* + * SAF (RW) + * + * Source Address Filter Enable + * When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. + */ +#define ENET_MACFF_SAF_MASK (0x200U) +#define ENET_MACFF_SAF_SHIFT (9U) +#define ENET_MACFF_SAF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAF_SHIFT) & ENET_MACFF_SAF_MASK) +#define ENET_MACFF_SAF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAF_MASK) >> ENET_MACFF_SAF_SHIFT) + +/* + * SAIF (RW) + * + * SA Inverse Filtering + * When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. + */ +#define ENET_MACFF_SAIF_MASK (0x100U) +#define ENET_MACFF_SAIF_SHIFT (8U) +#define ENET_MACFF_SAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAIF_SHIFT) & ENET_MACFF_SAIF_MASK) +#define ENET_MACFF_SAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAIF_MASK) >> ENET_MACFF_SAIF_SHIFT) + +/* + * PCF (RW) + * + * Pass Control Frames + * These bits control the forwarding of all control frames (including unicast and multicast Pause frames). + * - 00: MAC filters all control frames from reaching the application. + * - 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. + * - 10: MAC forwards all control frames to application even if they fail the Address Filter. + * - 11: MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing: - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. Note: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). + */ +#define ENET_MACFF_PCF_MASK (0xC0U) +#define ENET_MACFF_PCF_SHIFT (6U) +#define ENET_MACFF_PCF_SET(x) (((uint32_t)(x) << ENET_MACFF_PCF_SHIFT) & ENET_MACFF_PCF_MASK) +#define ENET_MACFF_PCF_GET(x) (((uint32_t)(x) & ENET_MACFF_PCF_MASK) >> ENET_MACFF_PCF_SHIFT) + +/* + * DBF (RW) + * + * Disable Broadcast Frames + * When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. + */ +#define ENET_MACFF_DBF_MASK (0x20U) +#define ENET_MACFF_DBF_SHIFT (5U) +#define ENET_MACFF_DBF_SET(x) (((uint32_t)(x) << ENET_MACFF_DBF_SHIFT) & ENET_MACFF_DBF_MASK) +#define ENET_MACFF_DBF_GET(x) (((uint32_t)(x) & ENET_MACFF_DBF_MASK) >> ENET_MACFF_DBF_SHIFT) + +/* + * PM (RW) + * + * Pass All Multicast + * When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. When reset, filtering of multicast frame depends on HMC bit. + */ +#define ENET_MACFF_PM_MASK (0x10U) +#define ENET_MACFF_PM_SHIFT (4U) +#define ENET_MACFF_PM_SET(x) (((uint32_t)(x) << ENET_MACFF_PM_SHIFT) & ENET_MACFF_PM_MASK) +#define ENET_MACFF_PM_GET(x) (((uint32_t)(x) & ENET_MACFF_PM_MASK) >> ENET_MACFF_PM_SHIFT) + +/* + * DAIF (RW) + * + * DA Inverse Filtering + * When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. + */ +#define ENET_MACFF_DAIF_MASK (0x8U) +#define ENET_MACFF_DAIF_SHIFT (3U) +#define ENET_MACFF_DAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_DAIF_SHIFT) & ENET_MACFF_DAIF_MASK) +#define ENET_MACFF_DAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_DAIF_MASK) >> ENET_MACFF_DAIF_SHIFT) + +/* + * HMC (RW) + * + * Hash Multicast + * When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. + */ +#define ENET_MACFF_HMC_MASK (0x4U) +#define ENET_MACFF_HMC_SHIFT (2U) +#define ENET_MACFF_HMC_SET(x) (((uint32_t)(x) << ENET_MACFF_HMC_SHIFT) & ENET_MACFF_HMC_MASK) +#define ENET_MACFF_HMC_GET(x) (((uint32_t)(x) & ENET_MACFF_HMC_MASK) >> ENET_MACFF_HMC_SHIFT) + +/* + * HUC (RW) + * + * Hash Unicast + * When set, the MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. + */ +#define ENET_MACFF_HUC_MASK (0x2U) +#define ENET_MACFF_HUC_SHIFT (1U) +#define ENET_MACFF_HUC_SET(x) (((uint32_t)(x) << ENET_MACFF_HUC_SHIFT) & ENET_MACFF_HUC_MASK) +#define ENET_MACFF_HUC_GET(x) (((uint32_t)(x) & ENET_MACFF_HUC_MASK) >> ENET_MACFF_HUC_SHIFT) + +/* + * PR (RW) + * + * Promiscuous Mode + * When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. + */ +#define ENET_MACFF_PR_MASK (0x1U) +#define ENET_MACFF_PR_SHIFT (0U) +#define ENET_MACFF_PR_SET(x) (((uint32_t)(x) << ENET_MACFF_PR_SHIFT) & ENET_MACFF_PR_MASK) +#define ENET_MACFF_PR_GET(x) (((uint32_t)(x) & ENET_MACFF_PR_MASK) >> ENET_MACFF_PR_SHIFT) + +/* Bitfield definition for register: HASH_H */ +/* + * HTH (RW) + * + * Hash Table High + * This field contains the upper 32 bits of the Hash table. + */ +#define ENET_HASH_H_HTH_MASK (0xFFFFFFFFUL) +#define ENET_HASH_H_HTH_SHIFT (0U) +#define ENET_HASH_H_HTH_SET(x) (((uint32_t)(x) << ENET_HASH_H_HTH_SHIFT) & ENET_HASH_H_HTH_MASK) +#define ENET_HASH_H_HTH_GET(x) (((uint32_t)(x) & ENET_HASH_H_HTH_MASK) >> ENET_HASH_H_HTH_SHIFT) + +/* Bitfield definition for register: HASH_L */ +/* + * HTL (RW) + * + * Hash Table Low + * This field contains the lower 32 bits of the Hash table. + */ +#define ENET_HASH_L_HTL_MASK (0xFFFFFFFFUL) +#define ENET_HASH_L_HTL_SHIFT (0U) +#define ENET_HASH_L_HTL_SET(x) (((uint32_t)(x) << ENET_HASH_L_HTL_SHIFT) & ENET_HASH_L_HTL_MASK) +#define ENET_HASH_L_HTL_GET(x) (((uint32_t)(x) & ENET_HASH_L_HTL_MASK) >> ENET_HASH_L_HTL_SHIFT) + +/* Bitfield definition for register: GMII_ADDR */ +/* + * PA (RW) + * + * Physical Layer Address + * This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. + */ +#define ENET_GMII_ADDR_PA_MASK (0xF800U) +#define ENET_GMII_ADDR_PA_SHIFT (11U) +#define ENET_GMII_ADDR_PA_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_PA_SHIFT) & ENET_GMII_ADDR_PA_MASK) +#define ENET_GMII_ADDR_PA_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_PA_MASK) >> ENET_GMII_ADDR_PA_SHIFT) + +/* + * GR (RW) + * + * GMII Register + * These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. + */ +#define ENET_GMII_ADDR_GR_MASK (0x7C0U) +#define ENET_GMII_ADDR_GR_SHIFT (6U) +#define ENET_GMII_ADDR_GR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GR_SHIFT) & ENET_GMII_ADDR_GR_MASK) +#define ENET_GMII_ADDR_GR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GR_MASK) >> ENET_GMII_ADDR_GR_SHIFT) + +/* + * CR (RW) + * + * CSR Clock Range + * The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. + * - 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. + * - 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. + * - 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. + * - 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. + * - 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. + * - 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. + * - 0110, 0111: Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. + * - 1000: CSR clock/4 + * - 1001: CSR clock/6 + * - 1010: CSR clock/8 + * - 1011: CSR clock/10 + * - 1100: CSR clock/12 + * - 1101: CSR clock/14 + * - 1110: CSR clock/16 + * - 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. + */ +#define ENET_GMII_ADDR_CR_MASK (0x3CU) +#define ENET_GMII_ADDR_CR_SHIFT (2U) +#define ENET_GMII_ADDR_CR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_CR_SHIFT) & ENET_GMII_ADDR_CR_MASK) +#define ENET_GMII_ADDR_CR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_CR_MASK) >> ENET_GMII_ADDR_CR_SHIFT) + +/* + * GW (RW) + * + * GMII Write + * When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. + */ +#define ENET_GMII_ADDR_GW_MASK (0x2U) +#define ENET_GMII_ADDR_GW_SHIFT (1U) +#define ENET_GMII_ADDR_GW_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GW_SHIFT) & ENET_GMII_ADDR_GW_MASK) +#define ENET_GMII_ADDR_GW_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GW_MASK) >> ENET_GMII_ADDR_GW_SHIFT) + +/* + * GB (RW) + * + * GMII Busy + * This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. + */ +#define ENET_GMII_ADDR_GB_MASK (0x1U) +#define ENET_GMII_ADDR_GB_SHIFT (0U) +#define ENET_GMII_ADDR_GB_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GB_SHIFT) & ENET_GMII_ADDR_GB_MASK) +#define ENET_GMII_ADDR_GB_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GB_MASK) >> ENET_GMII_ADDR_GB_SHIFT) + +/* Bitfield definition for register: GMII_DATA */ +/* + * GD (RW) + * + * GMII Data + * This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. + */ +#define ENET_GMII_DATA_GD_MASK (0xFFFFU) +#define ENET_GMII_DATA_GD_SHIFT (0U) +#define ENET_GMII_DATA_GD_SET(x) (((uint32_t)(x) << ENET_GMII_DATA_GD_SHIFT) & ENET_GMII_DATA_GD_MASK) +#define ENET_GMII_DATA_GD_GET(x) (((uint32_t)(x) & ENET_GMII_DATA_GD_MASK) >> ENET_GMII_DATA_GD_SHIFT) + +/* Bitfield definition for register: FLOWCTRL */ +/* + * PT (RW) + * + * Pause Time + * This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. + */ +#define ENET_FLOWCTRL_PT_MASK (0xFFFF0000UL) +#define ENET_FLOWCTRL_PT_SHIFT (16U) +#define ENET_FLOWCTRL_PT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PT_SHIFT) & ENET_FLOWCTRL_PT_MASK) +#define ENET_FLOWCTRL_PT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PT_MASK) >> ENET_FLOWCTRL_PT_SHIFT) + +/* + * DZPQ (RW) + * + * Disable Zero-Quanta Pause + * When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. + */ +#define ENET_FLOWCTRL_DZPQ_MASK (0x80U) +#define ENET_FLOWCTRL_DZPQ_SHIFT (7U) +#define ENET_FLOWCTRL_DZPQ_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_DZPQ_SHIFT) & ENET_FLOWCTRL_DZPQ_MASK) +#define ENET_FLOWCTRL_DZPQ_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_DZPQ_MASK) >> ENET_FLOWCTRL_DZPQ_SHIFT) + +/* + * PLT (RW) + * + * Pause Low Threshold + * This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: + * - 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). + * - 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). + * - 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). + * - 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. + */ +#define ENET_FLOWCTRL_PLT_MASK (0x30U) +#define ENET_FLOWCTRL_PLT_SHIFT (4U) +#define ENET_FLOWCTRL_PLT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PLT_SHIFT) & ENET_FLOWCTRL_PLT_MASK) +#define ENET_FLOWCTRL_PLT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PLT_MASK) >> ENET_FLOWCTRL_PLT_SHIFT) + +/* + * UP (RW) + * + * Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. + */ +#define ENET_FLOWCTRL_UP_MASK (0x8U) +#define ENET_FLOWCTRL_UP_SHIFT (3U) +#define ENET_FLOWCTRL_UP_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_UP_SHIFT) & ENET_FLOWCTRL_UP_MASK) +#define ENET_FLOWCTRL_UP_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_UP_MASK) >> ENET_FLOWCTRL_UP_SHIFT) + +/* + * RFE (RW) + * + * Receive Flow Control Enable + * When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. + */ +#define ENET_FLOWCTRL_RFE_MASK (0x4U) +#define ENET_FLOWCTRL_RFE_SHIFT (2U) +#define ENET_FLOWCTRL_RFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_RFE_SHIFT) & ENET_FLOWCTRL_RFE_MASK) +#define ENET_FLOWCTRL_RFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_RFE_MASK) >> ENET_FLOWCTRL_RFE_SHIFT) + +/* + * TFE (RW) + * + * Transmit Flow Control Enable + * In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. + */ +#define ENET_FLOWCTRL_TFE_MASK (0x2U) +#define ENET_FLOWCTRL_TFE_SHIFT (1U) +#define ENET_FLOWCTRL_TFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_TFE_SHIFT) & ENET_FLOWCTRL_TFE_MASK) +#define ENET_FLOWCTRL_TFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_TFE_MASK) >> ENET_FLOWCTRL_TFE_SHIFT) + +/* + * FCB_BPA (RW) + * + * Flow Control Busy or Backpressure Activate + * This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. + */ +#define ENET_FLOWCTRL_FCB_BPA_MASK (0x1U) +#define ENET_FLOWCTRL_FCB_BPA_SHIFT (0U) +#define ENET_FLOWCTRL_FCB_BPA_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_FCB_BPA_SHIFT) & ENET_FLOWCTRL_FCB_BPA_MASK) +#define ENET_FLOWCTRL_FCB_BPA_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_FCB_BPA_MASK) >> ENET_FLOWCTRL_FCB_BPA_SHIFT) + +/* Bitfield definition for register: VLAN_TAG */ +/* + * VTHM (RW) + * + * VLAN Tag Hash Table Match Enable + * When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. + */ +#define ENET_VLAN_TAG_VTHM_MASK (0x80000UL) +#define ENET_VLAN_TAG_VTHM_SHIFT (19U) +#define ENET_VLAN_TAG_VTHM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTHM_SHIFT) & ENET_VLAN_TAG_VTHM_MASK) +#define ENET_VLAN_TAG_VTHM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTHM_MASK) >> ENET_VLAN_TAG_VTHM_SHIFT) + +/* + * ESVL (RW) + * + * Enable S-VLAN + * When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. + */ +#define ENET_VLAN_TAG_ESVL_MASK (0x40000UL) +#define ENET_VLAN_TAG_ESVL_SHIFT (18U) +#define ENET_VLAN_TAG_ESVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ESVL_SHIFT) & ENET_VLAN_TAG_ESVL_MASK) +#define ENET_VLAN_TAG_ESVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ESVL_MASK) >> ENET_VLAN_TAG_ESVL_SHIFT) + +/* + * VTIM (RW) + * + * VLAN Tag Inverse Match Enable + * When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. + */ +#define ENET_VLAN_TAG_VTIM_MASK (0x20000UL) +#define ENET_VLAN_TAG_VTIM_SHIFT (17U) +#define ENET_VLAN_TAG_VTIM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTIM_SHIFT) & ENET_VLAN_TAG_VTIM_MASK) +#define ENET_VLAN_TAG_VTIM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTIM_MASK) >> ENET_VLAN_TAG_VTIM_SHIFT) + +/* + * ETV (RW) + * + * Enable 12-Bit VLAN Tag Comparison + * When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. + */ +#define ENET_VLAN_TAG_ETV_MASK (0x10000UL) +#define ENET_VLAN_TAG_ETV_SHIFT (16U) +#define ENET_VLAN_TAG_ETV_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ETV_SHIFT) & ENET_VLAN_TAG_ETV_MASK) +#define ENET_VLAN_TAG_ETV_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ETV_MASK) >> ENET_VLAN_TAG_ETV_SHIFT) + +/* + * VL (RW) + * + * VLAN Tag Identifier for Receive Frames + * This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: - Bits [15:13]: User Priority - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. + */ +#define ENET_VLAN_TAG_VL_MASK (0xFFFFU) +#define ENET_VLAN_TAG_VL_SHIFT (0U) +#define ENET_VLAN_TAG_VL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VL_SHIFT) & ENET_VLAN_TAG_VL_MASK) +#define ENET_VLAN_TAG_VL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VL_MASK) >> ENET_VLAN_TAG_VL_SHIFT) + +/* Bitfield definition for register: VERSION */ +/* + * USERVER (RO) + * + * User-defined Version + */ +#define ENET_VERSION_USERVER_MASK (0xFF00U) +#define ENET_VERSION_USERVER_SHIFT (8U) +#define ENET_VERSION_USERVER_GET(x) (((uint32_t)(x) & ENET_VERSION_USERVER_MASK) >> ENET_VERSION_USERVER_SHIFT) + +/* + * SNPSVER (RO) + * + * Synopsys-defined Version (3.7) + */ +#define ENET_VERSION_SNPSVER_MASK (0xFFU) +#define ENET_VERSION_SNPSVER_SHIFT (0U) +#define ENET_VERSION_SNPSVER_GET(x) (((uint32_t)(x) & ENET_VERSION_SNPSVER_MASK) >> ENET_VERSION_SNPSVER_SHIFT) + +/* Bitfield definition for register: DEBUGGING */ +/* + * TXSTSFSTS (RO) + * + * MTL TxStatus FIFO Full Status + * When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. + */ +#define ENET_DEBUGGING_TXSTSFSTS_MASK (0x2000000UL) +#define ENET_DEBUGGING_TXSTSFSTS_SHIFT (25U) +#define ENET_DEBUGGING_TXSTSFSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TXSTSFSTS_MASK) >> ENET_DEBUGGING_TXSTSFSTS_SHIFT) + +/* + * TXFSTS (RO) + * + * MTL Tx FIFO Not Empty Status + * When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. + */ +#define ENET_DEBUGGING_TXFSTS_MASK (0x1000000UL) +#define ENET_DEBUGGING_TXFSTS_SHIFT (24U) +#define ENET_DEBUGGING_TXFSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TXFSTS_MASK) >> ENET_DEBUGGING_TXFSTS_SHIFT) + +/* + * TWCSTS (RO) + * + * MTL Tx FIFO Write Controller Status + * When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. + */ +#define ENET_DEBUGGING_TWCSTS_MASK (0x400000UL) +#define ENET_DEBUGGING_TWCSTS_SHIFT (22U) +#define ENET_DEBUGGING_TWCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TWCSTS_MASK) >> ENET_DEBUGGING_TWCSTS_SHIFT) + +/* + * TRCSTS (RO) + * + * MTL Tx FIFO Read Controller Status + * This field indicates the state of the Tx FIFO Read Controller: + * - 00: IDLE state + * - 01: READ state (transferring data to the MAC transmitter) + * - 10: Waiting for TxStatus from the MAC transmitter + * - 11: Writing the received TxStatus or flushing the Tx FIFO + */ +#define ENET_DEBUGGING_TRCSTS_MASK (0x300000UL) +#define ENET_DEBUGGING_TRCSTS_SHIFT (20U) +#define ENET_DEBUGGING_TRCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TRCSTS_MASK) >> ENET_DEBUGGING_TRCSTS_SHIFT) + +/* + * TXPAUSED (RO) + * + * MAC Transmitter in Pause + * When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-only mode) and hence does not schedule any frame for transmission. + */ +#define ENET_DEBUGGING_TXPAUSED_MASK (0x80000UL) +#define ENET_DEBUGGING_TXPAUSED_SHIFT (19U) +#define ENET_DEBUGGING_TXPAUSED_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TXPAUSED_MASK) >> ENET_DEBUGGING_TXPAUSED_SHIFT) + +/* + * TFCSTS (RO) + * + * MAC Transmit Frame Controller Status + * This field indicates the state of the MAC Transmit Frame Controller module: + * - 00: IDLE state + * - 01: Waiting for status of previous frame or IFG or backoff period to be over + * - 10: Generating and transmitting a Pause frame (in the full-duplex mode) + * - 11: Transferring input frame for transmission + */ +#define ENET_DEBUGGING_TFCSTS_MASK (0x60000UL) +#define ENET_DEBUGGING_TFCSTS_SHIFT (17U) +#define ENET_DEBUGGING_TFCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TFCSTS_MASK) >> ENET_DEBUGGING_TFCSTS_SHIFT) + +/* + * TPESTS (RO) + * + * MAC GMII or MII Transmit Protocol Engine Status + * When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. + */ +#define ENET_DEBUGGING_TPESTS_MASK (0x10000UL) +#define ENET_DEBUGGING_TPESTS_SHIFT (16U) +#define ENET_DEBUGGING_TPESTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TPESTS_MASK) >> ENET_DEBUGGING_TPESTS_SHIFT) + +/* + * RXFSTS (RO) + * + * MTL RxFIFO Fill-Level Status + * This field gives the status of the fill-level of the Rx FIFO: + * - 00: Rx FIFO Empty + * - 01: Rx FIFO fill-level below flow-control deactivate threshold + * - 10: Rx FIFO fill-level above flow-control activate threshold + * - 11: Rx FIFO Full + */ +#define ENET_DEBUGGING_RXFSTS_MASK (0x300U) +#define ENET_DEBUGGING_RXFSTS_SHIFT (8U) +#define ENET_DEBUGGING_RXFSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RXFSTS_MASK) >> ENET_DEBUGGING_RXFSTS_SHIFT) + +/* + * RRCSTS (RO) + * + * MTL RxFIFO Read Controller State + * This field gives the state of the Rx FIFO read Controller: + * - 00: IDLE state + * - 01: Reading frame data + * - 10: Reading frame status (or timestamp) + * - 11: Flushing the frame data and status + */ +#define ENET_DEBUGGING_RRCSTS_MASK (0x60U) +#define ENET_DEBUGGING_RRCSTS_SHIFT (5U) +#define ENET_DEBUGGING_RRCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RRCSTS_MASK) >> ENET_DEBUGGING_RRCSTS_SHIFT) + +/* + * RWCSTS (RO) + * + * MTL Rx FIFO Write Controller Active Status + * When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. + */ +#define ENET_DEBUGGING_RWCSTS_MASK (0x10U) +#define ENET_DEBUGGING_RWCSTS_SHIFT (4U) +#define ENET_DEBUGGING_RWCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RWCSTS_MASK) >> ENET_DEBUGGING_RWCSTS_SHIFT) + +/* + * RFCFCSTS (RO) + * + * MAC Receive Frame FIFO Controller Status + * When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. - RFCFCSTS[1] represents the status of small FIFO Read controller. - RFCFCSTS[0] represents the status of small FIFO Write controller. + */ +#define ENET_DEBUGGING_RFCFCSTS_MASK (0x6U) +#define ENET_DEBUGGING_RFCFCSTS_SHIFT (1U) +#define ENET_DEBUGGING_RFCFCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RFCFCSTS_MASK) >> ENET_DEBUGGING_RFCFCSTS_SHIFT) + +/* + * RPESTS (RO) + * + * MAC GMII or MII Receive Protocol Engine Status + * When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. + */ +#define ENET_DEBUGGING_RPESTS_MASK (0x1U) +#define ENET_DEBUGGING_RPESTS_SHIFT (0U) +#define ENET_DEBUGGING_RPESTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RPESTS_MASK) >> ENET_DEBUGGING_RPESTS_SHIFT) + +/* Bitfield definition for register: RWKFRMFILT */ +/* + * WKUPFRMFILT (RW) + * + * This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers + */ +#define ENET_RWKFRMFILT_WKUPFRMFILT_MASK (0xFFFFFFFFUL) +#define ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT (0U) +#define ENET_RWKFRMFILT_WKUPFRMFILT_SET(x) (((uint32_t)(x) << ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) +#define ENET_RWKFRMFILT_WKUPFRMFILT_GET(x) (((uint32_t)(x) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) >> ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) + +/* Bitfield definition for register: PMT_CSR */ +/* + * RWKFILTRST (RW) + * + * Remote Wake-Up Frame Filter Register Pointer Reset + * When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. + */ +#define ENET_PMT_CSR_RWKFILTRST_MASK (0x80000000UL) +#define ENET_PMT_CSR_RWKFILTRST_SHIFT (31U) +#define ENET_PMT_CSR_RWKFILTRST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKFILTRST_SHIFT) & ENET_PMT_CSR_RWKFILTRST_MASK) +#define ENET_PMT_CSR_RWKFILTRST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKFILTRST_MASK) >> ENET_PMT_CSR_RWKFILTRST_SHIFT) + +/* + * RWKPTR (RW) + * + * Remote Wake-up FIFO Pointer + * This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. + */ +#define ENET_PMT_CSR_RWKPTR_MASK (0x1F000000UL) +#define ENET_PMT_CSR_RWKPTR_SHIFT (24U) +#define ENET_PMT_CSR_RWKPTR_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPTR_SHIFT) & ENET_PMT_CSR_RWKPTR_MASK) +#define ENET_PMT_CSR_RWKPTR_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPTR_MASK) >> ENET_PMT_CSR_RWKPTR_SHIFT) + +/* + * GLBLUCAST (RW) + * + * Global Unicast + * When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. + */ +#define ENET_PMT_CSR_GLBLUCAST_MASK (0x200U) +#define ENET_PMT_CSR_GLBLUCAST_SHIFT (9U) +#define ENET_PMT_CSR_GLBLUCAST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_GLBLUCAST_SHIFT) & ENET_PMT_CSR_GLBLUCAST_MASK) +#define ENET_PMT_CSR_GLBLUCAST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_GLBLUCAST_MASK) >> ENET_PMT_CSR_GLBLUCAST_SHIFT) + +/* + * RWKPRCVD (RW) + * + * Remote Wake-Up Frame Received + * When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. + */ +#define ENET_PMT_CSR_RWKPRCVD_MASK (0x40U) +#define ENET_PMT_CSR_RWKPRCVD_SHIFT (6U) +#define ENET_PMT_CSR_RWKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPRCVD_SHIFT) & ENET_PMT_CSR_RWKPRCVD_MASK) +#define ENET_PMT_CSR_RWKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPRCVD_MASK) >> ENET_PMT_CSR_RWKPRCVD_SHIFT) + +/* + * MGKPRCVD (RW) + * + * Magic Packet Received + * When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. + */ +#define ENET_PMT_CSR_MGKPRCVD_MASK (0x20U) +#define ENET_PMT_CSR_MGKPRCVD_SHIFT (5U) +#define ENET_PMT_CSR_MGKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPRCVD_SHIFT) & ENET_PMT_CSR_MGKPRCVD_MASK) +#define ENET_PMT_CSR_MGKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPRCVD_MASK) >> ENET_PMT_CSR_MGKPRCVD_SHIFT) + +/* + * RWKPKTEN (RW) + * + * Remote Wake-Up Frame Enable + * When set, enables generation of a power management event because of remote wake-up frame reception. + */ +#define ENET_PMT_CSR_RWKPKTEN_MASK (0x4U) +#define ENET_PMT_CSR_RWKPKTEN_SHIFT (2U) +#define ENET_PMT_CSR_RWKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPKTEN_SHIFT) & ENET_PMT_CSR_RWKPKTEN_MASK) +#define ENET_PMT_CSR_RWKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPKTEN_MASK) >> ENET_PMT_CSR_RWKPKTEN_SHIFT) + +/* + * MGKPKTEN (RW) + * + * Magic Packet Enable + * When set, enables generation of a power management event because of magic packet reception. + */ +#define ENET_PMT_CSR_MGKPKTEN_MASK (0x2U) +#define ENET_PMT_CSR_MGKPKTEN_SHIFT (1U) +#define ENET_PMT_CSR_MGKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPKTEN_SHIFT) & ENET_PMT_CSR_MGKPKTEN_MASK) +#define ENET_PMT_CSR_MGKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPKTEN_MASK) >> ENET_PMT_CSR_MGKPKTEN_SHIFT) + +/* + * PWRDWN (RW) + * + * Power Down + * When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. This bit is then self-cleared and the power-down mode is disabled. The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. The frames, received by the MAC after this bit is cleared, are forwarded to the application. This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable bit is set high. Note: You can gate-off the CSR clock during the power-down mode. However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. + */ +#define ENET_PMT_CSR_PWRDWN_MASK (0x1U) +#define ENET_PMT_CSR_PWRDWN_SHIFT (0U) +#define ENET_PMT_CSR_PWRDWN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_PWRDWN_SHIFT) & ENET_PMT_CSR_PWRDWN_MASK) +#define ENET_PMT_CSR_PWRDWN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_PWRDWN_MASK) >> ENET_PMT_CSR_PWRDWN_SHIFT) + +/* Bitfield definition for register: LPI_CSR */ +/* + * LPITXA (RW) + * + * LPI TX Automate + * This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + */ +#define ENET_LPI_CSR_LPITXA_MASK (0x80000UL) +#define ENET_LPI_CSR_LPITXA_SHIFT (19U) +#define ENET_LPI_CSR_LPITXA_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPITXA_SHIFT) & ENET_LPI_CSR_LPITXA_MASK) +#define ENET_LPI_CSR_LPITXA_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPITXA_MASK) >> ENET_LPI_CSR_LPITXA_SHIFT) + +/* + * PLSEN (RW) + * + * PHY Link Status Enable + * This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. + */ +#define ENET_LPI_CSR_PLSEN_MASK (0x40000UL) +#define ENET_LPI_CSR_PLSEN_SHIFT (18U) +#define ENET_LPI_CSR_PLSEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLSEN_SHIFT) & ENET_LPI_CSR_PLSEN_MASK) +#define ENET_LPI_CSR_PLSEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLSEN_MASK) >> ENET_LPI_CSR_PLSEN_SHIFT) + +/* + * PLS (RW) + * + * PHY Link Status + * This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. + */ +#define ENET_LPI_CSR_PLS_MASK (0x20000UL) +#define ENET_LPI_CSR_PLS_SHIFT (17U) +#define ENET_LPI_CSR_PLS_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLS_SHIFT) & ENET_LPI_CSR_PLS_MASK) +#define ENET_LPI_CSR_PLS_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLS_MASK) >> ENET_LPI_CSR_PLS_SHIFT) + +/* + * LPIEN (RW) + * + * LPI Enable + * When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + */ +#define ENET_LPI_CSR_LPIEN_MASK (0x10000UL) +#define ENET_LPI_CSR_LPIEN_SHIFT (16U) +#define ENET_LPI_CSR_LPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPIEN_SHIFT) & ENET_LPI_CSR_LPIEN_MASK) +#define ENET_LPI_CSR_LPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPIEN_MASK) >> ENET_LPI_CSR_LPIEN_SHIFT) + +/* + * RLPIST (RW) + * + * Receive LPI State + * When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. + */ +#define ENET_LPI_CSR_RLPIST_MASK (0x200U) +#define ENET_LPI_CSR_RLPIST_SHIFT (9U) +#define ENET_LPI_CSR_RLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIST_SHIFT) & ENET_LPI_CSR_RLPIST_MASK) +#define ENET_LPI_CSR_RLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIST_MASK) >> ENET_LPI_CSR_RLPIST_SHIFT) + +/* + * TLPIST (RW) + * + * Transmit LPI State + * When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. + */ +#define ENET_LPI_CSR_TLPIST_MASK (0x100U) +#define ENET_LPI_CSR_TLPIST_SHIFT (8U) +#define ENET_LPI_CSR_TLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIST_SHIFT) & ENET_LPI_CSR_TLPIST_MASK) +#define ENET_LPI_CSR_TLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIST_MASK) >> ENET_LPI_CSR_TLPIST_SHIFT) + +/* + * RLPIEX (RW) + * + * Receive LPI Exit + * When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + */ +#define ENET_LPI_CSR_RLPIEX_MASK (0x8U) +#define ENET_LPI_CSR_RLPIEX_SHIFT (3U) +#define ENET_LPI_CSR_RLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEX_SHIFT) & ENET_LPI_CSR_RLPIEX_MASK) +#define ENET_LPI_CSR_RLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEX_MASK) >> ENET_LPI_CSR_RLPIEX_SHIFT) + +/* + * RLPIEN (RW) + * + * Receive LPI Entry + * When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + */ +#define ENET_LPI_CSR_RLPIEN_MASK (0x4U) +#define ENET_LPI_CSR_RLPIEN_SHIFT (2U) +#define ENET_LPI_CSR_RLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEN_SHIFT) & ENET_LPI_CSR_RLPIEN_MASK) +#define ENET_LPI_CSR_RLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEN_MASK) >> ENET_LPI_CSR_RLPIEN_SHIFT) + +/* + * TLPIEX (RW) + * + * Transmit LPI Exit + * When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. + */ +#define ENET_LPI_CSR_TLPIEX_MASK (0x2U) +#define ENET_LPI_CSR_TLPIEX_SHIFT (1U) +#define ENET_LPI_CSR_TLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEX_SHIFT) & ENET_LPI_CSR_TLPIEX_MASK) +#define ENET_LPI_CSR_TLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEX_MASK) >> ENET_LPI_CSR_TLPIEX_SHIFT) + +/* + * TLPIEN (RW) + * + * Transmit LPI Entry + * When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. + */ +#define ENET_LPI_CSR_TLPIEN_MASK (0x1U) +#define ENET_LPI_CSR_TLPIEN_SHIFT (0U) +#define ENET_LPI_CSR_TLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEN_SHIFT) & ENET_LPI_CSR_TLPIEN_MASK) +#define ENET_LPI_CSR_TLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEN_MASK) >> ENET_LPI_CSR_TLPIEN_SHIFT) + +/* Bitfield definition for register: LPI_TCR */ +/* + * LST (RW) + * + * LPI LS TIMER + * This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. + */ +#define ENET_LPI_TCR_LST_MASK (0x3FF0000UL) +#define ENET_LPI_TCR_LST_SHIFT (16U) +#define ENET_LPI_TCR_LST_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_LST_SHIFT) & ENET_LPI_TCR_LST_MASK) +#define ENET_LPI_TCR_LST_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_LST_MASK) >> ENET_LPI_TCR_LST_SHIFT) + +/* + * TWT (RW) + * + * LPI TW TIMER + * This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. + */ +#define ENET_LPI_TCR_TWT_MASK (0xFFFFU) +#define ENET_LPI_TCR_TWT_SHIFT (0U) +#define ENET_LPI_TCR_TWT_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_TWT_SHIFT) & ENET_LPI_TCR_TWT_MASK) +#define ENET_LPI_TCR_TWT_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_TWT_MASK) >> ENET_LPI_TCR_TWT_SHIFT) + +/* Bitfield definition for register: INTR_STATUS */ +/* + * GPIIS (RO) + * + * GPI Interrupt Status + * When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). When the GPIO feature is not enabled, this bit is reserved. + */ +#define ENET_INTR_STATUS_GPIIS_MASK (0x800U) +#define ENET_INTR_STATUS_GPIIS_SHIFT (11U) +#define ENET_INTR_STATUS_GPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_GPIIS_MASK) >> ENET_INTR_STATUS_GPIIS_SHIFT) + +/* + * LPIIS (RO) + * + * LPI Interrupt Status + * When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. + */ +#define ENET_INTR_STATUS_LPIIS_MASK (0x400U) +#define ENET_INTR_STATUS_LPIIS_SHIFT (10U) +#define ENET_INTR_STATUS_LPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_LPIIS_MASK) >> ENET_INTR_STATUS_LPIIS_SHIFT) + +/* + * TSIS (RO) + * + * Timestamp Interrupt Status + * When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - There is an overflow in the seconds register. - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). + */ +#define ENET_INTR_STATUS_TSIS_MASK (0x200U) +#define ENET_INTR_STATUS_TSIS_SHIFT (9U) +#define ENET_INTR_STATUS_TSIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_TSIS_MASK) >> ENET_INTR_STATUS_TSIS_SHIFT) + +/* + * MMCRXIPIS (RO) + * + * MMC Receive Checksum Offload Interrupt Status + * This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + */ +#define ENET_INTR_STATUS_MMCRXIPIS_MASK (0x80U) +#define ENET_INTR_STATUS_MMCRXIPIS_SHIFT (7U) +#define ENET_INTR_STATUS_MMCRXIPIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIPIS_MASK) >> ENET_INTR_STATUS_MMCRXIPIS_SHIFT) + +/* + * MMCTXIS (RO) + * + * MMC Transmit Interrupt Status + * This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + */ +#define ENET_INTR_STATUS_MMCTXIS_MASK (0x40U) +#define ENET_INTR_STATUS_MMCTXIS_SHIFT (6U) +#define ENET_INTR_STATUS_MMCTXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCTXIS_MASK) >> ENET_INTR_STATUS_MMCTXIS_SHIFT) + +/* + * MMCRXIS (RO) + * + * MMC Receive Interrupt Status + * This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. + */ +#define ENET_INTR_STATUS_MMCRXIS_MASK (0x20U) +#define ENET_INTR_STATUS_MMCRXIS_SHIFT (5U) +#define ENET_INTR_STATUS_MMCRXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIS_MASK) >> ENET_INTR_STATUS_MMCRXIS_SHIFT) + +/* + * MMCIS (RO) + * + * MMC Interrupt Status + * This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. + */ +#define ENET_INTR_STATUS_MMCIS_MASK (0x10U) +#define ENET_INTR_STATUS_MMCIS_SHIFT (4U) +#define ENET_INTR_STATUS_MMCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCIS_MASK) >> ENET_INTR_STATUS_MMCIS_SHIFT) + +/* + * PMTIS (RO) + * + * PMT Interrupt Status + * This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. + */ +#define ENET_INTR_STATUS_PMTIS_MASK (0x8U) +#define ENET_INTR_STATUS_PMTIS_SHIFT (3U) +#define ENET_INTR_STATUS_PMTIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PMTIS_MASK) >> ENET_INTR_STATUS_PMTIS_SHIFT) + +/* + * PCSANCIS (RO) + * + * PCS Auto-Negotiation Complete + * This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register. + */ +#define ENET_INTR_STATUS_PCSANCIS_MASK (0x4U) +#define ENET_INTR_STATUS_PCSANCIS_SHIFT (2U) +#define ENET_INTR_STATUS_PCSANCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSANCIS_MASK) >> ENET_INTR_STATUS_PCSANCIS_SHIFT) + +/* + * PCSLCHGIS (RO) + * + * PCS Link Status Changed + * This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register. + */ +#define ENET_INTR_STATUS_PCSLCHGIS_MASK (0x2U) +#define ENET_INTR_STATUS_PCSLCHGIS_SHIFT (1U) +#define ENET_INTR_STATUS_PCSLCHGIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSLCHGIS_MASK) >> ENET_INTR_STATUS_PCSLCHGIS_SHIFT) + +/* + * RGSMIIIS (RO) + * + * RGMII or SMII Interrupt Status + * This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. + */ +#define ENET_INTR_STATUS_RGSMIIIS_MASK (0x1U) +#define ENET_INTR_STATUS_RGSMIIIS_SHIFT (0U) +#define ENET_INTR_STATUS_RGSMIIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_RGSMIIIS_MASK) >> ENET_INTR_STATUS_RGSMIIIS_SHIFT) + +/* Bitfield definition for register: INTR_MASK */ +/* + * LPIIM (RW) + * + * LPI Interrupt Mask + * When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). + */ +#define ENET_INTR_MASK_LPIIM_MASK (0x400U) +#define ENET_INTR_MASK_LPIIM_SHIFT (10U) +#define ENET_INTR_MASK_LPIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_LPIIM_SHIFT) & ENET_INTR_MASK_LPIIM_MASK) +#define ENET_INTR_MASK_LPIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_LPIIM_MASK) >> ENET_INTR_MASK_LPIIM_SHIFT) + +/* + * TSIM (RW) + * + * Timestamp Interrupt Mask + * When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). + */ +#define ENET_INTR_MASK_TSIM_MASK (0x200U) +#define ENET_INTR_MASK_TSIM_SHIFT (9U) +#define ENET_INTR_MASK_TSIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_TSIM_SHIFT) & ENET_INTR_MASK_TSIM_MASK) +#define ENET_INTR_MASK_TSIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_TSIM_MASK) >> ENET_INTR_MASK_TSIM_SHIFT) + +/* + * PMTIM (RW) + * + * PMT Interrupt Mask + * When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). + */ +#define ENET_INTR_MASK_PMTIM_MASK (0x8U) +#define ENET_INTR_MASK_PMTIM_SHIFT (3U) +#define ENET_INTR_MASK_PMTIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PMTIM_SHIFT) & ENET_INTR_MASK_PMTIM_MASK) +#define ENET_INTR_MASK_PMTIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PMTIM_MASK) >> ENET_INTR_MASK_PMTIM_SHIFT) + +/* + * PCSANCIM (RW) + * + * PCS AN Completion Interrupt Mask + * When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). + */ +#define ENET_INTR_MASK_PCSANCIM_MASK (0x4U) +#define ENET_INTR_MASK_PCSANCIM_SHIFT (2U) +#define ENET_INTR_MASK_PCSANCIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSANCIM_SHIFT) & ENET_INTR_MASK_PCSANCIM_MASK) +#define ENET_INTR_MASK_PCSANCIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSANCIM_MASK) >> ENET_INTR_MASK_PCSANCIM_SHIFT) + +/* + * PCSLCHGIM (RW) + * + * PCS Link Status Interrupt Mask + * When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). + */ +#define ENET_INTR_MASK_PCSLCHGIM_MASK (0x2U) +#define ENET_INTR_MASK_PCSLCHGIM_SHIFT (1U) +#define ENET_INTR_MASK_PCSLCHGIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSLCHGIM_SHIFT) & ENET_INTR_MASK_PCSLCHGIM_MASK) +#define ENET_INTR_MASK_PCSLCHGIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSLCHGIM_MASK) >> ENET_INTR_MASK_PCSLCHGIM_SHIFT) + +/* + * RGSMIIIM (RW) + * + * RGMII or SMII Interrupt Mask + * When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). + */ +#define ENET_INTR_MASK_RGSMIIIM_MASK (0x1U) +#define ENET_INTR_MASK_RGSMIIIM_SHIFT (0U) +#define ENET_INTR_MASK_RGSMIIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_RGSMIIIM_SHIFT) & ENET_INTR_MASK_RGSMIIIM_MASK) +#define ENET_INTR_MASK_RGSMIIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_RGSMIIIM_MASK) >> ENET_INTR_MASK_RGSMIIIM_SHIFT) + +/* Bitfield definition for register: MAC_ADDR_0_HIGH */ +/* + * AE (RW) + * + * Address Enable + * This bit is always set to 1. + */ +#define ENET_MAC_ADDR_0_HIGH_AE_MASK (0x80000000UL) +#define ENET_MAC_ADDR_0_HIGH_AE_SHIFT (31U) +#define ENET_MAC_ADDR_0_HIGH_AE_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_HIGH_AE_SHIFT) & ENET_MAC_ADDR_0_HIGH_AE_MASK) +#define ENET_MAC_ADDR_0_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_AE_MASK) >> ENET_MAC_ADDR_0_HIGH_AE_SHIFT) + +/* + * ADDRHI (RW) + * + * MAC Address0 [47:32] + * This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + */ +#define ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK (0xFFFFU) +#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT (0U) +#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) +#define ENET_MAC_ADDR_0_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) + +/* Bitfield definition for register: MAC_ADDR_0_LOW */ +/* + * ADDRLO (RW) + * + * MAC Address0 [31:0] + * This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + */ +#define ENET_MAC_ADDR_0_LOW_ADDRLO_MASK (0xFFFFFFFFUL) +#define ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT (0U) +#define ENET_MAC_ADDR_0_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) +#define ENET_MAC_ADDR_0_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) + +/* Bitfield definition for register of struct array MAC_ADDR: HIGH */ +/* + * AE (RW) + * + * Address Enable + * When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. + */ +#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000UL) +#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U) +#define ENET_MAC_ADDR_HIGH_AE_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_AE_SHIFT) & ENET_MAC_ADDR_HIGH_AE_MASK) +#define ENET_MAC_ADDR_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_AE_MASK) >> ENET_MAC_ADDR_HIGH_AE_SHIFT) + +/* + * SA (RW) + * + * Source Address + * When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + */ +#define ENET_MAC_ADDR_HIGH_SA_MASK (0x40000000UL) +#define ENET_MAC_ADDR_HIGH_SA_SHIFT (30U) +#define ENET_MAC_ADDR_HIGH_SA_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_SA_SHIFT) & ENET_MAC_ADDR_HIGH_SA_MASK) +#define ENET_MAC_ADDR_HIGH_SA_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_SA_MASK) >> ENET_MAC_ADDR_HIGH_SA_SHIFT) + +/* + * MBC (RW) + * + * Mask Byte Control + * These bits are mask control bits for comparison of each of the MAC Address bytes. When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the masking of the bytes as follows: - Bit 29: Register 18[15:8] - Bit 28: Register 18[7:0] - Bit 27: Register 19[31:24] - ... - Bit 24: Register 19[7:0] You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + */ +#define ENET_MAC_ADDR_HIGH_MBC_MASK (0x3F000000UL) +#define ENET_MAC_ADDR_HIGH_MBC_SHIFT (24U) +#define ENET_MAC_ADDR_HIGH_MBC_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_MBC_SHIFT) & ENET_MAC_ADDR_HIGH_MBC_MASK) +#define ENET_MAC_ADDR_HIGH_MBC_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_MBC_MASK) >> ENET_MAC_ADDR_HIGH_MBC_SHIFT) + +/* + * ADDRHI (RW) + * + * MAC Address1 [47:32] + * This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + */ +#define ENET_MAC_ADDR_HIGH_ADDRHI_MASK (0xFFFFU) +#define ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT (0U) +#define ENET_MAC_ADDR_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) +#define ENET_MAC_ADDR_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) + +/* Bitfield definition for register of struct array MAC_ADDR: LOW */ +/* + * ADDRLO (RW) + * + * MAC Address1 [31:0] + * This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. + */ +#define ENET_MAC_ADDR_LOW_ADDRLO_MASK (0xFFFFFFFFUL) +#define ENET_MAC_ADDR_LOW_ADDRLO_SHIFT (0U) +#define ENET_MAC_ADDR_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) +#define ENET_MAC_ADDR_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) + +/* Bitfield definition for register: XMII_CSR */ +/* + * SMIDRXS (RO) + * + * Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal. If the SMII PHY Interface with source synchronous mode is selected during core configuration, this bit is reserved (RO with default value). + */ +#define ENET_XMII_CSR_SMIDRXS_MASK (0x10000UL) +#define ENET_XMII_CSR_SMIDRXS_SHIFT (16U) +#define ENET_XMII_CSR_SMIDRXS_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_SMIDRXS_MASK) >> ENET_XMII_CSR_SMIDRXS_SHIFT) + +/* + * FALSCARDET (RW) + * + * False Carrier Detected + * This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + */ +#define ENET_XMII_CSR_FALSCARDET_MASK (0x20U) +#define ENET_XMII_CSR_FALSCARDET_SHIFT (5U) +#define ENET_XMII_CSR_FALSCARDET_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_FALSCARDET_SHIFT) & ENET_XMII_CSR_FALSCARDET_MASK) +#define ENET_XMII_CSR_FALSCARDET_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_FALSCARDET_MASK) >> ENET_XMII_CSR_FALSCARDET_SHIFT) + +/* + * JABTO (RW) + * + * Jabber Timeout + * This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. + */ +#define ENET_XMII_CSR_JABTO_MASK (0x10U) +#define ENET_XMII_CSR_JABTO_SHIFT (4U) +#define ENET_XMII_CSR_JABTO_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_JABTO_SHIFT) & ENET_XMII_CSR_JABTO_MASK) +#define ENET_XMII_CSR_JABTO_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_JABTO_MASK) >> ENET_XMII_CSR_JABTO_SHIFT) + +/* + * LNKSTS (RW) + * + * Link Status + * This bit indicates whether the link between the local PHY and the remote PHY is up or down. It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. + */ +#define ENET_XMII_CSR_LNKSTS_MASK (0x8U) +#define ENET_XMII_CSR_LNKSTS_SHIFT (3U) +#define ENET_XMII_CSR_LNKSTS_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSTS_SHIFT) & ENET_XMII_CSR_LNKSTS_MASK) +#define ENET_XMII_CSR_LNKSTS_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSTS_MASK) >> ENET_XMII_CSR_LNKSTS_SHIFT) + +/* + * LNKSPEED (RW) + * + * Link Speed + * This bit indicates the current speed of the link: + * - 00: 2.5 MHz + * - 01: 25 MHz + * - 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. + */ +#define ENET_XMII_CSR_LNKSPEED_MASK (0x6U) +#define ENET_XMII_CSR_LNKSPEED_SHIFT (1U) +#define ENET_XMII_CSR_LNKSPEED_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSPEED_SHIFT) & ENET_XMII_CSR_LNKSPEED_MASK) +#define ENET_XMII_CSR_LNKSPEED_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSPEED_MASK) >> ENET_XMII_CSR_LNKSPEED_SHIFT) + +/* + * LNKMOD (RW) + * + * Link Mode + * This bit indicates the current mode of operation of the link: + * - 1’b0: Half-duplex mode + * - 1’b1: Full-duplex mode + */ +#define ENET_XMII_CSR_LNKMOD_MASK (0x1U) +#define ENET_XMII_CSR_LNKMOD_SHIFT (0U) +#define ENET_XMII_CSR_LNKMOD_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKMOD_SHIFT) & ENET_XMII_CSR_LNKMOD_MASK) +#define ENET_XMII_CSR_LNKMOD_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKMOD_MASK) >> ENET_XMII_CSR_LNKMOD_SHIFT) + +/* Bitfield definition for register: WDOG_WTO */ +/* + * PWE (RW) + * + * Programmable Watchdog Enable + * When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). + */ +#define ENET_WDOG_WTO_PWE_MASK (0x10000UL) +#define ENET_WDOG_WTO_PWE_SHIFT (16U) +#define ENET_WDOG_WTO_PWE_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_PWE_SHIFT) & ENET_WDOG_WTO_PWE_MASK) +#define ENET_WDOG_WTO_PWE_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_PWE_MASK) >> ENET_WDOG_WTO_PWE_SHIFT) + +/* + * WTO (RW) + * + * Watchdog Timeout + * When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. + */ +#define ENET_WDOG_WTO_WTO_MASK (0x3FFFU) +#define ENET_WDOG_WTO_WTO_SHIFT (0U) +#define ENET_WDOG_WTO_WTO_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_WTO_SHIFT) & ENET_WDOG_WTO_WTO_MASK) +#define ENET_WDOG_WTO_WTO_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_WTO_MASK) >> ENET_WDOG_WTO_WTO_SHIFT) + +/* Bitfield definition for register: GPIO */ +/* + * GPIT (RW) + * + */ +#define ENET_GPIO_GPIT_MASK (0xF000000UL) +#define ENET_GPIO_GPIT_SHIFT (24U) +#define ENET_GPIO_GPIT_SET(x) (((uint32_t)(x) << ENET_GPIO_GPIT_SHIFT) & ENET_GPIO_GPIT_MASK) +#define ENET_GPIO_GPIT_GET(x) (((uint32_t)(x) & ENET_GPIO_GPIT_MASK) >> ENET_GPIO_GPIT_SHIFT) + +/* + * GPIE (RW) + * + */ +#define ENET_GPIO_GPIE_MASK (0xF0000UL) +#define ENET_GPIO_GPIE_SHIFT (16U) +#define ENET_GPIO_GPIE_SET(x) (((uint32_t)(x) << ENET_GPIO_GPIE_SHIFT) & ENET_GPIO_GPIE_MASK) +#define ENET_GPIO_GPIE_GET(x) (((uint32_t)(x) & ENET_GPIO_GPIE_MASK) >> ENET_GPIO_GPIE_SHIFT) + +/* + * GPO (RW) + * + */ +#define ENET_GPIO_GPO_MASK (0xF00U) +#define ENET_GPIO_GPO_SHIFT (8U) +#define ENET_GPIO_GPO_SET(x) (((uint32_t)(x) << ENET_GPIO_GPO_SHIFT) & ENET_GPIO_GPO_MASK) +#define ENET_GPIO_GPO_GET(x) (((uint32_t)(x) & ENET_GPIO_GPO_MASK) >> ENET_GPIO_GPO_SHIFT) + +/* + * GPIS (RW) + * + */ +#define ENET_GPIO_GPIS_MASK (0xFU) +#define ENET_GPIO_GPIS_SHIFT (0U) +#define ENET_GPIO_GPIS_SET(x) (((uint32_t)(x) << ENET_GPIO_GPIS_SHIFT) & ENET_GPIO_GPIS_MASK) +#define ENET_GPIO_GPIS_GET(x) (((uint32_t)(x) & ENET_GPIO_GPIS_MASK) >> ENET_GPIO_GPIS_SHIFT) + +/* Bitfield definition for register: MMC_CNTRL */ +/* + * UCDBC (RW) + * + * Update MMC Counters for Dropped Broadcast Frames + * When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). When reset, the MMC Counters are not updated for dropped Broadcast frames. + */ +#define ENET_MMC_CNTRL_UCDBC_MASK (0x100U) +#define ENET_MMC_CNTRL_UCDBC_SHIFT (8U) +#define ENET_MMC_CNTRL_UCDBC_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_UCDBC_SHIFT) & ENET_MMC_CNTRL_UCDBC_MASK) +#define ENET_MMC_CNTRL_UCDBC_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_UCDBC_MASK) >> ENET_MMC_CNTRL_UCDBC_SHIFT) + +/* + * CNTPRSTLVL (RW) + * + * Full-Half Preset + * When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half + * - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half + * - 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full + * - 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full + * - 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. + */ +#define ENET_MMC_CNTRL_CNTPRSTLVL_MASK (0x20U) +#define ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT (5U) +#define ENET_MMC_CNTRL_CNTPRSTLVL_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) +#define ENET_MMC_CNTRL_CNTPRSTLVL_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) >> ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) + +/* + * CNTPRST (RW) + * + * Counters Preset + * When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. + */ +#define ENET_MMC_CNTRL_CNTPRST_MASK (0x10U) +#define ENET_MMC_CNTRL_CNTPRST_SHIFT (4U) +#define ENET_MMC_CNTRL_CNTPRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRST_SHIFT) & ENET_MMC_CNTRL_CNTPRST_MASK) +#define ENET_MMC_CNTRL_CNTPRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRST_MASK) >> ENET_MMC_CNTRL_CNTPRST_SHIFT) + +/* + * CNTFREEZ (RW) + * + * MMC Counter Freeze + * When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. + */ +#define ENET_MMC_CNTRL_CNTFREEZ_MASK (0x8U) +#define ENET_MMC_CNTRL_CNTFREEZ_SHIFT (3U) +#define ENET_MMC_CNTRL_CNTFREEZ_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTFREEZ_SHIFT) & ENET_MMC_CNTRL_CNTFREEZ_MASK) +#define ENET_MMC_CNTRL_CNTFREEZ_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTFREEZ_MASK) >> ENET_MMC_CNTRL_CNTFREEZ_SHIFT) + +/* + * RSTONRD (RW) + * + * Reset on Read + * When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. + */ +#define ENET_MMC_CNTRL_RSTONRD_MASK (0x4U) +#define ENET_MMC_CNTRL_RSTONRD_SHIFT (2U) +#define ENET_MMC_CNTRL_RSTONRD_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_RSTONRD_SHIFT) & ENET_MMC_CNTRL_RSTONRD_MASK) +#define ENET_MMC_CNTRL_RSTONRD_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_RSTONRD_MASK) >> ENET_MMC_CNTRL_RSTONRD_SHIFT) + +/* + * CNTSTOPRO (RW) + * + * Counter Stop Rollover + * When this bit is set, the counter does not roll over to zero after reaching the maximum value. + */ +#define ENET_MMC_CNTRL_CNTSTOPRO_MASK (0x2U) +#define ENET_MMC_CNTRL_CNTSTOPRO_SHIFT (1U) +#define ENET_MMC_CNTRL_CNTSTOPRO_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) +#define ENET_MMC_CNTRL_CNTSTOPRO_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) >> ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) + +/* + * CNTRST (RW) + * + * Counters Reset + * When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle + */ +#define ENET_MMC_CNTRL_CNTRST_MASK (0x1U) +#define ENET_MMC_CNTRL_CNTRST_SHIFT (0U) +#define ENET_MMC_CNTRL_CNTRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTRST_SHIFT) & ENET_MMC_CNTRL_CNTRST_MASK) +#define ENET_MMC_CNTRL_CNTRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTRST_MASK) >> ENET_MMC_CNTRL_CNTRST_SHIFT) + +/* Bitfield definition for register: MMC_INTR_RX */ +/* + * RXCTRLFIS (RW) + * + * MMC Receive Control Frame Counter Interrupt Status + * This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXCTRLFIS_MASK (0x2000000UL) +#define ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT (25U) +#define ENET_MMC_INTR_RX_RXCTRLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) +#define ENET_MMC_INTR_RX_RXCTRLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) >> ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) + +/* + * RXRCVERRFIS (RW) + * + * MMC Receive Error Frame Counter Interrupt Status + * This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXRCVERRFIS_MASK (0x1000000UL) +#define ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT (24U) +#define ENET_MMC_INTR_RX_RXRCVERRFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) +#define ENET_MMC_INTR_RX_RXRCVERRFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) >> ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) + +/* + * RXWDOGFIS (RW) + * + * MMC Receive Watchdog Error Frame Counter Interrupt Status + * This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXWDOGFIS_MASK (0x800000UL) +#define ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT (23U) +#define ENET_MMC_INTR_RX_RXWDOGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) +#define ENET_MMC_INTR_RX_RXWDOGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) >> ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) + +/* + * RXVLANGBFIS (RW) + * + * MMC Receive VLAN Good Bad Frame Counter Interrupt Status + * This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXVLANGBFIS_MASK (0x400000UL) +#define ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT (22U) +#define ENET_MMC_INTR_RX_RXVLANGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) +#define ENET_MMC_INTR_RX_RXVLANGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) >> ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) + +/* + * RXFOVFIS (RW) + * + * MMC Receive FIFO Overflow Frame Counter Interrupt Status + * This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXFOVFIS_MASK (0x200000UL) +#define ENET_MMC_INTR_RX_RXFOVFIS_SHIFT (21U) +#define ENET_MMC_INTR_RX_RXFOVFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) +#define ENET_MMC_INTR_RX_RXFOVFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) >> ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) + +/* + * RXPAUSFIS (RW) + * + * MMC Receive Pause Frame Counter Interrupt Status + * This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXPAUSFIS_MASK (0x100000UL) +#define ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT (20U) +#define ENET_MMC_INTR_RX_RXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) +#define ENET_MMC_INTR_RX_RXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) >> ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) + +/* + * RXORANGEFIS (RW) + * + * MMC Receive Out Of Range Error Frame Counter Interrupt Status. + * This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXORANGEFIS_MASK (0x80000UL) +#define ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT (19U) +#define ENET_MMC_INTR_RX_RXORANGEFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) +#define ENET_MMC_INTR_RX_RXORANGEFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) >> ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) + +/* + * RXLENERFIS (RW) + * + * MMC Receive Length Error Frame Counter Interrupt Status + * This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXLENERFIS_MASK (0x40000UL) +#define ENET_MMC_INTR_RX_RXLENERFIS_SHIFT (18U) +#define ENET_MMC_INTR_RX_RXLENERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) +#define ENET_MMC_INTR_RX_RXLENERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) >> ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) + +/* + * RXUCGFIS (RW) + * + * MMC Receive Unicast Good Frame Counter Interrupt Status + * This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXUCGFIS_MASK (0x20000UL) +#define ENET_MMC_INTR_RX_RXUCGFIS_SHIFT (17U) +#define ENET_MMC_INTR_RX_RXUCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) +#define ENET_MMC_INTR_RX_RXUCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) >> ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) + +/* + * RX1024TMAXOCTGBFIS (RW) + * + * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. + * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK (0x10000UL) +#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT (16U) +#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) +#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) + +/* + * RX512T1023OCTGBFIS (RW) + * + * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK (0x8000U) +#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT (15U) +#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) +#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) + +/* + * RX256T511OCTGBFIS (RW) + * + * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK (0x4000U) +#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT (14U) +#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) +#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) + +/* + * RX128T255OCTGBFIS (RW) + * + * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK (0x2000U) +#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT (13U) +#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) +#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) + +/* + * RX65T127OCTGBFIS (RW) + * + * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK (0x1000U) +#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT (12U) +#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) +#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) + +/* + * RX64OCTGBFIS (RW) + * + * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK (0x800U) +#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT (11U) +#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) +#define ENET_MMC_INTR_RX_RX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) + +/* + * RXOSIZEGFIS (RW) + * + * MMC Receive Oversize Good Frame Counter Interrupt Status + * This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK (0x400U) +#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT (10U) +#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) +#define ENET_MMC_INTR_RX_RXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) + +/* + * RXUSIZEGFIS (RW) + * + * MMC Receive Undersize Good Frame Counter Interrupt Status + * This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK (0x200U) +#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT (9U) +#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) +#define ENET_MMC_INTR_RX_RXUSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) + +/* + * RXJABERFIS (RW) + * + * MMC Receive Jabber Error Frame Counter Interrupt Status + * This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXJABERFIS_MASK (0x100U) +#define ENET_MMC_INTR_RX_RXJABERFIS_SHIFT (8U) +#define ENET_MMC_INTR_RX_RXJABERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) +#define ENET_MMC_INTR_RX_RXJABERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) >> ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) + +/* + * RXRUNTFIS (RW) + * + * MMC Receive Runt Frame Counter Interrupt Status + * This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXRUNTFIS_MASK (0x80U) +#define ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT (7U) +#define ENET_MMC_INTR_RX_RXRUNTFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) +#define ENET_MMC_INTR_RX_RXRUNTFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) >> ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) + +/* + * RXALGNERFIS (RW) + * + * MMC Receive Alignment Error Frame Counter Interrupt Status + * This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXALGNERFIS_MASK (0x40U) +#define ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT (6U) +#define ENET_MMC_INTR_RX_RXALGNERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) +#define ENET_MMC_INTR_RX_RXALGNERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) >> ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) + +/* + * RXCRCERFIS (RW) + * + * MMC Receive CRC Error Frame Counter Interrupt Status + * This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXCRCERFIS_MASK (0x20U) +#define ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT (5U) +#define ENET_MMC_INTR_RX_RXCRCERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) +#define ENET_MMC_INTR_RX_RXCRCERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) >> ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) + +/* + * RXMCGFIS (RW) + * + * MMC Receive Multicast Good Frame Counter Interrupt Status + * This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXMCGFIS_MASK (0x10U) +#define ENET_MMC_INTR_RX_RXMCGFIS_SHIFT (4U) +#define ENET_MMC_INTR_RX_RXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) +#define ENET_MMC_INTR_RX_RXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) >> ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) + +/* + * RXBCGFIS (RW) + * + * MMC Receive Broadcast Good Frame Counter Interrupt Status + * This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXBCGFIS_MASK (0x8U) +#define ENET_MMC_INTR_RX_RXBCGFIS_SHIFT (3U) +#define ENET_MMC_INTR_RX_RXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) +#define ENET_MMC_INTR_RX_RXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) >> ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) + +/* + * RXGOCTIS (RW) + * + * MMC Receive Good Octet Counter Interrupt Status + * This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXGOCTIS_MASK (0x4U) +#define ENET_MMC_INTR_RX_RXGOCTIS_SHIFT (2U) +#define ENET_MMC_INTR_RX_RXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) +#define ENET_MMC_INTR_RX_RXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) + +/* + * RXGBOCTIS (RW) + * + * MMC Receive Good Bad Octet Counter Interrupt Status + * This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXGBOCTIS_MASK (0x2U) +#define ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT (1U) +#define ENET_MMC_INTR_RX_RXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) +#define ENET_MMC_INTR_RX_RXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) + +/* + * RXGBFRMIS (RW) + * + * MMC Receive Good Bad Frame Counter Interrupt Status + * This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_RX_RXGBFRMIS_MASK (0x1U) +#define ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT (0U) +#define ENET_MMC_INTR_RX_RXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) +#define ENET_MMC_INTR_RX_RXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) >> ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) + +/* Bitfield definition for register: MMC_INTR_TX */ +/* + * TXOSIZEGFIS (RW) + * + * MMC Transmit Oversize Good Frame Counter Interrupt Status + * This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK (0x2000000UL) +#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT (25U) +#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) +#define ENET_MMC_INTR_TX_TXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) >> ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) + +/* + * TXVLANGFIS (RW) + * + * MMC Transmit VLAN Good Frame Counter Interrupt Status + * This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXVLANGFIS_MASK (0x1000000UL) +#define ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT (24U) +#define ENET_MMC_INTR_TX_TXVLANGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) +#define ENET_MMC_INTR_TX_TXVLANGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) >> ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) + +/* + * TXPAUSFIS (RW) + * + * MMC Transmit Pause Frame Counter Interrupt Status + * This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXPAUSFIS_MASK (0x800000UL) +#define ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT (23U) +#define ENET_MMC_INTR_TX_TXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) +#define ENET_MMC_INTR_TX_TXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) >> ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) + +/* + * TXEXDEFFIS (RW) + * + * MMC Transmit Excessive Deferral Frame Counter Interrupt Status + * This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXEXDEFFIS_MASK (0x400000UL) +#define ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT (22U) +#define ENET_MMC_INTR_TX_TXEXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) +#define ENET_MMC_INTR_TX_TXEXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) + +/* + * TXGFRMIS (RW) + * + * MMC Transmit Good Frame Counter Interrupt Status + * This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXGFRMIS_MASK (0x200000UL) +#define ENET_MMC_INTR_TX_TXGFRMIS_SHIFT (21U) +#define ENET_MMC_INTR_TX_TXGFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) +#define ENET_MMC_INTR_TX_TXGFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) + +/* + * TXGOCTIS (RW) + * + * MMC Transmit Good Octet Counter Interrupt Status + * This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXGOCTIS_MASK (0x100000UL) +#define ENET_MMC_INTR_TX_TXGOCTIS_SHIFT (20U) +#define ENET_MMC_INTR_TX_TXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) +#define ENET_MMC_INTR_TX_TXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) + +/* + * TXCARERFIS (RW) + * + * MMC Transmit Carrier Error Frame Counter Interrupt Status + * This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXCARERFIS_MASK (0x80000UL) +#define ENET_MMC_INTR_TX_TXCARERFIS_SHIFT (19U) +#define ENET_MMC_INTR_TX_TXCARERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) +#define ENET_MMC_INTR_TX_TXCARERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) >> ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) + +/* + * TXEXCOLFIS (RW) + * + * MMC Transmit Excessive Collision Frame Counter Interrupt Status + * This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXEXCOLFIS_MASK (0x40000UL) +#define ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT (18U) +#define ENET_MMC_INTR_TX_TXEXCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) +#define ENET_MMC_INTR_TX_TXEXCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) + +/* + * TXLATCOLFIS (RW) + * + * MMC Transmit Late Collision Frame Counter Interrupt Status + * This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXLATCOLFIS_MASK (0x20000UL) +#define ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT (17U) +#define ENET_MMC_INTR_TX_TXLATCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) +#define ENET_MMC_INTR_TX_TXLATCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) + +/* + * TXDEFFIS (RW) + * + * MMC Transmit Deferred Frame Counter Interrupt Status + * This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXDEFFIS_MASK (0x10000UL) +#define ENET_MMC_INTR_TX_TXDEFFIS_SHIFT (16U) +#define ENET_MMC_INTR_TX_TXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) +#define ENET_MMC_INTR_TX_TXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) + +/* + * TXMCOLGFIS (RW) + * + * MMC Transmit Multiple Collision Good Frame Counter Interrupt Status + * This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXMCOLGFIS_MASK (0x8000U) +#define ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT (15U) +#define ENET_MMC_INTR_TX_TXMCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) +#define ENET_MMC_INTR_TX_TXMCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) + +/* + * TXSCOLGFIS (RW) + * + * MMC Transmit Single Collision Good Frame Counter Interrupt Status + * This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXSCOLGFIS_MASK (0x4000U) +#define ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT (14U) +#define ENET_MMC_INTR_TX_TXSCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) +#define ENET_MMC_INTR_TX_TXSCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) + +/* + * TXUFLOWERFIS (RW) + * + * MMC Transmit Underflow Error Frame Counter Interrupt Status + * This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK (0x2000U) +#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT (13U) +#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) +#define ENET_MMC_INTR_TX_TXUFLOWERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) >> ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) + +/* + * TXBCGBFIS (RW) + * + * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status + * This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXBCGBFIS_MASK (0x1000U) +#define ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT (12U) +#define ENET_MMC_INTR_TX_TXBCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) +#define ENET_MMC_INTR_TX_TXBCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) + +/* + * TXMCGBFIS (RW) + * + * MMC Transmit Multicast Good Bad Frame Counter Interrupt Status + * The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXMCGBFIS_MASK (0x800U) +#define ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT (11U) +#define ENET_MMC_INTR_TX_TXMCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) +#define ENET_MMC_INTR_TX_TXMCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) + +/* + * TXUCGBFIS (RW) + * + * MMC Transmit Unicast Good Bad Frame Counter Interrupt Status + * This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXUCGBFIS_MASK (0x400U) +#define ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT (10U) +#define ENET_MMC_INTR_TX_TXUCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) +#define ENET_MMC_INTR_TX_TXUCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) + +/* + * TX1024TMAXOCTGBFIS (RW) + * + * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK (0x200U) +#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT (9U) +#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) +#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) + +/* + * TX512T1023OCTGBFIS (RW) + * + * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK (0x100U) +#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT (8U) +#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) +#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) + +/* + * TX256T511OCTGBFIS (RW) + * + * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK (0x80U) +#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT (7U) +#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) +#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) + +/* + * TX128T255OCTGBFIS (RW) + * + * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK (0x40U) +#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT (6U) +#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) +#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) + +/* + * TX65T127OCTGBFIS (RW) + * + * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. + */ +#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK (0x20U) +#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT (5U) +#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) +#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) + +/* + * TX64OCTGBFIS (RW) + * + * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status + * This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK (0x10U) +#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT (4U) +#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) +#define ENET_MMC_INTR_TX_TX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) + +/* + * TXMCGFIS (RW) + * + * MMC Transmit Multicast Good Frame Counter Interrupt Status + * This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXMCGFIS_MASK (0x8U) +#define ENET_MMC_INTR_TX_TXMCGFIS_SHIFT (3U) +#define ENET_MMC_INTR_TX_TXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) +#define ENET_MMC_INTR_TX_TXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) + +/* + * TXBCGFIS (RW) + * + * MMC Transmit Broadcast Good Frame Counter Interrupt Status + * This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXBCGFIS_MASK (0x4U) +#define ENET_MMC_INTR_TX_TXBCGFIS_SHIFT (2U) +#define ENET_MMC_INTR_TX_TXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) +#define ENET_MMC_INTR_TX_TXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) + +/* + * TXGBFRMIS (RW) + * + * MMC Transmit Good Bad Frame Counter Interrupt Status + * This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXGBFRMIS_MASK (0x2U) +#define ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT (1U) +#define ENET_MMC_INTR_TX_TXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) +#define ENET_MMC_INTR_TX_TXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) + +/* + * TXGBOCTIS (RW) + * + * MMC Transmit Good Bad Octet Counter Interrupt Status + * This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_TX_TXGBOCTIS_MASK (0x1U) +#define ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT (0U) +#define ENET_MMC_INTR_TX_TXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) +#define ENET_MMC_INTR_TX_TXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) + +/* Bitfield definition for register: MMC_INTR_MASK_RX */ +/* + * RXCTRLFIM (RW) + * + * MMC Receive Control Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK (0x2000000UL) +#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT (25U) +#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) + +/* + * RXRCVERRFIM (RW) + * + * MMC Receive Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK (0x1000000UL) +#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT (24U) +#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) + +/* + * RXWDOGFIM (RW) + * + * MMC Receive Watchdog Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK (0x800000UL) +#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT (23U) +#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) + +/* + * RXVLANGBFIM (RW) + * + * MMC Receive VLAN Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK (0x400000UL) +#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT (22U) +#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) + +/* + * RXFOVFIM (RW) + * + * MMC Receive FIFO Overflow Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK (0x200000UL) +#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT (21U) +#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) + +/* + * RXPAUSFIM (RW) + * + * MMC Receive Pause Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK (0x100000UL) +#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT (20U) +#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) + +/* + * RXORANGEFIM (RW) + * + * MMC Receive Out Of Range Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK (0x80000UL) +#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT (19U) +#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) + +/* + * RXLENERFIM (RW) + * + * MMC Receive Length Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK (0x40000UL) +#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT (18U) +#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) + +/* + * RXUCGFIM (RW) + * + * MMC Receive Unicast Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK (0x20000UL) +#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT (17U) +#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) + +/* + * RX1024TMAXOCTGBFIM (RW) + * + * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. + * Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK (0x10000UL) +#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT (16U) +#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) + +/* + * RX512T1023OCTGBFIM (RW) + * + * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK (0x8000U) +#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT (15U) +#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) + +/* + * RX256T511OCTGBFIM (RW) + * + * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK (0x4000U) +#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT (14U) +#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) + +/* + * RX128T255OCTGBFIM (RW) + * + * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK (0x2000U) +#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT (13U) +#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) + +/* + * RX65T127OCTGBFIM (RW) + * + * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK (0x1000U) +#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT (12U) +#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) + +/* + * RX64OCTGBFIM (RW) + * + * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK (0x800U) +#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT (11U) +#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) + +/* + * RXOSIZEGFIM (RW) + * + * MMC Receive Oversize Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK (0x400U) +#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT (10U) +#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) + +/* + * RXUSIZEGFIM (RW) + * + * MMC Receive Undersize Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK (0x200U) +#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT (9U) +#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) + +/* + * RXJABERFIM (RW) + * + * MMC Receive Jabber Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK (0x100U) +#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT (8U) +#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) + +/* + * RXRUNTFIM (RW) + * + * MMC Receive Runt Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK (0x80U) +#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT (7U) +#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) + +/* + * RXALGNERFIM (RW) + * + * MMC Receive Alignment Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK (0x40U) +#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT (6U) +#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) + +/* + * RXCRCERFIM (RW) + * + * MMC Receive CRC Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK (0x20U) +#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT (5U) +#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) + +/* + * RXMCGFIM (RW) + * + * MMC Receive Multicast Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK (0x10U) +#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT (4U) +#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) + +/* + * RXBCGFIM (RW) + * + * MMC Receive Broadcast Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK (0x8U) +#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT (3U) +#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) + +/* + * RXGOCTIM (RW) + * + * MMC Receive Good Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK (0x4U) +#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT (2U) +#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) + +/* + * RXGBOCTIM (RW) + * + * MMC Receive Good Bad Octet Counter Interrupt Mask. + * Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK (0x2U) +#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT (1U) +#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) +#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) + +/* Bitfield definition for register: MMC_INTR_MASK_TX */ +/* + * TXOSIZEGFIM (RW) + * + * MMC Transmit Oversize Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK (0x2000000UL) +#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT (25U) +#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) + +/* + * TXVLANGFIM (RW) + * + * MMC Transmit VLAN Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK (0x1000000UL) +#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT (24U) +#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) + +/* + * TXPAUSFIM (RW) + * + * MMC Transmit Pause Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK (0x800000UL) +#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT (23U) +#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) + +/* + * TXEXDEFFIM (RW) + * + * MMC Transmit Excessive Deferral Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK (0x400000UL) +#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT (22U) +#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) + +/* + * TXGFRMIM (RW) + * + * MMC Transmit Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK (0x200000UL) +#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT (21U) +#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) + +/* + * TXGOCTIM (RW) + * + * MMC Transmit Good Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK (0x100000UL) +#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT (20U) +#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) + +/* + * TXCARERFIM (RW) + * + * MMC Transmit Carrier Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK (0x80000UL) +#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT (19U) +#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) + +/* + * TXEXCOLFIM (RW) + * + * MMC Transmit Excessive Collision Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK (0x40000UL) +#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT (18U) +#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) + +/* + * TXLATCOLFIM (RW) + * + * MMC Transmit Late Collision Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK (0x20000UL) +#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT (17U) +#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) + +/* + * TXDEFFIM (RW) + * + * MMC Transmit Deferred Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK (0x10000UL) +#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT (16U) +#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) + +/* + * TXMCOLGFIM (RW) + * + * MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK (0x8000U) +#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT (15U) +#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) + +/* + * TXSCOLGFIM (RW) + * + * MMC Transmit Single Collision Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK (0x4000U) +#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT (14U) +#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) + +/* + * TXUFLOWERFIM (RW) + * + * MMC Transmit Underflow Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK (0x2000U) +#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT (13U) +#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) + +/* + * TXBCGBFIM (RW) + * + * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK (0x1000U) +#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT (12U) +#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) + +/* + * TXMCGBFIM (RW) + * + * MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK (0x800U) +#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT (11U) +#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) + +/* + * TXUCGBFIM (RW) + * + * MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK (0x400U) +#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT (10U) +#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) + +/* + * TX1024TMAXOCTGBFIM (RW) + * + * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK (0x200U) +#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT (9U) +#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) + +/* + * TX512T1023OCTGBFIM (RW) + * + * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK (0x100U) +#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT (8U) +#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) + +/* + * TX256T511OCTGBFIM (RW) + * + * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK (0x80U) +#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT (7U) +#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) + +/* + * TX128T255OCTGBFIM (RW) + * + * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK (0x40U) +#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT (6U) +#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) + +/* + * TX65T127OCTGBFIM (RW) + * + * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK (0x20U) +#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT (5U) +#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) + +/* + * TX64OCTGBFIM (RW) + * + * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK (0x10U) +#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT (4U) +#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) + +/* + * TXMCGFIM (RW) + * + * MMC Transmit Multicast Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK (0x8U) +#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT (3U) +#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) + +/* + * TXBCGFIM (RW) + * + * MMC Transmit Broadcast Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK (0x4U) +#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT (2U) +#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) + +/* + * TXGBFRMIM (RW) + * + * MMC Transmit Good Bad Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK (0x2U) +#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT (1U) +#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) + +/* + * TXGBOCTIM (RW) + * + * MMC Transmit Good Bad Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK (0x1U) +#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT (0U) +#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) +#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) + +/* Bitfield definition for register: TXOCTETCOUNT_GB */ +/* + * BYTECNT (RW) + * + * Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames. + */ +#define ENET_TXOCTETCOUNT_GB_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_TXOCTETCOUNT_GB_BYTECNT_SHIFT (0U) +#define ENET_TXOCTETCOUNT_GB_BYTECNT_SET(x) (((uint32_t)(x) << ENET_TXOCTETCOUNT_GB_BYTECNT_SHIFT) & ENET_TXOCTETCOUNT_GB_BYTECNT_MASK) +#define ENET_TXOCTETCOUNT_GB_BYTECNT_GET(x) (((uint32_t)(x) & ENET_TXOCTETCOUNT_GB_BYTECNT_MASK) >> ENET_TXOCTETCOUNT_GB_BYTECNT_SHIFT) + +/* Bitfield definition for register: TXFRAMECOUNT_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames transmitted, exclusive of retried frames. + */ +#define ENET_TXFRAMECOUNT_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXFRAMECOUNT_GB_FRMCNT_SHIFT (0U) +#define ENET_TXFRAMECOUNT_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXFRAMECOUNT_GB_FRMCNT_SHIFT) & ENET_TXFRAMECOUNT_GB_FRMCNT_MASK) +#define ENET_TXFRAMECOUNT_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXFRAMECOUNT_GB_FRMCNT_MASK) >> ENET_TXFRAMECOUNT_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXBROADCASTFRAMES_G */ +/* + * FRMCNT (RW) + * + * Number of good broadcast frames transmitted. + */ +#define ENET_TXBROADCASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXBROADCASTFRAMES_G_FRMCNT_SHIFT (0U) +#define ENET_TXBROADCASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXBROADCASTFRAMES_G_FRMCNT_SHIFT) & ENET_TXBROADCASTFRAMES_G_FRMCNT_MASK) +#define ENET_TXBROADCASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXBROADCASTFRAMES_G_FRMCNT_MASK) >> ENET_TXBROADCASTFRAMES_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXMLTICASTFRAMES_G */ +/* + * FRMCNT (RW) + * + * Number of good multicast frames transmitted. + */ +#define ENET_TXMLTICASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXMLTICASTFRAMES_G_FRMCNT_SHIFT (0U) +#define ENET_TXMLTICASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXMLTICASTFRAMES_G_FRMCNT_SHIFT) & ENET_TXMLTICASTFRAMES_G_FRMCNT_MASK) +#define ENET_TXMLTICASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXMLTICASTFRAMES_G_FRMCNT_MASK) >> ENET_TXMLTICASTFRAMES_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: TX64OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. + */ +#define ENET_TX64OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TX64OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_TX64OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX64OCTETS_GB_FRMCNT_SHIFT) & ENET_TX64OCTETS_GB_FRMCNT_MASK) +#define ENET_TX64OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX64OCTETS_GB_FRMCNT_MASK) >> ENET_TX64OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TX65TO127OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. + */ +#define ENET_TX65TO127OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_TX65TO127OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) +#define ENET_TX65TO127OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) >> ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TX128TO255OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. + */ +#define ENET_TX128TO255OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_TX128TO255OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) +#define ENET_TX128TO255OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) >> ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TX256TO511OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. + */ +#define ENET_TX256TO511OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_TX256TO511OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) +#define ENET_TX256TO511OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) >> ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TX512TO1023OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. + */ +#define ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) +#define ENET_TX512TO1023OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) >> ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TX1024TOMAXOCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + */ +#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) +#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXUNICASTFRAMES_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad unicast frames transmitted. + */ +#define ENET_TXUNICASTFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXUNICASTFRAMES_GB_FRMCNT_SHIFT (0U) +#define ENET_TXUNICASTFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXUNICASTFRAMES_GB_FRMCNT_SHIFT) & ENET_TXUNICASTFRAMES_GB_FRMCNT_MASK) +#define ENET_TXUNICASTFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXUNICASTFRAMES_GB_FRMCNT_MASK) >> ENET_TXUNICASTFRAMES_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXMULTICASTFRAMES_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad multicast frames transmitted. + */ +#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_SHIFT (0U) +#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXMULTICASTFRAMES_GB_FRMCNT_SHIFT) & ENET_TXMULTICASTFRAMES_GB_FRMCNT_MASK) +#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXMULTICASTFRAMES_GB_FRMCNT_MASK) >> ENET_TXMULTICASTFRAMES_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXBROADCASTFRAMES_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad broadcast frames transmitted. + */ +#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_SHIFT (0U) +#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXBROADCASTFRAMES_GB_FRMCNT_SHIFT) & ENET_TXBROADCASTFRAMES_GB_FRMCNT_MASK) +#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXBROADCASTFRAMES_GB_FRMCNT_MASK) >> ENET_TXBROADCASTFRAMES_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXUNDERFLOWERROR */ +/* + * FRMCNT (RW) + * + * Number of frames aborted because of frame underflow error. + */ +#define ENET_TXUNDERFLOWERROR_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXUNDERFLOWERROR_FRMCNT_SHIFT (0U) +#define ENET_TXUNDERFLOWERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXUNDERFLOWERROR_FRMCNT_SHIFT) & ENET_TXUNDERFLOWERROR_FRMCNT_MASK) +#define ENET_TXUNDERFLOWERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXUNDERFLOWERROR_FRMCNT_MASK) >> ENET_TXUNDERFLOWERROR_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXSINGLECOL_G */ +/* + * FRMCNT (RW) + * + * Number of successfully transmitted frames after a single collision in the half-duplex mode. + */ +#define ENET_TXSINGLECOL_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXSINGLECOL_G_FRMCNT_SHIFT (0U) +#define ENET_TXSINGLECOL_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXSINGLECOL_G_FRMCNT_SHIFT) & ENET_TXSINGLECOL_G_FRMCNT_MASK) +#define ENET_TXSINGLECOL_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXSINGLECOL_G_FRMCNT_MASK) >> ENET_TXSINGLECOL_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXMULTICOL_G */ +/* + * FRMCNT (RW) + * + * Number of successfully transmitted frames after multiple collisions in the half-duplex mode. + */ +#define ENET_TXMULTICOL_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXMULTICOL_G_FRMCNT_SHIFT (0U) +#define ENET_TXMULTICOL_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXMULTICOL_G_FRMCNT_SHIFT) & ENET_TXMULTICOL_G_FRMCNT_MASK) +#define ENET_TXMULTICOL_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXMULTICOL_G_FRMCNT_MASK) >> ENET_TXMULTICOL_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXDEFERRED */ +/* + * FRMCNT (RW) + * + * Number of successfully transmitted frames after a deferral in the half-duplex mode. + */ +#define ENET_TXDEFERRED_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXDEFERRED_FRMCNT_SHIFT (0U) +#define ENET_TXDEFERRED_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXDEFERRED_FRMCNT_SHIFT) & ENET_TXDEFERRED_FRMCNT_MASK) +#define ENET_TXDEFERRED_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXDEFERRED_FRMCNT_MASK) >> ENET_TXDEFERRED_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXLATECOL */ +/* + * FRMCNT (RW) + * + * Number of frames aborted because of late collision error. + */ +#define ENET_TXLATECOL_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXLATECOL_FRMCNT_SHIFT (0U) +#define ENET_TXLATECOL_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXLATECOL_FRMCNT_SHIFT) & ENET_TXLATECOL_FRMCNT_MASK) +#define ENET_TXLATECOL_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXLATECOL_FRMCNT_MASK) >> ENET_TXLATECOL_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXEXESSCOL */ +/* + * FRMCNT (RW) + * + * Number of frames aborted because of excessive (16) collision errors. + */ +#define ENET_TXEXESSCOL_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXEXESSCOL_FRMCNT_SHIFT (0U) +#define ENET_TXEXESSCOL_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXEXESSCOL_FRMCNT_SHIFT) & ENET_TXEXESSCOL_FRMCNT_MASK) +#define ENET_TXEXESSCOL_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXEXESSCOL_FRMCNT_MASK) >> ENET_TXEXESSCOL_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXCARRIERERROR */ +/* + * FRMCNT (RW) + * + * Number of frames aborted because of carrier sense error (no carrier or loss of carrier). + */ +#define ENET_TXCARRIERERROR_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXCARRIERERROR_FRMCNT_SHIFT (0U) +#define ENET_TXCARRIERERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXCARRIERERROR_FRMCNT_SHIFT) & ENET_TXCARRIERERROR_FRMCNT_MASK) +#define ENET_TXCARRIERERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXCARRIERERROR_FRMCNT_MASK) >> ENET_TXCARRIERERROR_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXOCTETCOUNT_G */ +/* + * BYTECNT (RW) + * + * Number of bytes transmitted, exclusive of preamble, only in good frames. + */ +#define ENET_TXOCTETCOUNT_G_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_TXOCTETCOUNT_G_BYTECNT_SHIFT (0U) +#define ENET_TXOCTETCOUNT_G_BYTECNT_SET(x) (((uint32_t)(x) << ENET_TXOCTETCOUNT_G_BYTECNT_SHIFT) & ENET_TXOCTETCOUNT_G_BYTECNT_MASK) +#define ENET_TXOCTETCOUNT_G_BYTECNT_GET(x) (((uint32_t)(x) & ENET_TXOCTETCOUNT_G_BYTECNT_MASK) >> ENET_TXOCTETCOUNT_G_BYTECNT_SHIFT) + +/* Bitfield definition for register: TXFRAMECOUNT_G */ +/* + * FRMCNT (RW) + * + * Number of good frames transmitted. + */ +#define ENET_TXFRAMECOUNT_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXFRAMECOUNT_G_FRMCNT_SHIFT (0U) +#define ENET_TXFRAMECOUNT_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXFRAMECOUNT_G_FRMCNT_SHIFT) & ENET_TXFRAMECOUNT_G_FRMCNT_MASK) +#define ENET_TXFRAMECOUNT_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXFRAMECOUNT_G_FRMCNT_MASK) >> ENET_TXFRAMECOUNT_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXEXCESSDEF */ +/* + * FRMCNT (RW) + * + * Number of frames aborted because of excessive deferral error (deferred for more than two max-sized frame times). + */ +#define ENET_TXEXCESSDEF_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXEXCESSDEF_FRMCNT_SHIFT (0U) +#define ENET_TXEXCESSDEF_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXEXCESSDEF_FRMCNT_SHIFT) & ENET_TXEXCESSDEF_FRMCNT_MASK) +#define ENET_TXEXCESSDEF_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXEXCESSDEF_FRMCNT_MASK) >> ENET_TXEXCESSDEF_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXPAUSEFRAMES */ +/* + * FRMCNT (RW) + * + * Number of good Pause frames transmitted. + */ +#define ENET_TXPAUSEFRAMES_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXPAUSEFRAMES_FRMCNT_SHIFT (0U) +#define ENET_TXPAUSEFRAMES_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXPAUSEFRAMES_FRMCNT_SHIFT) & ENET_TXPAUSEFRAMES_FRMCNT_MASK) +#define ENET_TXPAUSEFRAMES_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXPAUSEFRAMES_FRMCNT_MASK) >> ENET_TXPAUSEFRAMES_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXVLANFRAMES_G */ +/* + * FRMCNT (RW) + * + * Number of good VLAN frames transmitted, exclusive of retried frames. + */ +#define ENET_TXVLANFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXVLANFRAMES_G_FRMCNT_SHIFT (0U) +#define ENET_TXVLANFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXVLANFRAMES_G_FRMCNT_SHIFT) & ENET_TXVLANFRAMES_G_FRMCNT_MASK) +#define ENET_TXVLANFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXVLANFRAMES_G_FRMCNT_MASK) >> ENET_TXVLANFRAMES_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: TXOVERSIZE_G */ +/* + * FRMCNT (RW) + * + * Number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). + */ +#define ENET_TXOVERSIZE_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TXOVERSIZE_G_FRMCNT_SHIFT (0U) +#define ENET_TXOVERSIZE_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXOVERSIZE_G_FRMCNT_SHIFT) & ENET_TXOVERSIZE_G_FRMCNT_MASK) +#define ENET_TXOVERSIZE_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXOVERSIZE_G_FRMCNT_MASK) >> ENET_TXOVERSIZE_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXFRAMECOUNT_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames received. + */ +#define ENET_RXFRAMECOUNT_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT (0U) +#define ENET_RXFRAMECOUNT_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) +#define ENET_RXFRAMECOUNT_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) >> ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXOCTETCOUNT_G */ +/* + * BYTECNT (RW) + * + * Number of bytes received, exclusive of preamble, in good and bad frames. + */ +#define ENET_RXOCTETCOUNT_G_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXOCTETCOUNT_G_BYTECNT_SHIFT (0U) +#define ENET_RXOCTETCOUNT_G_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXOCTETCOUNT_G_BYTECNT_SHIFT) & ENET_RXOCTETCOUNT_G_BYTECNT_MASK) +#define ENET_RXOCTETCOUNT_G_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXOCTETCOUNT_G_BYTECNT_MASK) >> ENET_RXOCTETCOUNT_G_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXOCTETCOUNT_GB */ +/* + * BYTECNT (RW) + * + * Number of bytes received, exclusive of preamble, only in good frames. + */ +#define ENET_RXOCTETCOUNT_GB_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXOCTETCOUNT_GB_BYTECNT_SHIFT (0U) +#define ENET_RXOCTETCOUNT_GB_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXOCTETCOUNT_GB_BYTECNT_SHIFT) & ENET_RXOCTETCOUNT_GB_BYTECNT_MASK) +#define ENET_RXOCTETCOUNT_GB_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXOCTETCOUNT_GB_BYTECNT_MASK) >> ENET_RXOCTETCOUNT_GB_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXBROADCASTFRAMES_G */ +/* + * FRMCNT (RW) + * + * Number of good broadcast frames received. + */ +#define ENET_RXBROADCASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXBROADCASTFRAMES_G_FRMCNT_SHIFT (0U) +#define ENET_RXBROADCASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXBROADCASTFRAMES_G_FRMCNT_SHIFT) & ENET_RXBROADCASTFRAMES_G_FRMCNT_MASK) +#define ENET_RXBROADCASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXBROADCASTFRAMES_G_FRMCNT_MASK) >> ENET_RXBROADCASTFRAMES_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXMULTICASTFRAMES_G */ +/* + * FRMCNT (RW) + * + * Number of good multicast frames received. + */ +#define ENET_RXMULTICASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXMULTICASTFRAMES_G_FRMCNT_SHIFT (0U) +#define ENET_RXMULTICASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXMULTICASTFRAMES_G_FRMCNT_SHIFT) & ENET_RXMULTICASTFRAMES_G_FRMCNT_MASK) +#define ENET_RXMULTICASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXMULTICASTFRAMES_G_FRMCNT_MASK) >> ENET_RXMULTICASTFRAMES_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXCRCERROR */ +/* + * FRMCNT (RW) + * + * Number of frames received with CRC error. + */ +#define ENET_RXCRCERROR_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXCRCERROR_FRMCNT_SHIFT (0U) +#define ENET_RXCRCERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXCRCERROR_FRMCNT_SHIFT) & ENET_RXCRCERROR_FRMCNT_MASK) +#define ENET_RXCRCERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXCRCERROR_FRMCNT_MASK) >> ENET_RXCRCERROR_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXALIGNMENTERROR */ +/* + * FRMCNT (RW) + * + * Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. + */ +#define ENET_RXALIGNMENTERROR_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXALIGNMENTERROR_FRMCNT_SHIFT (0U) +#define ENET_RXALIGNMENTERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXALIGNMENTERROR_FRMCNT_SHIFT) & ENET_RXALIGNMENTERROR_FRMCNT_MASK) +#define ENET_RXALIGNMENTERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXALIGNMENTERROR_FRMCNT_MASK) >> ENET_RXALIGNMENTERROR_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXRUNTERROR */ +/* + * FRMCNT (RW) + * + * Number of frames received with runt (<64 bytes and CRC error) error. + */ +#define ENET_RXRUNTERROR_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXRUNTERROR_FRMCNT_SHIFT (0U) +#define ENET_RXRUNTERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXRUNTERROR_FRMCNT_SHIFT) & ENET_RXRUNTERROR_FRMCNT_MASK) +#define ENET_RXRUNTERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXRUNTERROR_FRMCNT_MASK) >> ENET_RXRUNTERROR_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXJABBERERROR */ +/* + * FRMCNT (RW) + * + * Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. + */ +#define ENET_RXJABBERERROR_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXJABBERERROR_FRMCNT_SHIFT (0U) +#define ENET_RXJABBERERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXJABBERERROR_FRMCNT_SHIFT) & ENET_RXJABBERERROR_FRMCNT_MASK) +#define ENET_RXJABBERERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXJABBERERROR_FRMCNT_MASK) >> ENET_RXJABBERERROR_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXUNDERSIZE_G */ +/* + * FRMCNT (RW) + * + * Number of frames received with length less than 64 bytes, without any errors. + */ +#define ENET_RXUNDERSIZE_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXUNDERSIZE_G_FRMCNT_SHIFT (0U) +#define ENET_RXUNDERSIZE_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUNDERSIZE_G_FRMCNT_SHIFT) & ENET_RXUNDERSIZE_G_FRMCNT_MASK) +#define ENET_RXUNDERSIZE_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUNDERSIZE_G_FRMCNT_MASK) >> ENET_RXUNDERSIZE_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXOVERSIZE_G */ +/* + * FRMCNT (RW) + * + * Number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). + */ +#define ENET_RXOVERSIZE_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXOVERSIZE_G_FRMCNT_SHIFT (0U) +#define ENET_RXOVERSIZE_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXOVERSIZE_G_FRMCNT_SHIFT) & ENET_RXOVERSIZE_G_FRMCNT_MASK) +#define ENET_RXOVERSIZE_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXOVERSIZE_G_FRMCNT_MASK) >> ENET_RXOVERSIZE_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: RX64OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames received with length 64 bytes, exclusive of preamble. + */ +#define ENET_RX64OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RX64OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_RX64OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX64OCTETS_GB_FRMCNT_SHIFT) & ENET_RX64OCTETS_GB_FRMCNT_MASK) +#define ENET_RX64OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX64OCTETS_GB_FRMCNT_MASK) >> ENET_RX64OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: RX65TO127OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. + */ +#define ENET_RX65TO127OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RX65TO127OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_RX65TO127OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX65TO127OCTETS_GB_FRMCNT_SHIFT) & ENET_RX65TO127OCTETS_GB_FRMCNT_MASK) +#define ENET_RX65TO127OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX65TO127OCTETS_GB_FRMCNT_MASK) >> ENET_RX65TO127OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: RX128TO255OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. + */ +#define ENET_RX128TO255OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RX128TO255OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_RX128TO255OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX128TO255OCTETS_GB_FRMCNT_SHIFT) & ENET_RX128TO255OCTETS_GB_FRMCNT_MASK) +#define ENET_RX128TO255OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX128TO255OCTETS_GB_FRMCNT_MASK) >> ENET_RX128TO255OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: RX256TO511OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. + */ +#define ENET_RX256TO511OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RX256TO511OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_RX256TO511OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX256TO511OCTETS_GB_FRMCNT_SHIFT) & ENET_RX256TO511OCTETS_GB_FRMCNT_MASK) +#define ENET_RX256TO511OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX256TO511OCTETS_GB_FRMCNT_MASK) >> ENET_RX256TO511OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: RX512TO1023OCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. + */ +#define ENET_RX512TO1023OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RX512TO1023OCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_RX512TO1023OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX512TO1023OCTETS_GB_FRMCNT_SHIFT) & ENET_RX512TO1023OCTETS_GB_FRMCNT_MASK) +#define ENET_RX512TO1023OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX512TO1023OCTETS_GB_FRMCNT_MASK) >> ENET_RX512TO1023OCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: RX1024TOMAXOCTETS_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. + */ +#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_RX1024TOMAXOCTETS_GB_FRMCNT_MASK) +#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXUNICASTFRAMES_G */ +/* + * FRMCNT (RW) + * + * Number of received good unicast frames. + */ +#define ENET_RXUNICASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXUNICASTFRAMES_G_FRMCNT_SHIFT (0U) +#define ENET_RXUNICASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUNICASTFRAMES_G_FRMCNT_SHIFT) & ENET_RXUNICASTFRAMES_G_FRMCNT_MASK) +#define ENET_RXUNICASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUNICASTFRAMES_G_FRMCNT_MASK) >> ENET_RXUNICASTFRAMES_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXLENGTHERROR */ +/* + * FRMCNT (RW) + * + * Number of frames received with length error (Length type field ≠ frame size), for all frames with valid length field. + */ +#define ENET_RXLENGTHERROR_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXLENGTHERROR_FRMCNT_SHIFT (0U) +#define ENET_RXLENGTHERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXLENGTHERROR_FRMCNT_SHIFT) & ENET_RXLENGTHERROR_FRMCNT_MASK) +#define ENET_RXLENGTHERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXLENGTHERROR_FRMCNT_MASK) >> ENET_RXLENGTHERROR_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXOUTOFRANGETYPE */ +/* + * FRMCNT (RW) + * + * Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). + */ +#define ENET_RXOUTOFRANGETYPE_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXOUTOFRANGETYPE_FRMCNT_SHIFT (0U) +#define ENET_RXOUTOFRANGETYPE_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXOUTOFRANGETYPE_FRMCNT_SHIFT) & ENET_RXOUTOFRANGETYPE_FRMCNT_MASK) +#define ENET_RXOUTOFRANGETYPE_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXOUTOFRANGETYPE_FRMCNT_MASK) >> ENET_RXOUTOFRANGETYPE_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXPAUSEFRAMES */ +/* + * FRMCNT (RW) + * + * Number of good and valid Pause frames received. + */ +#define ENET_RXPAUSEFRAMES_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXPAUSEFRAMES_FRMCNT_SHIFT (0U) +#define ENET_RXPAUSEFRAMES_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXPAUSEFRAMES_FRMCNT_SHIFT) & ENET_RXPAUSEFRAMES_FRMCNT_MASK) +#define ENET_RXPAUSEFRAMES_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXPAUSEFRAMES_FRMCNT_MASK) >> ENET_RXPAUSEFRAMES_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXFIFOOVERFLOW */ +/* + * FRMCNT (RW) + * + * Number of missed received frames because of FIFO overflow. This counter is not present in the GMAC-CORE configuration. + */ +#define ENET_RXFIFOOVERFLOW_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXFIFOOVERFLOW_FRMCNT_SHIFT (0U) +#define ENET_RXFIFOOVERFLOW_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFIFOOVERFLOW_FRMCNT_SHIFT) & ENET_RXFIFOOVERFLOW_FRMCNT_MASK) +#define ENET_RXFIFOOVERFLOW_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFIFOOVERFLOW_FRMCNT_MASK) >> ENET_RXFIFOOVERFLOW_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXVLANFRAMES_GB */ +/* + * FRMCNT (RW) + * + * Number of good and bad VLAN frames received. + */ +#define ENET_RXVLANFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXVLANFRAMES_GB_FRMCNT_SHIFT (0U) +#define ENET_RXVLANFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXVLANFRAMES_GB_FRMCNT_SHIFT) & ENET_RXVLANFRAMES_GB_FRMCNT_MASK) +#define ENET_RXVLANFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXVLANFRAMES_GB_FRMCNT_MASK) >> ENET_RXVLANFRAMES_GB_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXWATCHDOGERROR */ +/* + * FRMCNT (RW) + * + * Number of frames received with error because of watchdog timeout error (frames with a data load larger than 2,048 bytes or the value programmed in Register 55 (Watchdog Timeout Register)). + */ +#define ENET_RXWATCHDOGERROR_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXWATCHDOGERROR_FRMCNT_SHIFT (0U) +#define ENET_RXWATCHDOGERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXWATCHDOGERROR_FRMCNT_SHIFT) & ENET_RXWATCHDOGERROR_FRMCNT_MASK) +#define ENET_RXWATCHDOGERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXWATCHDOGERROR_FRMCNT_MASK) >> ENET_RXWATCHDOGERROR_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXRCVERROR */ +/* + * FRMCNT (RW) + * + * Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. + */ +#define ENET_RXRCVERROR_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXRCVERROR_FRMCNT_SHIFT (0U) +#define ENET_RXRCVERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXRCVERROR_FRMCNT_SHIFT) & ENET_RXRCVERROR_FRMCNT_MASK) +#define ENET_RXRCVERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXRCVERROR_FRMCNT_MASK) >> ENET_RXRCVERROR_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXCTRLFRAMES_G */ +/* + * FRMCNT (RW) + * + * Number of received good control frames. + */ +#define ENET_RXCTRLFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXCTRLFRAMES_G_FRMCNT_SHIFT (0U) +#define ENET_RXCTRLFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXCTRLFRAMES_G_FRMCNT_SHIFT) & ENET_RXCTRLFRAMES_G_FRMCNT_MASK) +#define ENET_RXCTRLFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXCTRLFRAMES_G_FRMCNT_MASK) >> ENET_RXCTRLFRAMES_G_FRMCNT_SHIFT) + +/* Bitfield definition for register: MMC_IPC_INTR_MASK_RX */ +/* + * RXICMPEROIM (RW) + * + * MMC Receive ICMP Error Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK (0x20000000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT (29U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) + +/* + * RXICMPGOIM (RW) + * + * MMC Receive ICMP Good Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK (0x10000000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT (28U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) + +/* + * RXTCPEROIM (RW) + * + * MMC Receive TCP Error Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK (0x8000000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT (27U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) + +/* + * RXTCPGOIM (RW) + * + * MMC Receive TCP Good Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK (0x4000000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT (26U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) + +/* + * RXUDPEROIM (RW) + * + * MMC Receive UDP Good Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK (0x2000000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT (25U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) + +/* + * RXUDPGOIM (RW) + * + * MMC Receive IPV6 No Payload Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK (0x1000000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT (24U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) + +/* + * RXIPV6NOPAYOIM (RW) + * + * MMC Receive IPV6 Header Error Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK (0x800000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT (23U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) + +/* + * RXIPV6HEROIM (RW) + * + * MMC Receive IPV6 Good Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK (0x400000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT (22U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) + +/* + * RXIPV6GOIM (RW) + * + * MMC Receive IPV6 Good Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK (0x200000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT (21U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) + +/* + * RXIPV4UDSBLOIM (RW) + * + * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK (0x100000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT (20U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) + +/* + * RXIPV4FRAGOIM (RW) + * + * MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK (0x80000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT (19U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) + +/* + * RXIPV4NOPAYOIM (RW) + * + * MMC Receive IPV4 No Payload Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK (0x40000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT (18U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) + +/* + * RXIPV4HEROIM (RW) + * + * MMC Receive IPV4 Header Error Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK (0x20000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT (17U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) + +/* + * RXIPV4GOIM (RW) + * + * MMC Receive IPV4 Good Octet Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK (0x10000UL) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT (16U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) + +/* + * RXICMPERFIM (RW) + * + * MMC Receive ICMP Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK (0x2000U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT (13U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) + +/* + * RXICMPGFIM (RW) + * + * MMC Receive ICMP Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK (0x1000U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT (12U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) + +/* + * RXTCPERFIM (RW) + * + * MMC Receive TCP Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK (0x800U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT (11U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) + +/* + * RXTCPGFIM (RW) + * + * MMC Receive TCP Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK (0x400U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT (10U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) + +/* + * RXUDPERFIM (RW) + * + * MMC Receive UDP Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK (0x200U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT (9U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) + +/* + * RXUDPGFIM (RW) + * + * MMC Receive UDP Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK (0x100U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT (8U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) + +/* + * RXIPV6NOPAYFIM (RW) + * + * MMC Receive IPV6 No Payload Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK (0x80U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT (7U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) + +/* + * RXIPV6HERFIM (RW) + * + * MMC Receive IPV6 Header Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK (0x40U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT (6U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) + +/* + * RXIPV6GFIM (RW) + * + * MMC Receive IPV6 Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK (0x20U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT (5U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) + +/* + * RXIPV4UDSBLFIM (RW) + * + * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK (0x10U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT (4U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) + +/* + * RXIPV4FRAGFIM (RW) + * + * MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK (0x8U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT (3U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) + +/* + * RXIPV4NOPAYFIM (RW) + * + * MMC Receive IPV4 No Payload Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK (0x4U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT (2U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) + +/* + * RXIPV4HERFIM (RW) + * + * MMC Receive IPV4 Header Error Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK (0x2U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT (1U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) + +/* + * RXIPV4GFIM (RW) + * + * MMC Receive IPV4 Good Frame Counter Interrupt Mask + * Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK (0x1U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT (0U) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) +#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) + +/* Bitfield definition for register: MMC_IPC_INTR_RX */ +/* + * RXICMPEROIS (RW) + * + * MMC Receive ICMP Error Octet Counter Interrupt Status + * This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK (0x20000000UL) +#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT (29U) +#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) + +/* + * RXICMPGOIS (RW) + * + * MMC Receive ICMP Good Octet Counter Interrupt Status + * This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK (0x10000000UL) +#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT (28U) +#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) + +/* + * RXTCPEROIS (RW) + * + * MMC Receive TCP Error Octet Counter Interrupt Status + * This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK (0x8000000UL) +#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT (27U) +#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) + +/* + * RXTCPGOIS (RW) + * + * MMC Receive TCP Good Octet Counter Interrupt Status + * This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value + */ +#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK (0x4000000UL) +#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT (26U) +#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) + +/* + * RXUDPEROIS (RW) + * + * MMC Receive UDP Error Octet Counter Interrupt Status + * This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK (0x2000000UL) +#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT (25U) +#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) + +/* + * RXUDPGOIS (RW) + * + * MMC Receive UDP Good Octet Counter Interrupt Status + * This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK (0x1000000UL) +#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT (24U) +#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) + +/* + * RXIPV6NOPAYOIS (RW) + * + * MMC Receive IPV6 No Payload Octet Counter Interrupt Status + * This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK (0x800000UL) +#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT (23U) +#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) + +/* + * RXIPV6HEROIS (RW) + * + * MMC Receive IPV6 Header Error Octet Counter Interrupt Status + * This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK (0x400000UL) +#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT (22U) +#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) + +/* + * RXIPV6GOIS (RW) + * + * MMC Receive IPV6 Good Octet Counter Interrupt Status + * This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK (0x200000UL) +#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT (21U) +#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) + +/* + * RXIPV4UDSBLOIS (RW) + * + * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status + * This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK (0x100000UL) +#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT (20U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) + +/* + * RXIPV4FRAGOIS (RW) + * + * MMC Receive IPV4 Fragmented Octet Counter Interrupt Status + * This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK (0x80000UL) +#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT (19U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) + +/* + * RXIPV4NOPAYOIS (RW) + * + * MMC Receive IPV4 No Payload Octet Counter Interrupt Status + * This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK (0x40000UL) +#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT (18U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) + +/* + * RXIPV4HEROIS (RW) + * + * MMC Receive IPV4 Header Error Octet Counter Interrupt Status + * This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK (0x20000UL) +#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT (17U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) + +/* + * RXIPV4GOIS (RW) + * + * MMC Receive IPV4 Good Octet Counter Interrupt Status + * This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK (0x10000UL) +#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT (16U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) + +/* + * RXICMPERFIS (RW) + * + * MMC Receive ICMP Error Frame Counter Interrupt Status + * This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK (0x2000U) +#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT (13U) +#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) + +/* + * RXICMPGFIS (RW) + * + * MMC Receive ICMP Good Frame Counter Interrupt Status + * This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK (0x1000U) +#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT (12U) +#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) + +/* + * RXTCPERFIS (RW) + * + * MMC Receive TCP Error Frame Counter Interrupt Status + * This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK (0x800U) +#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT (11U) +#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) + +/* + * RXTCPGFIS (RW) + * + * MMC Receive TCP Good Frame Counter Interrupt Status + * This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK (0x400U) +#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT (10U) +#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) + +/* + * RXUDPERFIS (RW) + * + * MMC Receive UDP Error Frame Counter Interrupt Status + * This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK (0x200U) +#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT (9U) +#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) + +/* + * RXUDPGFIS (RW) + * + * MMC Receive UDP Good Frame Counter Interrupt Status + * This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK (0x100U) +#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT (8U) +#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) + +/* + * RXIPV6NOPAYFIS (RW) + * + * MMC Receive IPV6 No Payload Frame Counter Interrupt Status + * This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK (0x80U) +#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT (7U) +#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) + +/* + * RXIPV6HERFIS (RW) + * + * MMC Receive IPV6 Header Error Frame Counter Interrupt Status + * This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK (0x40U) +#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT (6U) +#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) + +/* + * RXIPV6GFIS (RW) + * + * MMC Receive IPV6 Good Frame Counter Interrupt Status + * This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK (0x20U) +#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT (5U) +#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) + +/* + * RXIPV4UDSBLFIS (RW) + * + * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status + * This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK (0x10U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT (4U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) + +/* + * RXIPV4FRAGFIS (RW) + * + * MMC Receive IPV4 Fragmented Frame Counter Interrupt Status + * This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK (0x8U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT (3U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) + +/* + * RXIPV4NOPAYFIS (RW) + * + * MMC Receive IPV4 No Payload Frame Counter Interrupt Status + * This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK (0x4U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT (2U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) + +/* + * RXIPV4HERFIS (RW) + * + * MMC Receive IPV4 Header Error Frame Counter Interrupt Status + * This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK (0x2U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT (1U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) + +/* + * RXIPV4GFIS (RW) + * + * MMC Receive IPV4 Good Frame Counter Interrupt Status + * This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. + */ +#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK (0x1U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT (0U) +#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) +#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) + +/* Bitfield definition for register: RXIPV4_GD_FMS */ +/* + * FRMCNT (RW) + * + * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload + */ +#define ENET_RXIPV4_GD_FMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT (0U) +#define ENET_RXIPV4_GD_FMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) +#define ENET_RXIPV4_GD_FMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) >> ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXIPV4_HDRERR_FRMS */ +/* + * FRMCNT (RW) + * + * Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors + */ +#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_HDRERR_FRMS_FRMCNT_MASK) +#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_HDRERR_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXIPV4_NOPAY_FRMS */ +/* + * FRMCNT (RW) + * + * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine + */ +#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_NOPAY_FRMS_FRMCNT_MASK) +#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_NOPAY_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXIPV4_FRAG_FRMS */ +/* + * FRMCNT (RW) + * + * Number of good IPv4 datagrams with fragmentation + */ +#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_FRAG_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_FRAG_FRMS_FRMCNT_MASK) +#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_FRAG_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_FRAG_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXIPV4_UDSBL_FRMS */ +/* + * FRMCNT (RW) + * + * Number of good IPv4 datagrams received that had a UDP payload with checksum disabled + */ +#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_UDSBL_FRMS_FRMCNT_MASK) +#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_UDSBL_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXIPV6_GD_FRMS */ +/* + * FRMCNT (RW) + * + * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads + */ +#define ENET_RXIPV6_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV6_GD_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXIPV6_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_GD_FRMS_FRMCNT_SHIFT) & ENET_RXIPV6_GD_FRMS_FRMCNT_MASK) +#define ENET_RXIPV6_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_GD_FRMS_FRMCNT_MASK) >> ENET_RXIPV6_GD_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXIPV6_HDRERR_FRMS */ +/* + * FRMCNT (RW) + * + * Number of IPv6 datagrams received with header errors (length or version mismatch) + */ +#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SHIFT) & ENET_RXIPV6_HDRERR_FRMS_FRMCNT_MASK) +#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_HDRERR_FRMS_FRMCNT_MASK) >> ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXIPV6_NOPAY_FRMS */ +/* + * FRMCNT (RW) + * + * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers + */ +#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SHIFT) & ENET_RXIPV6_NOPAY_FRMS_FRMCNT_MASK) +#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_NOPAY_FRMS_FRMCNT_MASK) >> ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXUDP_GD_FRMS */ +/* + * FRMCNT (RW) + * + * Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. + */ +#define ENET_RXUDP_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXUDP_GD_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXUDP_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_GD_FRMS_FRMCNT_SHIFT) & ENET_RXUDP_GD_FRMS_FRMCNT_MASK) +#define ENET_RXUDP_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_GD_FRMS_FRMCNT_MASK) >> ENET_RXUDP_GD_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXUDP_ERR_FRMS */ +/* + * FRMCNT (RW) + * + * Number of good IP datagrams whose UDP payload has a checksum error + */ +#define ENET_RXUDP_ERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXUDP_ERR_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXUDP_ERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_ERR_FRMS_FRMCNT_SHIFT) & ENET_RXUDP_ERR_FRMS_FRMCNT_MASK) +#define ENET_RXUDP_ERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_ERR_FRMS_FRMCNT_MASK) >> ENET_RXUDP_ERR_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXTCP_GD_FRMS */ +/* + * FRMCNT (RW) + * + * Number of good IP datagrams with a good TCP payload + */ +#define ENET_RXTCP_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXTCP_GD_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXTCP_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_GD_FRMS_FRMCNT_SHIFT) & ENET_RXTCP_GD_FRMS_FRMCNT_MASK) +#define ENET_RXTCP_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_GD_FRMS_FRMCNT_MASK) >> ENET_RXTCP_GD_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXTCP_ERR_FRMS */ +/* + * FRMCNT (RW) + * + * Number of good IP datagrams whose TCP payload has a checksum error + */ +#define ENET_RXTCP_ERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXTCP_ERR_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXTCP_ERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_ERR_FRMS_FRMCNT_SHIFT) & ENET_RXTCP_ERR_FRMS_FRMCNT_MASK) +#define ENET_RXTCP_ERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_ERR_FRMS_FRMCNT_MASK) >> ENET_RXTCP_ERR_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXICMP_GD_FRMS */ +/* + * FRMCNT (RW) + * + * Number of good IP datagrams with a good ICMP payload + */ +#define ENET_RXICMP_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXICMP_GD_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXICMP_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXICMP_GD_FRMS_FRMCNT_SHIFT) & ENET_RXICMP_GD_FRMS_FRMCNT_MASK) +#define ENET_RXICMP_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXICMP_GD_FRMS_FRMCNT_MASK) >> ENET_RXICMP_GD_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXICMP_ERR_FRMS */ +/* + * FRMCNT (RW) + * + * Number of good IP datagrams whose ICMP payload has a checksum error + */ +#define ENET_RXICMP_ERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXICMP_ERR_FRMS_FRMCNT_SHIFT (0U) +#define ENET_RXICMP_ERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXICMP_ERR_FRMS_FRMCNT_SHIFT) & ENET_RXICMP_ERR_FRMS_FRMCNT_MASK) +#define ENET_RXICMP_ERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXICMP_ERR_FRMS_FRMCNT_MASK) >> ENET_RXICMP_ERR_FRMS_FRMCNT_SHIFT) + +/* Bitfield definition for register: RXIPV4_GD_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). + */ +#define ENET_RXIPV4_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_GD_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXIPV4_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_GD_OCTETS_BYTECNT_MASK) +#define ENET_RXIPV4_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_GD_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXIPV4_HDRERR_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. + */ +#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_MASK) +#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXIPV4_NOPAY_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header’s Length field is used to update this counter. + */ +#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_MASK) +#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXIPV4_FRAG_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header’s Length field is used to update this counter. + */ +#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_FRAG_OCTETS_BYTECNT_MASK) +#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_FRAG_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXIPV4_UDSBL_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. + */ +#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_MASK) +#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXIPV6_GD_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data + */ +#define ENET_RXIPV6_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV6_GD_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXIPV6_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV6_GD_OCTETS_BYTECNT_MASK) +#define ENET_RXIPV6_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_GD_OCTETS_BYTECNT_MASK) >> ENET_RXIPV6_GD_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXIPV6_HDRERR_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header’s Length field is used to update this counter. + */ +#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_MASK) +#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_MASK) >> ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXIPV6_NOPAY_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header’s Length field is used to update this counter. + */ +#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_MASK) +#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_MASK) >> ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXUDP_GD_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. + */ +#define ENET_RXUDP_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXUDP_GD_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXUDP_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXUDP_GD_OCTETS_BYTECNT_MASK) +#define ENET_RXUDP_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_GD_OCTETS_BYTECNT_MASK) >> ENET_RXUDP_GD_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXUDP_ERR_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in a UDP segment that had checksum errors + */ +#define ENET_RXUDP_ERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXUDP_ERR_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXUDP_ERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_ERR_OCTETS_BYTECNT_SHIFT) & ENET_RXUDP_ERR_OCTETS_BYTECNT_MASK) +#define ENET_RXUDP_ERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_ERR_OCTETS_BYTECNT_MASK) >> ENET_RXUDP_ERR_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXTCP_GD_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in a good TCP segment + */ +#define ENET_RXTCP_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXTCP_GD_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXTCP_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXTCP_GD_OCTETS_BYTECNT_MASK) +#define ENET_RXTCP_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_GD_OCTETS_BYTECNT_MASK) >> ENET_RXTCP_GD_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXTCP_ERR_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in a TCP segment with checksum errors + */ +#define ENET_RXTCP_ERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXTCP_ERR_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXTCP_ERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_ERR_OCTETS_BYTECNT_SHIFT) & ENET_RXTCP_ERR_OCTETS_BYTECNT_MASK) +#define ENET_RXTCP_ERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_ERR_OCTETS_BYTECNT_MASK) >> ENET_RXTCP_ERR_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register: RXICMP_GD_OCTETS */ +/* + * BYTECNT (RW) + * + * Number of bytes received in a good ICMP segment + */ +#define ENET_RXICMP_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) +#define ENET_RXICMP_GD_OCTETS_BYTECNT_SHIFT (0U) +#define ENET_RXICMP_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXICMP_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXICMP_GD_OCTETS_BYTECNT_MASK) +#define ENET_RXICMP_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXICMP_GD_OCTETS_BYTECNT_MASK) >> ENET_RXICMP_GD_OCTETS_BYTECNT_SHIFT) + +/* Bitfield definition for register of struct array L3_L4_CFG: L3_L4_CTRL */ +/* + * L4DPIM0 (RW) + * + * Layer 4 Destination Port Inverse Match Enable + * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK (0x200000UL) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT (21U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) + +/* + * L4DPM0 (RW) + * + * Layer 4 Destination Port Match Enable + * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK (0x100000UL) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT (20U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) + +/* + * L4SPIM0 (RW) + * + * Layer 4 Source Port Inverse Match Enable + * When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK (0x80000UL) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT (19U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) + +/* + * L4SPM0 (RW) + * + * Layer 4 Source Port Match Enable + * When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK (0x40000UL) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT (18U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) + +/* + * L4PEN0 (RW) + * + * Layer 4 Protocol Enable + * When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK (0x10000UL) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT (16U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) + +/* + * L3HDBM0 (RW) + * + * Layer 3 IP DA Higher Bits Match + * IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: + * - 0: No bits are masked. + * - 1: LSb[0] is masked. + * - 2: Two LSbs [1:0] are masked. - ... + * - 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: + * - 0: No bits are masked. + * - 1: LSb[0] is masked. + * - 2: Two LSbs [1:0] are masked. - … + * - 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK (0xF800U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT (11U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) + +/* + * L3HSBM0 (RW) + * + * Layer 3 IP SA Higher Bits Match + * IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: + * - 0: No bits are masked. + * - 1: LSb[0] is masked. + * - 2: Two LSbs [1:0] are masked. - ... + * - 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK (0x7C0U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT (6U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) + +/* + * L3DAIM0 (RW) + * + * Layer 3 IP DA Inverse Match Enable + * When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK (0x20U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT (5U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) + +/* + * L3DAM0 (RW) + * + * Layer 3 IP DA Match Enable + * When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK (0x10U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT (4U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) + +/* + * L3SAIM0 (RW) + * + * Layer 3 IP SA Inverse Match Enable + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK (0x8U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT (3U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) + +/* + * L3SAM0 (RW) + * + * Layer 3 IP SA Match Enable + * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK (0x4U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT (2U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) + +/* + * L3PEN0 (RW) + * + * Layer 3 Protocol Enable + * When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + */ +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK (0x1U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT (0U) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) +#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) + +/* Bitfield definition for register of struct array L3_L4_CFG: L4_ADDR */ +/* + * L4DP0 (RW) + * + * Layer 4 Destination Port Number Field + * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + */ +#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK (0xFFFF0000UL) +#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT (16U) +#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) +#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) + +/* + * L4SP0 (RW) + * + * Layer 4 Source Port Number Field + * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + */ +#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK (0xFFFFU) +#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT (0U) +#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) +#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) + +/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_0 */ +/* + * L3A00 (RW) + * + * Layer 3 Address 0 Field + * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + */ +#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK (0xFFFFFFFFUL) +#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT (0U) +#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) +#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) >> ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) + +/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_1 */ +/* + * L3A10 (RW) + * + * Layer 3 Address 1 Field + * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + */ +#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK (0xFFFFFFFFUL) +#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT (0U) +#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) +#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) >> ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) + +/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_2 */ +/* + * L3A20 (RW) + * + * Layer 3 Address 2 Field + * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + */ +#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK (0xFFFFFFFFUL) +#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT (0U) +#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) +#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) >> ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) + +/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_3 */ +/* + * L3A30 (RW) + * + * Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + */ +#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK (0xFFFFFFFFUL) +#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT (0U) +#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) +#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) >> ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) + +/* Bitfield definition for register array: HASH_TABLE */ +/* + * HT31T0 (RW) + * + * First 32 bits of Hash Table + * This field contains the first 32 Bits (31:0) of the Hash table. + */ +#define ENET_HASH_TABLE_HT31T0_MASK (0xFFFFFFFFUL) +#define ENET_HASH_TABLE_HT31T0_SHIFT (0U) +#define ENET_HASH_TABLE_HT31T0_SET(x) (((uint32_t)(x) << ENET_HASH_TABLE_HT31T0_SHIFT) & ENET_HASH_TABLE_HT31T0_MASK) +#define ENET_HASH_TABLE_HT31T0_GET(x) (((uint32_t)(x) & ENET_HASH_TABLE_HT31T0_MASK) >> ENET_HASH_TABLE_HT31T0_SHIFT) + +/* Bitfield definition for register: VLAN_TAG_INC_RPL */ +/* + * CSVL (RW) + * + * C-VLAN or S-VLAN + * When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. + */ +#define ENET_VLAN_TAG_INC_RPL_CSVL_MASK (0x80000UL) +#define ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT (19U) +#define ENET_VLAN_TAG_INC_RPL_CSVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) +#define ENET_VLAN_TAG_INC_RPL_CSVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) >> ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) + +/* + * VLP (RW) + * + * VLAN Priority Control + * When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. + */ +#define ENET_VLAN_TAG_INC_RPL_VLP_MASK (0x40000UL) +#define ENET_VLAN_TAG_INC_RPL_VLP_SHIFT (18U) +#define ENET_VLAN_TAG_INC_RPL_VLP_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) +#define ENET_VLAN_TAG_INC_RPL_VLP_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) >> ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) + +/* + * VLC (RW) + * + * VLAN Tag Control in Transmit Frames + * - 2’b00: No VLAN tag deletion, insertion, or replacement + * - 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. + * - 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. + * - 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. + */ +#define ENET_VLAN_TAG_INC_RPL_VLC_MASK (0x30000UL) +#define ENET_VLAN_TAG_INC_RPL_VLC_SHIFT (16U) +#define ENET_VLAN_TAG_INC_RPL_VLC_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) +#define ENET_VLAN_TAG_INC_RPL_VLC_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) >> ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) + +/* + * VLT (RW) + * + * VLAN Tag for Transmit Frames + * This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. + */ +#define ENET_VLAN_TAG_INC_RPL_VLT_MASK (0xFFFFU) +#define ENET_VLAN_TAG_INC_RPL_VLT_SHIFT (0U) +#define ENET_VLAN_TAG_INC_RPL_VLT_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) +#define ENET_VLAN_TAG_INC_RPL_VLT_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) >> ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) + +/* Bitfield definition for register: VLAN_HASH */ +/* + * VLHT (RW) + * + * VLAN Hash Table + * This field contains the 16-bit VLAN Hash Table. + */ +#define ENET_VLAN_HASH_VLHT_MASK (0xFFFFU) +#define ENET_VLAN_HASH_VLHT_SHIFT (0U) +#define ENET_VLAN_HASH_VLHT_SET(x) (((uint32_t)(x) << ENET_VLAN_HASH_VLHT_SHIFT) & ENET_VLAN_HASH_VLHT_MASK) +#define ENET_VLAN_HASH_VLHT_GET(x) (((uint32_t)(x) & ENET_VLAN_HASH_VLHT_MASK) >> ENET_VLAN_HASH_VLHT_SHIFT) + +/* Bitfield definition for register: TS_CTRL */ +/* + * ATSEN3 (RW) + * + * Auxiliary Snapshot 3 Enable + * This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. + */ +#define ENET_TS_CTRL_ATSEN3_MASK (0x10000000UL) +#define ENET_TS_CTRL_ATSEN3_SHIFT (28U) +#define ENET_TS_CTRL_ATSEN3_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN3_SHIFT) & ENET_TS_CTRL_ATSEN3_MASK) +#define ENET_TS_CTRL_ATSEN3_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN3_MASK) >> ENET_TS_CTRL_ATSEN3_SHIFT) + +/* + * ATSEN2 (RW) + * + * Auxiliary Snapshot 2 Enable + * This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. + */ +#define ENET_TS_CTRL_ATSEN2_MASK (0x8000000UL) +#define ENET_TS_CTRL_ATSEN2_SHIFT (27U) +#define ENET_TS_CTRL_ATSEN2_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN2_SHIFT) & ENET_TS_CTRL_ATSEN2_MASK) +#define ENET_TS_CTRL_ATSEN2_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN2_MASK) >> ENET_TS_CTRL_ATSEN2_SHIFT) + +/* + * ATSEN1 (RW) + * + * Auxiliary Snapshot 1 Enable + * This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. + */ +#define ENET_TS_CTRL_ATSEN1_MASK (0x4000000UL) +#define ENET_TS_CTRL_ATSEN1_SHIFT (26U) +#define ENET_TS_CTRL_ATSEN1_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN1_SHIFT) & ENET_TS_CTRL_ATSEN1_MASK) +#define ENET_TS_CTRL_ATSEN1_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN1_MASK) >> ENET_TS_CTRL_ATSEN1_SHIFT) + +/* + * ATSEN0 (RW) + * + * Auxiliary Snapshot 0 Enable + * This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. + */ +#define ENET_TS_CTRL_ATSEN0_MASK (0x2000000UL) +#define ENET_TS_CTRL_ATSEN0_SHIFT (25U) +#define ENET_TS_CTRL_ATSEN0_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN0_SHIFT) & ENET_TS_CTRL_ATSEN0_MASK) +#define ENET_TS_CTRL_ATSEN0_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN0_MASK) >> ENET_TS_CTRL_ATSEN0_SHIFT) + +/* + * ATSFC (RW) + * + * Auxiliary Snapshot FIFO Clear + * When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. + */ +#define ENET_TS_CTRL_ATSFC_MASK (0x1000000UL) +#define ENET_TS_CTRL_ATSFC_SHIFT (24U) +#define ENET_TS_CTRL_ATSFC_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSFC_SHIFT) & ENET_TS_CTRL_ATSFC_MASK) +#define ENET_TS_CTRL_ATSFC_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSFC_MASK) >> ENET_TS_CTRL_ATSFC_SHIFT) + +/* + * TSENMACADDR (RW) + * + * Enable MAC address for PTP Frame Filtering + * When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. + */ +#define ENET_TS_CTRL_TSENMACADDR_MASK (0x40000UL) +#define ENET_TS_CTRL_TSENMACADDR_SHIFT (18U) +#define ENET_TS_CTRL_TSENMACADDR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENMACADDR_SHIFT) & ENET_TS_CTRL_TSENMACADDR_MASK) +#define ENET_TS_CTRL_TSENMACADDR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENMACADDR_MASK) >> ENET_TS_CTRL_TSENMACADDR_SHIFT) + +/* + * SNAPTYPSEL (RW) + * + * Select PTP packets for Taking Snapshots + * These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. + */ +#define ENET_TS_CTRL_SNAPTYPSEL_MASK (0x30000UL) +#define ENET_TS_CTRL_SNAPTYPSEL_SHIFT (16U) +#define ENET_TS_CTRL_SNAPTYPSEL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_SNAPTYPSEL_SHIFT) & ENET_TS_CTRL_SNAPTYPSEL_MASK) +#define ENET_TS_CTRL_SNAPTYPSEL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_SNAPTYPSEL_MASK) >> ENET_TS_CTRL_SNAPTYPSEL_SHIFT) + +/* + * TSMSTRENA (RW) + * + * Enable Snapshot for Messages Relevant to Master + * When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. + */ +#define ENET_TS_CTRL_TSMSTRENA_MASK (0x8000U) +#define ENET_TS_CTRL_TSMSTRENA_SHIFT (15U) +#define ENET_TS_CTRL_TSMSTRENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSMSTRENA_SHIFT) & ENET_TS_CTRL_TSMSTRENA_MASK) +#define ENET_TS_CTRL_TSMSTRENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSMSTRENA_MASK) >> ENET_TS_CTRL_TSMSTRENA_SHIFT) + +/* + * TSEVNTENA (RW) + * + * Enable Timestamp Snapshot for Event Messages + * When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. + */ +#define ENET_TS_CTRL_TSEVNTENA_MASK (0x4000U) +#define ENET_TS_CTRL_TSEVNTENA_SHIFT (14U) +#define ENET_TS_CTRL_TSEVNTENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSEVNTENA_SHIFT) & ENET_TS_CTRL_TSEVNTENA_MASK) +#define ENET_TS_CTRL_TSEVNTENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSEVNTENA_MASK) >> ENET_TS_CTRL_TSEVNTENA_SHIFT) + +/* + * TSIPV4ENA (RW) + * + * Enable Processing of PTP Frames Sent over IPv4-UDP + * When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. + */ +#define ENET_TS_CTRL_TSIPV4ENA_MASK (0x2000U) +#define ENET_TS_CTRL_TSIPV4ENA_SHIFT (13U) +#define ENET_TS_CTRL_TSIPV4ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV4ENA_SHIFT) & ENET_TS_CTRL_TSIPV4ENA_MASK) +#define ENET_TS_CTRL_TSIPV4ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV4ENA_MASK) >> ENET_TS_CTRL_TSIPV4ENA_SHIFT) + +/* + * TSIPV6ENA (RW) + * + * Enable Processing of PTP Frames Sent over IPv6-UDP + * When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. + */ +#define ENET_TS_CTRL_TSIPV6ENA_MASK (0x1000U) +#define ENET_TS_CTRL_TSIPV6ENA_SHIFT (12U) +#define ENET_TS_CTRL_TSIPV6ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV6ENA_SHIFT) & ENET_TS_CTRL_TSIPV6ENA_MASK) +#define ENET_TS_CTRL_TSIPV6ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV6ENA_MASK) >> ENET_TS_CTRL_TSIPV6ENA_SHIFT) + +/* + * TSIPENA (RW) + * + * Enable Processing of PTP over Ethernet Frames + * When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets + */ +#define ENET_TS_CTRL_TSIPENA_MASK (0x800U) +#define ENET_TS_CTRL_TSIPENA_SHIFT (11U) +#define ENET_TS_CTRL_TSIPENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPENA_SHIFT) & ENET_TS_CTRL_TSIPENA_MASK) +#define ENET_TS_CTRL_TSIPENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPENA_MASK) >> ENET_TS_CTRL_TSIPENA_SHIFT) + +/* + * TSVER2ENA (RW) + * + * Enable PTP packet Processing for Version 2 Format + * When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. + */ +#define ENET_TS_CTRL_TSVER2ENA_MASK (0x400U) +#define ENET_TS_CTRL_TSVER2ENA_SHIFT (10U) +#define ENET_TS_CTRL_TSVER2ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSVER2ENA_SHIFT) & ENET_TS_CTRL_TSVER2ENA_MASK) +#define ENET_TS_CTRL_TSVER2ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSVER2ENA_MASK) >> ENET_TS_CTRL_TSVER2ENA_SHIFT) + +/* + * TSCTRLSSR (RW) + * + * Timestamp Digital or Binary Rollover Control + * When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. + */ +#define ENET_TS_CTRL_TSCTRLSSR_MASK (0x200U) +#define ENET_TS_CTRL_TSCTRLSSR_SHIFT (9U) +#define ENET_TS_CTRL_TSCTRLSSR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCTRLSSR_SHIFT) & ENET_TS_CTRL_TSCTRLSSR_MASK) +#define ENET_TS_CTRL_TSCTRLSSR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCTRLSSR_MASK) >> ENET_TS_CTRL_TSCTRLSSR_SHIFT) + +/* + * TSENALL (RW) + * + * Enable Timestamp for All Frames + * When set, the timestamp snapshot is enabled for all frames received by the MAC. + */ +#define ENET_TS_CTRL_TSENALL_MASK (0x100U) +#define ENET_TS_CTRL_TSENALL_SHIFT (8U) +#define ENET_TS_CTRL_TSENALL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENALL_SHIFT) & ENET_TS_CTRL_TSENALL_MASK) +#define ENET_TS_CTRL_TSENALL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENALL_MASK) >> ENET_TS_CTRL_TSENALL_SHIFT) + +/* + * TSADDREG (RW) + * + * Addend Reg Update + * When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. + */ +#define ENET_TS_CTRL_TSADDREG_MASK (0x20U) +#define ENET_TS_CTRL_TSADDREG_SHIFT (5U) +#define ENET_TS_CTRL_TSADDREG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSADDREG_SHIFT) & ENET_TS_CTRL_TSADDREG_MASK) +#define ENET_TS_CTRL_TSADDREG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSADDREG_MASK) >> ENET_TS_CTRL_TSADDREG_SHIFT) + +/* + * TSTRIG (RW) + * + * Timestamp Interrupt Trigger Enable + * When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. + */ +#define ENET_TS_CTRL_TSTRIG_MASK (0x10U) +#define ENET_TS_CTRL_TSTRIG_SHIFT (4U) +#define ENET_TS_CTRL_TSTRIG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSTRIG_SHIFT) & ENET_TS_CTRL_TSTRIG_MASK) +#define ENET_TS_CTRL_TSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSTRIG_MASK) >> ENET_TS_CTRL_TSTRIG_SHIFT) + +/* + * TSUPDT (RW) + * + * Timestamp Update + * When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. + */ +#define ENET_TS_CTRL_TSUPDT_MASK (0x8U) +#define ENET_TS_CTRL_TSUPDT_SHIFT (3U) +#define ENET_TS_CTRL_TSUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSUPDT_SHIFT) & ENET_TS_CTRL_TSUPDT_MASK) +#define ENET_TS_CTRL_TSUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSUPDT_MASK) >> ENET_TS_CTRL_TSUPDT_SHIFT) + +/* + * TSINIT (RW) + * + * Timestamp Initialize + * When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. + */ +#define ENET_TS_CTRL_TSINIT_MASK (0x4U) +#define ENET_TS_CTRL_TSINIT_SHIFT (2U) +#define ENET_TS_CTRL_TSINIT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSINIT_SHIFT) & ENET_TS_CTRL_TSINIT_MASK) +#define ENET_TS_CTRL_TSINIT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSINIT_MASK) >> ENET_TS_CTRL_TSINIT_SHIFT) + +/* + * TSCFUPDT (RW) + * + * Timestamp Fine or Coarse Update + * When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. + */ +#define ENET_TS_CTRL_TSCFUPDT_MASK (0x2U) +#define ENET_TS_CTRL_TSCFUPDT_SHIFT (1U) +#define ENET_TS_CTRL_TSCFUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCFUPDT_SHIFT) & ENET_TS_CTRL_TSCFUPDT_MASK) +#define ENET_TS_CTRL_TSCFUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCFUPDT_MASK) >> ENET_TS_CTRL_TSCFUPDT_SHIFT) + +/* + * TSENA (RW) + * + * Timestamp Enable + * When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. + */ +#define ENET_TS_CTRL_TSENA_MASK (0x1U) +#define ENET_TS_CTRL_TSENA_SHIFT (0U) +#define ENET_TS_CTRL_TSENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENA_SHIFT) & ENET_TS_CTRL_TSENA_MASK) +#define ENET_TS_CTRL_TSENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENA_MASK) >> ENET_TS_CTRL_TSENA_SHIFT) + +/* Bitfield definition for register: SUB_SEC_INCR */ +/* + * SSINC (RW) + * + * Sub-second Increment Value + * The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. + */ +#define ENET_SUB_SEC_INCR_SSINC_MASK (0xFFU) +#define ENET_SUB_SEC_INCR_SSINC_SHIFT (0U) +#define ENET_SUB_SEC_INCR_SSINC_SET(x) (((uint32_t)(x) << ENET_SUB_SEC_INCR_SSINC_SHIFT) & ENET_SUB_SEC_INCR_SSINC_MASK) +#define ENET_SUB_SEC_INCR_SSINC_GET(x) (((uint32_t)(x) & ENET_SUB_SEC_INCR_SSINC_MASK) >> ENET_SUB_SEC_INCR_SSINC_SHIFT) + +/* Bitfield definition for register: SYST_SEC */ +/* + * TSS (RW) + * + * Timestamp Second + * The value in this field indicates the current value in seconds of the System Time maintained by the MAC. + */ +#define ENET_SYST_SEC_TSS_MASK (0xFFFFFFFFUL) +#define ENET_SYST_SEC_TSS_SHIFT (0U) +#define ENET_SYST_SEC_TSS_SET(x) (((uint32_t)(x) << ENET_SYST_SEC_TSS_SHIFT) & ENET_SYST_SEC_TSS_MASK) +#define ENET_SYST_SEC_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_TSS_MASK) >> ENET_SYST_SEC_TSS_SHIFT) + +/* Bitfield definition for register: SYST_NSEC */ +/* + * TSSS (RW) + * + * Timestamp Sub Seconds + * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. + */ +#define ENET_SYST_NSEC_TSSS_MASK (0x7FFFFFFFUL) +#define ENET_SYST_NSEC_TSSS_SHIFT (0U) +#define ENET_SYST_NSEC_TSSS_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_TSSS_SHIFT) & ENET_SYST_NSEC_TSSS_MASK) +#define ENET_SYST_NSEC_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_TSSS_MASK) >> ENET_SYST_NSEC_TSSS_SHIFT) + +/* Bitfield definition for register: SYST_SEC_UPD */ +/* + * TSS (RW) + * + * Timestamp Second + * The value in this field indicates the time in seconds to be initialized or added to the system time. + */ +#define ENET_SYST_SEC_UPD_TSS_MASK (0xFFFFFFFFUL) +#define ENET_SYST_SEC_UPD_TSS_SHIFT (0U) +#define ENET_SYST_SEC_UPD_TSS_SET(x) (((uint32_t)(x) << ENET_SYST_SEC_UPD_TSS_SHIFT) & ENET_SYST_SEC_UPD_TSS_MASK) +#define ENET_SYST_SEC_UPD_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_UPD_TSS_MASK) >> ENET_SYST_SEC_UPD_TSS_SHIFT) + +/* Bitfield definition for register: SYST_NSEC_UPD */ +/* + * ADDSUB (RW) + * + * Add or Subtract Time + * When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. + */ +#define ENET_SYST_NSEC_UPD_ADDSUB_MASK (0x80000000UL) +#define ENET_SYST_NSEC_UPD_ADDSUB_SHIFT (31U) +#define ENET_SYST_NSEC_UPD_ADDSUB_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) +#define ENET_SYST_NSEC_UPD_ADDSUB_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) >> ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) + +/* + * TSSS (RW) + * + * Timestamp Sub Seconds + * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. + */ +#define ENET_SYST_NSEC_UPD_TSSS_MASK (0x7FFFFFFFUL) +#define ENET_SYST_NSEC_UPD_TSSS_SHIFT (0U) +#define ENET_SYST_NSEC_UPD_TSSS_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_TSSS_SHIFT) & ENET_SYST_NSEC_UPD_TSSS_MASK) +#define ENET_SYST_NSEC_UPD_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_TSSS_MASK) >> ENET_SYST_NSEC_UPD_TSSS_SHIFT) + +/* Bitfield definition for register: TS_ADDEND */ +/* + * TSAR (RW) + * + * Timestamp Addend Register + * This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. + */ +#define ENET_TS_ADDEND_TSAR_MASK (0xFFFFFFFFUL) +#define ENET_TS_ADDEND_TSAR_SHIFT (0U) +#define ENET_TS_ADDEND_TSAR_SET(x) (((uint32_t)(x) << ENET_TS_ADDEND_TSAR_SHIFT) & ENET_TS_ADDEND_TSAR_MASK) +#define ENET_TS_ADDEND_TSAR_GET(x) (((uint32_t)(x) & ENET_TS_ADDEND_TSAR_MASK) >> ENET_TS_ADDEND_TSAR_SHIFT) + +/* Bitfield definition for register: TGTTM_SEC */ +/* + * TSTR (RW) + * + * Target Time Seconds Register + * This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + */ +#define ENET_TGTTM_SEC_TSTR_MASK (0xFFFFFFFFUL) +#define ENET_TGTTM_SEC_TSTR_SHIFT (0U) +#define ENET_TGTTM_SEC_TSTR_SET(x) (((uint32_t)(x) << ENET_TGTTM_SEC_TSTR_SHIFT) & ENET_TGTTM_SEC_TSTR_MASK) +#define ENET_TGTTM_SEC_TSTR_GET(x) (((uint32_t)(x) & ENET_TGTTM_SEC_TSTR_MASK) >> ENET_TGTTM_SEC_TSTR_SHIFT) + +/* Bitfield definition for register: TGTTM_NSEC */ +/* + * TRGTBUSY (RW) + * + * Target Time Register Busy + * The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. + */ +#define ENET_TGTTM_NSEC_TRGTBUSY_MASK (0x80000000UL) +#define ENET_TGTTM_NSEC_TRGTBUSY_SHIFT (31U) +#define ENET_TGTTM_NSEC_TRGTBUSY_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) +#define ENET_TGTTM_NSEC_TRGTBUSY_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) >> ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) + +/* + * TTSLO (RW) + * + * Target Timestamp Low Register + * This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + */ +#define ENET_TGTTM_NSEC_TTSLO_MASK (0x7FFFFFFFUL) +#define ENET_TGTTM_NSEC_TTSLO_SHIFT (0U) +#define ENET_TGTTM_NSEC_TTSLO_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TTSLO_SHIFT) & ENET_TGTTM_NSEC_TTSLO_MASK) +#define ENET_TGTTM_NSEC_TTSLO_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TTSLO_MASK) >> ENET_TGTTM_NSEC_TTSLO_SHIFT) + +/* Bitfield definition for register: SYSTM_H_SEC */ +/* + * TSHWR (RW) + * + * Timestamp Higher Word Register + * This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. + */ +#define ENET_SYSTM_H_SEC_TSHWR_MASK (0xFFFFU) +#define ENET_SYSTM_H_SEC_TSHWR_SHIFT (0U) +#define ENET_SYSTM_H_SEC_TSHWR_SET(x) (((uint32_t)(x) << ENET_SYSTM_H_SEC_TSHWR_SHIFT) & ENET_SYSTM_H_SEC_TSHWR_MASK) +#define ENET_SYSTM_H_SEC_TSHWR_GET(x) (((uint32_t)(x) & ENET_SYSTM_H_SEC_TSHWR_MASK) >> ENET_SYSTM_H_SEC_TSHWR_SHIFT) + +/* Bitfield definition for register: TS_STATUS */ +/* + * ATSNS (RO) + * + * Number of Auxiliary Timestamp Snapshots + * This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + */ +#define ENET_TS_STATUS_ATSNS_MASK (0x3E000000UL) +#define ENET_TS_STATUS_ATSNS_SHIFT (25U) +#define ENET_TS_STATUS_ATSNS_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSNS_MASK) >> ENET_TS_STATUS_ATSNS_SHIFT) + +/* + * ATSSTM (RO) + * + * Auxiliary Timestamp Snapshot Trigger Missed + * This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + */ +#define ENET_TS_STATUS_ATSSTM_MASK (0x1000000UL) +#define ENET_TS_STATUS_ATSSTM_SHIFT (24U) +#define ENET_TS_STATUS_ATSSTM_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTM_MASK) >> ENET_TS_STATUS_ATSSTM_SHIFT) + +/* + * ATSSTN (RO) + * + * Auxiliary Timestamp Snapshot Trigger Identifier + * These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. + */ +#define ENET_TS_STATUS_ATSSTN_MASK (0xF0000UL) +#define ENET_TS_STATUS_ATSSTN_SHIFT (16U) +#define ENET_TS_STATUS_ATSSTN_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTN_MASK) >> ENET_TS_STATUS_ATSSTN_SHIFT) + +/* + * TSTRGTERR3 (RO) + * + * Timestamp Target Time Error + * This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. + */ +#define ENET_TS_STATUS_TSTRGTERR3_MASK (0x200U) +#define ENET_TS_STATUS_TSTRGTERR3_SHIFT (9U) +#define ENET_TS_STATUS_TSTRGTERR3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR3_MASK) >> ENET_TS_STATUS_TSTRGTERR3_SHIFT) + +/* + * TSTARGT3 (RO) + * + * Timestamp Target Time Reached for Target Time PPS3 + * When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). + */ +#define ENET_TS_STATUS_TSTARGT3_MASK (0x100U) +#define ENET_TS_STATUS_TSTARGT3_SHIFT (8U) +#define ENET_TS_STATUS_TSTARGT3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT3_MASK) >> ENET_TS_STATUS_TSTARGT3_SHIFT) + +/* + * TSTRGTERR2 (RO) + * + */ +#define ENET_TS_STATUS_TSTRGTERR2_MASK (0x80U) +#define ENET_TS_STATUS_TSTRGTERR2_SHIFT (7U) +#define ENET_TS_STATUS_TSTRGTERR2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR2_MASK) >> ENET_TS_STATUS_TSTRGTERR2_SHIFT) + +/* + * TSTARGT2 (RO) + * + */ +#define ENET_TS_STATUS_TSTARGT2_MASK (0x40U) +#define ENET_TS_STATUS_TSTARGT2_SHIFT (6U) +#define ENET_TS_STATUS_TSTARGT2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT2_MASK) >> ENET_TS_STATUS_TSTARGT2_SHIFT) + +/* + * TSTRGTERR1 (RO) + * + */ +#define ENET_TS_STATUS_TSTRGTERR1_MASK (0x20U) +#define ENET_TS_STATUS_TSTRGTERR1_SHIFT (5U) +#define ENET_TS_STATUS_TSTRGTERR1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR1_MASK) >> ENET_TS_STATUS_TSTRGTERR1_SHIFT) + +/* + * TSTARGT1 (RO) + * + */ +#define ENET_TS_STATUS_TSTARGT1_MASK (0x10U) +#define ENET_TS_STATUS_TSTARGT1_SHIFT (4U) +#define ENET_TS_STATUS_TSTARGT1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT1_MASK) >> ENET_TS_STATUS_TSTARGT1_SHIFT) + +/* + * TSTRGTERR (RO) + * + */ +#define ENET_TS_STATUS_TSTRGTERR_MASK (0x8U) +#define ENET_TS_STATUS_TSTRGTERR_SHIFT (3U) +#define ENET_TS_STATUS_TSTRGTERR_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR_MASK) >> ENET_TS_STATUS_TSTRGTERR_SHIFT) + +/* + * AUXTSTRIG (RO) + * + */ +#define ENET_TS_STATUS_AUXTSTRIG_MASK (0x4U) +#define ENET_TS_STATUS_AUXTSTRIG_SHIFT (2U) +#define ENET_TS_STATUS_AUXTSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_AUXTSTRIG_MASK) >> ENET_TS_STATUS_AUXTSTRIG_SHIFT) + +/* + * TSTARGT (RO) + * + */ +#define ENET_TS_STATUS_TSTARGT_MASK (0x2U) +#define ENET_TS_STATUS_TSTARGT_SHIFT (1U) +#define ENET_TS_STATUS_TSTARGT_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT_MASK) >> ENET_TS_STATUS_TSTARGT_SHIFT) + +/* + * TSSOVF (RO) + * + */ +#define ENET_TS_STATUS_TSSOVF_MASK (0x1U) +#define ENET_TS_STATUS_TSSOVF_SHIFT (0U) +#define ENET_TS_STATUS_TSSOVF_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSSOVF_MASK) >> ENET_TS_STATUS_TSSOVF_SHIFT) + +/* Bitfield definition for register: PPS_CTRL */ +/* + * TRGTMODSEL3 (RW) + * + * Target Time Register Mode for PPS3 Output + * This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. + */ +#define ENET_PPS_CTRL_TRGTMODSEL3_MASK (0x60000000UL) +#define ENET_PPS_CTRL_TRGTMODSEL3_SHIFT (29U) +#define ENET_PPS_CTRL_TRGTMODSEL3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) +#define ENET_PPS_CTRL_TRGTMODSEL3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) >> ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) + +/* + * PPSCMD3 (RW) + * + * Flexible PPS3 Output Control + * This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. + */ +#define ENET_PPS_CTRL_PPSCMD3_MASK (0x7000000UL) +#define ENET_PPS_CTRL_PPSCMD3_SHIFT (24U) +#define ENET_PPS_CTRL_PPSCMD3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD3_SHIFT) & ENET_PPS_CTRL_PPSCMD3_MASK) +#define ENET_PPS_CTRL_PPSCMD3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD3_MASK) >> ENET_PPS_CTRL_PPSCMD3_SHIFT) + +/* + * TRGTMODSEL2 (RW) + * + * Target Time Register Mode for PPS2 Output + * This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. + */ +#define ENET_PPS_CTRL_TRGTMODSEL2_MASK (0x600000UL) +#define ENET_PPS_CTRL_TRGTMODSEL2_SHIFT (21U) +#define ENET_PPS_CTRL_TRGTMODSEL2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) +#define ENET_PPS_CTRL_TRGTMODSEL2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) >> ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) + +/* + * PPSCMD2 (RW) + * + * Flexible PPS2 Output Control + * This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. + */ +#define ENET_PPS_CTRL_PPSCMD2_MASK (0x70000UL) +#define ENET_PPS_CTRL_PPSCMD2_SHIFT (16U) +#define ENET_PPS_CTRL_PPSCMD2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD2_SHIFT) & ENET_PPS_CTRL_PPSCMD2_MASK) +#define ENET_PPS_CTRL_PPSCMD2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD2_MASK) >> ENET_PPS_CTRL_PPSCMD2_SHIFT) + +/* + * TRGTMODSEL1 (RW) + * + * Target Time Register Mode for PPS1 Output + * This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. + */ +#define ENET_PPS_CTRL_TRGTMODSEL1_MASK (0x6000U) +#define ENET_PPS_CTRL_TRGTMODSEL1_SHIFT (13U) +#define ENET_PPS_CTRL_TRGTMODSEL1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) +#define ENET_PPS_CTRL_TRGTMODSEL1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) >> ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) + +/* + * PPSCMD1 (RW) + * + * Flexible PPS1 Output Control + * This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. + */ +#define ENET_PPS_CTRL_PPSCMD1_MASK (0x700U) +#define ENET_PPS_CTRL_PPSCMD1_SHIFT (8U) +#define ENET_PPS_CTRL_PPSCMD1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD1_SHIFT) & ENET_PPS_CTRL_PPSCMD1_MASK) +#define ENET_PPS_CTRL_PPSCMD1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD1_MASK) >> ENET_PPS_CTRL_PPSCMD1_SHIFT) + +/* + * TRGTMODSEL0 (RW) + * + * Target Time Register Mode for PPS0 Output + * This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: + * - 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. + * - 01: Reserved + * - 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. + * - 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. + */ +#define ENET_PPS_CTRL_TRGTMODSEL0_MASK (0x60U) +#define ENET_PPS_CTRL_TRGTMODSEL0_SHIFT (5U) +#define ENET_PPS_CTRL_TRGTMODSEL0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) +#define ENET_PPS_CTRL_TRGTMODSEL0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) >> ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) + +/* + * PPSEN0 (RW) + * + * Flexible PPS Output Mode Enable + * When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. + */ +#define ENET_PPS_CTRL_PPSEN0_MASK (0x10U) +#define ENET_PPS_CTRL_PPSEN0_SHIFT (4U) +#define ENET_PPS_CTRL_PPSEN0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSEN0_SHIFT) & ENET_PPS_CTRL_PPSEN0_MASK) +#define ENET_PPS_CTRL_PPSEN0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSEN0_MASK) >> ENET_PPS_CTRL_PPSEN0_SHIFT) + +/* + * PPSCTRL0 (RW) + * + * PPSCTRL0: PPS0 Output Frequency Control + * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: + * - 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. + * - 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. + * - 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. + * - 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... + * - 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) + */ +#define ENET_PPS_CTRL_PPSCTRL0_MASK (0xFU) +#define ENET_PPS_CTRL_PPSCTRL0_SHIFT (0U) +#define ENET_PPS_CTRL_PPSCTRL0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCTRL0_SHIFT) & ENET_PPS_CTRL_PPSCTRL0_MASK) +#define ENET_PPS_CTRL_PPSCTRL0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCTRL0_MASK) >> ENET_PPS_CTRL_PPSCTRL0_SHIFT) + +/* Bitfield definition for register: AUX_TS_NSEC */ +/* + * AUXTSLO (RW) + * + * Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. + */ +#define ENET_AUX_TS_NSEC_AUXTSLO_MASK (0x7FFFFFFFUL) +#define ENET_AUX_TS_NSEC_AUXTSLO_SHIFT (0U) +#define ENET_AUX_TS_NSEC_AUXTSLO_SET(x) (((uint32_t)(x) << ENET_AUX_TS_NSEC_AUXTSLO_SHIFT) & ENET_AUX_TS_NSEC_AUXTSLO_MASK) +#define ENET_AUX_TS_NSEC_AUXTSLO_GET(x) (((uint32_t)(x) & ENET_AUX_TS_NSEC_AUXTSLO_MASK) >> ENET_AUX_TS_NSEC_AUXTSLO_SHIFT) + +/* Bitfield definition for register: AUX_TS_SEC */ +/* + * AUXTSHI (RW) + * + * Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. + */ +#define ENET_AUX_TS_SEC_AUXTSHI_MASK (0xFFFFFFFFUL) +#define ENET_AUX_TS_SEC_AUXTSHI_SHIFT (0U) +#define ENET_AUX_TS_SEC_AUXTSHI_SET(x) (((uint32_t)(x) << ENET_AUX_TS_SEC_AUXTSHI_SHIFT) & ENET_AUX_TS_SEC_AUXTSHI_MASK) +#define ENET_AUX_TS_SEC_AUXTSHI_GET(x) (((uint32_t)(x) & ENET_AUX_TS_SEC_AUXTSHI_MASK) >> ENET_AUX_TS_SEC_AUXTSHI_SHIFT) + +/* Bitfield definition for register: PPS0_INTERVAL */ +/* + * PPSINT (RW) + * + * PPS0 Output Signal Interval + * These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + */ +#define ENET_PPS0_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) +#define ENET_PPS0_INTERVAL_PPSINT_SHIFT (0U) +#define ENET_PPS0_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS0_INTERVAL_PPSINT_SHIFT) & ENET_PPS0_INTERVAL_PPSINT_MASK) +#define ENET_PPS0_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS0_INTERVAL_PPSINT_MASK) >> ENET_PPS0_INTERVAL_PPSINT_SHIFT) + +/* Bitfield definition for register: PPS0_WIDTH */ +/* + * PPSWIDTH (RW) + * + * PPS0 Output Signal Width + * These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + */ +#define ENET_PPS0_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) +#define ENET_PPS0_WIDTH_PPSWIDTH_SHIFT (0U) +#define ENET_PPS0_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) +#define ENET_PPS0_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) >> ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) + +/* Bitfield definition for register of struct array PPS: TGTTM_SEC */ +/* + * TSTRH1 (RW) + * + * PPS1 Target Time Seconds Register + * This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + */ +#define ENET_PPS_TGTTM_SEC_TSTRH1_MASK (0xFFFFFFFFUL) +#define ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT (0U) +#define ENET_PPS_TGTTM_SEC_TSTRH1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) +#define ENET_PPS_TGTTM_SEC_TSTRH1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) >> ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) + +/* Bitfield definition for register of struct array PPS: TGTTM_NSEC */ +/* + * TRGTBUSY1 (RW) + * + * PPS1 Target Time Register Busy + * The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + */ +#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK (0x80000000UL) +#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT (31U) +#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) +#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) >> ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) + +/* + * TTSL1 (RW) + * + * Target Time Low for PPS1 Register + * This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + */ +#define ENET_PPS_TGTTM_NSEC_TTSL1_MASK (0x7FFFFFFFUL) +#define ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT (0U) +#define ENET_PPS_TGTTM_NSEC_TTSL1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) +#define ENET_PPS_TGTTM_NSEC_TTSL1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) >> ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) + +/* Bitfield definition for register of struct array PPS: INTERVAL */ +/* + * PPSINT (RW) + * + * PPS1 Output Signal Interval + * These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + */ +#define ENET_PPS_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) +#define ENET_PPS_INTERVAL_PPSINT_SHIFT (0U) +#define ENET_PPS_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS_INTERVAL_PPSINT_SHIFT) & ENET_PPS_INTERVAL_PPSINT_MASK) +#define ENET_PPS_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS_INTERVAL_PPSINT_MASK) >> ENET_PPS_INTERVAL_PPSINT_SHIFT) + +/* Bitfield definition for register of struct array PPS: WIDTH */ +/* + * PPSWIDTH (RW) + * + * PPS1 Output Signal Width + * These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + */ +#define ENET_PPS_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) +#define ENET_PPS_WIDTH_PPSWIDTH_SHIFT (0U) +#define ENET_PPS_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS_WIDTH_PPSWIDTH_MASK) +#define ENET_PPS_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS_WIDTH_PPSWIDTH_MASK) >> ENET_PPS_WIDTH_PPSWIDTH_SHIFT) + +/* Bitfield definition for register: DMA_BUS_MODE */ +/* + * RIB (RW) + * + * Rebuild INCRx Burst + * When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. + */ +#define ENET_DMA_BUS_MODE_RIB_MASK (0x80000000UL) +#define ENET_DMA_BUS_MODE_RIB_SHIFT (31U) +#define ENET_DMA_BUS_MODE_RIB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RIB_SHIFT) & ENET_DMA_BUS_MODE_RIB_MASK) +#define ENET_DMA_BUS_MODE_RIB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RIB_MASK) >> ENET_DMA_BUS_MODE_RIB_SHIFT) + +/* + * PRWG (RW) + * + * Channel Priority + * Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. + * - 00: The priority weight is 1. + * - 01: The priority weight is 2. + * - 10: The priority weight is 3. + * - 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). + */ +#define ENET_DMA_BUS_MODE_PRWG_MASK (0x30000000UL) +#define ENET_DMA_BUS_MODE_PRWG_SHIFT (28U) +#define ENET_DMA_BUS_MODE_PRWG_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PRWG_SHIFT) & ENET_DMA_BUS_MODE_PRWG_MASK) +#define ENET_DMA_BUS_MODE_PRWG_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PRWG_MASK) >> ENET_DMA_BUS_MODE_PRWG_SHIFT) + +/* + * TXPR (RW) + * + * Transmit Priority + * When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). + */ +#define ENET_DMA_BUS_MODE_TXPR_MASK (0x8000000UL) +#define ENET_DMA_BUS_MODE_TXPR_SHIFT (27U) +#define ENET_DMA_BUS_MODE_TXPR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_TXPR_SHIFT) & ENET_DMA_BUS_MODE_TXPR_MASK) +#define ENET_DMA_BUS_MODE_TXPR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_TXPR_MASK) >> ENET_DMA_BUS_MODE_TXPR_SHIFT) + +/* + * MB (RW) + * + * Mixed Burst + * When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. + */ +#define ENET_DMA_BUS_MODE_MB_MASK (0x4000000UL) +#define ENET_DMA_BUS_MODE_MB_SHIFT (26U) +#define ENET_DMA_BUS_MODE_MB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_MB_SHIFT) & ENET_DMA_BUS_MODE_MB_MASK) +#define ENET_DMA_BUS_MODE_MB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_MB_MASK) >> ENET_DMA_BUS_MODE_MB_SHIFT) + +/* + * AAL (RW) + * + * Address-Aligned Beats + * When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. + */ +#define ENET_DMA_BUS_MODE_AAL_MASK (0x2000000UL) +#define ENET_DMA_BUS_MODE_AAL_SHIFT (25U) +#define ENET_DMA_BUS_MODE_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_AAL_SHIFT) & ENET_DMA_BUS_MODE_AAL_MASK) +#define ENET_DMA_BUS_MODE_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_AAL_MASK) >> ENET_DMA_BUS_MODE_AAL_SHIFT) + +/* + * PBLX8 (RW) + * + * PBLx8 Mode + * When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. + */ +#define ENET_DMA_BUS_MODE_PBLX8_MASK (0x1000000UL) +#define ENET_DMA_BUS_MODE_PBLX8_SHIFT (24U) +#define ENET_DMA_BUS_MODE_PBLX8_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBLX8_SHIFT) & ENET_DMA_BUS_MODE_PBLX8_MASK) +#define ENET_DMA_BUS_MODE_PBLX8_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBLX8_MASK) >> ENET_DMA_BUS_MODE_PBLX8_SHIFT) + +/* + * USP (RW) + * + * Use Separate PBL + * When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. + */ +#define ENET_DMA_BUS_MODE_USP_MASK (0x800000UL) +#define ENET_DMA_BUS_MODE_USP_SHIFT (23U) +#define ENET_DMA_BUS_MODE_USP_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_USP_SHIFT) & ENET_DMA_BUS_MODE_USP_MASK) +#define ENET_DMA_BUS_MODE_USP_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_USP_MASK) >> ENET_DMA_BUS_MODE_USP_SHIFT) + +/* + * RPBL (RW) + * + * Rx DMA PBL + * This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. + */ +#define ENET_DMA_BUS_MODE_RPBL_MASK (0x7E0000UL) +#define ENET_DMA_BUS_MODE_RPBL_SHIFT (17U) +#define ENET_DMA_BUS_MODE_RPBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RPBL_SHIFT) & ENET_DMA_BUS_MODE_RPBL_MASK) +#define ENET_DMA_BUS_MODE_RPBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RPBL_MASK) >> ENET_DMA_BUS_MODE_RPBL_SHIFT) + +/* + * FB (RW) + * + * Fixed Burst + * This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. + */ +#define ENET_DMA_BUS_MODE_FB_MASK (0x10000UL) +#define ENET_DMA_BUS_MODE_FB_SHIFT (16U) +#define ENET_DMA_BUS_MODE_FB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_FB_SHIFT) & ENET_DMA_BUS_MODE_FB_MASK) +#define ENET_DMA_BUS_MODE_FB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_FB_MASK) >> ENET_DMA_BUS_MODE_FB_SHIFT) + +/* + * PR (RW) + * + * Priority Ratio + * These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. + * - 00: The Priority Ratio is 1:1. + * - 01: The Priority Ratio is 2:1. + * - 10: The Priority Ratio is 3:1. + * - 11: The Priority Ratio is 4:1. + */ +#define ENET_DMA_BUS_MODE_PR_MASK (0xC000U) +#define ENET_DMA_BUS_MODE_PR_SHIFT (14U) +#define ENET_DMA_BUS_MODE_PR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PR_SHIFT) & ENET_DMA_BUS_MODE_PR_MASK) +#define ENET_DMA_BUS_MODE_PR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PR_MASK) >> ENET_DMA_BUS_MODE_PR_SHIFT) + +/* + * PBL (RW) + * + * Programmable Burst Length + * These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. + */ +#define ENET_DMA_BUS_MODE_PBL_MASK (0x3F00U) +#define ENET_DMA_BUS_MODE_PBL_SHIFT (8U) +#define ENET_DMA_BUS_MODE_PBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBL_SHIFT) & ENET_DMA_BUS_MODE_PBL_MASK) +#define ENET_DMA_BUS_MODE_PBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBL_MASK) >> ENET_DMA_BUS_MODE_PBL_SHIFT) + +/* + * ATDS (RW) + * + * Alternate Descriptor Size + * When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). + */ +#define ENET_DMA_BUS_MODE_ATDS_MASK (0x80U) +#define ENET_DMA_BUS_MODE_ATDS_SHIFT (7U) +#define ENET_DMA_BUS_MODE_ATDS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_ATDS_SHIFT) & ENET_DMA_BUS_MODE_ATDS_MASK) +#define ENET_DMA_BUS_MODE_ATDS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_ATDS_MASK) >> ENET_DMA_BUS_MODE_ATDS_SHIFT) + +/* + * DSL (RW) + * + * Descriptor Skip Length + * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. + */ +#define ENET_DMA_BUS_MODE_DSL_MASK (0x7CU) +#define ENET_DMA_BUS_MODE_DSL_SHIFT (2U) +#define ENET_DMA_BUS_MODE_DSL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DSL_SHIFT) & ENET_DMA_BUS_MODE_DSL_MASK) +#define ENET_DMA_BUS_MODE_DSL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DSL_MASK) >> ENET_DMA_BUS_MODE_DSL_SHIFT) + +/* + * DA (RW) + * + * DMA Arbitration Scheme + * This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. + * - 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). + * - 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. + */ +#define ENET_DMA_BUS_MODE_DA_MASK (0x2U) +#define ENET_DMA_BUS_MODE_DA_SHIFT (1U) +#define ENET_DMA_BUS_MODE_DA_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DA_SHIFT) & ENET_DMA_BUS_MODE_DA_MASK) +#define ENET_DMA_BUS_MODE_DA_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DA_MASK) >> ENET_DMA_BUS_MODE_DA_SHIFT) + +/* + * SWR (RW) + * + * Software Reset + * When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. + */ +#define ENET_DMA_BUS_MODE_SWR_MASK (0x1U) +#define ENET_DMA_BUS_MODE_SWR_SHIFT (0U) +#define ENET_DMA_BUS_MODE_SWR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_SWR_SHIFT) & ENET_DMA_BUS_MODE_SWR_MASK) +#define ENET_DMA_BUS_MODE_SWR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_SWR_MASK) >> ENET_DMA_BUS_MODE_SWR_SHIFT) + +/* Bitfield definition for register: DMA_TX_POLL_DEMAND */ +/* + * TPD (RW) + * + * Transmit Poll Demand + * When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. + */ +#define ENET_DMA_TX_POLL_DEMAND_TPD_MASK (0xFFFFFFFFUL) +#define ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT (0U) +#define ENET_DMA_TX_POLL_DEMAND_TPD_SET(x) (((uint32_t)(x) << ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) +#define ENET_DMA_TX_POLL_DEMAND_TPD_GET(x) (((uint32_t)(x) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) >> ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) + +/* Bitfield definition for register: DMA_RX_POLL_DEMAND */ +/* + * RPD (RW) + * + * Receive Poll Demand + * When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. + */ +#define ENET_DMA_RX_POLL_DEMAND_RPD_MASK (0xFFFFFFFFUL) +#define ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT (0U) +#define ENET_DMA_RX_POLL_DEMAND_RPD_SET(x) (((uint32_t)(x) << ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) +#define ENET_DMA_RX_POLL_DEMAND_RPD_GET(x) (((uint32_t)(x) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) >> ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) + +/* Bitfield definition for register: DMA_RX_DESC_LIST_ADDR */ +/* + * RDESLA (RW) + * + * Start of Receive List + * This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + */ +#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFFFUL) +#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT (0U) +#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) +#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) >> ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) + +/* Bitfield definition for register: DMA_TX_DESC_LIST_ADDR */ +/* + * TDESLA (RW) + * + * Start of Transmit List + * This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + */ +#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFFFUL) +#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT (0U) +#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) +#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) >> ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) + +/* Bitfield definition for register: DMA_STATUS */ +/* + * GLPII (RW) + * + * GLPII: GMAC LPI Interrupt (for Channel 0) + * This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. + */ +#define ENET_DMA_STATUS_GLPII_MASK (0x40000000UL) +#define ENET_DMA_STATUS_GLPII_SHIFT (30U) +#define ENET_DMA_STATUS_GLPII_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLPII_SHIFT) & ENET_DMA_STATUS_GLPII_MASK) +#define ENET_DMA_STATUS_GLPII_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLPII_MASK) >> ENET_DMA_STATUS_GLPII_SHIFT) + +/* + * TTI (RW) + * + * Timestamp Trigger Interrupt + * This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. + */ +#define ENET_DMA_STATUS_TTI_MASK (0x20000000UL) +#define ENET_DMA_STATUS_TTI_SHIFT (29U) +#define ENET_DMA_STATUS_TTI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TTI_SHIFT) & ENET_DMA_STATUS_TTI_MASK) +#define ENET_DMA_STATUS_TTI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TTI_MASK) >> ENET_DMA_STATUS_TTI_SHIFT) + +/* + * GPI (RW) + * + * GMAC PMT Interrupt + * This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. + */ +#define ENET_DMA_STATUS_GPI_MASK (0x10000000UL) +#define ENET_DMA_STATUS_GPI_SHIFT (28U) +#define ENET_DMA_STATUS_GPI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GPI_SHIFT) & ENET_DMA_STATUS_GPI_MASK) +#define ENET_DMA_STATUS_GPI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GPI_MASK) >> ENET_DMA_STATUS_GPI_SHIFT) + +/* + * GMI (RW) + * + * GMAC MMC Interrupt + * This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. + */ +#define ENET_DMA_STATUS_GMI_MASK (0x8000000UL) +#define ENET_DMA_STATUS_GMI_SHIFT (27U) +#define ENET_DMA_STATUS_GMI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GMI_SHIFT) & ENET_DMA_STATUS_GMI_MASK) +#define ENET_DMA_STATUS_GMI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GMI_MASK) >> ENET_DMA_STATUS_GMI_SHIFT) + +/* + * GLI (RW) + * + * GMAC Line Interface Interrupt + * When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. + */ +#define ENET_DMA_STATUS_GLI_MASK (0x4000000UL) +#define ENET_DMA_STATUS_GLI_SHIFT (26U) +#define ENET_DMA_STATUS_GLI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLI_SHIFT) & ENET_DMA_STATUS_GLI_MASK) +#define ENET_DMA_STATUS_GLI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLI_MASK) >> ENET_DMA_STATUS_GLI_SHIFT) + +/* + * EB (RW) + * + * Error Bits + * This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. + * - 0 0 0: Error during Rx DMA Write Data Transfer + * - 0 1 1: Error during Tx DMA Read Data Transfer + * - 1 0 0: Error during Rx DMA Descriptor Write Access + * - 1 0 1: Error during Tx DMA Descriptor Write Access + * - 1 1 0: Error during Rx DMA Descriptor Read Access + * - 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. + */ +#define ENET_DMA_STATUS_EB_MASK (0x3800000UL) +#define ENET_DMA_STATUS_EB_SHIFT (23U) +#define ENET_DMA_STATUS_EB_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_EB_SHIFT) & ENET_DMA_STATUS_EB_MASK) +#define ENET_DMA_STATUS_EB_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_EB_MASK) >> ENET_DMA_STATUS_EB_SHIFT) + +/* + * TS (RW) + * + * Transmit Process State + * This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. + * - 3’b000: Stopped; Reset or Stop Transmit Command issued + * - 3’b001: Running; Fetching Transmit Transfer Descriptor + * - 3’b010: Running; Waiting for status + * - 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) + * - 3’b100: TIME_STAMP write state + * - 3’b101: Reserved for future use + * - 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow + * - 3’b111: Running; Closing Transmit Descriptor + */ +#define ENET_DMA_STATUS_TS_MASK (0x700000UL) +#define ENET_DMA_STATUS_TS_SHIFT (20U) +#define ENET_DMA_STATUS_TS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TS_SHIFT) & ENET_DMA_STATUS_TS_MASK) +#define ENET_DMA_STATUS_TS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TS_MASK) >> ENET_DMA_STATUS_TS_SHIFT) + +/* + * RS (RW) + * + * Receive Process State + * This field indicates the Receive DMA FSM state. This field does not generate an interrupt. + * - 3’b000: Stopped: Reset or Stop Receive Command issued + * - 3’b001: Running: Fetching Receive Transfer Descriptor + * - 3’b010: Reserved for future use + * - 3’b011: Running: Waiting for receive packet + * - 3’b100: Suspended: Receive Descriptor Unavailable + * - 3’b101: Running: Closing Receive Descriptor + * - 3’b110: TIME_STAMP write state + * - 3’b111: Running: Transferring the receive packet data from receive buffer to host memory + */ +#define ENET_DMA_STATUS_RS_MASK (0xE0000UL) +#define ENET_DMA_STATUS_RS_SHIFT (17U) +#define ENET_DMA_STATUS_RS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RS_SHIFT) & ENET_DMA_STATUS_RS_MASK) +#define ENET_DMA_STATUS_RS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RS_MASK) >> ENET_DMA_STATUS_RS_SHIFT) + +/* + * NIS (RW) + * + * Normal Interrupt Summary + * Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. + */ +#define ENET_DMA_STATUS_NIS_MASK (0x10000UL) +#define ENET_DMA_STATUS_NIS_SHIFT (16U) +#define ENET_DMA_STATUS_NIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_NIS_SHIFT) & ENET_DMA_STATUS_NIS_MASK) +#define ENET_DMA_STATUS_NIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_NIS_MASK) >> ENET_DMA_STATUS_NIS_SHIFT) + +/* + * AIS (RW) + * + * Abnormal Interrupt Summary + * Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. + */ +#define ENET_DMA_STATUS_AIS_MASK (0x8000U) +#define ENET_DMA_STATUS_AIS_SHIFT (15U) +#define ENET_DMA_STATUS_AIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_AIS_SHIFT) & ENET_DMA_STATUS_AIS_MASK) +#define ENET_DMA_STATUS_AIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_AIS_MASK) >> ENET_DMA_STATUS_AIS_SHIFT) + +/* + * ERI (RW) + * + * Early Receive Interrupt + * This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). + */ +#define ENET_DMA_STATUS_ERI_MASK (0x4000U) +#define ENET_DMA_STATUS_ERI_SHIFT (14U) +#define ENET_DMA_STATUS_ERI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ERI_SHIFT) & ENET_DMA_STATUS_ERI_MASK) +#define ENET_DMA_STATUS_ERI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ERI_MASK) >> ENET_DMA_STATUS_ERI_SHIFT) + +/* + * FBI (RW) + * + * Fatal Bus Error Interrupt + * This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. + */ +#define ENET_DMA_STATUS_FBI_MASK (0x2000U) +#define ENET_DMA_STATUS_FBI_SHIFT (13U) +#define ENET_DMA_STATUS_FBI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_FBI_SHIFT) & ENET_DMA_STATUS_FBI_MASK) +#define ENET_DMA_STATUS_FBI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_FBI_MASK) >> ENET_DMA_STATUS_FBI_SHIFT) + +/* + * ETI (RW) + * + * Early Transmit Interrupt + * This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + */ +#define ENET_DMA_STATUS_ETI_MASK (0x400U) +#define ENET_DMA_STATUS_ETI_SHIFT (10U) +#define ENET_DMA_STATUS_ETI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ETI_SHIFT) & ENET_DMA_STATUS_ETI_MASK) +#define ENET_DMA_STATUS_ETI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ETI_MASK) >> ENET_DMA_STATUS_ETI_SHIFT) + +/* + * RWT (RW) + * + * Receive Watchdog Timeout + * When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + */ +#define ENET_DMA_STATUS_RWT_MASK (0x200U) +#define ENET_DMA_STATUS_RWT_SHIFT (9U) +#define ENET_DMA_STATUS_RWT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RWT_SHIFT) & ENET_DMA_STATUS_RWT_MASK) +#define ENET_DMA_STATUS_RWT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RWT_MASK) >> ENET_DMA_STATUS_RWT_SHIFT) + +/* + * RPS (RW) + * + * Receive Process Stopped + * This bit is asserted when the Receive Process enters the Stopped state. + */ +#define ENET_DMA_STATUS_RPS_MASK (0x100U) +#define ENET_DMA_STATUS_RPS_SHIFT (8U) +#define ENET_DMA_STATUS_RPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RPS_SHIFT) & ENET_DMA_STATUS_RPS_MASK) +#define ENET_DMA_STATUS_RPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RPS_MASK) >> ENET_DMA_STATUS_RPS_SHIFT) + +/* + * RU (RW) + * + * Receive Buffer Unavailable + * This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. + */ +#define ENET_DMA_STATUS_RU_MASK (0x80U) +#define ENET_DMA_STATUS_RU_SHIFT (7U) +#define ENET_DMA_STATUS_RU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RU_SHIFT) & ENET_DMA_STATUS_RU_MASK) +#define ENET_DMA_STATUS_RU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RU_MASK) >> ENET_DMA_STATUS_RU_SHIFT) + +/* + * RI (RW) + * + * Receive Interrupt + * This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. + */ +#define ENET_DMA_STATUS_RI_MASK (0x40U) +#define ENET_DMA_STATUS_RI_SHIFT (6U) +#define ENET_DMA_STATUS_RI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RI_SHIFT) & ENET_DMA_STATUS_RI_MASK) +#define ENET_DMA_STATUS_RI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RI_MASK) >> ENET_DMA_STATUS_RI_SHIFT) + +/* + * UNF (RW) + * + * Transmit Underflow + * This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + */ +#define ENET_DMA_STATUS_UNF_MASK (0x20U) +#define ENET_DMA_STATUS_UNF_SHIFT (5U) +#define ENET_DMA_STATUS_UNF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_UNF_SHIFT) & ENET_DMA_STATUS_UNF_MASK) +#define ENET_DMA_STATUS_UNF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_UNF_MASK) >> ENET_DMA_STATUS_UNF_SHIFT) + +/* + * OVF (RW) + * + * Receive Overflow + * This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. + */ +#define ENET_DMA_STATUS_OVF_MASK (0x10U) +#define ENET_DMA_STATUS_OVF_SHIFT (4U) +#define ENET_DMA_STATUS_OVF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_OVF_SHIFT) & ENET_DMA_STATUS_OVF_MASK) +#define ENET_DMA_STATUS_OVF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_OVF_MASK) >> ENET_DMA_STATUS_OVF_SHIFT) + +/* + * TJT (RW) + * + * Transmit Jabber Timeout + * This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + */ +#define ENET_DMA_STATUS_TJT_MASK (0x8U) +#define ENET_DMA_STATUS_TJT_SHIFT (3U) +#define ENET_DMA_STATUS_TJT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TJT_SHIFT) & ENET_DMA_STATUS_TJT_MASK) +#define ENET_DMA_STATUS_TJT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TJT_MASK) >> ENET_DMA_STATUS_TJT_SHIFT) + +/* + * TU (RW) + * + * Transmit Buffer Unavailable + * This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. + */ +#define ENET_DMA_STATUS_TU_MASK (0x4U) +#define ENET_DMA_STATUS_TU_SHIFT (2U) +#define ENET_DMA_STATUS_TU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TU_SHIFT) & ENET_DMA_STATUS_TU_MASK) +#define ENET_DMA_STATUS_TU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TU_MASK) >> ENET_DMA_STATUS_TU_SHIFT) + +/* + * TPS (RW) + * + * Transmit Process Stopped + * This bit is set when the transmission is stopped. + */ +#define ENET_DMA_STATUS_TPS_MASK (0x2U) +#define ENET_DMA_STATUS_TPS_SHIFT (1U) +#define ENET_DMA_STATUS_TPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TPS_SHIFT) & ENET_DMA_STATUS_TPS_MASK) +#define ENET_DMA_STATUS_TPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TPS_MASK) >> ENET_DMA_STATUS_TPS_SHIFT) + +/* + * TI (RW) + * + * Transmit Interrupt + * This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. + */ +#define ENET_DMA_STATUS_TI_MASK (0x1U) +#define ENET_DMA_STATUS_TI_SHIFT (0U) +#define ENET_DMA_STATUS_TI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TI_SHIFT) & ENET_DMA_STATUS_TI_MASK) +#define ENET_DMA_STATUS_TI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TI_MASK) >> ENET_DMA_STATUS_TI_SHIFT) + +/* Bitfield definition for register: DMA_OP_MODE */ +/* + * DT (RW) + * + * Disable Dropping of TCP/IP Checksum Error Frames + * When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). + */ +#define ENET_DMA_OP_MODE_DT_MASK (0x10000000UL) +#define ENET_DMA_OP_MODE_DT_SHIFT (28U) +#define ENET_DMA_OP_MODE_DT_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DT_SHIFT) & ENET_DMA_OP_MODE_DT_MASK) +#define ENET_DMA_OP_MODE_DT_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DT_MASK) >> ENET_DMA_OP_MODE_DT_SHIFT) + +/* + * RSF (RW) + * + * Receive Store and Forward + * When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. + */ +#define ENET_DMA_OP_MODE_RSF_MASK (0x2000000UL) +#define ENET_DMA_OP_MODE_RSF_SHIFT (25U) +#define ENET_DMA_OP_MODE_RSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RSF_SHIFT) & ENET_DMA_OP_MODE_RSF_MASK) +#define ENET_DMA_OP_MODE_RSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RSF_MASK) >> ENET_DMA_OP_MODE_RSF_SHIFT) + +/* + * DFF (RW) + * + * Disable Flushing of Received Frames + * When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) + */ +#define ENET_DMA_OP_MODE_DFF_MASK (0x1000000UL) +#define ENET_DMA_OP_MODE_DFF_SHIFT (24U) +#define ENET_DMA_OP_MODE_DFF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DFF_SHIFT) & ENET_DMA_OP_MODE_DFF_MASK) +#define ENET_DMA_OP_MODE_DFF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DFF_MASK) >> ENET_DMA_OP_MODE_DFF_SHIFT) + +/* + * RFA_2 (RW) + * + * MSB of Threshold for Activating Flow Control + * If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: + * - 100: Full minus 5 KB, that is, FULL — 5 KB + * - 101: Full minus 6 KB, that is, FULL — 6 KB + * - 110: Full minus 7 KB, that is, FULL — 7 KB + * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + */ +#define ENET_DMA_OP_MODE_RFA_2_MASK (0x800000UL) +#define ENET_DMA_OP_MODE_RFA_2_SHIFT (23U) +#define ENET_DMA_OP_MODE_RFA_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_2_SHIFT) & ENET_DMA_OP_MODE_RFA_2_MASK) +#define ENET_DMA_OP_MODE_RFA_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_2_MASK) >> ENET_DMA_OP_MODE_RFA_2_SHIFT) + +/* + * RFD_2 (RW) + * + * MSB of Threshold for Deactivating Flow Control + * If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: + * - 100: Full minus 5 KB, that is, FULL — 5 KB + * - 101: Full minus 6 KB, that is, FULL — 6 KB + * - 110: Full minus 7 KB, that is, FULL — 7 KB + * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + */ +#define ENET_DMA_OP_MODE_RFD_2_MASK (0x400000UL) +#define ENET_DMA_OP_MODE_RFD_2_SHIFT (22U) +#define ENET_DMA_OP_MODE_RFD_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_2_SHIFT) & ENET_DMA_OP_MODE_RFD_2_MASK) +#define ENET_DMA_OP_MODE_RFD_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_2_MASK) >> ENET_DMA_OP_MODE_RFD_2_SHIFT) + +/* + * TSF (RW) + * + * Transmit Store and Forward + * When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. + */ +#define ENET_DMA_OP_MODE_TSF_MASK (0x200000UL) +#define ENET_DMA_OP_MODE_TSF_SHIFT (21U) +#define ENET_DMA_OP_MODE_TSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TSF_SHIFT) & ENET_DMA_OP_MODE_TSF_MASK) +#define ENET_DMA_OP_MODE_TSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TSF_MASK) >> ENET_DMA_OP_MODE_TSF_SHIFT) + +/* + * FTF (RW) + * + * Flush Transmit FIFO + * When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. + */ +#define ENET_DMA_OP_MODE_FTF_MASK (0x100000UL) +#define ENET_DMA_OP_MODE_FTF_SHIFT (20U) +#define ENET_DMA_OP_MODE_FTF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FTF_SHIFT) & ENET_DMA_OP_MODE_FTF_MASK) +#define ENET_DMA_OP_MODE_FTF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FTF_MASK) >> ENET_DMA_OP_MODE_FTF_SHIFT) + +/* + * TTC (RW) + * + * Transmit Threshold Control + * These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. + * - 000: 64 + * - 001: 128 + * - 010: 192 + * - 011: 256 + * - 100: 40 + * - 101: 32 + * - 110: 24 + * - 111: 16 + */ +#define ENET_DMA_OP_MODE_TTC_MASK (0x1C000UL) +#define ENET_DMA_OP_MODE_TTC_SHIFT (14U) +#define ENET_DMA_OP_MODE_TTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TTC_SHIFT) & ENET_DMA_OP_MODE_TTC_MASK) +#define ENET_DMA_OP_MODE_TTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TTC_MASK) >> ENET_DMA_OP_MODE_TTC_SHIFT) + +/* + * ST (RW) + * + * Start or Stop Transmission Command + * When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. + */ +#define ENET_DMA_OP_MODE_ST_MASK (0x2000U) +#define ENET_DMA_OP_MODE_ST_SHIFT (13U) +#define ENET_DMA_OP_MODE_ST_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_ST_SHIFT) & ENET_DMA_OP_MODE_ST_MASK) +#define ENET_DMA_OP_MODE_ST_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_ST_MASK) >> ENET_DMA_OP_MODE_ST_SHIFT) + +/* + * RFD (RW) + * + * Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. + * - 00: Full minus 1 KB, that is, FULL — 1 KB + * - 01: Full minus 2 KB, that is, FULL — 2 KB + * - 10: Full minus 3 KB, that is, FULL — 3 KB + * - 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. + */ +#define ENET_DMA_OP_MODE_RFD_MASK (0x1800U) +#define ENET_DMA_OP_MODE_RFD_SHIFT (11U) +#define ENET_DMA_OP_MODE_RFD_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_SHIFT) & ENET_DMA_OP_MODE_RFD_MASK) +#define ENET_DMA_OP_MODE_RFD_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_MASK) >> ENET_DMA_OP_MODE_RFD_SHIFT) + +/* + * RFA (RW) + * + * Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. + * - 00: Full minus 1 KB, that is, FULL—1KB. + * - 01: Full minus 2 KB, that is, FULL—2KB. + * - 10: Full minus 3 KB, that is, FULL—3KB. + * - 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition + */ +#define ENET_DMA_OP_MODE_RFA_MASK (0x600U) +#define ENET_DMA_OP_MODE_RFA_SHIFT (9U) +#define ENET_DMA_OP_MODE_RFA_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_SHIFT) & ENET_DMA_OP_MODE_RFA_MASK) +#define ENET_DMA_OP_MODE_RFA_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_MASK) >> ENET_DMA_OP_MODE_RFA_SHIFT) + +/* + * EFC (RW) + * + * Enable HW Flow Control + * When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. + */ +#define ENET_DMA_OP_MODE_EFC_MASK (0x100U) +#define ENET_DMA_OP_MODE_EFC_SHIFT (8U) +#define ENET_DMA_OP_MODE_EFC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_EFC_SHIFT) & ENET_DMA_OP_MODE_EFC_MASK) +#define ENET_DMA_OP_MODE_EFC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_EFC_MASK) >> ENET_DMA_OP_MODE_EFC_SHIFT) + +/* + * FEF (RW) + * + * Forward Error Frames + * When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. + */ +#define ENET_DMA_OP_MODE_FEF_MASK (0x80U) +#define ENET_DMA_OP_MODE_FEF_SHIFT (7U) +#define ENET_DMA_OP_MODE_FEF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FEF_SHIFT) & ENET_DMA_OP_MODE_FEF_MASK) +#define ENET_DMA_OP_MODE_FEF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FEF_MASK) >> ENET_DMA_OP_MODE_FEF_SHIFT) + +/* + * FUF (RW) + * + * Forward Undersized Good Frames + * When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. + */ +#define ENET_DMA_OP_MODE_FUF_MASK (0x40U) +#define ENET_DMA_OP_MODE_FUF_SHIFT (6U) +#define ENET_DMA_OP_MODE_FUF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FUF_SHIFT) & ENET_DMA_OP_MODE_FUF_MASK) +#define ENET_DMA_OP_MODE_FUF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FUF_MASK) >> ENET_DMA_OP_MODE_FUF_SHIFT) + +/* + * DGF (RW) + * + * Drop Giant Frames + * When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). + */ +#define ENET_DMA_OP_MODE_DGF_MASK (0x20U) +#define ENET_DMA_OP_MODE_DGF_SHIFT (5U) +#define ENET_DMA_OP_MODE_DGF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DGF_SHIFT) & ENET_DMA_OP_MODE_DGF_MASK) +#define ENET_DMA_OP_MODE_DGF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DGF_MASK) >> ENET_DMA_OP_MODE_DGF_SHIFT) + +/* + * RTC (RW) + * + * Receive Threshold Control + * These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. + * - 00: 64 + * - 01: 32 + * - 10: 96 + * - 11: 128 + */ +#define ENET_DMA_OP_MODE_RTC_MASK (0x18U) +#define ENET_DMA_OP_MODE_RTC_SHIFT (3U) +#define ENET_DMA_OP_MODE_RTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RTC_SHIFT) & ENET_DMA_OP_MODE_RTC_MASK) +#define ENET_DMA_OP_MODE_RTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RTC_MASK) >> ENET_DMA_OP_MODE_RTC_SHIFT) + +/* + * OSF (RW) + * + * Operate on Second Frame + * When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + */ +#define ENET_DMA_OP_MODE_OSF_MASK (0x4U) +#define ENET_DMA_OP_MODE_OSF_SHIFT (2U) +#define ENET_DMA_OP_MODE_OSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_OSF_SHIFT) & ENET_DMA_OP_MODE_OSF_MASK) +#define ENET_DMA_OP_MODE_OSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_OSF_MASK) >> ENET_DMA_OP_MODE_OSF_SHIFT) + +/* + * SR (RW) + * + * Start or Stop Receive + * When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. + */ +#define ENET_DMA_OP_MODE_SR_MASK (0x2U) +#define ENET_DMA_OP_MODE_SR_SHIFT (1U) +#define ENET_DMA_OP_MODE_SR_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_SR_SHIFT) & ENET_DMA_OP_MODE_SR_MASK) +#define ENET_DMA_OP_MODE_SR_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_SR_MASK) >> ENET_DMA_OP_MODE_SR_SHIFT) + +/* Bitfield definition for register: DMA_INTR_EN */ +/* + * NIE (RW) + * + * Normal Interrupt Summary Enable + * When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt + */ +#define ENET_DMA_INTR_EN_NIE_MASK (0x10000UL) +#define ENET_DMA_INTR_EN_NIE_SHIFT (16U) +#define ENET_DMA_INTR_EN_NIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_NIE_SHIFT) & ENET_DMA_INTR_EN_NIE_MASK) +#define ENET_DMA_INTR_EN_NIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_NIE_MASK) >> ENET_DMA_INTR_EN_NIE_SHIFT) + +/* + * AIE (RW) + * + * Abnormal Interrupt Summary Enable + * When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error + */ +#define ENET_DMA_INTR_EN_AIE_MASK (0x8000U) +#define ENET_DMA_INTR_EN_AIE_SHIFT (15U) +#define ENET_DMA_INTR_EN_AIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_AIE_SHIFT) & ENET_DMA_INTR_EN_AIE_MASK) +#define ENET_DMA_INTR_EN_AIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_AIE_MASK) >> ENET_DMA_INTR_EN_AIE_SHIFT) + +/* + * ERE (RW) + * + * Early Receive Interrupt Enable + * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_ERE_MASK (0x4000U) +#define ENET_DMA_INTR_EN_ERE_SHIFT (14U) +#define ENET_DMA_INTR_EN_ERE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ERE_SHIFT) & ENET_DMA_INTR_EN_ERE_MASK) +#define ENET_DMA_INTR_EN_ERE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ERE_MASK) >> ENET_DMA_INTR_EN_ERE_SHIFT) + +/* + * FBE (RW) + * + * Fatal Bus Error Enable + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_FBE_MASK (0x2000U) +#define ENET_DMA_INTR_EN_FBE_SHIFT (13U) +#define ENET_DMA_INTR_EN_FBE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_FBE_SHIFT) & ENET_DMA_INTR_EN_FBE_MASK) +#define ENET_DMA_INTR_EN_FBE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_FBE_MASK) >> ENET_DMA_INTR_EN_FBE_SHIFT) + +/* + * ETE (RW) + * + * Early Transmit Interrupt Enable + * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_ETE_MASK (0x400U) +#define ENET_DMA_INTR_EN_ETE_SHIFT (10U) +#define ENET_DMA_INTR_EN_ETE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ETE_SHIFT) & ENET_DMA_INTR_EN_ETE_MASK) +#define ENET_DMA_INTR_EN_ETE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ETE_MASK) >> ENET_DMA_INTR_EN_ETE_SHIFT) + +/* + * RWE (RW) + * + * Receive Watchdog Timeout Enable + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_RWE_MASK (0x200U) +#define ENET_DMA_INTR_EN_RWE_SHIFT (9U) +#define ENET_DMA_INTR_EN_RWE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RWE_SHIFT) & ENET_DMA_INTR_EN_RWE_MASK) +#define ENET_DMA_INTR_EN_RWE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RWE_MASK) >> ENET_DMA_INTR_EN_RWE_SHIFT) + +/* + * RSE (RW) + * + * Receive Stopped Enable + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_RSE_MASK (0x100U) +#define ENET_DMA_INTR_EN_RSE_SHIFT (8U) +#define ENET_DMA_INTR_EN_RSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RSE_SHIFT) & ENET_DMA_INTR_EN_RSE_MASK) +#define ENET_DMA_INTR_EN_RSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RSE_MASK) >> ENET_DMA_INTR_EN_RSE_SHIFT) + +/* + * RUE (RW) + * + * Receive Buffer Unavailable Enable + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_RUE_MASK (0x80U) +#define ENET_DMA_INTR_EN_RUE_SHIFT (7U) +#define ENET_DMA_INTR_EN_RUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RUE_SHIFT) & ENET_DMA_INTR_EN_RUE_MASK) +#define ENET_DMA_INTR_EN_RUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RUE_MASK) >> ENET_DMA_INTR_EN_RUE_SHIFT) + +/* + * RIE (RW) + * + * Receive Interrupt Enable + * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_RIE_MASK (0x40U) +#define ENET_DMA_INTR_EN_RIE_SHIFT (6U) +#define ENET_DMA_INTR_EN_RIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RIE_SHIFT) & ENET_DMA_INTR_EN_RIE_MASK) +#define ENET_DMA_INTR_EN_RIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RIE_MASK) >> ENET_DMA_INTR_EN_RIE_SHIFT) + +/* + * UNE (RW) + * + * Underflow Interrupt Enable + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_UNE_MASK (0x20U) +#define ENET_DMA_INTR_EN_UNE_SHIFT (5U) +#define ENET_DMA_INTR_EN_UNE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_UNE_SHIFT) & ENET_DMA_INTR_EN_UNE_MASK) +#define ENET_DMA_INTR_EN_UNE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_UNE_MASK) >> ENET_DMA_INTR_EN_UNE_SHIFT) + +/* + * OVE (RW) + * + * Overflow Interrupt Enable + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_OVE_MASK (0x10U) +#define ENET_DMA_INTR_EN_OVE_SHIFT (4U) +#define ENET_DMA_INTR_EN_OVE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_OVE_SHIFT) & ENET_DMA_INTR_EN_OVE_MASK) +#define ENET_DMA_INTR_EN_OVE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_OVE_MASK) >> ENET_DMA_INTR_EN_OVE_SHIFT) + +/* + * TJE (RW) + * + * Transmit Jabber Timeout Enable + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_TJE_MASK (0x8U) +#define ENET_DMA_INTR_EN_TJE_SHIFT (3U) +#define ENET_DMA_INTR_EN_TJE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TJE_SHIFT) & ENET_DMA_INTR_EN_TJE_MASK) +#define ENET_DMA_INTR_EN_TJE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TJE_MASK) >> ENET_DMA_INTR_EN_TJE_SHIFT) + +/* + * TUE (RW) + * + * Transmit Buffer Unavailable Enable + * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_TUE_MASK (0x4U) +#define ENET_DMA_INTR_EN_TUE_SHIFT (2U) +#define ENET_DMA_INTR_EN_TUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TUE_SHIFT) & ENET_DMA_INTR_EN_TUE_MASK) +#define ENET_DMA_INTR_EN_TUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TUE_MASK) >> ENET_DMA_INTR_EN_TUE_SHIFT) + +/* + * TSE (RW) + * + * Transmit Stopped Enable + * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_TSE_MASK (0x2U) +#define ENET_DMA_INTR_EN_TSE_SHIFT (1U) +#define ENET_DMA_INTR_EN_TSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TSE_SHIFT) & ENET_DMA_INTR_EN_TSE_MASK) +#define ENET_DMA_INTR_EN_TSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TSE_MASK) >> ENET_DMA_INTR_EN_TSE_SHIFT) + +/* + * TIE (RW) + * + * Transmit Interrupt Enable + * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. + */ +#define ENET_DMA_INTR_EN_TIE_MASK (0x1U) +#define ENET_DMA_INTR_EN_TIE_SHIFT (0U) +#define ENET_DMA_INTR_EN_TIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TIE_SHIFT) & ENET_DMA_INTR_EN_TIE_MASK) +#define ENET_DMA_INTR_EN_TIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TIE_MASK) >> ENET_DMA_INTR_EN_TIE_SHIFT) + +/* Bitfield definition for register: DMA_MISS_OVF_CNT */ +/* + * ONFCNTOVF (RW) + * + * Overflow Bit for FIFO Overflow Counter + * This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. + */ +#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK (0x10000000UL) +#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT (28U) +#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) +#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) + +/* + * OVFFRMCNT (RW) + * + * Overflow Frame Counter + * This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. + */ +#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK (0xFFE0000UL) +#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT (17U) +#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) +#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) + +/* + * MISCNTOVF (RW) + * + * Overflow Bit for Missed Frame Counter + * This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. + */ +#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK (0x10000UL) +#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT (16U) +#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) +#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) + +/* + * MISFRMCNT (RW) + * + * Missed Frame Counter + * This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. + */ +#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK (0xFFFFU) +#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT (0U) +#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) +#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) + +/* Bitfield definition for register: DMA_RX_INTR_WDOG */ +/* + * RIWT (RW) + * + * RI Watchdog Timer Count + * This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + */ +#define ENET_DMA_RX_INTR_WDOG_RIWT_MASK (0xFFU) +#define ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT (0U) +#define ENET_DMA_RX_INTR_WDOG_RIWT_SET(x) (((uint32_t)(x) << ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) +#define ENET_DMA_RX_INTR_WDOG_RIWT_GET(x) (((uint32_t)(x) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) >> ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) + +/* Bitfield definition for register: DMA_AXI_MODE */ +/* + * EN_LPI (RW) + * + * Enable Low Power Interface (LPI) + * When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. + */ +#define ENET_DMA_AXI_MODE_EN_LPI_MASK (0x80000000UL) +#define ENET_DMA_AXI_MODE_EN_LPI_SHIFT (31U) +#define ENET_DMA_AXI_MODE_EN_LPI_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_EN_LPI_SHIFT) & ENET_DMA_AXI_MODE_EN_LPI_MASK) +#define ENET_DMA_AXI_MODE_EN_LPI_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_EN_LPI_MASK) >> ENET_DMA_AXI_MODE_EN_LPI_SHIFT) + +/* + * LPI_XIT_FRM (RW) + * + * Unlock on Magic Packet or Remote Wake-Up Frame + * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. + */ +#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK (0x40000000UL) +#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT (30U) +#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) +#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) >> ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) + +/* + * WR_OSR_LMT (RW) + * + * AXI Maximum Write Outstanding Request Limit + * This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. + */ +#define ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK (0xF00000UL) +#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT (20U) +#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) +#define ENET_DMA_AXI_MODE_WR_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) + +/* + * RD_OSR_LMT (RW) + * + * AXI Maximum Read Outstanding Request Limit + * This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. + */ +#define ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK (0xF0000UL) +#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT (16U) +#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) +#define ENET_DMA_AXI_MODE_RD_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) + +/* + * ONEKBBE (RW) + * + * 1 KB Boundary Crossing Enable for the GMAC-AXI Master + * When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. + */ +#define ENET_DMA_AXI_MODE_ONEKBBE_MASK (0x2000U) +#define ENET_DMA_AXI_MODE_ONEKBBE_SHIFT (13U) +#define ENET_DMA_AXI_MODE_ONEKBBE_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) +#define ENET_DMA_AXI_MODE_ONEKBBE_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) >> ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) + +/* + * AXI_AAL (RW) + * + * Address-Aligned Beats + * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. + */ +#define ENET_DMA_AXI_MODE_AXI_AAL_MASK (0x1000U) +#define ENET_DMA_AXI_MODE_AXI_AAL_SHIFT (12U) +#define ENET_DMA_AXI_MODE_AXI_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) +#define ENET_DMA_AXI_MODE_AXI_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) >> ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) + +/* + * BLEN256 (RW) + * + * AXI Burst Length 256 + * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). + */ +#define ENET_DMA_AXI_MODE_BLEN256_MASK (0x80U) +#define ENET_DMA_AXI_MODE_BLEN256_SHIFT (7U) +#define ENET_DMA_AXI_MODE_BLEN256_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN256_SHIFT) & ENET_DMA_AXI_MODE_BLEN256_MASK) +#define ENET_DMA_AXI_MODE_BLEN256_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN256_MASK) >> ENET_DMA_AXI_MODE_BLEN256_SHIFT) + +/* + * BLEN128 (RW) + * + * AXI Burst Length 128 + * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). + */ +#define ENET_DMA_AXI_MODE_BLEN128_MASK (0x40U) +#define ENET_DMA_AXI_MODE_BLEN128_SHIFT (6U) +#define ENET_DMA_AXI_MODE_BLEN128_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN128_SHIFT) & ENET_DMA_AXI_MODE_BLEN128_MASK) +#define ENET_DMA_AXI_MODE_BLEN128_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN128_MASK) >> ENET_DMA_AXI_MODE_BLEN128_SHIFT) + +/* + * BLEN64 (RW) + * + * AXI Burst Length 64 + * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). + */ +#define ENET_DMA_AXI_MODE_BLEN64_MASK (0x20U) +#define ENET_DMA_AXI_MODE_BLEN64_SHIFT (5U) +#define ENET_DMA_AXI_MODE_BLEN64_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN64_SHIFT) & ENET_DMA_AXI_MODE_BLEN64_MASK) +#define ENET_DMA_AXI_MODE_BLEN64_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN64_MASK) >> ENET_DMA_AXI_MODE_BLEN64_SHIFT) + +/* + * BLEN32 (RW) + * + * AXI Burst Length 32 + * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). + */ +#define ENET_DMA_AXI_MODE_BLEN32_MASK (0x10U) +#define ENET_DMA_AXI_MODE_BLEN32_SHIFT (4U) +#define ENET_DMA_AXI_MODE_BLEN32_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN32_SHIFT) & ENET_DMA_AXI_MODE_BLEN32_MASK) +#define ENET_DMA_AXI_MODE_BLEN32_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN32_MASK) >> ENET_DMA_AXI_MODE_BLEN32_SHIFT) + +/* + * BLEN16 (RW) + * + * AXI Burst Length 16 + * When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. + */ +#define ENET_DMA_AXI_MODE_BLEN16_MASK (0x8U) +#define ENET_DMA_AXI_MODE_BLEN16_SHIFT (3U) +#define ENET_DMA_AXI_MODE_BLEN16_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN16_SHIFT) & ENET_DMA_AXI_MODE_BLEN16_MASK) +#define ENET_DMA_AXI_MODE_BLEN16_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN16_MASK) >> ENET_DMA_AXI_MODE_BLEN16_SHIFT) + +/* + * BLEN8 (RW) + * + * AXI Burst Length 8 + * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + */ +#define ENET_DMA_AXI_MODE_BLEN8_MASK (0x4U) +#define ENET_DMA_AXI_MODE_BLEN8_SHIFT (2U) +#define ENET_DMA_AXI_MODE_BLEN8_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN8_SHIFT) & ENET_DMA_AXI_MODE_BLEN8_MASK) +#define ENET_DMA_AXI_MODE_BLEN8_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN8_MASK) >> ENET_DMA_AXI_MODE_BLEN8_SHIFT) + +/* + * BLEN4 (RW) + * + * AXI Burst Length 4 + * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + */ +#define ENET_DMA_AXI_MODE_BLEN4_MASK (0x2U) +#define ENET_DMA_AXI_MODE_BLEN4_SHIFT (1U) +#define ENET_DMA_AXI_MODE_BLEN4_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN4_SHIFT) & ENET_DMA_AXI_MODE_BLEN4_MASK) +#define ENET_DMA_AXI_MODE_BLEN4_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN4_MASK) >> ENET_DMA_AXI_MODE_BLEN4_SHIFT) + +/* + * UNDEF (RW) + * + * AXI Undefined Burst Length + * This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. + */ +#define ENET_DMA_AXI_MODE_UNDEF_MASK (0x1U) +#define ENET_DMA_AXI_MODE_UNDEF_SHIFT (0U) +#define ENET_DMA_AXI_MODE_UNDEF_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_UNDEF_SHIFT) & ENET_DMA_AXI_MODE_UNDEF_MASK) +#define ENET_DMA_AXI_MODE_UNDEF_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_UNDEF_MASK) >> ENET_DMA_AXI_MODE_UNDEF_SHIFT) + +/* Bitfield definition for register: DMA_BUS_STATUS */ +/* + * AXIRDSTS (RW) + * + * AXI Master Read Channel Status + * When high, it indicates that AXI master's read channel is active and transferring data. + */ +#define ENET_DMA_BUS_STATUS_AXIRDSTS_MASK (0x2U) +#define ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT (1U) +#define ENET_DMA_BUS_STATUS_AXIRDSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) +#define ENET_DMA_BUS_STATUS_AXIRDSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) >> ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) + +/* + * AXWHSTS (RW) + * + * AXI Master Write Channel or AHB Master Status + * When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. + */ +#define ENET_DMA_BUS_STATUS_AXWHSTS_MASK (0x1U) +#define ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT (0U) +#define ENET_DMA_BUS_STATUS_AXWHSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) +#define ENET_DMA_BUS_STATUS_AXWHSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) >> ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) + +/* Bitfield definition for register: DMA_CURR_HOST_TX_DESC */ +/* + * CURTDESAPTR (RW) + * + * Host Transmit Descriptor Address Pointer + * Cleared on Reset. Pointer updated by the DMA during operation. + */ +#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK (0xFFFFFFFFUL) +#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT (0U) +#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) +#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) + +/* Bitfield definition for register: DMA_CURR_HOST_RX_DESC */ +/* + * CURRDESAPTR (RW) + * + * Host Receive Descriptor Address Pointer + * Cleared on Reset. Pointer updated by the DMA during operation. + */ +#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK (0xFFFFFFFFUL) +#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT (0U) +#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) +#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) + +/* Bitfield definition for register: DMA_CURR_HOST_TX_BUF */ +/* + * CURTBUFAPTR (RW) + * + * Host Transmit Buffer Address Pointer + * Cleared on Reset. Pointer updated by the DMA during operation. + */ +#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK (0xFFFFFFFFUL) +#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT (0U) +#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) +#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) + +/* Bitfield definition for register: DMA_CURR_HOST_RX_BUF */ +/* + * CURRBUFAPTR (RW) + * + * Host Receive Buffer Address Pointer + * Cleared on Reset. Pointer updated by the DMA during operation. + */ +#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK (0xFFFFFFFFUL) +#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT (0U) +#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) +#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) + +/* Bitfield definition for register: DMA_HW_FEATURE */ +/* + * ACTPHYIF (RW) + * + * Active or selected PHY interface + * When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. + * - 000: GMII or MII + * - 001: RGMII + * - 010: SGMII + * - 011: TBI + * - 100: RMII + * - 101: RTBI + * - 110: SMII + * - 111: RevMII - All Others: Reserved + */ +#define ENET_DMA_HW_FEATURE_ACTPHYIF_MASK (0x70000000UL) +#define ENET_DMA_HW_FEATURE_ACTPHYIF_SHIFT (28U) +#define ENET_DMA_HW_FEATURE_ACTPHYIF_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_ACTPHYIF_SHIFT) & ENET_DMA_HW_FEATURE_ACTPHYIF_MASK) +#define ENET_DMA_HW_FEATURE_ACTPHYIF_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_ACTPHYIF_MASK) >> ENET_DMA_HW_FEATURE_ACTPHYIF_SHIFT) + +/* + * SAVLANINS (RW) + * + * Source Address or VLAN Insertion + */ +#define ENET_DMA_HW_FEATURE_SAVLANINS_MASK (0x8000000UL) +#define ENET_DMA_HW_FEATURE_SAVLANINS_SHIFT (27U) +#define ENET_DMA_HW_FEATURE_SAVLANINS_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_SAVLANINS_SHIFT) & ENET_DMA_HW_FEATURE_SAVLANINS_MASK) +#define ENET_DMA_HW_FEATURE_SAVLANINS_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_SAVLANINS_MASK) >> ENET_DMA_HW_FEATURE_SAVLANINS_SHIFT) + +/* + * FLEXIPPSEN (RW) + * + * Flexible Pulse-Per-Second Output + */ +#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_MASK (0x4000000UL) +#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_SHIFT (26U) +#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_FLEXIPPSEN_SHIFT) & ENET_DMA_HW_FEATURE_FLEXIPPSEN_MASK) +#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_FLEXIPPSEN_MASK) >> ENET_DMA_HW_FEATURE_FLEXIPPSEN_SHIFT) + +/* + * INTTSEN (RW) + * + * Timestamping with Internal System Time + */ +#define ENET_DMA_HW_FEATURE_INTTSEN_MASK (0x2000000UL) +#define ENET_DMA_HW_FEATURE_INTTSEN_SHIFT (25U) +#define ENET_DMA_HW_FEATURE_INTTSEN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_INTTSEN_SHIFT) & ENET_DMA_HW_FEATURE_INTTSEN_MASK) +#define ENET_DMA_HW_FEATURE_INTTSEN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_INTTSEN_MASK) >> ENET_DMA_HW_FEATURE_INTTSEN_SHIFT) + +/* + * ENHDESSEL (RW) + * + * Alternate (Enhanced Descriptor) + */ +#define ENET_DMA_HW_FEATURE_ENHDESSEL_MASK (0x1000000UL) +#define ENET_DMA_HW_FEATURE_ENHDESSEL_SHIFT (24U) +#define ENET_DMA_HW_FEATURE_ENHDESSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_ENHDESSEL_SHIFT) & ENET_DMA_HW_FEATURE_ENHDESSEL_MASK) +#define ENET_DMA_HW_FEATURE_ENHDESSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_ENHDESSEL_MASK) >> ENET_DMA_HW_FEATURE_ENHDESSEL_SHIFT) + +/* + * TXCHCNT (RW) + * + * Number of additional Tx Channels + */ +#define ENET_DMA_HW_FEATURE_TXCHCNT_MASK (0xC00000UL) +#define ENET_DMA_HW_FEATURE_TXCHCNT_SHIFT (22U) +#define ENET_DMA_HW_FEATURE_TXCHCNT_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TXCHCNT_SHIFT) & ENET_DMA_HW_FEATURE_TXCHCNT_MASK) +#define ENET_DMA_HW_FEATURE_TXCHCNT_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TXCHCNT_MASK) >> ENET_DMA_HW_FEATURE_TXCHCNT_SHIFT) + +/* + * RXCHCNT (RW) + * + * Number of additional Rx Channels + */ +#define ENET_DMA_HW_FEATURE_RXCHCNT_MASK (0x300000UL) +#define ENET_DMA_HW_FEATURE_RXCHCNT_SHIFT (20U) +#define ENET_DMA_HW_FEATURE_RXCHCNT_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXCHCNT_SHIFT) & ENET_DMA_HW_FEATURE_RXCHCNT_MASK) +#define ENET_DMA_HW_FEATURE_RXCHCNT_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXCHCNT_MASK) >> ENET_DMA_HW_FEATURE_RXCHCNT_SHIFT) + +/* + * RXFIFOSIZE (RW) + * + * Rx FIFO > 2,048 Bytes + */ +#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_MASK (0x80000UL) +#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_SHIFT (19U) +#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXFIFOSIZE_SHIFT) & ENET_DMA_HW_FEATURE_RXFIFOSIZE_MASK) +#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXFIFOSIZE_MASK) >> ENET_DMA_HW_FEATURE_RXFIFOSIZE_SHIFT) + +/* + * RXTYP2COE (RW) + * + * IP Checksum Offload (Type 2) in Rx + */ +#define ENET_DMA_HW_FEATURE_RXTYP2COE_MASK (0x40000UL) +#define ENET_DMA_HW_FEATURE_RXTYP2COE_SHIFT (18U) +#define ENET_DMA_HW_FEATURE_RXTYP2COE_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXTYP2COE_SHIFT) & ENET_DMA_HW_FEATURE_RXTYP2COE_MASK) +#define ENET_DMA_HW_FEATURE_RXTYP2COE_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXTYP2COE_MASK) >> ENET_DMA_HW_FEATURE_RXTYP2COE_SHIFT) + +/* + * RXTYP1COE (RW) + * + * IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1. + */ +#define ENET_DMA_HW_FEATURE_RXTYP1COE_MASK (0x20000UL) +#define ENET_DMA_HW_FEATURE_RXTYP1COE_SHIFT (17U) +#define ENET_DMA_HW_FEATURE_RXTYP1COE_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXTYP1COE_SHIFT) & ENET_DMA_HW_FEATURE_RXTYP1COE_MASK) +#define ENET_DMA_HW_FEATURE_RXTYP1COE_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXTYP1COE_MASK) >> ENET_DMA_HW_FEATURE_RXTYP1COE_SHIFT) + +/* + * TXCOESEL (RW) + * + * Checksum Offload in Tx + */ +#define ENET_DMA_HW_FEATURE_TXCOESEL_MASK (0x10000UL) +#define ENET_DMA_HW_FEATURE_TXCOESEL_SHIFT (16U) +#define ENET_DMA_HW_FEATURE_TXCOESEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TXCOESEL_SHIFT) & ENET_DMA_HW_FEATURE_TXCOESEL_MASK) +#define ENET_DMA_HW_FEATURE_TXCOESEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TXCOESEL_MASK) >> ENET_DMA_HW_FEATURE_TXCOESEL_SHIFT) + +/* + * AVSEL (RW) + * + * AV feature + */ +#define ENET_DMA_HW_FEATURE_AVSEL_MASK (0x8000U) +#define ENET_DMA_HW_FEATURE_AVSEL_SHIFT (15U) +#define ENET_DMA_HW_FEATURE_AVSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_AVSEL_SHIFT) & ENET_DMA_HW_FEATURE_AVSEL_MASK) +#define ENET_DMA_HW_FEATURE_AVSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_AVSEL_MASK) >> ENET_DMA_HW_FEATURE_AVSEL_SHIFT) + +/* + * EEESEL (RW) + * + * Energy Efficient Ethernet + */ +#define ENET_DMA_HW_FEATURE_EEESEL_MASK (0x4000U) +#define ENET_DMA_HW_FEATURE_EEESEL_SHIFT (14U) +#define ENET_DMA_HW_FEATURE_EEESEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_EEESEL_SHIFT) & ENET_DMA_HW_FEATURE_EEESEL_MASK) +#define ENET_DMA_HW_FEATURE_EEESEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_EEESEL_MASK) >> ENET_DMA_HW_FEATURE_EEESEL_SHIFT) + +/* + * TSVER2SEL (RW) + * + * IEEE 1588-2008 Advanced timestamp + */ +#define ENET_DMA_HW_FEATURE_TSVER2SEL_MASK (0x2000U) +#define ENET_DMA_HW_FEATURE_TSVER2SEL_SHIFT (13U) +#define ENET_DMA_HW_FEATURE_TSVER2SEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TSVER2SEL_SHIFT) & ENET_DMA_HW_FEATURE_TSVER2SEL_MASK) +#define ENET_DMA_HW_FEATURE_TSVER2SEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TSVER2SEL_MASK) >> ENET_DMA_HW_FEATURE_TSVER2SEL_SHIFT) + +/* + * TSVER1SEL (RW) + * + * Only IEEE 1588-2002 timestamp + */ +#define ENET_DMA_HW_FEATURE_TSVER1SEL_MASK (0x1000U) +#define ENET_DMA_HW_FEATURE_TSVER1SEL_SHIFT (12U) +#define ENET_DMA_HW_FEATURE_TSVER1SEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TSVER1SEL_SHIFT) & ENET_DMA_HW_FEATURE_TSVER1SEL_MASK) +#define ENET_DMA_HW_FEATURE_TSVER1SEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TSVER1SEL_MASK) >> ENET_DMA_HW_FEATURE_TSVER1SEL_SHIFT) + +/* + * MMCSEL (RW) + * + * RMON module + */ +#define ENET_DMA_HW_FEATURE_MMCSEL_MASK (0x800U) +#define ENET_DMA_HW_FEATURE_MMCSEL_SHIFT (11U) +#define ENET_DMA_HW_FEATURE_MMCSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_MMCSEL_SHIFT) & ENET_DMA_HW_FEATURE_MMCSEL_MASK) +#define ENET_DMA_HW_FEATURE_MMCSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_MMCSEL_MASK) >> ENET_DMA_HW_FEATURE_MMCSEL_SHIFT) + +/* + * MGKSEL (RW) + * + * PMT magic packet + */ +#define ENET_DMA_HW_FEATURE_MGKSEL_MASK (0x400U) +#define ENET_DMA_HW_FEATURE_MGKSEL_SHIFT (10U) +#define ENET_DMA_HW_FEATURE_MGKSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_MGKSEL_SHIFT) & ENET_DMA_HW_FEATURE_MGKSEL_MASK) +#define ENET_DMA_HW_FEATURE_MGKSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_MGKSEL_MASK) >> ENET_DMA_HW_FEATURE_MGKSEL_SHIFT) + +/* + * RWKSEL (RW) + * + * PMT remote wake-up frame + */ +#define ENET_DMA_HW_FEATURE_RWKSEL_MASK (0x200U) +#define ENET_DMA_HW_FEATURE_RWKSEL_SHIFT (9U) +#define ENET_DMA_HW_FEATURE_RWKSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RWKSEL_SHIFT) & ENET_DMA_HW_FEATURE_RWKSEL_MASK) +#define ENET_DMA_HW_FEATURE_RWKSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RWKSEL_MASK) >> ENET_DMA_HW_FEATURE_RWKSEL_SHIFT) + +/* + * SMASEL (RW) + * + * SMA (MDIO) Interface + */ +#define ENET_DMA_HW_FEATURE_SMASEL_MASK (0x100U) +#define ENET_DMA_HW_FEATURE_SMASEL_SHIFT (8U) +#define ENET_DMA_HW_FEATURE_SMASEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_SMASEL_SHIFT) & ENET_DMA_HW_FEATURE_SMASEL_MASK) +#define ENET_DMA_HW_FEATURE_SMASEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_SMASEL_MASK) >> ENET_DMA_HW_FEATURE_SMASEL_SHIFT) + +/* + * L3L4FLTREN (RW) + * + * Layer 3 and Layer 4 feature + */ +#define ENET_DMA_HW_FEATURE_L3L4FLTREN_MASK (0x80U) +#define ENET_DMA_HW_FEATURE_L3L4FLTREN_SHIFT (7U) +#define ENET_DMA_HW_FEATURE_L3L4FLTREN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_L3L4FLTREN_SHIFT) & ENET_DMA_HW_FEATURE_L3L4FLTREN_MASK) +#define ENET_DMA_HW_FEATURE_L3L4FLTREN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_L3L4FLTREN_MASK) >> ENET_DMA_HW_FEATURE_L3L4FLTREN_SHIFT) + +/* + * PCSSEL (RW) + * + * PCS registers (TBI, SGMII, or RTBI PHY interface) + */ +#define ENET_DMA_HW_FEATURE_PCSSEL_MASK (0x40U) +#define ENET_DMA_HW_FEATURE_PCSSEL_SHIFT (6U) +#define ENET_DMA_HW_FEATURE_PCSSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_PCSSEL_SHIFT) & ENET_DMA_HW_FEATURE_PCSSEL_MASK) +#define ENET_DMA_HW_FEATURE_PCSSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_PCSSEL_MASK) >> ENET_DMA_HW_FEATURE_PCSSEL_SHIFT) + +/* + * ADDMACADRSEL (RW) + * + * Multiple MAC Address registers + */ +#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_MASK (0x20U) +#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_SHIFT (5U) +#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_ADDMACADRSEL_SHIFT) & ENET_DMA_HW_FEATURE_ADDMACADRSEL_MASK) +#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_ADDMACADRSEL_MASK) >> ENET_DMA_HW_FEATURE_ADDMACADRSEL_SHIFT) + +/* + * HASHSEL (RW) + * + * HASH filter + */ +#define ENET_DMA_HW_FEATURE_HASHSEL_MASK (0x10U) +#define ENET_DMA_HW_FEATURE_HASHSEL_SHIFT (4U) +#define ENET_DMA_HW_FEATURE_HASHSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_HASHSEL_SHIFT) & ENET_DMA_HW_FEATURE_HASHSEL_MASK) +#define ENET_DMA_HW_FEATURE_HASHSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_HASHSEL_MASK) >> ENET_DMA_HW_FEATURE_HASHSEL_SHIFT) + +/* + * EXTHASHEN (RW) + * + * Expanded DA Hash filter + */ +#define ENET_DMA_HW_FEATURE_EXTHASHEN_MASK (0x8U) +#define ENET_DMA_HW_FEATURE_EXTHASHEN_SHIFT (3U) +#define ENET_DMA_HW_FEATURE_EXTHASHEN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_EXTHASHEN_SHIFT) & ENET_DMA_HW_FEATURE_EXTHASHEN_MASK) +#define ENET_DMA_HW_FEATURE_EXTHASHEN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_EXTHASHEN_MASK) >> ENET_DMA_HW_FEATURE_EXTHASHEN_SHIFT) + +/* + * HDSEL (RW) + * + * Half-duplex support + */ +#define ENET_DMA_HW_FEATURE_HDSEL_MASK (0x4U) +#define ENET_DMA_HW_FEATURE_HDSEL_SHIFT (2U) +#define ENET_DMA_HW_FEATURE_HDSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_HDSEL_SHIFT) & ENET_DMA_HW_FEATURE_HDSEL_MASK) +#define ENET_DMA_HW_FEATURE_HDSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_HDSEL_MASK) >> ENET_DMA_HW_FEATURE_HDSEL_SHIFT) + +/* + * GMIISEL (RW) + * + * 1000 Mbps support + */ +#define ENET_DMA_HW_FEATURE_GMIISEL_MASK (0x2U) +#define ENET_DMA_HW_FEATURE_GMIISEL_SHIFT (1U) +#define ENET_DMA_HW_FEATURE_GMIISEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_GMIISEL_SHIFT) & ENET_DMA_HW_FEATURE_GMIISEL_MASK) +#define ENET_DMA_HW_FEATURE_GMIISEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_GMIISEL_MASK) >> ENET_DMA_HW_FEATURE_GMIISEL_SHIFT) + +/* + * MIISEL (RW) + * + * 10 or 100 Mbps support + */ +#define ENET_DMA_HW_FEATURE_MIISEL_MASK (0x1U) +#define ENET_DMA_HW_FEATURE_MIISEL_SHIFT (0U) +#define ENET_DMA_HW_FEATURE_MIISEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_MIISEL_SHIFT) & ENET_DMA_HW_FEATURE_MIISEL_MASK) +#define ENET_DMA_HW_FEATURE_MIISEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_MIISEL_MASK) >> ENET_DMA_HW_FEATURE_MIISEL_SHIFT) + +/* Bitfield definition for register: CTRL0 */ +/* + * ENET0_RXCLK_DLY_SEL (RW) + * + */ +#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3E0U) +#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (5U) +#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) +#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) + +/* + * ENET0_TXCLK_DLY_SEL (RW) + * + */ +#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x1FU) +#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT (0U) +#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) +#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) + +/* Bitfield definition for register: CTRL2 */ +/* + * ENET0_IRQ_EN (RW) + * + */ +#define ENET_CTRL2_ENET0_IRQ_EN_MASK (0xF8000000UL) +#define ENET_CTRL2_ENET0_IRQ_EN_SHIFT (27U) +#define ENET_CTRL2_ENET0_IRQ_EN_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_IRQ_EN_SHIFT) & ENET_CTRL2_ENET0_IRQ_EN_MASK) +#define ENET_CTRL2_ENET0_IRQ_EN_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_IRQ_EN_MASK) >> ENET_CTRL2_ENET0_IRQ_EN_SHIFT) + +/* + * ENET0_REFCLK_OE (RW) + * + */ +#define ENET_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL) +#define ENET_CTRL2_ENET0_REFCLK_OE_SHIFT (19U) +#define ENET_CTRL2_ENET0_REFCLK_OE_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_REFCLK_OE_SHIFT) & ENET_CTRL2_ENET0_REFCLK_OE_MASK) +#define ENET_CTRL2_ENET0_REFCLK_OE_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_REFCLK_OE_MASK) >> ENET_CTRL2_ENET0_REFCLK_OE_SHIFT) + +/* + * ENET0_PHY_INF_SEL (RW) + * + */ +#define ENET_CTRL2_ENET0_PHY_INF_SEL_MASK (0xE000U) +#define ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT (13U) +#define ENET_CTRL2_ENET0_PHY_INF_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT) & ENET_CTRL2_ENET0_PHY_INF_SEL_MASK) +#define ENET_CTRL2_ENET0_PHY_INF_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_PHY_INF_SEL_MASK) >> ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT) + +/* + * ENET0_FLOWCTRL (RW) + * + */ +#define ENET_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U) +#define ENET_CTRL2_ENET0_FLOWCTRL_SHIFT (12U) +#define ENET_CTRL2_ENET0_FLOWCTRL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_FLOWCTRL_SHIFT) & ENET_CTRL2_ENET0_FLOWCTRL_MASK) +#define ENET_CTRL2_ENET0_FLOWCTRL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_FLOWCTRL_MASK) >> ENET_CTRL2_ENET0_FLOWCTRL_SHIFT) + +/* + * ENET0_RMII_TXCLK_SEL (RW) + * + */ +#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U) +#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U) +#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) +#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) + + + +/* MAC_ADDR register group index macro definition */ +#define ENET_MAC_ADDR_1 (0UL) +#define ENET_MAC_ADDR_2 (1UL) +#define ENET_MAC_ADDR_3 (2UL) +#define ENET_MAC_ADDR_4 (3UL) + +/* L3_L4_CFG register group index macro definition */ +#define ENET_L3_L4_CFG_0 (0UL) +#define ENET_L3_L4_CFG_1 (1UL) +#define ENET_L3_L4_CFG_2 (2UL) +#define ENET_L3_L4_CFG_3 (3UL) + +/* HASH_TABLE register group index macro definition */ +#define ENET_HASH_TABLE_REGISTER0 (0UL) +#define ENET_HASH_TABLE_REGISTER1 (1UL) +#define ENET_HASH_TABLE_REGISTER2 (2UL) +#define ENET_HASH_TABLE_REGISTER3 (3UL) +#define ENET_HASH_TABLE_REGISTER4 (4UL) +#define ENET_HASH_TABLE_REGISTER5 (5UL) +#define ENET_HASH_TABLE_REGISTER6 (6UL) +#define ENET_HASH_TABLE_REGISTER7 (7UL) + +/* PPS register group index macro definition */ +#define ENET_PPS_1 (0UL) +#define ENET_PPS_2 (1UL) +#define ENET_PPS_3 (2UL) + + +#endif /* HPM_ENET_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_exip_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_exip_regs.h new file mode 100644 index 0000000000..024cffc5c0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_exip_regs.h @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_EXIP_H +#define HPM_EXIP_H + +typedef struct { + __R uint8_t RESERVED0[3072]; /* 0x0 - 0xBFF: Reserved */ + __RW uint32_t CFG; /* 0xC00: Configure Register */ + __R uint32_t STA; /* 0xC04: Status Register */ + __R uint8_t RESERVED1[248]; /* 0xC08 - 0xCFF: Reserved */ + struct { + __RW uint32_t KEY0; /* 0xD00: AES KEY */ + __RW uint32_t KEY1; /* 0xD04: AES KEY */ + __RW uint32_t KEY2; /* 0xD08: AES KEY */ + __RW uint32_t KEY3; /* 0xD0C: AES KEY */ + __RW uint32_t CTR0; /* 0xD10: AES Counter Word */ + __RW uint32_t CTR1; /* 0xD14: AES Counter Word */ + __RW uint32_t RGN_SA; /* 0xD18: AES Region Descriptor Word */ + __RW uint32_t RGN_EA; /* 0xD1C: AES Region Descriptor Word */ + __R uint8_t RESERVED0[32]; /* 0xD20 - 0xD3F: Reserved */ + } RGN[4]; +} EXIP_Type; + + +/* Bitfield definition for register: CFG */ +/* + * EXIPE (RW) + * + * Block Enable, when set to "0", this block disabled, and all the data from QSPI will pass the the read mast directly; EXIP process data as the configuration in the CR regs. + */ +#define EXIP_CFG_EXIPE_MASK (0x80000000UL) +#define EXIP_CFG_EXIPE_SHIFT (31U) +#define EXIP_CFG_EXIPE_SET(x) (((uint32_t)(x) << EXIP_CFG_EXIPE_SHIFT) & EXIP_CFG_EXIPE_MASK) +#define EXIP_CFG_EXIPE_GET(x) (((uint32_t)(x) & EXIP_CFG_EXIPE_MASK) >> EXIP_CFG_EXIPE_SHIFT) + +/* + * KBS (RW) + * + * KeyBlob Initiate + * "0", Key Blob was not initiated yet. + * "1", Key Blob was properly initiated. + */ +#define EXIP_CFG_KBS_MASK (0x40000000UL) +#define EXIP_CFG_KBS_SHIFT (30U) +#define EXIP_CFG_KBS_SET(x) (((uint32_t)(x) << EXIP_CFG_KBS_SHIFT) & EXIP_CFG_KBS_MASK) +#define EXIP_CFG_KBS_GET(x) (((uint32_t)(x) & EXIP_CFG_KBS_MASK) >> EXIP_CFG_KBS_SHIFT) + +/* + * KBEN (RW) + * + * Key Block Processing Enable. + * "0", key blob processing is enabled. + * "1", Key blob processing is disabled. + */ +#define EXIP_CFG_KBEN_MASK (0x20U) +#define EXIP_CFG_KBEN_SHIFT (5U) +#define EXIP_CFG_KBEN_SET(x) (((uint32_t)(x) << EXIP_CFG_KBEN_SHIFT) & EXIP_CFG_KBEN_MASK) +#define EXIP_CFG_KBEN_GET(x) (((uint32_t)(x) & EXIP_CFG_KBEN_MASK) >> EXIP_CFG_KBEN_SHIFT) + +/* + * IE (RW) + * + * Interrupt Request Enable. This field determines if the setting of SR[KBERR] generates a system interrupt. + * 0b - SR[KBERR] = 1 does not generate an interrupt request. + * 1b - SR[KBERR] = 1 generates an interrupt request. + */ +#define EXIP_CFG_IE_MASK (0x1U) +#define EXIP_CFG_IE_SHIFT (0U) +#define EXIP_CFG_IE_SET(x) (((uint32_t)(x) << EXIP_CFG_IE_SHIFT) & EXIP_CFG_IE_MASK) +#define EXIP_CFG_IE_GET(x) (((uint32_t)(x) & EXIP_CFG_IE_MASK) >> EXIP_CFG_IE_SHIFT) + +/* Bitfield definition for register: STA */ +/* + * KBC (RO) + * + * Key Blob Processing Done + * "0", key blob was not enabled or processing not done yet. + * "1", key blob processing was enabled and done. + */ +#define EXIP_STA_KBC_MASK (0x80000000UL) +#define EXIP_STA_KBC_SHIFT (31U) +#define EXIP_STA_KBC_GET(x) (((uint32_t)(x) & EXIP_STA_KBC_MASK) >> EXIP_STA_KBC_SHIFT) + +/* + * KBEN (RO) + * + * Key Blob Processing Enable + * “0”, Key Blob processing is not enabled. + * "1", Key Blob processing is enabled. + */ +#define EXIP_STA_KBEN_MASK (0x40000000UL) +#define EXIP_STA_KBEN_SHIFT (30U) +#define EXIP_STA_KBEN_GET(x) (((uint32_t)(x) & EXIP_STA_KBEN_MASK) >> EXIP_STA_KBEN_SHIFT) + +/* + * EXIPE (RO) + * + * Block Enable Mode. + * "0", EXIP disabled and bypasses all the data by the QSPI + * "1", EXIP is enabled, and processes data from the QSPI as the hw configuration bits. + */ +#define EXIP_STA_EXIPE_MASK (0x20000000UL) +#define EXIP_STA_EXIPE_SHIFT (29U) +#define EXIP_STA_EXIPE_GET(x) (((uint32_t)(x) & EXIP_STA_EXIPE_MASK) >> EXIP_STA_EXIPE_SHIFT) + +/* + * RGNE (RO) + * + * Context Integrity Error. + * This field signals an integrity error was detected in a specific context during key blob processing as signaled by SR[KBERR] = 1. bit 19 corresponds to context 3, bit 18 to context 2, bit 17 to context 1, bit 16 to context 0. + * This field is cleared if SR[KBERR] was set in response to a write asserting CR[FERR]. It is also cleared when SR[KBERR] is cleared. + * 0000b - No key blob integrity error was detected for context “n”. + * 0001b - A key blob integrity error was detected in context “n”. + */ +#define EXIP_STA_RGNE_MASK (0xF0000UL) +#define EXIP_STA_RGNE_SHIFT (16U) +#define EXIP_STA_RGNE_GET(x) (((uint32_t)(x) & EXIP_STA_RGNE_MASK) >> EXIP_STA_RGNE_SHIFT) + +/* + * KBERR (RO) + * + * Key Blob Error + * This field signals that one or more errors were detected during key blob processing. SR[ERCTX] provides + * the details on which contexts detected errors. This indicator can also be set by writing CR[FERR] = 1 (for + * testing purposes). If CR[IRQE] = 1, then the assertion of KBERR generates an interrupt request. + * "0", No key blob error detected. + * "1", One or more key blob errors has been detected + */ +#define EXIP_STA_KBERR_MASK (0x1U) +#define EXIP_STA_KBERR_SHIFT (0U) +#define EXIP_STA_KBERR_GET(x) (((uint32_t)(x) & EXIP_STA_KBERR_MASK) >> EXIP_STA_KBERR_SHIFT) + +/* Bitfield definition for register of struct array RGN: KEY0 */ +/* + * KEY (RW) + * + * AES Key + * The key is typically loaded as the corresponding key blob is unwrapped; alternatively, if enabled, it can be + * written using the APB bus. The four consecutive little-endian memory-mapped registers + * provide 128 bits of key storage. + * Word0: KEY[31:0][A03, A02, A01, A00] + * Word1: KEY[31:0][A07, A06, A05, A04] + * Word2: KEY[31:0][A11, A10, A09, A08] + * Word3: KEY[31:0][A15, A14, A13, A12] + */ +#define EXIP_RGN_KEY0_KEY_MASK (0xFFFFFFFFUL) +#define EXIP_RGN_KEY0_KEY_SHIFT (0U) +#define EXIP_RGN_KEY0_KEY_SET(x) (((uint32_t)(x) << EXIP_RGN_KEY0_KEY_SHIFT) & EXIP_RGN_KEY0_KEY_MASK) +#define EXIP_RGN_KEY0_KEY_GET(x) (((uint32_t)(x) & EXIP_RGN_KEY0_KEY_MASK) >> EXIP_RGN_KEY0_KEY_SHIFT) + +/* Bitfield definition for register of struct array RGN: KEY1 */ +/* + * KEY (RW) + * + * AES Key + * The key is typically loaded as the corresponding key blob is unwrapped; alternatively, if enabled, it can be + * written using the APB bus. The four consecutive little-endian memory-mapped registers + * provide 128 bits of key storage. + * Word0: KEY[31:0][A03, A02, A01, A00] + * Word1: KEY[31:0][A07, A06, A05, A04] + * Word2: KEY[31:0][A11, A10, A09, A08] + * Word3: KEY[31:0][A15, A14, A13, A12] + */ +#define EXIP_RGN_KEY1_KEY_MASK (0xFFFFFFFFUL) +#define EXIP_RGN_KEY1_KEY_SHIFT (0U) +#define EXIP_RGN_KEY1_KEY_SET(x) (((uint32_t)(x) << EXIP_RGN_KEY1_KEY_SHIFT) & EXIP_RGN_KEY1_KEY_MASK) +#define EXIP_RGN_KEY1_KEY_GET(x) (((uint32_t)(x) & EXIP_RGN_KEY1_KEY_MASK) >> EXIP_RGN_KEY1_KEY_SHIFT) + +/* Bitfield definition for register of struct array RGN: KEY2 */ +/* + * KEY (RW) + * + * AES Key + * The key is typically loaded as the corresponding key blob is unwrapped; alternatively, if enabled, it can be + * written using the APB bus. The four consecutive little-endian memory-mapped registers + * provide 128 bits of key storage. + * Word0: KEY[31:0][A03, A02, A01, A00] + * Word1: KEY[31:0][A07, A06, A05, A04] + * Word2: KEY[31:0][A11, A10, A09, A08] + * Word3: KEY[31:0][A15, A14, A13, A12] + */ +#define EXIP_RGN_KEY2_KEY_MASK (0xFFFFFFFFUL) +#define EXIP_RGN_KEY2_KEY_SHIFT (0U) +#define EXIP_RGN_KEY2_KEY_SET(x) (((uint32_t)(x) << EXIP_RGN_KEY2_KEY_SHIFT) & EXIP_RGN_KEY2_KEY_MASK) +#define EXIP_RGN_KEY2_KEY_GET(x) (((uint32_t)(x) & EXIP_RGN_KEY2_KEY_MASK) >> EXIP_RGN_KEY2_KEY_SHIFT) + +/* Bitfield definition for register of struct array RGN: KEY3 */ +/* + * KEY (RW) + * + * AES Key + * The key is typically loaded as the corresponding key blob is unwrapped; alternatively, if enabled, it can be + * written using the APB bus. The four consecutive little-endian memory-mapped registers + * provide 128 bits of key storage. + * Word0: KEY[31:0][A03, A02, A01, A00] + * Word1: KEY[31:0][A07, A06, A05, A04] + * Word2: KEY[31:0][A11, A10, A09, A08] + * Word3: KEY[31:0][A15, A14, A13, A12] + */ +#define EXIP_RGN_KEY3_KEY_MASK (0xFFFFFFFFUL) +#define EXIP_RGN_KEY3_KEY_SHIFT (0U) +#define EXIP_RGN_KEY3_KEY_SET(x) (((uint32_t)(x) << EXIP_RGN_KEY3_KEY_SHIFT) & EXIP_RGN_KEY3_KEY_MASK) +#define EXIP_RGN_KEY3_KEY_GET(x) (((uint32_t)(x) & EXIP_RGN_KEY3_KEY_MASK) >> EXIP_RGN_KEY3_KEY_SHIFT) + +/* Bitfield definition for register of struct array RGN: CTR0 */ +/* + * CTR (RW) + * + * AES Counter + * The upper 64 bits of the counter are typically loaded as the corresponding key blob is unwrapped; + * alternatively, if enabled, it can be written using the slave peripheral bus. The two consecutive memorymapped registers directly provide the upper 64 bits of counter storage. + * Word0: CTR[31:0][C3, C2, C1, C0] + * Word1: CTR[31:0][C7, C6, C5, C4] + * The third 32-bit portion of the CTR is formed by exclusive-or’ing the upper 64 bits of the counter as two + * 32-bit values, while the least-significant portion of the counter is the 32-bit 0-modulo-16 byte system + * address of the external flash memory. + * CTR[C0...C15] = {CTR[C0...C7], CTR[C0...C3] ^ CTR[C4...C7], systemAddress[31–4], 0h} + */ +#define EXIP_RGN_CTR0_CTR_MASK (0xFFFFFFFFUL) +#define EXIP_RGN_CTR0_CTR_SHIFT (0U) +#define EXIP_RGN_CTR0_CTR_SET(x) (((uint32_t)(x) << EXIP_RGN_CTR0_CTR_SHIFT) & EXIP_RGN_CTR0_CTR_MASK) +#define EXIP_RGN_CTR0_CTR_GET(x) (((uint32_t)(x) & EXIP_RGN_CTR0_CTR_MASK) >> EXIP_RGN_CTR0_CTR_SHIFT) + +/* Bitfield definition for register of struct array RGN: CTR1 */ +/* + * CTR (RW) + * + * AES Counter + * The upper 64 bits of the counter are typically loaded as the corresponding key blob is unwrapped; + * alternatively, if enabled, it can be written using the slave peripheral bus. The two consecutive memorymapped registers directly provide the upper 64 bits of counter storage. + * Word0: CTR[31:0][C3, C2, C1, C0] + * Word1: CTR[31:0][C7, C6, C5, C4] + * The third 32-bit portion of the CTR is formed by exclusive-or’ing the upper 64 bits of the counter as two + * 32-bit values, while the least-significant portion of the counter is the 32-bit 0-modulo-16 byte system + * address of the external flash memory. + * CTR[C0...C15] = {CTR[C0...C7], CTR[C0...C3] ^ CTR[C4...C7], systemAddress[31–4], 0h} + */ +#define EXIP_RGN_CTR1_CTR_MASK (0xFFFFFFFFUL) +#define EXIP_RGN_CTR1_CTR_SHIFT (0U) +#define EXIP_RGN_CTR1_CTR_SET(x) (((uint32_t)(x) << EXIP_RGN_CTR1_CTR_SHIFT) & EXIP_RGN_CTR1_CTR_MASK) +#define EXIP_RGN_CTR1_CTR_GET(x) (((uint32_t)(x) & EXIP_RGN_CTR1_CTR_MASK) >> EXIP_RGN_CTR1_CTR_SHIFT) + +/* Bitfield definition for register of struct array RGN: RGN_SA */ +/* + * START (RW) + * + * Start Address + * This field defines the most significant bits of the 0-modulo-1024 byte start address of the memory region + * for context n. + */ +#define EXIP_RGN_RGN_SA_START_MASK (0xFFFFFC00UL) +#define EXIP_RGN_RGN_SA_START_SHIFT (10U) +#define EXIP_RGN_RGN_SA_START_SET(x) (((uint32_t)(x) << EXIP_RGN_RGN_SA_START_SHIFT) & EXIP_RGN_RGN_SA_START_MASK) +#define EXIP_RGN_RGN_SA_START_GET(x) (((uint32_t)(x) & EXIP_RGN_RGN_SA_START_MASK) >> EXIP_RGN_RGN_SA_START_SHIFT) + +/* Bitfield definition for register of struct array RGN: RGN_EA */ +/* + * END (RW) + * + * End Address + * This field defines the most significant bits of the 1023-modulo-1024 byte end address of the memory + * region for context n. + */ +#define EXIP_RGN_RGN_EA_END_MASK (0xFFFFFC00UL) +#define EXIP_RGN_RGN_EA_END_SHIFT (10U) +#define EXIP_RGN_RGN_EA_END_SET(x) (((uint32_t)(x) << EXIP_RGN_RGN_EA_END_SHIFT) & EXIP_RGN_RGN_EA_END_MASK) +#define EXIP_RGN_RGN_EA_END_GET(x) (((uint32_t)(x) & EXIP_RGN_RGN_EA_END_MASK) >> EXIP_RGN_RGN_EA_END_SHIFT) + +/* + * DECEN (RW) + * + * AES Decryption Enable. + * For accesses hitting in a valid context, this bit indicates if the fetched data is to be decrypted or simply + * bypassed. + * "0" - Bypass the fetched data. + * "1" - Perform the CTR-AES128 mode decryption on the fetched data + */ +#define EXIP_RGN_RGN_EA_DECEN_MASK (0x2U) +#define EXIP_RGN_RGN_EA_DECEN_SHIFT (1U) +#define EXIP_RGN_RGN_EA_DECEN_SET(x) (((uint32_t)(x) << EXIP_RGN_RGN_EA_DECEN_SHIFT) & EXIP_RGN_RGN_EA_DECEN_MASK) +#define EXIP_RGN_RGN_EA_DECEN_GET(x) (((uint32_t)(x) & EXIP_RGN_RGN_EA_DECEN_MASK) >> EXIP_RGN_RGN_EA_DECEN_SHIFT) + +/* + * VALID (RW) + * + * Valid + * This field signals if the context is valid or not. + * "0" - Context is invalid. + * "1" - Context is valid. + */ +#define EXIP_RGN_RGN_EA_VALID_MASK (0x1U) +#define EXIP_RGN_RGN_EA_VALID_SHIFT (0U) +#define EXIP_RGN_RGN_EA_VALID_SET(x) (((uint32_t)(x) << EXIP_RGN_RGN_EA_VALID_SHIFT) & EXIP_RGN_RGN_EA_VALID_MASK) +#define EXIP_RGN_RGN_EA_VALID_GET(x) (((uint32_t)(x) & EXIP_RGN_RGN_EA_VALID_MASK) >> EXIP_RGN_RGN_EA_VALID_SHIFT) + + + +/* RGN register group index macro definition */ +#define EXIP_RGN_0 (0UL) +#define EXIP_RGN_1 (1UL) +#define EXIP_RGN_2 (2UL) +#define EXIP_RGN_3 (3UL) + + +#endif /* HPM_EXIP_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h new file mode 100644 index 0000000000..8c7bca3438 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_FFA_H +#define HPM_FFA_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: */ + __R uint32_t STATUS; /* 0x4: */ + __RW uint32_t INT_EN; /* 0x8: */ + __R uint8_t RESERVED0[20]; /* 0xC - 0x1F: Reserved */ + __RW uint32_t OP_CTRL; /* 0x20: */ + __RW uint32_t OP_CMD; /* 0x24: */ + union { + __RW uint32_t OP_REG0; /* 0x28: */ + __RW uint32_t OP_FIR_MISC; /* 0x28: */ + __RW uint32_t OP_FFT_MISC; /* 0x28: */ + }; + union { + __RW uint32_t OP_REG1; /* 0x2C: */ + __RW uint32_t OP_FIR_MISC1; /* 0x2C: */ + }; + union { + __RW uint32_t OP_REG2; /* 0x30: */ + __RW uint32_t OP_FFT_INRBUF; /* 0x30: */ + }; + union { + __RW uint32_t OP_REG3; /* 0x34: */ + __RW uint32_t OP_FIR_INBUF; /* 0x34: */ + }; + union { + __RW uint32_t OP_REG4; /* 0x38: */ + __RW uint32_t OP_FIR_COEFBUF; /* 0x38: */ + __RW uint32_t OP_FFT_OUTRBUF; /* 0x38: */ + }; + union { + __RW uint32_t OP_REG5; /* 0x3C: */ + __RW uint32_t OP_FIR_OUTBUF; /* 0x3C: */ + }; + __RW uint32_t OP_REG6; /* 0x40: */ + __RW uint32_t OP_REG7; /* 0x44: */ +} FFA_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SFTRST (RW) + * + * software reset the module if asserted to be 1. + * EN is only active after this bit is zero. + */ +#define FFA_CTRL_SFTRST_MASK (0x80000000UL) +#define FFA_CTRL_SFTRST_SHIFT (31U) +#define FFA_CTRL_SFTRST_SET(x) (((uint32_t)(x) << FFA_CTRL_SFTRST_SHIFT) & FFA_CTRL_SFTRST_MASK) +#define FFA_CTRL_SFTRST_GET(x) (((uint32_t)(x) & FFA_CTRL_SFTRST_MASK) >> FFA_CTRL_SFTRST_SHIFT) + +/* + * EN (RW) + * + * Asserted to enable the module + */ +#define FFA_CTRL_EN_MASK (0x1U) +#define FFA_CTRL_EN_SHIFT (0U) +#define FFA_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_CTRL_EN_SHIFT) & FFA_CTRL_EN_MASK) +#define FFA_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_CTRL_EN_MASK) >> FFA_CTRL_EN_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * FIR_OV (ROI) + * + * FIR Overflow err + */ +#define FFA_STATUS_FIR_OV_MASK (0x80U) +#define FFA_STATUS_FIR_OV_SHIFT (7U) +#define FFA_STATUS_FIR_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FIR_OV_MASK) >> FFA_STATUS_FIR_OV_SHIFT) + +/* + * FFT_OV (ROI) + * + * FFT Overflow Err + */ +#define FFA_STATUS_FFT_OV_MASK (0x40U) +#define FFA_STATUS_FFT_OV_SHIFT (6U) +#define FFA_STATUS_FFT_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FFT_OV_MASK) >> FFA_STATUS_FFT_OV_SHIFT) + +/* + * WR_ERR (ROI) + * + * AXI Data Write Error + */ +#define FFA_STATUS_WR_ERR_MASK (0x20U) +#define FFA_STATUS_WR_ERR_SHIFT (5U) +#define FFA_STATUS_WR_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_WR_ERR_MASK) >> FFA_STATUS_WR_ERR_SHIFT) + +/* + * RD_NXT_ERR (ROI) + * + * AXI Read Bus Error for NXT DATA + */ +#define FFA_STATUS_RD_NXT_ERR_MASK (0x10U) +#define FFA_STATUS_RD_NXT_ERR_SHIFT (4U) +#define FFA_STATUS_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_NXT_ERR_MASK) >> FFA_STATUS_RD_NXT_ERR_SHIFT) + +/* + * RD_ERR (ROI) + * + * AXI Data Read Error + */ +#define FFA_STATUS_RD_ERR_MASK (0x8U) +#define FFA_STATUS_RD_ERR_SHIFT (3U) +#define FFA_STATUS_RD_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_ERR_MASK) >> FFA_STATUS_RD_ERR_SHIFT) + +/* + * NXT_CMD_RD_DONE (ROI) + * + * Indicate that next command sequence is already read into the module. + */ +#define FFA_STATUS_NXT_CMD_RD_DONE_MASK (0x2U) +#define FFA_STATUS_NXT_CMD_RD_DONE_SHIFT (1U) +#define FFA_STATUS_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) >> FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) + +/* + * OP_CMD_DONE (ROI) + * + * Indicate that operation cmd is done, and data are available in system memory. + */ +#define FFA_STATUS_OP_CMD_DONE_MASK (0x1U) +#define FFA_STATUS_OP_CMD_DONE_SHIFT (0U) +#define FFA_STATUS_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_OP_CMD_DONE_MASK) >> FFA_STATUS_OP_CMD_DONE_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * WRSV1 (RW) + * + * Reserved + */ +#define FFA_INT_EN_WRSV1_MASK (0xFFFFFF00UL) +#define FFA_INT_EN_WRSV1_SHIFT (8U) +#define FFA_INT_EN_WRSV1_SET(x) (((uint32_t)(x) << FFA_INT_EN_WRSV1_SHIFT) & FFA_INT_EN_WRSV1_MASK) +#define FFA_INT_EN_WRSV1_GET(x) (((uint32_t)(x) & FFA_INT_EN_WRSV1_MASK) >> FFA_INT_EN_WRSV1_SHIFT) + +/* + * FIR_OV (RW) + * + * FIR Overflow err + */ +#define FFA_INT_EN_FIR_OV_MASK (0x80U) +#define FFA_INT_EN_FIR_OV_SHIFT (7U) +#define FFA_INT_EN_FIR_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FIR_OV_SHIFT) & FFA_INT_EN_FIR_OV_MASK) +#define FFA_INT_EN_FIR_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FIR_OV_MASK) >> FFA_INT_EN_FIR_OV_SHIFT) + +/* + * FFT_OV (RW) + * + * FFT Overflow Err + */ +#define FFA_INT_EN_FFT_OV_MASK (0x40U) +#define FFA_INT_EN_FFT_OV_SHIFT (6U) +#define FFA_INT_EN_FFT_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FFT_OV_SHIFT) & FFA_INT_EN_FFT_OV_MASK) +#define FFA_INT_EN_FFT_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FFT_OV_MASK) >> FFA_INT_EN_FFT_OV_SHIFT) + +/* + * WR_ERR (RW) + * + * Enable Data Write Error interrupt + */ +#define FFA_INT_EN_WR_ERR_MASK (0x20U) +#define FFA_INT_EN_WR_ERR_SHIFT (5U) +#define FFA_INT_EN_WR_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_WR_ERR_SHIFT) & FFA_INT_EN_WR_ERR_MASK) +#define FFA_INT_EN_WR_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_WR_ERR_MASK) >> FFA_INT_EN_WR_ERR_SHIFT) + +/* + * RD_NXT_ERR (RW) + * + * Enable Read Bus Error for NXT DATA interrupt + */ +#define FFA_INT_EN_RD_NXT_ERR_MASK (0x10U) +#define FFA_INT_EN_RD_NXT_ERR_SHIFT (4U) +#define FFA_INT_EN_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_NXT_ERR_SHIFT) & FFA_INT_EN_RD_NXT_ERR_MASK) +#define FFA_INT_EN_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_NXT_ERR_MASK) >> FFA_INT_EN_RD_NXT_ERR_SHIFT) + +/* + * RD_ERR (RW) + * + * Enable Data Read Error interrupt + */ +#define FFA_INT_EN_RD_ERR_MASK (0x8U) +#define FFA_INT_EN_RD_ERR_SHIFT (3U) +#define FFA_INT_EN_RD_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_ERR_SHIFT) & FFA_INT_EN_RD_ERR_MASK) +#define FFA_INT_EN_RD_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_ERR_MASK) >> FFA_INT_EN_RD_ERR_SHIFT) + +/* + * NXT_CMD_RD_DONE (RW) + * + * Indicate that next command sequence is already read into the module. + */ +#define FFA_INT_EN_NXT_CMD_RD_DONE_MASK (0x2U) +#define FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT (1U) +#define FFA_INT_EN_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) +#define FFA_INT_EN_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) >> FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) + +/* + * OP_CMD_DONE (RW) + * + * Indicate that operation cmd is done, and data are available in system memory. + */ +#define FFA_INT_EN_OP_CMD_DONE_MASK (0x1U) +#define FFA_INT_EN_OP_CMD_DONE_SHIFT (0U) +#define FFA_INT_EN_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_OP_CMD_DONE_SHIFT) & FFA_INT_EN_OP_CMD_DONE_MASK) +#define FFA_INT_EN_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_OP_CMD_DONE_MASK) >> FFA_INT_EN_OP_CMD_DONE_SHIFT) + +/* Bitfield definition for register: OP_CTRL */ +/* + * NXT_ADDR (RW) + * + * The address for the next command. + * It will be processed after CUR_CMD is executed and done.. + */ +#define FFA_OP_CTRL_NXT_ADDR_MASK (0xFFFFFFFCUL) +#define FFA_OP_CTRL_NXT_ADDR_SHIFT (2U) +#define FFA_OP_CTRL_NXT_ADDR_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_ADDR_SHIFT) & FFA_OP_CTRL_NXT_ADDR_MASK) +#define FFA_OP_CTRL_NXT_ADDR_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_ADDR_MASK) >> FFA_OP_CTRL_NXT_ADDR_SHIFT) + +/* + * NXT_EN (RW) + * + * Whether NXT_CMD is enabled. + * Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. + */ +#define FFA_OP_CTRL_NXT_EN_MASK (0x2U) +#define FFA_OP_CTRL_NXT_EN_SHIFT (1U) +#define FFA_OP_CTRL_NXT_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_EN_SHIFT) & FFA_OP_CTRL_NXT_EN_MASK) +#define FFA_OP_CTRL_NXT_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_EN_MASK) >> FFA_OP_CTRL_NXT_EN_SHIFT) + +/* + * EN (RW) + * + * Whether CUR_CMD is enabled. + * Asserted to enable the CUR_CMD + */ +#define FFA_OP_CTRL_EN_MASK (0x1U) +#define FFA_OP_CTRL_EN_SHIFT (0U) +#define FFA_OP_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_EN_SHIFT) & FFA_OP_CTRL_EN_MASK) +#define FFA_OP_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_EN_MASK) >> FFA_OP_CTRL_EN_SHIFT) + +/* Bitfield definition for register: OP_CMD */ +/* + * CONJ_C (RW) + * + * asserted to have conjuate value for coefs in computation + */ +#define FFA_OP_CMD_CONJ_C_MASK (0x1000000UL) +#define FFA_OP_CMD_CONJ_C_SHIFT (24U) +#define FFA_OP_CMD_CONJ_C_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CONJ_C_SHIFT) & FFA_OP_CMD_CONJ_C_MASK) +#define FFA_OP_CMD_CONJ_C_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CONJ_C_MASK) >> FFA_OP_CMD_CONJ_C_SHIFT) + +/* + * CMD (RW) + * + * The Command Used: + * 0: FIR + * 2: FFT + * Others: Reserved + */ +#define FFA_OP_CMD_CMD_MASK (0xFC0000UL) +#define FFA_OP_CMD_CMD_SHIFT (18U) +#define FFA_OP_CMD_CMD_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CMD_SHIFT) & FFA_OP_CMD_CMD_MASK) +#define FFA_OP_CMD_CMD_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CMD_MASK) >> FFA_OP_CMD_CMD_SHIFT) + +/* + * OUTD_TYPE (RW) + * + * Output data type: + * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 + */ +#define FFA_OP_CMD_OUTD_TYPE_MASK (0x38000UL) +#define FFA_OP_CMD_OUTD_TYPE_SHIFT (15U) +#define FFA_OP_CMD_OUTD_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_OUTD_TYPE_SHIFT) & FFA_OP_CMD_OUTD_TYPE_MASK) +#define FFA_OP_CMD_OUTD_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_OUTD_TYPE_MASK) >> FFA_OP_CMD_OUTD_TYPE_SHIFT) + +/* + * COEF_TYPE (RW) + * + * Coef data type (used for FIR): + * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 + */ +#define FFA_OP_CMD_COEF_TYPE_MASK (0x7000U) +#define FFA_OP_CMD_COEF_TYPE_SHIFT (12U) +#define FFA_OP_CMD_COEF_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_COEF_TYPE_SHIFT) & FFA_OP_CMD_COEF_TYPE_MASK) +#define FFA_OP_CMD_COEF_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_COEF_TYPE_MASK) >> FFA_OP_CMD_COEF_TYPE_SHIFT) + +/* + * IND_TYPE (RW) + * + * Input data type: + * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 + */ +#define FFA_OP_CMD_IND_TYPE_MASK (0xE00U) +#define FFA_OP_CMD_IND_TYPE_SHIFT (9U) +#define FFA_OP_CMD_IND_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_IND_TYPE_SHIFT) & FFA_OP_CMD_IND_TYPE_MASK) +#define FFA_OP_CMD_IND_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_IND_TYPE_MASK) >> FFA_OP_CMD_IND_TYPE_SHIFT) + +/* + * NXT_CMD_LEN (RW) + * + * The length of nxt commands in 32-bit words + */ +#define FFA_OP_CMD_NXT_CMD_LEN_MASK (0xFFU) +#define FFA_OP_CMD_NXT_CMD_LEN_SHIFT (0U) +#define FFA_OP_CMD_NXT_CMD_LEN_SET(x) (((uint32_t)(x) << FFA_OP_CMD_NXT_CMD_LEN_SHIFT) & FFA_OP_CMD_NXT_CMD_LEN_MASK) +#define FFA_OP_CMD_NXT_CMD_LEN_GET(x) (((uint32_t)(x) & FFA_OP_CMD_NXT_CMD_LEN_MASK) >> FFA_OP_CMD_NXT_CMD_LEN_SHIFT) + +/* Bitfield definition for register: OP_REG0 */ +/* + * CT (RW) + * + * Contents + */ +#define FFA_OP_REG0_CT_MASK (0xFFFFFFFFUL) +#define FFA_OP_REG0_CT_SHIFT (0U) +#define FFA_OP_REG0_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG0_CT_SHIFT) & FFA_OP_REG0_CT_MASK) +#define FFA_OP_REG0_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG0_CT_MASK) >> FFA_OP_REG0_CT_SHIFT) + +/* Bitfield definition for register: OP_FIR_MISC */ +/* + * FIR_COEF_TAPS (RW) + * + * Length of FIR coefs + */ +#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK (0x3FFFU) +#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT (0U) +#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) +#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) >> FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) + +/* Bitfield definition for register: OP_FFT_MISC */ +/* + * FFT_LEN (RW) + * + * FFT length + * 0:8, + * ..., + * n:2^(3+n) + */ +#define FFA_OP_FFT_MISC_FFT_LEN_MASK (0x780U) +#define FFA_OP_FFT_MISC_FFT_LEN_SHIFT (7U) +#define FFA_OP_FFT_MISC_FFT_LEN_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_FFT_LEN_SHIFT) & FFA_OP_FFT_MISC_FFT_LEN_MASK) +#define FFA_OP_FFT_MISC_FFT_LEN_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_FFT_LEN_MASK) >> FFA_OP_FFT_MISC_FFT_LEN_SHIFT) + +/* + * IFFT (RW) + * + * Asserted to indicate IFFT + */ +#define FFA_OP_FFT_MISC_IFFT_MASK (0x40U) +#define FFA_OP_FFT_MISC_IFFT_SHIFT (6U) +#define FFA_OP_FFT_MISC_IFFT_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IFFT_SHIFT) & FFA_OP_FFT_MISC_IFFT_MASK) +#define FFA_OP_FFT_MISC_IFFT_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IFFT_MASK) >> FFA_OP_FFT_MISC_IFFT_SHIFT) + +/* + * TMP_BLK (RW) + * + * Memory block for indata. Should be assigned as 1 + */ +#define FFA_OP_FFT_MISC_TMP_BLK_MASK (0xCU) +#define FFA_OP_FFT_MISC_TMP_BLK_SHIFT (2U) +#define FFA_OP_FFT_MISC_TMP_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_TMP_BLK_SHIFT) & FFA_OP_FFT_MISC_TMP_BLK_MASK) +#define FFA_OP_FFT_MISC_TMP_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_TMP_BLK_MASK) >> FFA_OP_FFT_MISC_TMP_BLK_SHIFT) + +/* + * IND_BLK (RW) + * + * Memory block for indata. Should be assigned as 0 + */ +#define FFA_OP_FFT_MISC_IND_BLK_MASK (0x3U) +#define FFA_OP_FFT_MISC_IND_BLK_SHIFT (0U) +#define FFA_OP_FFT_MISC_IND_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IND_BLK_SHIFT) & FFA_OP_FFT_MISC_IND_BLK_MASK) +#define FFA_OP_FFT_MISC_IND_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IND_BLK_MASK) >> FFA_OP_FFT_MISC_IND_BLK_SHIFT) + +/* Bitfield definition for register: OP_REG1 */ +/* + * CT (RW) + * + * Contents + */ +#define FFA_OP_REG1_CT_MASK (0xFFFFFFFFUL) +#define FFA_OP_REG1_CT_SHIFT (0U) +#define FFA_OP_REG1_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG1_CT_SHIFT) & FFA_OP_REG1_CT_MASK) +#define FFA_OP_REG1_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG1_CT_MASK) >> FFA_OP_REG1_CT_SHIFT) + +/* Bitfield definition for register: OP_FIR_MISC1 */ +/* + * OUTD_MEM_BLK (RW) + * + * Should be assigned as 0 + */ +#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK (0x300000UL) +#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT (20U) +#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) +#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) + +/* + * COEF_MEM_BLK (RW) + * + * Should be assigned as 1 + */ +#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK (0xC0000UL) +#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT (18U) +#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) +#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) + +/* + * IND_MEM_BLK (RW) + * + * Should be assigned as 2 + */ +#define FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK (0x30000UL) +#define FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT (16U) +#define FFA_OP_FIR_MISC1_IND_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) +#define FFA_OP_FIR_MISC1_IND_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) + +/* + * FIR_DATA_TAPS (RW) + * + * The input data data length + */ +#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK (0xFFFFU) +#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT (0U) +#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) +#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) >> FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) + +/* Bitfield definition for register: OP_REG2 */ +/* + * CT (RW) + * + * Contents + */ +#define FFA_OP_REG2_CT_MASK (0xFFFFFFFFUL) +#define FFA_OP_REG2_CT_SHIFT (0U) +#define FFA_OP_REG2_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG2_CT_SHIFT) & FFA_OP_REG2_CT_MASK) +#define FFA_OP_REG2_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG2_CT_MASK) >> FFA_OP_REG2_CT_SHIFT) + +/* Bitfield definition for register: OP_FFT_INRBUF */ +/* + * LOC (RW) + * + * The input (real) data buffer pointer + */ +#define FFA_OP_FFT_INRBUF_LOC_MASK (0xFFFFFFFFUL) +#define FFA_OP_FFT_INRBUF_LOC_SHIFT (0U) +#define FFA_OP_FFT_INRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_INRBUF_LOC_SHIFT) & FFA_OP_FFT_INRBUF_LOC_MASK) +#define FFA_OP_FFT_INRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_INRBUF_LOC_MASK) >> FFA_OP_FFT_INRBUF_LOC_SHIFT) + +/* Bitfield definition for register: OP_REG3 */ +/* + * CT (RW) + * + * Contents + */ +#define FFA_OP_REG3_CT_MASK (0xFFFFFFFFUL) +#define FFA_OP_REG3_CT_SHIFT (0U) +#define FFA_OP_REG3_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG3_CT_SHIFT) & FFA_OP_REG3_CT_MASK) +#define FFA_OP_REG3_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG3_CT_MASK) >> FFA_OP_REG3_CT_SHIFT) + +/* Bitfield definition for register: OP_FIR_INBUF */ +/* + * LOC (RW) + * + * The input data buffer pointer + */ +#define FFA_OP_FIR_INBUF_LOC_MASK (0xFFFFFFFFUL) +#define FFA_OP_FIR_INBUF_LOC_SHIFT (0U) +#define FFA_OP_FIR_INBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_INBUF_LOC_SHIFT) & FFA_OP_FIR_INBUF_LOC_MASK) +#define FFA_OP_FIR_INBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_INBUF_LOC_MASK) >> FFA_OP_FIR_INBUF_LOC_SHIFT) + +/* Bitfield definition for register: OP_REG4 */ +/* + * CT (RW) + * + * Contents + */ +#define FFA_OP_REG4_CT_MASK (0xFFFFFFFFUL) +#define FFA_OP_REG4_CT_SHIFT (0U) +#define FFA_OP_REG4_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG4_CT_SHIFT) & FFA_OP_REG4_CT_MASK) +#define FFA_OP_REG4_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG4_CT_MASK) >> FFA_OP_REG4_CT_SHIFT) + +/* Bitfield definition for register: OP_FIR_COEFBUF */ +/* + * LOC (RW) + * + * The coef buf pointer + */ +#define FFA_OP_FIR_COEFBUF_LOC_MASK (0xFFFFFFFFUL) +#define FFA_OP_FIR_COEFBUF_LOC_SHIFT (0U) +#define FFA_OP_FIR_COEFBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_COEFBUF_LOC_SHIFT) & FFA_OP_FIR_COEFBUF_LOC_MASK) +#define FFA_OP_FIR_COEFBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_COEFBUF_LOC_MASK) >> FFA_OP_FIR_COEFBUF_LOC_SHIFT) + +/* Bitfield definition for register: OP_FFT_OUTRBUF */ +/* + * LOC (RW) + * + * The output (real) data buffer pointer + */ +#define FFA_OP_FFT_OUTRBUF_LOC_MASK (0xFFFFFFFFUL) +#define FFA_OP_FFT_OUTRBUF_LOC_SHIFT (0U) +#define FFA_OP_FFT_OUTRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_OUTRBUF_LOC_SHIFT) & FFA_OP_FFT_OUTRBUF_LOC_MASK) +#define FFA_OP_FFT_OUTRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_OUTRBUF_LOC_MASK) >> FFA_OP_FFT_OUTRBUF_LOC_SHIFT) + +/* Bitfield definition for register: OP_REG5 */ +/* + * CT (RW) + * + * Contents + */ +#define FFA_OP_REG5_CT_MASK (0xFFFFFFFFUL) +#define FFA_OP_REG5_CT_SHIFT (0U) +#define FFA_OP_REG5_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG5_CT_SHIFT) & FFA_OP_REG5_CT_MASK) +#define FFA_OP_REG5_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG5_CT_MASK) >> FFA_OP_REG5_CT_SHIFT) + +/* Bitfield definition for register: OP_FIR_OUTBUF */ +/* + * LOC (RW) + * + * The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） + */ +#define FFA_OP_FIR_OUTBUF_LOC_MASK (0xFFFFFFFFUL) +#define FFA_OP_FIR_OUTBUF_LOC_SHIFT (0U) +#define FFA_OP_FIR_OUTBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_OUTBUF_LOC_SHIFT) & FFA_OP_FIR_OUTBUF_LOC_MASK) +#define FFA_OP_FIR_OUTBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_OUTBUF_LOC_MASK) >> FFA_OP_FIR_OUTBUF_LOC_SHIFT) + +/* Bitfield definition for register: OP_REG6 */ +/* + * CT (RW) + * + * Contents + */ +#define FFA_OP_REG6_CT_MASK (0xFFFFFFFFUL) +#define FFA_OP_REG6_CT_SHIFT (0U) +#define FFA_OP_REG6_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG6_CT_SHIFT) & FFA_OP_REG6_CT_MASK) +#define FFA_OP_REG6_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG6_CT_MASK) >> FFA_OP_REG6_CT_SHIFT) + +/* Bitfield definition for register: OP_REG7 */ +/* + * CT (RW) + * + * Contents + */ +#define FFA_OP_REG7_CT_MASK (0xFFFFFFFFUL) +#define FFA_OP_REG7_CT_SHIFT (0U) +#define FFA_OP_REG7_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG7_CT_SHIFT) & FFA_OP_REG7_CT_MASK) +#define FFA_OP_REG7_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG7_CT_MASK) >> FFA_OP_REG7_CT_SHIFT) + + + + +#endif /* HPM_FFA_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h new file mode 100644 index 0000000000..59783d253b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h @@ -0,0 +1,575 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPIO_H +#define HPM_GPIO_H + +typedef struct { + struct { + __RW uint32_t VALUE; /* 0x0: GPIO input value */ + __RW uint32_t SET; /* 0x4: GPIO input set */ + __RW uint32_t CLEAR; /* 0x8: GPIO input clear */ + __RW uint32_t TOGGLE; /* 0xC: GPIO input toggle */ + } DI[16]; + struct { + __RW uint32_t VALUE; /* 0x100: GPIO output value */ + __RW uint32_t SET; /* 0x104: GPIO output set */ + __RW uint32_t CLEAR; /* 0x108: GPIO output clear */ + __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */ + } DO[16]; + struct { + __RW uint32_t VALUE; /* 0x200: GPIO direction value */ + __RW uint32_t SET; /* 0x204: GPIO direction set */ + __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */ + __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */ + } OE[16]; + struct { + __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ + __RW uint32_t SET; /* 0x304: GPIO interrupt flag set */ + __RW uint32_t CLEAR; /* 0x308: GPIO interrupt flag clear */ + __RW uint32_t TOGGLE; /* 0x30C: GPIO interrupt flag toggle */ + } IF[16]; + struct { + __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ + __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */ + __RW uint32_t CLEAR; /* 0x408: GPIO interrupt enable clear */ + __RW uint32_t TOGGLE; /* 0x40C: GPIO interrupt enable toggle */ + } IE[16]; + struct { + __RW uint32_t VALUE; /* 0x500: GPIO interrupt polarity value */ + __RW uint32_t SET; /* 0x504: GPIO interrupt polarity set */ + __RW uint32_t CLEAR; /* 0x508: GPIO interrupt polarity clear */ + __RW uint32_t TOGGLE; /* 0x50C: GPIO interrupt polarity toggle */ + } PL[16]; + struct { + __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */ + __RW uint32_t SET; /* 0x604: GPIO interrupt type set */ + __RW uint32_t CLEAR; /* 0x608: GPIO interrupt type clear */ + __RW uint32_t TOGGLE; /* 0x60C: GPIO interrupt type toggle */ + } TP[16]; + struct { + __RW uint32_t VALUE; /* 0x700: GPIO interrupt asynchronous value */ + __RW uint32_t SET; /* 0x704: GPIO interrupt asynchronous set */ + __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ + __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ + } AS[16]; +} GPIO_Type; + + +/* Bitfield definition for register of struct array DI: VALUE */ +/* + * INPUT (RW) + * + * GPIO input bus value, each bit represents a bus bit + * 0: low level presents on chip pin + * 1: high level presents on chip pin + */ +#define GPIO_DI_VALUE_INPUT_MASK (0xFFFFFFFFUL) +#define GPIO_DI_VALUE_INPUT_SHIFT (0U) +#define GPIO_DI_VALUE_INPUT_SET(x) (((uint32_t)(x) << GPIO_DI_VALUE_INPUT_SHIFT) & GPIO_DI_VALUE_INPUT_MASK) +#define GPIO_DI_VALUE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_VALUE_INPUT_MASK) >> GPIO_DI_VALUE_INPUT_SHIFT) + +/* Bitfield definition for register of struct array DI: SET */ +/* + * INPUT (RW) + * + * GPIO input bus value, each bit represents a bus bit + * 0: low level presents on chip pin + * 1: high level presents on chip pin + */ +#define GPIO_DI_SET_INPUT_MASK (0xFFFFFFFFUL) +#define GPIO_DI_SET_INPUT_SHIFT (0U) +#define GPIO_DI_SET_INPUT_SET(x) (((uint32_t)(x) << GPIO_DI_SET_INPUT_SHIFT) & GPIO_DI_SET_INPUT_MASK) +#define GPIO_DI_SET_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_SET_INPUT_MASK) >> GPIO_DI_SET_INPUT_SHIFT) + +/* Bitfield definition for register of struct array DI: CLEAR */ +/* + * INPUT (RW) + * + * GPIO input bus value, each bit represents a bus bit + * 0: low level presents on chip pin + * 1: high level presents on chip pin + */ +#define GPIO_DI_CLEAR_INPUT_MASK (0xFFFFFFFFUL) +#define GPIO_DI_CLEAR_INPUT_SHIFT (0U) +#define GPIO_DI_CLEAR_INPUT_SET(x) (((uint32_t)(x) << GPIO_DI_CLEAR_INPUT_SHIFT) & GPIO_DI_CLEAR_INPUT_MASK) +#define GPIO_DI_CLEAR_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_CLEAR_INPUT_MASK) >> GPIO_DI_CLEAR_INPUT_SHIFT) + +/* Bitfield definition for register of struct array DI: TOGGLE */ +/* + * INPUT (RW) + * + * GPIO input bus value, each bit represents a bus bit + * 0: low level presents on chip pin + * 1: high level presents on chip pin + */ +#define GPIO_DI_TOGGLE_INPUT_MASK (0xFFFFFFFFUL) +#define GPIO_DI_TOGGLE_INPUT_SHIFT (0U) +#define GPIO_DI_TOGGLE_INPUT_SET(x) (((uint32_t)(x) << GPIO_DI_TOGGLE_INPUT_SHIFT) & GPIO_DI_TOGGLE_INPUT_MASK) +#define GPIO_DI_TOGGLE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_TOGGLE_INPUT_MASK) >> GPIO_DI_TOGGLE_INPUT_SHIFT) + +/* Bitfield definition for register of struct array DO: VALUE */ +/* + * OUTPUT (RW) + * + * GPIO output register value, each bit represents a bus bit + * 0: chip pin output low level when direction is output + * 1: chip pin output high level when direction is output + */ +#define GPIO_DO_VALUE_OUTPUT_MASK (0xFFFFFFFFUL) +#define GPIO_DO_VALUE_OUTPUT_SHIFT (0U) +#define GPIO_DO_VALUE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_VALUE_OUTPUT_SHIFT) & GPIO_DO_VALUE_OUTPUT_MASK) +#define GPIO_DO_VALUE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_VALUE_OUTPUT_MASK) >> GPIO_DO_VALUE_OUTPUT_SHIFT) + +/* Bitfield definition for register of struct array DO: SET */ +/* + * OUTPUT (RW) + * + * GPIO output register value, each bit represents a bus bit + * 0: chip pin output low level when direction is output + * 1: chip pin output high level when direction is output + */ +#define GPIO_DO_SET_OUTPUT_MASK (0xFFFFFFFFUL) +#define GPIO_DO_SET_OUTPUT_SHIFT (0U) +#define GPIO_DO_SET_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_SET_OUTPUT_SHIFT) & GPIO_DO_SET_OUTPUT_MASK) +#define GPIO_DO_SET_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_SET_OUTPUT_MASK) >> GPIO_DO_SET_OUTPUT_SHIFT) + +/* Bitfield definition for register of struct array DO: CLEAR */ +/* + * OUTPUT (RW) + * + * GPIO output register value, each bit represents a bus bit + * 0: chip pin output low level when direction is output + * 1: chip pin output high level when direction is output + */ +#define GPIO_DO_CLEAR_OUTPUT_MASK (0xFFFFFFFFUL) +#define GPIO_DO_CLEAR_OUTPUT_SHIFT (0U) +#define GPIO_DO_CLEAR_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_CLEAR_OUTPUT_SHIFT) & GPIO_DO_CLEAR_OUTPUT_MASK) +#define GPIO_DO_CLEAR_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_CLEAR_OUTPUT_MASK) >> GPIO_DO_CLEAR_OUTPUT_SHIFT) + +/* Bitfield definition for register of struct array DO: TOGGLE */ +/* + * OUTPUT (RW) + * + * GPIO output register value, each bit represents a bus bit + * 0: chip pin output low level when direction is output + * 1: chip pin output high level when direction is output + */ +#define GPIO_DO_TOGGLE_OUTPUT_MASK (0xFFFFFFFFUL) +#define GPIO_DO_TOGGLE_OUTPUT_SHIFT (0U) +#define GPIO_DO_TOGGLE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_TOGGLE_OUTPUT_SHIFT) & GPIO_DO_TOGGLE_OUTPUT_MASK) +#define GPIO_DO_TOGGLE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_TOGGLE_OUTPUT_MASK) >> GPIO_DO_TOGGLE_OUTPUT_SHIFT) + +/* Bitfield definition for register of struct array OE: VALUE */ +/* + * DIRECTION (RW) + * + * GPIO direction, each bit represents a bus bit + * 0: input + * 1: output + */ +#define GPIO_OE_VALUE_DIRECTION_MASK (0xFFFFFFFFUL) +#define GPIO_OE_VALUE_DIRECTION_SHIFT (0U) +#define GPIO_OE_VALUE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_VALUE_DIRECTION_SHIFT) & GPIO_OE_VALUE_DIRECTION_MASK) +#define GPIO_OE_VALUE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_VALUE_DIRECTION_MASK) >> GPIO_OE_VALUE_DIRECTION_SHIFT) + +/* Bitfield definition for register of struct array OE: SET */ +/* + * DIRECTION (RW) + * + * GPIO direction, each bit represents a bus bit + * 0: input + * 1: output + */ +#define GPIO_OE_SET_DIRECTION_MASK (0xFFFFFFFFUL) +#define GPIO_OE_SET_DIRECTION_SHIFT (0U) +#define GPIO_OE_SET_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_SET_DIRECTION_SHIFT) & GPIO_OE_SET_DIRECTION_MASK) +#define GPIO_OE_SET_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_SET_DIRECTION_MASK) >> GPIO_OE_SET_DIRECTION_SHIFT) + +/* Bitfield definition for register of struct array OE: CLEAR */ +/* + * DIRECTION (RW) + * + * GPIO direction, each bit represents a bus bit + * 0: input + * 1: output + */ +#define GPIO_OE_CLEAR_DIRECTION_MASK (0xFFFFFFFFUL) +#define GPIO_OE_CLEAR_DIRECTION_SHIFT (0U) +#define GPIO_OE_CLEAR_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_CLEAR_DIRECTION_SHIFT) & GPIO_OE_CLEAR_DIRECTION_MASK) +#define GPIO_OE_CLEAR_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_CLEAR_DIRECTION_MASK) >> GPIO_OE_CLEAR_DIRECTION_SHIFT) + +/* Bitfield definition for register of struct array OE: TOGGLE */ +/* + * DIRECTION (RW) + * + * GPIO direction, each bit represents a bus bit + * 0: input + * 1: output + */ +#define GPIO_OE_TOGGLE_DIRECTION_MASK (0xFFFFFFFFUL) +#define GPIO_OE_TOGGLE_DIRECTION_SHIFT (0U) +#define GPIO_OE_TOGGLE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_TOGGLE_DIRECTION_SHIFT) & GPIO_OE_TOGGLE_DIRECTION_MASK) +#define GPIO_OE_TOGGLE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_TOGGLE_DIRECTION_MASK) >> GPIO_OE_TOGGLE_DIRECTION_SHIFT) + +/* Bitfield definition for register of struct array IF: VALUE */ +/* + * IRQ_FLAG (W1C) + * + * GPIO interrupt flag, write 1 to clear this flag + * 0: no irq + * 1: irq pending + */ +#define GPIO_IF_VALUE_IRQ_FLAG_MASK (0xFFFFFFFFUL) +#define GPIO_IF_VALUE_IRQ_FLAG_SHIFT (0U) +#define GPIO_IF_VALUE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_VALUE_IRQ_FLAG_SHIFT) & GPIO_IF_VALUE_IRQ_FLAG_MASK) +#define GPIO_IF_VALUE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_VALUE_IRQ_FLAG_MASK) >> GPIO_IF_VALUE_IRQ_FLAG_SHIFT) + +/* Bitfield definition for register of struct array IF: SET */ +/* + * IRQ_FLAG (RW) + * + * GPIO interrupt flag, write 1 to clear this flag + * 0: no irq + * 1: irq pending + */ +#define GPIO_IF_SET_IRQ_FLAG_MASK (0xFFFFFFFFUL) +#define GPIO_IF_SET_IRQ_FLAG_SHIFT (0U) +#define GPIO_IF_SET_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_SET_IRQ_FLAG_SHIFT) & GPIO_IF_SET_IRQ_FLAG_MASK) +#define GPIO_IF_SET_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_SET_IRQ_FLAG_MASK) >> GPIO_IF_SET_IRQ_FLAG_SHIFT) + +/* Bitfield definition for register of struct array IF: CLEAR */ +/* + * IRQ_FLAG (RW) + * + * GPIO interrupt flag, write 1 to clear this flag + * 0: no irq + * 1: irq pending + */ +#define GPIO_IF_CLEAR_IRQ_FLAG_MASK (0xFFFFFFFFUL) +#define GPIO_IF_CLEAR_IRQ_FLAG_SHIFT (0U) +#define GPIO_IF_CLEAR_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_CLEAR_IRQ_FLAG_SHIFT) & GPIO_IF_CLEAR_IRQ_FLAG_MASK) +#define GPIO_IF_CLEAR_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_CLEAR_IRQ_FLAG_MASK) >> GPIO_IF_CLEAR_IRQ_FLAG_SHIFT) + +/* Bitfield definition for register of struct array IF: TOGGLE */ +/* + * IRQ_FLAG (RW) + * + * GPIO interrupt flag, write 1 to clear this flag + * 0: no irq + * 1: irq pending + */ +#define GPIO_IF_TOGGLE_IRQ_FLAG_MASK (0xFFFFFFFFUL) +#define GPIO_IF_TOGGLE_IRQ_FLAG_SHIFT (0U) +#define GPIO_IF_TOGGLE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_TOGGLE_IRQ_FLAG_SHIFT) & GPIO_IF_TOGGLE_IRQ_FLAG_MASK) +#define GPIO_IF_TOGGLE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_TOGGLE_IRQ_FLAG_MASK) >> GPIO_IF_TOGGLE_IRQ_FLAG_SHIFT) + +/* Bitfield definition for register of struct array IE: VALUE */ +/* + * IRQ_EN (RW) + * + * GPIO interrupt enable, each bit represents a bus bit + * 0: irq is disabled + * 1: irq is enable + */ +#define GPIO_IE_VALUE_IRQ_EN_MASK (0xFFFFFFFFUL) +#define GPIO_IE_VALUE_IRQ_EN_SHIFT (0U) +#define GPIO_IE_VALUE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_VALUE_IRQ_EN_SHIFT) & GPIO_IE_VALUE_IRQ_EN_MASK) +#define GPIO_IE_VALUE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_VALUE_IRQ_EN_MASK) >> GPIO_IE_VALUE_IRQ_EN_SHIFT) + +/* Bitfield definition for register of struct array IE: SET */ +/* + * IRQ_EN (RW) + * + * GPIO interrupt enable, each bit represents a bus bit + * 0: irq is disabled + * 1: irq is enable + */ +#define GPIO_IE_SET_IRQ_EN_MASK (0xFFFFFFFFUL) +#define GPIO_IE_SET_IRQ_EN_SHIFT (0U) +#define GPIO_IE_SET_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_SET_IRQ_EN_SHIFT) & GPIO_IE_SET_IRQ_EN_MASK) +#define GPIO_IE_SET_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_SET_IRQ_EN_MASK) >> GPIO_IE_SET_IRQ_EN_SHIFT) + +/* Bitfield definition for register of struct array IE: CLEAR */ +/* + * IRQ_EN (RW) + * + * GPIO interrupt enable, each bit represents a bus bit + * 0: irq is disabled + * 1: irq is enable + */ +#define GPIO_IE_CLEAR_IRQ_EN_MASK (0xFFFFFFFFUL) +#define GPIO_IE_CLEAR_IRQ_EN_SHIFT (0U) +#define GPIO_IE_CLEAR_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_CLEAR_IRQ_EN_SHIFT) & GPIO_IE_CLEAR_IRQ_EN_MASK) +#define GPIO_IE_CLEAR_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_CLEAR_IRQ_EN_MASK) >> GPIO_IE_CLEAR_IRQ_EN_SHIFT) + +/* Bitfield definition for register of struct array IE: TOGGLE */ +/* + * IRQ_EN (RW) + * + * GPIO interrupt enable, each bit represents a bus bit + * 0: irq is disabled + * 1: irq is enable + */ +#define GPIO_IE_TOGGLE_IRQ_EN_MASK (0xFFFFFFFFUL) +#define GPIO_IE_TOGGLE_IRQ_EN_SHIFT (0U) +#define GPIO_IE_TOGGLE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_TOGGLE_IRQ_EN_SHIFT) & GPIO_IE_TOGGLE_IRQ_EN_MASK) +#define GPIO_IE_TOGGLE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_TOGGLE_IRQ_EN_MASK) >> GPIO_IE_TOGGLE_IRQ_EN_SHIFT) + +/* Bitfield definition for register of struct array PL: VALUE */ +/* + * IRQ_POL (RW) + * + * GPIO interrupt polarity, each bit represents a bus bit + * 0: irq is high level or rising edge + * 1: irq is low level or falling edge + */ +#define GPIO_PL_VALUE_IRQ_POL_MASK (0xFFFFFFFFUL) +#define GPIO_PL_VALUE_IRQ_POL_SHIFT (0U) +#define GPIO_PL_VALUE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_VALUE_IRQ_POL_SHIFT) & GPIO_PL_VALUE_IRQ_POL_MASK) +#define GPIO_PL_VALUE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_VALUE_IRQ_POL_MASK) >> GPIO_PL_VALUE_IRQ_POL_SHIFT) + +/* Bitfield definition for register of struct array PL: SET */ +/* + * IRQ_POL (RW) + * + * GPIO interrupt polarity, each bit represents a bus bit + * 0: irq is high level or rising edge + * 1: irq is low level or falling edge + */ +#define GPIO_PL_SET_IRQ_POL_MASK (0xFFFFFFFFUL) +#define GPIO_PL_SET_IRQ_POL_SHIFT (0U) +#define GPIO_PL_SET_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_SET_IRQ_POL_SHIFT) & GPIO_PL_SET_IRQ_POL_MASK) +#define GPIO_PL_SET_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_SET_IRQ_POL_MASK) >> GPIO_PL_SET_IRQ_POL_SHIFT) + +/* Bitfield definition for register of struct array PL: CLEAR */ +/* + * IRQ_POL (RW) + * + * GPIO interrupt polarity, each bit represents a bus bit + * 0: irq is high level or rising edge + * 1: irq is low level or falling edge + */ +#define GPIO_PL_CLEAR_IRQ_POL_MASK (0xFFFFFFFFUL) +#define GPIO_PL_CLEAR_IRQ_POL_SHIFT (0U) +#define GPIO_PL_CLEAR_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_CLEAR_IRQ_POL_SHIFT) & GPIO_PL_CLEAR_IRQ_POL_MASK) +#define GPIO_PL_CLEAR_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_CLEAR_IRQ_POL_MASK) >> GPIO_PL_CLEAR_IRQ_POL_SHIFT) + +/* Bitfield definition for register of struct array PL: TOGGLE */ +/* + * IRQ_POL (RW) + * + * GPIO interrupt polarity, each bit represents a bus bit + * 0: irq is high level or rising edge + * 1: irq is low level or falling edge + */ +#define GPIO_PL_TOGGLE_IRQ_POL_MASK (0xFFFFFFFFUL) +#define GPIO_PL_TOGGLE_IRQ_POL_SHIFT (0U) +#define GPIO_PL_TOGGLE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_TOGGLE_IRQ_POL_SHIFT) & GPIO_PL_TOGGLE_IRQ_POL_MASK) +#define GPIO_PL_TOGGLE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_TOGGLE_IRQ_POL_MASK) >> GPIO_PL_TOGGLE_IRQ_POL_SHIFT) + +/* Bitfield definition for register of struct array TP: VALUE */ +/* + * IRQ_TYPE (RW) + * + * GPIO interrupt type, each bit represents a bus bit + * 0: irq is triggered by level + * 1: irq is triggered by edge + */ +#define GPIO_TP_VALUE_IRQ_TYPE_MASK (0xFFFFFFFFUL) +#define GPIO_TP_VALUE_IRQ_TYPE_SHIFT (0U) +#define GPIO_TP_VALUE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_VALUE_IRQ_TYPE_SHIFT) & GPIO_TP_VALUE_IRQ_TYPE_MASK) +#define GPIO_TP_VALUE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_VALUE_IRQ_TYPE_MASK) >> GPIO_TP_VALUE_IRQ_TYPE_SHIFT) + +/* Bitfield definition for register of struct array TP: SET */ +/* + * IRQ_TYPE (RW) + * + * GPIO interrupt type, each bit represents a bus bit + * 0: irq is triggered by level + * 1: irq is triggered by edge + */ +#define GPIO_TP_SET_IRQ_TYPE_MASK (0xFFFFFFFFUL) +#define GPIO_TP_SET_IRQ_TYPE_SHIFT (0U) +#define GPIO_TP_SET_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_SET_IRQ_TYPE_SHIFT) & GPIO_TP_SET_IRQ_TYPE_MASK) +#define GPIO_TP_SET_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_SET_IRQ_TYPE_MASK) >> GPIO_TP_SET_IRQ_TYPE_SHIFT) + +/* Bitfield definition for register of struct array TP: CLEAR */ +/* + * IRQ_TYPE (RW) + * + * GPIO interrupt type, each bit represents a bus bit + * 0: irq is triggered by level + * 1: irq is triggered by edge + */ +#define GPIO_TP_CLEAR_IRQ_TYPE_MASK (0xFFFFFFFFUL) +#define GPIO_TP_CLEAR_IRQ_TYPE_SHIFT (0U) +#define GPIO_TP_CLEAR_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) +#define GPIO_TP_CLEAR_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) >> GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) + +/* Bitfield definition for register of struct array TP: TOGGLE */ +/* + * IRQ_TYPE (RW) + * + * GPIO interrupt type, each bit represents a bus bit + * 0: irq is triggered by level + * 1: irq is triggered by edge + */ +#define GPIO_TP_TOGGLE_IRQ_TYPE_MASK (0xFFFFFFFFUL) +#define GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT (0U) +#define GPIO_TP_TOGGLE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) +#define GPIO_TP_TOGGLE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) >> GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) + +/* Bitfield definition for register of struct array AS: VALUE */ +/* + * IRQ_ASYNC (RW) + * + * GPIO interrupt asynchronous, each bit represents a bus bit + * 0: irq is triggered base on system clock + * 1: irq is triggered combinational + * Note: combinational interrupt is sensitive to environment noise + */ +#define GPIO_AS_VALUE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) +#define GPIO_AS_VALUE_IRQ_ASYNC_SHIFT (0U) +#define GPIO_AS_VALUE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) +#define GPIO_AS_VALUE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) >> GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) + +/* Bitfield definition for register of struct array AS: SET */ +/* + * IRQ_ASYNC (RW) + * + * GPIO interrupt asynchronous, each bit represents a bus bit + * 0: irq is triggered base on system clock + * 1: irq is triggered combinational + * Note: combinational interrupt is sensitive to environment noise + */ +#define GPIO_AS_SET_IRQ_ASYNC_MASK (0xFFFFFFFFUL) +#define GPIO_AS_SET_IRQ_ASYNC_SHIFT (0U) +#define GPIO_AS_SET_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_SET_IRQ_ASYNC_SHIFT) & GPIO_AS_SET_IRQ_ASYNC_MASK) +#define GPIO_AS_SET_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_SET_IRQ_ASYNC_MASK) >> GPIO_AS_SET_IRQ_ASYNC_SHIFT) + +/* Bitfield definition for register of struct array AS: CLEAR */ +/* + * IRQ_ASYNC (RW) + * + * GPIO interrupt asynchronous, each bit represents a bus bit + * 0: irq is triggered base on system clock + * 1: irq is triggered combinational + * Note: combinational interrupt is sensitive to environment noise + */ +#define GPIO_AS_CLEAR_IRQ_ASYNC_MASK (0xFFFFFFFFUL) +#define GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT (0U) +#define GPIO_AS_CLEAR_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) +#define GPIO_AS_CLEAR_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) >> GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) + +/* Bitfield definition for register of struct array AS: TOGGLE */ +/* + * IRQ_ASYNC (RW) + * + * GPIO interrupt asynchronous, each bit represents a bus bit + * 0: irq is triggered base on system clock + * 1: irq is triggered combinational + * Note: combinational interrupt is sensitive to environment noise + */ +#define GPIO_AS_TOGGLE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) +#define GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT (0U) +#define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) +#define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) + + + +/* DI register group index macro definition */ +#define GPIO_DI_GPIOA (0UL) +#define GPIO_DI_GPIOB (1UL) +#define GPIO_DI_GPIOC (2UL) +#define GPIO_DI_GPIOD (3UL) +#define GPIO_DI_GPIOE (4UL) +#define GPIO_DI_GPIOF (5UL) +#define GPIO_DI_GPIOX (13UL) +#define GPIO_DI_GPIOY (14UL) +#define GPIO_DI_GPIOZ (15UL) + +/* DO register group index macro definition */ +#define GPIO_DO_GPIOA (0UL) +#define GPIO_DO_GPIOB (1UL) +#define GPIO_DO_GPIOC (2UL) +#define GPIO_DO_GPIOD (3UL) +#define GPIO_DO_GPIOE (4UL) +#define GPIO_DO_GPIOF (5UL) +#define GPIO_DO_GPIOX (13UL) +#define GPIO_DO_GPIOY (14UL) +#define GPIO_DO_GPIOZ (15UL) + +/* OE register group index macro definition */ +#define GPIO_OE_GPIOA (0UL) +#define GPIO_OE_GPIOB (1UL) +#define GPIO_OE_GPIOC (2UL) +#define GPIO_OE_GPIOD (3UL) +#define GPIO_OE_GPIOE (4UL) +#define GPIO_OE_GPIOF (5UL) +#define GPIO_OE_GPIOX (13UL) +#define GPIO_OE_GPIOY (14UL) +#define GPIO_OE_GPIOZ (15UL) + +/* IF register group index macro definition */ +#define GPIO_IF_GPIOA (0UL) +#define GPIO_IF_GPIOB (1UL) +#define GPIO_IF_GPIOC (2UL) +#define GPIO_IF_GPIOD (3UL) +#define GPIO_IF_GPIOE (4UL) +#define GPIO_IF_GPIOF (5UL) +#define GPIO_IF_GPIOX (13UL) +#define GPIO_IF_GPIOY (14UL) +#define GPIO_IF_GPIOZ (15UL) + +/* IE register group index macro definition */ +#define GPIO_IE_GPIOA (0UL) +#define GPIO_IE_GPIOB (1UL) +#define GPIO_IE_GPIOC (2UL) +#define GPIO_IE_GPIOD (3UL) +#define GPIO_IE_GPIOE (4UL) +#define GPIO_IE_GPIOF (5UL) +#define GPIO_IE_GPIOX (13UL) +#define GPIO_IE_GPIOY (14UL) +#define GPIO_IE_GPIOZ (15UL) + +/* PL register group index macro definition */ +#define GPIO_PL_GPIOA (0UL) +#define GPIO_PL_GPIOB (1UL) +#define GPIO_PL_GPIOC (2UL) +#define GPIO_PL_GPIOD (3UL) +#define GPIO_PL_GPIOE (4UL) +#define GPIO_PL_GPIOF (5UL) +#define GPIO_PL_GPIOX (13UL) +#define GPIO_PL_GPIOY (14UL) +#define GPIO_PL_GPIOZ (15UL) + +/* TP register group index macro definition */ +#define GPIO_TP_GPIOA (0UL) +#define GPIO_TP_GPIOB (1UL) +#define GPIO_TP_GPIOC (2UL) +#define GPIO_TP_GPIOD (3UL) +#define GPIO_TP_GPIOE (4UL) +#define GPIO_TP_GPIOF (5UL) +#define GPIO_TP_GPIOX (13UL) +#define GPIO_TP_GPIOY (14UL) +#define GPIO_TP_GPIOZ (15UL) + +/* AS register group index macro definition */ +#define GPIO_AS_GPIOA (0UL) +#define GPIO_AS_GPIOB (1UL) +#define GPIO_AS_GPIOC (2UL) +#define GPIO_AS_GPIOD (3UL) +#define GPIO_AS_GPIOE (4UL) +#define GPIO_AS_GPIOF (5UL) +#define GPIO_AS_GPIOX (13UL) +#define GPIO_AS_GPIOY (14UL) +#define GPIO_AS_GPIOZ (15UL) + + +#endif /* HPM_GPIO_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gptmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gptmr_regs.h new file mode 100644 index 0000000000..52f5c93478 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gptmr_regs.h @@ -0,0 +1,607 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPTMR_H +#define HPM_GPTMR_H + +typedef struct { + struct { + __RW uint32_t CR; /* 0x0: Control Register */ + __RW uint32_t CMP[2]; /* 0x4 - 0x8: Comparator register 0 */ + __RW uint32_t RLD; /* 0xC: Reload register */ + __RW uint32_t CNTUPTVAL; /* 0x10: Counter update value register */ + __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ + __R uint32_t CAPPOS; /* 0x20: Capture rising edge register */ + __R uint32_t CAPNEG; /* 0x24: Capture falling edge register */ + __R uint32_t CAPPRD; /* 0x28: PWM period measure register */ + __R uint32_t CAPDTY; /* 0x2C: PWM duty cycle measure register */ + __R uint32_t CNT; /* 0x30: Counter */ + __R uint8_t RESERVED1[12]; /* 0x34 - 0x3F: Reserved */ + } CHANNEL[4]; + __R uint8_t RESERVED0[256]; /* 0x100 - 0x1FF: Reserved */ + __RW uint32_t SR; /* 0x200: Status register */ + __RW uint32_t IRQEN; /* 0x204: Interrupt request enable register */ + __RW uint32_t GCR; /* 0x208: Global control register */ +} GPTMR_Type; + + +/* Bitfield definition for register of struct array CHANNEL: CR */ +/* + * CNTUPT (WO) + * + * 1- update counter to new value as CNTUPTVAL + * This bit will be auto cleared after 1 cycle + */ +#define GPTMR_CHANNEL_CR_CNTUPT_MASK (0x80000000UL) +#define GPTMR_CHANNEL_CR_CNTUPT_SHIFT (31U) +#define GPTMR_CHANNEL_CR_CNTUPT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) +#define GPTMR_CHANNEL_CR_CNTUPT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) + +/* + * CNTRST (RW) + * + * 1- reset counter + */ +#define GPTMR_CHANNEL_CR_CNTRST_MASK (0x4000U) +#define GPTMR_CHANNEL_CR_CNTRST_SHIFT (14U) +#define GPTMR_CHANNEL_CR_CNTRST_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTRST_SHIFT) & GPTMR_CHANNEL_CR_CNTRST_MASK) +#define GPTMR_CHANNEL_CR_CNTRST_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTRST_MASK) >> GPTMR_CHANNEL_CR_CNTRST_SHIFT) + +/* + * SYNCFLW (RW) + * + * 1- enable this channel to reset counter to reload(RLD) together with its previous channel. + * This bit is not valid for channel 0. + */ +#define GPTMR_CHANNEL_CR_SYNCFLW_MASK (0x2000U) +#define GPTMR_CHANNEL_CR_SYNCFLW_SHIFT (13U) +#define GPTMR_CHANNEL_CR_SYNCFLW_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) +#define GPTMR_CHANNEL_CR_SYNCFLW_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) >> GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) + +/* + * SYNCIFEN (RW) + * + * 1- SYNCI is valid on its falling edge + */ +#define GPTMR_CHANNEL_CR_SYNCIFEN_MASK (0x1000U) +#define GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT (12U) +#define GPTMR_CHANNEL_CR_SYNCIFEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) +#define GPTMR_CHANNEL_CR_SYNCIFEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) >> GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) + +/* + * SYNCIREN (RW) + * + * 1- SYNCI is valid on its rising edge + */ +#define GPTMR_CHANNEL_CR_SYNCIREN_MASK (0x800U) +#define GPTMR_CHANNEL_CR_SYNCIREN_SHIFT (11U) +#define GPTMR_CHANNEL_CR_SYNCIREN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) +#define GPTMR_CHANNEL_CR_SYNCIREN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) >> GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) + +/* + * CEN (RW) + * + * 1- counter enable + */ +#define GPTMR_CHANNEL_CR_CEN_MASK (0x400U) +#define GPTMR_CHANNEL_CR_CEN_SHIFT (10U) +#define GPTMR_CHANNEL_CR_CEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CEN_SHIFT) & GPTMR_CHANNEL_CR_CEN_MASK) +#define GPTMR_CHANNEL_CR_CEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CEN_MASK) >> GPTMR_CHANNEL_CR_CEN_SHIFT) + +/* + * CMPINIT (RW) + * + * Output compare initial poliarity + * 1- The channel output initial level is high + * 0- The channel output initial level is low + * User should set this bit before set CMPEN to 1. + */ +#define GPTMR_CHANNEL_CR_CMPINIT_MASK (0x200U) +#define GPTMR_CHANNEL_CR_CMPINIT_SHIFT (9U) +#define GPTMR_CHANNEL_CR_CMPINIT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPINIT_SHIFT) & GPTMR_CHANNEL_CR_CMPINIT_MASK) +#define GPTMR_CHANNEL_CR_CMPINIT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPINIT_MASK) >> GPTMR_CHANNEL_CR_CMPINIT_SHIFT) + +/* + * CMPEN (RW) + * + * 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + */ +#define GPTMR_CHANNEL_CR_CMPEN_MASK (0x100U) +#define GPTMR_CHANNEL_CR_CMPEN_SHIFT (8U) +#define GPTMR_CHANNEL_CR_CMPEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPEN_SHIFT) & GPTMR_CHANNEL_CR_CMPEN_MASK) +#define GPTMR_CHANNEL_CR_CMPEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPEN_MASK) >> GPTMR_CHANNEL_CR_CMPEN_SHIFT) + +/* + * DMASEL (RW) + * + * select one of DMA request: + * 00- RLD flag, counter reload; + * 01- Input signal toggle captured + * 10- CMP0 flag + * 11- CMP1 flag + */ +#define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) +#define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) +#define GPTMR_CHANNEL_CR_DMASEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMASEL_SHIFT) & GPTMR_CHANNEL_CR_DMASEL_MASK) +#define GPTMR_CHANNEL_CR_DMASEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMASEL_MASK) >> GPTMR_CHANNEL_CR_DMASEL_SHIFT) + +/* + * DMAEN (RW) + * + * 1- enable dma + */ +#define GPTMR_CHANNEL_CR_DMAEN_MASK (0x20U) +#define GPTMR_CHANNEL_CR_DMAEN_SHIFT (5U) +#define GPTMR_CHANNEL_CR_DMAEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMAEN_SHIFT) & GPTMR_CHANNEL_CR_DMAEN_MASK) +#define GPTMR_CHANNEL_CR_DMAEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMAEN_MASK) >> GPTMR_CHANNEL_CR_DMAEN_SHIFT) + +/* + * SWSYNCIEN (RW) + * + * 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + */ +#define GPTMR_CHANNEL_CR_SWSYNCIEN_MASK (0x10U) +#define GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT (4U) +#define GPTMR_CHANNEL_CR_SWSYNCIEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) +#define GPTMR_CHANNEL_CR_SWSYNCIEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) >> GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) + +/* + * DBGPAUSE (RW) + * + * 1- counter will pause if chip is in debug mode + */ +#define GPTMR_CHANNEL_CR_DBGPAUSE_MASK (0x8U) +#define GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT (3U) +#define GPTMR_CHANNEL_CR_DBGPAUSE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) +#define GPTMR_CHANNEL_CR_DBGPAUSE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) >> GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) + +/* + * CAPMODE (RW) + * + * This bitfield define the input capture mode + * 100: width measure mode, timer will calculate the input signal period and duty cycle + * 011: capture at both rising edge and falling edge + * 010: capture at falling edge + * 001: capture at rising edge + * 000: No capture + */ +#define GPTMR_CHANNEL_CR_CAPMODE_MASK (0x7U) +#define GPTMR_CHANNEL_CR_CAPMODE_SHIFT (0U) +#define GPTMR_CHANNEL_CR_CAPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CAPMODE_SHIFT) & GPTMR_CHANNEL_CR_CAPMODE_MASK) +#define GPTMR_CHANNEL_CR_CAPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CAPMODE_MASK) >> GPTMR_CHANNEL_CR_CAPMODE_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CMP0 */ +/* + * CMP (RW) + * + * compare value 0 + */ +#define GPTMR_CMP_CMP_MASK (0xFFFFFFFFUL) +#define GPTMR_CMP_CMP_SHIFT (0U) +#define GPTMR_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CMP_CMP_SHIFT) & GPTMR_CMP_CMP_MASK) +#define GPTMR_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CMP_CMP_MASK) >> GPTMR_CMP_CMP_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: RLD */ +/* + * RLD (RW) + * + * reload value + */ +#define GPTMR_CHANNEL_RLD_RLD_MASK (0xFFFFFFFFUL) +#define GPTMR_CHANNEL_RLD_RLD_SHIFT (0U) +#define GPTMR_CHANNEL_RLD_RLD_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_RLD_RLD_SHIFT) & GPTMR_CHANNEL_RLD_RLD_MASK) +#define GPTMR_CHANNEL_RLD_RLD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_RLD_RLD_MASK) >> GPTMR_CHANNEL_RLD_RLD_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CNTUPTVAL */ +/* + * CNTUPTVAL (RW) + * + * counter will be set to this value when software write cntupt bit in CR + */ +#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK (0xFFFFFFFFUL) +#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT (0U) +#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) +#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) >> GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CAPPOS */ +/* + * CAPPOS (RO) + * + * This register contains the counter value captured at input signal rising edge + */ +#define GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK (0xFFFFFFFFUL) +#define GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT (0U) +#define GPTMR_CHANNEL_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CAPNEG */ +/* + * CAPNEG (RO) + * + * This register contains the counter value captured at input signal falling edge + */ +#define GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) +#define GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT (0U) +#define GPTMR_CHANNEL_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CAPPRD */ +/* + * CAPPRD (RO) + * + * This register contains the input signal period when channel is configured to input capture measure mode. + */ +#define GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK (0xFFFFFFFFUL) +#define GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT (0U) +#define GPTMR_CHANNEL_CAPPRD_CAPPRD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CAPDTY */ +/* + * MEAS_HIGH (RO) + * + * This register contains the input signal duty cycle when channel is configured to input capture measure mode. + */ +#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK (0xFFFFFFFFUL) +#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT (0U) +#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT) + +/* Bitfield definition for register of struct array CHANNEL: CNT */ +/* + * COUNTER (RO) + * + * 32 bit counter value + */ +#define GPTMR_CHANNEL_CNT_COUNTER_MASK (0xFFFFFFFFUL) +#define GPTMR_CHANNEL_CNT_COUNTER_SHIFT (0U) +#define GPTMR_CHANNEL_CNT_COUNTER_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT) + +/* Bitfield definition for register: SR */ +/* + * CH3CMP1F (W1C) + * + * channel 3 compare value 1 match flag + */ +#define GPTMR_SR_CH3CMP1F_MASK (0x8000U) +#define GPTMR_SR_CH3CMP1F_SHIFT (15U) +#define GPTMR_SR_CH3CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP1F_SHIFT) & GPTMR_SR_CH3CMP1F_MASK) +#define GPTMR_SR_CH3CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP1F_MASK) >> GPTMR_SR_CH3CMP1F_SHIFT) + +/* + * CH3CMP0F (W1C) + * + * channel 3 compare value 1 match flag + */ +#define GPTMR_SR_CH3CMP0F_MASK (0x4000U) +#define GPTMR_SR_CH3CMP0F_SHIFT (14U) +#define GPTMR_SR_CH3CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP0F_SHIFT) & GPTMR_SR_CH3CMP0F_MASK) +#define GPTMR_SR_CH3CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP0F_MASK) >> GPTMR_SR_CH3CMP0F_SHIFT) + +/* + * CH3CAPF (W1C) + * + * channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + */ +#define GPTMR_SR_CH3CAPF_MASK (0x2000U) +#define GPTMR_SR_CH3CAPF_SHIFT (13U) +#define GPTMR_SR_CH3CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CAPF_SHIFT) & GPTMR_SR_CH3CAPF_MASK) +#define GPTMR_SR_CH3CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CAPF_MASK) >> GPTMR_SR_CH3CAPF_SHIFT) + +/* + * CH3RLDF (W1C) + * + * channel 3 counter reload flag + */ +#define GPTMR_SR_CH3RLDF_MASK (0x1000U) +#define GPTMR_SR_CH3RLDF_SHIFT (12U) +#define GPTMR_SR_CH3RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3RLDF_SHIFT) & GPTMR_SR_CH3RLDF_MASK) +#define GPTMR_SR_CH3RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3RLDF_MASK) >> GPTMR_SR_CH3RLDF_SHIFT) + +/* + * CH2CMP1F (W1C) + * + * channel 2 compare value 1 match flag + */ +#define GPTMR_SR_CH2CMP1F_MASK (0x800U) +#define GPTMR_SR_CH2CMP1F_SHIFT (11U) +#define GPTMR_SR_CH2CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP1F_SHIFT) & GPTMR_SR_CH2CMP1F_MASK) +#define GPTMR_SR_CH2CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP1F_MASK) >> GPTMR_SR_CH2CMP1F_SHIFT) + +/* + * CH2CMP0F (W1C) + * + * channel 2 compare value 1 match flag + */ +#define GPTMR_SR_CH2CMP0F_MASK (0x400U) +#define GPTMR_SR_CH2CMP0F_SHIFT (10U) +#define GPTMR_SR_CH2CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP0F_SHIFT) & GPTMR_SR_CH2CMP0F_MASK) +#define GPTMR_SR_CH2CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP0F_MASK) >> GPTMR_SR_CH2CMP0F_SHIFT) + +/* + * CH2CAPF (W1C) + * + * channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + */ +#define GPTMR_SR_CH2CAPF_MASK (0x200U) +#define GPTMR_SR_CH2CAPF_SHIFT (9U) +#define GPTMR_SR_CH2CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CAPF_SHIFT) & GPTMR_SR_CH2CAPF_MASK) +#define GPTMR_SR_CH2CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CAPF_MASK) >> GPTMR_SR_CH2CAPF_SHIFT) + +/* + * CH2RLDF (W1C) + * + * channel 2 counter reload flag + */ +#define GPTMR_SR_CH2RLDF_MASK (0x100U) +#define GPTMR_SR_CH2RLDF_SHIFT (8U) +#define GPTMR_SR_CH2RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2RLDF_SHIFT) & GPTMR_SR_CH2RLDF_MASK) +#define GPTMR_SR_CH2RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2RLDF_MASK) >> GPTMR_SR_CH2RLDF_SHIFT) + +/* + * CH1CMP1F (W1C) + * + * channel 1 compare value 1 match flag + */ +#define GPTMR_SR_CH1CMP1F_MASK (0x80U) +#define GPTMR_SR_CH1CMP1F_SHIFT (7U) +#define GPTMR_SR_CH1CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP1F_SHIFT) & GPTMR_SR_CH1CMP1F_MASK) +#define GPTMR_SR_CH1CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP1F_MASK) >> GPTMR_SR_CH1CMP1F_SHIFT) + +/* + * CH1CMP0F (W1C) + * + * channel 1 compare value 1 match flag + */ +#define GPTMR_SR_CH1CMP0F_MASK (0x40U) +#define GPTMR_SR_CH1CMP0F_SHIFT (6U) +#define GPTMR_SR_CH1CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP0F_SHIFT) & GPTMR_SR_CH1CMP0F_MASK) +#define GPTMR_SR_CH1CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP0F_MASK) >> GPTMR_SR_CH1CMP0F_SHIFT) + +/* + * CH1CAPF (W1C) + * + * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + */ +#define GPTMR_SR_CH1CAPF_MASK (0x20U) +#define GPTMR_SR_CH1CAPF_SHIFT (5U) +#define GPTMR_SR_CH1CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CAPF_SHIFT) & GPTMR_SR_CH1CAPF_MASK) +#define GPTMR_SR_CH1CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CAPF_MASK) >> GPTMR_SR_CH1CAPF_SHIFT) + +/* + * CH1RLDF (W1C) + * + * channel 1 counter reload flag + */ +#define GPTMR_SR_CH1RLDF_MASK (0x10U) +#define GPTMR_SR_CH1RLDF_SHIFT (4U) +#define GPTMR_SR_CH1RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1RLDF_SHIFT) & GPTMR_SR_CH1RLDF_MASK) +#define GPTMR_SR_CH1RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1RLDF_MASK) >> GPTMR_SR_CH1RLDF_SHIFT) + +/* + * CH0CMP1F (W1C) + * + * channel 1 compare value 1 match flag + */ +#define GPTMR_SR_CH0CMP1F_MASK (0x8U) +#define GPTMR_SR_CH0CMP1F_SHIFT (3U) +#define GPTMR_SR_CH0CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP1F_SHIFT) & GPTMR_SR_CH0CMP1F_MASK) +#define GPTMR_SR_CH0CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP1F_MASK) >> GPTMR_SR_CH0CMP1F_SHIFT) + +/* + * CH0CMP0F (W1C) + * + * channel 1 compare value 1 match flag + */ +#define GPTMR_SR_CH0CMP0F_MASK (0x4U) +#define GPTMR_SR_CH0CMP0F_SHIFT (2U) +#define GPTMR_SR_CH0CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP0F_SHIFT) & GPTMR_SR_CH0CMP0F_MASK) +#define GPTMR_SR_CH0CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP0F_MASK) >> GPTMR_SR_CH0CMP0F_SHIFT) + +/* + * CH0CAPF (W1C) + * + * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + */ +#define GPTMR_SR_CH0CAPF_MASK (0x2U) +#define GPTMR_SR_CH0CAPF_SHIFT (1U) +#define GPTMR_SR_CH0CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CAPF_SHIFT) & GPTMR_SR_CH0CAPF_MASK) +#define GPTMR_SR_CH0CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CAPF_MASK) >> GPTMR_SR_CH0CAPF_SHIFT) + +/* + * CH0RLDF (W1C) + * + * channel 1 counter reload flag + */ +#define GPTMR_SR_CH0RLDF_MASK (0x1U) +#define GPTMR_SR_CH0RLDF_SHIFT (0U) +#define GPTMR_SR_CH0RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0RLDF_SHIFT) & GPTMR_SR_CH0RLDF_MASK) +#define GPTMR_SR_CH0RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0RLDF_MASK) >> GPTMR_SR_CH0RLDF_SHIFT) + +/* Bitfield definition for register: IRQEN */ +/* + * CH3CMP1EN (RW) + * + * 1- generate interrupt request when ch3cmp1f flag is set + */ +#define GPTMR_IRQEN_CH3CMP1EN_MASK (0x8000U) +#define GPTMR_IRQEN_CH3CMP1EN_SHIFT (15U) +#define GPTMR_IRQEN_CH3CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP1EN_SHIFT) & GPTMR_IRQEN_CH3CMP1EN_MASK) +#define GPTMR_IRQEN_CH3CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP1EN_MASK) >> GPTMR_IRQEN_CH3CMP1EN_SHIFT) + +/* + * CH3CMP0EN (RW) + * + * 1- generate interrupt request when ch3cmp0f flag is set + */ +#define GPTMR_IRQEN_CH3CMP0EN_MASK (0x4000U) +#define GPTMR_IRQEN_CH3CMP0EN_SHIFT (14U) +#define GPTMR_IRQEN_CH3CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP0EN_SHIFT) & GPTMR_IRQEN_CH3CMP0EN_MASK) +#define GPTMR_IRQEN_CH3CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP0EN_MASK) >> GPTMR_IRQEN_CH3CMP0EN_SHIFT) + +/* + * CH3CAPEN (RW) + * + * 1- generate interrupt request when ch3capf flag is set + */ +#define GPTMR_IRQEN_CH3CAPEN_MASK (0x2000U) +#define GPTMR_IRQEN_CH3CAPEN_SHIFT (13U) +#define GPTMR_IRQEN_CH3CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CAPEN_SHIFT) & GPTMR_IRQEN_CH3CAPEN_MASK) +#define GPTMR_IRQEN_CH3CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CAPEN_MASK) >> GPTMR_IRQEN_CH3CAPEN_SHIFT) + +/* + * CH3RLDEN (RW) + * + * 1- generate interrupt request when ch3rldf flag is set + */ +#define GPTMR_IRQEN_CH3RLDEN_MASK (0x1000U) +#define GPTMR_IRQEN_CH3RLDEN_SHIFT (12U) +#define GPTMR_IRQEN_CH3RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3RLDEN_SHIFT) & GPTMR_IRQEN_CH3RLDEN_MASK) +#define GPTMR_IRQEN_CH3RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3RLDEN_MASK) >> GPTMR_IRQEN_CH3RLDEN_SHIFT) + +/* + * CH2CMP1EN (RW) + * + * 1- generate interrupt request when ch2cmp1f flag is set + */ +#define GPTMR_IRQEN_CH2CMP1EN_MASK (0x800U) +#define GPTMR_IRQEN_CH2CMP1EN_SHIFT (11U) +#define GPTMR_IRQEN_CH2CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP1EN_SHIFT) & GPTMR_IRQEN_CH2CMP1EN_MASK) +#define GPTMR_IRQEN_CH2CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP1EN_MASK) >> GPTMR_IRQEN_CH2CMP1EN_SHIFT) + +/* + * CH2CMP0EN (RW) + * + * 1- generate interrupt request when ch2cmp0f flag is set + */ +#define GPTMR_IRQEN_CH2CMP0EN_MASK (0x400U) +#define GPTMR_IRQEN_CH2CMP0EN_SHIFT (10U) +#define GPTMR_IRQEN_CH2CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP0EN_SHIFT) & GPTMR_IRQEN_CH2CMP0EN_MASK) +#define GPTMR_IRQEN_CH2CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP0EN_MASK) >> GPTMR_IRQEN_CH2CMP0EN_SHIFT) + +/* + * CH2CAPEN (RW) + * + * 1- generate interrupt request when ch2capf flag is set + */ +#define GPTMR_IRQEN_CH2CAPEN_MASK (0x200U) +#define GPTMR_IRQEN_CH2CAPEN_SHIFT (9U) +#define GPTMR_IRQEN_CH2CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CAPEN_SHIFT) & GPTMR_IRQEN_CH2CAPEN_MASK) +#define GPTMR_IRQEN_CH2CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CAPEN_MASK) >> GPTMR_IRQEN_CH2CAPEN_SHIFT) + +/* + * CH2RLDEN (RW) + * + * 1- generate interrupt request when ch2rldf flag is set + */ +#define GPTMR_IRQEN_CH2RLDEN_MASK (0x100U) +#define GPTMR_IRQEN_CH2RLDEN_SHIFT (8U) +#define GPTMR_IRQEN_CH2RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2RLDEN_SHIFT) & GPTMR_IRQEN_CH2RLDEN_MASK) +#define GPTMR_IRQEN_CH2RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2RLDEN_MASK) >> GPTMR_IRQEN_CH2RLDEN_SHIFT) + +/* + * CH1CMP1EN (RW) + * + * 1- generate interrupt request when ch1cmp1f flag is set + */ +#define GPTMR_IRQEN_CH1CMP1EN_MASK (0x80U) +#define GPTMR_IRQEN_CH1CMP1EN_SHIFT (7U) +#define GPTMR_IRQEN_CH1CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP1EN_SHIFT) & GPTMR_IRQEN_CH1CMP1EN_MASK) +#define GPTMR_IRQEN_CH1CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP1EN_MASK) >> GPTMR_IRQEN_CH1CMP1EN_SHIFT) + +/* + * CH1CMP0EN (RW) + * + * 1- generate interrupt request when ch1cmp0f flag is set + */ +#define GPTMR_IRQEN_CH1CMP0EN_MASK (0x40U) +#define GPTMR_IRQEN_CH1CMP0EN_SHIFT (6U) +#define GPTMR_IRQEN_CH1CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP0EN_SHIFT) & GPTMR_IRQEN_CH1CMP0EN_MASK) +#define GPTMR_IRQEN_CH1CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP0EN_MASK) >> GPTMR_IRQEN_CH1CMP0EN_SHIFT) + +/* + * CH1CAPEN (RW) + * + * 1- generate interrupt request when ch1capf flag is set + */ +#define GPTMR_IRQEN_CH1CAPEN_MASK (0x20U) +#define GPTMR_IRQEN_CH1CAPEN_SHIFT (5U) +#define GPTMR_IRQEN_CH1CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CAPEN_SHIFT) & GPTMR_IRQEN_CH1CAPEN_MASK) +#define GPTMR_IRQEN_CH1CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CAPEN_MASK) >> GPTMR_IRQEN_CH1CAPEN_SHIFT) + +/* + * CH1RLDEN (RW) + * + * 1- generate interrupt request when ch1rldf flag is set + */ +#define GPTMR_IRQEN_CH1RLDEN_MASK (0x10U) +#define GPTMR_IRQEN_CH1RLDEN_SHIFT (4U) +#define GPTMR_IRQEN_CH1RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1RLDEN_SHIFT) & GPTMR_IRQEN_CH1RLDEN_MASK) +#define GPTMR_IRQEN_CH1RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1RLDEN_MASK) >> GPTMR_IRQEN_CH1RLDEN_SHIFT) + +/* + * CH0CMP1EN (RW) + * + * 1- generate interrupt request when ch0cmp1f flag is set + */ +#define GPTMR_IRQEN_CH0CMP1EN_MASK (0x8U) +#define GPTMR_IRQEN_CH0CMP1EN_SHIFT (3U) +#define GPTMR_IRQEN_CH0CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP1EN_SHIFT) & GPTMR_IRQEN_CH0CMP1EN_MASK) +#define GPTMR_IRQEN_CH0CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP1EN_MASK) >> GPTMR_IRQEN_CH0CMP1EN_SHIFT) + +/* + * CH0CMP0EN (RW) + * + * 1- generate interrupt request when ch0cmp0f flag is set + */ +#define GPTMR_IRQEN_CH0CMP0EN_MASK (0x4U) +#define GPTMR_IRQEN_CH0CMP0EN_SHIFT (2U) +#define GPTMR_IRQEN_CH0CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP0EN_SHIFT) & GPTMR_IRQEN_CH0CMP0EN_MASK) +#define GPTMR_IRQEN_CH0CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP0EN_MASK) >> GPTMR_IRQEN_CH0CMP0EN_SHIFT) + +/* + * CH0CAPEN (RW) + * + * 1- generate interrupt request when ch0capf flag is set + */ +#define GPTMR_IRQEN_CH0CAPEN_MASK (0x2U) +#define GPTMR_IRQEN_CH0CAPEN_SHIFT (1U) +#define GPTMR_IRQEN_CH0CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CAPEN_SHIFT) & GPTMR_IRQEN_CH0CAPEN_MASK) +#define GPTMR_IRQEN_CH0CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CAPEN_MASK) >> GPTMR_IRQEN_CH0CAPEN_SHIFT) + +/* + * CH0RLDEN (RW) + * + * 1- generate interrupt request when ch0rldf flag is set + */ +#define GPTMR_IRQEN_CH0RLDEN_MASK (0x1U) +#define GPTMR_IRQEN_CH0RLDEN_SHIFT (0U) +#define GPTMR_IRQEN_CH0RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0RLDEN_SHIFT) & GPTMR_IRQEN_CH0RLDEN_MASK) +#define GPTMR_IRQEN_CH0RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0RLDEN_MASK) >> GPTMR_IRQEN_CH0RLDEN_SHIFT) + +/* Bitfield definition for register: GCR */ +/* + * SWSYNCT (RW) + * + * set this bitfield to trigger software coutner sync event + */ +#define GPTMR_GCR_SWSYNCT_MASK (0xFU) +#define GPTMR_GCR_SWSYNCT_SHIFT (0U) +#define GPTMR_GCR_SWSYNCT_SET(x) (((uint32_t)(x) << GPTMR_GCR_SWSYNCT_SHIFT) & GPTMR_GCR_SWSYNCT_MASK) +#define GPTMR_GCR_SWSYNCT_GET(x) (((uint32_t)(x) & GPTMR_GCR_SWSYNCT_MASK) >> GPTMR_GCR_SWSYNCT_SHIFT) + + + +/* CMP register group index macro definition */ +#define GPTMR_CHANNEL_CMP_CMP0 (0UL) +#define GPTMR_CHANNEL_CMP_CMP1 (1UL) + +/* CHANNEL register group index macro definition */ +#define GPTMR_CHANNEL_CH0 (0UL) +#define GPTMR_CHANNEL_CH1 (1UL) +#define GPTMR_CHANNEL_CH2 (2UL) +#define GPTMR_CHANNEL_CH3 (3UL) + + +#endif /* HPM_GPTMR_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_hall_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_hall_regs.h new file mode 100644 index 0000000000..52dae76c15 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_hall_regs.h @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_HALL_H +#define HPM_HALL_H + +typedef struct { + __RW uint32_t CR; /* 0x0: Control Register */ + __RW uint32_t PHCFG; /* 0x4: Phase configure register */ + __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ + __RW uint32_t UVWCFG; /* 0xC: U,V,W configure register */ + __RW uint32_t TRGOEN; /* 0x10: Trigger output enable register */ + __RW uint32_t READEN; /* 0x14: Read event enable register */ + __R uint8_t RESERVED0[12]; /* 0x18 - 0x23: Reserved */ + __RW uint32_t DMAEN; /* 0x24: DMA enable register */ + __RW uint32_t SR; /* 0x28: Status register */ + __RW uint32_t IRQEN; /* 0x2C: Interrupt request enable register */ + struct { + __R uint32_t W; /* 0x30: W counter */ + __R uint32_t V; /* 0x34: V counter */ + __R uint32_t U; /* 0x38: U counter */ + __R uint32_t TMR; /* 0x3C: Timer counter */ + } COUNT[4]; + struct { + __R uint32_t HIS0; /* 0x70: history register 0 */ + __R uint32_t HIS1; /* 0x74: history register 1 */ + } HIS[3]; +} HALL_Type; + + +/* Bitfield definition for register: CR */ +/* + * READ (WO) + * + * 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + */ +#define HALL_CR_READ_MASK (0x80000000UL) +#define HALL_CR_READ_SHIFT (31U) +#define HALL_CR_READ_SET(x) (((uint32_t)(x) << HALL_CR_READ_SHIFT) & HALL_CR_READ_MASK) +#define HALL_CR_READ_GET(x) (((uint32_t)(x) & HALL_CR_READ_MASK) >> HALL_CR_READ_SHIFT) + +/* + * SNAPEN (RW) + * + * 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert + */ +#define HALL_CR_SNAPEN_MASK (0x800U) +#define HALL_CR_SNAPEN_SHIFT (11U) +#define HALL_CR_SNAPEN_SET(x) (((uint32_t)(x) << HALL_CR_SNAPEN_SHIFT) & HALL_CR_SNAPEN_MASK) +#define HALL_CR_SNAPEN_GET(x) (((uint32_t)(x) & HALL_CR_SNAPEN_MASK) >> HALL_CR_SNAPEN_SHIFT) + +/* + * RSTCNT (RW) + * + * set to reset all counter and related snapshots + */ +#define HALL_CR_RSTCNT_MASK (0x10U) +#define HALL_CR_RSTCNT_SHIFT (4U) +#define HALL_CR_RSTCNT_SET(x) (((uint32_t)(x) << HALL_CR_RSTCNT_SHIFT) & HALL_CR_RSTCNT_MASK) +#define HALL_CR_RSTCNT_GET(x) (((uint32_t)(x) & HALL_CR_RSTCNT_MASK) >> HALL_CR_RSTCNT_SHIFT) + +/* Bitfield definition for register: PHCFG */ +/* + * DLYSEL (RW) + * + * This bit select delay start time: + * 1- start counting delay after pre-trigger + * 0- start counting delay after u,v,w toggle + */ +#define HALL_PHCFG_DLYSEL_MASK (0x80000000UL) +#define HALL_PHCFG_DLYSEL_SHIFT (31U) +#define HALL_PHCFG_DLYSEL_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYSEL_SHIFT) & HALL_PHCFG_DLYSEL_MASK) +#define HALL_PHCFG_DLYSEL_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYSEL_MASK) >> HALL_PHCFG_DLYSEL_SHIFT) + +/* + * DLYCNT (RW) + * + * delay clock cycles number + */ +#define HALL_PHCFG_DLYCNT_MASK (0xFFFFFFUL) +#define HALL_PHCFG_DLYCNT_SHIFT (0U) +#define HALL_PHCFG_DLYCNT_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYCNT_SHIFT) & HALL_PHCFG_DLYCNT_MASK) +#define HALL_PHCFG_DLYCNT_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYCNT_MASK) >> HALL_PHCFG_DLYCNT_SHIFT) + +/* Bitfield definition for register: WDGCFG */ +/* + * WDGEN (RW) + * + * 1- enable wdog counter + */ +#define HALL_WDGCFG_WDGEN_MASK (0x80000000UL) +#define HALL_WDGCFG_WDGEN_SHIFT (31U) +#define HALL_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGEN_SHIFT) & HALL_WDGCFG_WDGEN_MASK) +#define HALL_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGEN_MASK) >> HALL_WDGCFG_WDGEN_SHIFT) + +/* + * WDGTO (RW) + * + * watch dog timeout value + */ +#define HALL_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) +#define HALL_WDGCFG_WDGTO_SHIFT (0U) +#define HALL_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGTO_SHIFT) & HALL_WDGCFG_WDGTO_MASK) +#define HALL_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGTO_MASK) >> HALL_WDGCFG_WDGTO_SHIFT) + +/* Bitfield definition for register: UVWCFG */ +/* + * PRECNT (RW) + * + * the clock cycle number which the pre flag will set before the next uvw transition + */ +#define HALL_UVWCFG_PRECNT_MASK (0xFFFFFFUL) +#define HALL_UVWCFG_PRECNT_SHIFT (0U) +#define HALL_UVWCFG_PRECNT_SET(x) (((uint32_t)(x) << HALL_UVWCFG_PRECNT_SHIFT) & HALL_UVWCFG_PRECNT_MASK) +#define HALL_UVWCFG_PRECNT_GET(x) (((uint32_t)(x) & HALL_UVWCFG_PRECNT_MASK) >> HALL_UVWCFG_PRECNT_SHIFT) + +/* Bitfield definition for register: TRGOEN */ +/* + * WDGEN (RW) + * + * 1- enable trigger output when wdg flag set + */ +#define HALL_TRGOEN_WDGEN_MASK (0x80000000UL) +#define HALL_TRGOEN_WDGEN_SHIFT (31U) +#define HALL_TRGOEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WDGEN_SHIFT) & HALL_TRGOEN_WDGEN_MASK) +#define HALL_TRGOEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WDGEN_MASK) >> HALL_TRGOEN_WDGEN_SHIFT) + +/* + * PHUPTEN (RW) + * + * 1- enable trigger output when phupt flag set + */ +#define HALL_TRGOEN_PHUPTEN_MASK (0x40000000UL) +#define HALL_TRGOEN_PHUPTEN_SHIFT (30U) +#define HALL_TRGOEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHUPTEN_SHIFT) & HALL_TRGOEN_PHUPTEN_MASK) +#define HALL_TRGOEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHUPTEN_MASK) >> HALL_TRGOEN_PHUPTEN_SHIFT) + +/* + * PHPREEN (RW) + * + * 1- enable trigger output when phpre flag set + */ +#define HALL_TRGOEN_PHPREEN_MASK (0x20000000UL) +#define HALL_TRGOEN_PHPREEN_SHIFT (29U) +#define HALL_TRGOEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHPREEN_SHIFT) & HALL_TRGOEN_PHPREEN_MASK) +#define HALL_TRGOEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHPREEN_MASK) >> HALL_TRGOEN_PHPREEN_SHIFT) + +/* + * PHDLYEN (RW) + * + * 1- enable trigger output when phdly flag set + */ +#define HALL_TRGOEN_PHDLYEN_MASK (0x10000000UL) +#define HALL_TRGOEN_PHDLYEN_SHIFT (28U) +#define HALL_TRGOEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHDLYEN_SHIFT) & HALL_TRGOEN_PHDLYEN_MASK) +#define HALL_TRGOEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHDLYEN_MASK) >> HALL_TRGOEN_PHDLYEN_SHIFT) + +/* + * UFEN (RW) + * + * 1- enable trigger output when u flag set + */ +#define HALL_TRGOEN_UFEN_MASK (0x800000UL) +#define HALL_TRGOEN_UFEN_SHIFT (23U) +#define HALL_TRGOEN_UFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_UFEN_SHIFT) & HALL_TRGOEN_UFEN_MASK) +#define HALL_TRGOEN_UFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_UFEN_MASK) >> HALL_TRGOEN_UFEN_SHIFT) + +/* + * VFEN (RW) + * + * 1- enable trigger output when v flag set + */ +#define HALL_TRGOEN_VFEN_MASK (0x400000UL) +#define HALL_TRGOEN_VFEN_SHIFT (22U) +#define HALL_TRGOEN_VFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_VFEN_SHIFT) & HALL_TRGOEN_VFEN_MASK) +#define HALL_TRGOEN_VFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_VFEN_MASK) >> HALL_TRGOEN_VFEN_SHIFT) + +/* + * WFEN (RW) + * + * 1- enable trigger output when w flag set + */ +#define HALL_TRGOEN_WFEN_MASK (0x200000UL) +#define HALL_TRGOEN_WFEN_SHIFT (21U) +#define HALL_TRGOEN_WFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WFEN_SHIFT) & HALL_TRGOEN_WFEN_MASK) +#define HALL_TRGOEN_WFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WFEN_MASK) >> HALL_TRGOEN_WFEN_SHIFT) + +/* Bitfield definition for register: READEN */ +/* + * WDGEN (RW) + * + * 1- load counters to their read registers when wdg flag set + */ +#define HALL_READEN_WDGEN_MASK (0x80000000UL) +#define HALL_READEN_WDGEN_SHIFT (31U) +#define HALL_READEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_READEN_WDGEN_SHIFT) & HALL_READEN_WDGEN_MASK) +#define HALL_READEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_READEN_WDGEN_MASK) >> HALL_READEN_WDGEN_SHIFT) + +/* + * PHUPTEN (RW) + * + * 1- load counters to their read registers when phupt flag set + */ +#define HALL_READEN_PHUPTEN_MASK (0x40000000UL) +#define HALL_READEN_PHUPTEN_SHIFT (30U) +#define HALL_READEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHUPTEN_SHIFT) & HALL_READEN_PHUPTEN_MASK) +#define HALL_READEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHUPTEN_MASK) >> HALL_READEN_PHUPTEN_SHIFT) + +/* + * PHPREEN (RW) + * + * 1- load counters to their read registers when phpre flag set + */ +#define HALL_READEN_PHPREEN_MASK (0x20000000UL) +#define HALL_READEN_PHPREEN_SHIFT (29U) +#define HALL_READEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHPREEN_SHIFT) & HALL_READEN_PHPREEN_MASK) +#define HALL_READEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHPREEN_MASK) >> HALL_READEN_PHPREEN_SHIFT) + +/* + * PHDLYEN (RW) + * + * 1- load counters to their read registers when phdly flag set + */ +#define HALL_READEN_PHDLYEN_MASK (0x10000000UL) +#define HALL_READEN_PHDLYEN_SHIFT (28U) +#define HALL_READEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHDLYEN_SHIFT) & HALL_READEN_PHDLYEN_MASK) +#define HALL_READEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHDLYEN_MASK) >> HALL_READEN_PHDLYEN_SHIFT) + +/* + * UFEN (RW) + * + * 1- load counters to their read registers when u flag set + */ +#define HALL_READEN_UFEN_MASK (0x800000UL) +#define HALL_READEN_UFEN_SHIFT (23U) +#define HALL_READEN_UFEN_SET(x) (((uint32_t)(x) << HALL_READEN_UFEN_SHIFT) & HALL_READEN_UFEN_MASK) +#define HALL_READEN_UFEN_GET(x) (((uint32_t)(x) & HALL_READEN_UFEN_MASK) >> HALL_READEN_UFEN_SHIFT) + +/* + * VFEN (RW) + * + * 1- load counters to their read registers when v flag set + */ +#define HALL_READEN_VFEN_MASK (0x400000UL) +#define HALL_READEN_VFEN_SHIFT (22U) +#define HALL_READEN_VFEN_SET(x) (((uint32_t)(x) << HALL_READEN_VFEN_SHIFT) & HALL_READEN_VFEN_MASK) +#define HALL_READEN_VFEN_GET(x) (((uint32_t)(x) & HALL_READEN_VFEN_MASK) >> HALL_READEN_VFEN_SHIFT) + +/* + * WFEN (RW) + * + * 1- load counters to their read registers when w flag set + */ +#define HALL_READEN_WFEN_MASK (0x200000UL) +#define HALL_READEN_WFEN_SHIFT (21U) +#define HALL_READEN_WFEN_SET(x) (((uint32_t)(x) << HALL_READEN_WFEN_SHIFT) & HALL_READEN_WFEN_MASK) +#define HALL_READEN_WFEN_GET(x) (((uint32_t)(x) & HALL_READEN_WFEN_MASK) >> HALL_READEN_WFEN_SHIFT) + +/* Bitfield definition for register: DMAEN */ +/* + * WDGEN (RW) + * + * 1- generate dma request when wdg flag set + */ +#define HALL_DMAEN_WDGEN_MASK (0x80000000UL) +#define HALL_DMAEN_WDGEN_SHIFT (31U) +#define HALL_DMAEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WDGEN_SHIFT) & HALL_DMAEN_WDGEN_MASK) +#define HALL_DMAEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WDGEN_MASK) >> HALL_DMAEN_WDGEN_SHIFT) + +/* + * PHUPTEN (RW) + * + * 1- generate dma request when phupt flag set + */ +#define HALL_DMAEN_PHUPTEN_MASK (0x40000000UL) +#define HALL_DMAEN_PHUPTEN_SHIFT (30U) +#define HALL_DMAEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHUPTEN_SHIFT) & HALL_DMAEN_PHUPTEN_MASK) +#define HALL_DMAEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHUPTEN_MASK) >> HALL_DMAEN_PHUPTEN_SHIFT) + +/* + * PHPREEN (RW) + * + * 1- generate dma request when phpre flag set + */ +#define HALL_DMAEN_PHPREEN_MASK (0x20000000UL) +#define HALL_DMAEN_PHPREEN_SHIFT (29U) +#define HALL_DMAEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHPREEN_SHIFT) & HALL_DMAEN_PHPREEN_MASK) +#define HALL_DMAEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHPREEN_MASK) >> HALL_DMAEN_PHPREEN_SHIFT) + +/* + * PHDLYEN (RW) + * + * 1- generate dma request when phdly flag set + */ +#define HALL_DMAEN_PHDLYEN_MASK (0x10000000UL) +#define HALL_DMAEN_PHDLYEN_SHIFT (28U) +#define HALL_DMAEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHDLYEN_SHIFT) & HALL_DMAEN_PHDLYEN_MASK) +#define HALL_DMAEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHDLYEN_MASK) >> HALL_DMAEN_PHDLYEN_SHIFT) + +/* + * UFEN (RW) + * + * 1- generate dma request when u flag set + */ +#define HALL_DMAEN_UFEN_MASK (0x800000UL) +#define HALL_DMAEN_UFEN_SHIFT (23U) +#define HALL_DMAEN_UFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_UFEN_SHIFT) & HALL_DMAEN_UFEN_MASK) +#define HALL_DMAEN_UFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_UFEN_MASK) >> HALL_DMAEN_UFEN_SHIFT) + +/* + * VFEN (RW) + * + * 1- generate dma request when v flag set + */ +#define HALL_DMAEN_VFEN_MASK (0x400000UL) +#define HALL_DMAEN_VFEN_SHIFT (22U) +#define HALL_DMAEN_VFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_VFEN_SHIFT) & HALL_DMAEN_VFEN_MASK) +#define HALL_DMAEN_VFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_VFEN_MASK) >> HALL_DMAEN_VFEN_SHIFT) + +/* + * WFEN (RW) + * + * 1- generate dma request when w flag set + */ +#define HALL_DMAEN_WFEN_MASK (0x200000UL) +#define HALL_DMAEN_WFEN_SHIFT (21U) +#define HALL_DMAEN_WFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WFEN_SHIFT) & HALL_DMAEN_WFEN_MASK) +#define HALL_DMAEN_WFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WFEN_MASK) >> HALL_DMAEN_WFEN_SHIFT) + +/* Bitfield definition for register: SR */ +/* + * WDGF (RW) + * + * watchdog count timeout flag + */ +#define HALL_SR_WDGF_MASK (0x80000000UL) +#define HALL_SR_WDGF_SHIFT (31U) +#define HALL_SR_WDGF_SET(x) (((uint32_t)(x) << HALL_SR_WDGF_SHIFT) & HALL_SR_WDGF_MASK) +#define HALL_SR_WDGF_GET(x) (((uint32_t)(x) & HALL_SR_WDGF_MASK) >> HALL_SR_WDGF_SHIFT) + +/* + * PHUPTF (RW) + * + * phase update flag, will set when any of u, v, w signal toggle + */ +#define HALL_SR_PHUPTF_MASK (0x40000000UL) +#define HALL_SR_PHUPTF_SHIFT (30U) +#define HALL_SR_PHUPTF_SET(x) (((uint32_t)(x) << HALL_SR_PHUPTF_SHIFT) & HALL_SR_PHUPTF_MASK) +#define HALL_SR_PHUPTF_GET(x) (((uint32_t)(x) & HALL_SR_PHUPTF_MASK) >> HALL_SR_PHUPTF_SHIFT) + +/* + * PHPREF (RW) + * + * phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle + */ +#define HALL_SR_PHPREF_MASK (0x20000000UL) +#define HALL_SR_PHPREF_SHIFT (29U) +#define HALL_SR_PHPREF_SET(x) (((uint32_t)(x) << HALL_SR_PHPREF_SHIFT) & HALL_SR_PHPREF_MASK) +#define HALL_SR_PHPREF_GET(x) (((uint32_t)(x) & HALL_SR_PHPREF_MASK) >> HALL_SR_PHPREF_SHIFT) + +/* + * PHDLYF (RW) + * + * phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting + */ +#define HALL_SR_PHDLYF_MASK (0x10000000UL) +#define HALL_SR_PHDLYF_SHIFT (28U) +#define HALL_SR_PHDLYF_SET(x) (((uint32_t)(x) << HALL_SR_PHDLYF_SHIFT) & HALL_SR_PHDLYF_MASK) +#define HALL_SR_PHDLYF_GET(x) (((uint32_t)(x) & HALL_SR_PHDLYF_MASK) >> HALL_SR_PHDLYF_SHIFT) + +/* + * UF (RW) + * + * u flag, will set when u signal toggle + */ +#define HALL_SR_UF_MASK (0x800000UL) +#define HALL_SR_UF_SHIFT (23U) +#define HALL_SR_UF_SET(x) (((uint32_t)(x) << HALL_SR_UF_SHIFT) & HALL_SR_UF_MASK) +#define HALL_SR_UF_GET(x) (((uint32_t)(x) & HALL_SR_UF_MASK) >> HALL_SR_UF_SHIFT) + +/* + * VF (RW) + * + * v flag, will set when v signal toggle + */ +#define HALL_SR_VF_MASK (0x400000UL) +#define HALL_SR_VF_SHIFT (22U) +#define HALL_SR_VF_SET(x) (((uint32_t)(x) << HALL_SR_VF_SHIFT) & HALL_SR_VF_MASK) +#define HALL_SR_VF_GET(x) (((uint32_t)(x) & HALL_SR_VF_MASK) >> HALL_SR_VF_SHIFT) + +/* + * WF (RW) + * + * w flag, will set when w signal toggle + */ +#define HALL_SR_WF_MASK (0x200000UL) +#define HALL_SR_WF_SHIFT (21U) +#define HALL_SR_WF_SET(x) (((uint32_t)(x) << HALL_SR_WF_SHIFT) & HALL_SR_WF_MASK) +#define HALL_SR_WF_GET(x) (((uint32_t)(x) & HALL_SR_WF_MASK) >> HALL_SR_WF_SHIFT) + +/* Bitfield definition for register: IRQEN */ +/* + * WDGIE (RW) + * + * 1- generate interrupt request when wdg flag set + */ +#define HALL_IRQEN_WDGIE_MASK (0x80000000UL) +#define HALL_IRQEN_WDGIE_SHIFT (31U) +#define HALL_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WDGIE_SHIFT) & HALL_IRQEN_WDGIE_MASK) +#define HALL_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WDGIE_MASK) >> HALL_IRQEN_WDGIE_SHIFT) + +/* + * PHUPTIE (RW) + * + * 1- generate interrupt request when phupt flag set + */ +#define HALL_IRQEN_PHUPTIE_MASK (0x40000000UL) +#define HALL_IRQEN_PHUPTIE_SHIFT (30U) +#define HALL_IRQEN_PHUPTIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHUPTIE_SHIFT) & HALL_IRQEN_PHUPTIE_MASK) +#define HALL_IRQEN_PHUPTIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHUPTIE_MASK) >> HALL_IRQEN_PHUPTIE_SHIFT) + +/* + * PHPREIE (RW) + * + * 1- generate interrupt request when phpre flag set + */ +#define HALL_IRQEN_PHPREIE_MASK (0x20000000UL) +#define HALL_IRQEN_PHPREIE_SHIFT (29U) +#define HALL_IRQEN_PHPREIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHPREIE_SHIFT) & HALL_IRQEN_PHPREIE_MASK) +#define HALL_IRQEN_PHPREIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHPREIE_MASK) >> HALL_IRQEN_PHPREIE_SHIFT) + +/* + * PHDLYIE (RW) + * + * 1- generate interrupt request when phdly flag set + */ +#define HALL_IRQEN_PHDLYIE_MASK (0x10000000UL) +#define HALL_IRQEN_PHDLYIE_SHIFT (28U) +#define HALL_IRQEN_PHDLYIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHDLYIE_SHIFT) & HALL_IRQEN_PHDLYIE_MASK) +#define HALL_IRQEN_PHDLYIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHDLYIE_MASK) >> HALL_IRQEN_PHDLYIE_SHIFT) + +/* + * UFIE (RW) + * + * 1- generate interrupt request when u flag set + */ +#define HALL_IRQEN_UFIE_MASK (0x800000UL) +#define HALL_IRQEN_UFIE_SHIFT (23U) +#define HALL_IRQEN_UFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_UFIE_SHIFT) & HALL_IRQEN_UFIE_MASK) +#define HALL_IRQEN_UFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_UFIE_MASK) >> HALL_IRQEN_UFIE_SHIFT) + +/* + * VFIE (RW) + * + * 1- generate interrupt request when v flag set + */ +#define HALL_IRQEN_VFIE_MASK (0x400000UL) +#define HALL_IRQEN_VFIE_SHIFT (22U) +#define HALL_IRQEN_VFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_VFIE_SHIFT) & HALL_IRQEN_VFIE_MASK) +#define HALL_IRQEN_VFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_VFIE_MASK) >> HALL_IRQEN_VFIE_SHIFT) + +/* + * WFIE (RW) + * + * 1- generate interrupt request when w flag set + */ +#define HALL_IRQEN_WFIE_MASK (0x200000UL) +#define HALL_IRQEN_WFIE_SHIFT (21U) +#define HALL_IRQEN_WFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WFIE_SHIFT) & HALL_IRQEN_WFIE_MASK) +#define HALL_IRQEN_WFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WFIE_MASK) >> HALL_IRQEN_WFIE_SHIFT) + +/* Bitfield definition for register of struct array COUNT: W */ +/* + * WCNT (RO) + * + * wcnt counter + */ +#define HALL_COUNT_W_WCNT_MASK (0xFFFFFFFUL) +#define HALL_COUNT_W_WCNT_SHIFT (0U) +#define HALL_COUNT_W_WCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_W_WCNT_MASK) >> HALL_COUNT_W_WCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: V */ +/* + * VCNT (RO) + * + * vcnt counter + */ +#define HALL_COUNT_V_VCNT_MASK (0xFFFFFFFUL) +#define HALL_COUNT_V_VCNT_SHIFT (0U) +#define HALL_COUNT_V_VCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_V_VCNT_MASK) >> HALL_COUNT_V_VCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: U */ +/* + * DIR (RO) + * + * 1- reverse rotation + * 0- forward rotation + */ +#define HALL_COUNT_U_DIR_MASK (0x80000000UL) +#define HALL_COUNT_U_DIR_SHIFT (31U) +#define HALL_COUNT_U_DIR_GET(x) (((uint32_t)(x) & HALL_COUNT_U_DIR_MASK) >> HALL_COUNT_U_DIR_SHIFT) + +/* + * USTAT (RO) + * + * this bit indicate U state + */ +#define HALL_COUNT_U_USTAT_MASK (0x40000000UL) +#define HALL_COUNT_U_USTAT_SHIFT (30U) +#define HALL_COUNT_U_USTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_USTAT_MASK) >> HALL_COUNT_U_USTAT_SHIFT) + +/* + * VSTAT (RO) + * + * this bit indicate V state + */ +#define HALL_COUNT_U_VSTAT_MASK (0x20000000UL) +#define HALL_COUNT_U_VSTAT_SHIFT (29U) +#define HALL_COUNT_U_VSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_VSTAT_MASK) >> HALL_COUNT_U_VSTAT_SHIFT) + +/* + * WSTAT (RO) + * + * this bit indicate W state + */ +#define HALL_COUNT_U_WSTAT_MASK (0x10000000UL) +#define HALL_COUNT_U_WSTAT_SHIFT (28U) +#define HALL_COUNT_U_WSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_WSTAT_MASK) >> HALL_COUNT_U_WSTAT_SHIFT) + +/* + * UCNT (RO) + * + * ucnt counter + */ +#define HALL_COUNT_U_UCNT_MASK (0xFFFFFFFUL) +#define HALL_COUNT_U_UCNT_SHIFT (0U) +#define HALL_COUNT_U_UCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_UCNT_MASK) >> HALL_COUNT_U_UCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: TMR */ +/* + * TIMER (RO) + * + * 32 bit free run timer + */ +#define HALL_COUNT_TMR_TIMER_MASK (0xFFFFFFFFUL) +#define HALL_COUNT_TMR_TIMER_SHIFT (0U) +#define HALL_COUNT_TMR_TIMER_GET(x) (((uint32_t)(x) & HALL_COUNT_TMR_TIMER_MASK) >> HALL_COUNT_TMR_TIMER_SHIFT) + +/* Bitfield definition for register of struct array HIS: HIS0 */ +/* + * UHIS0 (RO) + * + * copy of ucnt when u signal transition from 0 to 1 + */ +#define HALL_HIS_HIS0_UHIS0_MASK (0xFFFFFFFFUL) +#define HALL_HIS_HIS0_UHIS0_SHIFT (0U) +#define HALL_HIS_HIS0_UHIS0_GET(x) (((uint32_t)(x) & HALL_HIS_HIS0_UHIS0_MASK) >> HALL_HIS_HIS0_UHIS0_SHIFT) + +/* Bitfield definition for register of struct array HIS: HIS1 */ +/* + * UHIS1 (RO) + * + * copy of ucnt when u signal transition from 1 to 0 + */ +#define HALL_HIS_HIS1_UHIS1_MASK (0xFFFFFFFFUL) +#define HALL_HIS_HIS1_UHIS1_SHIFT (0U) +#define HALL_HIS_HIS1_UHIS1_GET(x) (((uint32_t)(x) & HALL_HIS_HIS1_UHIS1_MASK) >> HALL_HIS_HIS1_UHIS1_SHIFT) + + + +/* COUNT register group index macro definition */ +#define HALL_COUNT_CURRENT (0UL) +#define HALL_COUNT_READ (1UL) +#define HALL_COUNT_SNAP0 (2UL) +#define HALL_COUNT_SNAP1 (3UL) + +/* HIS register group index macro definition */ +#define HALL_HIS_U (0UL) +#define HALL_HIS_V (1UL) +#define HALL_HIS_W (2UL) + + +#endif /* HPM_HALL_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2c_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2c_regs.h new file mode 100644 index 0000000000..639abf4261 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2c_regs.h @@ -0,0 +1,557 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_I2C_H +#define HPM_I2C_H + +typedef struct { + __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __RW uint32_t CFG; /* 0x10: Configuration Register */ + __RW uint32_t INTEN; /* 0x14: Interrupt Enable Register */ + __RW uint32_t STATUS; /* 0x18: Status Register */ + __RW uint32_t ADDR; /* 0x1C: Address Register */ + __RW uint32_t DATA; /* 0x20: Data Register */ + __RW uint32_t CTRL; /* 0x24: Control Register */ + __RW uint32_t CMD; /* 0x28: Command Register */ + __RW uint32_t SETUP; /* 0x2C: Setup Register */ + __RW uint32_t TPM; /* 0x30: I2C Timing Paramater Multiplier */ +} I2C_Type; + + +/* Bitfield definition for register: CFG */ +/* + * FIFOSIZE (RO) + * + * FIFO Size: + * 0: 2 bytes + * 1: 4 bytes + * 2: 8 bytes + * 3: 16 bytes + */ +#define I2C_CFG_FIFOSIZE_MASK (0x3U) +#define I2C_CFG_FIFOSIZE_SHIFT (0U) +#define I2C_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & I2C_CFG_FIFOSIZE_MASK) >> I2C_CFG_FIFOSIZE_SHIFT) + +/* Bitfield definition for register: INTEN */ +/* + * CMPL (RW) + * + * Set to enable the Completion Interrupt. + * Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. + * Slave: interrupts when a transaction addressing the controller is completed. + */ +#define I2C_INTEN_CMPL_MASK (0x200U) +#define I2C_INTEN_CMPL_SHIFT (9U) +#define I2C_INTEN_CMPL_SET(x) (((uint32_t)(x) << I2C_INTEN_CMPL_SHIFT) & I2C_INTEN_CMPL_MASK) +#define I2C_INTEN_CMPL_GET(x) (((uint32_t)(x) & I2C_INTEN_CMPL_MASK) >> I2C_INTEN_CMPL_SHIFT) + +/* + * BYTERECV (RW) + * + * Set to enable the Byte Receive Interrupt. + * Interrupts when a byte of data is received + * Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + */ +#define I2C_INTEN_BYTERECV_MASK (0x100U) +#define I2C_INTEN_BYTERECV_SHIFT (8U) +#define I2C_INTEN_BYTERECV_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTERECV_SHIFT) & I2C_INTEN_BYTERECV_MASK) +#define I2C_INTEN_BYTERECV_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTERECV_MASK) >> I2C_INTEN_BYTERECV_SHIFT) + +/* + * BYTETRANS (RW) + * + * Set to enable the Byte Transmit Interrupt. + * Interrupts when a byte of data is transmitted. + */ +#define I2C_INTEN_BYTETRANS_MASK (0x80U) +#define I2C_INTEN_BYTETRANS_SHIFT (7U) +#define I2C_INTEN_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTETRANS_SHIFT) & I2C_INTEN_BYTETRANS_MASK) +#define I2C_INTEN_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTETRANS_MASK) >> I2C_INTEN_BYTETRANS_SHIFT) + +/* + * START (RW) + * + * Set to enable the START Condition Interrupt. + * Interrupts when a START condition/repeated START condition is detected. + */ +#define I2C_INTEN_START_MASK (0x40U) +#define I2C_INTEN_START_SHIFT (6U) +#define I2C_INTEN_START_SET(x) (((uint32_t)(x) << I2C_INTEN_START_SHIFT) & I2C_INTEN_START_MASK) +#define I2C_INTEN_START_GET(x) (((uint32_t)(x) & I2C_INTEN_START_MASK) >> I2C_INTEN_START_SHIFT) + +/* + * STOP (RW) + * + * Set to enable the STOP Condition Interrupt + * Interrupts when a STOP condition is detected. + */ +#define I2C_INTEN_STOP_MASK (0x20U) +#define I2C_INTEN_STOP_SHIFT (5U) +#define I2C_INTEN_STOP_SET(x) (((uint32_t)(x) << I2C_INTEN_STOP_SHIFT) & I2C_INTEN_STOP_MASK) +#define I2C_INTEN_STOP_GET(x) (((uint32_t)(x) & I2C_INTEN_STOP_MASK) >> I2C_INTEN_STOP_SHIFT) + +/* + * ARBLOSE (RW) + * + * Set to enable the Arbitration Lose Interrupt. + * Master: interrupts when the controller loses the bus arbitration + * Slave: not available in this mode. + */ +#define I2C_INTEN_ARBLOSE_MASK (0x10U) +#define I2C_INTEN_ARBLOSE_SHIFT (4U) +#define I2C_INTEN_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_INTEN_ARBLOSE_SHIFT) & I2C_INTEN_ARBLOSE_MASK) +#define I2C_INTEN_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_INTEN_ARBLOSE_MASK) >> I2C_INTEN_ARBLOSE_SHIFT) + +/* + * ADDRHIT (RW) + * + * Set to enable the Address Hit Interrupt. + * Master: interrupts when the addressed slave returned an ACK. + * Slave: interrupts when the controller is addressed. + */ +#define I2C_INTEN_ADDRHIT_MASK (0x8U) +#define I2C_INTEN_ADDRHIT_SHIFT (3U) +#define I2C_INTEN_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_INTEN_ADDRHIT_SHIFT) & I2C_INTEN_ADDRHIT_MASK) +#define I2C_INTEN_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_INTEN_ADDRHIT_MASK) >> I2C_INTEN_ADDRHIT_SHIFT) + +/* + * FIFOHALF (RW) + * + * Set to enable the FIFO Half Interrupt. + * Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. + * Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. + * This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + */ +#define I2C_INTEN_FIFOHALF_MASK (0x4U) +#define I2C_INTEN_FIFOHALF_SHIFT (2U) +#define I2C_INTEN_FIFOHALF_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOHALF_SHIFT) & I2C_INTEN_FIFOHALF_MASK) +#define I2C_INTEN_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOHALF_MASK) >> I2C_INTEN_FIFOHALF_SHIFT) + +/* + * FIFOFULL (RW) + * + * Set to enable the FIFO Full Interrupt. + * Interrupts when the FIFO is full. + */ +#define I2C_INTEN_FIFOFULL_MASK (0x2U) +#define I2C_INTEN_FIFOFULL_SHIFT (1U) +#define I2C_INTEN_FIFOFULL_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOFULL_SHIFT) & I2C_INTEN_FIFOFULL_MASK) +#define I2C_INTEN_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOFULL_MASK) >> I2C_INTEN_FIFOFULL_SHIFT) + +/* + * FIFOEMPTY (RW) + * + * Set to enabled the FIFO Empty Interrupt + * Interrupts when the FIFO is empty. + */ +#define I2C_INTEN_FIFOEMPTY_MASK (0x1U) +#define I2C_INTEN_FIFOEMPTY_SHIFT (0U) +#define I2C_INTEN_FIFOEMPTY_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOEMPTY_SHIFT) & I2C_INTEN_FIFOEMPTY_MASK) +#define I2C_INTEN_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOEMPTY_MASK) >> I2C_INTEN_FIFOEMPTY_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * LINESDA (RO) + * + * Indicates the current status of the SDA line on the bus + * 1: high + * 0: low + */ +#define I2C_STATUS_LINESDA_MASK (0x4000U) +#define I2C_STATUS_LINESDA_SHIFT (14U) +#define I2C_STATUS_LINESDA_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESDA_MASK) >> I2C_STATUS_LINESDA_SHIFT) + +/* + * LINESCL (RO) + * + * Indicates the current status of the SCL line on the bus + * 1: high + * 0: low + */ +#define I2C_STATUS_LINESCL_MASK (0x2000U) +#define I2C_STATUS_LINESCL_SHIFT (13U) +#define I2C_STATUS_LINESCL_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESCL_MASK) >> I2C_STATUS_LINESCL_SHIFT) + +/* + * GENCALL (RO) + * + * Indicates that the address of the current transaction is a general call address: + * 1: General call + * 0: Not general call + */ +#define I2C_STATUS_GENCALL_MASK (0x1000U) +#define I2C_STATUS_GENCALL_SHIFT (12U) +#define I2C_STATUS_GENCALL_GET(x) (((uint32_t)(x) & I2C_STATUS_GENCALL_MASK) >> I2C_STATUS_GENCALL_SHIFT) + +/* + * BUSBUSY (RO) + * + * Indicates that the bus is busy + * The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus + * 1: Busy + * 0: Not busy + */ +#define I2C_STATUS_BUSBUSY_MASK (0x800U) +#define I2C_STATUS_BUSBUSY_SHIFT (11U) +#define I2C_STATUS_BUSBUSY_GET(x) (((uint32_t)(x) & I2C_STATUS_BUSBUSY_MASK) >> I2C_STATUS_BUSBUSY_SHIFT) + +/* + * ACK (RO) + * + * Indicates the type of the last received/transmitted acknowledgement bit: + * 1: ACK + * 0: NACK + */ +#define I2C_STATUS_ACK_MASK (0x400U) +#define I2C_STATUS_ACK_SHIFT (10U) +#define I2C_STATUS_ACK_GET(x) (((uint32_t)(x) & I2C_STATUS_ACK_MASK) >> I2C_STATUS_ACK_SHIFT) + +/* + * CMPL (W1C) + * + * Transaction Completion + * Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration + * Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + */ +#define I2C_STATUS_CMPL_MASK (0x200U) +#define I2C_STATUS_CMPL_SHIFT (9U) +#define I2C_STATUS_CMPL_SET(x) (((uint32_t)(x) << I2C_STATUS_CMPL_SHIFT) & I2C_STATUS_CMPL_MASK) +#define I2C_STATUS_CMPL_GET(x) (((uint32_t)(x) & I2C_STATUS_CMPL_MASK) >> I2C_STATUS_CMPL_SHIFT) + +/* + * BYTERECV (W1C) + * + * Indicates that a byte of data has been received. + */ +#define I2C_STATUS_BYTERECV_MASK (0x100U) +#define I2C_STATUS_BYTERECV_SHIFT (8U) +#define I2C_STATUS_BYTERECV_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTERECV_SHIFT) & I2C_STATUS_BYTERECV_MASK) +#define I2C_STATUS_BYTERECV_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTERECV_MASK) >> I2C_STATUS_BYTERECV_SHIFT) + +/* + * BYTETRANS (W1C) + * + * Indicates that a byte of data has been transmitted. + */ +#define I2C_STATUS_BYTETRANS_MASK (0x80U) +#define I2C_STATUS_BYTETRANS_SHIFT (7U) +#define I2C_STATUS_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTETRANS_SHIFT) & I2C_STATUS_BYTETRANS_MASK) +#define I2C_STATUS_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTETRANS_MASK) >> I2C_STATUS_BYTETRANS_SHIFT) + +/* + * START (W1C) + * + * Indicates that a START Condition or a repeated START condition has been transmitted/received. + */ +#define I2C_STATUS_START_MASK (0x40U) +#define I2C_STATUS_START_SHIFT (6U) +#define I2C_STATUS_START_SET(x) (((uint32_t)(x) << I2C_STATUS_START_SHIFT) & I2C_STATUS_START_MASK) +#define I2C_STATUS_START_GET(x) (((uint32_t)(x) & I2C_STATUS_START_MASK) >> I2C_STATUS_START_SHIFT) + +/* + * STOP (W1C) + * + * Indicates that a STOP Condition has been transmitted/received. + */ +#define I2C_STATUS_STOP_MASK (0x20U) +#define I2C_STATUS_STOP_SHIFT (5U) +#define I2C_STATUS_STOP_SET(x) (((uint32_t)(x) << I2C_STATUS_STOP_SHIFT) & I2C_STATUS_STOP_MASK) +#define I2C_STATUS_STOP_GET(x) (((uint32_t)(x) & I2C_STATUS_STOP_MASK) >> I2C_STATUS_STOP_SHIFT) + +/* + * ARBLOSE (W1C) + * + * Indicates that the controller has lost the bus arbitration. + */ +#define I2C_STATUS_ARBLOSE_MASK (0x10U) +#define I2C_STATUS_ARBLOSE_SHIFT (4U) +#define I2C_STATUS_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_STATUS_ARBLOSE_SHIFT) & I2C_STATUS_ARBLOSE_MASK) +#define I2C_STATUS_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_STATUS_ARBLOSE_MASK) >> I2C_STATUS_ARBLOSE_SHIFT) + +/* + * ADDRHIT (W1C) + * + * Master: indicates that a slave has responded to the transaction. + * Slave: indicates that a transaction is targeting the controller (including the General Call). + */ +#define I2C_STATUS_ADDRHIT_MASK (0x8U) +#define I2C_STATUS_ADDRHIT_SHIFT (3U) +#define I2C_STATUS_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_STATUS_ADDRHIT_SHIFT) & I2C_STATUS_ADDRHIT_MASK) +#define I2C_STATUS_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_STATUS_ADDRHIT_MASK) >> I2C_STATUS_ADDRHIT_SHIFT) + +/* + * FIFOHALF (RO) + * + * Transmitter: Indicates that the FIFO is half-empty. + */ +#define I2C_STATUS_FIFOHALF_MASK (0x4U) +#define I2C_STATUS_FIFOHALF_SHIFT (2U) +#define I2C_STATUS_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOHALF_MASK) >> I2C_STATUS_FIFOHALF_SHIFT) + +/* + * FIFOFULL (RO) + * + * Indicates that the FIFO is full. + */ +#define I2C_STATUS_FIFOFULL_MASK (0x2U) +#define I2C_STATUS_FIFOFULL_SHIFT (1U) +#define I2C_STATUS_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOFULL_MASK) >> I2C_STATUS_FIFOFULL_SHIFT) + +/* + * FIFOEMPTY (RO) + * + * Indicates that the FIFO is empty. + */ +#define I2C_STATUS_FIFOEMPTY_MASK (0x1U) +#define I2C_STATUS_FIFOEMPTY_SHIFT (0U) +#define I2C_STATUS_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOEMPTY_MASK) >> I2C_STATUS_FIFOEMPTY_SHIFT) + +/* Bitfield definition for register: ADDR */ +/* + * ADDR (RW) + * + * The slave address. + * For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + */ +#define I2C_ADDR_ADDR_MASK (0x3FFU) +#define I2C_ADDR_ADDR_SHIFT (0U) +#define I2C_ADDR_ADDR_SET(x) (((uint32_t)(x) << I2C_ADDR_ADDR_SHIFT) & I2C_ADDR_ADDR_MASK) +#define I2C_ADDR_ADDR_GET(x) (((uint32_t)(x) & I2C_ADDR_ADDR_MASK) >> I2C_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register: DATA */ +/* + * DATA (RW) + * + * Write this register to put one byte of data to the FIFO. + * Read this register to get one byte of data from the FIFO. + */ +#define I2C_DATA_DATA_MASK (0xFFU) +#define I2C_DATA_DATA_SHIFT (0U) +#define I2C_DATA_DATA_SET(x) (((uint32_t)(x) << I2C_DATA_DATA_SHIFT) & I2C_DATA_DATA_MASK) +#define I2C_DATA_DATA_GET(x) (((uint32_t)(x) & I2C_DATA_DATA_MASK) >> I2C_DATA_DATA_SHIFT) + +/* Bitfield definition for register: CTRL */ +/* + * PHASE_START (RW) + * + * Enable this bit to send a START condition at the beginning of transaction. + * Master mode only. + */ +#define I2C_CTRL_PHASE_START_MASK (0x1000U) +#define I2C_CTRL_PHASE_START_SHIFT (12U) +#define I2C_CTRL_PHASE_START_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_START_SHIFT) & I2C_CTRL_PHASE_START_MASK) +#define I2C_CTRL_PHASE_START_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_START_MASK) >> I2C_CTRL_PHASE_START_SHIFT) + +/* + * PHASE_ADDR (RW) + * + * Enable this bit to send the address after START condition. + * Master mode only. + */ +#define I2C_CTRL_PHASE_ADDR_MASK (0x800U) +#define I2C_CTRL_PHASE_ADDR_SHIFT (11U) +#define I2C_CTRL_PHASE_ADDR_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_ADDR_SHIFT) & I2C_CTRL_PHASE_ADDR_MASK) +#define I2C_CTRL_PHASE_ADDR_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_ADDR_MASK) >> I2C_CTRL_PHASE_ADDR_SHIFT) + +/* + * PHASE_DATA (RW) + * + * Enable this bit to send the data after Address phase. + * Master mode only. + */ +#define I2C_CTRL_PHASE_DATA_MASK (0x400U) +#define I2C_CTRL_PHASE_DATA_SHIFT (10U) +#define I2C_CTRL_PHASE_DATA_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_DATA_SHIFT) & I2C_CTRL_PHASE_DATA_MASK) +#define I2C_CTRL_PHASE_DATA_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_DATA_MASK) >> I2C_CTRL_PHASE_DATA_SHIFT) + +/* + * PHASE_STOP (RW) + * + * Enable this bit to send a STOP condition at the end of a transaction. + * Master mode only. + */ +#define I2C_CTRL_PHASE_STOP_MASK (0x200U) +#define I2C_CTRL_PHASE_STOP_SHIFT (9U) +#define I2C_CTRL_PHASE_STOP_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_STOP_SHIFT) & I2C_CTRL_PHASE_STOP_MASK) +#define I2C_CTRL_PHASE_STOP_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_STOP_MASK) >> I2C_CTRL_PHASE_STOP_SHIFT) + +/* + * DIR (RW) + * + * Transaction direction + * Master: Set this bit to determine the direction for the next transaction. + * 0: Transmitter + * 1: Receiver + * Slave: The direction of the last received transaction. + * 0: Receiver + * 1: Transmitter + */ +#define I2C_CTRL_DIR_MASK (0x100U) +#define I2C_CTRL_DIR_SHIFT (8U) +#define I2C_CTRL_DIR_SET(x) (((uint32_t)(x) << I2C_CTRL_DIR_SHIFT) & I2C_CTRL_DIR_MASK) +#define I2C_CTRL_DIR_GET(x) (((uint32_t)(x) & I2C_CTRL_DIR_MASK) >> I2C_CTRL_DIR_SHIFT) + +/* + * DATACNT (RW) + * + * Data counts in bytes. + * Master: The number of bytes to transmit/receive. 0 means 256 bytes. DataCnt will be decreased by one for each byte transmitted/received. + * Slave: the meaning of DataCnt depends on the DMA mode: + * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. + * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + */ +#define I2C_CTRL_DATACNT_MASK (0xFFU) +#define I2C_CTRL_DATACNT_SHIFT (0U) +#define I2C_CTRL_DATACNT_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_SHIFT) & I2C_CTRL_DATACNT_MASK) +#define I2C_CTRL_DATACNT_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_MASK) >> I2C_CTRL_DATACNT_SHIFT) + +/* Bitfield definition for register: CMD */ +/* + * CMD (RW) + * + * Write this register with the following values to perform the corresponding actions: + * 0x0: no action + * 0x1: issue a data transaction (Master only) + * 0x2: respond with an ACK to the received byte + * 0x3: respond with a NACK to the received byte + * 0x4: clear the FIFO + * 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) + * When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. + * Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + */ +#define I2C_CMD_CMD_MASK (0x7U) +#define I2C_CMD_CMD_SHIFT (0U) +#define I2C_CMD_CMD_SET(x) (((uint32_t)(x) << I2C_CMD_CMD_SHIFT) & I2C_CMD_CMD_MASK) +#define I2C_CMD_CMD_GET(x) (((uint32_t)(x) & I2C_CMD_CMD_MASK) >> I2C_CMD_CMD_SHIFT) + +/* Bitfield definition for register: SETUP */ +/* + * T_SUDAT (RW) + * + * T_SUDAT defines the data setup time before releasing the SCL. + * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) + * tpclk = PCLK period + * TPM = The multiplier value in Timing Parameter Multiplier Register + */ +#define I2C_SETUP_T_SUDAT_MASK (0x1F000000UL) +#define I2C_SETUP_T_SUDAT_SHIFT (24U) +#define I2C_SETUP_T_SUDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SUDAT_SHIFT) & I2C_SETUP_T_SUDAT_MASK) +#define I2C_SETUP_T_SUDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SUDAT_MASK) >> I2C_SETUP_T_SUDAT_SHIFT) + +/* + * T_SP (RW) + * + * T_SP defines the pulse width of spikes that must be suppressed by the input filter. + * Pulse width = T_SP * tpclk* (TPM+1) + */ +#define I2C_SETUP_T_SP_MASK (0xE00000UL) +#define I2C_SETUP_T_SP_SHIFT (21U) +#define I2C_SETUP_T_SP_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SP_SHIFT) & I2C_SETUP_T_SP_MASK) +#define I2C_SETUP_T_SP_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SP_MASK) >> I2C_SETUP_T_SP_SHIFT) + +/* + * T_HDDAT (RW) + * + * T_HDDAT defines the data hold time after SCL goes LOW + * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + */ +#define I2C_SETUP_T_HDDAT_MASK (0x1F0000UL) +#define I2C_SETUP_T_HDDAT_SHIFT (16U) +#define I2C_SETUP_T_HDDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_HDDAT_SHIFT) & I2C_SETUP_T_HDDAT_MASK) +#define I2C_SETUP_T_HDDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_HDDAT_MASK) >> I2C_SETUP_T_HDDAT_SHIFT) + +/* + * T_SCLRADIO (RW) + * + * The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. + * SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) + * 1: ratio = 2 + * 0: ratio = 1 + * This field is only valid when the controller is in the master mode. + */ +#define I2C_SETUP_T_SCLRADIO_MASK (0x2000U) +#define I2C_SETUP_T_SCLRADIO_SHIFT (13U) +#define I2C_SETUP_T_SCLRADIO_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLRADIO_SHIFT) & I2C_SETUP_T_SCLRADIO_MASK) +#define I2C_SETUP_T_SCLRADIO_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLRADIO_MASK) >> I2C_SETUP_T_SCLRADIO_SHIFT) + +/* + * T_SCLHI (RW) + * + * The HIGH period of generated SCL clock is defined by T_SCLHi. + * SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) + * The T_SCLHi value must be greater than T_SP and T_HDDAT values. + * This field is only valid when the controller is in the master mode. + */ +#define I2C_SETUP_T_SCLHI_MASK (0x1FF0U) +#define I2C_SETUP_T_SCLHI_SHIFT (4U) +#define I2C_SETUP_T_SCLHI_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLHI_SHIFT) & I2C_SETUP_T_SCLHI_MASK) +#define I2C_SETUP_T_SCLHI_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLHI_MASK) >> I2C_SETUP_T_SCLHI_SHIFT) + +/* + * DMAEN (RW) + * + * Enable the direct memory access mode data transfer. + * 1: Enable + * 0: Disable + */ +#define I2C_SETUP_DMAEN_MASK (0x8U) +#define I2C_SETUP_DMAEN_SHIFT (3U) +#define I2C_SETUP_DMAEN_SET(x) (((uint32_t)(x) << I2C_SETUP_DMAEN_SHIFT) & I2C_SETUP_DMAEN_MASK) +#define I2C_SETUP_DMAEN_GET(x) (((uint32_t)(x) & I2C_SETUP_DMAEN_MASK) >> I2C_SETUP_DMAEN_SHIFT) + +/* + * MASTER (RW) + * + * Configure this device as a master or a slave. + * 1: Master mode + * 0: Slave mode + */ +#define I2C_SETUP_MASTER_MASK (0x4U) +#define I2C_SETUP_MASTER_SHIFT (2U) +#define I2C_SETUP_MASTER_SET(x) (((uint32_t)(x) << I2C_SETUP_MASTER_SHIFT) & I2C_SETUP_MASTER_MASK) +#define I2C_SETUP_MASTER_GET(x) (((uint32_t)(x) & I2C_SETUP_MASTER_MASK) >> I2C_SETUP_MASTER_SHIFT) + +/* + * ADDRESSING (RW) + * + * I2C addressing mode: + * 1: 10-bit addressing mode + * 0: 7-bit addressing mode + */ +#define I2C_SETUP_ADDRESSING_MASK (0x2U) +#define I2C_SETUP_ADDRESSING_SHIFT (1U) +#define I2C_SETUP_ADDRESSING_SET(x) (((uint32_t)(x) << I2C_SETUP_ADDRESSING_SHIFT) & I2C_SETUP_ADDRESSING_MASK) +#define I2C_SETUP_ADDRESSING_GET(x) (((uint32_t)(x) & I2C_SETUP_ADDRESSING_MASK) >> I2C_SETUP_ADDRESSING_SHIFT) + +/* + * IICEN (RW) + * + * Enable the I2C controller. + * 1: Enable + * 0: Disable + */ +#define I2C_SETUP_IICEN_MASK (0x1U) +#define I2C_SETUP_IICEN_SHIFT (0U) +#define I2C_SETUP_IICEN_SET(x) (((uint32_t)(x) << I2C_SETUP_IICEN_SHIFT) & I2C_SETUP_IICEN_MASK) +#define I2C_SETUP_IICEN_GET(x) (((uint32_t)(x) & I2C_SETUP_IICEN_MASK) >> I2C_SETUP_IICEN_SHIFT) + +/* Bitfield definition for register: TPM */ +/* + * TPM (RW) + * + * A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + */ +#define I2C_TPM_TPM_MASK (0x1FU) +#define I2C_TPM_TPM_SHIFT (0U) +#define I2C_TPM_TPM_SET(x) (((uint32_t)(x) << I2C_TPM_TPM_SHIFT) & I2C_TPM_TPM_MASK) +#define I2C_TPM_TPM_GET(x) (((uint32_t)(x) & I2C_TPM_TPM_MASK) >> I2C_TPM_TPM_SHIFT) + + + + +#endif /* HPM_I2C_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h new file mode 100644 index 0000000000..7a64f7857a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h @@ -0,0 +1,590 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_I2S_H +#define HPM_I2S_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: Control Register */ + __R uint32_t RFIFO_FILLINGS; /* 0x4: Rx FIFO Filling Level */ + __R uint32_t TFIFO_FILLINGS; /* 0x8: Tx FIFO Filling Level */ + __RW uint32_t FIFO_THRESH; /* 0xC: TX/RX FIFO Threshold setting. */ + __RW uint32_t STA; /* 0x10: Status Registers */ + __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ + __R uint32_t RXD[4]; /* 0x20 - 0x2C: Rx Data0 */ + __W uint32_t TXD[4]; /* 0x30 - 0x3C: Tx Data0 */ + __R uint8_t RESERVED1[16]; /* 0x40 - 0x4F: Reserved */ + __RW uint32_t CFGR; /* 0x50: Configruation Regsiters */ + __R uint8_t RESERVED2[4]; /* 0x54 - 0x57: Reserved */ + __RW uint32_t MISC_CFGR; /* 0x58: Misc configuration Registers */ + __R uint8_t RESERVED3[4]; /* 0x5C - 0x5F: Reserved */ + __RW uint32_t RXDSLOT[4]; /* 0x60 - 0x6C: Rx Slots Enable for Rx Data0 */ + __RW uint32_t TXDSLOT[4]; /* 0x70 - 0x7C: Tx Slots Enable for Tx Data0. */ +} I2S_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SFTRST_RX (RW) + * + * software reset the RX module if asserted to be 1'b1. Self-clear. + */ +#define I2S_CTRL_SFTRST_RX_MASK (0x40000UL) +#define I2S_CTRL_SFTRST_RX_SHIFT (18U) +#define I2S_CTRL_SFTRST_RX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_RX_SHIFT) & I2S_CTRL_SFTRST_RX_MASK) +#define I2S_CTRL_SFTRST_RX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_RX_MASK) >> I2S_CTRL_SFTRST_RX_SHIFT) + +/* + * SFTRST_TX (RW) + * + * software reset the TX module if asserted to be 1'b1. Self-clear. + */ +#define I2S_CTRL_SFTRST_TX_MASK (0x20000UL) +#define I2S_CTRL_SFTRST_TX_SHIFT (17U) +#define I2S_CTRL_SFTRST_TX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_TX_SHIFT) & I2S_CTRL_SFTRST_TX_MASK) +#define I2S_CTRL_SFTRST_TX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_TX_MASK) >> I2S_CTRL_SFTRST_TX_SHIFT) + +/* + * SFTRST_CLKGEN (RW) + * + * software reset the CLK GEN module if asserted to be 1'b1. Self-clear. + */ +#define I2S_CTRL_SFTRST_CLKGEN_MASK (0x10000UL) +#define I2S_CTRL_SFTRST_CLKGEN_SHIFT (16U) +#define I2S_CTRL_SFTRST_CLKGEN_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_CLKGEN_SHIFT) & I2S_CTRL_SFTRST_CLKGEN_MASK) +#define I2S_CTRL_SFTRST_CLKGEN_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_CLKGEN_MASK) >> I2S_CTRL_SFTRST_CLKGEN_SHIFT) + +/* + * TXDNIE (RW) + * + * TX buffer data needed interrupt enable + * 0: TXE interrupt masked + * 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + */ +#define I2S_CTRL_TXDNIE_MASK (0x8000U) +#define I2S_CTRL_TXDNIE_SHIFT (15U) +#define I2S_CTRL_TXDNIE_SET(x) (((uint32_t)(x) << I2S_CTRL_TXDNIE_SHIFT) & I2S_CTRL_TXDNIE_MASK) +#define I2S_CTRL_TXDNIE_GET(x) (((uint32_t)(x) & I2S_CTRL_TXDNIE_MASK) >> I2S_CTRL_TXDNIE_SHIFT) + +/* + * RXDAIE (RW) + * + * RX buffer data available interrupt enable + * 0: RXNE interrupt masked + * 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + */ +#define I2S_CTRL_RXDAIE_MASK (0x4000U) +#define I2S_CTRL_RXDAIE_SHIFT (14U) +#define I2S_CTRL_RXDAIE_SET(x) (((uint32_t)(x) << I2S_CTRL_RXDAIE_SHIFT) & I2S_CTRL_RXDAIE_MASK) +#define I2S_CTRL_RXDAIE_GET(x) (((uint32_t)(x) & I2S_CTRL_RXDAIE_MASK) >> I2S_CTRL_RXDAIE_SHIFT) + +/* + * ERRIE (RW) + * + * Error interrupt enable + * This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. + * 0: Error interrupt is masked + * 1: Error interrupt is enabled + */ +#define I2S_CTRL_ERRIE_MASK (0x2000U) +#define I2S_CTRL_ERRIE_SHIFT (13U) +#define I2S_CTRL_ERRIE_SET(x) (((uint32_t)(x) << I2S_CTRL_ERRIE_SHIFT) & I2S_CTRL_ERRIE_MASK) +#define I2S_CTRL_ERRIE_GET(x) (((uint32_t)(x) & I2S_CTRL_ERRIE_MASK) >> I2S_CTRL_ERRIE_SHIFT) + +/* + * TX_DMA_EN (RW) + * + * Asserted to use DMA, else to use interrupt + */ +#define I2S_CTRL_TX_DMA_EN_MASK (0x1000U) +#define I2S_CTRL_TX_DMA_EN_SHIFT (12U) +#define I2S_CTRL_TX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_DMA_EN_SHIFT) & I2S_CTRL_TX_DMA_EN_MASK) +#define I2S_CTRL_TX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_DMA_EN_MASK) >> I2S_CTRL_TX_DMA_EN_SHIFT) + +/* + * RX_DMA_EN (RW) + * + * Asserted to use DMA, else to use interrupt + */ +#define I2S_CTRL_RX_DMA_EN_MASK (0x800U) +#define I2S_CTRL_RX_DMA_EN_SHIFT (11U) +#define I2S_CTRL_RX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_DMA_EN_SHIFT) & I2S_CTRL_RX_DMA_EN_MASK) +#define I2S_CTRL_RX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_DMA_EN_MASK) >> I2S_CTRL_RX_DMA_EN_SHIFT) + +/* + * TXFIFOCLR (RW) + * + * Self-clear + */ +#define I2S_CTRL_TXFIFOCLR_MASK (0x400U) +#define I2S_CTRL_TXFIFOCLR_SHIFT (10U) +#define I2S_CTRL_TXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_TXFIFOCLR_SHIFT) & I2S_CTRL_TXFIFOCLR_MASK) +#define I2S_CTRL_TXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_TXFIFOCLR_MASK) >> I2S_CTRL_TXFIFOCLR_SHIFT) + +/* + * RXFIFOCLR (RW) + * + * Self-clear + */ +#define I2S_CTRL_RXFIFOCLR_MASK (0x200U) +#define I2S_CTRL_RXFIFOCLR_SHIFT (9U) +#define I2S_CTRL_RXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_RXFIFOCLR_SHIFT) & I2S_CTRL_RXFIFOCLR_MASK) +#define I2S_CTRL_RXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_RXFIFOCLR_MASK) >> I2S_CTRL_RXFIFOCLR_SHIFT) + +/* + * TX_EN (RW) + * + * enable for each TX data pad + */ +#define I2S_CTRL_TX_EN_MASK (0x1E0U) +#define I2S_CTRL_TX_EN_SHIFT (5U) +#define I2S_CTRL_TX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_EN_SHIFT) & I2S_CTRL_TX_EN_MASK) +#define I2S_CTRL_TX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_EN_MASK) >> I2S_CTRL_TX_EN_SHIFT) + +/* + * RX_EN (RW) + * + * enable for each RX data pad + */ +#define I2S_CTRL_RX_EN_MASK (0x1EU) +#define I2S_CTRL_RX_EN_SHIFT (1U) +#define I2S_CTRL_RX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_EN_SHIFT) & I2S_CTRL_RX_EN_MASK) +#define I2S_CTRL_RX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_EN_MASK) >> I2S_CTRL_RX_EN_SHIFT) + +/* + * I2S_EN (RW) + * + * enable for the module + */ +#define I2S_CTRL_I2S_EN_MASK (0x1U) +#define I2S_CTRL_I2S_EN_SHIFT (0U) +#define I2S_CTRL_I2S_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_I2S_EN_SHIFT) & I2S_CTRL_I2S_EN_MASK) +#define I2S_CTRL_I2S_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_I2S_EN_MASK) >> I2S_CTRL_I2S_EN_SHIFT) + +/* Bitfield definition for register: RFIFO_FILLINGS */ +/* + * RX3 (RO) + * + * RX3 fifo fillings + */ +#define I2S_RFIFO_FILLINGS_RX3_MASK (0xFF000000UL) +#define I2S_RFIFO_FILLINGS_RX3_SHIFT (24U) +#define I2S_RFIFO_FILLINGS_RX3_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX3_MASK) >> I2S_RFIFO_FILLINGS_RX3_SHIFT) + +/* + * RX2 (RO) + * + * RX2 fifo fillings + */ +#define I2S_RFIFO_FILLINGS_RX2_MASK (0xFF0000UL) +#define I2S_RFIFO_FILLINGS_RX2_SHIFT (16U) +#define I2S_RFIFO_FILLINGS_RX2_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX2_MASK) >> I2S_RFIFO_FILLINGS_RX2_SHIFT) + +/* + * RX1 (RO) + * + * RX1 fifo fillings + */ +#define I2S_RFIFO_FILLINGS_RX1_MASK (0xFF00U) +#define I2S_RFIFO_FILLINGS_RX1_SHIFT (8U) +#define I2S_RFIFO_FILLINGS_RX1_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX1_MASK) >> I2S_RFIFO_FILLINGS_RX1_SHIFT) + +/* + * RX0 (RO) + * + * RX0 fifo fillings + */ +#define I2S_RFIFO_FILLINGS_RX0_MASK (0xFFU) +#define I2S_RFIFO_FILLINGS_RX0_SHIFT (0U) +#define I2S_RFIFO_FILLINGS_RX0_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX0_MASK) >> I2S_RFIFO_FILLINGS_RX0_SHIFT) + +/* Bitfield definition for register: TFIFO_FILLINGS */ +/* + * TX3 (RO) + * + * TX3 fifo fillings + */ +#define I2S_TFIFO_FILLINGS_TX3_MASK (0xFF000000UL) +#define I2S_TFIFO_FILLINGS_TX3_SHIFT (24U) +#define I2S_TFIFO_FILLINGS_TX3_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX3_MASK) >> I2S_TFIFO_FILLINGS_TX3_SHIFT) + +/* + * TX2 (RO) + * + * TX2 fifo fillings + */ +#define I2S_TFIFO_FILLINGS_TX2_MASK (0xFF0000UL) +#define I2S_TFIFO_FILLINGS_TX2_SHIFT (16U) +#define I2S_TFIFO_FILLINGS_TX2_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX2_MASK) >> I2S_TFIFO_FILLINGS_TX2_SHIFT) + +/* + * TX1 (RO) + * + * TX1 fifo fillings + */ +#define I2S_TFIFO_FILLINGS_TX1_MASK (0xFF00U) +#define I2S_TFIFO_FILLINGS_TX1_SHIFT (8U) +#define I2S_TFIFO_FILLINGS_TX1_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX1_MASK) >> I2S_TFIFO_FILLINGS_TX1_SHIFT) + +/* + * TX0 (RO) + * + * TX0 fifo fillings + */ +#define I2S_TFIFO_FILLINGS_TX0_MASK (0xFFU) +#define I2S_TFIFO_FILLINGS_TX0_SHIFT (0U) +#define I2S_TFIFO_FILLINGS_TX0_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX0_MASK) >> I2S_TFIFO_FILLINGS_TX0_SHIFT) + +/* Bitfield definition for register: FIFO_THRESH */ +/* + * TX (RW) + * + * TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. + */ +#define I2S_FIFO_THRESH_TX_MASK (0xFF00U) +#define I2S_FIFO_THRESH_TX_SHIFT (8U) +#define I2S_FIFO_THRESH_TX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_TX_SHIFT) & I2S_FIFO_THRESH_TX_MASK) +#define I2S_FIFO_THRESH_TX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_TX_MASK) >> I2S_FIFO_THRESH_TX_SHIFT) + +/* + * RX (RW) + * + * RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. + */ +#define I2S_FIFO_THRESH_RX_MASK (0xFFU) +#define I2S_FIFO_THRESH_RX_SHIFT (0U) +#define I2S_FIFO_THRESH_RX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_RX_SHIFT) & I2S_FIFO_THRESH_RX_MASK) +#define I2S_FIFO_THRESH_RX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_RX_MASK) >> I2S_FIFO_THRESH_RX_SHIFT) + +/* Bitfield definition for register: STA */ +/* + * TX_UD (W1C) + * + * Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. + */ +#define I2S_STA_TX_UD_MASK (0x1E000UL) +#define I2S_STA_TX_UD_SHIFT (13U) +#define I2S_STA_TX_UD_SET(x) (((uint32_t)(x) << I2S_STA_TX_UD_SHIFT) & I2S_STA_TX_UD_MASK) +#define I2S_STA_TX_UD_GET(x) (((uint32_t)(x) & I2S_STA_TX_UD_MASK) >> I2S_STA_TX_UD_SHIFT) + +/* + * RX_OV (W1C) + * + * Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. + */ +#define I2S_STA_RX_OV_MASK (0x1E00U) +#define I2S_STA_RX_OV_SHIFT (9U) +#define I2S_STA_RX_OV_SET(x) (((uint32_t)(x) << I2S_STA_RX_OV_SHIFT) & I2S_STA_RX_OV_MASK) +#define I2S_STA_RX_OV_GET(x) (((uint32_t)(x) & I2S_STA_RX_OV_MASK) >> I2S_STA_RX_OV_SHIFT) + +/* + * TX_DN (RO) + * + * Asserted when tx fifo data are needed. + */ +#define I2S_STA_TX_DN_MASK (0x1E0U) +#define I2S_STA_TX_DN_SHIFT (5U) +#define I2S_STA_TX_DN_GET(x) (((uint32_t)(x) & I2S_STA_TX_DN_MASK) >> I2S_STA_TX_DN_SHIFT) + +/* + * RX_DA (RO) + * + * Asserted when rx fifo data are available. + */ +#define I2S_STA_RX_DA_MASK (0x1EU) +#define I2S_STA_RX_DA_SHIFT (1U) +#define I2S_STA_RX_DA_GET(x) (((uint32_t)(x) & I2S_STA_RX_DA_MASK) >> I2S_STA_RX_DA_SHIFT) + +/* Bitfield definition for register array: RXD */ +/* + * D (RO) + * + */ +#define I2S_RXD_D_MASK (0xFFFFFFFFUL) +#define I2S_RXD_D_SHIFT (0U) +#define I2S_RXD_D_GET(x) (((uint32_t)(x) & I2S_RXD_D_MASK) >> I2S_RXD_D_SHIFT) + +/* Bitfield definition for register array: TXD */ +/* + * D (WO) + * + */ +#define I2S_TXD_D_MASK (0xFFFFFFFFUL) +#define I2S_TXD_D_SHIFT (0U) +#define I2S_TXD_D_SET(x) (((uint32_t)(x) << I2S_TXD_D_SHIFT) & I2S_TXD_D_MASK) +#define I2S_TXD_D_GET(x) (((uint32_t)(x) & I2S_TXD_D_MASK) >> I2S_TXD_D_SHIFT) + +/* Bitfield definition for register: CFGR */ +/* + * BCLK_GATEOFF (RW) + * + * Gate off the bclk. Asserted to gate-off the BCLK. + */ +#define I2S_CFGR_BCLK_GATEOFF_MASK (0x40000000UL) +#define I2S_CFGR_BCLK_GATEOFF_SHIFT (30U) +#define I2S_CFGR_BCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_GATEOFF_SHIFT) & I2S_CFGR_BCLK_GATEOFF_MASK) +#define I2S_CFGR_BCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_GATEOFF_MASK) >> I2S_CFGR_BCLK_GATEOFF_SHIFT) + +/* + * BCLK_DIV (RW) + * + * Linear prescaler to generate BCLK from MCLK. + * BCLK_DIV [8:0] = 0: BCLK=No CLK. + * BCLK_DIV [8:0] = 1: BCLK=MCLK/1 + * BCLK_DIV [8:0] = n: BCLK=MCLK/(n). + * Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + */ +#define I2S_CFGR_BCLK_DIV_MASK (0x3FE00000UL) +#define I2S_CFGR_BCLK_DIV_SHIFT (21U) +#define I2S_CFGR_BCLK_DIV_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_DIV_SHIFT) & I2S_CFGR_BCLK_DIV_MASK) +#define I2S_CFGR_BCLK_DIV_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_DIV_MASK) >> I2S_CFGR_BCLK_DIV_SHIFT) + +/* + * INV_BCLK_OUT (RW) + * + * Invert the BCLK before sending it out to pad. Only valid in BCLK master mode + */ +#define I2S_CFGR_INV_BCLK_OUT_MASK (0x100000UL) +#define I2S_CFGR_INV_BCLK_OUT_SHIFT (20U) +#define I2S_CFGR_INV_BCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_OUT_SHIFT) & I2S_CFGR_INV_BCLK_OUT_MASK) +#define I2S_CFGR_INV_BCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_OUT_MASK) >> I2S_CFGR_INV_BCLK_OUT_SHIFT) + +/* + * INV_BCLK_IN (RW) + * + * Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode + */ +#define I2S_CFGR_INV_BCLK_IN_MASK (0x80000UL) +#define I2S_CFGR_INV_BCLK_IN_SHIFT (19U) +#define I2S_CFGR_INV_BCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_IN_SHIFT) & I2S_CFGR_INV_BCLK_IN_MASK) +#define I2S_CFGR_INV_BCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_IN_MASK) >> I2S_CFGR_INV_BCLK_IN_SHIFT) + +/* + * INV_FCLK_OUT (RW) + * + * Invert the FCLK before sending it out to pad. Only valid in FCLK master mode + */ +#define I2S_CFGR_INV_FCLK_OUT_MASK (0x40000UL) +#define I2S_CFGR_INV_FCLK_OUT_SHIFT (18U) +#define I2S_CFGR_INV_FCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_OUT_SHIFT) & I2S_CFGR_INV_FCLK_OUT_MASK) +#define I2S_CFGR_INV_FCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_OUT_MASK) >> I2S_CFGR_INV_FCLK_OUT_SHIFT) + +/* + * INV_FCLK_IN (RW) + * + * Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode + */ +#define I2S_CFGR_INV_FCLK_IN_MASK (0x20000UL) +#define I2S_CFGR_INV_FCLK_IN_SHIFT (17U) +#define I2S_CFGR_INV_FCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_IN_SHIFT) & I2S_CFGR_INV_FCLK_IN_MASK) +#define I2S_CFGR_INV_FCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_IN_MASK) >> I2S_CFGR_INV_FCLK_IN_SHIFT) + +/* + * INV_MCLK_OUT (RW) + * + * Invert the MCLK before sending it out to pad. Only valid in MCLK master mode + */ +#define I2S_CFGR_INV_MCLK_OUT_MASK (0x10000UL) +#define I2S_CFGR_INV_MCLK_OUT_SHIFT (16U) +#define I2S_CFGR_INV_MCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_OUT_SHIFT) & I2S_CFGR_INV_MCLK_OUT_MASK) +#define I2S_CFGR_INV_MCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_OUT_MASK) >> I2S_CFGR_INV_MCLK_OUT_SHIFT) + +/* + * INV_MCLK_IN (RW) + * + * Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode + */ +#define I2S_CFGR_INV_MCLK_IN_MASK (0x8000U) +#define I2S_CFGR_INV_MCLK_IN_SHIFT (15U) +#define I2S_CFGR_INV_MCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_IN_SHIFT) & I2S_CFGR_INV_MCLK_IN_MASK) +#define I2S_CFGR_INV_MCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_IN_MASK) >> I2S_CFGR_INV_MCLK_IN_SHIFT) + +/* + * BCLK_SEL_OP (RW) + * + * asserted to use external clk source + */ +#define I2S_CFGR_BCLK_SEL_OP_MASK (0x4000U) +#define I2S_CFGR_BCLK_SEL_OP_SHIFT (14U) +#define I2S_CFGR_BCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_SEL_OP_SHIFT) & I2S_CFGR_BCLK_SEL_OP_MASK) +#define I2S_CFGR_BCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_SEL_OP_MASK) >> I2S_CFGR_BCLK_SEL_OP_SHIFT) + +/* + * FCLK_SEL_OP (RW) + * + * asserted to use external clk source + */ +#define I2S_CFGR_FCLK_SEL_OP_MASK (0x2000U) +#define I2S_CFGR_FCLK_SEL_OP_SHIFT (13U) +#define I2S_CFGR_FCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_FCLK_SEL_OP_SHIFT) & I2S_CFGR_FCLK_SEL_OP_MASK) +#define I2S_CFGR_FCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_FCLK_SEL_OP_MASK) >> I2S_CFGR_FCLK_SEL_OP_SHIFT) + +/* + * MCK_SEL_OP (RW) + * + * asserted to use external clk source + */ +#define I2S_CFGR_MCK_SEL_OP_MASK (0x1000U) +#define I2S_CFGR_MCK_SEL_OP_SHIFT (12U) +#define I2S_CFGR_MCK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_MCK_SEL_OP_SHIFT) & I2S_CFGR_MCK_SEL_OP_MASK) +#define I2S_CFGR_MCK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_MCK_SEL_OP_MASK) >> I2S_CFGR_MCK_SEL_OP_SHIFT) + +/* + * FRAME_EDGE (RW) + * + * The start edge of a frame + * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) + * 1: Rising edge indicates a new frame + */ +#define I2S_CFGR_FRAME_EDGE_MASK (0x800U) +#define I2S_CFGR_FRAME_EDGE_SHIFT (11U) +#define I2S_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << I2S_CFGR_FRAME_EDGE_SHIFT) & I2S_CFGR_FRAME_EDGE_MASK) +#define I2S_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & I2S_CFGR_FRAME_EDGE_MASK) >> I2S_CFGR_FRAME_EDGE_SHIFT) + +/* + * CH_MAX (RW) + * + * CH_MAX[3:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. + * It must be an even number, so CH_MAX[0] is always 0. + * 4'h2: 2 channels + * 4'h4: 4 channels + * ... + */ +#define I2S_CFGR_CH_MAX_MASK (0x7C0U) +#define I2S_CFGR_CH_MAX_SHIFT (6U) +#define I2S_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << I2S_CFGR_CH_MAX_SHIFT) & I2S_CFGR_CH_MAX_MASK) +#define I2S_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & I2S_CFGR_CH_MAX_MASK) >> I2S_CFGR_CH_MAX_SHIFT) + +/* + * TDM_EN (RW) + * + * TDM mode + * 0: not TDM mode + * 1: TDM mode + */ +#define I2S_CFGR_TDM_EN_MASK (0x20U) +#define I2S_CFGR_TDM_EN_SHIFT (5U) +#define I2S_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << I2S_CFGR_TDM_EN_SHIFT) & I2S_CFGR_TDM_EN_MASK) +#define I2S_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & I2S_CFGR_TDM_EN_MASK) >> I2S_CFGR_TDM_EN_SHIFT) + +/* + * STD (RW) + * + * I2S standard selection + * 00: I2S Philips standard. + * 01: MSB justified standard (left justified) + * 10: LSB justified standard (right justified) + * 11: PCM standard + * Note: For correct operation, these bits should be configured when the I2S is disabled. + */ +#define I2S_CFGR_STD_MASK (0x18U) +#define I2S_CFGR_STD_SHIFT (3U) +#define I2S_CFGR_STD_SET(x) (((uint32_t)(x) << I2S_CFGR_STD_SHIFT) & I2S_CFGR_STD_MASK) +#define I2S_CFGR_STD_GET(x) (((uint32_t)(x) & I2S_CFGR_STD_MASK) >> I2S_CFGR_STD_SHIFT) + +/* + * DATSIZ (RW) + * + * Data length to be transferred + * 00: 16-bit data length + * 01: 24-bit data length + * 10: 32-bit data length + * 11: Not allowed + * Note: For correct operation, these bits should be configured when the I2S is disabled. + */ +#define I2S_CFGR_DATSIZ_MASK (0x6U) +#define I2S_CFGR_DATSIZ_SHIFT (1U) +#define I2S_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_DATSIZ_SHIFT) & I2S_CFGR_DATSIZ_MASK) +#define I2S_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_DATSIZ_MASK) >> I2S_CFGR_DATSIZ_SHIFT) + +/* + * CHSIZ (RW) + * + * Channel length (number of bits per audio channel) + * 0: 16-bit wide + * 1: 32-bit wide + * The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + * Note: For correct operation, this bit should be configured when the I2S is disabled. + */ +#define I2S_CFGR_CHSIZ_MASK (0x1U) +#define I2S_CFGR_CHSIZ_SHIFT (0U) +#define I2S_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_CHSIZ_SHIFT) & I2S_CFGR_CHSIZ_MASK) +#define I2S_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_CHSIZ_MASK) >> I2S_CFGR_CHSIZ_SHIFT) + +/* Bitfield definition for register: MISC_CFGR */ +/* + * MCLK_GATEOFF (RW) + * + * Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. + */ +#define I2S_MISC_CFGR_MCLK_GATEOFF_MASK (0x2000U) +#define I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT (13U) +#define I2S_MISC_CFGR_MCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) +#define I2S_MISC_CFGR_MCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) >> I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) + +/* + * MCLKOE (RW) + * + * Master clock output to pad enable + * 0: Master clock output is disabled + * 1: Master clock output is enabled + * Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. + */ +#define I2S_MISC_CFGR_MCLKOE_MASK (0x1U) +#define I2S_MISC_CFGR_MCLKOE_SHIFT (0U) +#define I2S_MISC_CFGR_MCLKOE_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLKOE_SHIFT) & I2S_MISC_CFGR_MCLKOE_MASK) +#define I2S_MISC_CFGR_MCLKOE_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLKOE_MASK) >> I2S_MISC_CFGR_MCLKOE_SHIFT) + +/* Bitfield definition for register array: RXDSLOT */ +/* + * EN (RW) + * + */ +#define I2S_RXDSLOT_EN_MASK (0xFFFFU) +#define I2S_RXDSLOT_EN_SHIFT (0U) +#define I2S_RXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_RXDSLOT_EN_SHIFT) & I2S_RXDSLOT_EN_MASK) +#define I2S_RXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_RXDSLOT_EN_MASK) >> I2S_RXDSLOT_EN_SHIFT) + +/* Bitfield definition for register array: TXDSLOT */ +/* + * EN (RW) + * + */ +#define I2S_TXDSLOT_EN_MASK (0xFFFFU) +#define I2S_TXDSLOT_EN_SHIFT (0U) +#define I2S_TXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_TXDSLOT_EN_SHIFT) & I2S_TXDSLOT_EN_MASK) +#define I2S_TXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_TXDSLOT_EN_MASK) >> I2S_TXDSLOT_EN_SHIFT) + + + +/* RXD register group index macro definition */ +#define I2S_RXD_DATA0 (0UL) +#define I2S_RXD_DATA1 (1UL) +#define I2S_RXD_DATA2 (2UL) +#define I2S_RXD_DATA3 (3UL) + +/* TXD register group index macro definition */ +#define I2S_TXD_DATA0 (0UL) +#define I2S_TXD_DATA1 (1UL) +#define I2S_TXD_DATA2 (2UL) +#define I2S_TXD_DATA3 (3UL) + +/* RXDSLOT register group index macro definition */ +#define I2S_RXDSLOT_DATA0 (0UL) +#define I2S_RXDSLOT_DATA1 (1UL) +#define I2S_RXDSLOT_DATA2 (2UL) +#define I2S_RXDSLOT_DATA3 (3UL) + +/* TXDSLOT register group index macro definition */ +#define I2S_TXDSLOT_DATA0 (0UL) +#define I2S_TXDSLOT_DATA1 (1UL) +#define I2S_TXDSLOT_DATA2 (2UL) +#define I2S_TXDSLOT_DATA3 (3UL) + + +#endif /* HPM_I2S_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_jpeg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_jpeg_regs.h new file mode 100644 index 0000000000..b7bf305c6f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_jpeg_regs.h @@ -0,0 +1,1095 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_JPEG_H +#define HPM_JPEG_H + +typedef struct { + __RW uint32_t INDMA_MISC; /* 0x0: In DMA Misc Control Register */ + __RW uint32_t INDMABASE; /* 0x4: In DMA Buf Address */ + __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ + __RW uint32_t INDMA_CTRL0; /* 0xC: In DMA Buf Control 0 Register */ + __RW uint32_t INDMA_CTRL1; /* 0x10: In DMA Buf Control 1 Register */ + __RW uint32_t INXT_CMD; /* 0x14: In DMA Next Command Register */ + __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ + __RW uint32_t OUTDMA_MISC; /* 0x20: Out DMA Misc Control Register */ + __RW uint32_t OUTDMABASE; /* 0x24: Out DMA Buf Address */ + __R uint8_t RESERVED2[4]; /* 0x28 - 0x2B: Reserved */ + __RW uint32_t OUTDMA_CTRL0; /* 0x2C: Out DMA Buf Control 0 Register */ + __RW uint32_t OUTDMA_CTRL1; /* 0x30: Out DMA Buf Control 1 Register */ + __RW uint32_t ONXT_CMD; /* 0x34: Out DMA Next Command Register */ + __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t CFG; /* 0x40: Configuration Register */ + __RW uint32_t STAT; /* 0x44: Status Register */ + __RW uint32_t WIDTH; /* 0x48: Image width register */ + __RW uint32_t HEIGHT; /* 0x4C: Image height register */ + __RW uint32_t BUFADDR; /* 0x50: Buf Access Addr */ + __RW uint32_t BUFDATA; /* 0x54: Buf Access Data */ + __R uint32_t OUTDMACNT; /* 0x58: Out DMA Bytes Counter */ + __RW uint32_t CSC_COEF0; /* 0x5C: YUV2RGB coefficients Register 0 */ + __RW uint32_t CSC_COEF1; /* 0x60: YUV2RGB coefficients Register 1 */ + __RW uint32_t CSC_COEF2; /* 0x64: YUV2RGB coefficients Register 2 */ + __RW uint32_t RGB2YUV_COEF0; /* 0x68: RGB2YUV coefficients Register 0 */ + __RW uint32_t RGB2YUV_COEF1; /* 0x6C: RGB2YUV coefficients Register 1 */ + __RW uint32_t RGB2YUV_COEF2; /* 0x70: RGB2YUV coefficients Register 2 */ + __RW uint32_t RGB2YUV_COEF3; /* 0x74: RGB2YUV coefficients Register 3 */ + __RW uint32_t RGB2YUV_COEF4; /* 0x78: RGB2YUV coefficients Register 4 */ + __R uint8_t RESERVED4[8]; /* 0x7C - 0x83: Reserved */ + __RW uint32_t IMGREG1; /* 0x84: Image Control Register 1 */ + __RW uint32_t IMGREG2; /* 0x88: Image Control Register 2 */ + __RW uint32_t IMGREG3; /* 0x8C: Image Control Register 3 */ + __RW uint32_t IMGREG[4]; /* 0x90 - 0x9C: Image Control Register 40 */ +} JPEG_Type; + + +/* Bitfield definition for register: INDMA_MISC */ +/* + * ARQOS (RW) + * + * QoS for AXI read channel + */ +#define JPEG_INDMA_MISC_ARQOS_MASK (0x780000UL) +#define JPEG_INDMA_MISC_ARQOS_SHIFT (19U) +#define JPEG_INDMA_MISC_ARQOS_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_ARQOS_SHIFT) & JPEG_INDMA_MISC_ARQOS_MASK) +#define JPEG_INDMA_MISC_ARQOS_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_ARQOS_MASK) >> JPEG_INDMA_MISC_ARQOS_SHIFT) + +/* + * MAX_OT (RW) + * + * max_ot when input are RGB pixels. + * For 16 bits per pixel, it can be set as 4. + * For 32 bits per pixel, it will be set as 2. + */ +#define JPEG_INDMA_MISC_MAX_OT_MASK (0x78000UL) +#define JPEG_INDMA_MISC_MAX_OT_SHIFT (15U) +#define JPEG_INDMA_MISC_MAX_OT_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_MAX_OT_SHIFT) & JPEG_INDMA_MISC_MAX_OT_MASK) +#define JPEG_INDMA_MISC_MAX_OT_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_MAX_OT_MASK) >> JPEG_INDMA_MISC_MAX_OT_SHIFT) + +/* + * INB13_SWAP (RW) + * + * Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. + */ +#define JPEG_INDMA_MISC_INB13_SWAP_MASK (0x4000U) +#define JPEG_INDMA_MISC_INB13_SWAP_SHIFT (14U) +#define JPEG_INDMA_MISC_INB13_SWAP_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INB13_SWAP_SHIFT) & JPEG_INDMA_MISC_INB13_SWAP_MASK) +#define JPEG_INDMA_MISC_INB13_SWAP_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INB13_SWAP_MASK) >> JPEG_INDMA_MISC_INB13_SWAP_SHIFT) + +/* + * PACK_DIR (RW) + * + * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. + * 2'b00: no change {A3, A2, A1, A0} + * 2'b01: {A2, A3, A0, A1} + * 2'b10: {A1, A0, A3, A2} + * 2'b11: {A0, A1, A2, A3} + */ +#define JPEG_INDMA_MISC_PACK_DIR_MASK (0x3000U) +#define JPEG_INDMA_MISC_PACK_DIR_SHIFT (12U) +#define JPEG_INDMA_MISC_PACK_DIR_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_PACK_DIR_SHIFT) & JPEG_INDMA_MISC_PACK_DIR_MASK) +#define JPEG_INDMA_MISC_PACK_DIR_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_PACK_DIR_MASK) >> JPEG_INDMA_MISC_PACK_DIR_SHIFT) + +/* + * INDMA_RENEW (RW) + * + * Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. + */ +#define JPEG_INDMA_MISC_INDMA_RENEW_MASK (0x800U) +#define JPEG_INDMA_MISC_INDMA_RENEW_SHIFT (11U) +#define JPEG_INDMA_MISC_INDMA_RENEW_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INDMA_RENEW_SHIFT) & JPEG_INDMA_MISC_INDMA_RENEW_MASK) +#define JPEG_INDMA_MISC_INDMA_RENEW_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INDMA_RENEW_MASK) >> JPEG_INDMA_MISC_INDMA_RENEW_SHIFT) + +/* + * NXT_IRQ_EN (RW) + * + * In DMA Next Interrupt Enable + */ +#define JPEG_INDMA_MISC_NXT_IRQ_EN_MASK (0x400U) +#define JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT (10U) +#define JPEG_INDMA_MISC_NXT_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_NXT_IRQ_EN_MASK) +#define JPEG_INDMA_MISC_NXT_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_NXT_IRQ_EN_MASK) >> JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT) + +/* + * IN_DMA_DONE_IRQ_EN (RW) + * + * In DMA Done enable + */ +#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK (0x200U) +#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT (9U) +#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK) +#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK) >> JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT) + +/* + * AXI_ERR_IRQ_EN (RW) + * + * In DMA axi bus error inetrrupt enable + */ +#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK (0x100U) +#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT (8U) +#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK) +#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK) >> JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) + +/* + * IRQ_EN (RW) + * + * interrupt enable for all interrupt sources of In DMA module + */ +#define JPEG_INDMA_MISC_IRQ_EN_MASK (0x80U) +#define JPEG_INDMA_MISC_IRQ_EN_SHIFT (7U) +#define JPEG_INDMA_MISC_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_IRQ_EN_MASK) +#define JPEG_INDMA_MISC_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IRQ_EN_MASK) >> JPEG_INDMA_MISC_IRQ_EN_SHIFT) + +/* + * IN_DMA_ID (RW) + * + * 0: Pixel (In) + * 1: ECS (In) + * 2: Qmem + * 3: HuffEnc + * 4: HuffMin + * 5: HuffBase + * 6: HuffSymb + */ +#define JPEG_INDMA_MISC_IN_DMA_ID_MASK (0x70U) +#define JPEG_INDMA_MISC_IN_DMA_ID_SHIFT (4U) +#define JPEG_INDMA_MISC_IN_DMA_ID_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_ID_SHIFT) & JPEG_INDMA_MISC_IN_DMA_ID_MASK) +#define JPEG_INDMA_MISC_IN_DMA_ID_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_ID_MASK) >> JPEG_INDMA_MISC_IN_DMA_ID_SHIFT) + +/* + * IN_DMA_REQ (RW) + * + * Asserted to request DMA. Automatically clear after DMA is done. + */ +#define JPEG_INDMA_MISC_IN_DMA_REQ_MASK (0x8U) +#define JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT (3U) +#define JPEG_INDMA_MISC_IN_DMA_REQ_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT) & JPEG_INDMA_MISC_IN_DMA_REQ_MASK) +#define JPEG_INDMA_MISC_IN_DMA_REQ_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_REQ_MASK) >> JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT) + +/* + * INDMA2D (RW) + * + * Asserted if In_DMA_ID=Pixel. + */ +#define JPEG_INDMA_MISC_INDMA2D_MASK (0x4U) +#define JPEG_INDMA_MISC_INDMA2D_SHIFT (2U) +#define JPEG_INDMA_MISC_INDMA2D_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INDMA2D_SHIFT) & JPEG_INDMA_MISC_INDMA2D_MASK) +#define JPEG_INDMA_MISC_INDMA2D_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INDMA2D_MASK) >> JPEG_INDMA_MISC_INDMA2D_SHIFT) + +/* Bitfield definition for register: INDMABASE */ +/* + * ADDR (RW) + * + * Y plane (or Encoded Bit Plane) + */ +#define JPEG_INDMABASE_ADDR_MASK (0xFFFFFFFFUL) +#define JPEG_INDMABASE_ADDR_SHIFT (0U) +#define JPEG_INDMABASE_ADDR_SET(x) (((uint32_t)(x) << JPEG_INDMABASE_ADDR_SHIFT) & JPEG_INDMABASE_ADDR_MASK) +#define JPEG_INDMABASE_ADDR_GET(x) (((uint32_t)(x) & JPEG_INDMABASE_ADDR_MASK) >> JPEG_INDMABASE_ADDR_SHIFT) + +/* Bitfield definition for register: INDMA_CTRL0 */ +/* + * TTLEN (RW) + * + * Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. + */ +#define JPEG_INDMA_CTRL0_TTLEN_MASK (0xFFFF0000UL) +#define JPEG_INDMA_CTRL0_TTLEN_SHIFT (16U) +#define JPEG_INDMA_CTRL0_TTLEN_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL0_TTLEN_SHIFT) & JPEG_INDMA_CTRL0_TTLEN_MASK) +#define JPEG_INDMA_CTRL0_TTLEN_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL0_TTLEN_MASK) >> JPEG_INDMA_CTRL0_TTLEN_SHIFT) + +/* + * PITCH (RW) + * + * Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. + */ +#define JPEG_INDMA_CTRL0_PITCH_MASK (0xFFFFU) +#define JPEG_INDMA_CTRL0_PITCH_SHIFT (0U) +#define JPEG_INDMA_CTRL0_PITCH_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL0_PITCH_SHIFT) & JPEG_INDMA_CTRL0_PITCH_MASK) +#define JPEG_INDMA_CTRL0_PITCH_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL0_PITCH_MASK) >> JPEG_INDMA_CTRL0_PITCH_SHIFT) + +/* Bitfield definition for register: INDMA_CTRL1 */ +/* + * ROWLEN (RW) + * + * Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] + */ +#define JPEG_INDMA_CTRL1_ROWLEN_MASK (0xFFFFU) +#define JPEG_INDMA_CTRL1_ROWLEN_SHIFT (0U) +#define JPEG_INDMA_CTRL1_ROWLEN_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL1_ROWLEN_SHIFT) & JPEG_INDMA_CTRL1_ROWLEN_MASK) +#define JPEG_INDMA_CTRL1_ROWLEN_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL1_ROWLEN_MASK) >> JPEG_INDMA_CTRL1_ROWLEN_SHIFT) + +/* Bitfield definition for register: INXT_CMD */ +/* + * ADDR (RW) + * + * The address pointing to the next command + */ +#define JPEG_INXT_CMD_ADDR_MASK (0xFFFFFFFCUL) +#define JPEG_INXT_CMD_ADDR_SHIFT (2U) +#define JPEG_INXT_CMD_ADDR_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_ADDR_SHIFT) & JPEG_INXT_CMD_ADDR_MASK) +#define JPEG_INXT_CMD_ADDR_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_ADDR_MASK) >> JPEG_INXT_CMD_ADDR_SHIFT) + +/* + * OP_VALID (RW) + * + * asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. + */ +#define JPEG_INXT_CMD_OP_VALID_MASK (0x2U) +#define JPEG_INXT_CMD_OP_VALID_SHIFT (1U) +#define JPEG_INXT_CMD_OP_VALID_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_OP_VALID_SHIFT) & JPEG_INXT_CMD_OP_VALID_MASK) +#define JPEG_INXT_CMD_OP_VALID_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_OP_VALID_MASK) >> JPEG_INXT_CMD_OP_VALID_SHIFT) + +/* + * EN (RW) + * + * NXTCMD phase Enable Bit + */ +#define JPEG_INXT_CMD_EN_MASK (0x1U) +#define JPEG_INXT_CMD_EN_SHIFT (0U) +#define JPEG_INXT_CMD_EN_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_EN_SHIFT) & JPEG_INXT_CMD_EN_MASK) +#define JPEG_INXT_CMD_EN_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_EN_MASK) >> JPEG_INXT_CMD_EN_SHIFT) + +/* Bitfield definition for register: OUTDMA_MISC */ +/* + * AWQOS (RW) + * + */ +#define JPEG_OUTDMA_MISC_AWQOS_MASK (0x3C000UL) +#define JPEG_OUTDMA_MISC_AWQOS_SHIFT (14U) +#define JPEG_OUTDMA_MISC_AWQOS_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_AWQOS_SHIFT) & JPEG_OUTDMA_MISC_AWQOS_MASK) +#define JPEG_OUTDMA_MISC_AWQOS_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_AWQOS_MASK) >> JPEG_OUTDMA_MISC_AWQOS_SHIFT) + +/* + * PACK_DIR (RW) + * + * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. + * 2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) + * 2'b01: {A2, A3, A0, A1} + * 2'b10: {A1, A0, A3, A2} + * 2'b11: {A0, A1, A2, A3} + */ +#define JPEG_OUTDMA_MISC_PACK_DIR_MASK (0x3000U) +#define JPEG_OUTDMA_MISC_PACK_DIR_SHIFT (12U) +#define JPEG_OUTDMA_MISC_PACK_DIR_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_PACK_DIR_SHIFT) & JPEG_OUTDMA_MISC_PACK_DIR_MASK) +#define JPEG_OUTDMA_MISC_PACK_DIR_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_PACK_DIR_MASK) >> JPEG_OUTDMA_MISC_PACK_DIR_SHIFT) + +/* + * EN_OUTCNT (RW) + * + * Enable output counter (unit as bytes) + */ +#define JPEG_OUTDMA_MISC_EN_OUTCNT_MASK (0x800U) +#define JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT (11U) +#define JPEG_OUTDMA_MISC_EN_OUTCNT_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT) & JPEG_OUTDMA_MISC_EN_OUTCNT_MASK) +#define JPEG_OUTDMA_MISC_EN_OUTCNT_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_EN_OUTCNT_MASK) >> JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT) + +/* + * INI_OUTCNT (RW) + * + * Asserted to ini output counter + */ +#define JPEG_OUTDMA_MISC_INI_OUTCNT_MASK (0x400U) +#define JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT (10U) +#define JPEG_OUTDMA_MISC_INI_OUTCNT_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT) & JPEG_OUTDMA_MISC_INI_OUTCNT_MASK) +#define JPEG_OUTDMA_MISC_INI_OUTCNT_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_INI_OUTCNT_MASK) >> JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT) + +/* + * ADD_ODMA_ENDINGS (RW) + * + * Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. + */ +#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK (0x200U) +#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT (9U) +#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT) & JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK) +#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK) >> JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT) + +/* + * NXT_IRQ_EN (RW) + * + * Out DMA Next Interrupt Enable + */ +#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK (0x100U) +#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT (8U) +#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK) +#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT) + +/* + * OUT_DMA_DONE_IRQ_EN (RW) + * + * Out DMA Done interrupt Enable + */ +#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK (0x80U) +#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT (7U) +#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK) +#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT) + +/* + * AXI_ERR_IRQ_EN (RW) + * + * Out DMA axi bus error inetrrupt enable + */ +#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK (0x40U) +#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT (6U) +#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK) +#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) + +/* + * IRQ_EN (RW) + * + * interrupt enable for all interrupt sources of Out DMA module + */ +#define JPEG_OUTDMA_MISC_IRQ_EN_MASK (0x20U) +#define JPEG_OUTDMA_MISC_IRQ_EN_SHIFT (5U) +#define JPEG_OUTDMA_MISC_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_IRQ_EN_MASK) +#define JPEG_OUTDMA_MISC_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_IRQ_EN_SHIFT) + +/* + * OUT_DMA_ID (RW) + * + * 0: Pixel (Out) + * 1: ECS (Out) + */ +#define JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK (0x10U) +#define JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT (4U) +#define JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK) +#define JPEG_OUTDMA_MISC_OUT_DMA_ID_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT) + +/* + * OUT_DMA_REQ (RW) + * + * Asserted to enable Out DMA request + */ +#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK (0x8U) +#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT (3U) +#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK) +#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT) + +/* + * OUTDMA2D (RW) + * + * Asserted if Out_DMA_ID==Pixel + */ +#define JPEG_OUTDMA_MISC_OUTDMA2D_MASK (0x4U) +#define JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT (2U) +#define JPEG_OUTDMA_MISC_OUTDMA2D_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT) & JPEG_OUTDMA_MISC_OUTDMA2D_MASK) +#define JPEG_OUTDMA_MISC_OUTDMA2D_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUTDMA2D_MASK) >> JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT) + +/* Bitfield definition for register: OUTDMABASE */ +/* + * ADDR (RW) + * + * Y plane (or Encoded Bit Plane) + */ +#define JPEG_OUTDMABASE_ADDR_MASK (0xFFFFFFFFUL) +#define JPEG_OUTDMABASE_ADDR_SHIFT (0U) +#define JPEG_OUTDMABASE_ADDR_SET(x) (((uint32_t)(x) << JPEG_OUTDMABASE_ADDR_SHIFT) & JPEG_OUTDMABASE_ADDR_MASK) +#define JPEG_OUTDMABASE_ADDR_GET(x) (((uint32_t)(x) & JPEG_OUTDMABASE_ADDR_MASK) >> JPEG_OUTDMABASE_ADDR_SHIFT) + +/* Bitfield definition for register: OUTDMA_CTRL0 */ +/* + * TTLEN (RW) + * + * Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. + */ +#define JPEG_OUTDMA_CTRL0_TTLEN_MASK (0xFFFF0000UL) +#define JPEG_OUTDMA_CTRL0_TTLEN_SHIFT (16U) +#define JPEG_OUTDMA_CTRL0_TTLEN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL0_TTLEN_SHIFT) & JPEG_OUTDMA_CTRL0_TTLEN_MASK) +#define JPEG_OUTDMA_CTRL0_TTLEN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL0_TTLEN_MASK) >> JPEG_OUTDMA_CTRL0_TTLEN_SHIFT) + +/* + * PITCH (RW) + * + * Pitch between the starting point of Rows when Out_DMA_ID==Pixel + */ +#define JPEG_OUTDMA_CTRL0_PITCH_MASK (0xFFFFU) +#define JPEG_OUTDMA_CTRL0_PITCH_SHIFT (0U) +#define JPEG_OUTDMA_CTRL0_PITCH_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL0_PITCH_SHIFT) & JPEG_OUTDMA_CTRL0_PITCH_MASK) +#define JPEG_OUTDMA_CTRL0_PITCH_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL0_PITCH_MASK) >> JPEG_OUTDMA_CTRL0_PITCH_SHIFT) + +/* Bitfield definition for register: OUTDMA_CTRL1 */ +/* + * ROWLEN (RW) + * + * Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] + */ +#define JPEG_OUTDMA_CTRL1_ROWLEN_MASK (0xFFFFU) +#define JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT (0U) +#define JPEG_OUTDMA_CTRL1_ROWLEN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT) & JPEG_OUTDMA_CTRL1_ROWLEN_MASK) +#define JPEG_OUTDMA_CTRL1_ROWLEN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL1_ROWLEN_MASK) >> JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT) + +/* Bitfield definition for register: ONXT_CMD */ +/* + * ADDR (RW) + * + * The address pointing to the next command + */ +#define JPEG_ONXT_CMD_ADDR_MASK (0xFFFFFFFCUL) +#define JPEG_ONXT_CMD_ADDR_SHIFT (2U) +#define JPEG_ONXT_CMD_ADDR_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_ADDR_SHIFT) & JPEG_ONXT_CMD_ADDR_MASK) +#define JPEG_ONXT_CMD_ADDR_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_ADDR_MASK) >> JPEG_ONXT_CMD_ADDR_SHIFT) + +/* + * OP_VALID (RW) + * + * asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. + */ +#define JPEG_ONXT_CMD_OP_VALID_MASK (0x2U) +#define JPEG_ONXT_CMD_OP_VALID_SHIFT (1U) +#define JPEG_ONXT_CMD_OP_VALID_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_OP_VALID_SHIFT) & JPEG_ONXT_CMD_OP_VALID_MASK) +#define JPEG_ONXT_CMD_OP_VALID_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_OP_VALID_MASK) >> JPEG_ONXT_CMD_OP_VALID_SHIFT) + +/* + * EN (RW) + * + * NXTCMD phase Enable Bit + */ +#define JPEG_ONXT_CMD_EN_MASK (0x1U) +#define JPEG_ONXT_CMD_EN_SHIFT (0U) +#define JPEG_ONXT_CMD_EN_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_EN_SHIFT) & JPEG_ONXT_CMD_EN_MASK) +#define JPEG_ONXT_CMD_EN_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_EN_MASK) >> JPEG_ONXT_CMD_EN_SHIFT) + +/* Bitfield definition for register: CFG */ +/* + * JD_UVSWAP (RW) + * + * Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. + */ +#define JPEG_CFG_JD_UVSWAP_MASK (0x400000UL) +#define JPEG_CFG_JD_UVSWAP_SHIFT (22U) +#define JPEG_CFG_JD_UVSWAP_SET(x) (((uint32_t)(x) << JPEG_CFG_JD_UVSWAP_SHIFT) & JPEG_CFG_JD_UVSWAP_MASK) +#define JPEG_CFG_JD_UVSWAP_GET(x) (((uint32_t)(x) & JPEG_CFG_JD_UVSWAP_MASK) >> JPEG_CFG_JD_UVSWAP_SHIFT) + +/* + * CFG_IPATH_SEL (RW) + * + * 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V + * 2'b01:ARGB8888, byte sequence as B,G,R,A + * 2'b10:RGB565, byte sequence as B,R + * 2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 + */ +#define JPEG_CFG_CFG_IPATH_SEL_MASK (0x300000UL) +#define JPEG_CFG_CFG_IPATH_SEL_SHIFT (20U) +#define JPEG_CFG_CFG_IPATH_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_CFG_IPATH_SEL_SHIFT) & JPEG_CFG_CFG_IPATH_SEL_MASK) +#define JPEG_CFG_CFG_IPATH_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_CFG_IPATH_SEL_MASK) >> JPEG_CFG_CFG_IPATH_SEL_SHIFT) + +/* + * CODEC_OVER_IRQ_EN (RW) + * + * The jpg endec process done interrupt enable + */ +#define JPEG_CFG_CODEC_OVER_IRQ_EN_MASK (0x80000UL) +#define JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT (19U) +#define JPEG_CFG_CODEC_OVER_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT) & JPEG_CFG_CODEC_OVER_IRQ_EN_MASK) +#define JPEG_CFG_CODEC_OVER_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_CODEC_OVER_IRQ_EN_MASK) >> JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT) + +/* + * CODEC_RESTART_ERR_IRQ_EN (RW) + * + * The jpg endec restart error interrupt enable + */ +#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK (0x40000UL) +#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT (18U) +#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT) & JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK) +#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK) >> JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT) + +/* + * MEM_DEBUG_CLK_SEL (RW) + * + * asserted to use APB clock, so that the memory contents could be read out through APB interface + */ +#define JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK (0x20000UL) +#define JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT (17U) +#define JPEG_CFG_MEM_DEBUG_CLK_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT) & JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK) +#define JPEG_CFG_MEM_DEBUG_CLK_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK) >> JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT) + +/* + * CLKGATE (RW) + * + * Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. + */ +#define JPEG_CFG_CLKGATE_MASK (0x200U) +#define JPEG_CFG_CLKGATE_SHIFT (9U) +#define JPEG_CFG_CLKGATE_SET(x) (((uint32_t)(x) << JPEG_CFG_CLKGATE_SHIFT) & JPEG_CFG_CLKGATE_MASK) +#define JPEG_CFG_CLKGATE_GET(x) (((uint32_t)(x) & JPEG_CFG_CLKGATE_MASK) >> JPEG_CFG_CLKGATE_SHIFT) + +/* + * CFG_OPATH_SEL (RW) + * + * 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V + * 2'b01:ARGB8888, byte sequence as B,G,R,A + * 2'b10:RGB565, byte sequence as R,B + * 2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 + */ +#define JPEG_CFG_CFG_OPATH_SEL_MASK (0x180U) +#define JPEG_CFG_CFG_OPATH_SEL_SHIFT (7U) +#define JPEG_CFG_CFG_OPATH_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_CFG_OPATH_SEL_SHIFT) & JPEG_CFG_CFG_OPATH_SEL_MASK) +#define JPEG_CFG_CFG_OPATH_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_CFG_OPATH_SEL_MASK) >> JPEG_CFG_CFG_OPATH_SEL_SHIFT) + +/* + * JDATA_FORMAT (RW) + * + * 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU + * 3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU + * 3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU + * 3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU + * 3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU + * Others: Undefined + */ +#define JPEG_CFG_JDATA_FORMAT_MASK (0x70U) +#define JPEG_CFG_JDATA_FORMAT_SHIFT (4U) +#define JPEG_CFG_JDATA_FORMAT_SET(x) (((uint32_t)(x) << JPEG_CFG_JDATA_FORMAT_SHIFT) & JPEG_CFG_JDATA_FORMAT_MASK) +#define JPEG_CFG_JDATA_FORMAT_GET(x) (((uint32_t)(x) & JPEG_CFG_JDATA_FORMAT_MASK) >> JPEG_CFG_JDATA_FORMAT_SHIFT) + +/* + * JPEG_SFTRST (RW) + * + * Software Reset + */ +#define JPEG_CFG_JPEG_SFTRST_MASK (0x8U) +#define JPEG_CFG_JPEG_SFTRST_SHIFT (3U) +#define JPEG_CFG_JPEG_SFTRST_SET(x) (((uint32_t)(x) << JPEG_CFG_JPEG_SFTRST_SHIFT) & JPEG_CFG_JPEG_SFTRST_MASK) +#define JPEG_CFG_JPEG_SFTRST_GET(x) (((uint32_t)(x) & JPEG_CFG_JPEG_SFTRST_MASK) >> JPEG_CFG_JPEG_SFTRST_SHIFT) + +/* + * START (RW) + * + * Asserted if to start a new encoder/decoder conversion. + * It will at first stop the inner JPEG module, then reset it, and then re-run it. + * It is a different mode from DMA phase mode. + * It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. + * Auto clear. + */ +#define JPEG_CFG_START_MASK (0x4U) +#define JPEG_CFG_START_SHIFT (2U) +#define JPEG_CFG_START_SET(x) (((uint32_t)(x) << JPEG_CFG_START_SHIFT) & JPEG_CFG_START_MASK) +#define JPEG_CFG_START_GET(x) (((uint32_t)(x) & JPEG_CFG_START_MASK) >> JPEG_CFG_START_SHIFT) + +/* + * MODE (RW) + * + * 1: decoder, 0:encoder + */ +#define JPEG_CFG_MODE_MASK (0x2U) +#define JPEG_CFG_MODE_SHIFT (1U) +#define JPEG_CFG_MODE_SET(x) (((uint32_t)(x) << JPEG_CFG_MODE_SHIFT) & JPEG_CFG_MODE_MASK) +#define JPEG_CFG_MODE_GET(x) (((uint32_t)(x) & JPEG_CFG_MODE_MASK) >> JPEG_CFG_MODE_SHIFT) + +/* + * JPEG_EN (RW) + * + * 1b - Enabled + */ +#define JPEG_CFG_JPEG_EN_MASK (0x1U) +#define JPEG_CFG_JPEG_EN_SHIFT (0U) +#define JPEG_CFG_JPEG_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_JPEG_EN_SHIFT) & JPEG_CFG_JPEG_EN_MASK) +#define JPEG_CFG_JPEG_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_JPEG_EN_MASK) >> JPEG_CFG_JPEG_EN_SHIFT) + +/* Bitfield definition for register: STAT */ +/* + * BUSY (ROI) + * + * When 1 means that the module is busy doing conversion and data transfer. + */ +#define JPEG_STAT_BUSY_MASK (0x80000000UL) +#define JPEG_STAT_BUSY_SHIFT (31U) +#define JPEG_STAT_BUSY_GET(x) (((uint32_t)(x) & JPEG_STAT_BUSY_MASK) >> JPEG_STAT_BUSY_SHIFT) + +/* + * AXI_ERR_ID (ROI) + * + * the axi err id + */ +#define JPEG_STAT_AXI_ERR_ID_MASK (0x3C00U) +#define JPEG_STAT_AXI_ERR_ID_SHIFT (10U) +#define JPEG_STAT_AXI_ERR_ID_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_ERR_ID_MASK) >> JPEG_STAT_AXI_ERR_ID_SHIFT) + +/* + * AXI_READ_ERR (ROI) + * + * in-dma axi bus error + */ +#define JPEG_STAT_AXI_READ_ERR_MASK (0x200U) +#define JPEG_STAT_AXI_READ_ERR_SHIFT (9U) +#define JPEG_STAT_AXI_READ_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_READ_ERR_MASK) >> JPEG_STAT_AXI_READ_ERR_SHIFT) + +/* + * AXI_WRITE_ERR (ROI) + * + * out-dma axi bus error + */ +#define JPEG_STAT_AXI_WRITE_ERR_MASK (0x100U) +#define JPEG_STAT_AXI_WRITE_ERR_SHIFT (8U) +#define JPEG_STAT_AXI_WRITE_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_WRITE_ERR_MASK) >> JPEG_STAT_AXI_WRITE_ERR_SHIFT) + +/* + * AXI_ERR (W1C) + * + * axi bus error + */ +#define JPEG_STAT_AXI_ERR_MASK (0x80U) +#define JPEG_STAT_AXI_ERR_SHIFT (7U) +#define JPEG_STAT_AXI_ERR_SET(x) (((uint32_t)(x) << JPEG_STAT_AXI_ERR_SHIFT) & JPEG_STAT_AXI_ERR_MASK) +#define JPEG_STAT_AXI_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_ERR_MASK) >> JPEG_STAT_AXI_ERR_SHIFT) + +/* + * ONXT_IRQ (W1C) + * + * OutDMA next interrupt + */ +#define JPEG_STAT_ONXT_IRQ_MASK (0x40U) +#define JPEG_STAT_ONXT_IRQ_SHIFT (6U) +#define JPEG_STAT_ONXT_IRQ_SET(x) (((uint32_t)(x) << JPEG_STAT_ONXT_IRQ_SHIFT) & JPEG_STAT_ONXT_IRQ_MASK) +#define JPEG_STAT_ONXT_IRQ_GET(x) (((uint32_t)(x) & JPEG_STAT_ONXT_IRQ_MASK) >> JPEG_STAT_ONXT_IRQ_SHIFT) + +/* + * INXT_IRQ (W1C) + * + * InDMA next interrupt + */ +#define JPEG_STAT_INXT_IRQ_MASK (0x20U) +#define JPEG_STAT_INXT_IRQ_SHIFT (5U) +#define JPEG_STAT_INXT_IRQ_SET(x) (((uint32_t)(x) << JPEG_STAT_INXT_IRQ_SHIFT) & JPEG_STAT_INXT_IRQ_MASK) +#define JPEG_STAT_INXT_IRQ_GET(x) (((uint32_t)(x) & JPEG_STAT_INXT_IRQ_MASK) >> JPEG_STAT_INXT_IRQ_SHIFT) + +/* + * OUT_DMA_TRANSFER_DONE (W1C) + * + * OutDMA process done + */ +#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK (0x10U) +#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT (4U) +#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_SET(x) (((uint32_t)(x) << JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT) & JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK) +#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_GET(x) (((uint32_t)(x) & JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK) >> JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT) + +/* + * IN_DMA_TRANSFER_DONE (W1C) + * + * InDMA process done + */ +#define JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK (0x8U) +#define JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT (3U) +#define JPEG_STAT_IN_DMA_TRANSFER_DONE_SET(x) (((uint32_t)(x) << JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT) & JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK) +#define JPEG_STAT_IN_DMA_TRANSFER_DONE_GET(x) (((uint32_t)(x) & JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK) >> JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT) + +/* + * CODEC_OVER (W1C) + * + * Coding or decoding process is over. DMA is not included. + * The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. + */ +#define JPEG_STAT_CODEC_OVER_MASK (0x4U) +#define JPEG_STAT_CODEC_OVER_SHIFT (2U) +#define JPEG_STAT_CODEC_OVER_SET(x) (((uint32_t)(x) << JPEG_STAT_CODEC_OVER_SHIFT) & JPEG_STAT_CODEC_OVER_MASK) +#define JPEG_STAT_CODEC_OVER_GET(x) (((uint32_t)(x) & JPEG_STAT_CODEC_OVER_MASK) >> JPEG_STAT_CODEC_OVER_SHIFT) + +/* + * RESTART_MARKER_ERROR (W1C) + * + * codec restart marker error interrupt + */ +#define JPEG_STAT_RESTART_MARKER_ERROR_MASK (0x2U) +#define JPEG_STAT_RESTART_MARKER_ERROR_SHIFT (1U) +#define JPEG_STAT_RESTART_MARKER_ERROR_SET(x) (((uint32_t)(x) << JPEG_STAT_RESTART_MARKER_ERROR_SHIFT) & JPEG_STAT_RESTART_MARKER_ERROR_MASK) +#define JPEG_STAT_RESTART_MARKER_ERROR_GET(x) (((uint32_t)(x) & JPEG_STAT_RESTART_MARKER_ERROR_MASK) >> JPEG_STAT_RESTART_MARKER_ERROR_SHIFT) + +/* Bitfield definition for register: WIDTH */ +/* + * IMG (RW) + * + * Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) + */ +#define JPEG_WIDTH_IMG_MASK (0xFFFFU) +#define JPEG_WIDTH_IMG_SHIFT (0U) +#define JPEG_WIDTH_IMG_SET(x) (((uint32_t)(x) << JPEG_WIDTH_IMG_SHIFT) & JPEG_WIDTH_IMG_MASK) +#define JPEG_WIDTH_IMG_GET(x) (((uint32_t)(x) & JPEG_WIDTH_IMG_MASK) >> JPEG_WIDTH_IMG_SHIFT) + +/* Bitfield definition for register: HEIGHT */ +/* + * IMG (RW) + * + * Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) + */ +#define JPEG_HEIGHT_IMG_MASK (0xFFFFU) +#define JPEG_HEIGHT_IMG_SHIFT (0U) +#define JPEG_HEIGHT_IMG_SET(x) (((uint32_t)(x) << JPEG_HEIGHT_IMG_SHIFT) & JPEG_HEIGHT_IMG_MASK) +#define JPEG_HEIGHT_IMG_GET(x) (((uint32_t)(x) & JPEG_HEIGHT_IMG_MASK) >> JPEG_HEIGHT_IMG_SHIFT) + +/* Bitfield definition for register: BUFADDR */ +/* + * ADDR (RW) + * + * ADDR[31:28] denotes the buffer type: + * 0x2: Qmem + * 0x3: HuffEnc + * 0x4: HuffMin + * 0x5: HuffBase + * 0x6: HuffSymb + * ADDR[27:0] is the address inside the buffer + */ +#define JPEG_BUFADDR_ADDR_MASK (0xFFFFFFFFUL) +#define JPEG_BUFADDR_ADDR_SHIFT (0U) +#define JPEG_BUFADDR_ADDR_SET(x) (((uint32_t)(x) << JPEG_BUFADDR_ADDR_SHIFT) & JPEG_BUFADDR_ADDR_MASK) +#define JPEG_BUFADDR_ADDR_GET(x) (((uint32_t)(x) & JPEG_BUFADDR_ADDR_MASK) >> JPEG_BUFADDR_ADDR_SHIFT) + +/* Bitfield definition for register: BUFDATA */ +/* + * DATA (RW) + * + * The data write-to/read-from buffer. + * The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. + */ +#define JPEG_BUFDATA_DATA_MASK (0xFFFFFFFFUL) +#define JPEG_BUFDATA_DATA_SHIFT (0U) +#define JPEG_BUFDATA_DATA_SET(x) (((uint32_t)(x) << JPEG_BUFDATA_DATA_SHIFT) & JPEG_BUFDATA_DATA_MASK) +#define JPEG_BUFDATA_DATA_GET(x) (((uint32_t)(x) & JPEG_BUFDATA_DATA_MASK) >> JPEG_BUFDATA_DATA_SHIFT) + +/* Bitfield definition for register: OUTDMACNT */ +/* + * VAL (ROI) + * + * The out DMA counter + */ +#define JPEG_OUTDMACNT_VAL_MASK (0xFFFFFFFFUL) +#define JPEG_OUTDMACNT_VAL_SHIFT (0U) +#define JPEG_OUTDMACNT_VAL_GET(x) (((uint32_t)(x) & JPEG_OUTDMACNT_VAL_MASK) >> JPEG_OUTDMACNT_VAL_SHIFT) + +/* Bitfield definition for register: CSC_COEF0 */ +/* + * YCBCR_MODE (RW) + * + * This bit changes the behavior when performing U/V converting. + * 0b - Converting YUV to RGB data + * 1b - Converting YCbCr to RGB data + */ +#define JPEG_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) +#define JPEG_CSC_COEF0_YCBCR_MODE_SHIFT (31U) +#define JPEG_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_YCBCR_MODE_SHIFT) & JPEG_CSC_COEF0_YCBCR_MODE_MASK) +#define JPEG_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_YCBCR_MODE_MASK) >> JPEG_CSC_COEF0_YCBCR_MODE_SHIFT) + +/* + * ENABLE (RW) + * + * Enable the CSC unit. + * 0b - The CSC is bypassed + * 1b - The CSC is enabled + */ +#define JPEG_CSC_COEF0_ENABLE_MASK (0x40000000UL) +#define JPEG_CSC_COEF0_ENABLE_SHIFT (30U) +#define JPEG_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_ENABLE_SHIFT) & JPEG_CSC_COEF0_ENABLE_MASK) +#define JPEG_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_ENABLE_MASK) >> JPEG_CSC_COEF0_ENABLE_SHIFT) + +/* + * C0 (RW) + * + * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + */ +#define JPEG_CSC_COEF0_C0_MASK (0x1FFC0000UL) +#define JPEG_CSC_COEF0_C0_SHIFT (18U) +#define JPEG_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_C0_SHIFT) & JPEG_CSC_COEF0_C0_MASK) +#define JPEG_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_C0_MASK) >> JPEG_CSC_COEF0_C0_SHIFT) + +/* + * UV_OFFSET (RW) + * + * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. + * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + */ +#define JPEG_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) +#define JPEG_CSC_COEF0_UV_OFFSET_SHIFT (9U) +#define JPEG_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_UV_OFFSET_SHIFT) & JPEG_CSC_COEF0_UV_OFFSET_MASK) +#define JPEG_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_UV_OFFSET_MASK) >> JPEG_CSC_COEF0_UV_OFFSET_SHIFT) + +/* + * Y_OFFSET (RW) + * + * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is + * typically -16 (0x1F0). + */ +#define JPEG_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) +#define JPEG_CSC_COEF0_Y_OFFSET_SHIFT (0U) +#define JPEG_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_Y_OFFSET_SHIFT) & JPEG_CSC_COEF0_Y_OFFSET_MASK) +#define JPEG_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_Y_OFFSET_MASK) >> JPEG_CSC_COEF0_Y_OFFSET_SHIFT) + +/* Bitfield definition for register: CSC_COEF1 */ +/* + * C1 (RW) + * + * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + */ +#define JPEG_CSC_COEF1_C1_MASK (0x7FF0000UL) +#define JPEG_CSC_COEF1_C1_SHIFT (16U) +#define JPEG_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF1_C1_SHIFT) & JPEG_CSC_COEF1_C1_MASK) +#define JPEG_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF1_C1_MASK) >> JPEG_CSC_COEF1_C1_SHIFT) + +/* + * C4 (RW) + * + * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + */ +#define JPEG_CSC_COEF1_C4_MASK (0x7FFU) +#define JPEG_CSC_COEF1_C4_SHIFT (0U) +#define JPEG_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF1_C4_SHIFT) & JPEG_CSC_COEF1_C4_MASK) +#define JPEG_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF1_C4_MASK) >> JPEG_CSC_COEF1_C4_SHIFT) + +/* Bitfield definition for register: CSC_COEF2 */ +/* + * C2 (RW) + * + * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + */ +#define JPEG_CSC_COEF2_C2_MASK (0x7FF0000UL) +#define JPEG_CSC_COEF2_C2_SHIFT (16U) +#define JPEG_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF2_C2_SHIFT) & JPEG_CSC_COEF2_C2_MASK) +#define JPEG_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF2_C2_MASK) >> JPEG_CSC_COEF2_C2_SHIFT) + +/* + * C3 (RW) + * + * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + */ +#define JPEG_CSC_COEF2_C3_MASK (0x7FFU) +#define JPEG_CSC_COEF2_C3_SHIFT (0U) +#define JPEG_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF2_C3_SHIFT) & JPEG_CSC_COEF2_C3_MASK) +#define JPEG_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF2_C3_MASK) >> JPEG_CSC_COEF2_C3_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF0 */ +/* + * YCBCR_MODE (RW) + * + * Asserted to use YCrCb mode. Must be assigned as 1. + */ +#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK (0x80000000UL) +#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT (31U) +#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) & JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK) +#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK) >> JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) + +/* + * ENABLE (RW) + * + * Asserted to enable this RGB2YCbCr CSC stage + */ +#define JPEG_RGB2YUV_COEF0_ENABLE_MASK (0x40000000UL) +#define JPEG_RGB2YUV_COEF0_ENABLE_SHIFT (30U) +#define JPEG_RGB2YUV_COEF0_ENABLE_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_ENABLE_SHIFT) & JPEG_RGB2YUV_COEF0_ENABLE_MASK) +#define JPEG_RGB2YUV_COEF0_ENABLE_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_ENABLE_MASK) >> JPEG_RGB2YUV_COEF0_ENABLE_SHIFT) + +/* + * C0 (RW) + * + * CSC parameters C0 + */ +#define JPEG_RGB2YUV_COEF0_C0_MASK (0x1FFC0000UL) +#define JPEG_RGB2YUV_COEF0_C0_SHIFT (18U) +#define JPEG_RGB2YUV_COEF0_C0_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_C0_SHIFT) & JPEG_RGB2YUV_COEF0_C0_MASK) +#define JPEG_RGB2YUV_COEF0_C0_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_C0_MASK) >> JPEG_RGB2YUV_COEF0_C0_SHIFT) + +/* + * UV_OFFSET (RW) + * + * CSC parameters UV_OFFSET + */ +#define JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK (0x3FE00UL) +#define JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT (9U) +#define JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT) & JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK) +#define JPEG_RGB2YUV_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK) >> JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT) + +/* + * Y_OFFSET (RW) + * + * CSC parameters Y_OFFSET + */ +#define JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK (0x1FFU) +#define JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT (0U) +#define JPEG_RGB2YUV_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT) & JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK) +#define JPEG_RGB2YUV_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK) >> JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF1 */ +/* + * C1 (RW) + * + * CSC parameters C1 + */ +#define JPEG_RGB2YUV_COEF1_C1_MASK (0x7FF0000UL) +#define JPEG_RGB2YUV_COEF1_C1_SHIFT (16U) +#define JPEG_RGB2YUV_COEF1_C1_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF1_C1_SHIFT) & JPEG_RGB2YUV_COEF1_C1_MASK) +#define JPEG_RGB2YUV_COEF1_C1_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF1_C1_MASK) >> JPEG_RGB2YUV_COEF1_C1_SHIFT) + +/* + * C4 (RW) + * + * CSC parameters C4 + */ +#define JPEG_RGB2YUV_COEF1_C4_MASK (0x7FFU) +#define JPEG_RGB2YUV_COEF1_C4_SHIFT (0U) +#define JPEG_RGB2YUV_COEF1_C4_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF1_C4_SHIFT) & JPEG_RGB2YUV_COEF1_C4_MASK) +#define JPEG_RGB2YUV_COEF1_C4_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF1_C4_MASK) >> JPEG_RGB2YUV_COEF1_C4_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF2 */ +/* + * C2 (RW) + * + * CSC parameters C2 + */ +#define JPEG_RGB2YUV_COEF2_C2_MASK (0x7FF0000UL) +#define JPEG_RGB2YUV_COEF2_C2_SHIFT (16U) +#define JPEG_RGB2YUV_COEF2_C2_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF2_C2_SHIFT) & JPEG_RGB2YUV_COEF2_C2_MASK) +#define JPEG_RGB2YUV_COEF2_C2_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF2_C2_MASK) >> JPEG_RGB2YUV_COEF2_C2_SHIFT) + +/* + * C3 (RW) + * + * CSC parameters C3 + */ +#define JPEG_RGB2YUV_COEF2_C3_MASK (0x7FFU) +#define JPEG_RGB2YUV_COEF2_C3_SHIFT (0U) +#define JPEG_RGB2YUV_COEF2_C3_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF2_C3_SHIFT) & JPEG_RGB2YUV_COEF2_C3_MASK) +#define JPEG_RGB2YUV_COEF2_C3_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF2_C3_MASK) >> JPEG_RGB2YUV_COEF2_C3_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF3 */ +/* + * C6 (RW) + * + * CSC parameters C6 + */ +#define JPEG_RGB2YUV_COEF3_C6_MASK (0x7FF0000UL) +#define JPEG_RGB2YUV_COEF3_C6_SHIFT (16U) +#define JPEG_RGB2YUV_COEF3_C6_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF3_C6_SHIFT) & JPEG_RGB2YUV_COEF3_C6_MASK) +#define JPEG_RGB2YUV_COEF3_C6_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF3_C6_MASK) >> JPEG_RGB2YUV_COEF3_C6_SHIFT) + +/* + * C5 (RW) + * + * CSC parameters C5 + */ +#define JPEG_RGB2YUV_COEF3_C5_MASK (0x7FFU) +#define JPEG_RGB2YUV_COEF3_C5_SHIFT (0U) +#define JPEG_RGB2YUV_COEF3_C5_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF3_C5_SHIFT) & JPEG_RGB2YUV_COEF3_C5_MASK) +#define JPEG_RGB2YUV_COEF3_C5_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF3_C5_MASK) >> JPEG_RGB2YUV_COEF3_C5_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF4 */ +/* + * C8 (RW) + * + * CSC parameters C8 + */ +#define JPEG_RGB2YUV_COEF4_C8_MASK (0x7FF0000UL) +#define JPEG_RGB2YUV_COEF4_C8_SHIFT (16U) +#define JPEG_RGB2YUV_COEF4_C8_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF4_C8_SHIFT) & JPEG_RGB2YUV_COEF4_C8_MASK) +#define JPEG_RGB2YUV_COEF4_C8_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF4_C8_MASK) >> JPEG_RGB2YUV_COEF4_C8_SHIFT) + +/* + * C7 (RW) + * + * CSC parameters C7 + */ +#define JPEG_RGB2YUV_COEF4_C7_MASK (0x7FFU) +#define JPEG_RGB2YUV_COEF4_C7_SHIFT (0U) +#define JPEG_RGB2YUV_COEF4_C7_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF4_C7_SHIFT) & JPEG_RGB2YUV_COEF4_C7_MASK) +#define JPEG_RGB2YUV_COEF4_C7_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF4_C7_MASK) >> JPEG_RGB2YUV_COEF4_C7_SHIFT) + +/* Bitfield definition for register: IMGREG1 */ +/* + * RE (RW) + * + * Encoder Use only. + * Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs + */ +#define JPEG_IMGREG1_RE_MASK (0x4U) +#define JPEG_IMGREG1_RE_SHIFT (2U) +#define JPEG_IMGREG1_RE_SET(x) (((uint32_t)(x) << JPEG_IMGREG1_RE_SHIFT) & JPEG_IMGREG1_RE_MASK) +#define JPEG_IMGREG1_RE_GET(x) (((uint32_t)(x) & JPEG_IMGREG1_RE_MASK) >> JPEG_IMGREG1_RE_SHIFT) + +/* + * NCOL (RW) + * + * Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 + */ +#define JPEG_IMGREG1_NCOL_MASK (0x3U) +#define JPEG_IMGREG1_NCOL_SHIFT (0U) +#define JPEG_IMGREG1_NCOL_SET(x) (((uint32_t)(x) << JPEG_IMGREG1_NCOL_SHIFT) & JPEG_IMGREG1_NCOL_MASK) +#define JPEG_IMGREG1_NCOL_GET(x) (((uint32_t)(x) & JPEG_IMGREG1_NCOL_MASK) >> JPEG_IMGREG1_NCOL_SHIFT) + +/* Bitfield definition for register: IMGREG2 */ +/* + * NMCU (RW) + * + * Encoder Use only. + * The number of NMCU to be generated in encoder mode + */ +#define JPEG_IMGREG2_NMCU_MASK (0x3FFFFFFUL) +#define JPEG_IMGREG2_NMCU_SHIFT (0U) +#define JPEG_IMGREG2_NMCU_SET(x) (((uint32_t)(x) << JPEG_IMGREG2_NMCU_SHIFT) & JPEG_IMGREG2_NMCU_MASK) +#define JPEG_IMGREG2_NMCU_GET(x) (((uint32_t)(x) & JPEG_IMGREG2_NMCU_MASK) >> JPEG_IMGREG2_NMCU_SHIFT) + +/* Bitfield definition for register: IMGREG3 */ +/* + * NRST (RW) + * + * Encoder use only. + * It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. + */ +#define JPEG_IMGREG3_NRST_MASK (0xFFFFU) +#define JPEG_IMGREG3_NRST_SHIFT (0U) +#define JPEG_IMGREG3_NRST_SET(x) (((uint32_t)(x) << JPEG_IMGREG3_NRST_SHIFT) & JPEG_IMGREG3_NRST_MASK) +#define JPEG_IMGREG3_NRST_GET(x) (((uint32_t)(x) & JPEG_IMGREG3_NRST_MASK) >> JPEG_IMGREG3_NRST_SHIFT) + +/* Bitfield definition for register array: IMGREG */ +/* + * NBLOCK (RW) + * + * Encoder use only. + * The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. + */ +#define JPEG_IMGREG_NBLOCK_MASK (0xF0U) +#define JPEG_IMGREG_NBLOCK_SHIFT (4U) +#define JPEG_IMGREG_NBLOCK_SET(x) (((uint32_t)(x) << JPEG_IMGREG_NBLOCK_SHIFT) & JPEG_IMGREG_NBLOCK_MASK) +#define JPEG_IMGREG_NBLOCK_GET(x) (((uint32_t)(x) & JPEG_IMGREG_NBLOCK_MASK) >> JPEG_IMGREG_NBLOCK_SHIFT) + +/* + * QT (RW) + * + * Encoder use only. + * The selection of the quantization table. + */ +#define JPEG_IMGREG_QT_MASK (0xCU) +#define JPEG_IMGREG_QT_SHIFT (2U) +#define JPEG_IMGREG_QT_SET(x) (((uint32_t)(x) << JPEG_IMGREG_QT_SHIFT) & JPEG_IMGREG_QT_MASK) +#define JPEG_IMGREG_QT_GET(x) (((uint32_t)(x) & JPEG_IMGREG_QT_MASK) >> JPEG_IMGREG_QT_SHIFT) + +/* + * HA (RW) + * + * Encoder use only. + * The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. + */ +#define JPEG_IMGREG_HA_MASK (0x2U) +#define JPEG_IMGREG_HA_SHIFT (1U) +#define JPEG_IMGREG_HA_SET(x) (((uint32_t)(x) << JPEG_IMGREG_HA_SHIFT) & JPEG_IMGREG_HA_MASK) +#define JPEG_IMGREG_HA_GET(x) (((uint32_t)(x) & JPEG_IMGREG_HA_MASK) >> JPEG_IMGREG_HA_SHIFT) + +/* + * HD (RW) + * + * Encoder use only. + * The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. + */ +#define JPEG_IMGREG_HD_MASK (0x1U) +#define JPEG_IMGREG_HD_SHIFT (0U) +#define JPEG_IMGREG_HD_SET(x) (((uint32_t)(x) << JPEG_IMGREG_HD_SHIFT) & JPEG_IMGREG_HD_MASK) +#define JPEG_IMGREG_HD_GET(x) (((uint32_t)(x) & JPEG_IMGREG_HD_MASK) >> JPEG_IMGREG_HD_SHIFT) + + + +/* IMGREG register group index macro definition */ +#define JPEG_IMGREG_REG40 (0UL) +#define JPEG_IMGREG_REG41 (1UL) +#define JPEG_IMGREG_REG42 (2UL) +#define JPEG_IMGREG_REG43 (3UL) + + +#endif /* HPM_JPEG_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keym_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keym_regs.h new file mode 100644 index 0000000000..c935fdb66f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keym_regs.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_KEYM_H +#define HPM_KEYM_H + +typedef struct { + __RW uint32_t SOFTMKEY[8]; /* 0x0 - 0x1C: software set symmetric key */ + __RW uint32_t SOFTPKEY[8]; /* 0x20 - 0x3C: system asymmetric key */ + __RW uint32_t SEC_KEY_CTL; /* 0x40: secure key generation */ + __RW uint32_t NSC_KEY_CTL; /* 0x44: non-secure key generation */ + __RW uint32_t RNG; /* 0x48: Random number interface behavior */ + __RW uint32_t READ_CONTROL; /* 0x4C: key read out control */ +} KEYM_Type; + + +/* Bitfield definition for register array: SOFTMKEY */ +/* + * KEY (RW) + * + * software symmetric key + * key will be scambled to 4 variants for software to use, and replicable on same chip. + * scramble keys are chip different, and not replicable on different chip + * must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + */ +#define KEYM_SOFTMKEY_KEY_MASK (0xFFFFFFFFUL) +#define KEYM_SOFTMKEY_KEY_SHIFT (0U) +#define KEYM_SOFTMKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTMKEY_KEY_SHIFT) & KEYM_SOFTMKEY_KEY_MASK) +#define KEYM_SOFTMKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTMKEY_KEY_MASK) >> KEYM_SOFTMKEY_KEY_SHIFT) + +/* Bitfield definition for register array: SOFTPKEY */ +/* + * KEY (RW) + * + * software asymmetric key + * key is derived from scrambles of fuse private key, software input key, SRK, and system security status. + * This key os read once, sencondary read will read out 0 + */ +#define KEYM_SOFTPKEY_KEY_MASK (0xFFFFFFFFUL) +#define KEYM_SOFTPKEY_KEY_SHIFT (0U) +#define KEYM_SOFTPKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTPKEY_KEY_SHIFT) & KEYM_SOFTPKEY_KEY_MASK) +#define KEYM_SOFTPKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTPKEY_KEY_MASK) >> KEYM_SOFTPKEY_KEY_SHIFT) + +/* Bitfield definition for register: SEC_KEY_CTL */ +/* + * LOCK_SEC_CTL (RW) + * + * block secure state key setting being changed + */ +#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK (0x80000000UL) +#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT (31U) +#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) +#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) >> KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) + +/* + * SK_VAL (RO) + * + * session key valid + * 0: session key is all 0's and not usable + * 1: session key is valid + */ +#define KEYM_SEC_KEY_CTL_SK_VAL_MASK (0x10000UL) +#define KEYM_SEC_KEY_CTL_SK_VAL_SHIFT (16U) +#define KEYM_SEC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SK_VAL_MASK) >> KEYM_SEC_KEY_CTL_SK_VAL_SHIFT) + +/* + * SMK_SEL (RW) + * + * software symmetric key selection + * 0: use origin value in software symmetric key + * 1: use scramble version of software symmetric key + */ +#define KEYM_SEC_KEY_CTL_SMK_SEL_MASK (0x1000U) +#define KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT (12U) +#define KEYM_SEC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) +#define KEYM_SEC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) + +/* + * ZMK_SEL (RW) + * + * batt symmetric key selection + * 0: use scramble version of software symmetric key + * 1: use origin value in software symmetric key + */ +#define KEYM_SEC_KEY_CTL_ZMK_SEL_MASK (0x100U) +#define KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT (8U) +#define KEYM_SEC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) +#define KEYM_SEC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) + +/* + * FMK_SEL (RW) + * + * fuse symmetric key selection + * 0: use scramble version of fuse symmetric key + * 1: use alnertave scramble of fuse symmetric key + */ +#define KEYM_SEC_KEY_CTL_FMK_SEL_MASK (0x10U) +#define KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT (4U) +#define KEYM_SEC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) +#define KEYM_SEC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) + +/* + * KEY_SEL (RW) + * + * secure symmtric key synthesize setting, key is a XOR of followings + * bit0: fuse mk, 0: not selected, 1:selected + * bit1: zmk from batt, 0: not selected, 1:selected + * bit2: software key 0: not selected, 1:selected + */ +#define KEYM_SEC_KEY_CTL_KEY_SEL_MASK (0x7U) +#define KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT (0U) +#define KEYM_SEC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) +#define KEYM_SEC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) >> KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) + +/* Bitfield definition for register: NSC_KEY_CTL */ +/* + * LOCK_NSC_CTL (RW) + * + * block non-secure state key setting being changed + */ +#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK (0x80000000UL) +#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT (31U) +#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) +#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) >> KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) + +/* + * SK_VAL (RO) + * + * session key valid + * 0: session key is all 0's and not usable + * 1: session key is valid + */ +#define KEYM_NSC_KEY_CTL_SK_VAL_MASK (0x10000UL) +#define KEYM_NSC_KEY_CTL_SK_VAL_SHIFT (16U) +#define KEYM_NSC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SK_VAL_MASK) >> KEYM_NSC_KEY_CTL_SK_VAL_SHIFT) + +/* + * SMK_SEL (RW) + * + * software symmetric key selection + * 0: use scramble version of software symmetric key + * 1: use origin value in software symmetric key + */ +#define KEYM_NSC_KEY_CTL_SMK_SEL_MASK (0x1000U) +#define KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT (12U) +#define KEYM_NSC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) +#define KEYM_NSC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) + +/* + * ZMK_SEL (RW) + * + * batt symmetric key selection + * 0: use scramble version of software symmetric key + * 1: use origin value in software symmetric key + */ +#define KEYM_NSC_KEY_CTL_ZMK_SEL_MASK (0x100U) +#define KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT (8U) +#define KEYM_NSC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) +#define KEYM_NSC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) + +/* + * FMK_SEL (RW) + * + * fuse symmetric key selection + * 0: use scramble version of fuse symmetric key + * 1: use origin value in fuse symmetric key + */ +#define KEYM_NSC_KEY_CTL_FMK_SEL_MASK (0x10U) +#define KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT (4U) +#define KEYM_NSC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) +#define KEYM_NSC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) + +/* + * KEY_SEL (RW) + * + * non-secure symmtric key synthesize setting, key is a XOR of followings + * bit0: fuse mk, 0: not selected, 1:selected + * bit1: zmk from batt, 0: not selected, 1:selected + * bit2: software key 0: not selected, 1:selected + */ +#define KEYM_NSC_KEY_CTL_KEY_SEL_MASK (0x7U) +#define KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT (0U) +#define KEYM_NSC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) +#define KEYM_NSC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) >> KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) + +/* Bitfield definition for register: RNG */ +/* + * BLOCK_RNG_XOR (RW) + * + * block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset + * 0: RNG_XOR can be changed by software + * 1: RNG_XOR ignore software change from software + */ +#define KEYM_RNG_BLOCK_RNG_XOR_MASK (0x10000UL) +#define KEYM_RNG_BLOCK_RNG_XOR_SHIFT (16U) +#define KEYM_RNG_BLOCK_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_BLOCK_RNG_XOR_SHIFT) & KEYM_RNG_BLOCK_RNG_XOR_MASK) +#define KEYM_RNG_BLOCK_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_BLOCK_RNG_XOR_MASK) >> KEYM_RNG_BLOCK_RNG_XOR_SHIFT) + +/* + * RNG_XOR (RW) + * + * control how SFK is accepted from random number generator + * 0: SFK value replaced by random number input + * 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + */ +#define KEYM_RNG_RNG_XOR_MASK (0x1U) +#define KEYM_RNG_RNG_XOR_SHIFT (0U) +#define KEYM_RNG_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_RNG_XOR_SHIFT) & KEYM_RNG_RNG_XOR_MASK) +#define KEYM_RNG_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_RNG_XOR_MASK) >> KEYM_RNG_RNG_XOR_SHIFT) + +/* Bitfield definition for register: READ_CONTROL */ +/* + * BLOCK_PK_READ (RW) + * + * asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset + * 0: key can be read out + * 1: key cannot be read out + */ +#define KEYM_READ_CONTROL_BLOCK_PK_READ_MASK (0x10000UL) +#define KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT (16U) +#define KEYM_READ_CONTROL_BLOCK_PK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) +#define KEYM_READ_CONTROL_BLOCK_PK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) + +/* + * BLOCK_SMK_READ (RW) + * + * symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset + * 0: key can be read out + * 1: key cannot be read out + */ +#define KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK (0x1U) +#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT (0U) +#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) +#define KEYM_READ_CONTROL_BLOCK_SMK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) + + + +/* SOFTMKEY register group index macro definition */ +#define KEYM_SOFTMKEY_SFK0 (0UL) +#define KEYM_SOFTMKEY_SFK1 (1UL) +#define KEYM_SOFTMKEY_SFK2 (2UL) +#define KEYM_SOFTMKEY_SFK3 (3UL) +#define KEYM_SOFTMKEY_SFK4 (4UL) +#define KEYM_SOFTMKEY_SFK5 (5UL) +#define KEYM_SOFTMKEY_SFK6 (6UL) +#define KEYM_SOFTMKEY_SFK7 (7UL) + +/* SOFTPKEY register group index macro definition */ +#define KEYM_SOFTPKEY_SPK0 (0UL) +#define KEYM_SOFTPKEY_SPK1 (1UL) +#define KEYM_SOFTPKEY_SPK2 (2UL) +#define KEYM_SOFTPKEY_SPK3 (3UL) +#define KEYM_SOFTPKEY_SPK4 (4UL) +#define KEYM_SOFTPKEY_SPK5 (5UL) +#define KEYM_SOFTPKEY_SPK6 (6UL) +#define KEYM_SOFTPKEY_SPK7 (7UL) + + +#endif /* HPM_KEYM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keyman_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keyman_regs.h new file mode 100644 index 0000000000..a257d2cf53 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_keyman_regs.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_KEYMAN_H +#define HPM_KEYMAN_H + +typedef struct { + __RW uint32_t SOFTMKEY[8]; /* 0x0 - 0x1C: software set symmetric key */ + __RW uint32_t SOFTPKEY[8]; /* 0x20 - 0x3C: system asymmetric key */ + __RW uint32_t SEC_KEY_CTL; /* 0x40: Random number interface behavior */ + __RW uint32_t NSC_KEY_CTL; /* 0x44: Random number interface behavior */ + __RW uint32_t RNG; /* 0x48: Random number interface behavior */ + __RW uint32_t READ_CONTROL; /* 0x4C: symmetric and asymmetric key read out control */ +} KEYMAN_Type; + + +/* Bitfield definition for register array: SOFTMKEY */ +/* + * KEY (RW) + * + * software symmetric key + * key will be scambled to 4 variants for software to use, and replicable on same chip. + * scramble keys are chip different, and not replicable on different chip + * must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + */ +#define KEYMAN_SOFTMKEY_KEY_MASK (0xFFFFFFFFUL) +#define KEYMAN_SOFTMKEY_KEY_SHIFT (0U) +#define KEYMAN_SOFTMKEY_KEY_SET(x) (((uint32_t)(x) << KEYMAN_SOFTMKEY_KEY_SHIFT) & KEYMAN_SOFTMKEY_KEY_MASK) +#define KEYMAN_SOFTMKEY_KEY_GET(x) (((uint32_t)(x) & KEYMAN_SOFTMKEY_KEY_MASK) >> KEYMAN_SOFTMKEY_KEY_SHIFT) + +/* Bitfield definition for register array: SOFTPKEY */ +/* + * KEY (RW) + * + * software asymmetric key + * key is XOR version of scrambles of fuse private key, software input key, SRK, and system security status. + * This key os read once, sencondary read will read out 0 + */ +#define KEYMAN_SOFTPKEY_KEY_MASK (0xFFFFFFFFUL) +#define KEYMAN_SOFTPKEY_KEY_SHIFT (0U) +#define KEYMAN_SOFTPKEY_KEY_SET(x) (((uint32_t)(x) << KEYMAN_SOFTPKEY_KEY_SHIFT) & KEYMAN_SOFTPKEY_KEY_MASK) +#define KEYMAN_SOFTPKEY_KEY_GET(x) (((uint32_t)(x) & KEYMAN_SOFTPKEY_KEY_MASK) >> KEYMAN_SOFTPKEY_KEY_SHIFT) + +/* Bitfield definition for register: SEC_KEY_CTL */ +/* + * LOCK_SEC_CTL (RW) + * + * block secure state key setting being changed + */ +#define KEYMAN_SEC_KEY_CTL_LOCK_SEC_CTL_MASK (0x80000000UL) +#define KEYMAN_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT (31U) +#define KEYMAN_SEC_KEY_CTL_LOCK_SEC_CTL_SET(x) (((uint32_t)(x) << KEYMAN_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) & KEYMAN_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) +#define KEYMAN_SEC_KEY_CTL_LOCK_SEC_CTL_GET(x) (((uint32_t)(x) & KEYMAN_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) >> KEYMAN_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) + +/* + * SK_VAL (RO) + * + * session key valid + * 0: session key is all 0's and not usable + * 1: session key is valid + */ +#define KEYMAN_SEC_KEY_CTL_SK_VAL_MASK (0x10000UL) +#define KEYMAN_SEC_KEY_CTL_SK_VAL_SHIFT (16U) +#define KEYMAN_SEC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYMAN_SEC_KEY_CTL_SK_VAL_MASK) >> KEYMAN_SEC_KEY_CTL_SK_VAL_SHIFT) + +/* + * SMK_SEL (RW) + * + * software symmetric key selection + * 0: use scramble version of software symmetric key + * 1: use origin value in software symmetric key + */ +#define KEYMAN_SEC_KEY_CTL_SMK_SEL_MASK (0x1000U) +#define KEYMAN_SEC_KEY_CTL_SMK_SEL_SHIFT (12U) +#define KEYMAN_SEC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYMAN_SEC_KEY_CTL_SMK_SEL_SHIFT) & KEYMAN_SEC_KEY_CTL_SMK_SEL_MASK) +#define KEYMAN_SEC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYMAN_SEC_KEY_CTL_SMK_SEL_MASK) >> KEYMAN_SEC_KEY_CTL_SMK_SEL_SHIFT) + +/* + * ZMK_SEL (RW) + * + * software symmetric key selection + * 0: use scramble version of software symmetric key + * 1: use origin value in software symmetric key + */ +#define KEYMAN_SEC_KEY_CTL_ZMK_SEL_MASK (0x100U) +#define KEYMAN_SEC_KEY_CTL_ZMK_SEL_SHIFT (8U) +#define KEYMAN_SEC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYMAN_SEC_KEY_CTL_ZMK_SEL_SHIFT) & KEYMAN_SEC_KEY_CTL_ZMK_SEL_MASK) +#define KEYMAN_SEC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYMAN_SEC_KEY_CTL_ZMK_SEL_MASK) >> KEYMAN_SEC_KEY_CTL_ZMK_SEL_SHIFT) + +/* + * FMK_SEL (RW) + * + * fuse symmetric key selection + * 0: use scramble version of fuse symmetric key + * 1: use origin value in fuse symmetric key + */ +#define KEYMAN_SEC_KEY_CTL_FMK_SEL_MASK (0x10U) +#define KEYMAN_SEC_KEY_CTL_FMK_SEL_SHIFT (4U) +#define KEYMAN_SEC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYMAN_SEC_KEY_CTL_FMK_SEL_SHIFT) & KEYMAN_SEC_KEY_CTL_FMK_SEL_MASK) +#define KEYMAN_SEC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYMAN_SEC_KEY_CTL_FMK_SEL_MASK) >> KEYMAN_SEC_KEY_CTL_FMK_SEL_SHIFT) + +/* + * KEY_SEL (RW) + * + * secure symmtric key synthesize setting, key is a XOR of followings + * bit0: fuse mk, 0: not selected, 1:selected + * bit1: zmk from batt, 0: not selected, 1:selected + * bit2: software key 0: not selected, 1:selected + */ +#define KEYMAN_SEC_KEY_CTL_KEY_SEL_MASK (0x7U) +#define KEYMAN_SEC_KEY_CTL_KEY_SEL_SHIFT (0U) +#define KEYMAN_SEC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYMAN_SEC_KEY_CTL_KEY_SEL_SHIFT) & KEYMAN_SEC_KEY_CTL_KEY_SEL_MASK) +#define KEYMAN_SEC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYMAN_SEC_KEY_CTL_KEY_SEL_MASK) >> KEYMAN_SEC_KEY_CTL_KEY_SEL_SHIFT) + +/* Bitfield definition for register: NSC_KEY_CTL */ +/* + * LOCK_NSC_CTL (RW) + * + * block non-secure state key setting being changed + */ +#define KEYMAN_NSC_KEY_CTL_LOCK_NSC_CTL_MASK (0x80000000UL) +#define KEYMAN_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT (31U) +#define KEYMAN_NSC_KEY_CTL_LOCK_NSC_CTL_SET(x) (((uint32_t)(x) << KEYMAN_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) & KEYMAN_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) +#define KEYMAN_NSC_KEY_CTL_LOCK_NSC_CTL_GET(x) (((uint32_t)(x) & KEYMAN_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) >> KEYMAN_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) + +/* + * SK_VAL (RO) + * + * session key valid + * 0: session key is all 0's and not usable + * 1: session key is valid + */ +#define KEYMAN_NSC_KEY_CTL_SK_VAL_MASK (0x10000UL) +#define KEYMAN_NSC_KEY_CTL_SK_VAL_SHIFT (16U) +#define KEYMAN_NSC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYMAN_NSC_KEY_CTL_SK_VAL_MASK) >> KEYMAN_NSC_KEY_CTL_SK_VAL_SHIFT) + +/* + * SMK_SEL (RW) + * + * software symmetric key selection + * 0: use scramble version of software symmetric key + * 1: use origin value in software symmetric key + */ +#define KEYMAN_NSC_KEY_CTL_SMK_SEL_MASK (0x1000U) +#define KEYMAN_NSC_KEY_CTL_SMK_SEL_SHIFT (12U) +#define KEYMAN_NSC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYMAN_NSC_KEY_CTL_SMK_SEL_SHIFT) & KEYMAN_NSC_KEY_CTL_SMK_SEL_MASK) +#define KEYMAN_NSC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYMAN_NSC_KEY_CTL_SMK_SEL_MASK) >> KEYMAN_NSC_KEY_CTL_SMK_SEL_SHIFT) + +/* + * ZMK_SEL (RW) + * + * software symmetric key selection + * 0: use scramble version of software symmetric key + * 1: use origin value in software symmetric key + */ +#define KEYMAN_NSC_KEY_CTL_ZMK_SEL_MASK (0x100U) +#define KEYMAN_NSC_KEY_CTL_ZMK_SEL_SHIFT (8U) +#define KEYMAN_NSC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYMAN_NSC_KEY_CTL_ZMK_SEL_SHIFT) & KEYMAN_NSC_KEY_CTL_ZMK_SEL_MASK) +#define KEYMAN_NSC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYMAN_NSC_KEY_CTL_ZMK_SEL_MASK) >> KEYMAN_NSC_KEY_CTL_ZMK_SEL_SHIFT) + +/* + * FMK_SEL (RW) + * + * fuse symmetric key selection + * 0: use scramble version of fuse symmetric key + * 1: use origin value in fuse symmetric key + */ +#define KEYMAN_NSC_KEY_CTL_FMK_SEL_MASK (0x10U) +#define KEYMAN_NSC_KEY_CTL_FMK_SEL_SHIFT (4U) +#define KEYMAN_NSC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYMAN_NSC_KEY_CTL_FMK_SEL_SHIFT) & KEYMAN_NSC_KEY_CTL_FMK_SEL_MASK) +#define KEYMAN_NSC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYMAN_NSC_KEY_CTL_FMK_SEL_MASK) >> KEYMAN_NSC_KEY_CTL_FMK_SEL_SHIFT) + +/* + * KEY_SEL (RW) + * + * non-secure symmtric key synthesize setting, key is a XOR of followings + * bit0: fuse mk, 0: not selected, 1:selected + * bit1: zmk from batt, 0: not selected, 1:selected + * bit2: software key 0: not selected, 1:selected + */ +#define KEYMAN_NSC_KEY_CTL_KEY_SEL_MASK (0x7U) +#define KEYMAN_NSC_KEY_CTL_KEY_SEL_SHIFT (0U) +#define KEYMAN_NSC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYMAN_NSC_KEY_CTL_KEY_SEL_SHIFT) & KEYMAN_NSC_KEY_CTL_KEY_SEL_MASK) +#define KEYMAN_NSC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYMAN_NSC_KEY_CTL_KEY_SEL_MASK) >> KEYMAN_NSC_KEY_CTL_KEY_SEL_SHIFT) + +/* Bitfield definition for register: RNG */ +/* + * BLOCK_RNG_XOR (RW) + * + * block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset + * 0: RNG_XOR can be changed by software + * 1: RNG_XOR ignore software change from software + */ +#define KEYMAN_RNG_BLOCK_RNG_XOR_MASK (0x10000UL) +#define KEYMAN_RNG_BLOCK_RNG_XOR_SHIFT (16U) +#define KEYMAN_RNG_BLOCK_RNG_XOR_SET(x) (((uint32_t)(x) << KEYMAN_RNG_BLOCK_RNG_XOR_SHIFT) & KEYMAN_RNG_BLOCK_RNG_XOR_MASK) +#define KEYMAN_RNG_BLOCK_RNG_XOR_GET(x) (((uint32_t)(x) & KEYMAN_RNG_BLOCK_RNG_XOR_MASK) >> KEYMAN_RNG_BLOCK_RNG_XOR_SHIFT) + +/* + * RNG_XOR (RW) + * + * control how SFK is accepted from random number generator + * 0: SFK value replaced by random number input + * 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + */ +#define KEYMAN_RNG_RNG_XOR_MASK (0x1U) +#define KEYMAN_RNG_RNG_XOR_SHIFT (0U) +#define KEYMAN_RNG_RNG_XOR_SET(x) (((uint32_t)(x) << KEYMAN_RNG_RNG_XOR_SHIFT) & KEYMAN_RNG_RNG_XOR_MASK) +#define KEYMAN_RNG_RNG_XOR_GET(x) (((uint32_t)(x) & KEYMAN_RNG_RNG_XOR_MASK) >> KEYMAN_RNG_RNG_XOR_SHIFT) + +/* Bitfield definition for register: READ_CONTROL */ +/* + * BLOCK_PK_READ (RW) + * + * asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset + * 0: key can be read out + * 1: key cannot be read out + */ +#define KEYMAN_READ_CONTROL_BLOCK_PK_READ_MASK (0x10000UL) +#define KEYMAN_READ_CONTROL_BLOCK_PK_READ_SHIFT (16U) +#define KEYMAN_READ_CONTROL_BLOCK_PK_READ_SET(x) (((uint32_t)(x) << KEYMAN_READ_CONTROL_BLOCK_PK_READ_SHIFT) & KEYMAN_READ_CONTROL_BLOCK_PK_READ_MASK) +#define KEYMAN_READ_CONTROL_BLOCK_PK_READ_GET(x) (((uint32_t)(x) & KEYMAN_READ_CONTROL_BLOCK_PK_READ_MASK) >> KEYMAN_READ_CONTROL_BLOCK_PK_READ_SHIFT) + +/* + * BLOCK_SMK_READ (RW) + * + * symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset + * 0: key can be read out + * 1: key cannot be read out + */ +#define KEYMAN_READ_CONTROL_BLOCK_SMK_READ_MASK (0x1U) +#define KEYMAN_READ_CONTROL_BLOCK_SMK_READ_SHIFT (0U) +#define KEYMAN_READ_CONTROL_BLOCK_SMK_READ_SET(x) (((uint32_t)(x) << KEYMAN_READ_CONTROL_BLOCK_SMK_READ_SHIFT) & KEYMAN_READ_CONTROL_BLOCK_SMK_READ_MASK) +#define KEYMAN_READ_CONTROL_BLOCK_SMK_READ_GET(x) (((uint32_t)(x) & KEYMAN_READ_CONTROL_BLOCK_SMK_READ_MASK) >> KEYMAN_READ_CONTROL_BLOCK_SMK_READ_SHIFT) + + + +/* SOFTMKEY register group index macro definition */ +#define KEYMAN_SOFTMKEY_SFK0 (0UL) +#define KEYMAN_SOFTMKEY_SFK1 (1UL) +#define KEYMAN_SOFTMKEY_SFK2 (2UL) +#define KEYMAN_SOFTMKEY_SFK3 (3UL) +#define KEYMAN_SOFTMKEY_SFK4 (4UL) +#define KEYMAN_SOFTMKEY_SFK5 (5UL) +#define KEYMAN_SOFTMKEY_SFK6 (6UL) +#define KEYMAN_SOFTMKEY_SFK7 (7UL) + +/* SOFTPKEY register group index macro definition */ +#define KEYMAN_SOFTPKEY_SPK0 (0UL) +#define KEYMAN_SOFTPKEY_SPK1 (1UL) +#define KEYMAN_SOFTPKEY_SPK2 (2UL) +#define KEYMAN_SOFTPKEY_SPK3 (3UL) +#define KEYMAN_SOFTPKEY_SPK4 (4UL) +#define KEYMAN_SOFTPKEY_SPK5 (5UL) +#define KEYMAN_SOFTPKEY_SPK6 (6UL) +#define KEYMAN_SOFTPKEY_SPK7 (7UL) + + +#endif /* HPM_KEYMAN_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h new file mode 100644 index 0000000000..d6c0a4ea1d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h @@ -0,0 +1,834 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_LCDC_H +#define HPM_LCDC_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: Control Register */ + __RW uint32_t BGND_CL; /* 0x4: Background Color Register */ + __RW uint32_t DISP_WN_SIZE; /* 0x8: Display Window Size Register */ + __RW uint32_t HSYNC_PARA; /* 0xC: HSYNC Config Register */ + __RW uint32_t VSYNC_PARA; /* 0x10: VSYNC Config Register */ + __W uint32_t DMA_ST; /* 0x14: DMA Status Register */ + __W uint32_t ST; /* 0x18: Status Register */ + __RW uint32_t INT_EN; /* 0x1C: Interrupt Enable Register */ + __RW uint32_t TXFIFO; /* 0x20: TX FIFO Register */ + __R uint8_t RESERVED0[476]; /* 0x24 - 0x1FF: Reserved */ + struct { + __RW uint32_t LAYCTRL; /* 0x200: Layer Control Register */ + __RW uint32_t ALPHAS; /* 0x204: Layer Alpha Register */ + __RW uint32_t LAYSIZE; /* 0x208: Layer Size Register */ + __RW uint32_t LAYPOS; /* 0x20C: Layer Position Register */ + __RW uint32_t START0; /* 0x210: Layer Buffer Pointer Register */ + __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */ + __RW uint32_t LINECFG; /* 0x218: Layer Bus Config Register */ + __RW uint32_t BG_CL; /* 0x21C: Layer Background Color Register */ + __RW uint32_t CSC_COEF0; /* 0x220: Layer Color Space Conversion Config Register 0 */ + __RW uint32_t CSC_COEF1; /* 0x224: Layer Color Space Conversion Config Register 1 */ + __RW uint32_t CSC_COEF2; /* 0x228: Layer Color Space Conversion Config Register 2 */ + __R uint8_t RESERVED1[20]; /* 0x22C - 0x23F: Reserved */ + } LAYER[8]; + __RW uint32_t CLUT_LOAD; /* 0x400: Clut Load Control Register */ +} LCDC_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SW_RST (RW) + * + * Software reset, high active. When write 1 ,all internal logical will be reset. + * 0b - No action + * 1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. + */ +#define LCDC_CTRL_SW_RST_MASK (0x80000000UL) +#define LCDC_CTRL_SW_RST_SHIFT (31U) +#define LCDC_CTRL_SW_RST_SET(x) (((uint32_t)(x) << LCDC_CTRL_SW_RST_SHIFT) & LCDC_CTRL_SW_RST_MASK) +#define LCDC_CTRL_SW_RST_GET(x) (((uint32_t)(x) & LCDC_CTRL_SW_RST_MASK) >> LCDC_CTRL_SW_RST_SHIFT) + +/* + * DISP_ON (RW) + * + * Display panel On/Off mode. + * 0b - Display Off. + * 1b - Display On. + * Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. + * So a good procedure to stop and turn on the display is: + * 1) clr VS_BLANK status + * 2) assert software reset + * 3) de-assert software reset + * 4) set display off + * 5) check VS_BLANK status until it is asserted, + * 6)reset the module, change settings + * 7) set display on + */ +#define LCDC_CTRL_DISP_ON_MASK (0x40000000UL) +#define LCDC_CTRL_DISP_ON_SHIFT (30U) +#define LCDC_CTRL_DISP_ON_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_ON_SHIFT) & LCDC_CTRL_DISP_ON_MASK) +#define LCDC_CTRL_DISP_ON_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_ON_MASK) >> LCDC_CTRL_DISP_ON_SHIFT) + +/* + * LINE_PATTERN (RW) + * + * LCDIF line output order. + * 000b - RGB. + * 001b - RBG. + * 010b - GBR. + * 011b - GRB. + * 100b - BRG. + * 101b - BGR. + */ +#define LCDC_CTRL_LINE_PATTERN_MASK (0x38000000UL) +#define LCDC_CTRL_LINE_PATTERN_SHIFT (27U) +#define LCDC_CTRL_LINE_PATTERN_SET(x) (((uint32_t)(x) << LCDC_CTRL_LINE_PATTERN_SHIFT) & LCDC_CTRL_LINE_PATTERN_MASK) +#define LCDC_CTRL_LINE_PATTERN_GET(x) (((uint32_t)(x) & LCDC_CTRL_LINE_PATTERN_MASK) >> LCDC_CTRL_LINE_PATTERN_SHIFT) + +/* + * DISP_MODE (RW) + * + * LCDIF operating mode. + * 00b - Normal mode. Panel content controlled by layer configuration. + * 01b - Test Mode1.(BGND Color Display) + * 10b - Test Mode2.(Column Color Bar) + * 11b - Test Mode3.(Row Color Bar) + */ +#define LCDC_CTRL_DISP_MODE_MASK (0x6000000UL) +#define LCDC_CTRL_DISP_MODE_SHIFT (25U) +#define LCDC_CTRL_DISP_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_MODE_SHIFT) & LCDC_CTRL_DISP_MODE_MASK) +#define LCDC_CTRL_DISP_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_MODE_MASK) >> LCDC_CTRL_DISP_MODE_SHIFT) + +/* + * BGDCL4CLR (RW) + * + * background color for clear mode when the alpha channel is 0 + */ +#define LCDC_CTRL_BGDCL4CLR_MASK (0x1000000UL) +#define LCDC_CTRL_BGDCL4CLR_SHIFT (24U) +#define LCDC_CTRL_BGDCL4CLR_SET(x) (((uint32_t)(x) << LCDC_CTRL_BGDCL4CLR_SHIFT) & LCDC_CTRL_BGDCL4CLR_MASK) +#define LCDC_CTRL_BGDCL4CLR_GET(x) (((uint32_t)(x) & LCDC_CTRL_BGDCL4CLR_MASK) >> LCDC_CTRL_BGDCL4CLR_SHIFT) + +/* + * ARQOS (RW) + * + * ARQOS for bus fabric arbitration + */ +#define LCDC_CTRL_ARQOS_MASK (0xF00000UL) +#define LCDC_CTRL_ARQOS_SHIFT (20U) +#define LCDC_CTRL_ARQOS_SET(x) (((uint32_t)(x) << LCDC_CTRL_ARQOS_SHIFT) & LCDC_CTRL_ARQOS_MASK) +#define LCDC_CTRL_ARQOS_GET(x) (((uint32_t)(x) & LCDC_CTRL_ARQOS_MASK) >> LCDC_CTRL_ARQOS_SHIFT) + +/* + * INV_PXDATA (RW) + * + * Indicates if value at the output (pixel data output) needs to be negated. + * 0b - Output is to remain same as the data inside memory + * 1b - Output to be negated from the data inside memory + */ +#define LCDC_CTRL_INV_PXDATA_MASK (0x10U) +#define LCDC_CTRL_INV_PXDATA_SHIFT (4U) +#define LCDC_CTRL_INV_PXDATA_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXDATA_SHIFT) & LCDC_CTRL_INV_PXDATA_MASK) +#define LCDC_CTRL_INV_PXDATA_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXDATA_MASK) >> LCDC_CTRL_INV_PXDATA_SHIFT) + +/* + * INV_PXCLK (RW) + * + * Polarity change of Pixel Clock. + * 0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge + * 1b - LCDC outputs data on the falling edge, Display samples data on the rising edge + */ +#define LCDC_CTRL_INV_PXCLK_MASK (0x8U) +#define LCDC_CTRL_INV_PXCLK_SHIFT (3U) +#define LCDC_CTRL_INV_PXCLK_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXCLK_SHIFT) & LCDC_CTRL_INV_PXCLK_MASK) +#define LCDC_CTRL_INV_PXCLK_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXCLK_MASK) >> LCDC_CTRL_INV_PXCLK_SHIFT) + +/* + * INV_HREF (RW) + * + * Polarity of HREF + * 0b - HREF signal active HIGH, indicating active pixel data + * 1b - HREF signal active LOW + */ +#define LCDC_CTRL_INV_HREF_MASK (0x4U) +#define LCDC_CTRL_INV_HREF_SHIFT (2U) +#define LCDC_CTRL_INV_HREF_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HREF_SHIFT) & LCDC_CTRL_INV_HREF_MASK) +#define LCDC_CTRL_INV_HREF_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HREF_MASK) >> LCDC_CTRL_INV_HREF_SHIFT) + +/* + * INV_VSYNC (RW) + * + * Polarity of VSYNC + * 0b - VSYNC signal active HIGH + * 1b - VSYNC signal active LOW + */ +#define LCDC_CTRL_INV_VSYNC_MASK (0x2U) +#define LCDC_CTRL_INV_VSYNC_SHIFT (1U) +#define LCDC_CTRL_INV_VSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_VSYNC_SHIFT) & LCDC_CTRL_INV_VSYNC_MASK) +#define LCDC_CTRL_INV_VSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_VSYNC_MASK) >> LCDC_CTRL_INV_VSYNC_SHIFT) + +/* + * INV_HSYNC (RW) + * + * Polarity of HSYNC + * 0b - HSYNC signal active HIGH + * 1b - HSYNC signal active LOW + */ +#define LCDC_CTRL_INV_HSYNC_MASK (0x1U) +#define LCDC_CTRL_INV_HSYNC_SHIFT (0U) +#define LCDC_CTRL_INV_HSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HSYNC_SHIFT) & LCDC_CTRL_INV_HSYNC_MASK) +#define LCDC_CTRL_INV_HSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HSYNC_MASK) >> LCDC_CTRL_INV_HSYNC_SHIFT) + +/* Bitfield definition for register: BGND_CL */ +/* + * R (RW) + * + * Red component of the default color displayed in the sectors where no layer is active. + */ +#define LCDC_BGND_CL_R_MASK (0xFF0000UL) +#define LCDC_BGND_CL_R_SHIFT (16U) +#define LCDC_BGND_CL_R_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_R_SHIFT) & LCDC_BGND_CL_R_MASK) +#define LCDC_BGND_CL_R_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_R_MASK) >> LCDC_BGND_CL_R_SHIFT) + +/* + * G (RW) + * + * Green component of the default color displayed in the sectors where no layer is active. + */ +#define LCDC_BGND_CL_G_MASK (0xFF00U) +#define LCDC_BGND_CL_G_SHIFT (8U) +#define LCDC_BGND_CL_G_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_G_SHIFT) & LCDC_BGND_CL_G_MASK) +#define LCDC_BGND_CL_G_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_G_MASK) >> LCDC_BGND_CL_G_SHIFT) + +/* + * B (RW) + * + * Blue component of the default color displayed in the sectors where no layer is active. + */ +#define LCDC_BGND_CL_B_MASK (0xFFU) +#define LCDC_BGND_CL_B_SHIFT (0U) +#define LCDC_BGND_CL_B_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_B_SHIFT) & LCDC_BGND_CL_B_MASK) +#define LCDC_BGND_CL_B_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_B_MASK) >> LCDC_BGND_CL_B_SHIFT) + +/* Bitfield definition for register: DISP_WN_SIZE */ +/* + * Y (RW) + * + * Sets the display size vertical resolution in pixels. + */ +#define LCDC_DISP_WN_SIZE_Y_MASK (0xFFF0000UL) +#define LCDC_DISP_WN_SIZE_Y_SHIFT (16U) +#define LCDC_DISP_WN_SIZE_Y_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_Y_SHIFT) & LCDC_DISP_WN_SIZE_Y_MASK) +#define LCDC_DISP_WN_SIZE_Y_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_Y_MASK) >> LCDC_DISP_WN_SIZE_Y_SHIFT) + +/* + * X (RW) + * + * Sets the display size horizontal resolution in pixels. + */ +#define LCDC_DISP_WN_SIZE_X_MASK (0xFFFU) +#define LCDC_DISP_WN_SIZE_X_SHIFT (0U) +#define LCDC_DISP_WN_SIZE_X_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_X_SHIFT) & LCDC_DISP_WN_SIZE_X_MASK) +#define LCDC_DISP_WN_SIZE_X_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_X_MASK) >> LCDC_DISP_WN_SIZE_X_SHIFT) + +/* Bitfield definition for register: HSYNC_PARA */ +/* + * FP (RW) + * + * HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC + */ +#define LCDC_HSYNC_PARA_FP_MASK (0x7FC00000UL) +#define LCDC_HSYNC_PARA_FP_SHIFT (22U) +#define LCDC_HSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_FP_SHIFT) & LCDC_HSYNC_PARA_FP_MASK) +#define LCDC_HSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_FP_MASK) >> LCDC_HSYNC_PARA_FP_SHIFT) + +/* + * BP (RW) + * + * HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC + */ +#define LCDC_HSYNC_PARA_BP_MASK (0xFF800UL) +#define LCDC_HSYNC_PARA_BP_SHIFT (11U) +#define LCDC_HSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_BP_SHIFT) & LCDC_HSYNC_PARA_BP_MASK) +#define LCDC_HSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_BP_MASK) >> LCDC_HSYNC_PARA_BP_SHIFT) + +/* + * PW (RW) + * + * HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. + */ +#define LCDC_HSYNC_PARA_PW_MASK (0x1FFU) +#define LCDC_HSYNC_PARA_PW_SHIFT (0U) +#define LCDC_HSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_PW_SHIFT) & LCDC_HSYNC_PARA_PW_MASK) +#define LCDC_HSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_PW_MASK) >> LCDC_HSYNC_PARA_PW_SHIFT) + +/* Bitfield definition for register: VSYNC_PARA */ +/* + * FP (RW) + * + * VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC + */ +#define LCDC_VSYNC_PARA_FP_MASK (0x7FC00000UL) +#define LCDC_VSYNC_PARA_FP_SHIFT (22U) +#define LCDC_VSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_FP_SHIFT) & LCDC_VSYNC_PARA_FP_MASK) +#define LCDC_VSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_FP_MASK) >> LCDC_VSYNC_PARA_FP_SHIFT) + +/* + * BP (RW) + * + * VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC + */ +#define LCDC_VSYNC_PARA_BP_MASK (0xFF800UL) +#define LCDC_VSYNC_PARA_BP_SHIFT (11U) +#define LCDC_VSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_BP_SHIFT) & LCDC_VSYNC_PARA_BP_MASK) +#define LCDC_VSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_BP_MASK) >> LCDC_VSYNC_PARA_BP_SHIFT) + +/* + * PW (RW) + * + * VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. + */ +#define LCDC_VSYNC_PARA_PW_MASK (0x1FFU) +#define LCDC_VSYNC_PARA_PW_SHIFT (0U) +#define LCDC_VSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_PW_SHIFT) & LCDC_VSYNC_PARA_PW_MASK) +#define LCDC_VSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_PW_MASK) >> LCDC_VSYNC_PARA_PW_SHIFT) + +/* Bitfield definition for register: DMA_ST */ +/* + * DMA_ERR (W1C) + * + * plane n axi error. W1C. + */ +#define LCDC_DMA_ST_DMA_ERR_MASK (0xFF000000UL) +#define LCDC_DMA_ST_DMA_ERR_SHIFT (24U) +#define LCDC_DMA_ST_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA_ERR_SHIFT) & LCDC_DMA_ST_DMA_ERR_MASK) +#define LCDC_DMA_ST_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA_ERR_MASK) >> LCDC_DMA_ST_DMA_ERR_SHIFT) + +/* + * DMA1_DONE (W1C) + * + * Plane n frame 1 dma done. W1C. + */ +#define LCDC_DMA_ST_DMA1_DONE_MASK (0xFF0000UL) +#define LCDC_DMA_ST_DMA1_DONE_SHIFT (16U) +#define LCDC_DMA_ST_DMA1_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA1_DONE_SHIFT) & LCDC_DMA_ST_DMA1_DONE_MASK) +#define LCDC_DMA_ST_DMA1_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA1_DONE_MASK) >> LCDC_DMA_ST_DMA1_DONE_SHIFT) + +/* + * DMA0_DONE (W1C) + * + * Plane n frame 0 dma done. W1C. + */ +#define LCDC_DMA_ST_DMA0_DONE_MASK (0xFF00U) +#define LCDC_DMA_ST_DMA0_DONE_SHIFT (8U) +#define LCDC_DMA_ST_DMA0_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA0_DONE_SHIFT) & LCDC_DMA_ST_DMA0_DONE_MASK) +#define LCDC_DMA_ST_DMA0_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA0_DONE_MASK) >> LCDC_DMA_ST_DMA0_DONE_SHIFT) + +/* Bitfield definition for register: ST */ +/* + * URGENT_UNDERRUN (W1C) + * + * Asserted when the output buffer urgent underrun condition encountered + */ +#define LCDC_ST_URGENT_UNDERRUN_MASK (0x8U) +#define LCDC_ST_URGENT_UNDERRUN_SHIFT (3U) +#define LCDC_ST_URGENT_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_URGENT_UNDERRUN_SHIFT) & LCDC_ST_URGENT_UNDERRUN_MASK) +#define LCDC_ST_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_URGENT_UNDERRUN_MASK) >> LCDC_ST_URGENT_UNDERRUN_SHIFT) + +/* + * VS_BLANK (W1C) + * + * Asserted when in vertical blanking period. At the start of VSYNC + */ +#define LCDC_ST_VS_BLANK_MASK (0x4U) +#define LCDC_ST_VS_BLANK_SHIFT (2U) +#define LCDC_ST_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_ST_VS_BLANK_SHIFT) & LCDC_ST_VS_BLANK_MASK) +#define LCDC_ST_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_ST_VS_BLANK_MASK) >> LCDC_ST_VS_BLANK_SHIFT) + +/* + * UNDERRUN (W1C) + * + * Asserted when the output buffer underrun condition encountered + */ +#define LCDC_ST_UNDERRUN_MASK (0x2U) +#define LCDC_ST_UNDERRUN_SHIFT (1U) +#define LCDC_ST_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_UNDERRUN_SHIFT) & LCDC_ST_UNDERRUN_MASK) +#define LCDC_ST_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_UNDERRUN_MASK) >> LCDC_ST_UNDERRUN_SHIFT) + +/* + * VSYNC (W1C) + * + * Asserted when in vertical blanking period. At the end of VSYNC + */ +#define LCDC_ST_VSYNC_MASK (0x1U) +#define LCDC_ST_VSYNC_SHIFT (0U) +#define LCDC_ST_VSYNC_SET(x) (((uint32_t)(x) << LCDC_ST_VSYNC_SHIFT) & LCDC_ST_VSYNC_MASK) +#define LCDC_ST_VSYNC_GET(x) (((uint32_t)(x) & LCDC_ST_VSYNC_MASK) >> LCDC_ST_VSYNC_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * DMA_ERR (RW) + * + * Interrupt enable for DMA error + */ +#define LCDC_INT_EN_DMA_ERR_MASK (0xFF000000UL) +#define LCDC_INT_EN_DMA_ERR_SHIFT (24U) +#define LCDC_INT_EN_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_ERR_SHIFT) & LCDC_INT_EN_DMA_ERR_MASK) +#define LCDC_INT_EN_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_ERR_MASK) >> LCDC_INT_EN_DMA_ERR_SHIFT) + +/* + * DMA_DONE (RW) + * + * Interrupt enable for DMA done + */ +#define LCDC_INT_EN_DMA_DONE_MASK (0xFF0000UL) +#define LCDC_INT_EN_DMA_DONE_SHIFT (16U) +#define LCDC_INT_EN_DMA_DONE_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_DONE_SHIFT) & LCDC_INT_EN_DMA_DONE_MASK) +#define LCDC_INT_EN_DMA_DONE_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_DONE_MASK) >> LCDC_INT_EN_DMA_DONE_SHIFT) + +/* + * URGENT_UNDERRUN (ROI) + * + * Asserted when the output buffer urgent underrun condition encountered + */ +#define LCDC_INT_EN_URGENT_UNDERRUN_MASK (0x8U) +#define LCDC_INT_EN_URGENT_UNDERRUN_SHIFT (3U) +#define LCDC_INT_EN_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) >> LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) + +/* + * VS_BLANK (RW) + * + * Interrupt enable for start of sof + */ +#define LCDC_INT_EN_VS_BLANK_MASK (0x4U) +#define LCDC_INT_EN_VS_BLANK_SHIFT (2U) +#define LCDC_INT_EN_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VS_BLANK_SHIFT) & LCDC_INT_EN_VS_BLANK_MASK) +#define LCDC_INT_EN_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VS_BLANK_MASK) >> LCDC_INT_EN_VS_BLANK_SHIFT) + +/* + * UNDERRUN (RW) + * + * Interrupt enable for underrun + */ +#define LCDC_INT_EN_UNDERRUN_MASK (0x2U) +#define LCDC_INT_EN_UNDERRUN_SHIFT (1U) +#define LCDC_INT_EN_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_INT_EN_UNDERRUN_SHIFT) & LCDC_INT_EN_UNDERRUN_MASK) +#define LCDC_INT_EN_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_UNDERRUN_MASK) >> LCDC_INT_EN_UNDERRUN_SHIFT) + +/* + * VSYNC (RW) + * + * Interrupt enable for end of sof + */ +#define LCDC_INT_EN_VSYNC_MASK (0x1U) +#define LCDC_INT_EN_VSYNC_SHIFT (0U) +#define LCDC_INT_EN_VSYNC_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VSYNC_SHIFT) & LCDC_INT_EN_VSYNC_MASK) +#define LCDC_INT_EN_VSYNC_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VSYNC_MASK) >> LCDC_INT_EN_VSYNC_SHIFT) + +/* Bitfield definition for register: TXFIFO */ +/* + * THRSH (RW) + * + * Threshold to start the lcd raster (0--0x7F) + */ +#define LCDC_TXFIFO_THRSH_MASK (0xFFU) +#define LCDC_TXFIFO_THRSH_SHIFT (0U) +#define LCDC_TXFIFO_THRSH_SET(x) (((uint32_t)(x) << LCDC_TXFIFO_THRSH_SHIFT) & LCDC_TXFIFO_THRSH_MASK) +#define LCDC_TXFIFO_THRSH_GET(x) (((uint32_t)(x) & LCDC_TXFIFO_THRSH_MASK) >> LCDC_TXFIFO_THRSH_SHIFT) + +/* Bitfield definition for register of struct array LAYER: LAYCTRL */ +/* + * PACK_DIR (RW) + * + * The byte sequence of the 4 bytes in a 32-bit word. + * 1: {A0, A1, A2, A3} byte re-ordered. + * 0: {A3, A2, A1, A0} the normal case with no byte re-order + */ +#define LCDC_LAYER_LAYCTRL_PACK_DIR_MASK (0x80000UL) +#define LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT (19U) +#define LCDC_LAYER_LAYCTRL_PACK_DIR_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) +#define LCDC_LAYER_LAYCTRL_PACK_DIR_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) >> LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) + +/* + * SHADOW_LOAD_EN (RW) + * + * Shadow Load Enable + * The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. + */ +#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK (0x10000UL) +#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT (16U) +#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) +#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) >> LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) + +/* + * YUV_FORMAT (RW) + * + * The YUV422 input format selection. + * 00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 + * 01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 + * 10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 + * 11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 + * If not YUV422 mode, + * FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) + * FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) + */ +#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK (0xC000U) +#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT (14U) +#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) +#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) >> LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) + +/* + * PIXFORMAT (RW) + * + * Layer encoding format (bit per pixel) + * 0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. + * 0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. + * 0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. + * 0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. + * 0100b - 16 bpp (RGB565), byte sequence as B,R + * 0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] + * 1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A + * 1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 + */ +#define LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK (0x3C00U) +#define LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT (10U) +#define LCDC_LAYER_LAYCTRL_PIXFORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) +#define LCDC_LAYER_LAYCTRL_PIXFORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) >> LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) + +/* + * LOCALPHA_OP (RW) + * + * The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) + * 0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream + * 1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) + * 2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream + * Others: Reserved + */ +#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK (0x300U) +#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT (8U) +#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) +#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) + +/* + * INALPHA_OP (RW) + * + * The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) + * 0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline + * 1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) + * 2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline + * Others: Reserved + */ +#define LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK (0xC0U) +#define LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT (6U) +#define LCDC_LAYER_LAYCTRL_INALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) +#define LCDC_LAYER_LAYCTRL_INALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) + +/* + * AB_MODE (RW) + * + * Alpha Blending Mode + * 0: SKBlendMode_Clear; + * 1: SKBlendMode_Src ; + * 2: SKBlendMode_Dst + * 3: SKBlendMode_SrcOver + * 4: SKBlendMode_DstOver + * 5: SKBlendMode_SrcIn + * 6: SKBlendMode_DstIn + * 7: SKBlendMode_SrcOut + * 8: SKBlendMode_DstOut + * 9: SKBlendMode_SrcATop + * 10: SKBlendMode_DstATop + * 11: SKBlendMode_Xor + * 12: SKBlendMode_Plus (The conventional blending mode) + * 13: SKBlendMode_Modulate + * 14: SRC org + * 15: DST org + * Others: Reserved. + */ +#define LCDC_LAYER_LAYCTRL_AB_MODE_MASK (0x3CU) +#define LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT (2U) +#define LCDC_LAYER_LAYCTRL_AB_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) +#define LCDC_LAYER_LAYCTRL_AB_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) >> LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) + +/* + * EN (RW) + * + * Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. + */ +#define LCDC_LAYER_LAYCTRL_EN_MASK (0x1U) +#define LCDC_LAYER_LAYCTRL_EN_SHIFT (0U) +#define LCDC_LAYER_LAYCTRL_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_EN_SHIFT) & LCDC_LAYER_LAYCTRL_EN_MASK) +#define LCDC_LAYER_LAYCTRL_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_EN_MASK) >> LCDC_LAYER_LAYCTRL_EN_SHIFT) + +/* Bitfield definition for register of struct array LAYER: ALPHAS */ +/* + * LOCD (RW) + * + * The system alpha value for the data stream of current layer stream (SRC) + */ +#define LCDC_LAYER_ALPHAS_LOCD_MASK (0xFF00U) +#define LCDC_LAYER_ALPHAS_LOCD_SHIFT (8U) +#define LCDC_LAYER_ALPHAS_LOCD_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_LOCD_SHIFT) & LCDC_LAYER_ALPHAS_LOCD_MASK) +#define LCDC_LAYER_ALPHAS_LOCD_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_LOCD_MASK) >> LCDC_LAYER_ALPHAS_LOCD_SHIFT) + +/* + * IND (RW) + * + * The system alpha value for the input stream from previous stage (DST) + */ +#define LCDC_LAYER_ALPHAS_IND_MASK (0xFFU) +#define LCDC_LAYER_ALPHAS_IND_SHIFT (0U) +#define LCDC_LAYER_ALPHAS_IND_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_IND_SHIFT) & LCDC_LAYER_ALPHAS_IND_MASK) +#define LCDC_LAYER_ALPHAS_IND_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_IND_MASK) >> LCDC_LAYER_ALPHAS_IND_SHIFT) + +/* Bitfield definition for register of struct array LAYER: LAYSIZE */ +/* + * HEIGHT (RW) + * + * Height of the layer in pixels + */ +#define LCDC_LAYER_LAYSIZE_HEIGHT_MASK (0xFFF0000UL) +#define LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT (16U) +#define LCDC_LAYER_LAYSIZE_HEIGHT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) +#define LCDC_LAYER_LAYSIZE_HEIGHT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) >> LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) + +/* + * WIDTH (RW) + * + * Width of the layer in pixels (Note: not actual width-1) + * The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. + */ +#define LCDC_LAYER_LAYSIZE_WIDTH_MASK (0xFFFU) +#define LCDC_LAYER_LAYSIZE_WIDTH_SHIFT (0U) +#define LCDC_LAYER_LAYSIZE_WIDTH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) +#define LCDC_LAYER_LAYSIZE_WIDTH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) >> LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) + +/* Bitfield definition for register of struct array LAYER: LAYPOS */ +/* + * Y (RW) + * + * The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. + */ +#define LCDC_LAYER_LAYPOS_Y_MASK (0xFFFF0000UL) +#define LCDC_LAYER_LAYPOS_Y_SHIFT (16U) +#define LCDC_LAYER_LAYPOS_Y_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_Y_SHIFT) & LCDC_LAYER_LAYPOS_Y_MASK) +#define LCDC_LAYER_LAYPOS_Y_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_Y_MASK) >> LCDC_LAYER_LAYPOS_Y_SHIFT) + +/* + * X (RW) + * + * The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. + */ +#define LCDC_LAYER_LAYPOS_X_MASK (0xFFFFU) +#define LCDC_LAYER_LAYPOS_X_SHIFT (0U) +#define LCDC_LAYER_LAYPOS_X_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_X_SHIFT) & LCDC_LAYER_LAYPOS_X_MASK) +#define LCDC_LAYER_LAYPOS_X_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_X_MASK) >> LCDC_LAYER_LAYPOS_X_SHIFT) + +/* Bitfield definition for register of struct array LAYER: START0 */ +/* + * ADDR0 (RW) + * + * Input buffer Start address 0 + */ +#define LCDC_LAYER_START0_ADDR0_MASK (0xFFFFFFFFUL) +#define LCDC_LAYER_START0_ADDR0_SHIFT (0U) +#define LCDC_LAYER_START0_ADDR0_SET(x) (((uint32_t)(x) << LCDC_LAYER_START0_ADDR0_SHIFT) & LCDC_LAYER_START0_ADDR0_MASK) +#define LCDC_LAYER_START0_ADDR0_GET(x) (((uint32_t)(x) & LCDC_LAYER_START0_ADDR0_MASK) >> LCDC_LAYER_START0_ADDR0_SHIFT) + +/* Bitfield definition for register of struct array LAYER: LINECFG */ +/* + * MPT_SIZE (RW) + * + * Maximal Per Transfer Data Size: + * 0: 64 bytes + * 1: 128 bytes + * 2: 256 bytes + * 3: 512 bytes + * 4: 1024 bytes + */ +#define LCDC_LAYER_LINECFG_MPT_SIZE_MASK (0xE0000000UL) +#define LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT (29U) +#define LCDC_LAYER_LINECFG_MPT_SIZE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) +#define LCDC_LAYER_LINECFG_MPT_SIZE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) >> LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) + +/* + * MAX_OT (RW) + * + * the number of outstanding axi read transactions. + * If zero, it means max 8. + */ +#define LCDC_LAYER_LINECFG_MAX_OT_MASK (0xE00000UL) +#define LCDC_LAYER_LINECFG_MAX_OT_SHIFT (21U) +#define LCDC_LAYER_LINECFG_MAX_OT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MAX_OT_SHIFT) & LCDC_LAYER_LINECFG_MAX_OT_MASK) +#define LCDC_LAYER_LINECFG_MAX_OT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MAX_OT_MASK) >> LCDC_LAYER_LINECFG_MAX_OT_SHIFT) + +/* + * PITCH (RW) + * + * Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. + */ +#define LCDC_LAYER_LINECFG_PITCH_MASK (0xFFFFU) +#define LCDC_LAYER_LINECFG_PITCH_SHIFT (0U) +#define LCDC_LAYER_LINECFG_PITCH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_PITCH_SHIFT) & LCDC_LAYER_LINECFG_PITCH_MASK) +#define LCDC_LAYER_LINECFG_PITCH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_PITCH_MASK) >> LCDC_LAYER_LINECFG_PITCH_SHIFT) + +/* Bitfield definition for register of struct array LAYER: BG_CL */ +/* + * ARGB (RW) + * + * ARGB8888. It is only useful in the last active stage in the pipeline. + */ +#define LCDC_LAYER_BG_CL_ARGB_MASK (0xFFFFFFFFUL) +#define LCDC_LAYER_BG_CL_ARGB_SHIFT (0U) +#define LCDC_LAYER_BG_CL_ARGB_SET(x) (((uint32_t)(x) << LCDC_LAYER_BG_CL_ARGB_SHIFT) & LCDC_LAYER_BG_CL_ARGB_MASK) +#define LCDC_LAYER_BG_CL_ARGB_GET(x) (((uint32_t)(x) & LCDC_LAYER_BG_CL_ARGB_MASK) >> LCDC_LAYER_BG_CL_ARGB_SHIFT) + +/* Bitfield definition for register of struct array LAYER: CSC_COEF0 */ +/* + * YCBCR_MODE (RW) + * + * This bit changes the behavior when performing U/V converting. + * 0b - Converting YUV to RGB data + * 1b - Converting YCbCr to RGB data + */ +#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) +#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT (31U) +#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) +#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) >> LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) + +/* + * ENABLE (RW) + * + * Enable the CSC unit in the LCDC plane data path. + * 0b - The CSC is bypassed and the input pixels are RGB data already + * 1b - The CSC is enabled and the pixels will be converted to RGB data + * This bit will be shadowed. + */ +#define LCDC_LAYER_CSC_COEF0_ENABLE_MASK (0x40000000UL) +#define LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT (30U) +#define LCDC_LAYER_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) +#define LCDC_LAYER_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) >> LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) + +/* + * C0 (RW) + * + * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + */ +#define LCDC_LAYER_CSC_COEF0_C0_MASK (0x1FFC0000UL) +#define LCDC_LAYER_CSC_COEF0_C0_SHIFT (18U) +#define LCDC_LAYER_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_C0_SHIFT) & LCDC_LAYER_CSC_COEF0_C0_MASK) +#define LCDC_LAYER_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_C0_MASK) >> LCDC_LAYER_CSC_COEF0_C0_SHIFT) + +/* + * UV_OFFSET (RW) + * + * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. + * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + */ +#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) +#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT (9U) +#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) +#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) + +/* + * Y_OFFSET (RW) + * + * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is + * typically -16 (0x1F0). + */ +#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) +#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT (0U) +#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) +#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) + +/* Bitfield definition for register of struct array LAYER: CSC_COEF1 */ +/* + * C1 (RW) + * + * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + */ +#define LCDC_LAYER_CSC_COEF1_C1_MASK (0x7FF0000UL) +#define LCDC_LAYER_CSC_COEF1_C1_SHIFT (16U) +#define LCDC_LAYER_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C1_SHIFT) & LCDC_LAYER_CSC_COEF1_C1_MASK) +#define LCDC_LAYER_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C1_MASK) >> LCDC_LAYER_CSC_COEF1_C1_SHIFT) + +/* + * C4 (RW) + * + * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + */ +#define LCDC_LAYER_CSC_COEF1_C4_MASK (0x7FFU) +#define LCDC_LAYER_CSC_COEF1_C4_SHIFT (0U) +#define LCDC_LAYER_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C4_SHIFT) & LCDC_LAYER_CSC_COEF1_C4_MASK) +#define LCDC_LAYER_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C4_MASK) >> LCDC_LAYER_CSC_COEF1_C4_SHIFT) + +/* Bitfield definition for register of struct array LAYER: CSC_COEF2 */ +/* + * C2 (RW) + * + * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + */ +#define LCDC_LAYER_CSC_COEF2_C2_MASK (0x7FF0000UL) +#define LCDC_LAYER_CSC_COEF2_C2_SHIFT (16U) +#define LCDC_LAYER_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C2_SHIFT) & LCDC_LAYER_CSC_COEF2_C2_MASK) +#define LCDC_LAYER_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C2_MASK) >> LCDC_LAYER_CSC_COEF2_C2_SHIFT) + +/* + * C3 (RW) + * + * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + */ +#define LCDC_LAYER_CSC_COEF2_C3_MASK (0x7FFU) +#define LCDC_LAYER_CSC_COEF2_C3_SHIFT (0U) +#define LCDC_LAYER_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C3_SHIFT) & LCDC_LAYER_CSC_COEF2_C3_MASK) +#define LCDC_LAYER_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C3_MASK) >> LCDC_LAYER_CSC_COEF2_C3_SHIFT) + +/* Bitfield definition for register: CLUT_LOAD */ +/* + * SEL_NUM (RW) + * + * Selected CLUT Number + * The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. + * . 3'h0 - PLANE 0 + * . 3'h1 - PLANE 1 + * . ------ + * . 3'h7 - PLANE 7 + * CLUT 8 can be modified via APB even when display is on. + * Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. + */ +#define LCDC_CLUT_LOAD_SEL_NUM_MASK (0x70U) +#define LCDC_CLUT_LOAD_SEL_NUM_SHIFT (4U) +#define LCDC_CLUT_LOAD_SEL_NUM_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_SEL_NUM_SHIFT) & LCDC_CLUT_LOAD_SEL_NUM_MASK) +#define LCDC_CLUT_LOAD_SEL_NUM_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_SEL_NUM_MASK) >> LCDC_CLUT_LOAD_SEL_NUM_SHIFT) + +/* + * UPDATE_EN (RW) + * + * CLUT Update Enable + * The bit is written to 1 when software want to update the Color Look Up Tables during display. + * If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. + * If set to 0, software can update CLUT8 directly according to the CLUT memory map. + * Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. + */ +#define LCDC_CLUT_LOAD_UPDATE_EN_MASK (0x1U) +#define LCDC_CLUT_LOAD_UPDATE_EN_SHIFT (0U) +#define LCDC_CLUT_LOAD_UPDATE_EN_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) +#define LCDC_CLUT_LOAD_UPDATE_EN_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) >> LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) + + + +/* LAYER register group index macro definition */ +#define LCDC_LAYER_0 (0UL) +#define LCDC_LAYER_1 (1UL) +#define LCDC_LAYER_2 (2UL) +#define LCDC_LAYER_3 (3UL) +#define LCDC_LAYER_4 (4UL) +#define LCDC_LAYER_5 (5UL) +#define LCDC_LAYER_6 (6UL) +#define LCDC_LAYER_7 (7UL) + + +#endif /* HPM_LCDC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mbx_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mbx_regs.h new file mode 100644 index 0000000000..f75d851c47 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mbx_regs.h @@ -0,0 +1,346 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MBX_H +#define HPM_MBX_H + +typedef struct { + __RW uint32_t CR; /* 0x0: Command Registers */ + __RW uint32_t SR; /* 0x4: Status Registers */ + __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */ + __R uint32_t RXREG; /* 0xC: Receive word message from other core. */ + __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */ + __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ + __R uint32_t RXWRD[1]; /* 0x20: RXFIFO for receiving message from other core */ +} MBX_Type; + + +/* Bitfield definition for register: CR */ +/* + * TXRESET (RW) + * + * Reset TX Fifo and word. + */ +#define MBX_CR_TXRESET_MASK (0x80000000UL) +#define MBX_CR_TXRESET_SHIFT (31U) +#define MBX_CR_TXRESET_SET(x) (((uint32_t)(x) << MBX_CR_TXRESET_SHIFT) & MBX_CR_TXRESET_MASK) +#define MBX_CR_TXRESET_GET(x) (((uint32_t)(x) & MBX_CR_TXRESET_MASK) >> MBX_CR_TXRESET_SHIFT) + +/* + * BARCTL (RW) + * + * Bus Acccess Response Control, when bit 15:14= + * 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + * 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. + * 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. + * 11: reserved. + */ +#define MBX_CR_BARCTL_MASK (0xC000U) +#define MBX_CR_BARCTL_SHIFT (14U) +#define MBX_CR_BARCTL_SET(x) (((uint32_t)(x) << MBX_CR_BARCTL_SHIFT) & MBX_CR_BARCTL_MASK) +#define MBX_CR_BARCTL_GET(x) (((uint32_t)(x) & MBX_CR_BARCTL_MASK) >> MBX_CR_BARCTL_SHIFT) + +/* + * BEIE (RW) + * + * Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. + * 1, enable the bus access error interrupt. + * 0, disable the bus access error interrupt. + */ +#define MBX_CR_BEIE_MASK (0x100U) +#define MBX_CR_BEIE_SHIFT (8U) +#define MBX_CR_BEIE_SET(x) (((uint32_t)(x) << MBX_CR_BEIE_SHIFT) & MBX_CR_BEIE_MASK) +#define MBX_CR_BEIE_GET(x) (((uint32_t)(x) & MBX_CR_BEIE_MASK) >> MBX_CR_BEIE_SHIFT) + +/* + * TFMAIE (RW) + * + * TX FIFO message available interrupt enable. + * 1, enable the TX FIFO massage available interrupt. + * 0, disable the TX FIFO message available interrupt. + */ +#define MBX_CR_TFMAIE_MASK (0x80U) +#define MBX_CR_TFMAIE_SHIFT (7U) +#define MBX_CR_TFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMAIE_SHIFT) & MBX_CR_TFMAIE_MASK) +#define MBX_CR_TFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMAIE_MASK) >> MBX_CR_TFMAIE_SHIFT) + +/* + * TFMEIE (RW) + * + * TX FIFO message empty interrupt enable. + * 1, enable the TX FIFO massage empty interrupt. + * 0, disable the TX FIFO message empty interrupt. + */ +#define MBX_CR_TFMEIE_MASK (0x40U) +#define MBX_CR_TFMEIE_SHIFT (6U) +#define MBX_CR_TFMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMEIE_SHIFT) & MBX_CR_TFMEIE_MASK) +#define MBX_CR_TFMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMEIE_MASK) >> MBX_CR_TFMEIE_SHIFT) + +/* + * RFMAIE (RW) + * + * RX FIFO message available interrupt enable. + * 1, enable the RX FIFO massage available interrupt. + * 0, disable the RX FIFO message available interrupt. + */ +#define MBX_CR_RFMAIE_MASK (0x20U) +#define MBX_CR_RFMAIE_SHIFT (5U) +#define MBX_CR_RFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMAIE_SHIFT) & MBX_CR_RFMAIE_MASK) +#define MBX_CR_RFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMAIE_MASK) >> MBX_CR_RFMAIE_SHIFT) + +/* + * RFMFIE (RW) + * + * RX fifo message full interrupt enable. + * 1, enable the RX fifo message full interrupt. + * 0, disable the RX fifo message full interrupt. + */ +#define MBX_CR_RFMFIE_MASK (0x10U) +#define MBX_CR_RFMFIE_SHIFT (4U) +#define MBX_CR_RFMFIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMFIE_SHIFT) & MBX_CR_RFMFIE_MASK) +#define MBX_CR_RFMFIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMFIE_MASK) >> MBX_CR_RFMFIE_SHIFT) + +/* + * TWMEIE (RW) + * + * TX word message empty interrupt enable. + * 1, enable the TX word massage empty interrupt. + * 0, disable the TX word message empty interrupt. + */ +#define MBX_CR_TWMEIE_MASK (0x2U) +#define MBX_CR_TWMEIE_SHIFT (1U) +#define MBX_CR_TWMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TWMEIE_SHIFT) & MBX_CR_TWMEIE_MASK) +#define MBX_CR_TWMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TWMEIE_MASK) >> MBX_CR_TWMEIE_SHIFT) + +/* + * RWMVIE (RW) + * + * RX word message valid interrupt enable. + * 1, enable the RX word massage valid interrupt. + * 0, disable the RX word message valid interrupt. + */ +#define MBX_CR_RWMVIE_MASK (0x1U) +#define MBX_CR_RWMVIE_SHIFT (0U) +#define MBX_CR_RWMVIE_SET(x) (((uint32_t)(x) << MBX_CR_RWMVIE_SHIFT) & MBX_CR_RWMVIE_MASK) +#define MBX_CR_RWMVIE_GET(x) (((uint32_t)(x) & MBX_CR_RWMVIE_MASK) >> MBX_CR_RWMVIE_SHIFT) + +/* Bitfield definition for register: SR */ +/* + * RFVC (RO) + * + * RX FIFO valid message count + */ +#define MBX_SR_RFVC_MASK (0xF00000UL) +#define MBX_SR_RFVC_SHIFT (20U) +#define MBX_SR_RFVC_GET(x) (((uint32_t)(x) & MBX_SR_RFVC_MASK) >> MBX_SR_RFVC_SHIFT) + +/* + * TFEC (RO) + * + * TX FIFO empty message word count + */ +#define MBX_SR_TFEC_MASK (0xF0000UL) +#define MBX_SR_TFEC_SHIFT (16U) +#define MBX_SR_TFEC_GET(x) (((uint32_t)(x) & MBX_SR_TFEC_MASK) >> MBX_SR_TFEC_SHIFT) + +/* + * ERRRE (W1C) + * + * bus Error for read when rx word message are still invalid, this bit is W1C bit. + * 1, read from word message when the word message are still invalid will cause this error bit set. + * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + */ +#define MBX_SR_ERRRE_MASK (0x2000U) +#define MBX_SR_ERRRE_SHIFT (13U) +#define MBX_SR_ERRRE_SET(x) (((uint32_t)(x) << MBX_SR_ERRRE_SHIFT) & MBX_SR_ERRRE_MASK) +#define MBX_SR_ERRRE_GET(x) (((uint32_t)(x) & MBX_SR_ERRRE_MASK) >> MBX_SR_ERRRE_SHIFT) + +/* + * EWTRF (W1C) + * + * bus Error for write when tx word message are still valid, this bit is W1C bit. + * 1, write to word message when the word message are still valid will cause this error bit set. + * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + */ +#define MBX_SR_EWTRF_MASK (0x1000U) +#define MBX_SR_EWTRF_SHIFT (12U) +#define MBX_SR_EWTRF_SET(x) (((uint32_t)(x) << MBX_SR_EWTRF_SHIFT) & MBX_SR_EWTRF_MASK) +#define MBX_SR_EWTRF_GET(x) (((uint32_t)(x) & MBX_SR_EWTRF_MASK) >> MBX_SR_EWTRF_SHIFT) + +/* + * ERRFE (W1C) + * + * bus Error for read when rx fifo empty, this bit is W1C bit. + * 1, read from a empty rx fifo will cause this error bit set. + * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + */ +#define MBX_SR_ERRFE_MASK (0x800U) +#define MBX_SR_ERRFE_SHIFT (11U) +#define MBX_SR_ERRFE_SET(x) (((uint32_t)(x) << MBX_SR_ERRFE_SHIFT) & MBX_SR_ERRFE_MASK) +#define MBX_SR_ERRFE_GET(x) (((uint32_t)(x) & MBX_SR_ERRFE_MASK) >> MBX_SR_ERRFE_SHIFT) + +/* + * EWTFF (W1C) + * + * bus Error for write when tx fifo full, this bit is W1C bit. + * 1, write to a fulled tx fifo will cause this error bit set. + * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + */ +#define MBX_SR_EWTFF_MASK (0x400U) +#define MBX_SR_EWTFF_SHIFT (10U) +#define MBX_SR_EWTFF_SET(x) (((uint32_t)(x) << MBX_SR_EWTFF_SHIFT) & MBX_SR_EWTFF_MASK) +#define MBX_SR_EWTFF_GET(x) (((uint32_t)(x) & MBX_SR_EWTFF_MASK) >> MBX_SR_EWTFF_SHIFT) + +/* + * EAIVA (W1C) + * + * bus Error for Accessing Invalid Address; this bit is W1C bit. + * 1, read and write to invalid address in the bus of this block, will set this bit. + * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + */ +#define MBX_SR_EAIVA_MASK (0x200U) +#define MBX_SR_EAIVA_SHIFT (9U) +#define MBX_SR_EAIVA_SET(x) (((uint32_t)(x) << MBX_SR_EAIVA_SHIFT) & MBX_SR_EAIVA_MASK) +#define MBX_SR_EAIVA_GET(x) (((uint32_t)(x) & MBX_SR_EAIVA_MASK) >> MBX_SR_EAIVA_SHIFT) + +/* + * EW2RO (W1C) + * + * bus Error for Write to Read Only address; this bit is W1C bit. + * 1, write to read only address happened in the bus of this block. + * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + */ +#define MBX_SR_EW2RO_MASK (0x100U) +#define MBX_SR_EW2RO_SHIFT (8U) +#define MBX_SR_EW2RO_SET(x) (((uint32_t)(x) << MBX_SR_EW2RO_SHIFT) & MBX_SR_EW2RO_MASK) +#define MBX_SR_EW2RO_GET(x) (((uint32_t)(x) & MBX_SR_EW2RO_MASK) >> MBX_SR_EW2RO_SHIFT) + +/* + * TFMA (RW) + * + * TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. + * 1, TXFIFO message buffer has slot available + * 0, no slot available (fifo full) + */ +#define MBX_SR_TFMA_MASK (0x80U) +#define MBX_SR_TFMA_SHIFT (7U) +#define MBX_SR_TFMA_SET(x) (((uint32_t)(x) << MBX_SR_TFMA_SHIFT) & MBX_SR_TFMA_MASK) +#define MBX_SR_TFMA_GET(x) (((uint32_t)(x) & MBX_SR_TFMA_MASK) >> MBX_SR_TFMA_SHIFT) + +/* + * TFME (RW) + * + * TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. + * 1, no any message data in TXFIFO from other core. + * 0, there are some data in the 4x32 TX FIFO from other core yet. + */ +#define MBX_SR_TFME_MASK (0x40U) +#define MBX_SR_TFME_SHIFT (6U) +#define MBX_SR_TFME_SET(x) (((uint32_t)(x) << MBX_SR_TFME_SHIFT) & MBX_SR_TFME_MASK) +#define MBX_SR_TFME_GET(x) (((uint32_t)(x) & MBX_SR_TFME_MASK) >> MBX_SR_TFME_SHIFT) + +/* + * RFMA (RO) + * + * RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. + * 1, no any data in the 4x32 TXFIFO message buffer. + * 0, there are some data in the the 4x32 TXFIFO message buffer already. + */ +#define MBX_SR_RFMA_MASK (0x20U) +#define MBX_SR_RFMA_SHIFT (5U) +#define MBX_SR_RFMA_GET(x) (((uint32_t)(x) & MBX_SR_RFMA_MASK) >> MBX_SR_RFMA_SHIFT) + +/* + * RFMF (RO) + * + * RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. + * 1, the other core had written 4x32 message in the RXFIFO. + * 0, no 4x32 RX FIFO message from other core yet. + */ +#define MBX_SR_RFMF_MASK (0x10U) +#define MBX_SR_RFMF_SHIFT (4U) +#define MBX_SR_RFMF_GET(x) (((uint32_t)(x) & MBX_SR_RFMF_MASK) >> MBX_SR_RFMF_SHIFT) + +/* + * TWME (RO) + * + * TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. + * 1, means this core had write word message to TXREG. + * 0, means no valid word message in the TXREG yet. + */ +#define MBX_SR_TWME_MASK (0x2U) +#define MBX_SR_TWME_SHIFT (1U) +#define MBX_SR_TWME_GET(x) (((uint32_t)(x) & MBX_SR_TWME_MASK) >> MBX_SR_TWME_SHIFT) + +/* + * RWMV (RO) + * + * RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. + * 1, the other core had written word message in the RXREG. + * 0, no valid word message yet in the RXREG. + */ +#define MBX_SR_RWMV_MASK (0x1U) +#define MBX_SR_RWMV_SHIFT (0U) +#define MBX_SR_RWMV_GET(x) (((uint32_t)(x) & MBX_SR_RWMV_MASK) >> MBX_SR_RWMV_SHIFT) + +/* Bitfield definition for register: TXREG */ +/* + * TXREG (WO) + * + * Transmit word message to other core. + */ +#define MBX_TXREG_TXREG_MASK (0xFFFFFFFFUL) +#define MBX_TXREG_TXREG_SHIFT (0U) +#define MBX_TXREG_TXREG_SET(x) (((uint32_t)(x) << MBX_TXREG_TXREG_SHIFT) & MBX_TXREG_TXREG_MASK) +#define MBX_TXREG_TXREG_GET(x) (((uint32_t)(x) & MBX_TXREG_TXREG_MASK) >> MBX_TXREG_TXREG_SHIFT) + +/* Bitfield definition for register: RXREG */ +/* + * RXREG (RO) + * + * Receive word message from other core. + */ +#define MBX_RXREG_RXREG_MASK (0xFFFFFFFFUL) +#define MBX_RXREG_RXREG_SHIFT (0U) +#define MBX_RXREG_RXREG_GET(x) (((uint32_t)(x) & MBX_RXREG_RXREG_MASK) >> MBX_RXREG_RXREG_SHIFT) + +/* Bitfield definition for register array: TXWRD */ +/* + * TXFIFO (WO) + * + * TXFIFO for sending message to other core, FIFO size, 4x32 + * can write one of the word address to push data to the FIFO; + * can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + */ +#define MBX_TXWRD_TXFIFO_MASK (0xFFFFFFFFUL) +#define MBX_TXWRD_TXFIFO_SHIFT (0U) +#define MBX_TXWRD_TXFIFO_SET(x) (((uint32_t)(x) << MBX_TXWRD_TXFIFO_SHIFT) & MBX_TXWRD_TXFIFO_MASK) +#define MBX_TXWRD_TXFIFO_GET(x) (((uint32_t)(x) & MBX_TXWRD_TXFIFO_MASK) >> MBX_TXWRD_TXFIFO_SHIFT) + +/* Bitfield definition for register array: RXWRD */ +/* + * RXFIFO (RO) + * + * RXFIFO for receiving message from other core, FIFO size, 4x32 + * can read one of the word address to pop data to the FIFO; + * can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + */ +#define MBX_RXWRD_RXFIFO_MASK (0xFFFFFFFFUL) +#define MBX_RXWRD_RXFIFO_SHIFT (0U) +#define MBX_RXWRD_RXFIFO_GET(x) (((uint32_t)(x) & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT) + + + +/* TXWRD register group index macro definition */ +#define MBX_TXWRD_TXFIFO0 (0UL) + +/* RXWRD register group index macro definition */ +#define MBX_RXWRD_RXFIFO0 (0UL) + + +#endif /* HPM_MBX_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mchtmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mchtmr_regs.h new file mode 100644 index 0000000000..e54a80d7e2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mchtmr_regs.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MCHTMR_H +#define HPM_MCHTMR_H + +typedef struct { + __RW uint64_t MTIME; /* 0x0: Machine Time */ + __RW uint64_t MTIMECMP; /* 0x8: Machine Time Compare */ +} MCHTMR_Type; + + +/* Bitfield definition for register: MTIME */ +/* + * MTIME (RW) + * + * Machine time + */ +#define MCHTMR_MTIME_MTIME_MASK (0xFFFFFFFFFFFFFFFFULL) +#define MCHTMR_MTIME_MTIME_SHIFT (0U) +#define MCHTMR_MTIME_MTIME_SET(x) (((uint64_t)(x) << MCHTMR_MTIME_MTIME_SHIFT) & MCHTMR_MTIME_MTIME_MASK) +#define MCHTMR_MTIME_MTIME_GET(x) (((uint64_t)(x) & MCHTMR_MTIME_MTIME_MASK) >> MCHTMR_MTIME_MTIME_SHIFT) + +/* Bitfield definition for register: MTIMECMP */ +/* + * MTIMECMP (RW) + * + * Machine time compare + */ +#define MCHTMR_MTIMECMP_MTIMECMP_MASK (0xFFFFFFFFFFFFFFFFULL) +#define MCHTMR_MTIMECMP_MTIMECMP_SHIFT (0U) +#define MCHTMR_MTIMECMP_MTIMECMP_SET(x) (((uint64_t)(x) << MCHTMR_MTIMECMP_MTIMECMP_SHIFT) & MCHTMR_MTIMECMP_MTIMECMP_MASK) +#define MCHTMR_MTIMECMP_MTIMECMP_GET(x) (((uint64_t)(x) & MCHTMR_MTIMECMP_MTIMECMP_MASK) >> MCHTMR_MTIMECMP_MTIMECMP_SHIFT) + + + + +#endif /* HPM_MCHTMR_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h new file mode 100644 index 0000000000..9b39012b95 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MON_H +#define HPM_MON_H + +typedef struct { + struct { + __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ + __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ + } MONITOR[4]; + __RW uint32_t TEST_MODE; /* 0x20: */ + __R uint8_t RESERVED0[28]; /* 0x24 - 0x3F: Reserved */ + __RW uint32_t IRQ_FLAG; /* 0x40: */ + __RW uint32_t IRQ_ENABLE; /* 0x44: */ +} MON_Type; + + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * ACTIVE (RW) + * + * select glitch works in active mode or passve mode. + * 0: passive mode, depends on power glitch destory DFF value + * 1: active mode, check glitch by DFF chain + */ +#define MON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) +#define MON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) +#define MON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << MON_MONITOR_CONTROL_ACTIVE_SHIFT) & MON_MONITOR_CONTROL_ACTIVE_MASK) +#define MON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & MON_MONITOR_CONTROL_ACTIVE_MASK) >> MON_MONITOR_CONTROL_ACTIVE_SHIFT) + +/* + * ENABLE (RW) + * + * enable glitch detector + * 0: detector disabled + * 1: detector enabled + */ +#define MON_MONITOR_CONTROL_ENABLE_MASK (0x1U) +#define MON_MONITOR_CONTROL_ENABLE_SHIFT (0U) +#define MON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << MON_MONITOR_CONTROL_ENABLE_SHIFT) & MON_MONITOR_CONTROL_ENABLE_MASK) +#define MON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & MON_MONITOR_CONTROL_ENABLE_MASK) >> MON_MONITOR_CONTROL_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: STATUS */ +/* + * FLAG (RW) + * + * flag for glitch detected, write 1 to clear this flag + * 0: glitch not detected + * 1: glitch detected + */ +#define MON_MONITOR_STATUS_FLAG_MASK (0x1U) +#define MON_MONITOR_STATUS_FLAG_SHIFT (0U) +#define MON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << MON_MONITOR_STATUS_FLAG_SHIFT) & MON_MONITOR_STATUS_FLAG_MASK) +#define MON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & MON_MONITOR_STATUS_FLAG_MASK) >> MON_MONITOR_STATUS_FLAG_SHIFT) + +/* Bitfield definition for register: TEST_MODE */ +/* + * DISABLE (RW) + * + * disable test mode entry, any non-zero value written to this register causes disable bit set + * 0: test mode enabled + * 1: test mode disabled + * Note: This register only available in BATT domain + */ +#define MON_TEST_MODE_DISABLE_MASK (0xFFFFFFFFUL) +#define MON_TEST_MODE_DISABLE_SHIFT (0U) +#define MON_TEST_MODE_DISABLE_SET(x) (((uint32_t)(x) << MON_TEST_MODE_DISABLE_SHIFT) & MON_TEST_MODE_DISABLE_MASK) +#define MON_TEST_MODE_DISABLE_GET(x) (((uint32_t)(x) & MON_TEST_MODE_DISABLE_MASK) >> MON_TEST_MODE_DISABLE_SHIFT) + +/* Bitfield definition for register: IRQ_FLAG */ +/* + * FLAG (RW) + * + * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag + * 0: no monitor interrupt + * 1: monitor interrupt happened + * Note: This register only available in PMIC domain + */ +#define MON_IRQ_FLAG_FLAG_MASK (0xFU) +#define MON_IRQ_FLAG_FLAG_SHIFT (0U) +#define MON_IRQ_FLAG_FLAG_SET(x) (((uint32_t)(x) << MON_IRQ_FLAG_FLAG_SHIFT) & MON_IRQ_FLAG_FLAG_MASK) +#define MON_IRQ_FLAG_FLAG_GET(x) (((uint32_t)(x) & MON_IRQ_FLAG_FLAG_MASK) >> MON_IRQ_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: IRQ_ENABLE */ +/* + * ENABLE (RW) + * + * interrupt enable, each bit represents for one monitor + * 0: monitor interrupt disabled + * 1: monitor interrupt enabled + * Note: This register only available in PMIC domain + */ +#define MON_IRQ_ENABLE_ENABLE_MASK (0xFU) +#define MON_IRQ_ENABLE_ENABLE_SHIFT (0U) +#define MON_IRQ_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << MON_IRQ_ENABLE_ENABLE_SHIFT) & MON_IRQ_ENABLE_ENABLE_MASK) +#define MON_IRQ_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & MON_IRQ_ENABLE_ENABLE_MASK) >> MON_IRQ_ENABLE_ENABLE_SHIFT) + + + +/* MONITOR register group index macro definition */ +#define MON_MONITOR_GLITCH0 (0UL) +#define MON_MONITOR_GLITCH1 (1UL) +#define MON_MONITOR_CLOCK0 (2UL) +#define MON_MONITOR_CLOCK1 (3UL) + + +#endif /* HPM_MON_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h new file mode 100644 index 0000000000..0db009eabf --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mono_regs.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MONO_H +#define HPM_MONO_H + +typedef struct { + __RW uint32_t MONOL; /* 0x0: Low part of monotonic counter */ + __RW uint32_t MONOH; /* 0x4: High part of monotonic counter */ +} MONO_Type; + + +/* Bitfield definition for register: MONOL */ +/* + * COUNTER (RW) + * + * low part of monotonica counter, write to this counter will cause counter increase by 1 + */ +#define MONO_MONOL_COUNTER_MASK (0xFFFFFFFFUL) +#define MONO_MONOL_COUNTER_SHIFT (0U) +#define MONO_MONOL_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOL_COUNTER_SHIFT) & MONO_MONOL_COUNTER_MASK) +#define MONO_MONOL_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOL_COUNTER_MASK) >> MONO_MONOL_COUNTER_SHIFT) + +/* Bitfield definition for register: MONOH */ +/* + * EPOCH (RW) + * + * Fuse value for high part of monotonica + */ +#define MONO_MONOH_EPOCH_MASK (0xFFFF0000UL) +#define MONO_MONOH_EPOCH_SHIFT (16U) +#define MONO_MONOH_EPOCH_SET(x) (((uint32_t)(x) << MONO_MONOH_EPOCH_SHIFT) & MONO_MONOH_EPOCH_MASK) +#define MONO_MONOH_EPOCH_GET(x) (((uint32_t)(x) & MONO_MONOH_EPOCH_MASK) >> MONO_MONOH_EPOCH_SHIFT) + +/* + * COUNTER (RW) + * + * high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow + */ +#define MONO_MONOH_COUNTER_MASK (0xFFFFU) +#define MONO_MONOH_COUNTER_SHIFT (0U) +#define MONO_MONOH_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOH_COUNTER_SHIFT) & MONO_MONOH_COUNTER_MASK) +#define MONO_MONOH_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOH_COUNTER_MASK) >> MONO_MONOH_COUNTER_SHIFT) + + + + +#endif /* HPM_MONO_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_otp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_otp_regs.h new file mode 100644 index 0000000000..821405f19b --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_otp_regs.h @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_OTP_H +#define HPM_OTP_H + +typedef struct { + __RW uint32_t SHADOW[128]; /* 0x0 - 0x1FC: Fuse shadow registers */ + __RW uint32_t SHADOW_LOCK[8]; /* 0x200 - 0x21C: Fuse shadow lock */ + __R uint8_t RESERVED0[480]; /* 0x220 - 0x3FF: Reserved */ + __RW uint32_t FUSE[128]; /* 0x400 - 0x5FC: Fuse Array */ + __RW uint32_t FUSE_LOCK[8]; /* 0x600 - 0x61C: Fuse lock */ + __R uint8_t RESERVED1[480]; /* 0x620 - 0x7FF: Reserved */ + __RW uint32_t UNLOCK; /* 0x800: UNLOCK */ + __RW uint32_t DATA; /* 0x804: DATA */ + __RW uint32_t ADDR; /* 0x808: ADDR */ + __RW uint32_t CMD; /* 0x80C: CMD */ + __R uint8_t RESERVED2[496]; /* 0x810 - 0x9FF: Reserved */ + __RW uint32_t LOAD_REQ; /* 0xA00: LOAD Request */ + __RW uint32_t LOAD_COMP; /* 0xA04: LOAD complete */ + __R uint8_t RESERVED3[24]; /* 0xA08 - 0xA1F: Reserved */ + __RW uint32_t REGION[4]; /* 0xA20 - 0xA2C: LOAD region */ + __R uint8_t RESERVED4[464]; /* 0xA30 - 0xBFF: Reserved */ + __RW uint32_t INT_FLAG; /* 0xC00: interrupt flag */ + __RW uint32_t INT_EN; /* 0xC04: interrupt enable */ +} OTP_Type; + + +/* Bitfield definition for register array: SHADOW */ +/* + * SHADOW (RW) + * + * shadow register of fuse for pmic area + * for PMIC, index valid for 0-15, for SOC index valid for 16-128 + */ +#define OTP_SHADOW_SHADOW_MASK (0xFFFFFFFFUL) +#define OTP_SHADOW_SHADOW_SHIFT (0U) +#define OTP_SHADOW_SHADOW_SET(x) (((uint32_t)(x) << OTP_SHADOW_SHADOW_SHIFT) & OTP_SHADOW_SHADOW_MASK) +#define OTP_SHADOW_SHADOW_GET(x) (((uint32_t)(x) & OTP_SHADOW_SHADOW_MASK) >> OTP_SHADOW_SHADOW_SHIFT) + +/* Bitfield definition for register array: SHADOW_LOCK */ +/* + * LOCK (RW) + * + * lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types + * 00: not locked + * 01: soft locked + * 10: not locked, and cannot lock in furture + * 11: double locked + */ +#define OTP_SHADOW_LOCK_LOCK_MASK (0xFFFFFFFFUL) +#define OTP_SHADOW_LOCK_LOCK_SHIFT (0U) +#define OTP_SHADOW_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_SHADOW_LOCK_LOCK_SHIFT) & OTP_SHADOW_LOCK_LOCK_MASK) +#define OTP_SHADOW_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_SHADOW_LOCK_LOCK_MASK) >> OTP_SHADOW_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register array: FUSE */ +/* + * FUSE (RW) + * + * fuse array, valid in PMIC part only + * read operation will read out value in fuse array + * write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + */ +#define OTP_FUSE_FUSE_MASK (0xFFFFFFFFUL) +#define OTP_FUSE_FUSE_SHIFT (0U) +#define OTP_FUSE_FUSE_SET(x) (((uint32_t)(x) << OTP_FUSE_FUSE_SHIFT) & OTP_FUSE_FUSE_MASK) +#define OTP_FUSE_FUSE_GET(x) (((uint32_t)(x) & OTP_FUSE_FUSE_MASK) >> OTP_FUSE_FUSE_SHIFT) + +/* Bitfield definition for register array: FUSE_LOCK */ +/* + * LOCK (RW) + * + * lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types + * 00: not locked + * 01: soft locked + * 10: not locked, and cannot lock in furture + * 11: double locked + */ +#define OTP_FUSE_LOCK_LOCK_MASK (0xFFFFFFFFUL) +#define OTP_FUSE_LOCK_LOCK_SHIFT (0U) +#define OTP_FUSE_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_FUSE_LOCK_LOCK_SHIFT) & OTP_FUSE_LOCK_LOCK_MASK) +#define OTP_FUSE_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_FUSE_LOCK_LOCK_MASK) >> OTP_FUSE_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register: UNLOCK */ +/* + * UNLOCK (RW) + * + * unlock word for fuse array operation + * write "OPEN" to unlock fuse array, write any other value will lock write to fuse. + * Please make sure 24M crystal is running and 2.5V LDO working properly + */ +#define OTP_UNLOCK_UNLOCK_MASK (0xFFFFFFFFUL) +#define OTP_UNLOCK_UNLOCK_SHIFT (0U) +#define OTP_UNLOCK_UNLOCK_SET(x) (((uint32_t)(x) << OTP_UNLOCK_UNLOCK_SHIFT) & OTP_UNLOCK_UNLOCK_MASK) +#define OTP_UNLOCK_UNLOCK_GET(x) (((uint32_t)(x) & OTP_UNLOCK_UNLOCK_MASK) >> OTP_UNLOCK_UNLOCK_SHIFT) + +/* Bitfield definition for register: DATA */ +/* + * DATA (RW) + * + * data register for non-blocking access + * this register hold dat read from fuse array or data to by programmed to fuse array + */ +#define OTP_DATA_DATA_MASK (0xFFFFFFFFUL) +#define OTP_DATA_DATA_SHIFT (0U) +#define OTP_DATA_DATA_SET(x) (((uint32_t)(x) << OTP_DATA_DATA_SHIFT) & OTP_DATA_DATA_MASK) +#define OTP_DATA_DATA_GET(x) (((uint32_t)(x) & OTP_DATA_DATA_MASK) >> OTP_DATA_DATA_SHIFT) + +/* Bitfield definition for register: ADDR */ +/* + * ADDR (RW) + * + * word address to be read or write + */ +#define OTP_ADDR_ADDR_MASK (0x7FU) +#define OTP_ADDR_ADDR_SHIFT (0U) +#define OTP_ADDR_ADDR_SET(x) (((uint32_t)(x) << OTP_ADDR_ADDR_SHIFT) & OTP_ADDR_ADDR_MASK) +#define OTP_ADDR_ADDR_GET(x) (((uint32_t)(x) & OTP_ADDR_ADDR_MASK) >> OTP_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register: CMD */ +/* + * CMD (RW) + * + * command to access fure array + * "BLOW" will update fuse word at ADDR to value hold in DATA + * "READ" will fetch fuse value in at ADDR to DATA register + */ +#define OTP_CMD_CMD_MASK (0xFFFFFFFFUL) +#define OTP_CMD_CMD_SHIFT (0U) +#define OTP_CMD_CMD_SET(x) (((uint32_t)(x) << OTP_CMD_CMD_SHIFT) & OTP_CMD_CMD_MASK) +#define OTP_CMD_CMD_GET(x) (((uint32_t)(x) & OTP_CMD_CMD_MASK) >> OTP_CMD_CMD_SHIFT) + +/* Bitfield definition for register: LOAD_REQ */ +/* + * REQUEST (RW) + * + * reload request for 4 regions + * bit0: region0 + * bit1: region1 + * bit2: region2 + * bit3: region3 + */ +#define OTP_LOAD_REQ_REQUEST_MASK (0xFU) +#define OTP_LOAD_REQ_REQUEST_SHIFT (0U) +#define OTP_LOAD_REQ_REQUEST_SET(x) (((uint32_t)(x) << OTP_LOAD_REQ_REQUEST_SHIFT) & OTP_LOAD_REQ_REQUEST_MASK) +#define OTP_LOAD_REQ_REQUEST_GET(x) (((uint32_t)(x) & OTP_LOAD_REQ_REQUEST_MASK) >> OTP_LOAD_REQ_REQUEST_SHIFT) + +/* Bitfield definition for register: LOAD_COMP */ +/* + * COMPLETE (RW) + * + * reload complete sign for 4 regions + * bit0: region 0 + * bit1: region1 + * bit2: region2 + * bit3: region3 + */ +#define OTP_LOAD_COMP_COMPLETE_MASK (0xFU) +#define OTP_LOAD_COMP_COMPLETE_SHIFT (0U) +#define OTP_LOAD_COMP_COMPLETE_SET(x) (((uint32_t)(x) << OTP_LOAD_COMP_COMPLETE_SHIFT) & OTP_LOAD_COMP_COMPLETE_MASK) +#define OTP_LOAD_COMP_COMPLETE_GET(x) (((uint32_t)(x) & OTP_LOAD_COMP_COMPLETE_MASK) >> OTP_LOAD_COMP_COMPLETE_SHIFT) + +/* Bitfield definition for register array: REGION */ +/* + * STOP (RW) + * + * stop address of load region, fuse word at end address will NOT be reloaded + * region0: fixed at 8 + * region1: fixed at 16 + * region2: fixed at 0, + * region3: usrer configurable + */ +#define OTP_REGION_STOP_MASK (0x7F00U) +#define OTP_REGION_STOP_SHIFT (8U) +#define OTP_REGION_STOP_SET(x) (((uint32_t)(x) << OTP_REGION_STOP_SHIFT) & OTP_REGION_STOP_MASK) +#define OTP_REGION_STOP_GET(x) (((uint32_t)(x) & OTP_REGION_STOP_MASK) >> OTP_REGION_STOP_SHIFT) + +/* + * START (RW) + * + * start address of load region, fuse word at start address will be reloaded + * region0: fixed at 0 + * region1: fixed at 8 + * region2: fixed at 16, + * region3: usrer configurable + */ +#define OTP_REGION_START_MASK (0x7FU) +#define OTP_REGION_START_SHIFT (0U) +#define OTP_REGION_START_SET(x) (((uint32_t)(x) << OTP_REGION_START_SHIFT) & OTP_REGION_START_MASK) +#define OTP_REGION_START_GET(x) (((uint32_t)(x) & OTP_REGION_START_MASK) >> OTP_REGION_START_SHIFT) + +/* Bitfield definition for register: INT_FLAG */ +/* + * WRITE (RW) + * + * fuse write flag, write 1 to clear + * 0: fuse is not written or writing + * 1: value in DATA register is programmed into fuse + */ +#define OTP_INT_FLAG_WRITE_MASK (0x4U) +#define OTP_INT_FLAG_WRITE_SHIFT (2U) +#define OTP_INT_FLAG_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_WRITE_SHIFT) & OTP_INT_FLAG_WRITE_MASK) +#define OTP_INT_FLAG_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_WRITE_MASK) >> OTP_INT_FLAG_WRITE_SHIFT) + +/* + * READ (RW) + * + * fuse read flag, write 1 to clear + * 0: fuse is not read or reading + * 1: fuse value is put in DATA register + */ +#define OTP_INT_FLAG_READ_MASK (0x2U) +#define OTP_INT_FLAG_READ_SHIFT (1U) +#define OTP_INT_FLAG_READ_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_READ_SHIFT) & OTP_INT_FLAG_READ_MASK) +#define OTP_INT_FLAG_READ_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_READ_MASK) >> OTP_INT_FLAG_READ_SHIFT) + +/* + * LOAD (RW) + * + * fuse load flag, write 1 to clear + * 0: fuse is not loaded or loading + * 1: fuse loaded + */ +#define OTP_INT_FLAG_LOAD_MASK (0x1U) +#define OTP_INT_FLAG_LOAD_SHIFT (0U) +#define OTP_INT_FLAG_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_LOAD_SHIFT) & OTP_INT_FLAG_LOAD_MASK) +#define OTP_INT_FLAG_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_LOAD_MASK) >> OTP_INT_FLAG_LOAD_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * WRITE (RW) + * + * fuse write interrupt enable + * 0: fuse write interrupt is not enable + * 1: fuse write interrupt is enable + */ +#define OTP_INT_EN_WRITE_MASK (0x4U) +#define OTP_INT_EN_WRITE_SHIFT (2U) +#define OTP_INT_EN_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_EN_WRITE_SHIFT) & OTP_INT_EN_WRITE_MASK) +#define OTP_INT_EN_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_EN_WRITE_MASK) >> OTP_INT_EN_WRITE_SHIFT) + +/* + * READ (RW) + * + * fuse read interrupt enable + * 0: fuse read interrupt is not enable + * 1: fuse read interrupt is enable + */ +#define OTP_INT_EN_READ_MASK (0x2U) +#define OTP_INT_EN_READ_SHIFT (1U) +#define OTP_INT_EN_READ_SET(x) (((uint32_t)(x) << OTP_INT_EN_READ_SHIFT) & OTP_INT_EN_READ_MASK) +#define OTP_INT_EN_READ_GET(x) (((uint32_t)(x) & OTP_INT_EN_READ_MASK) >> OTP_INT_EN_READ_SHIFT) + +/* + * LOAD (RW) + * + * fuse load interrupt enable + * 0: fuse load interrupt is not enable + * 1: fuse load interrupt is enable + */ +#define OTP_INT_EN_LOAD_MASK (0x1U) +#define OTP_INT_EN_LOAD_SHIFT (0U) +#define OTP_INT_EN_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_EN_LOAD_SHIFT) & OTP_INT_EN_LOAD_MASK) +#define OTP_INT_EN_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_EN_LOAD_MASK) >> OTP_INT_EN_LOAD_SHIFT) + + + +/* SHADOW register group index macro definition */ +#define OTP_SHADOW_SHADOW000 (0UL) +#define OTP_SHADOW_SHADOW001 (1UL) +#define OTP_SHADOW_SHADOW002 (2UL) +#define OTP_SHADOW_SHADOW003 (3UL) +#define OTP_SHADOW_SHADOW004 (4UL) +#define OTP_SHADOW_SHADOW005 (5UL) +#define OTP_SHADOW_SHADOW006 (6UL) +#define OTP_SHADOW_SHADOW007 (7UL) +#define OTP_SHADOW_SHADOW008 (8UL) +#define OTP_SHADOW_SHADOW009 (9UL) +#define OTP_SHADOW_SHADOW010 (10UL) +#define OTP_SHADOW_SHADOW011 (11UL) +#define OTP_SHADOW_SHADOW012 (12UL) +#define OTP_SHADOW_SHADOW013 (13UL) +#define OTP_SHADOW_SHADOW014 (14UL) +#define OTP_SHADOW_SHADOW015 (15UL) +#define OTP_SHADOW_SHADOW016 (16UL) +#define OTP_SHADOW_SHADOW017 (17UL) +#define OTP_SHADOW_SHADOW018 (18UL) +#define OTP_SHADOW_SHADOW019 (19UL) +#define OTP_SHADOW_SHADOW020 (20UL) +#define OTP_SHADOW_SHADOW021 (21UL) +#define OTP_SHADOW_SHADOW022 (22UL) +#define OTP_SHADOW_SHADOW023 (23UL) +#define OTP_SHADOW_SHADOW024 (24UL) +#define OTP_SHADOW_SHADOW025 (25UL) +#define OTP_SHADOW_SHADOW026 (26UL) +#define OTP_SHADOW_SHADOW027 (27UL) +#define OTP_SHADOW_SHADOW028 (28UL) +#define OTP_SHADOW_SHADOW029 (29UL) +#define OTP_SHADOW_SHADOW030 (30UL) +#define OTP_SHADOW_SHADOW031 (31UL) +#define OTP_SHADOW_SHADOW032 (32UL) +#define OTP_SHADOW_SHADOW033 (33UL) +#define OTP_SHADOW_SHADOW034 (34UL) +#define OTP_SHADOW_SHADOW035 (35UL) +#define OTP_SHADOW_SHADOW036 (36UL) +#define OTP_SHADOW_SHADOW037 (37UL) +#define OTP_SHADOW_SHADOW038 (38UL) +#define OTP_SHADOW_SHADOW039 (39UL) +#define OTP_SHADOW_SHADOW040 (40UL) +#define OTP_SHADOW_SHADOW041 (41UL) +#define OTP_SHADOW_SHADOW042 (42UL) +#define OTP_SHADOW_SHADOW043 (43UL) +#define OTP_SHADOW_SHADOW044 (44UL) +#define OTP_SHADOW_SHADOW045 (45UL) +#define OTP_SHADOW_SHADOW046 (46UL) +#define OTP_SHADOW_SHADOW047 (47UL) +#define OTP_SHADOW_SHADOW048 (48UL) +#define OTP_SHADOW_SHADOW049 (49UL) +#define OTP_SHADOW_SHADOW050 (50UL) +#define OTP_SHADOW_SHADOW051 (51UL) +#define OTP_SHADOW_SHADOW052 (52UL) +#define OTP_SHADOW_SHADOW053 (53UL) +#define OTP_SHADOW_SHADOW054 (54UL) +#define OTP_SHADOW_SHADOW055 (55UL) +#define OTP_SHADOW_SHADOW056 (56UL) +#define OTP_SHADOW_SHADOW057 (57UL) +#define OTP_SHADOW_SHADOW058 (58UL) +#define OTP_SHADOW_SHADOW059 (59UL) +#define OTP_SHADOW_SHADOW060 (60UL) +#define OTP_SHADOW_SHADOW061 (61UL) +#define OTP_SHADOW_SHADOW062 (62UL) +#define OTP_SHADOW_SHADOW063 (63UL) +#define OTP_SHADOW_SHADOW064 (64UL) +#define OTP_SHADOW_SHADOW065 (65UL) +#define OTP_SHADOW_SHADOW066 (66UL) +#define OTP_SHADOW_SHADOW067 (67UL) +#define OTP_SHADOW_SHADOW068 (68UL) +#define OTP_SHADOW_SHADOW069 (69UL) +#define OTP_SHADOW_SHADOW070 (70UL) +#define OTP_SHADOW_SHADOW071 (71UL) +#define OTP_SHADOW_SHADOW072 (72UL) +#define OTP_SHADOW_SHADOW073 (73UL) +#define OTP_SHADOW_SHADOW074 (74UL) +#define OTP_SHADOW_SHADOW075 (75UL) +#define OTP_SHADOW_SHADOW076 (76UL) +#define OTP_SHADOW_SHADOW077 (77UL) +#define OTP_SHADOW_SHADOW078 (78UL) +#define OTP_SHADOW_SHADOW079 (79UL) +#define OTP_SHADOW_SHADOW080 (80UL) +#define OTP_SHADOW_SHADOW081 (81UL) +#define OTP_SHADOW_SHADOW082 (82UL) +#define OTP_SHADOW_SHADOW083 (83UL) +#define OTP_SHADOW_SHADOW084 (84UL) +#define OTP_SHADOW_SHADOW085 (85UL) +#define OTP_SHADOW_SHADOW086 (86UL) +#define OTP_SHADOW_SHADOW087 (87UL) +#define OTP_SHADOW_SHADOW088 (88UL) +#define OTP_SHADOW_SHADOW089 (89UL) +#define OTP_SHADOW_SHADOW090 (90UL) +#define OTP_SHADOW_SHADOW091 (91UL) +#define OTP_SHADOW_SHADOW092 (92UL) +#define OTP_SHADOW_SHADOW093 (93UL) +#define OTP_SHADOW_SHADOW094 (94UL) +#define OTP_SHADOW_SHADOW095 (95UL) +#define OTP_SHADOW_SHADOW096 (96UL) +#define OTP_SHADOW_SHADOW097 (97UL) +#define OTP_SHADOW_SHADOW098 (98UL) +#define OTP_SHADOW_SHADOW099 (99UL) +#define OTP_SHADOW_SHADOW100 (100UL) +#define OTP_SHADOW_SHADOW101 (101UL) +#define OTP_SHADOW_SHADOW102 (102UL) +#define OTP_SHADOW_SHADOW103 (103UL) +#define OTP_SHADOW_SHADOW104 (104UL) +#define OTP_SHADOW_SHADOW105 (105UL) +#define OTP_SHADOW_SHADOW106 (106UL) +#define OTP_SHADOW_SHADOW107 (107UL) +#define OTP_SHADOW_SHADOW108 (108UL) +#define OTP_SHADOW_SHADOW109 (109UL) +#define OTP_SHADOW_SHADOW110 (110UL) +#define OTP_SHADOW_SHADOW111 (111UL) +#define OTP_SHADOW_SHADOW112 (112UL) +#define OTP_SHADOW_SHADOW113 (113UL) +#define OTP_SHADOW_SHADOW114 (114UL) +#define OTP_SHADOW_SHADOW115 (115UL) +#define OTP_SHADOW_SHADOW116 (116UL) +#define OTP_SHADOW_SHADOW117 (117UL) +#define OTP_SHADOW_SHADOW118 (118UL) +#define OTP_SHADOW_SHADOW119 (119UL) +#define OTP_SHADOW_SHADOW120 (120UL) +#define OTP_SHADOW_SHADOW121 (121UL) +#define OTP_SHADOW_SHADOW122 (122UL) +#define OTP_SHADOW_SHADOW123 (123UL) +#define OTP_SHADOW_SHADOW124 (124UL) +#define OTP_SHADOW_SHADOW125 (125UL) +#define OTP_SHADOW_SHADOW126 (126UL) +#define OTP_SHADOW_SHADOW127 (127UL) + +/* SHADOW_LOCK register group index macro definition */ +#define OTP_SHADOW_LOCK_LOCK00 (0UL) +#define OTP_SHADOW_LOCK_LOCK01 (1UL) +#define OTP_SHADOW_LOCK_LOCK02 (2UL) +#define OTP_SHADOW_LOCK_LOCK03 (3UL) +#define OTP_SHADOW_LOCK_LOCK04 (4UL) +#define OTP_SHADOW_LOCK_LOCK05 (5UL) +#define OTP_SHADOW_LOCK_LOCK06 (6UL) +#define OTP_SHADOW_LOCK_LOCK07 (7UL) + +/* FUSE register group index macro definition */ +#define OTP_FUSE_FUSE000 (0UL) +#define OTP_FUSE_FUSE001 (1UL) +#define OTP_FUSE_FUSE002 (2UL) +#define OTP_FUSE_FUSE003 (3UL) +#define OTP_FUSE_FUSE004 (4UL) +#define OTP_FUSE_FUSE005 (5UL) +#define OTP_FUSE_FUSE006 (6UL) +#define OTP_FUSE_FUSE007 (7UL) +#define OTP_FUSE_FUSE008 (8UL) +#define OTP_FUSE_FUSE009 (9UL) +#define OTP_FUSE_FUSE010 (10UL) +#define OTP_FUSE_FUSE011 (11UL) +#define OTP_FUSE_FUSE012 (12UL) +#define OTP_FUSE_FUSE013 (13UL) +#define OTP_FUSE_FUSE014 (14UL) +#define OTP_FUSE_FUSE015 (15UL) +#define OTP_FUSE_FUSE016 (16UL) +#define OTP_FUSE_FUSE017 (17UL) +#define OTP_FUSE_FUSE018 (18UL) +#define OTP_FUSE_FUSE019 (19UL) +#define OTP_FUSE_FUSE020 (20UL) +#define OTP_FUSE_FUSE021 (21UL) +#define OTP_FUSE_FUSE022 (22UL) +#define OTP_FUSE_FUSE023 (23UL) +#define OTP_FUSE_FUSE024 (24UL) +#define OTP_FUSE_FUSE025 (25UL) +#define OTP_FUSE_FUSE026 (26UL) +#define OTP_FUSE_FUSE027 (27UL) +#define OTP_FUSE_FUSE028 (28UL) +#define OTP_FUSE_FUSE029 (29UL) +#define OTP_FUSE_FUSE030 (30UL) +#define OTP_FUSE_FUSE031 (31UL) +#define OTP_FUSE_FUSE032 (32UL) +#define OTP_FUSE_FUSE033 (33UL) +#define OTP_FUSE_FUSE034 (34UL) +#define OTP_FUSE_FUSE035 (35UL) +#define OTP_FUSE_FUSE036 (36UL) +#define OTP_FUSE_FUSE037 (37UL) +#define OTP_FUSE_FUSE038 (38UL) +#define OTP_FUSE_FUSE039 (39UL) +#define OTP_FUSE_FUSE040 (40UL) +#define OTP_FUSE_FUSE041 (41UL) +#define OTP_FUSE_FUSE042 (42UL) +#define OTP_FUSE_FUSE043 (43UL) +#define OTP_FUSE_FUSE044 (44UL) +#define OTP_FUSE_FUSE045 (45UL) +#define OTP_FUSE_FUSE046 (46UL) +#define OTP_FUSE_FUSE047 (47UL) +#define OTP_FUSE_FUSE048 (48UL) +#define OTP_FUSE_FUSE049 (49UL) +#define OTP_FUSE_FUSE050 (50UL) +#define OTP_FUSE_FUSE051 (51UL) +#define OTP_FUSE_FUSE052 (52UL) +#define OTP_FUSE_FUSE053 (53UL) +#define OTP_FUSE_FUSE054 (54UL) +#define OTP_FUSE_FUSE055 (55UL) +#define OTP_FUSE_FUSE056 (56UL) +#define OTP_FUSE_FUSE057 (57UL) +#define OTP_FUSE_FUSE058 (58UL) +#define OTP_FUSE_FUSE059 (59UL) +#define OTP_FUSE_FUSE060 (60UL) +#define OTP_FUSE_FUSE061 (61UL) +#define OTP_FUSE_FUSE062 (62UL) +#define OTP_FUSE_FUSE063 (63UL) +#define OTP_FUSE_FUSE064 (64UL) +#define OTP_FUSE_FUSE065 (65UL) +#define OTP_FUSE_FUSE066 (66UL) +#define OTP_FUSE_FUSE067 (67UL) +#define OTP_FUSE_FUSE068 (68UL) +#define OTP_FUSE_FUSE069 (69UL) +#define OTP_FUSE_FUSE070 (70UL) +#define OTP_FUSE_FUSE071 (71UL) +#define OTP_FUSE_FUSE072 (72UL) +#define OTP_FUSE_FUSE073 (73UL) +#define OTP_FUSE_FUSE074 (74UL) +#define OTP_FUSE_FUSE075 (75UL) +#define OTP_FUSE_FUSE076 (76UL) +#define OTP_FUSE_FUSE077 (77UL) +#define OTP_FUSE_FUSE078 (78UL) +#define OTP_FUSE_FUSE079 (79UL) +#define OTP_FUSE_FUSE080 (80UL) +#define OTP_FUSE_FUSE081 (81UL) +#define OTP_FUSE_FUSE082 (82UL) +#define OTP_FUSE_FUSE083 (83UL) +#define OTP_FUSE_FUSE084 (84UL) +#define OTP_FUSE_FUSE085 (85UL) +#define OTP_FUSE_FUSE086 (86UL) +#define OTP_FUSE_FUSE087 (87UL) +#define OTP_FUSE_FUSE088 (88UL) +#define OTP_FUSE_FUSE089 (89UL) +#define OTP_FUSE_FUSE090 (90UL) +#define OTP_FUSE_FUSE091 (91UL) +#define OTP_FUSE_FUSE092 (92UL) +#define OTP_FUSE_FUSE093 (93UL) +#define OTP_FUSE_FUSE094 (94UL) +#define OTP_FUSE_FUSE095 (95UL) +#define OTP_FUSE_FUSE096 (96UL) +#define OTP_FUSE_FUSE097 (97UL) +#define OTP_FUSE_FUSE098 (98UL) +#define OTP_FUSE_FUSE099 (99UL) +#define OTP_FUSE_FUSE100 (100UL) +#define OTP_FUSE_FUSE101 (101UL) +#define OTP_FUSE_FUSE102 (102UL) +#define OTP_FUSE_FUSE103 (103UL) +#define OTP_FUSE_FUSE104 (104UL) +#define OTP_FUSE_FUSE105 (105UL) +#define OTP_FUSE_FUSE106 (106UL) +#define OTP_FUSE_FUSE107 (107UL) +#define OTP_FUSE_FUSE108 (108UL) +#define OTP_FUSE_FUSE109 (109UL) +#define OTP_FUSE_FUSE110 (110UL) +#define OTP_FUSE_FUSE111 (111UL) +#define OTP_FUSE_FUSE112 (112UL) +#define OTP_FUSE_FUSE113 (113UL) +#define OTP_FUSE_FUSE114 (114UL) +#define OTP_FUSE_FUSE115 (115UL) +#define OTP_FUSE_FUSE116 (116UL) +#define OTP_FUSE_FUSE117 (117UL) +#define OTP_FUSE_FUSE118 (118UL) +#define OTP_FUSE_FUSE119 (119UL) +#define OTP_FUSE_FUSE120 (120UL) +#define OTP_FUSE_FUSE121 (121UL) +#define OTP_FUSE_FUSE122 (122UL) +#define OTP_FUSE_FUSE123 (123UL) +#define OTP_FUSE_FUSE124 (124UL) +#define OTP_FUSE_FUSE125 (125UL) +#define OTP_FUSE_FUSE126 (126UL) +#define OTP_FUSE_FUSE127 (127UL) + +/* FUSE_LOCK register group index macro definition */ +#define OTP_FUSE_LOCK_LOCK00 (0UL) +#define OTP_FUSE_LOCK_LOCK01 (1UL) +#define OTP_FUSE_LOCK_LOCK02 (2UL) +#define OTP_FUSE_LOCK_LOCK03 (3UL) +#define OTP_FUSE_LOCK_LOCK04 (4UL) +#define OTP_FUSE_LOCK_LOCK05 (5UL) +#define OTP_FUSE_LOCK_LOCK06 (6UL) +#define OTP_FUSE_LOCK_LOCK07 (7UL) + +/* REGION register group index macro definition */ +#define OTP_REGION_LOAD_REGION0 (0UL) +#define OTP_REGION_LOAD_REGION1 (1UL) +#define OTP_REGION_LOAD_REGION2 (2UL) +#define OTP_REGION_LOAD_REGION3 (3UL) + + +#endif /* HPM_OTP_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h new file mode 100644 index 0000000000..c1c7b99304 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h @@ -0,0 +1,927 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PCFG_H +#define HPM_PCFG_H + +typedef struct { + __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ + __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ + __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ + __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ + __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ + __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ + __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ + __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ + __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ + __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ + __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ + __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ + __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ + __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ + __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ + __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ + __RW uint32_t DEBUG_STOP; /* 0x50: Debug stop config */ + __R uint8_t RESERVED2[12]; /* 0x54 - 0x5F: Reserved */ + __RW uint32_t RC24M; /* 0x60: RC 24M config */ + __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ + __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ + __R uint32_t STATUS; /* 0x6C: RC 24M track status */ +} PCFG_Type; + + +/* Bitfield definition for register: BANDGAP */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) +#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) +#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) +#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +/* + * LOWPOWER_MODE (RW) + * + * Banggap work in low power mode, banggap function limited + * 0: banggap works in normal mode + * 1: banggap works in low power mode + */ +#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) +#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) +#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) +#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Banggap work in power save mode, banggap function normally + * 0: banggap works in high performance mode + * 1: banggap works in power saving mode + */ +#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) +#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) +#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) +#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) + +/* + * VBG_1P0_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) +#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +/* + * VBG_P65_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +/* + * VBG_P50_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) +#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) +#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +/* Bitfield definition for register: LDO1P1 */ +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO1P1_ENABLE_MASK (0x10000UL) +#define PCFG_LDO1P1_ENABLE_SHIFT (16U) +#define PCFG_LDO1P1_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_ENABLE_SHIFT) & PCFG_LDO1P1_ENABLE_MASK) +#define PCFG_LDO1P1_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_ENABLE_MASK) >> PCFG_LDO1P1_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. + * 700: 700mV + * 720: 720mV + * . . . + * 1320:1320mV + */ +#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) +#define PCFG_LDO1P1_VOLT_SHIFT (0U) +#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) +#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) + +/* Bitfield definition for register: LDO2P5 */ +/* + * READY (RO) + * + * Ready flag, will set 1ms after enabled or voltage change + * 0: LDO is not ready for use + * 1: LDO is ready + */ +#define PCFG_LDO2P5_READY_MASK (0x10000000UL) +#define PCFG_LDO2P5_READY_SHIFT (28U) +#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) +#define PCFG_LDO2P5_ENABLE_SHIFT (16U) +#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) +#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. + * 2125: 2125mV + * 2150: 2150mV + * . . . + * 2900:2900mV + */ +#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) +#define PCFG_LDO2P5_VOLT_SHIFT (0U) +#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) +#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDC is applying new change + * 1: DCDC is ready + */ +#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDC_MODE_READY_SHIFT (28U) +#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDC work mode + * XX0: trun off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDC_MODE_MODE_SHIFT (16U) +#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) +#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) +#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RW) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) +#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) + +/* + * DISABLE_POWER_LOSS (RW) + * + * disable power loss protection + * 0: power loss protection enabled, DCDC shuts down when power loss + * 1: power loss protection disabled, DCDC try working after power voltage drop + */ +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * ouput over voltage protection + * 0: protection enabled, DCDC will shut down is output voltage is unexpected high + * 1: protection disabled, DCDC continue to adjust output voltage + */ +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A, + * 1: 1.3A + */ +#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDC_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDC current level, current level is num * 50mA + */ +#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDC_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) +#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) +#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_AUTOLP (RW) + * + * enable auto enter low power mode + * 0: do not enter low power mode + * 1: enter low power mode if current is detected low + */ +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDC_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDC_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) +#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) +#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) +#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) +#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) +#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) +#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) +#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) +#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDC internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) +#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) +#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDC_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDC voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) +#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + */ +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: POWER_TRAP */ +/* + * TRIGGERED (RW) + * + * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. + * 0: low power trap is not triggered + * 1: low power trap triggered + */ +#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) +#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) +#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) +#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) + +/* + * RETENTION (RW) + * + * DCDC enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDC + * 1: reduce DCDC voltage + */ +#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) +#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) +#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) +#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) + +/* + * TRAP (RW) + * + * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered + * 0: trap not enabled, pmic side low power function disabled + * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + */ +#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) +#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) +#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) +#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) + +/* Bitfield definition for register: WAKE_CAUSE */ +/* + * CAUSE (RW) + * + * wake up cause, each bit represents one wake up source, write 1 to clear the register bit + * 0: wake up source is not active during last wakeup + * 1: wake up source is active furing last wakeup + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) +#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) +#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: WAKE_MASK */ +/* + * MASK (RW) + * + * mask for wake up sources, each bit represents one wakeup source + * 0: allow source to wake up system + * 1: disallow source to wakeup system + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_MASK_MASK_SHIFT (0U) +#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) +#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) + +/* Bitfield definition for register: SCG_CTRL */ +/* + * SCG (RW) + * + * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral + * 00,01: clock gated according to low power flow + * 10: clock is always off + * 11: clock is always on + * bit0-1: fuse + * bit2-3: sram + * bit4-5: vad + * bit6-7:gpio + * bit8-9:ioc + * bit10-11: timer + * bit12-13:wdog + * bit14-15:uart + * bit16-17:debug + */ +#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) +#define PCFG_SCG_CTRL_SCG_SHIFT (0U) +#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) +#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) + +/* Bitfield definition for register: DEBUG_STOP */ +/* + * CPU1 (RW) + * + * Stop peripheral when CPU1 enter debug mode + * 0: peripheral keep running when CPU1 in debug mode + * 1: peripheral enter debug mode when CPU1 enter debug + */ +#define PCFG_DEBUG_STOP_CPU1_MASK (0x2U) +#define PCFG_DEBUG_STOP_CPU1_SHIFT (1U) +#define PCFG_DEBUG_STOP_CPU1_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU1_SHIFT) & PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_CPU1_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU1_MASK) >> PCFG_DEBUG_STOP_CPU1_SHIFT) + +/* + * CPU0 (RW) + * + * Stop peripheral when CPU0 enter debug mode + * 0: peripheral keep running when CPU0 in debug mode + * 1: peripheral enter debug mode when CPU0 enter debug + */ +#define PCFG_DEBUG_STOP_CPU0_MASK (0x1U) +#define PCFG_DEBUG_STOP_CPU0_SHIFT (0U) +#define PCFG_DEBUG_STOP_CPU0_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU0_SHIFT) & PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_CPU0_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU0_MASK) >> PCFG_DEBUG_STOP_CPU0_SHIFT) + +/* Bitfield definition for register: RC24M */ +/* + * RC_TRIMMED (RW) + * + * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: RC is not trimmed + * 1: RC is trimmed + */ +#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) +#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) +#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) +#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) + +/* + * TRIM_C (RW) + * + * Coarse trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_C_MASK (0x700U) +#define PCFG_RC24M_TRIM_C_SHIFT (8U) +#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) +#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) + +/* + * TRIM_F (RW) + * + * Fine trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_F_MASK (0x1FU) +#define PCFG_RC24M_TRIM_F_SHIFT (0U) +#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) +#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) + +/* Bitfield definition for register: RC24M_TRACK */ +/* + * SEL24M (RW) + * + * Select track reference + * 0: select 32K as reference + * 1: select 24M XTAL as reference + */ +#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) +#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) +#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) +#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) + +/* + * RETURN (RW) + * + * Retrun default value when XTAL loss + * 0: remain last tracking value + * 1: switch to default value + */ +#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) +#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) +#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) +#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) + +/* + * TRACK (RW) + * + * track mode + * 0: RC24M free running + * 1: track RC24M to external XTAL + */ +#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) +#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) +#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) +#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) + +/* Bitfield definition for register: TRACK_TARGET */ +/* + * PRE_DIV (RW) + * + * Divider for reference source + */ +#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) +#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) +#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) +#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) + +/* + * TARGET (RW) + * + * Target frequency multiplier of divided source + */ +#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) +#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) +#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) +#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * SEL32K (RO) + * + * track is using XTAL32K + * 0: track is not using XTAL32K + * 1: track is using XTAL32K + */ +#define PCFG_STATUS_SEL32K_MASK (0x100000UL) +#define PCFG_STATUS_SEL32K_SHIFT (20U) +#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) + +/* + * SEL24M (RO) + * + * track is using XTAL24M + * 0: track is not using XTAL24M + * 1: track is using XTAL24M + */ +#define PCFG_STATUS_SEL24M_MASK (0x10000UL) +#define PCFG_STATUS_SEL24M_SHIFT (16U) +#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) + +/* + * EN_TRIM (RO) + * + * default value takes effect + * 0: default value is invalid + * 1: default value is valid + */ +#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) +#define PCFG_STATUS_EN_TRIM_SHIFT (15U) +#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) + +/* + * TRIM_C (RO) + * + * default coarse trim value + */ +#define PCFG_STATUS_TRIM_C_MASK (0x700U) +#define PCFG_STATUS_TRIM_C_SHIFT (8U) +#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) + +/* + * TRIM_F (RO) + * + * default fine trim value + */ +#define PCFG_STATUS_TRIM_F_MASK (0x1FU) +#define PCFG_STATUS_TRIM_F_SHIFT (0U) +#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) + + + + +#endif /* HPM_PCFG_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h new file mode 100644 index 0000000000..015a8c1d3e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h @@ -0,0 +1,492 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PDM_H +#define HPM_PDM_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: Control Register */ + __RW uint32_t CH_CTRL; /* 0x4: Channel Control Register */ + __W uint32_t ST; /* 0x8: Status Register */ + __RW uint32_t CH_CFG; /* 0xC: Channel Configuration Register */ + __RW uint32_t CIC_CFG; /* 0x10: CIC configuration register */ + __RW uint32_t CTRL_INBUF; /* 0x14: In Buf Control Register */ + __RW uint32_t CTRL_FILT0; /* 0x18: Filter 0 Control Register */ + __RW uint32_t CTRL_FILT1; /* 0x1C: Filter 1 Control Register */ + __RW uint32_t RUN; /* 0x20: Run Register */ + __RW uint32_t MEMADDR; /* 0x24: Memory Access Address */ + __RW uint32_t MEMDATA; /* 0x28: Memory Access Data */ + __RW uint32_t HPF_MA; /* 0x2C: HPF A Coef Register */ + __RW uint32_t HPF_B; /* 0x30: HPF B Coef Register */ +} PDM_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SFTRST (RW) + * + * software reset the module. Self-clear. + */ +#define PDM_CTRL_SFTRST_MASK (0x80000000UL) +#define PDM_CTRL_SFTRST_SHIFT (31U) +#define PDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << PDM_CTRL_SFTRST_SHIFT) & PDM_CTRL_SFTRST_MASK) +#define PDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & PDM_CTRL_SFTRST_MASK) >> PDM_CTRL_SFTRST_SHIFT) + +/* + * SOF_FEDGE (RW) + * + * asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. + */ +#define PDM_CTRL_SOF_FEDGE_MASK (0x800000UL) +#define PDM_CTRL_SOF_FEDGE_SHIFT (23U) +#define PDM_CTRL_SOF_FEDGE_SET(x) (((uint32_t)(x) << PDM_CTRL_SOF_FEDGE_SHIFT) & PDM_CTRL_SOF_FEDGE_MASK) +#define PDM_CTRL_SOF_FEDGE_GET(x) (((uint32_t)(x) & PDM_CTRL_SOF_FEDGE_MASK) >> PDM_CTRL_SOF_FEDGE_SHIFT) + +/* + * USE_COEF_RAM (RW) + * + * Asserted to use Coef RAM instead of Coef ROM + */ +#define PDM_CTRL_USE_COEF_RAM_MASK (0x100000UL) +#define PDM_CTRL_USE_COEF_RAM_SHIFT (20U) +#define PDM_CTRL_USE_COEF_RAM_SET(x) (((uint32_t)(x) << PDM_CTRL_USE_COEF_RAM_SHIFT) & PDM_CTRL_USE_COEF_RAM_MASK) +#define PDM_CTRL_USE_COEF_RAM_GET(x) (((uint32_t)(x) & PDM_CTRL_USE_COEF_RAM_MASK) >> PDM_CTRL_USE_COEF_RAM_SHIFT) + +/* + * FILT_CRX_ERR_IE (RW) + * + * data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. + */ +#define PDM_CTRL_FILT_CRX_ERR_IE_MASK (0x80000UL) +#define PDM_CTRL_FILT_CRX_ERR_IE_SHIFT (19U) +#define PDM_CTRL_FILT_CRX_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) +#define PDM_CTRL_FILT_CRX_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) >> PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) + +/* + * OFIFO_OVFL_ERR_IE (RW) + * + * output fifo overflow error interrupt enable + */ +#define PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x40000UL) +#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (18U) +#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) +#define PDM_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) + +/* + * CIC_OVLD_ERR_IE (RW) + * + * CIC overload error interrupt enable + */ +#define PDM_CTRL_CIC_OVLD_ERR_IE_MASK (0x20000UL) +#define PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT (17U) +#define PDM_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) +#define PDM_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) >> PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) + +/* + * CIC_SAT_ERR_IE (RW) + * + * Error interrupt enable + * This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. + * 0: Error interrupt is masked + * 1: Error interrupt is enabled + */ +#define PDM_CTRL_CIC_SAT_ERR_IE_MASK (0x10000UL) +#define PDM_CTRL_CIC_SAT_ERR_IE_SHIFT (16U) +#define PDM_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) +#define PDM_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) >> PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) + +/* + * DEC_AFT_CIC (RW) + * + * decimation rate after CIC. Now it is forced to be 3. + */ +#define PDM_CTRL_DEC_AFT_CIC_MASK (0xF000U) +#define PDM_CTRL_DEC_AFT_CIC_SHIFT (12U) +#define PDM_CTRL_DEC_AFT_CIC_SET(x) (((uint32_t)(x) << PDM_CTRL_DEC_AFT_CIC_SHIFT) & PDM_CTRL_DEC_AFT_CIC_MASK) +#define PDM_CTRL_DEC_AFT_CIC_GET(x) (((uint32_t)(x) & PDM_CTRL_DEC_AFT_CIC_MASK) >> PDM_CTRL_DEC_AFT_CIC_SHIFT) + +/* + * CAPT_DLY (RW) + * + * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + */ +#define PDM_CTRL_CAPT_DLY_MASK (0x780U) +#define PDM_CTRL_CAPT_DLY_SHIFT (7U) +#define PDM_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << PDM_CTRL_CAPT_DLY_SHIFT) & PDM_CTRL_CAPT_DLY_MASK) +#define PDM_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & PDM_CTRL_CAPT_DLY_MASK) >> PDM_CTRL_CAPT_DLY_SHIFT) + +/* + * PDM_CLK_HFDIV (RW) + * + * The clock divider will work at least 4. + * 0: div-by-2, + * 1: div-by-4 + * . . . + * n: div-by-2*(n+1) + */ +#define PDM_CTRL_PDM_CLK_HFDIV_MASK (0x78U) +#define PDM_CTRL_PDM_CLK_HFDIV_SHIFT (3U) +#define PDM_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_HFDIV_SHIFT) & PDM_CTRL_PDM_CLK_HFDIV_MASK) +#define PDM_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_HFDIV_MASK) >> PDM_CTRL_PDM_CLK_HFDIV_SHIFT) + +/* + * PDM_CLK_DIV_BYPASS (RW) + * + * asserted to bypass the pdm clock divider + */ +#define PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x4U) +#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (2U) +#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) +#define PDM_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) + +/* + * PDM_CLK_OE (RW) + * + * pdm_clk_output_en + */ +#define PDM_CTRL_PDM_CLK_OE_MASK (0x2U) +#define PDM_CTRL_PDM_CLK_OE_SHIFT (1U) +#define PDM_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_OE_SHIFT) & PDM_CTRL_PDM_CLK_OE_MASK) +#define PDM_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_OE_MASK) >> PDM_CTRL_PDM_CLK_OE_SHIFT) + +/* + * HPF_EN (RW) + * + * pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. + */ +#define PDM_CTRL_HPF_EN_MASK (0x1U) +#define PDM_CTRL_HPF_EN_SHIFT (0U) +#define PDM_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << PDM_CTRL_HPF_EN_SHIFT) & PDM_CTRL_HPF_EN_MASK) +#define PDM_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & PDM_CTRL_HPF_EN_MASK) >> PDM_CTRL_HPF_EN_SHIFT) + +/* Bitfield definition for register: CH_CTRL */ +/* + * CH_POL (RW) + * + * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + */ +#define PDM_CH_CTRL_CH_POL_MASK (0xFF0000UL) +#define PDM_CH_CTRL_CH_POL_SHIFT (16U) +#define PDM_CH_CTRL_CH_POL_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_POL_SHIFT) & PDM_CH_CTRL_CH_POL_MASK) +#define PDM_CH_CTRL_CH_POL_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_POL_MASK) >> PDM_CH_CTRL_CH_POL_SHIFT) + +/* + * CH_EN (RW) + * + * Asserted to enable the channel. + * Ch8 & 9 are refs. + * Ch0-7 are pdm mics. + */ +#define PDM_CH_CTRL_CH_EN_MASK (0x3FFU) +#define PDM_CH_CTRL_CH_EN_SHIFT (0U) +#define PDM_CH_CTRL_CH_EN_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_EN_SHIFT) & PDM_CH_CTRL_CH_EN_MASK) +#define PDM_CH_CTRL_CH_EN_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_EN_MASK) >> PDM_CH_CTRL_CH_EN_SHIFT) + +/* Bitfield definition for register: ST */ +/* + * FILT_CRX_ERR (W1C) + * + * data accessed out of boundary error + */ +#define PDM_ST_FILT_CRX_ERR_MASK (0x8U) +#define PDM_ST_FILT_CRX_ERR_SHIFT (3U) +#define PDM_ST_FILT_CRX_ERR_SET(x) (((uint32_t)(x) << PDM_ST_FILT_CRX_ERR_SHIFT) & PDM_ST_FILT_CRX_ERR_MASK) +#define PDM_ST_FILT_CRX_ERR_GET(x) (((uint32_t)(x) & PDM_ST_FILT_CRX_ERR_MASK) >> PDM_ST_FILT_CRX_ERR_SHIFT) + +/* + * OFIFO_OVFL_ERR (W1C) + * + * output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. + */ +#define PDM_ST_OFIFO_OVFL_ERR_MASK (0x4U) +#define PDM_ST_OFIFO_OVFL_ERR_SHIFT (2U) +#define PDM_ST_OFIFO_OVFL_ERR_SET(x) (((uint32_t)(x) << PDM_ST_OFIFO_OVFL_ERR_SHIFT) & PDM_ST_OFIFO_OVFL_ERR_MASK) +#define PDM_ST_OFIFO_OVFL_ERR_GET(x) (((uint32_t)(x) & PDM_ST_OFIFO_OVFL_ERR_MASK) >> PDM_ST_OFIFO_OVFL_ERR_SHIFT) + +/* + * CIC_OVLD_ERR (W1C) + * + * CIC overload error. write 1 clear + */ +#define PDM_ST_CIC_OVLD_ERR_MASK (0x2U) +#define PDM_ST_CIC_OVLD_ERR_SHIFT (1U) +#define PDM_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_OVLD_ERR_SHIFT) & PDM_ST_CIC_OVLD_ERR_MASK) +#define PDM_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_OVLD_ERR_MASK) >> PDM_ST_CIC_OVLD_ERR_SHIFT) + +/* + * CIC_SAT_ERR (W1C) + * + * CIC saturation. Write 1 clear + */ +#define PDM_ST_CIC_SAT_ERR_MASK (0x1U) +#define PDM_ST_CIC_SAT_ERR_SHIFT (0U) +#define PDM_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_SAT_ERR_SHIFT) & PDM_ST_CIC_SAT_ERR_MASK) +#define PDM_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_SAT_ERR_MASK) >> PDM_ST_CIC_SAT_ERR_SHIFT) + +/* Bitfield definition for register: CH_CFG */ +/* + * CH9_TYPE (RW) + * + */ +#define PDM_CH_CFG_CH9_TYPE_MASK (0xC0000UL) +#define PDM_CH_CFG_CH9_TYPE_SHIFT (18U) +#define PDM_CH_CFG_CH9_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH9_TYPE_SHIFT) & PDM_CH_CFG_CH9_TYPE_MASK) +#define PDM_CH_CFG_CH9_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH9_TYPE_MASK) >> PDM_CH_CFG_CH9_TYPE_SHIFT) + +/* + * CH8_TYPE (RW) + * + */ +#define PDM_CH_CFG_CH8_TYPE_MASK (0x30000UL) +#define PDM_CH_CFG_CH8_TYPE_SHIFT (16U) +#define PDM_CH_CFG_CH8_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH8_TYPE_SHIFT) & PDM_CH_CFG_CH8_TYPE_MASK) +#define PDM_CH_CFG_CH8_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH8_TYPE_MASK) >> PDM_CH_CFG_CH8_TYPE_SHIFT) + +/* + * CH7_TYPE (RW) + * + */ +#define PDM_CH_CFG_CH7_TYPE_MASK (0xC000U) +#define PDM_CH_CFG_CH7_TYPE_SHIFT (14U) +#define PDM_CH_CFG_CH7_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH7_TYPE_SHIFT) & PDM_CH_CFG_CH7_TYPE_MASK) +#define PDM_CH_CFG_CH7_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH7_TYPE_MASK) >> PDM_CH_CFG_CH7_TYPE_SHIFT) + +/* + * CH6_TYPE (RW) + * + */ +#define PDM_CH_CFG_CH6_TYPE_MASK (0x3000U) +#define PDM_CH_CFG_CH6_TYPE_SHIFT (12U) +#define PDM_CH_CFG_CH6_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH6_TYPE_SHIFT) & PDM_CH_CFG_CH6_TYPE_MASK) +#define PDM_CH_CFG_CH6_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH6_TYPE_MASK) >> PDM_CH_CFG_CH6_TYPE_SHIFT) + +/* + * CH5_TYPE (RW) + * + */ +#define PDM_CH_CFG_CH5_TYPE_MASK (0xC00U) +#define PDM_CH_CFG_CH5_TYPE_SHIFT (10U) +#define PDM_CH_CFG_CH5_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH5_TYPE_SHIFT) & PDM_CH_CFG_CH5_TYPE_MASK) +#define PDM_CH_CFG_CH5_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH5_TYPE_MASK) >> PDM_CH_CFG_CH5_TYPE_SHIFT) + +/* + * CH4_TYPE (RW) + * + */ +#define PDM_CH_CFG_CH4_TYPE_MASK (0x300U) +#define PDM_CH_CFG_CH4_TYPE_SHIFT (8U) +#define PDM_CH_CFG_CH4_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH4_TYPE_SHIFT) & PDM_CH_CFG_CH4_TYPE_MASK) +#define PDM_CH_CFG_CH4_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH4_TYPE_MASK) >> PDM_CH_CFG_CH4_TYPE_SHIFT) + +/* + * CH3_TYPE (RW) + * + */ +#define PDM_CH_CFG_CH3_TYPE_MASK (0xC0U) +#define PDM_CH_CFG_CH3_TYPE_SHIFT (6U) +#define PDM_CH_CFG_CH3_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH3_TYPE_SHIFT) & PDM_CH_CFG_CH3_TYPE_MASK) +#define PDM_CH_CFG_CH3_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH3_TYPE_MASK) >> PDM_CH_CFG_CH3_TYPE_SHIFT) + +/* + * CH2_TYPE (RW) + * + */ +#define PDM_CH_CFG_CH2_TYPE_MASK (0x30U) +#define PDM_CH_CFG_CH2_TYPE_SHIFT (4U) +#define PDM_CH_CFG_CH2_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH2_TYPE_SHIFT) & PDM_CH_CFG_CH2_TYPE_MASK) +#define PDM_CH_CFG_CH2_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH2_TYPE_MASK) >> PDM_CH_CFG_CH2_TYPE_SHIFT) + +/* + * CH1_TYPE (RW) + * + */ +#define PDM_CH_CFG_CH1_TYPE_MASK (0xCU) +#define PDM_CH_CFG_CH1_TYPE_SHIFT (2U) +#define PDM_CH_CFG_CH1_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH1_TYPE_SHIFT) & PDM_CH_CFG_CH1_TYPE_MASK) +#define PDM_CH_CFG_CH1_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH1_TYPE_MASK) >> PDM_CH_CFG_CH1_TYPE_SHIFT) + +/* + * CH0_TYPE (RW) + * + * Type of Channel 0 + * 2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) + * 2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) + */ +#define PDM_CH_CFG_CH0_TYPE_MASK (0x3U) +#define PDM_CH_CFG_CH0_TYPE_SHIFT (0U) +#define PDM_CH_CFG_CH0_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH0_TYPE_SHIFT) & PDM_CH_CFG_CH0_TYPE_MASK) +#define PDM_CH_CFG_CH0_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH0_TYPE_MASK) >> PDM_CH_CFG_CH0_TYPE_SHIFT) + +/* Bitfield definition for register: CIC_CFG */ +/* + * POST_SCALE (RW) + * + * the shift value after CIC results. + */ +#define PDM_CIC_CFG_POST_SCALE_MASK (0xFC00U) +#define PDM_CIC_CFG_POST_SCALE_SHIFT (10U) +#define PDM_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_POST_SCALE_SHIFT) & PDM_CIC_CFG_POST_SCALE_MASK) +#define PDM_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_POST_SCALE_MASK) >> PDM_CIC_CFG_POST_SCALE_SHIFT) + +/* + * SGD (RW) + * + * Sigma_delta_order[1:0] + * 2'b00: 7 + * 2'b01: 6 + * 2'b10: 5 + * Others: unused + */ +#define PDM_CIC_CFG_SGD_MASK (0x300U) +#define PDM_CIC_CFG_SGD_SHIFT (8U) +#define PDM_CIC_CFG_SGD_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_SGD_SHIFT) & PDM_CIC_CFG_SGD_MASK) +#define PDM_CIC_CFG_SGD_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_SGD_MASK) >> PDM_CIC_CFG_SGD_SHIFT) + +/* + * CIC_DEC_RATIO (RW) + * + * CIC decimation factor + */ +#define PDM_CIC_CFG_CIC_DEC_RATIO_MASK (0xFFU) +#define PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT (0U) +#define PDM_CIC_CFG_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) +#define PDM_CIC_CFG_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) >> PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) + +/* Bitfield definition for register: CTRL_INBUF */ +/* + * MAX_PTR (RW) + * + * The buf size-1 for each channel + */ +#define PDM_CTRL_INBUF_MAX_PTR_MASK (0x3FC00000UL) +#define PDM_CTRL_INBUF_MAX_PTR_SHIFT (22U) +#define PDM_CTRL_INBUF_MAX_PTR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_MAX_PTR_SHIFT) & PDM_CTRL_INBUF_MAX_PTR_MASK) +#define PDM_CTRL_INBUF_MAX_PTR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_MAX_PTR_MASK) >> PDM_CTRL_INBUF_MAX_PTR_SHIFT) + +/* + * PITCH (RW) + * + * The spacing between starting address of adjacent channels + */ +#define PDM_CTRL_INBUF_PITCH_MASK (0x3FF800UL) +#define PDM_CTRL_INBUF_PITCH_SHIFT (11U) +#define PDM_CTRL_INBUF_PITCH_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_PITCH_SHIFT) & PDM_CTRL_INBUF_PITCH_MASK) +#define PDM_CTRL_INBUF_PITCH_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_PITCH_MASK) >> PDM_CTRL_INBUF_PITCH_SHIFT) + +/* + * START_ADDR (RW) + * + * The starting address of channel 0 in filter data buffer + */ +#define PDM_CTRL_INBUF_START_ADDR_MASK (0x7FFU) +#define PDM_CTRL_INBUF_START_ADDR_SHIFT (0U) +#define PDM_CTRL_INBUF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_START_ADDR_SHIFT) & PDM_CTRL_INBUF_START_ADDR_MASK) +#define PDM_CTRL_INBUF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_START_ADDR_MASK) >> PDM_CTRL_INBUF_START_ADDR_SHIFT) + +/* Bitfield definition for register: CTRL_FILT0 */ +/* + * COEF_LEN_M0 (RW) + * + * Coef length of filter type 2'b00 in coef memory + */ +#define PDM_CTRL_FILT0_COEF_LEN_M0_MASK (0xFF00U) +#define PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT (8U) +#define PDM_CTRL_FILT0_COEF_LEN_M0_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) +#define PDM_CTRL_FILT0_COEF_LEN_M0_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) >> PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) + +/* + * COEF_START_ADDR (RW) + * + * Starting address of Coef of filter type 2'b00 in coef memory + */ +#define PDM_CTRL_FILT0_COEF_START_ADDR_MASK (0xFFU) +#define PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT (0U) +#define PDM_CTRL_FILT0_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) +#define PDM_CTRL_FILT0_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) + +/* Bitfield definition for register: CTRL_FILT1 */ +/* + * COEF_LEN_M1 (RW) + * + * Coef length of filter type 2'b01 in coef memory + */ +#define PDM_CTRL_FILT1_COEF_LEN_M1_MASK (0xFF00U) +#define PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT (8U) +#define PDM_CTRL_FILT1_COEF_LEN_M1_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) +#define PDM_CTRL_FILT1_COEF_LEN_M1_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) >> PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) + +/* + * COEF_START_ADDR (RW) + * + * Starting address of Coef of filter type 2'b01 in coef memory + */ +#define PDM_CTRL_FILT1_COEF_START_ADDR_MASK (0xFFU) +#define PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT (0U) +#define PDM_CTRL_FILT1_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) +#define PDM_CTRL_FILT1_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) + +/* Bitfield definition for register: RUN */ +/* + * PDM_EN (RW) + * + * Asserted to enable the module + */ +#define PDM_RUN_PDM_EN_MASK (0x1U) +#define PDM_RUN_PDM_EN_SHIFT (0U) +#define PDM_RUN_PDM_EN_SET(x) (((uint32_t)(x) << PDM_RUN_PDM_EN_SHIFT) & PDM_RUN_PDM_EN_MASK) +#define PDM_RUN_PDM_EN_GET(x) (((uint32_t)(x) & PDM_RUN_PDM_EN_MASK) >> PDM_RUN_PDM_EN_SHIFT) + +/* Bitfield definition for register: MEMADDR */ +/* + * ADDR (RW) + * + * 0--0x0FFFFFFF: COEF_RAM + * 0x10000000--0x1FFFFFFF: DATA_RAM + */ +#define PDM_MEMADDR_ADDR_MASK (0xFFFFFFFFUL) +#define PDM_MEMADDR_ADDR_SHIFT (0U) +#define PDM_MEMADDR_ADDR_SET(x) (((uint32_t)(x) << PDM_MEMADDR_ADDR_SHIFT) & PDM_MEMADDR_ADDR_MASK) +#define PDM_MEMADDR_ADDR_GET(x) (((uint32_t)(x) & PDM_MEMADDR_ADDR_MASK) >> PDM_MEMADDR_ADDR_SHIFT) + +/* Bitfield definition for register: MEMDATA */ +/* + * DATA (RW) + * + * The data write-to/read-from buffer + */ +#define PDM_MEMDATA_DATA_MASK (0xFFFFFFFFUL) +#define PDM_MEMDATA_DATA_SHIFT (0U) +#define PDM_MEMDATA_DATA_SET(x) (((uint32_t)(x) << PDM_MEMDATA_DATA_SHIFT) & PDM_MEMDATA_DATA_MASK) +#define PDM_MEMDATA_DATA_GET(x) (((uint32_t)(x) & PDM_MEMDATA_DATA_MASK) >> PDM_MEMDATA_DATA_SHIFT) + +/* Bitfield definition for register: HPF_MA */ +/* + * COEF (RW) + * + * Composite value of coef A of the Order-1 HPF + */ +#define PDM_HPF_MA_COEF_MASK (0xFFFFFFFFUL) +#define PDM_HPF_MA_COEF_SHIFT (0U) +#define PDM_HPF_MA_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_MA_COEF_SHIFT) & PDM_HPF_MA_COEF_MASK) +#define PDM_HPF_MA_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_MA_COEF_MASK) >> PDM_HPF_MA_COEF_SHIFT) + +/* Bitfield definition for register: HPF_B */ +/* + * COEF (RW) + * + * coef B of the Order-1 HPF + */ +#define PDM_HPF_B_COEF_MASK (0xFFFFFFFFUL) +#define PDM_HPF_B_COEF_SHIFT (0U) +#define PDM_HPF_B_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_B_COEF_SHIFT) & PDM_HPF_B_COEF_MASK) +#define PDM_HPF_B_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_B_COEF_MASK) >> PDM_HPF_B_COEF_SHIFT) + + + + +#endif /* HPM_PDM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h new file mode 100644 index 0000000000..aca242a62a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h @@ -0,0 +1,912 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PDMA_H +#define HPM_PDMA_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: Control Register */ + __RW uint32_t STAT; /* 0x4: Status Register */ + __RW uint32_t OUT_CTRL; /* 0x8: Out Layer Control Register */ + __RW uint32_t OUT_BUF; /* 0xC: Output buffer address */ + __R uint8_t RESERVED0[4]; /* 0x10 - 0x13: Reserved */ + __RW uint32_t OUT_PITCH; /* 0x14: Outlayer Pitch Register */ + __RW uint32_t OUT_LRC; /* 0x18: Output Lower Right Corner Register */ + struct { + __RW uint32_t ULC; /* 0x1C: Layer Upper Left Corner Register */ + __RW uint32_t LRC; /* 0x20: Layer Lower Right Corner Register */ + } OUT_PS[2]; + __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ + struct { + __RW uint32_t CTRL; /* 0x30: Layer Control Register */ + __RW uint32_t BUF; /* 0x34: Layer data buffer address */ + __R uint8_t RESERVED0[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t PITCH; /* 0x40: Layer data pitch register */ + __RW uint32_t BKGD; /* 0x44: Layer background color register */ + __RW uint32_t SCALE; /* 0x48: Layer scale register */ + __RW uint32_t OFFSET; /* 0x4C: Layer offset register */ + __RW uint32_t CLRKEY_LOW; /* 0x50: Layer low color key register */ + __RW uint32_t CLRKEY_HIGH; /* 0x54: Layer high color key register */ + __RW uint32_t ORG; /* 0x58: Layer original size register */ + __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */ + } PS[2]; + __R uint8_t RESERVED2[16]; /* 0x90 - 0x9F: Reserved */ + __RW uint32_t YUV2RGB_COEF0; /* 0xA0: YUV2RGB coefficients register 0 */ + __RW uint32_t YUV2RGB_COEF1; /* 0xA4: YUV2RGB coefficients register 1 */ + __RW uint32_t YUV2RGB_COEF2; /* 0xA8: YUV2RGB coefficients register 2 */ + __RW uint32_t RGB2YUV_COEF0; /* 0xAC: RGB2YUV coefficients register 0 */ + __RW uint32_t RGB2YUV_COEF1; /* 0xB0: RGB2YUV coefficients register 1 */ + __RW uint32_t RGB2YUV_COEF2; /* 0xB4: RGB2YUV coefficients register 2 */ + __RW uint32_t RGB2YUV_COEF3; /* 0xB8: RGB2YUV coefficients register 3 */ + __RW uint32_t RGB2YUV_COEF4; /* 0xBC: RGB2YUV coefficients register 4 */ +} PDMA_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * ARQOS (RW) + * + * QoS for AXI read bus + */ +#define PDMA_CTRL_ARQOS_MASK (0x780000UL) +#define PDMA_CTRL_ARQOS_SHIFT (19U) +#define PDMA_CTRL_ARQOS_SET(x) (((uint32_t)(x) << PDMA_CTRL_ARQOS_SHIFT) & PDMA_CTRL_ARQOS_MASK) +#define PDMA_CTRL_ARQOS_GET(x) (((uint32_t)(x) & PDMA_CTRL_ARQOS_MASK) >> PDMA_CTRL_ARQOS_SHIFT) + +/* + * AWQOS (RW) + * + * QoS for AXI write bus + */ +#define PDMA_CTRL_AWQOS_MASK (0x78000UL) +#define PDMA_CTRL_AWQOS_SHIFT (15U) +#define PDMA_CTRL_AWQOS_SET(x) (((uint32_t)(x) << PDMA_CTRL_AWQOS_SHIFT) & PDMA_CTRL_AWQOS_MASK) +#define PDMA_CTRL_AWQOS_GET(x) (((uint32_t)(x) & PDMA_CTRL_AWQOS_MASK) >> PDMA_CTRL_AWQOS_SHIFT) + +/* + * PACK_DIR (RW) + * + * Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. + * 2'b00: no change {A3, A2, A1, A0} + * 2'b01: {A2, A3, A0, A1} + * 2'b10: {A1, A0, A3, A2} + * 2'b11: {A0, A1, A2, A3} + */ +#define PDMA_CTRL_PACK_DIR_MASK (0x6000U) +#define PDMA_CTRL_PACK_DIR_SHIFT (13U) +#define PDMA_CTRL_PACK_DIR_SET(x) (((uint32_t)(x) << PDMA_CTRL_PACK_DIR_SHIFT) & PDMA_CTRL_PACK_DIR_MASK) +#define PDMA_CTRL_PACK_DIR_GET(x) (((uint32_t)(x) & PDMA_CTRL_PACK_DIR_MASK) >> PDMA_CTRL_PACK_DIR_SHIFT) + +/* + * AXIERR_IRQ_EN (RW) + * + * Enable interrupt of AXI bus error + */ +#define PDMA_CTRL_AXIERR_IRQ_EN_MASK (0x1000U) +#define PDMA_CTRL_AXIERR_IRQ_EN_SHIFT (12U) +#define PDMA_CTRL_AXIERR_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_AXIERR_IRQ_EN_SHIFT) & PDMA_CTRL_AXIERR_IRQ_EN_MASK) +#define PDMA_CTRL_AXIERR_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_AXIERR_IRQ_EN_MASK) >> PDMA_CTRL_AXIERR_IRQ_EN_SHIFT) + +/* + * PDMA_DONE_IRQ_EN (RW) + * + * Enable interrupt of PDMA_DONE + */ +#define PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK (0x800U) +#define PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT (11U) +#define PDMA_CTRL_PDMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT) & PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK) +#define PDMA_CTRL_PDMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK) >> PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT) + +/* + * CLKGATE (RW) + * + * Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. + */ +#define PDMA_CTRL_CLKGATE_MASK (0x200U) +#define PDMA_CTRL_CLKGATE_SHIFT (9U) +#define PDMA_CTRL_CLKGATE_SET(x) (((uint32_t)(x) << PDMA_CTRL_CLKGATE_SHIFT) & PDMA_CTRL_CLKGATE_MASK) +#define PDMA_CTRL_CLKGATE_GET(x) (((uint32_t)(x) & PDMA_CTRL_CLKGATE_MASK) >> PDMA_CTRL_CLKGATE_SHIFT) + +/* + * IRQ_EN (RW) + * + * Enable normal interrupt + */ +#define PDMA_CTRL_IRQ_EN_MASK (0x40U) +#define PDMA_CTRL_IRQ_EN_SHIFT (6U) +#define PDMA_CTRL_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_IRQ_EN_SHIFT) & PDMA_CTRL_IRQ_EN_MASK) +#define PDMA_CTRL_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_IRQ_EN_MASK) >> PDMA_CTRL_IRQ_EN_SHIFT) + +/* + * BS16 (RW) + * + * Asserted when the Block Size is 16x16, else 8x8 + */ +#define PDMA_CTRL_BS16_MASK (0x20U) +#define PDMA_CTRL_BS16_SHIFT (5U) +#define PDMA_CTRL_BS16_SET(x) (((uint32_t)(x) << PDMA_CTRL_BS16_SHIFT) & PDMA_CTRL_BS16_MASK) +#define PDMA_CTRL_BS16_GET(x) (((uint32_t)(x) & PDMA_CTRL_BS16_MASK) >> PDMA_CTRL_BS16_SHIFT) + +/* + * P1_EN (RW) + * + * Plane 1 Enable + */ +#define PDMA_CTRL_P1_EN_MASK (0x10U) +#define PDMA_CTRL_P1_EN_SHIFT (4U) +#define PDMA_CTRL_P1_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_P1_EN_SHIFT) & PDMA_CTRL_P1_EN_MASK) +#define PDMA_CTRL_P1_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_P1_EN_MASK) >> PDMA_CTRL_P1_EN_SHIFT) + +/* + * P0_EN (RW) + * + * Plane 0 Enable + */ +#define PDMA_CTRL_P0_EN_MASK (0x8U) +#define PDMA_CTRL_P0_EN_SHIFT (3U) +#define PDMA_CTRL_P0_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_P0_EN_SHIFT) & PDMA_CTRL_P0_EN_MASK) +#define PDMA_CTRL_P0_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_P0_EN_MASK) >> PDMA_CTRL_P0_EN_SHIFT) + +/* + * PDMA_SFTRST (RW) + * + * Software Reset. + * Write 1 to clear PDMA internal logic. + * Write 0 to exit software reset mode. + */ +#define PDMA_CTRL_PDMA_SFTRST_MASK (0x2U) +#define PDMA_CTRL_PDMA_SFTRST_SHIFT (1U) +#define PDMA_CTRL_PDMA_SFTRST_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_SFTRST_SHIFT) & PDMA_CTRL_PDMA_SFTRST_MASK) +#define PDMA_CTRL_PDMA_SFTRST_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_SFTRST_MASK) >> PDMA_CTRL_PDMA_SFTRST_SHIFT) + +/* + * PDMA_EN (RW) + * + * 1b - Enabled + */ +#define PDMA_CTRL_PDMA_EN_MASK (0x1U) +#define PDMA_CTRL_PDMA_EN_SHIFT (0U) +#define PDMA_CTRL_PDMA_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_EN_SHIFT) & PDMA_CTRL_PDMA_EN_MASK) +#define PDMA_CTRL_PDMA_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_EN_MASK) >> PDMA_CTRL_PDMA_EN_SHIFT) + +/* Bitfield definition for register: STAT */ +/* + * BLOCKY (ROI) + * + * Y block that is processing + */ +#define PDMA_STAT_BLOCKY_MASK (0xFF000000UL) +#define PDMA_STAT_BLOCKY_SHIFT (24U) +#define PDMA_STAT_BLOCKY_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKY_MASK) >> PDMA_STAT_BLOCKY_SHIFT) + +/* + * BLOCKX (ROI) + * + * X block that is processing + */ +#define PDMA_STAT_BLOCKX_MASK (0xFF0000UL) +#define PDMA_STAT_BLOCKX_SHIFT (16U) +#define PDMA_STAT_BLOCKX_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKX_MASK) >> PDMA_STAT_BLOCKX_SHIFT) + +/* + * PDMA_DONE (ROI) + * + * PDMA one image done + */ +#define PDMA_STAT_PDMA_DONE_MASK (0x200U) +#define PDMA_STAT_PDMA_DONE_SHIFT (9U) +#define PDMA_STAT_PDMA_DONE_GET(x) (((uint32_t)(x) & PDMA_STAT_PDMA_DONE_MASK) >> PDMA_STAT_PDMA_DONE_SHIFT) + +/* + * AXI_ERR_ID (ROI) + * + * AXI error ID + */ +#define PDMA_STAT_AXI_ERR_ID_MASK (0x1E0U) +#define PDMA_STAT_AXI_ERR_ID_SHIFT (5U) +#define PDMA_STAT_AXI_ERR_ID_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_ERR_ID_MASK) >> PDMA_STAT_AXI_ERR_ID_SHIFT) + +/* + * AXI_0_WRITE_ERR (W1C) + * + * AXI0 write err + */ +#define PDMA_STAT_AXI_0_WRITE_ERR_MASK (0x10U) +#define PDMA_STAT_AXI_0_WRITE_ERR_SHIFT (4U) +#define PDMA_STAT_AXI_0_WRITE_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_0_WRITE_ERR_SHIFT) & PDMA_STAT_AXI_0_WRITE_ERR_MASK) +#define PDMA_STAT_AXI_0_WRITE_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_WRITE_ERR_MASK) >> PDMA_STAT_AXI_0_WRITE_ERR_SHIFT) + +/* + * AXI_1_READ_ERR (W1C) + * + * AXI1 read err + */ +#define PDMA_STAT_AXI_1_READ_ERR_MASK (0x8U) +#define PDMA_STAT_AXI_1_READ_ERR_SHIFT (3U) +#define PDMA_STAT_AXI_1_READ_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_1_READ_ERR_SHIFT) & PDMA_STAT_AXI_1_READ_ERR_MASK) +#define PDMA_STAT_AXI_1_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_1_READ_ERR_MASK) >> PDMA_STAT_AXI_1_READ_ERR_SHIFT) + +/* + * AXI_0_READ_ERR (W1C) + * + * AXI0 read err + */ +#define PDMA_STAT_AXI_0_READ_ERR_MASK (0x4U) +#define PDMA_STAT_AXI_0_READ_ERR_SHIFT (2U) +#define PDMA_STAT_AXI_0_READ_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_0_READ_ERR_SHIFT) & PDMA_STAT_AXI_0_READ_ERR_MASK) +#define PDMA_STAT_AXI_0_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_READ_ERR_MASK) >> PDMA_STAT_AXI_0_READ_ERR_SHIFT) + +/* + * IRQ (W1C) + * + * Asserted to indicate a IRQ event + */ +#define PDMA_STAT_IRQ_MASK (0x1U) +#define PDMA_STAT_IRQ_SHIFT (0U) +#define PDMA_STAT_IRQ_SET(x) (((uint32_t)(x) << PDMA_STAT_IRQ_SHIFT) & PDMA_STAT_IRQ_MASK) +#define PDMA_STAT_IRQ_GET(x) (((uint32_t)(x) & PDMA_STAT_IRQ_MASK) >> PDMA_STAT_IRQ_SHIFT) + +/* Bitfield definition for register: OUT_CTRL */ +/* + * DSTALPHA (RW) + * + * The destination (P1) system ALPHA value. + */ +#define PDMA_OUT_CTRL_DSTALPHA_MASK (0xFF000000UL) +#define PDMA_OUT_CTRL_DSTALPHA_SHIFT (24U) +#define PDMA_OUT_CTRL_DSTALPHA_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_DSTALPHA_SHIFT) & PDMA_OUT_CTRL_DSTALPHA_MASK) +#define PDMA_OUT_CTRL_DSTALPHA_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_DSTALPHA_MASK) >> PDMA_OUT_CTRL_DSTALPHA_SHIFT) + +/* + * SRCALPHA (RW) + * + * The source (P0) system ALPHA value. + */ +#define PDMA_OUT_CTRL_SRCALPHA_MASK (0xFF0000UL) +#define PDMA_OUT_CTRL_SRCALPHA_SHIFT (16U) +#define PDMA_OUT_CTRL_SRCALPHA_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_SRCALPHA_SHIFT) & PDMA_OUT_CTRL_SRCALPHA_MASK) +#define PDMA_OUT_CTRL_SRCALPHA_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_SRCALPHA_MASK) >> PDMA_OUT_CTRL_SRCALPHA_SHIFT) + +/* + * DSTALPHA_OP (RW) + * + * The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) + * 0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream + * 1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) + * 2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream + * Others: Reserved + */ +#define PDMA_OUT_CTRL_DSTALPHA_OP_MASK (0xC000U) +#define PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT (14U) +#define PDMA_OUT_CTRL_DSTALPHA_OP_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT) & PDMA_OUT_CTRL_DSTALPHA_OP_MASK) +#define PDMA_OUT_CTRL_DSTALPHA_OP_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_DSTALPHA_OP_MASK) >> PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT) + +/* + * SRCALPHA_OP (RW) + * + * The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) + * 0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream + * 1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) + * 2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream + * Others: Reserved + */ +#define PDMA_OUT_CTRL_SRCALPHA_OP_MASK (0x3000U) +#define PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT (12U) +#define PDMA_OUT_CTRL_SRCALPHA_OP_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT) & PDMA_OUT_CTRL_SRCALPHA_OP_MASK) +#define PDMA_OUT_CTRL_SRCALPHA_OP_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_SRCALPHA_OP_MASK) >> PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT) + +/* + * ABLEND_MODE (RW) + * + * Alpha Blending Mode + * 0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); + * 1: SKBlendMode_Src ; + * 2: SKBlendMode_Dst + * 3: SKBlendMode_SrcOver + * 4: SKBlendMode_DstOver + * 5: SKBlendMode_SrcIn + * 6: SKBlendMode_DstIn + * 7: SKBlendMode_SrcOut + * 8: SKBlendMode_DstOut + * 9: SKBlendMode_SrcATop + * 10: SKBlendMode_DstATop + * 11: SKBlendMode_Xor + * 12: SKBlendMode_Plus (The conventional belding mode) + * 13: SKBlendMode_Modulate + * 14: SRC org + * 15: DST org + * Others: Reserved. + */ +#define PDMA_OUT_CTRL_ABLEND_MODE_MASK (0xF00U) +#define PDMA_OUT_CTRL_ABLEND_MODE_SHIFT (8U) +#define PDMA_OUT_CTRL_ABLEND_MODE_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) +#define PDMA_OUT_CTRL_ABLEND_MODE_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) >> PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) + +/* + * FORMAT (RW) + * + * Output buffer format. + * 0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A + * 0xE RGB565 - 16-bit pixels, byte sequence as B,R + * 0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) + */ +#define PDMA_OUT_CTRL_FORMAT_MASK (0x3FU) +#define PDMA_OUT_CTRL_FORMAT_SHIFT (0U) +#define PDMA_OUT_CTRL_FORMAT_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_FORMAT_SHIFT) & PDMA_OUT_CTRL_FORMAT_MASK) +#define PDMA_OUT_CTRL_FORMAT_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_FORMAT_MASK) >> PDMA_OUT_CTRL_FORMAT_SHIFT) + +/* Bitfield definition for register: OUT_BUF */ +/* + * ADDR (RW) + * + * Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. + */ +#define PDMA_OUT_BUF_ADDR_MASK (0xFFFFFFFFUL) +#define PDMA_OUT_BUF_ADDR_SHIFT (0U) +#define PDMA_OUT_BUF_ADDR_SET(x) (((uint32_t)(x) << PDMA_OUT_BUF_ADDR_SHIFT) & PDMA_OUT_BUF_ADDR_MASK) +#define PDMA_OUT_BUF_ADDR_GET(x) (((uint32_t)(x) & PDMA_OUT_BUF_ADDR_MASK) >> PDMA_OUT_BUF_ADDR_SHIFT) + +/* Bitfield definition for register: OUT_PITCH */ +/* + * BYTELEN (RW) + * + * Indicates the number of bytes in memory between two vertically adjacent pixels. + */ +#define PDMA_OUT_PITCH_BYTELEN_MASK (0xFFFFU) +#define PDMA_OUT_PITCH_BYTELEN_SHIFT (0U) +#define PDMA_OUT_PITCH_BYTELEN_SET(x) (((uint32_t)(x) << PDMA_OUT_PITCH_BYTELEN_SHIFT) & PDMA_OUT_PITCH_BYTELEN_MASK) +#define PDMA_OUT_PITCH_BYTELEN_GET(x) (((uint32_t)(x) & PDMA_OUT_PITCH_BYTELEN_MASK) >> PDMA_OUT_PITCH_BYTELEN_SHIFT) + +/* Bitfield definition for register: OUT_LRC */ +/* + * Y (RW) + * + * This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. + * The value is the height of the output image size. + */ +#define PDMA_OUT_LRC_Y_MASK (0x3FFF0000UL) +#define PDMA_OUT_LRC_Y_SHIFT (16U) +#define PDMA_OUT_LRC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_LRC_Y_SHIFT) & PDMA_OUT_LRC_Y_MASK) +#define PDMA_OUT_LRC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_LRC_Y_MASK) >> PDMA_OUT_LRC_Y_SHIFT) + +/* + * X (RW) + * + * This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. + * Should be the width of the output image size. + */ +#define PDMA_OUT_LRC_X_MASK (0x3FFFU) +#define PDMA_OUT_LRC_X_SHIFT (0U) +#define PDMA_OUT_LRC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_LRC_X_SHIFT) & PDMA_OUT_LRC_X_MASK) +#define PDMA_OUT_LRC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_LRC_X_MASK) >> PDMA_OUT_LRC_X_SHIFT) + +/* Bitfield definition for register of struct array OUT_PS: ULC */ +/* + * Y (RW) + * + * This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. + */ +#define PDMA_OUT_PS_ULC_Y_MASK (0x3FFF0000UL) +#define PDMA_OUT_PS_ULC_Y_SHIFT (16U) +#define PDMA_OUT_PS_ULC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_ULC_Y_SHIFT) & PDMA_OUT_PS_ULC_Y_MASK) +#define PDMA_OUT_PS_ULC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_ULC_Y_MASK) >> PDMA_OUT_PS_ULC_Y_SHIFT) + +/* + * X (RW) + * + * This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. + */ +#define PDMA_OUT_PS_ULC_X_MASK (0x3FFFU) +#define PDMA_OUT_PS_ULC_X_SHIFT (0U) +#define PDMA_OUT_PS_ULC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_ULC_X_SHIFT) & PDMA_OUT_PS_ULC_X_MASK) +#define PDMA_OUT_PS_ULC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_ULC_X_MASK) >> PDMA_OUT_PS_ULC_X_SHIFT) + +/* Bitfield definition for register of struct array OUT_PS: LRC */ +/* + * Y (RW) + * + * This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. + */ +#define PDMA_OUT_PS_LRC_Y_MASK (0x3FFF0000UL) +#define PDMA_OUT_PS_LRC_Y_SHIFT (16U) +#define PDMA_OUT_PS_LRC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_LRC_Y_SHIFT) & PDMA_OUT_PS_LRC_Y_MASK) +#define PDMA_OUT_PS_LRC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_LRC_Y_MASK) >> PDMA_OUT_PS_LRC_Y_SHIFT) + +/* + * X (RW) + * + * This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. + */ +#define PDMA_OUT_PS_LRC_X_MASK (0x3FFFU) +#define PDMA_OUT_PS_LRC_X_SHIFT (0U) +#define PDMA_OUT_PS_LRC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_LRC_X_SHIFT) & PDMA_OUT_PS_LRC_X_MASK) +#define PDMA_OUT_PS_LRC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_LRC_X_MASK) >> PDMA_OUT_PS_LRC_X_SHIFT) + +/* Bitfield definition for register of struct array PS: CTRL */ +/* + * INB13_SWAP (RW) + * + * Swap bit[31:24] and bit [15:8] before pack_dir operation. + */ +#define PDMA_PS_CTRL_INB13_SWAP_MASK (0x100000UL) +#define PDMA_PS_CTRL_INB13_SWAP_SHIFT (20U) +#define PDMA_PS_CTRL_INB13_SWAP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_INB13_SWAP_SHIFT) & PDMA_PS_CTRL_INB13_SWAP_MASK) +#define PDMA_PS_CTRL_INB13_SWAP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_INB13_SWAP_MASK) >> PDMA_PS_CTRL_INB13_SWAP_SHIFT) + +/* + * PACK_DIR (RW) + * + * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. + * 2'b00: no change {A3, A2, A1, A0} + * 2'b01: {A2, A3, A0, A1} + * 2'b10: {A1, A0, A3, A2} + * 2'b11: {A0, A1, A2, A3} + */ +#define PDMA_PS_CTRL_PACK_DIR_MASK (0xC0000UL) +#define PDMA_PS_CTRL_PACK_DIR_SHIFT (18U) +#define PDMA_PS_CTRL_PACK_DIR_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_PACK_DIR_SHIFT) & PDMA_PS_CTRL_PACK_DIR_MASK) +#define PDMA_PS_CTRL_PACK_DIR_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_PACK_DIR_MASK) >> PDMA_PS_CTRL_PACK_DIR_SHIFT) + +/* + * BKGCL4CLR (RW) + * + * Enable to use background color for clear area + */ +#define PDMA_PS_CTRL_BKGCL4CLR_MASK (0x20000UL) +#define PDMA_PS_CTRL_BKGCL4CLR_SHIFT (17U) +#define PDMA_PS_CTRL_BKGCL4CLR_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_BKGCL4CLR_SHIFT) & PDMA_PS_CTRL_BKGCL4CLR_MASK) +#define PDMA_PS_CTRL_BKGCL4CLR_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_BKGCL4CLR_MASK) >> PDMA_PS_CTRL_BKGCL4CLR_SHIFT) + +/* + * YCBCR_MODE (RW) + * + * YCbCr mode or YUV mode + */ +#define PDMA_PS_CTRL_YCBCR_MODE_MASK (0x10000UL) +#define PDMA_PS_CTRL_YCBCR_MODE_SHIFT (16U) +#define PDMA_PS_CTRL_YCBCR_MODE_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_YCBCR_MODE_SHIFT) & PDMA_PS_CTRL_YCBCR_MODE_MASK) +#define PDMA_PS_CTRL_YCBCR_MODE_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_YCBCR_MODE_MASK) >> PDMA_PS_CTRL_YCBCR_MODE_SHIFT) + +/* + * BYPASS (RW) + * + * Asserted to bypass the CSC stage + */ +#define PDMA_PS_CTRL_BYPASS_MASK (0x8000U) +#define PDMA_PS_CTRL_BYPASS_SHIFT (15U) +#define PDMA_PS_CTRL_BYPASS_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_BYPASS_SHIFT) & PDMA_PS_CTRL_BYPASS_MASK) +#define PDMA_PS_CTRL_BYPASS_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_BYPASS_MASK) >> PDMA_PS_CTRL_BYPASS_SHIFT) + +/* + * VFLIP (RW) + * + * Indicates that the input should be flipped vertically (effect applied before rotation). + */ +#define PDMA_PS_CTRL_VFLIP_MASK (0x4000U) +#define PDMA_PS_CTRL_VFLIP_SHIFT (14U) +#define PDMA_PS_CTRL_VFLIP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_VFLIP_SHIFT) & PDMA_PS_CTRL_VFLIP_MASK) +#define PDMA_PS_CTRL_VFLIP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_VFLIP_MASK) >> PDMA_PS_CTRL_VFLIP_SHIFT) + +/* + * HFLIP (RW) + * + * Indicates that the input should be flipped horizontally (effect applied before rotation). + */ +#define PDMA_PS_CTRL_HFLIP_MASK (0x2000U) +#define PDMA_PS_CTRL_HFLIP_SHIFT (13U) +#define PDMA_PS_CTRL_HFLIP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_HFLIP_SHIFT) & PDMA_PS_CTRL_HFLIP_MASK) +#define PDMA_PS_CTRL_HFLIP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_HFLIP_MASK) >> PDMA_PS_CTRL_HFLIP_SHIFT) + +/* + * ROTATE (RW) + * + * Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring + * after the FLIP_X and FLIP_Y permutation. + * 0x0 ROT_0 + * 0x1 ROT_90 + * 0x2 ROT_180 + * 0x3 ROT_270 + */ +#define PDMA_PS_CTRL_ROTATE_MASK (0x1800U) +#define PDMA_PS_CTRL_ROTATE_SHIFT (11U) +#define PDMA_PS_CTRL_ROTATE_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_ROTATE_SHIFT) & PDMA_PS_CTRL_ROTATE_MASK) +#define PDMA_PS_CTRL_ROTATE_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_ROTATE_MASK) >> PDMA_PS_CTRL_ROTATE_SHIFT) + +/* + * DECY (RW) + * + * Verticle pre decimation filter control. + * 0x0 DISABLE - Disable pre-decimation filter. + * 0x1 DECY2 - Decimate PS by 2. + * 0x2 DECY4 - Decimate PS by 4. + * 0x3 DECY8 - Decimate PS by 8. + */ +#define PDMA_PS_CTRL_DECY_MASK (0x600U) +#define PDMA_PS_CTRL_DECY_SHIFT (9U) +#define PDMA_PS_CTRL_DECY_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_DECY_SHIFT) & PDMA_PS_CTRL_DECY_MASK) +#define PDMA_PS_CTRL_DECY_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_DECY_MASK) >> PDMA_PS_CTRL_DECY_SHIFT) + +/* + * DECX (RW) + * + * Horizontal pre decimation filter control. + * 0x0 DISABLE - Disable pre-decimation filter. + * 0x1 DECX2 - Decimate PS by 2. + * 0x2 DECX4 - Decimate PS by 4. + * 0x3 DECX8 - Decimate PS by 8. + */ +#define PDMA_PS_CTRL_DECX_MASK (0x180U) +#define PDMA_PS_CTRL_DECX_SHIFT (7U) +#define PDMA_PS_CTRL_DECX_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_DECX_SHIFT) & PDMA_PS_CTRL_DECX_MASK) +#define PDMA_PS_CTRL_DECX_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_DECX_MASK) >> PDMA_PS_CTRL_DECX_SHIFT) + +/* + * HW_BYTE_SWAP (RW) + * + * Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. + */ +#define PDMA_PS_CTRL_HW_BYTE_SWAP_MASK (0x40U) +#define PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT (6U) +#define PDMA_PS_CTRL_HW_BYTE_SWAP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT) & PDMA_PS_CTRL_HW_BYTE_SWAP_MASK) +#define PDMA_PS_CTRL_HW_BYTE_SWAP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_HW_BYTE_SWAP_MASK) >> PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT) + +/* + * FORMAT (RW) + * + * PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. + * 0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A + * 0xE RGB565 - 16-bit pixels, byte sequence as B,R + * 0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) + */ +#define PDMA_PS_CTRL_FORMAT_MASK (0x3FU) +#define PDMA_PS_CTRL_FORMAT_SHIFT (0U) +#define PDMA_PS_CTRL_FORMAT_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_FORMAT_SHIFT) & PDMA_PS_CTRL_FORMAT_MASK) +#define PDMA_PS_CTRL_FORMAT_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_FORMAT_MASK) >> PDMA_PS_CTRL_FORMAT_SHIFT) + +/* Bitfield definition for register of struct array PS: BUF */ +/* + * ADDR (RW) + * + * Address pointer for the PS RGB or Y (luma) input buffer. + */ +#define PDMA_PS_BUF_ADDR_MASK (0xFFFFFFFFUL) +#define PDMA_PS_BUF_ADDR_SHIFT (0U) +#define PDMA_PS_BUF_ADDR_SET(x) (((uint32_t)(x) << PDMA_PS_BUF_ADDR_SHIFT) & PDMA_PS_BUF_ADDR_MASK) +#define PDMA_PS_BUF_ADDR_GET(x) (((uint32_t)(x) & PDMA_PS_BUF_ADDR_MASK) >> PDMA_PS_BUF_ADDR_SHIFT) + +/* Bitfield definition for register of struct array PS: PITCH */ +/* + * BYTELEN (RW) + * + * Indicates the number of bytes in memory between two vertically adjacent pixels. + */ +#define PDMA_PS_PITCH_BYTELEN_MASK (0xFFFFU) +#define PDMA_PS_PITCH_BYTELEN_SHIFT (0U) +#define PDMA_PS_PITCH_BYTELEN_SET(x) (((uint32_t)(x) << PDMA_PS_PITCH_BYTELEN_SHIFT) & PDMA_PS_PITCH_BYTELEN_MASK) +#define PDMA_PS_PITCH_BYTELEN_GET(x) (((uint32_t)(x) & PDMA_PS_PITCH_BYTELEN_MASK) >> PDMA_PS_PITCH_BYTELEN_SHIFT) + +/* Bitfield definition for register of struct array PS: BKGD */ +/* + * COLOR (RW) + * + * Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. + */ +#define PDMA_PS_BKGD_COLOR_MASK (0xFFFFFFFFUL) +#define PDMA_PS_BKGD_COLOR_SHIFT (0U) +#define PDMA_PS_BKGD_COLOR_SET(x) (((uint32_t)(x) << PDMA_PS_BKGD_COLOR_SHIFT) & PDMA_PS_BKGD_COLOR_MASK) +#define PDMA_PS_BKGD_COLOR_GET(x) (((uint32_t)(x) & PDMA_PS_BKGD_COLOR_MASK) >> PDMA_PS_BKGD_COLOR_SHIFT) + +/* Bitfield definition for register of struct array PS: SCALE */ +/* + * Y (RW) + * + * This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + */ +#define PDMA_PS_SCALE_Y_MASK (0x7FFF0000UL) +#define PDMA_PS_SCALE_Y_SHIFT (16U) +#define PDMA_PS_SCALE_Y_SET(x) (((uint32_t)(x) << PDMA_PS_SCALE_Y_SHIFT) & PDMA_PS_SCALE_Y_MASK) +#define PDMA_PS_SCALE_Y_GET(x) (((uint32_t)(x) & PDMA_PS_SCALE_Y_MASK) >> PDMA_PS_SCALE_Y_SHIFT) + +/* + * X (RW) + * + * This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. + */ +#define PDMA_PS_SCALE_X_MASK (0x7FFFU) +#define PDMA_PS_SCALE_X_SHIFT (0U) +#define PDMA_PS_SCALE_X_SET(x) (((uint32_t)(x) << PDMA_PS_SCALE_X_SHIFT) & PDMA_PS_SCALE_X_MASK) +#define PDMA_PS_SCALE_X_GET(x) (((uint32_t)(x) & PDMA_PS_SCALE_X_MASK) >> PDMA_PS_SCALE_X_SHIFT) + +/* Bitfield definition for register of struct array PS: OFFSET */ +/* + * Y (RW) + * + * This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. + * It is applied after the decimation filter stage, and before the bilinear filter stage. + */ +#define PDMA_PS_OFFSET_Y_MASK (0xFFF0000UL) +#define PDMA_PS_OFFSET_Y_SHIFT (16U) +#define PDMA_PS_OFFSET_Y_SET(x) (((uint32_t)(x) << PDMA_PS_OFFSET_Y_SHIFT) & PDMA_PS_OFFSET_Y_MASK) +#define PDMA_PS_OFFSET_Y_GET(x) (((uint32_t)(x) & PDMA_PS_OFFSET_Y_MASK) >> PDMA_PS_OFFSET_Y_SHIFT) + +/* + * X (RW) + * + * This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. + * It is applied after the decimation filter stage, and before the bilinear filter stage. + */ +#define PDMA_PS_OFFSET_X_MASK (0xFFFU) +#define PDMA_PS_OFFSET_X_SHIFT (0U) +#define PDMA_PS_OFFSET_X_SET(x) (((uint32_t)(x) << PDMA_PS_OFFSET_X_SHIFT) & PDMA_PS_OFFSET_X_MASK) +#define PDMA_PS_OFFSET_X_GET(x) (((uint32_t)(x) & PDMA_PS_OFFSET_X_MASK) >> PDMA_PS_OFFSET_X_SHIFT) + +/* Bitfield definition for register of struct array PS: CLRKEY_LOW */ +/* + * LIMIT (RW) + * + * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. + */ +#define PDMA_PS_CLRKEY_LOW_LIMIT_MASK (0xFFFFFFUL) +#define PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT (0U) +#define PDMA_PS_CLRKEY_LOW_LIMIT_SET(x) (((uint32_t)(x) << PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT) & PDMA_PS_CLRKEY_LOW_LIMIT_MASK) +#define PDMA_PS_CLRKEY_LOW_LIMIT_GET(x) (((uint32_t)(x) & PDMA_PS_CLRKEY_LOW_LIMIT_MASK) >> PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT) + +/* Bitfield definition for register of struct array PS: CLRKEY_HIGH */ +/* + * LIMIT (RW) + * + * High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 + */ +#define PDMA_PS_CLRKEY_HIGH_LIMIT_MASK (0xFFFFFFUL) +#define PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT (0U) +#define PDMA_PS_CLRKEY_HIGH_LIMIT_SET(x) (((uint32_t)(x) << PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT) & PDMA_PS_CLRKEY_HIGH_LIMIT_MASK) +#define PDMA_PS_CLRKEY_HIGH_LIMIT_GET(x) (((uint32_t)(x) & PDMA_PS_CLRKEY_HIGH_LIMIT_MASK) >> PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT) + +/* Bitfield definition for register of struct array PS: ORG */ +/* + * HIGHT (RW) + * + * The number of vertical pixels of the original frame (not -1) + */ +#define PDMA_PS_ORG_HIGHT_MASK (0x3FFF0000UL) +#define PDMA_PS_ORG_HIGHT_SHIFT (16U) +#define PDMA_PS_ORG_HIGHT_SET(x) (((uint32_t)(x) << PDMA_PS_ORG_HIGHT_SHIFT) & PDMA_PS_ORG_HIGHT_MASK) +#define PDMA_PS_ORG_HIGHT_GET(x) (((uint32_t)(x) & PDMA_PS_ORG_HIGHT_MASK) >> PDMA_PS_ORG_HIGHT_SHIFT) + +/* + * WIDTH (RW) + * + * The number of horizontal pixels of the original frame (not -1) + */ +#define PDMA_PS_ORG_WIDTH_MASK (0x3FFFU) +#define PDMA_PS_ORG_WIDTH_SHIFT (0U) +#define PDMA_PS_ORG_WIDTH_SET(x) (((uint32_t)(x) << PDMA_PS_ORG_WIDTH_SHIFT) & PDMA_PS_ORG_WIDTH_MASK) +#define PDMA_PS_ORG_WIDTH_GET(x) (((uint32_t)(x) & PDMA_PS_ORG_WIDTH_MASK) >> PDMA_PS_ORG_WIDTH_SHIFT) + +/* Bitfield definition for register: YUV2RGB_COEF0 */ +/* + * C0 (RW) + * + * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) + */ +#define PDMA_YUV2RGB_COEF0_C0_MASK (0x1FFC0000UL) +#define PDMA_YUV2RGB_COEF0_C0_SHIFT (18U) +#define PDMA_YUV2RGB_COEF0_C0_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_C0_SHIFT) & PDMA_YUV2RGB_COEF0_C0_MASK) +#define PDMA_YUV2RGB_COEF0_C0_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_C0_MASK) >> PDMA_YUV2RGB_COEF0_C0_SHIFT) + +/* + * UV_OFFSET (RW) + * + * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. + * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). + */ +#define PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK (0x3FE00UL) +#define PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT (9U) +#define PDMA_YUV2RGB_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT) & PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK) +#define PDMA_YUV2RGB_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK) >> PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT) + +/* + * Y_OFFSET (RW) + * + * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is + * typically -16 (0x1F0). + */ +#define PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK (0x1FFU) +#define PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT (0U) +#define PDMA_YUV2RGB_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT) & PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK) +#define PDMA_YUV2RGB_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK) >> PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT) + +/* Bitfield definition for register: YUV2RGB_COEF1 */ +/* + * C1 (RW) + * + * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). + */ +#define PDMA_YUV2RGB_COEF1_C1_MASK (0x7FF0000UL) +#define PDMA_YUV2RGB_COEF1_C1_SHIFT (16U) +#define PDMA_YUV2RGB_COEF1_C1_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF1_C1_SHIFT) & PDMA_YUV2RGB_COEF1_C1_MASK) +#define PDMA_YUV2RGB_COEF1_C1_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF1_C1_MASK) >> PDMA_YUV2RGB_COEF1_C1_SHIFT) + +/* + * C4 (RW) + * + * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). + */ +#define PDMA_YUV2RGB_COEF1_C4_MASK (0x7FFU) +#define PDMA_YUV2RGB_COEF1_C4_SHIFT (0U) +#define PDMA_YUV2RGB_COEF1_C4_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF1_C4_SHIFT) & PDMA_YUV2RGB_COEF1_C4_MASK) +#define PDMA_YUV2RGB_COEF1_C4_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF1_C4_MASK) >> PDMA_YUV2RGB_COEF1_C4_SHIFT) + +/* Bitfield definition for register: YUV2RGB_COEF2 */ +/* + * C2 (RW) + * + * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). + */ +#define PDMA_YUV2RGB_COEF2_C2_MASK (0x7FF0000UL) +#define PDMA_YUV2RGB_COEF2_C2_SHIFT (16U) +#define PDMA_YUV2RGB_COEF2_C2_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF2_C2_SHIFT) & PDMA_YUV2RGB_COEF2_C2_MASK) +#define PDMA_YUV2RGB_COEF2_C2_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF2_C2_MASK) >> PDMA_YUV2RGB_COEF2_C2_SHIFT) + +/* + * C3 (RW) + * + * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). + */ +#define PDMA_YUV2RGB_COEF2_C3_MASK (0x7FFU) +#define PDMA_YUV2RGB_COEF2_C3_SHIFT (0U) +#define PDMA_YUV2RGB_COEF2_C3_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF2_C3_SHIFT) & PDMA_YUV2RGB_COEF2_C3_MASK) +#define PDMA_YUV2RGB_COEF2_C3_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF2_C3_MASK) >> PDMA_YUV2RGB_COEF2_C3_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF0 */ +/* + * YCBCR_MODE (RW) + * + * Asserted to use YCrCb mode + */ +#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK (0x80000000UL) +#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT (31U) +#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) & PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK) +#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK) >> PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) + +/* + * ENABLE (RW) + * + * Asserted to enable this RGB2YUV CSC stage + */ +#define PDMA_RGB2YUV_COEF0_ENABLE_MASK (0x40000000UL) +#define PDMA_RGB2YUV_COEF0_ENABLE_SHIFT (30U) +#define PDMA_RGB2YUV_COEF0_ENABLE_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_ENABLE_SHIFT) & PDMA_RGB2YUV_COEF0_ENABLE_MASK) +#define PDMA_RGB2YUV_COEF0_ENABLE_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_ENABLE_MASK) >> PDMA_RGB2YUV_COEF0_ENABLE_SHIFT) + +/* + * C0 (RW) + * + * CSC parameters C0 + */ +#define PDMA_RGB2YUV_COEF0_C0_MASK (0x1FFC0000UL) +#define PDMA_RGB2YUV_COEF0_C0_SHIFT (18U) +#define PDMA_RGB2YUV_COEF0_C0_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_C0_SHIFT) & PDMA_RGB2YUV_COEF0_C0_MASK) +#define PDMA_RGB2YUV_COEF0_C0_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_C0_MASK) >> PDMA_RGB2YUV_COEF0_C0_SHIFT) + +/* + * UV_OFFSET (RW) + * + * CSC parameters UV_OFFSET + */ +#define PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK (0x3FE00UL) +#define PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT (9U) +#define PDMA_RGB2YUV_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT) & PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK) +#define PDMA_RGB2YUV_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK) >> PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT) + +/* + * Y_OFFSET (RW) + * + * CSC parameters Y_OFFSET + */ +#define PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK (0x1FFU) +#define PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT (0U) +#define PDMA_RGB2YUV_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT) & PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK) +#define PDMA_RGB2YUV_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK) >> PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF1 */ +/* + * C1 (RW) + * + * CSC parameters C1 + */ +#define PDMA_RGB2YUV_COEF1_C1_MASK (0x7FF0000UL) +#define PDMA_RGB2YUV_COEF1_C1_SHIFT (16U) +#define PDMA_RGB2YUV_COEF1_C1_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF1_C1_SHIFT) & PDMA_RGB2YUV_COEF1_C1_MASK) +#define PDMA_RGB2YUV_COEF1_C1_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF1_C1_MASK) >> PDMA_RGB2YUV_COEF1_C1_SHIFT) + +/* + * C4 (RW) + * + * CSC parameters C4 + */ +#define PDMA_RGB2YUV_COEF1_C4_MASK (0x7FFU) +#define PDMA_RGB2YUV_COEF1_C4_SHIFT (0U) +#define PDMA_RGB2YUV_COEF1_C4_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF1_C4_SHIFT) & PDMA_RGB2YUV_COEF1_C4_MASK) +#define PDMA_RGB2YUV_COEF1_C4_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF1_C4_MASK) >> PDMA_RGB2YUV_COEF1_C4_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF2 */ +/* + * C2 (RW) + * + * CSC parameters C2 + */ +#define PDMA_RGB2YUV_COEF2_C2_MASK (0x7FF0000UL) +#define PDMA_RGB2YUV_COEF2_C2_SHIFT (16U) +#define PDMA_RGB2YUV_COEF2_C2_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF2_C2_SHIFT) & PDMA_RGB2YUV_COEF2_C2_MASK) +#define PDMA_RGB2YUV_COEF2_C2_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF2_C2_MASK) >> PDMA_RGB2YUV_COEF2_C2_SHIFT) + +/* + * C3 (RW) + * + * CSC parameters C3 + */ +#define PDMA_RGB2YUV_COEF2_C3_MASK (0x7FFU) +#define PDMA_RGB2YUV_COEF2_C3_SHIFT (0U) +#define PDMA_RGB2YUV_COEF2_C3_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF2_C3_SHIFT) & PDMA_RGB2YUV_COEF2_C3_MASK) +#define PDMA_RGB2YUV_COEF2_C3_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF2_C3_MASK) >> PDMA_RGB2YUV_COEF2_C3_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF3 */ +/* + * C6 (RW) + * + * CSC parameters C6 + */ +#define PDMA_RGB2YUV_COEF3_C6_MASK (0x7FF0000UL) +#define PDMA_RGB2YUV_COEF3_C6_SHIFT (16U) +#define PDMA_RGB2YUV_COEF3_C6_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF3_C6_SHIFT) & PDMA_RGB2YUV_COEF3_C6_MASK) +#define PDMA_RGB2YUV_COEF3_C6_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF3_C6_MASK) >> PDMA_RGB2YUV_COEF3_C6_SHIFT) + +/* + * C5 (RW) + * + * CSC parameters C5 + */ +#define PDMA_RGB2YUV_COEF3_C5_MASK (0x7FFU) +#define PDMA_RGB2YUV_COEF3_C5_SHIFT (0U) +#define PDMA_RGB2YUV_COEF3_C5_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF3_C5_SHIFT) & PDMA_RGB2YUV_COEF3_C5_MASK) +#define PDMA_RGB2YUV_COEF3_C5_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF3_C5_MASK) >> PDMA_RGB2YUV_COEF3_C5_SHIFT) + +/* Bitfield definition for register: RGB2YUV_COEF4 */ +/* + * C8 (RW) + * + * CSC parameters C8 + */ +#define PDMA_RGB2YUV_COEF4_C8_MASK (0x7FF0000UL) +#define PDMA_RGB2YUV_COEF4_C8_SHIFT (16U) +#define PDMA_RGB2YUV_COEF4_C8_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF4_C8_SHIFT) & PDMA_RGB2YUV_COEF4_C8_MASK) +#define PDMA_RGB2YUV_COEF4_C8_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF4_C8_MASK) >> PDMA_RGB2YUV_COEF4_C8_SHIFT) + +/* + * C7 (RW) + * + * CSC parameters C7 + */ +#define PDMA_RGB2YUV_COEF4_C7_MASK (0x7FFU) +#define PDMA_RGB2YUV_COEF4_C7_SHIFT (0U) +#define PDMA_RGB2YUV_COEF4_C7_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF4_C7_SHIFT) & PDMA_RGB2YUV_COEF4_C7_MASK) +#define PDMA_RGB2YUV_COEF4_C7_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF4_C7_MASK) >> PDMA_RGB2YUV_COEF4_C7_SHIFT) + + + +/* OUT_PS register group index macro definition */ +#define PDMA_OUT_PS_0 (0UL) +#define PDMA_OUT_PS_1 (1UL) + +/* PS register group index macro definition */ +#define PDMA_PS_0 (0UL) +#define PDMA_PS_1 (1UL) + + +#endif /* HPM_PDMA_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h new file mode 100644 index 0000000000..ae9378a07d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PGPR_H +#define HPM_PGPR_H + +typedef struct { + __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ + __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ + __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ + __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ + __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ + __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ + __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ + __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ + __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ + __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ + __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ + __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ + __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ + __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ + __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ + __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ +} PGPR_Type; + + +/* Bitfield definition for register: PMIC_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) +#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) +#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) +#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) +#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR04 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) +#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR05 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) +#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR06 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) +#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR07 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) +#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR08 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) +#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR09 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) +#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR10 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) +#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR11 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) +#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR12 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) +#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR13 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) +#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR14 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) +#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR15 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) +#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) + + + + +#endif /* HPM_PGPR_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_regs.h new file mode 100644 index 0000000000..48c410378e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_regs.h @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PLIC_H +#define HPM_PLIC_H + +typedef struct { + __RW uint32_t FEATURE; /* 0x0: Feature enable register */ + __RW uint32_t PRIORITY[127]; /* 0x4 - 0x1FC: Source priority */ + __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */ + __RW uint32_t PENDING[4]; /* 0x1000 - 0x100C: Pending status */ + __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */ + __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */ + __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */ + __R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and targets */ + __R uint32_t INFO; /* 0x1104: Version and the maximum priority */ + __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */ + struct { + __RW uint32_t INTEN[4]; /* 0x2000 - 0x200C: machine interrupt enable */ + __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */ + } TARGETINT[2]; + __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */ + struct { + __RW uint32_t THRESHOLD; /* 0x200000: Target0 priority threshold */ + __RW uint32_t CLAIM; /* 0x200004: Target claim and complete */ + __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */ + __RW uint32_t PPS; /* 0x200400: Preempted priority stack */ + __R uint8_t RESERVED1[3068]; /* 0x200404 - 0x200FFF: Reserved */ + } TARGETCONFIG[2]; +} PLIC_Type; + + +/* Bitfield definition for register: FEATURE */ +/* + * VECTORED (RW) + * + * Vector mode enable + * 0: Disabled + * 1: Enabled + */ +#define PLIC_FEATURE_VECTORED_MASK (0x2U) +#define PLIC_FEATURE_VECTORED_SHIFT (1U) +#define PLIC_FEATURE_VECTORED_SET(x) (((uint32_t)(x) << PLIC_FEATURE_VECTORED_SHIFT) & PLIC_FEATURE_VECTORED_MASK) +#define PLIC_FEATURE_VECTORED_GET(x) (((uint32_t)(x) & PLIC_FEATURE_VECTORED_MASK) >> PLIC_FEATURE_VECTORED_SHIFT) + +/* + * PREEMPT (RW) + * + * Preemptive priority interrupt enable + * 0: Disabled + * 1: Enabled + */ +#define PLIC_FEATURE_PREEMPT_MASK (0x1U) +#define PLIC_FEATURE_PREEMPT_SHIFT (0U) +#define PLIC_FEATURE_PREEMPT_SET(x) (((uint32_t)(x) << PLIC_FEATURE_PREEMPT_SHIFT) & PLIC_FEATURE_PREEMPT_MASK) +#define PLIC_FEATURE_PREEMPT_GET(x) (((uint32_t)(x) & PLIC_FEATURE_PREEMPT_MASK) >> PLIC_FEATURE_PREEMPT_SHIFT) + +/* Bitfield definition for register array: PRIORITY */ +/* + * PRIORITY (RW) + * + * Interrupt source priority. The valid range of this field is 0-7. + * 0: Never interrupt + * 1-7: Interrupt source priority. The larger the value, the higher the priority. + */ +#define PLIC_PRIORITY_PRIORITY_MASK (0xFFFFFFFFUL) +#define PLIC_PRIORITY_PRIORITY_SHIFT (0U) +#define PLIC_PRIORITY_PRIORITY_SET(x) (((uint32_t)(x) << PLIC_PRIORITY_PRIORITY_SHIFT) & PLIC_PRIORITY_PRIORITY_MASK) +#define PLIC_PRIORITY_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_PRIORITY_PRIORITY_MASK) >> PLIC_PRIORITY_PRIORITY_SHIFT) + +/* Bitfield definition for register array: PENDING */ +/* + * INTERRUPT (RW) + * + * The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + */ +#define PLIC_PENDING_INTERRUPT_MASK (0xFFFFFFFFUL) +#define PLIC_PENDING_INTERRUPT_SHIFT (0U) +#define PLIC_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_PENDING_INTERRUPT_SHIFT) & PLIC_PENDING_INTERRUPT_MASK) +#define PLIC_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_PENDING_INTERRUPT_MASK) >> PLIC_PENDING_INTERRUPT_SHIFT) + +/* Bitfield definition for register array: TRIGGER */ +/* + * INTERRUPT (RO) + * + * The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. + * 0: Level-triggered interrupt + * 1: Edge-triggered interrupt + */ +#define PLIC_TRIGGER_INTERRUPT_MASK (0xFFFFFFFFUL) +#define PLIC_TRIGGER_INTERRUPT_SHIFT (0U) +#define PLIC_TRIGGER_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TRIGGER_INTERRUPT_MASK) >> PLIC_TRIGGER_INTERRUPT_SHIFT) + +/* Bitfield definition for register: NUMBER */ +/* + * NUM_TARGET (RO) + * + * The number of supported targets + */ +#define PLIC_NUMBER_NUM_TARGET_MASK (0xFFFF0000UL) +#define PLIC_NUMBER_NUM_TARGET_SHIFT (16U) +#define PLIC_NUMBER_NUM_TARGET_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_TARGET_MASK) >> PLIC_NUMBER_NUM_TARGET_SHIFT) + +/* + * NUM_INTERRUPT (RO) + * + * The number of supported interrupt sources + */ +#define PLIC_NUMBER_NUM_INTERRUPT_MASK (0xFFFFU) +#define PLIC_NUMBER_NUM_INTERRUPT_SHIFT (0U) +#define PLIC_NUMBER_NUM_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_INTERRUPT_MASK) >> PLIC_NUMBER_NUM_INTERRUPT_SHIFT) + +/* Bitfield definition for register: INFO */ +/* + * MAX_PRIORITY (RO) + * + * The maximum priority supported + */ +#define PLIC_INFO_MAX_PRIORITY_MASK (0xFFFF0000UL) +#define PLIC_INFO_MAX_PRIORITY_SHIFT (16U) +#define PLIC_INFO_MAX_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_INFO_MAX_PRIORITY_MASK) >> PLIC_INFO_MAX_PRIORITY_SHIFT) + +/* + * VERSION (RO) + * + * The version of the PLIC design + */ +#define PLIC_INFO_VERSION_MASK (0xFFFFU) +#define PLIC_INFO_VERSION_SHIFT (0U) +#define PLIC_INFO_VERSION_GET(x) (((uint32_t)(x) & PLIC_INFO_VERSION_MASK) >> PLIC_INFO_VERSION_SHIFT) + +/* Bitfield definition for register of struct array TARGETINT: INTEN0 */ +/* + * INTERRUPT (RW) + * + * The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + */ +#define PLIC_INTEN_INTERRUPT_MASK (0xFFFFFFFFUL) +#define PLIC_INTEN_INTERRUPT_SHIFT (0U) +#define PLIC_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_INTEN_INTERRUPT_SHIFT) & PLIC_INTEN_INTERRUPT_MASK) +#define PLIC_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_INTEN_INTERRUPT_MASK) >> PLIC_INTEN_INTERRUPT_SHIFT) + +/* Bitfield definition for register of struct array TARGETCONFIG: THRESHOLD */ +/* + * THRESHOLD (RW) + * + * Interrupt priority threshold. + */ +#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK (0xFFFFFFFFUL) +#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT (0U) +#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) +#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) >> PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) + +/* Bitfield definition for register of struct array TARGETCONFIG: CLAIM */ +/* + * INTERRUPT_ID (RW) + * + * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + */ +#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK (0x3FFU) +#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT (0U) +#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) +#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) >> PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) + +/* Bitfield definition for register of struct array TARGETCONFIG: PPS */ +/* + * PRIORITY_PREEMPTED (RW) + * + * Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + */ +#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK (0xFFFFFFFFUL) +#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT (0U) +#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) +#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) >> PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) + + + +/* PRIORITY register group index macro definition */ +#define PLIC_PRIORITY_PRIORITY1 (0UL) +#define PLIC_PRIORITY_PRIORITY2 (1UL) +#define PLIC_PRIORITY_PRIORITY3 (2UL) +#define PLIC_PRIORITY_PRIORITY4 (3UL) +#define PLIC_PRIORITY_PRIORITY5 (4UL) +#define PLIC_PRIORITY_PRIORITY6 (5UL) +#define PLIC_PRIORITY_PRIORITY7 (6UL) +#define PLIC_PRIORITY_PRIORITY8 (7UL) +#define PLIC_PRIORITY_PRIORITY9 (8UL) +#define PLIC_PRIORITY_PRIORITY10 (9UL) +#define PLIC_PRIORITY_PRIORITY11 (10UL) +#define PLIC_PRIORITY_PRIORITY12 (11UL) +#define PLIC_PRIORITY_PRIORITY13 (12UL) +#define PLIC_PRIORITY_PRIORITY14 (13UL) +#define PLIC_PRIORITY_PRIORITY15 (14UL) +#define PLIC_PRIORITY_PRIORITY16 (15UL) +#define PLIC_PRIORITY_PRIORITY17 (16UL) +#define PLIC_PRIORITY_PRIORITY18 (17UL) +#define PLIC_PRIORITY_PRIORITY19 (18UL) +#define PLIC_PRIORITY_PRIORITY20 (19UL) +#define PLIC_PRIORITY_PRIORITY21 (20UL) +#define PLIC_PRIORITY_PRIORITY22 (21UL) +#define PLIC_PRIORITY_PRIORITY23 (22UL) +#define PLIC_PRIORITY_PRIORITY24 (23UL) +#define PLIC_PRIORITY_PRIORITY25 (24UL) +#define PLIC_PRIORITY_PRIORITY26 (25UL) +#define PLIC_PRIORITY_PRIORITY27 (26UL) +#define PLIC_PRIORITY_PRIORITY28 (27UL) +#define PLIC_PRIORITY_PRIORITY29 (28UL) +#define PLIC_PRIORITY_PRIORITY30 (29UL) +#define PLIC_PRIORITY_PRIORITY31 (30UL) +#define PLIC_PRIORITY_PRIORITY32 (31UL) +#define PLIC_PRIORITY_PRIORITY33 (32UL) +#define PLIC_PRIORITY_PRIORITY34 (33UL) +#define PLIC_PRIORITY_PRIORITY35 (34UL) +#define PLIC_PRIORITY_PRIORITY36 (35UL) +#define PLIC_PRIORITY_PRIORITY37 (36UL) +#define PLIC_PRIORITY_PRIORITY38 (37UL) +#define PLIC_PRIORITY_PRIORITY39 (38UL) +#define PLIC_PRIORITY_PRIORITY40 (39UL) +#define PLIC_PRIORITY_PRIORITY41 (40UL) +#define PLIC_PRIORITY_PRIORITY42 (41UL) +#define PLIC_PRIORITY_PRIORITY43 (42UL) +#define PLIC_PRIORITY_PRIORITY44 (43UL) +#define PLIC_PRIORITY_PRIORITY45 (44UL) +#define PLIC_PRIORITY_PRIORITY46 (45UL) +#define PLIC_PRIORITY_PRIORITY47 (46UL) +#define PLIC_PRIORITY_PRIORITY48 (47UL) +#define PLIC_PRIORITY_PRIORITY49 (48UL) +#define PLIC_PRIORITY_PRIORITY50 (49UL) +#define PLIC_PRIORITY_PRIORITY51 (50UL) +#define PLIC_PRIORITY_PRIORITY52 (51UL) +#define PLIC_PRIORITY_PRIORITY53 (52UL) +#define PLIC_PRIORITY_PRIORITY54 (53UL) +#define PLIC_PRIORITY_PRIORITY55 (54UL) +#define PLIC_PRIORITY_PRIORITY56 (55UL) +#define PLIC_PRIORITY_PRIORITY57 (56UL) +#define PLIC_PRIORITY_PRIORITY58 (57UL) +#define PLIC_PRIORITY_PRIORITY59 (58UL) +#define PLIC_PRIORITY_PRIORITY60 (59UL) +#define PLIC_PRIORITY_PRIORITY61 (60UL) +#define PLIC_PRIORITY_PRIORITY62 (61UL) +#define PLIC_PRIORITY_PRIORITY63 (62UL) +#define PLIC_PRIORITY_PRIORITY64 (63UL) +#define PLIC_PRIORITY_PRIORITY65 (64UL) +#define PLIC_PRIORITY_PRIORITY66 (65UL) +#define PLIC_PRIORITY_PRIORITY67 (66UL) +#define PLIC_PRIORITY_PRIORITY68 (67UL) +#define PLIC_PRIORITY_PRIORITY69 (68UL) +#define PLIC_PRIORITY_PRIORITY70 (69UL) +#define PLIC_PRIORITY_PRIORITY71 (70UL) +#define PLIC_PRIORITY_PRIORITY72 (71UL) +#define PLIC_PRIORITY_PRIORITY73 (72UL) +#define PLIC_PRIORITY_PRIORITY74 (73UL) +#define PLIC_PRIORITY_PRIORITY75 (74UL) +#define PLIC_PRIORITY_PRIORITY76 (75UL) +#define PLIC_PRIORITY_PRIORITY77 (76UL) +#define PLIC_PRIORITY_PRIORITY78 (77UL) +#define PLIC_PRIORITY_PRIORITY79 (78UL) +#define PLIC_PRIORITY_PRIORITY80 (79UL) +#define PLIC_PRIORITY_PRIORITY81 (80UL) +#define PLIC_PRIORITY_PRIORITY82 (81UL) +#define PLIC_PRIORITY_PRIORITY83 (82UL) +#define PLIC_PRIORITY_PRIORITY84 (83UL) +#define PLIC_PRIORITY_PRIORITY85 (84UL) +#define PLIC_PRIORITY_PRIORITY86 (85UL) +#define PLIC_PRIORITY_PRIORITY87 (86UL) +#define PLIC_PRIORITY_PRIORITY88 (87UL) +#define PLIC_PRIORITY_PRIORITY89 (88UL) +#define PLIC_PRIORITY_PRIORITY90 (89UL) +#define PLIC_PRIORITY_PRIORITY91 (90UL) +#define PLIC_PRIORITY_PRIORITY92 (91UL) +#define PLIC_PRIORITY_PRIORITY93 (92UL) +#define PLIC_PRIORITY_PRIORITY94 (93UL) +#define PLIC_PRIORITY_PRIORITY95 (94UL) +#define PLIC_PRIORITY_PRIORITY96 (95UL) +#define PLIC_PRIORITY_PRIORITY97 (96UL) +#define PLIC_PRIORITY_PRIORITY98 (97UL) +#define PLIC_PRIORITY_PRIORITY99 (98UL) +#define PLIC_PRIORITY_PRIORITY100 (99UL) +#define PLIC_PRIORITY_PRIORITY101 (100UL) +#define PLIC_PRIORITY_PRIORITY102 (101UL) +#define PLIC_PRIORITY_PRIORITY103 (102UL) +#define PLIC_PRIORITY_PRIORITY104 (103UL) +#define PLIC_PRIORITY_PRIORITY105 (104UL) +#define PLIC_PRIORITY_PRIORITY106 (105UL) +#define PLIC_PRIORITY_PRIORITY107 (106UL) +#define PLIC_PRIORITY_PRIORITY108 (107UL) +#define PLIC_PRIORITY_PRIORITY109 (108UL) +#define PLIC_PRIORITY_PRIORITY110 (109UL) +#define PLIC_PRIORITY_PRIORITY111 (110UL) +#define PLIC_PRIORITY_PRIORITY112 (111UL) +#define PLIC_PRIORITY_PRIORITY113 (112UL) +#define PLIC_PRIORITY_PRIORITY114 (113UL) +#define PLIC_PRIORITY_PRIORITY115 (114UL) +#define PLIC_PRIORITY_PRIORITY116 (115UL) +#define PLIC_PRIORITY_PRIORITY117 (116UL) +#define PLIC_PRIORITY_PRIORITY118 (117UL) +#define PLIC_PRIORITY_PRIORITY119 (118UL) +#define PLIC_PRIORITY_PRIORITY120 (119UL) +#define PLIC_PRIORITY_PRIORITY121 (120UL) +#define PLIC_PRIORITY_PRIORITY122 (121UL) +#define PLIC_PRIORITY_PRIORITY123 (122UL) +#define PLIC_PRIORITY_PRIORITY124 (123UL) +#define PLIC_PRIORITY_PRIORITY125 (124UL) +#define PLIC_PRIORITY_PRIORITY126 (125UL) +#define PLIC_PRIORITY_PRIORITY127 (126UL) + +/* PENDING register group index macro definition */ +#define PLIC_PENDING_PENDING0 (0UL) +#define PLIC_PENDING_PENDING1 (1UL) +#define PLIC_PENDING_PENDING2 (2UL) +#define PLIC_PENDING_PENDING3 (3UL) + +/* TRIGGER register group index macro definition */ +#define PLIC_TRIGGER_TRIGGER0 (0UL) +#define PLIC_TRIGGER_TRIGGER1 (1UL) +#define PLIC_TRIGGER_TRIGGER2 (2UL) +#define PLIC_TRIGGER_TRIGGER3 (3UL) + +/* INTEN register group index macro definition */ +#define PLIC_TARGETINT_INTEN_INTEN0 (0UL) +#define PLIC_TARGETINT_INTEN_INTEN1 (1UL) +#define PLIC_TARGETINT_INTEN_INTEN2 (2UL) +#define PLIC_TARGETINT_INTEN_INTEN3 (3UL) + +/* TARGETINT register group index macro definition */ +#define PLIC_TARGETINT_TARGET0 (0UL) +#define PLIC_TARGETINT_TARGET1 (1UL) + +/* TARGETCONFIG register group index macro definition */ +#define PLIC_TARGETCONFIG_TARGET0 (0UL) +#define PLIC_TARGETCONFIG_TARGET1 (1UL) + + +#endif /* HPM_PLIC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_sw_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_sw_regs.h new file mode 100644 index 0000000000..dd6d68646c --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plic_sw_regs.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PLIC_SW_H +#define HPM_PLIC_SW_H + +typedef struct { + __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */ + __RW uint32_t PENDING; /* 0x1000: Pending status */ + __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */ + __RW uint32_t INTEN; /* 0x2000: Interrupt enable */ + __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */ + __RW uint32_t CLAIM; /* 0x200004: Claim and complete. */ +} PLIC_SW_Type; + + +/* Bitfield definition for register: PENDING */ +/* + * INTERRUPT (RW) + * + * writing 1 to trigger software interrupt + */ +#define PLIC_SW_PENDING_INTERRUPT_MASK (0x2U) +#define PLIC_SW_PENDING_INTERRUPT_SHIFT (1U) +#define PLIC_SW_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_PENDING_INTERRUPT_SHIFT) & PLIC_SW_PENDING_INTERRUPT_MASK) +#define PLIC_SW_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_PENDING_INTERRUPT_MASK) >> PLIC_SW_PENDING_INTERRUPT_SHIFT) + +/* Bitfield definition for register: INTEN */ +/* + * INTERRUPT (RW) + * + * enable software interrupt + */ +#define PLIC_SW_INTEN_INTERRUPT_MASK (0x1U) +#define PLIC_SW_INTEN_INTERRUPT_SHIFT (0U) +#define PLIC_SW_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_INTEN_INTERRUPT_SHIFT) & PLIC_SW_INTEN_INTERRUPT_MASK) +#define PLIC_SW_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_INTEN_INTERRUPT_MASK) >> PLIC_SW_INTEN_INTERRUPT_SHIFT) + +/* Bitfield definition for register: CLAIM */ +/* + * INTERRUPT_ID (RW) + * + * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + */ +#define PLIC_SW_CLAIM_INTERRUPT_ID_MASK (0x1U) +#define PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT (0U) +#define PLIC_SW_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) +#define PLIC_SW_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) >> PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) + + + + +#endif /* HPM_PLIC_SW_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctl_regs.h new file mode 100644 index 0000000000..c3bf35c7d4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctl_regs.h @@ -0,0 +1,446 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PLLCTL_H +#define HPM_PLLCTL_H + +typedef struct { + __RW uint32_t XTAL; /* 0x0: Crystal control and status */ + __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */ + struct { + __RW uint32_t CFG0; /* 0x80: PLLx config0 */ + __RW uint32_t CFG1; /* 0x84: PLLx config1 */ + __RW uint32_t CFG2; /* 0x88: PLLx config2 */ + __RW uint32_t FREQ; /* 0x8C: PLLx frac mode frequency adjust */ + __RW uint32_t LOCK; /* 0x90: PLLx lock control */ + __R uint8_t RESERVED0[12]; /* 0x94 - 0x9F: Reserved */ + __R uint32_t STATUS; /* 0xA0: PLLx status */ + __R uint8_t RESERVED1[28]; /* 0xA4 - 0xBF: Reserved */ + __RW uint32_t DIV0; /* 0xC0: PLLx divider0 control */ + __RW uint32_t DIV1; /* 0xC4: PLLx divider1 control */ + __R uint8_t RESERVED2[56]; /* 0xC8 - 0xFF: Reserved */ + } PLL[5]; +} PLLCTL_Type; + + +/* Bitfield definition for register: XTAL */ +/* + * RESPONSE (RO) + * + * Crystal oscillator status + * 0: Oscillator is not stable + * 1: Oscillator is stable for use + */ +#define PLLCTL_XTAL_RESPONSE_MASK (0x20000000UL) +#define PLLCTL_XTAL_RESPONSE_SHIFT (29U) +#define PLLCTL_XTAL_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_XTAL_RESPONSE_MASK) >> PLLCTL_XTAL_RESPONSE_SHIFT) + +/* + * ENABLE (RO) + * + * Crystal oscillator enable status + * 0: Oscillator is off + * 1: Oscillator is on + */ +#define PLLCTL_XTAL_ENABLE_MASK (0x10000000UL) +#define PLLCTL_XTAL_ENABLE_SHIFT (28U) +#define PLLCTL_XTAL_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_XTAL_ENABLE_MASK) >> PLLCTL_XTAL_ENABLE_SHIFT) + +/* + * RAMP_TIME (RW) + * + * Rampup time of XTAL oscillator in cycles of IRC24M clock + * 0: 0 cycle + * 1: 1 cycle + * 2: 2 cycle + * 1048575: 1048575 cycles + */ +#define PLLCTL_XTAL_RAMP_TIME_MASK (0xFFFFFUL) +#define PLLCTL_XTAL_RAMP_TIME_SHIFT (0U) +#define PLLCTL_XTAL_RAMP_TIME_SET(x) (((uint32_t)(x) << PLLCTL_XTAL_RAMP_TIME_SHIFT) & PLLCTL_XTAL_RAMP_TIME_MASK) +#define PLLCTL_XTAL_RAMP_TIME_GET(x) (((uint32_t)(x) & PLLCTL_XTAL_RAMP_TIME_MASK) >> PLLCTL_XTAL_RAMP_TIME_SHIFT) + +/* Bitfield definition for register of struct array PLL: CFG0 */ +/* + * SS_RSTPTR (RW) + * + * reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb + */ +#define PLLCTL_PLL_CFG0_SS_RSTPTR_MASK (0x80000000UL) +#define PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT (31U) +#define PLLCTL_PLL_CFG0_SS_RSTPTR_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK) +#define PLLCTL_PLL_CFG0_SS_RSTPTR_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK) >> PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT) + +/* + * REFDIV (RW) + * + * refclk diverder, lock when lock_en[24]&~pll_ana_pd + */ +#define PLLCTL_PLL_CFG0_REFDIV_MASK (0x3F000000UL) +#define PLLCTL_PLL_CFG0_REFDIV_SHIFT (24U) +#define PLLCTL_PLL_CFG0_REFDIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_REFDIV_SHIFT) & PLLCTL_PLL_CFG0_REFDIV_MASK) +#define PLLCTL_PLL_CFG0_REFDIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_REFDIV_MASK) >> PLLCTL_PLL_CFG0_REFDIV_SHIFT) + +/* + * POSTDIV1 (RW) + * + * lock when lock_en[20]&~pll_ana_pd + */ +#define PLLCTL_PLL_CFG0_POSTDIV1_MASK (0x700000UL) +#define PLLCTL_PLL_CFG0_POSTDIV1_SHIFT (20U) +#define PLLCTL_PLL_CFG0_POSTDIV1_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_POSTDIV1_SHIFT) & PLLCTL_PLL_CFG0_POSTDIV1_MASK) +#define PLLCTL_PLL_CFG0_POSTDIV1_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_POSTDIV1_MASK) >> PLLCTL_PLL_CFG0_POSTDIV1_SHIFT) + +/* + * SS_SPREAD (RW) + * + * lock when lock_en[14]&~pll_ana_pd + */ +#define PLLCTL_PLL_CFG0_SS_SPREAD_MASK (0x7C000UL) +#define PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT (14U) +#define PLLCTL_PLL_CFG0_SS_SPREAD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK) +#define PLLCTL_PLL_CFG0_SS_SPREAD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT) + +/* + * SS_DIVVAL (RW) + * + * sscg divval, lock when lock_en[8]&~pll_ana_pd + */ +#define PLLCTL_PLL_CFG0_SS_DIVVAL_MASK (0x3F00U) +#define PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT (8U) +#define PLLCTL_PLL_CFG0_SS_DIVVAL_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) +#define PLLCTL_PLL_CFG0_SS_DIVVAL_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) + +/* + * SS_DOWNSPREAD (RW) + * + * Downspread control + * 1’b0 –> Center-Spread + * 1’b1 –> Downspread + */ +#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK (0x80U) +#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT (7U) +#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK) +#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT) + +/* + * SS_RESET (RW) + * + */ +#define PLLCTL_PLL_CFG0_SS_RESET_MASK (0x40U) +#define PLLCTL_PLL_CFG0_SS_RESET_SHIFT (6U) +#define PLLCTL_PLL_CFG0_SS_RESET_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RESET_SHIFT) & PLLCTL_PLL_CFG0_SS_RESET_MASK) +#define PLLCTL_PLL_CFG0_SS_RESET_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RESET_MASK) >> PLLCTL_PLL_CFG0_SS_RESET_SHIFT) + +/* + * SS_DISABLE_SSCG (RW) + * + */ +#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK (0x20U) +#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT (5U) +#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK) +#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK) >> PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT) + +/* + * DSMPD (RW) + * + * 1: int mode; 0: frac mode + */ +#define PLLCTL_PLL_CFG0_DSMPD_MASK (0x8U) +#define PLLCTL_PLL_CFG0_DSMPD_SHIFT (3U) +#define PLLCTL_PLL_CFG0_DSMPD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_DSMPD_SHIFT) & PLLCTL_PLL_CFG0_DSMPD_MASK) +#define PLLCTL_PLL_CFG0_DSMPD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_DSMPD_MASK) >> PLLCTL_PLL_CFG0_DSMPD_SHIFT) + +/* Bitfield definition for register of struct array PLL: CFG1 */ +/* + * PLLCTRL_HW_EN (RW) + * + * 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value + * 0: full software control PLL settings + */ +#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK (0x80000000UL) +#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT (31U) +#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) +#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) >> PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT) + +/* + * CLKEN_SW (RW) + * + * the clock enable used to gate pll output, should be set after lock, and clear before power down pll. + * pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; + */ +#define PLLCTL_PLL_CFG1_CLKEN_SW_MASK (0x4000000UL) +#define PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT (26U) +#define PLLCTL_PLL_CFG1_CLKEN_SW_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK) +#define PLLCTL_PLL_CFG1_CLKEN_SW_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK) >> PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT) + +/* + * PLLPD_SW (RW) + * + * pll power down. + * pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; + * pll_pd_soc is just delay of soc enable, for soc to control pll on/off; + * pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence + */ +#define PLLCTL_PLL_CFG1_PLLPD_SW_MASK (0x2000000UL) +#define PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT (25U) +#define PLLCTL_PLL_CFG1_PLLPD_SW_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) +#define PLLCTL_PLL_CFG1_PLLPD_SW_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) >> PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT) + +/* + * LOCK_CNT_CFG (RW) + * + * used to wait lock if set larger than lock time; + * default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 + */ +#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK (0x8000U) +#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT (15U) +#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK) +#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK) >> PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT) + +/* Bitfield definition for register of struct array PLL: CFG2 */ +/* + * FBDIV_INT (RW) + * + * fbdiv used in int mode + */ +#define PLLCTL_PLL_CFG2_FBDIV_INT_MASK (0xFFFU) +#define PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT (0U) +#define PLLCTL_PLL_CFG2_FBDIV_INT_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK) +#define PLLCTL_PLL_CFG2_FBDIV_INT_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK) >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT) + +/* Bitfield definition for register of struct array PLL: FREQ */ +/* + * FRAC (RW) + * + * PLL output frequency is : + * Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 + * for default refdiv=1 and postdiv1=1, 24MHz refclk + * Fout is 24*fbdiv in int mode + * if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) + * Fout is 24*fbdiv in int mode + * if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) + */ +#define PLLCTL_PLL_FREQ_FRAC_MASK (0xFFFFFF00UL) +#define PLLCTL_PLL_FREQ_FRAC_SHIFT (8U) +#define PLLCTL_PLL_FREQ_FRAC_SET(x) (((uint32_t)(x) << PLLCTL_PLL_FREQ_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FRAC_MASK) +#define PLLCTL_PLL_FREQ_FRAC_GET(x) (((uint32_t)(x) & PLLCTL_PLL_FREQ_FRAC_MASK) >> PLLCTL_PLL_FREQ_FRAC_SHIFT) + +/* + * FBDIV_FRAC (RW) + * + * fbdiv used in frac mode + */ +#define PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK (0xFFU) +#define PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT (0U) +#define PLLCTL_PLL_FREQ_FBDIV_FRAC_SET(x) (((uint32_t)(x) << PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK) +#define PLLCTL_PLL_FREQ_FBDIV_FRAC_GET(x) (((uint32_t)(x) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK) >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT) + +/* Bitfield definition for register of struct array PLL: LOCK */ +/* + * LOCK_SS_RSTPTR (RW) + * + * lock bit of field ss_rstptr + * 0: field is open foe software to change + * 1: field is locked, not changeable + */ +#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK (0x80000000UL) +#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT (31U) +#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK) +#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT) + +/* + * LOCK_REFDIV (RW) + * + * lock bit of field refdiv + * 0: field is open foe software to change + * 1: field is locked, not changeable + */ +#define PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK (0x1000000UL) +#define PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT (24U) +#define PLLCTL_PLL_LOCK_LOCK_REFDIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK) +#define PLLCTL_PLL_LOCK_LOCK_REFDIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK) >> PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT) + +/* + * LOCK_POSTDIV1 (RW) + * + * lock bit of field postdiv1 + * 0: field is open foe software to change + * 1: field is locked, not changeable + */ +#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK (0x100000UL) +#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT (20U) +#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK) +#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK) >> PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT) + +/* + * LOCK_SS_SPEAD (RW) + * + * lock bit of field ss_spead + * 0: field is open foe software to change + * 1: field is locked, not changeable + */ +#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK (0x4000U) +#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT (14U) +#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK) +#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT) + +/* + * LOCK_SS_DIVVAL (RW) + * + * lock bit of field ss_divval + * 0: field is open foe software to change + * 1: field is locked, not changeable + */ +#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK (0x100U) +#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT (8U) +#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) +#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT) + +/* Bitfield definition for register of struct array PLL: STATUS */ +/* + * ENABLE (RO) + * + * enable from SYSCTL block + */ +#define PLLCTL_PLL_STATUS_ENABLE_MASK (0x8000000UL) +#define PLLCTL_PLL_STATUS_ENABLE_SHIFT (27U) +#define PLLCTL_PLL_STATUS_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_ENABLE_MASK) >> PLLCTL_PLL_STATUS_ENABLE_SHIFT) + +/* + * RESPONSE (RO) + * + * response to SYSCTL, PLL is power down when both enable and response are 0. + */ +#define PLLCTL_PLL_STATUS_RESPONSE_MASK (0x4U) +#define PLLCTL_PLL_STATUS_RESPONSE_SHIFT (2U) +#define PLLCTL_PLL_STATUS_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_RESPONSE_MASK) >> PLLCTL_PLL_STATUS_RESPONSE_SHIFT) + +/* + * PLL_LOCK_COMB (RO) + * + */ +#define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK (0x2U) +#define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT (1U) +#define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT) + +/* + * PLL_LOCK_SYNC (RO) + * + */ +#define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK (0x1U) +#define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT (0U) +#define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT) + +/* Bitfield definition for register of struct array PLL: DIV0 */ +/* + * BUSY (RO) + * + * Busy flag + * 0: divider is working + * 1: divider is changing status + */ +#define PLLCTL_PLL_DIV0_BUSY_MASK (0x80000000UL) +#define PLLCTL_PLL_DIV0_BUSY_SHIFT (31U) +#define PLLCTL_PLL_DIV0_BUSY_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_BUSY_MASK) >> PLLCTL_PLL_DIV0_BUSY_SHIFT) + +/* + * RESPONSE (RO) + * + * Crystal oscillator status + * 0: Oscillator is not stable + * 1: Oscillator is stable for use + */ +#define PLLCTL_PLL_DIV0_RESPONSE_MASK (0x20000000UL) +#define PLLCTL_PLL_DIV0_RESPONSE_SHIFT (29U) +#define PLLCTL_PLL_DIV0_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_RESPONSE_MASK) >> PLLCTL_PLL_DIV0_RESPONSE_SHIFT) + +/* + * ENABLE (RO) + * + * Crystal oscillator enable status + * 0: Oscillator is off + * 1: Oscillator is on + */ +#define PLLCTL_PLL_DIV0_ENABLE_MASK (0x10000000UL) +#define PLLCTL_PLL_DIV0_ENABLE_SHIFT (28U) +#define PLLCTL_PLL_DIV0_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_ENABLE_MASK) >> PLLCTL_PLL_DIV0_ENABLE_SHIFT) + +/* + * DIV (RW) + * + * Divider + * 0: divide by 1 + * 1: divide by2 + * . . . + * 255: divide by 256 + */ +#define PLLCTL_PLL_DIV0_DIV_MASK (0xFFU) +#define PLLCTL_PLL_DIV0_DIV_SHIFT (0U) +#define PLLCTL_PLL_DIV0_DIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_DIV0_DIV_SHIFT) & PLLCTL_PLL_DIV0_DIV_MASK) +#define PLLCTL_PLL_DIV0_DIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_DIV_MASK) >> PLLCTL_PLL_DIV0_DIV_SHIFT) + +/* Bitfield definition for register of struct array PLL: DIV1 */ +/* + * BUSY (RO) + * + * Busy flag + * 0: divider is working + * 1: divider is changing status + */ +#define PLLCTL_PLL_DIV1_BUSY_MASK (0x80000000UL) +#define PLLCTL_PLL_DIV1_BUSY_SHIFT (31U) +#define PLLCTL_PLL_DIV1_BUSY_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_BUSY_MASK) >> PLLCTL_PLL_DIV1_BUSY_SHIFT) + +/* + * RESPONSE (RO) + * + * Crystal oscillator status + * 0: Oscillator is not stable + * 1: Oscillator is stable for use + */ +#define PLLCTL_PLL_DIV1_RESPONSE_MASK (0x20000000UL) +#define PLLCTL_PLL_DIV1_RESPONSE_SHIFT (29U) +#define PLLCTL_PLL_DIV1_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_RESPONSE_MASK) >> PLLCTL_PLL_DIV1_RESPONSE_SHIFT) + +/* + * ENABLE (RO) + * + * Crystal oscillator enable status + * 0: Oscillator is off + * 1: Oscillator is on + */ +#define PLLCTL_PLL_DIV1_ENABLE_MASK (0x10000000UL) +#define PLLCTL_PLL_DIV1_ENABLE_SHIFT (28U) +#define PLLCTL_PLL_DIV1_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_ENABLE_MASK) >> PLLCTL_PLL_DIV1_ENABLE_SHIFT) + +/* + * DIV (RW) + * + * Divider + * 0: divide by 1 + * 1: divide by2 + * . . . + * 255: divide by 256 + */ +#define PLLCTL_PLL_DIV1_DIV_MASK (0xFFU) +#define PLLCTL_PLL_DIV1_DIV_SHIFT (0U) +#define PLLCTL_PLL_DIV1_DIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_DIV1_DIV_SHIFT) & PLLCTL_PLL_DIV1_DIV_MASK) +#define PLLCTL_PLL_DIV1_DIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_DIV_MASK) >> PLLCTL_PLL_DIV1_DIV_SHIFT) + + + +/* PLL register group index macro definition */ +#define PLLCTL_PLL_PLL0 (0UL) +#define PLLCTL_PLL_PLL1 (1UL) +#define PLLCTL_PLL_PLL2 (2UL) +#define PLLCTL_PLL_PLL3 (3UL) +#define PLLCTL_PLL_PLL4 (4UL) + + +#endif /* HPM_PLLCTL_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h new file mode 100644 index 0000000000..17de80ac8f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pllctlv2_regs.h @@ -0,0 +1,306 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PLLCTLV2_H +#define HPM_PLLCTLV2_H + +typedef struct { + __RW uint32_t XTAL; /* 0x0: OSC configuration */ + __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */ + struct { + __RW uint32_t MFI; /* 0x80: PLL0 multiple register */ + __RW uint32_t MFN; /* 0x84: PLL0 fraction numerator register */ + __RW uint32_t MFD; /* 0x88: PLL0 fraction demoninator register */ + __RW uint32_t SS_STEP; /* 0x8C: PLL0 spread spectrum step register */ + __RW uint32_t SS_STOP; /* 0x90: PLL0 spread spectrum stop register */ + __RW uint32_t CONFIG; /* 0x94: PLL0 confguration register */ + __RW uint32_t LOCKTIME; /* 0x98: PLL0 lock time register */ + __RW uint32_t STEPTIME; /* 0x9C: PLL0 step time register */ + __RW uint32_t ADVANCED; /* 0xA0: PLL0 advance configuration register */ + __R uint8_t RESERVED0[28]; /* 0xA4 - 0xBF: Reserved */ + __RW uint32_t DIV[3]; /* 0xC0 - 0xC8: PLL0 divider output 0 configuration register */ + __R uint8_t RESERVED1[52]; /* 0xCC - 0xFF: Reserved */ + } PLL[3]; +} PLLCTLV2_Type; + + +/* Bitfield definition for register: XTAL */ +/* + * BUSY (RO) + * + * Busy flag + * 0: Oscillator is working or shutdown + * 1: Oscillator is changing status + */ +#define PLLCTLV2_XTAL_BUSY_MASK (0x80000000UL) +#define PLLCTLV2_XTAL_BUSY_SHIFT (31U) +#define PLLCTLV2_XTAL_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_BUSY_MASK) >> PLLCTLV2_XTAL_BUSY_SHIFT) + +/* + * RESPONSE (RO) + * + * Crystal oscillator status + * 0: Oscillator is not stable + * 1: Oscillator is stable for use + */ +#define PLLCTLV2_XTAL_RESPONSE_MASK (0x20000000UL) +#define PLLCTLV2_XTAL_RESPONSE_SHIFT (29U) +#define PLLCTLV2_XTAL_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RESPONSE_MASK) >> PLLCTLV2_XTAL_RESPONSE_SHIFT) + +/* + * ENABLE (RO) + * + * Crystal oscillator enable status + * 0: Oscillator is off + * 1: Oscillator is on + */ +#define PLLCTLV2_XTAL_ENABLE_MASK (0x10000000UL) +#define PLLCTLV2_XTAL_ENABLE_SHIFT (28U) +#define PLLCTLV2_XTAL_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_ENABLE_MASK) >> PLLCTLV2_XTAL_ENABLE_SHIFT) + +/* + * RAMP_TIME (RW) + * + * Rampup time of XTAL oscillator in cycles of RC24M clock + * 0: 0 cycle + * 1: 1 cycle + * 2: 2 cycle + * 1048575: 1048575 cycles + */ +#define PLLCTLV2_XTAL_RAMP_TIME_MASK (0xFFFFFUL) +#define PLLCTLV2_XTAL_RAMP_TIME_SHIFT (0U) +#define PLLCTLV2_XTAL_RAMP_TIME_SET(x) (((uint32_t)(x) << PLLCTLV2_XTAL_RAMP_TIME_SHIFT) & PLLCTLV2_XTAL_RAMP_TIME_MASK) +#define PLLCTLV2_XTAL_RAMP_TIME_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RAMP_TIME_MASK) >> PLLCTLV2_XTAL_RAMP_TIME_SHIFT) + +/* Bitfield definition for register of struct array PLL: MFI */ +/* + * BUSY (RO) + * + * Busy flag + * 0: PLL is stable or shutdown + * 1: PLL is changing status + */ +#define PLLCTLV2_PLL_MFI_BUSY_MASK (0x80000000UL) +#define PLLCTLV2_PLL_MFI_BUSY_SHIFT (31U) +#define PLLCTLV2_PLL_MFI_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_BUSY_MASK) >> PLLCTLV2_PLL_MFI_BUSY_SHIFT) + +/* + * RESPONSE (RO) + * + * PLL status + * 0: PLL is not stable + * 1: PLL is stable for use + */ +#define PLLCTLV2_PLL_MFI_RESPONSE_MASK (0x20000000UL) +#define PLLCTLV2_PLL_MFI_RESPONSE_SHIFT (29U) +#define PLLCTLV2_PLL_MFI_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_RESPONSE_MASK) >> PLLCTLV2_PLL_MFI_RESPONSE_SHIFT) + +/* + * ENABLE (RO) + * + * PLL enable status + * 0: PLL is off + * 1: PLL is on + */ +#define PLLCTLV2_PLL_MFI_ENABLE_MASK (0x10000000UL) +#define PLLCTLV2_PLL_MFI_ENABLE_SHIFT (28U) +#define PLLCTLV2_PLL_MFI_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_ENABLE_MASK) >> PLLCTLV2_PLL_MFI_ENABLE_SHIFT) + +/* + * MFI (RW) + * + * loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) + * 0-15: invalid + * 16: divide by 16 + * 17: divide by17 + * . . . + * 42: divide by 42 + * 43~:invalid + */ +#define PLLCTLV2_PLL_MFI_MFI_MASK (0x7FU) +#define PLLCTLV2_PLL_MFI_MFI_SHIFT (0U) +#define PLLCTLV2_PLL_MFI_MFI_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFI_MFI_SHIFT) & PLLCTLV2_PLL_MFI_MFI_MASK) +#define PLLCTLV2_PLL_MFI_MFI_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_MFI_MASK) >> PLLCTLV2_PLL_MFI_MFI_SHIFT) + +/* Bitfield definition for register of struct array PLL: MFN */ +/* + * MFN (RW) + * + * Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + */ +#define PLLCTLV2_PLL_MFN_MFN_MASK (0x3FFFFFFFUL) +#define PLLCTLV2_PLL_MFN_MFN_SHIFT (0U) +#define PLLCTLV2_PLL_MFN_MFN_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT) & PLLCTLV2_PLL_MFN_MFN_MASK) +#define PLLCTLV2_PLL_MFN_MFN_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFN_MFN_MASK) >> PLLCTLV2_PLL_MFN_MFN_SHIFT) + +/* Bitfield definition for register of struct array PLL: MFD */ +/* + * MFD (RW) + * + * Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + */ +#define PLLCTLV2_PLL_MFD_MFD_MASK (0x3FFFFFFFUL) +#define PLLCTLV2_PLL_MFD_MFD_SHIFT (0U) +#define PLLCTLV2_PLL_MFD_MFD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFD_MFD_SHIFT) & PLLCTLV2_PLL_MFD_MFD_MASK) +#define PLLCTLV2_PLL_MFD_MFD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFD_MFD_MASK) >> PLLCTLV2_PLL_MFD_MFD_SHIFT) + +/* Bitfield definition for register of struct array PLL: SS_STEP */ +/* + * STEP (RW) + * + * Step of spread spectrum modulator. + * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + */ +#define PLLCTLV2_PLL_SS_STEP_STEP_MASK (0x3FFFFFFFUL) +#define PLLCTLV2_PLL_SS_STEP_STEP_SHIFT (0U) +#define PLLCTLV2_PLL_SS_STEP_STEP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) +#define PLLCTLV2_PLL_SS_STEP_STEP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) >> PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) + +/* Bitfield definition for register of struct array PLL: SS_STOP */ +/* + * STOP (RW) + * + * Stop point of spread spectrum modulator + * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + */ +#define PLLCTLV2_PLL_SS_STOP_STOP_MASK (0x3FFFFFFFUL) +#define PLLCTLV2_PLL_SS_STOP_STOP_SHIFT (0U) +#define PLLCTLV2_PLL_SS_STOP_STOP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) +#define PLLCTLV2_PLL_SS_STOP_STOP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) >> PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) + +/* Bitfield definition for register of struct array PLL: CONFIG */ +/* + * SPREAD (RW) + * + * Enable spread spectrum function. This field supports changing during PLL running. + */ +#define PLLCTLV2_PLL_CONFIG_SPREAD_MASK (0x100U) +#define PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT (8U) +#define PLLCTLV2_PLL_CONFIG_SPREAD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) +#define PLLCTLV2_PLL_CONFIG_SPREAD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) >> PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) + +/* + * REFSEL (RW) + * + * Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. + * 0: XTAL24M + * 1: IRC24M + */ +#define PLLCTLV2_PLL_CONFIG_REFSEL_MASK (0x1U) +#define PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT (0U) +#define PLLCTLV2_PLL_CONFIG_REFSEL_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) +#define PLLCTLV2_PLL_CONFIG_REFSEL_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) >> PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) + +/* Bitfield definition for register of struct array PLL: LOCKTIME */ +/* + * LOCKTIME (RW) + * + * Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + */ +#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK (0xFFFFU) +#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT (0U) +#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) +#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) >> PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) + +/* Bitfield definition for register of struct array PLL: STEPTIME */ +/* + * STEPTIME (RW) + * + * Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + */ +#define PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK (0xFFFFU) +#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT (0U) +#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) +#define PLLCTLV2_PLL_STEPTIME_STEPTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) >> PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) + +/* Bitfield definition for register of struct array PLL: ADVANCED */ +/* + * SLOW (RW) + * + * Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. + * 0: fast lock enabled, lock time is 100us + * 1: fast lock disabled, lock time is 400us + */ +#define PLLCTLV2_PLL_ADVANCED_SLOW_MASK (0x10000000UL) +#define PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT (28U) +#define PLLCTLV2_PLL_ADVANCED_SLOW_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) +#define PLLCTLV2_PLL_ADVANCED_SLOW_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) >> PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) + +/* + * DITHER (RW) + * + * Enable dither function + */ +#define PLLCTLV2_PLL_ADVANCED_DITHER_MASK (0x1000000UL) +#define PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT (24U) +#define PLLCTLV2_PLL_ADVANCED_DITHER_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) +#define PLLCTLV2_PLL_ADVANCED_DITHER_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) >> PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) + +/* Bitfield definition for register of struct array PLL: DIV0 */ +/* + * BUSY (RO) + * + * Busy flag + * 0: divider is working + * 1: divider is changing status + */ +#define PLLCTLV2_DIV_BUSY_MASK (0x80000000UL) +#define PLLCTLV2_DIV_BUSY_SHIFT (31U) +#define PLLCTLV2_DIV_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_DIV_BUSY_MASK) >> PLLCTLV2_DIV_BUSY_SHIFT) + +/* + * RESPONSE (RO) + * + * Divider response status + * 0: Divider is not stable + * 1: Divider is stable for use + */ +#define PLLCTLV2_DIV_RESPONSE_MASK (0x20000000UL) +#define PLLCTLV2_DIV_RESPONSE_SHIFT (29U) +#define PLLCTLV2_DIV_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_DIV_RESPONSE_MASK) >> PLLCTLV2_DIV_RESPONSE_SHIFT) + +/* + * ENABLE (RO) + * + * Divider enable status + * 0: Divider is off + * 1: Divider is on + */ +#define PLLCTLV2_DIV_ENABLE_MASK (0x10000000UL) +#define PLLCTLV2_DIV_ENABLE_SHIFT (28U) +#define PLLCTLV2_DIV_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_DIV_ENABLE_MASK) >> PLLCTLV2_DIV_ENABLE_SHIFT) + +/* + * DIV (RW) + * + * Divider factor, divider factor is DIV/5 + 1 + * 0: divide by 1 + * 1: divide by 1.2 + * 2: divide by 1.4 + * . . . + * 63: divide by 13.6 + */ +#define PLLCTLV2_DIV_DIV_MASK (0x3FU) +#define PLLCTLV2_DIV_DIV_SHIFT (0U) +#define PLLCTLV2_DIV_DIV_SET(x) (((uint32_t)(x) << PLLCTLV2_DIV_DIV_SHIFT) & PLLCTLV2_DIV_DIV_MASK) +#define PLLCTLV2_DIV_DIV_GET(x) (((uint32_t)(x) & PLLCTLV2_DIV_DIV_MASK) >> PLLCTLV2_DIV_DIV_SHIFT) + + + +/* DIV register group index macro definition */ +#define PLLCTLV2_PLL_DIV_DIV0 (0UL) +#define PLLCTLV2_PLL_DIV_DIV1 (1UL) +#define PLLCTLV2_PLL_DIV_DIV2 (2UL) + +/* PLL register group index macro definition */ +#define PLLCTLV2_PLL_PLL0 (0UL) +#define PLLCTLV2_PLL_PLL1 (1UL) +#define PLLCTLV2_PLL_PLL2 (2UL) + + +#endif /* HPM_PLLCTLV2_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pmon_regs.h new file mode 100644 index 0000000000..055225a6db --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pmon_regs.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PMON_H +#define HPM_PMON_H + +typedef struct { + struct { + __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ + __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ + } MONITOR[4]; + __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ + __RW uint32_t IRQ_FLAG; /* 0x40: */ + __RW uint32_t IRQ_ENABLE; /* 0x44: */ +} PMON_Type; + + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * ACTIVE (RW) + * + * select glitch works in active mode or passve mode. + * 0: passive mode, depends on power glitch destory DFF value + * 1: active mode, check glitch by DFF chain + */ +#define PMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) +#define PMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) +#define PMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ACTIVE_SHIFT) & PMON_MONITOR_CONTROL_ACTIVE_MASK) +#define PMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ACTIVE_MASK) >> PMON_MONITOR_CONTROL_ACTIVE_SHIFT) + +/* + * ENABLE (RW) + * + * enable glitch detector + * 0: detector disabled + * 1: detector enabled + */ +#define PMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) +#define PMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) +#define PMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ENABLE_SHIFT) & PMON_MONITOR_CONTROL_ENABLE_MASK) +#define PMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ENABLE_MASK) >> PMON_MONITOR_CONTROL_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: STATUS */ +/* + * FLAG (RW) + * + * flag for glitch detected, write 1 to clear this flag + * 0: glitch not detected + * 1: glitch detected + */ +#define PMON_MONITOR_STATUS_FLAG_MASK (0x1U) +#define PMON_MONITOR_STATUS_FLAG_SHIFT (0U) +#define PMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << PMON_MONITOR_STATUS_FLAG_SHIFT) & PMON_MONITOR_STATUS_FLAG_MASK) +#define PMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & PMON_MONITOR_STATUS_FLAG_MASK) >> PMON_MONITOR_STATUS_FLAG_SHIFT) + +/* Bitfield definition for register: IRQ_FLAG */ +/* + * FLAG (RW) + * + * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag + * 0: no monitor interrupt + * 1: monitor interrupt happened + */ +#define PMON_IRQ_FLAG_FLAG_MASK (0xFU) +#define PMON_IRQ_FLAG_FLAG_SHIFT (0U) +#define PMON_IRQ_FLAG_FLAG_SET(x) (((uint32_t)(x) << PMON_IRQ_FLAG_FLAG_SHIFT) & PMON_IRQ_FLAG_FLAG_MASK) +#define PMON_IRQ_FLAG_FLAG_GET(x) (((uint32_t)(x) & PMON_IRQ_FLAG_FLAG_MASK) >> PMON_IRQ_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: IRQ_ENABLE */ +/* + * ENABLE (RW) + * + * interrupt enable, each bit represents for one monitor + * 0: monitor interrupt disabled + * 1: monitor interrupt enabled + */ +#define PMON_IRQ_ENABLE_ENABLE_MASK (0xFU) +#define PMON_IRQ_ENABLE_ENABLE_SHIFT (0U) +#define PMON_IRQ_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PMON_IRQ_ENABLE_ENABLE_SHIFT) & PMON_IRQ_ENABLE_ENABLE_MASK) +#define PMON_IRQ_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PMON_IRQ_ENABLE_ENABLE_MASK) >> PMON_IRQ_ENABLE_ENABLE_SHIFT) + + + +/* MONITOR register group index macro definition */ +#define PMON_MONITOR_GLITCH0 (0UL) +#define PMON_MONITOR_GLITCH1 (1UL) +#define PMON_MONITOR_CLOCK0 (2UL) +#define PMON_MONITOR_CLOCK1 (3UL) + + +#endif /* HPM_PMON_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h new file mode 100644 index 0000000000..b4c2e280e0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PPOR_H +#define HPM_PPOR_H + +typedef struct { + __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ + __RW uint32_t RESET_STATUS; /* 0x4: reset source status */ + __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ + __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ + __RW uint32_t RESET_HOT; /* 0x10: reset type triggered by reset */ + __RW uint32_t RESET_COLD; /* 0x14: reset type attribute */ + __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ + __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ +} PPOR_Type; + + +/* Bitfield definition for register: RESET_FLAG */ +/* + * FLAG (W1C) + * + * reset reason of last hard reset, write 1 to clear each bit + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) +#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) +#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: RESET_STATUS */ +/* + * STATUS (RW) + * + * current status of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) +#define PPOR_RESET_STATUS_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_STATUS_STATUS_SHIFT) & PPOR_RESET_STATUS_STATUS_MASK) +#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_HOLD */ +/* + * STATUS (RW) + * + * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOLD_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOLD_STATUS_SHIFT (0U) +#define PPOR_RESET_HOLD_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_STATUS_SHIFT) & PPOR_RESET_HOLD_STATUS_MASK) +#define PPOR_RESET_HOLD_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_STATUS_MASK) >> PPOR_RESET_HOLD_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_ENABLE */ +/* + * ENABLE (RW) + * + * enable of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) +#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) +#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) + +/* Bitfield definition for register: RESET_HOT */ +/* + * TYPE (RW) + * + * reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOT_TYPE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOT_TYPE_SHIFT (0U) +#define PPOR_RESET_HOT_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_HOT_TYPE_SHIFT) & PPOR_RESET_HOT_TYPE_MASK) +#define PPOR_RESET_HOT_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_HOT_TYPE_MASK) >> PPOR_RESET_HOT_TYPE_SHIFT) + +/* Bitfield definition for register: RESET_COLD */ +/* + * FLAG (RW) + * + * perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_COLD_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_COLD_FLAG_SHIFT (0U) +#define PPOR_RESET_COLD_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_COLD_FLAG_SHIFT) & PPOR_RESET_COLD_FLAG_MASK) +#define PPOR_RESET_COLD_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_COLD_FLAG_MASK) >> PPOR_RESET_COLD_FLAG_SHIFT) + +/* Bitfield definition for register: SOFTWARE_RESET */ +/* + * COUNTER (RW) + * + * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + */ +#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) +#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) +#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) +#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) + + + + +#endif /* HPM_PPOR_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_psec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_psec_regs.h new file mode 100644 index 0000000000..249a9c544d --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_psec_regs.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PSEC_H +#define HPM_PSEC_H + +typedef struct { + __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ + __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ + __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ + __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ + __R uint32_t EVENT; /* 0x10: Event and escalate status */ + __R uint32_t LIFECYCLE; /* 0x14: Lifecycle */ +} PSEC_Type; + + +/* Bitfield definition for register: SECURE_STATE */ +/* + * ALLOW_NSC (RO) + * + * Non-secure state allow + * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state + * 1: system is healthy to enter non-secure state + */ +#define PSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) +#define PSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) +#define PSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_NSC_MASK) >> PSEC_SECURE_STATE_ALLOW_NSC_SHIFT) + +/* + * ALLOW_SEC (RO) + * + * Secure state allow + * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state + * 1: system is healthy to enter secure state + */ +#define PSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) +#define PSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) +#define PSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_SEC_MASK) >> PSEC_SECURE_STATE_ALLOW_SEC_SHIFT) + +/* + * PMIC_FAIL (RW) + * + * PMIC secure state one hot indicator + * 0: secure state is not in fail state + * 1: secure state is in fail state + */ +#define PSEC_SECURE_STATE_PMIC_FAIL_MASK (0x80U) +#define PSEC_SECURE_STATE_PMIC_FAIL_SHIFT (7U) +#define PSEC_SECURE_STATE_PMIC_FAIL_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) +#define PSEC_SECURE_STATE_PMIC_FAIL_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) >> PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) + +/* + * PMIC_NSC (RW) + * + * PMIC secure state one hot indicator + * 0: secure state is not in non-secure state + * 1: secure state is in non-secure state + */ +#define PSEC_SECURE_STATE_PMIC_NSC_MASK (0x40U) +#define PSEC_SECURE_STATE_PMIC_NSC_SHIFT (6U) +#define PSEC_SECURE_STATE_PMIC_NSC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_NSC_SHIFT) & PSEC_SECURE_STATE_PMIC_NSC_MASK) +#define PSEC_SECURE_STATE_PMIC_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_NSC_MASK) >> PSEC_SECURE_STATE_PMIC_NSC_SHIFT) + +/* + * PMIC_SEC (RW) + * + * PMIC secure state one hot indicator + * 0: secure state is not in secure state + * 1: secure state is in secure state + */ +#define PSEC_SECURE_STATE_PMIC_SEC_MASK (0x20U) +#define PSEC_SECURE_STATE_PMIC_SEC_SHIFT (5U) +#define PSEC_SECURE_STATE_PMIC_SEC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_SEC_SHIFT) & PSEC_SECURE_STATE_PMIC_SEC_MASK) +#define PSEC_SECURE_STATE_PMIC_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_SEC_MASK) >> PSEC_SECURE_STATE_PMIC_SEC_SHIFT) + +/* + * PMIC_INS (RW) + * + * PMIC secure state one hot indicator + * 0: secure state is not in inspect state + * 1: secure state is in inspect state + */ +#define PSEC_SECURE_STATE_PMIC_INS_MASK (0x10U) +#define PSEC_SECURE_STATE_PMIC_INS_SHIFT (4U) +#define PSEC_SECURE_STATE_PMIC_INS_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_INS_SHIFT) & PSEC_SECURE_STATE_PMIC_INS_MASK) +#define PSEC_SECURE_STATE_PMIC_INS_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_INS_MASK) >> PSEC_SECURE_STATE_PMIC_INS_SHIFT) + +/* Bitfield definition for register: SECURE_STATE_CONFIG */ +/* + * LOCK (RW) + * + * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset + * 0: not locked, register can be modified + * 1: register locked, write access to the register is ignored + */ +#define PSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) +#define PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) +#define PSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) +#define PSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) + +/* + * ALLOW_RESTART (RW) + * + * allow secure state restart from fail state + * 0: restart is not allowed, only hardware reset can recover secure state + * 1: software is allowed to switch to inspect state from fail state + */ +#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) +#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) +#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) +#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) + +/* Bitfield definition for register: VIOLATION_CONFIG */ +/* + * LOCK_NSC (RW) + * + * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) +#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) +#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) +#define PSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) + +/* + * NSC_VIO_CFG (RW) + * + * configuration of non-secure state violations, each bit represents one security event + * 0: event is not a security violation + * 1: event is a security violation + */ +#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) +#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) +#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) +#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) + +/* + * LOCK_SEC (RW) + * + * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) +#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) +#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) +#define PSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) + +/* + * SEC_VIO_CFG (RW) + * + * configuration of secure state violations, each bit represents one security event + * 0: event is not a security violation + * 1: event is a security violation + */ +#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) +#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) +#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) +#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) + +/* Bitfield definition for register: ESCALATE_CONFIG */ +/* + * LOCK_NSC (RW) + * + * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) +#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) +#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) +#define PSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) + +/* + * NSC_VIO_CFG (RW) + * + * configuration of non-secure state escalates, each bit represents one security event + * 0: event is not a security escalate + * 1: event is a security escalate + */ +#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) +#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) +#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) +#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) + +/* + * LOCK_SEC (RW) + * + * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) +#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) +#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) +#define PSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) + +/* + * SEC_VIO_CFG (RW) + * + * configuration of secure state escalates, each bit represents one security event + * 0: event is not a security escalate + * 1: event is a security escalate + */ +#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) +#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) +#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) +#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) + +/* Bitfield definition for register: EVENT */ +/* + * EVENT (RO) + * + * local event statue, each bit represents one security event + */ +#define PSEC_EVENT_EVENT_MASK (0xFFFF0000UL) +#define PSEC_EVENT_EVENT_SHIFT (16U) +#define PSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & PSEC_EVENT_EVENT_MASK) >> PSEC_EVENT_EVENT_SHIFT) + +/* + * PMIC_ESC_NSC (RO) + * + * PMIC is escalating non-secure event + */ +#define PSEC_EVENT_PMIC_ESC_NSC_MASK (0x8U) +#define PSEC_EVENT_PMIC_ESC_NSC_SHIFT (3U) +#define PSEC_EVENT_PMIC_ESC_NSC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_NSC_MASK) >> PSEC_EVENT_PMIC_ESC_NSC_SHIFT) + +/* + * PMIC_ESC_SEC (RO) + * + * PMIC is escalting secure event + */ +#define PSEC_EVENT_PMIC_ESC_SEC_MASK (0x4U) +#define PSEC_EVENT_PMIC_ESC_SEC_SHIFT (2U) +#define PSEC_EVENT_PMIC_ESC_SEC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_SEC_MASK) >> PSEC_EVENT_PMIC_ESC_SEC_SHIFT) + +/* Bitfield definition for register: LIFECYCLE */ +/* + * LIFECYCLE (RO) + * + * lifecycle status, + * bit7: lifecycle_debate, + * bit6: lifecycle_scribe, + * bit5: lifecycle_no_ret, + * bit4: lifecycle_return, + * bit3: lifecycle_secure, + * bit2: lifecycle_nonsec, + * bit1: lifecycle_create, + * bit0: lifecycle_unknow + */ +#define PSEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) +#define PSEC_LIFECYCLE_LIFECYCLE_SHIFT (0U) +#define PSEC_LIFECYCLE_LIFECYCLE_GET(x) (((uint32_t)(x) & PSEC_LIFECYCLE_LIFECYCLE_MASK) >> PSEC_LIFECYCLE_LIFECYCLE_SHIFT) + + + + +#endif /* HPM_PSEC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h new file mode 100644 index 0000000000..3fe0c72dd2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h @@ -0,0 +1,409 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PTPC_H +#define HPM_PTPC_H + +typedef struct { + struct { + __RW uint32_t CTRL0; /* 0x0: Control Register 0 */ + __RW uint32_t CTRL1; /* 0x4: Control Register 1 */ + __R uint32_t TIMEH; /* 0x8: timestamp high */ + __R uint32_t TIMEL; /* 0xC: timestamp low */ + __RW uint32_t TS_UPDTH; /* 0x10: timestamp update high */ + __RW uint32_t TS_UPDTL; /* 0x14: timestamp update low */ + __RW uint32_t ADDEND; /* 0x18: */ + __RW uint32_t TARH; /* 0x1C: */ + __RW uint32_t TARL; /* 0x20: */ + __R uint8_t RESERVED0[8]; /* 0x24 - 0x2B: Reserved */ + __RW uint32_t PPS_CTRL; /* 0x2C: */ + __R uint32_t CAPT_SNAPH; /* 0x30: */ + __RW uint32_t CAPT_SNAPL; /* 0x34: */ + __R uint8_t RESERVED1[4040]; /* 0x38 - 0xFFF: Reserved */ + } PTPC[2]; + __RW uint32_t TIME_SEL; /* 0x2000: */ + __W uint32_t INT_STS; /* 0x2004: */ + __RW uint32_t INT_EN; /* 0x2008: */ +} PTPC_Type; + + +/* Bitfield definition for register of struct array PTPC: CTRL0 */ +/* + * SUBSEC_DIGITAL_ROLLOVER (RW) + * + * Format for ns counter rollover, + * 1-digital, overflow time 1000000000/0x3B9ACA00 + * 0-binary, overflow time 0x7FFFFFFF + */ +#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK (0x200U) +#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT (9U) +#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) +#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) + +/* + * CAPT_SNAP_KEEP (RW) + * + * set will keep capture snap till software read capt_snapl. + * If this bit is set, software should read capt_snaph first to avoid wrong result. + * If this bit is cleared, capture result will be updated at each capture event + */ +#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK (0x100U) +#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT (8U) +#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) +#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) + +/* + * CAPT_SNAP_POS_EN (RW) + * + * set will use posege of input capture signal to latch timestamp value + */ +#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK (0x80U) +#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT (7U) +#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) +#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) + +/* + * CAPT_SNAP_NEG_EN (RW) + * + */ +#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK (0x40U) +#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT (6U) +#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) +#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) + +/* + * COMP_EN (RW) + * + * set to enable compare, will be cleared by HW when compare event triggered + */ +#define PTPC_PTPC_CTRL0_COMP_EN_MASK (0x10U) +#define PTPC_PTPC_CTRL0_COMP_EN_SHIFT (4U) +#define PTPC_PTPC_CTRL0_COMP_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK) +#define PTPC_PTPC_CTRL0_COMP_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT) + +/* + * UPDATE_TIMER (WO) + * + * update timer with +/- ts_updt, pulse, clear after set + */ +#define PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK (0x8U) +#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT (3U) +#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) +#define PTPC_PTPC_CTRL0_UPDATE_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) + +/* + * INIT_TIMER (WO) + * + * initial timer with ts_updt, pulse, clear after set + */ +#define PTPC_PTPC_CTRL0_INIT_TIMER_MASK (0x4U) +#define PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT (2U) +#define PTPC_PTPC_CTRL0_INIT_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) +#define PTPC_PTPC_CTRL0_INIT_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) + +/* + * FINE_COARSE_SEL (RW) + * + * 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow + * 1: coarse update, ns counter add ss_incr[7:0] each clk + */ +#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) +#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) +#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) +#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) + +/* + * TIMER_ENABLE (RW) + * + */ +#define PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK (0x1U) +#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT (0U) +#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) +#define PTPC_PTPC_CTRL0_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array PTPC: CTRL1 */ +/* + * SS_INCR (RW) + * + * constant value used to add ns counter; + * such as for 50MHz timer clock, set it to 8'd20 + */ +#define PTPC_PTPC_CTRL1_SS_INCR_MASK (0xFFU) +#define PTPC_PTPC_CTRL1_SS_INCR_SHIFT (0U) +#define PTPC_PTPC_CTRL1_SS_INCR_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK) +#define PTPC_PTPC_CTRL1_SS_INCR_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT) + +/* Bitfield definition for register of struct array PTPC: TIMEH */ +/* + * TIMESTAMP_HIGH (RO) + * + */ +#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL) +#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT (0U) +#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT) + +/* Bitfield definition for register of struct array PTPC: TIMEL */ +/* + * TIMESTAMP_LOW (RO) + * + */ +#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL) +#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT (0U) +#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT) + +/* Bitfield definition for register of struct array PTPC: TS_UPDTH */ +/* + * SEC_UPDATE (RW) + * + * together with ts_updtl, used to initial or update timestamp + */ +#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK (0xFFFFFFFFUL) +#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT (0U) +#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) +#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) + +/* Bitfield definition for register of struct array PTPC: TS_UPDTL */ +/* + * ADD_SUB (RW) + * + * 1 for sub; 0 for add, used only at update + */ +#define PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK (0x80000000UL) +#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT (31U) +#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) +#define PTPC_PTPC_TS_UPDTL_ADD_SUB_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) + +/* + * NS_UPDATE (RW) + * + */ +#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK (0x7FFFFFFFUL) +#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT (0U) +#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) +#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) + +/* Bitfield definition for register of struct array PTPC: ADDEND */ +/* + * ADDEND (RW) + * + * used in fine update mode only + */ +#define PTPC_PTPC_ADDEND_ADDEND_MASK (0xFFFFFFFFUL) +#define PTPC_PTPC_ADDEND_ADDEND_SHIFT (0U) +#define PTPC_PTPC_ADDEND_ADDEND_SET(x) (((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK) +#define PTPC_PTPC_ADDEND_ADDEND_GET(x) (((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT) + +/* Bitfield definition for register of struct array PTPC: TARH */ +/* + * TARGET_TIME_HIGH (RW) + * + * used for generate compare signal if enabled + */ +#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK (0xFFFFFFFFUL) +#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT (0U) +#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) +#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) + +/* Bitfield definition for register of struct array PTPC: TARL */ +/* + * TARGET_TIME_LOW (RW) + * + */ +#define PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK (0xFFFFFFFFUL) +#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT (0U) +#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) +#define PTPC_PTPC_TARL_TARGET_TIME_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) + +/* Bitfield definition for register of struct array PTPC: PPS_CTRL */ +/* + * PPS_CTRL (RW) + * + */ +#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK (0xFU) +#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT (0U) +#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(x) (((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) +#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET(x) (((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) + +/* Bitfield definition for register of struct array PTPC: CAPT_SNAPH */ +/* + * CAPT_SNAP_HIGH (RO) + * + * take snapshot for input capture signal, at pos or neg or both; + * the result can be kept or updated at each event according to cfg0.bit8 + */ +#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK (0xFFFFFFFFUL) +#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT (0U) +#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT) + +/* Bitfield definition for register of struct array PTPC: CAPT_SNAPL */ +/* + * CAPT_SNAP_LOW (RW) + * + */ +#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK (0xFFFFFFFFUL) +#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT (0U) +#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) +#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) + +/* Bitfield definition for register: TIME_SEL */ +/* + * CAN3_TIME_SEL (RW) + * + */ +#define PTPC_TIME_SEL_CAN3_TIME_SEL_MASK (0x8U) +#define PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT (3U) +#define PTPC_TIME_SEL_CAN3_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) +#define PTPC_TIME_SEL_CAN3_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) + +/* + * CAN2_TIME_SEL (RW) + * + */ +#define PTPC_TIME_SEL_CAN2_TIME_SEL_MASK (0x4U) +#define PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT (2U) +#define PTPC_TIME_SEL_CAN2_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) +#define PTPC_TIME_SEL_CAN2_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) + +/* + * CAN1_TIME_SEL (RW) + * + */ +#define PTPC_TIME_SEL_CAN1_TIME_SEL_MASK (0x2U) +#define PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT (1U) +#define PTPC_TIME_SEL_CAN1_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) +#define PTPC_TIME_SEL_CAN1_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) + +/* + * CAN0_TIME_SEL (RW) + * + * set to use ptpc1 for canx + * clr to use ptpc0 for canx + */ +#define PTPC_TIME_SEL_CAN0_TIME_SEL_MASK (0x1U) +#define PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT (0U) +#define PTPC_TIME_SEL_CAN0_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) +#define PTPC_TIME_SEL_CAN0_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) + +/* Bitfield definition for register: INT_STS */ +/* + * COMP_INT_STS1 (W1C) + * + */ +#define PTPC_INT_STS_COMP_INT_STS1_MASK (0x40000UL) +#define PTPC_INT_STS_COMP_INT_STS1_SHIFT (18U) +#define PTPC_INT_STS_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK) +#define PTPC_INT_STS_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT) + +/* + * CAPTURE_INT_STS1 (W1C) + * + */ +#define PTPC_INT_STS_CAPTURE_INT_STS1_MASK (0x20000UL) +#define PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT (17U) +#define PTPC_INT_STS_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) +#define PTPC_INT_STS_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) + +/* + * PPS_INT_STS1 (W1C) + * + */ +#define PTPC_INT_STS_PPS_INT_STS1_MASK (0x10000UL) +#define PTPC_INT_STS_PPS_INT_STS1_SHIFT (16U) +#define PTPC_INT_STS_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK) +#define PTPC_INT_STS_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT) + +/* + * COMP_INT_STS0 (W1C) + * + */ +#define PTPC_INT_STS_COMP_INT_STS0_MASK (0x4U) +#define PTPC_INT_STS_COMP_INT_STS0_SHIFT (2U) +#define PTPC_INT_STS_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK) +#define PTPC_INT_STS_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT) + +/* + * CAPTURE_INT_STS0 (W1C) + * + */ +#define PTPC_INT_STS_CAPTURE_INT_STS0_MASK (0x2U) +#define PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT (1U) +#define PTPC_INT_STS_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) +#define PTPC_INT_STS_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) + +/* + * PPS_INT_STS0 (W1C) + * + */ +#define PTPC_INT_STS_PPS_INT_STS0_MASK (0x1U) +#define PTPC_INT_STS_PPS_INT_STS0_SHIFT (0U) +#define PTPC_INT_STS_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK) +#define PTPC_INT_STS_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * COMP_INT_STS1 (RW) + * + */ +#define PTPC_INT_EN_COMP_INT_STS1_MASK (0x40000UL) +#define PTPC_INT_EN_COMP_INT_STS1_SHIFT (18U) +#define PTPC_INT_EN_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK) +#define PTPC_INT_EN_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT) + +/* + * CAPTURE_INT_STS1 (RW) + * + */ +#define PTPC_INT_EN_CAPTURE_INT_STS1_MASK (0x20000UL) +#define PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT (17U) +#define PTPC_INT_EN_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) +#define PTPC_INT_EN_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) + +/* + * PPS_INT_STS1 (RW) + * + */ +#define PTPC_INT_EN_PPS_INT_STS1_MASK (0x10000UL) +#define PTPC_INT_EN_PPS_INT_STS1_SHIFT (16U) +#define PTPC_INT_EN_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK) +#define PTPC_INT_EN_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT) + +/* + * COMP_INT_STS0 (RW) + * + */ +#define PTPC_INT_EN_COMP_INT_STS0_MASK (0x4U) +#define PTPC_INT_EN_COMP_INT_STS0_SHIFT (2U) +#define PTPC_INT_EN_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK) +#define PTPC_INT_EN_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT) + +/* + * CAPTURE_INT_STS0 (RW) + * + */ +#define PTPC_INT_EN_CAPTURE_INT_STS0_MASK (0x2U) +#define PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT (1U) +#define PTPC_INT_EN_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) +#define PTPC_INT_EN_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) + +/* + * PPS_INT_STS0 (RW) + * + */ +#define PTPC_INT_EN_PPS_INT_STS0_MASK (0x1U) +#define PTPC_INT_EN_PPS_INT_STS0_SHIFT (0U) +#define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) +#define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) + + + +/* PTPC register group index macro definition */ +#define PTPC_PTPC_0 (0UL) +#define PTPC_PTPC_1 (1UL) + + +#endif /* HPM_PTPC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h new file mode 100644 index 0000000000..3790ae929a --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h @@ -0,0 +1,923 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PWM_H +#define HPM_PWM_H + +typedef struct { + __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ + __RW uint32_t STA; /* 0x4: Counter start register */ + __RW uint32_t RLD; /* 0x8: Counter reload register */ + __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ + __R uint8_t RESERVED0[12]; /* 0x6C - 0x77: Reserved */ + __RW uint32_t FRCMD; /* 0x78: Force output mode register */ + __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ + __RW uint32_t CHCFG[24]; /* 0x80 - 0xDC: Output channel configure register */ + __R uint8_t RESERVED1[16]; /* 0xE0 - 0xEF: Reserved */ + __RW uint32_t GCR; /* 0xF0: Global control register */ + __RW uint32_t SHCR; /* 0xF4: Shadow register control register */ + __R uint8_t RESERVED2[8]; /* 0xF8 - 0xFF: Reserved */ + __R uint32_t CAPPOS[24]; /* 0x100 - 0x15C: Capture rising edge register */ + __R uint8_t RESERVED3[16]; /* 0x160 - 0x16F: Reserved */ + __R uint32_t CNT; /* 0x170: Counter */ + __R uint8_t RESERVED4[12]; /* 0x174 - 0x17F: Reserved */ + __R uint32_t CAPNEG[24]; /* 0x180 - 0x1DC: Capture falling edge register */ + __R uint8_t RESERVED5[16]; /* 0x1E0 - 0x1EF: Reserved */ + __R uint32_t CNTCOPY; /* 0x1F0: Counter copy */ + __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ + __RW uint32_t PWMCFG[8]; /* 0x200 - 0x21C: PWM channel configure register */ + __W uint32_t SR; /* 0x220: Status register */ + __RW uint32_t IRQEN; /* 0x224: Interrupt request enable register */ + __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ + __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ + __RW uint32_t CMPCFG[24]; /* 0x230 - 0x28C: Comparator configure register */ +} PWM_Type; + + +/* Bitfield definition for register: UNLK */ +/* + * SHUNLK (RW) + * + * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written. + */ +#define PWM_UNLK_SHUNLK_MASK (0xFFFFFFFFUL) +#define PWM_UNLK_SHUNLK_SHIFT (0U) +#define PWM_UNLK_SHUNLK_SET(x) (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK) +#define PWM_UNLK_SHUNLK_GET(x) (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT) + +/* Bitfield definition for register: STA */ +/* + * XSTA (RW) + * + * pwm timer counter extended start point, should back to this value after reach xrld + */ +#define PWM_STA_XSTA_MASK (0xF0000000UL) +#define PWM_STA_XSTA_SHIFT (28U) +#define PWM_STA_XSTA_SET(x) (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK) +#define PWM_STA_XSTA_GET(x) (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT) + +/* + * STA (RW) + * + * pwm timer counter start value + * sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk + */ +#define PWM_STA_STA_MASK (0xFFFFFF0UL) +#define PWM_STA_STA_SHIFT (4U) +#define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) +#define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) + +/* Bitfield definition for register: RLD */ +/* + * XRLD (RW) + * + * timeout counter extended reload point, counter will reload to xsta after reach this point + */ +#define PWM_RLD_XRLD_MASK (0xF0000000UL) +#define PWM_RLD_XRLD_SHIFT (28U) +#define PWM_RLD_XRLD_SET(x) (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK) +#define PWM_RLD_XRLD_GET(x) (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT) + +/* + * RLD (RW) + * + * pwm timer counter reload value + */ +#define PWM_RLD_RLD_MASK (0xFFFFFF0UL) +#define PWM_RLD_RLD_SHIFT (4U) +#define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) +#define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) + +/* Bitfield definition for register array: CMP */ +/* + * XCMP (RW) + * + * extended counter compare value + */ +#define PWM_CMP_XCMP_MASK (0xF0000000UL) +#define PWM_CMP_XCMP_SHIFT (28U) +#define PWM_CMP_XCMP_SET(x) (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK) +#define PWM_CMP_XCMP_GET(x) (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT) + +/* + * CMP (RW) + * + * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + */ +#define PWM_CMP_CMP_MASK (0xFFFFFF0UL) +#define PWM_CMP_CMP_SHIFT (4U) +#define PWM_CMP_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK) +#define PWM_CMP_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT) + +/* + * CMPHLF (RW) + * + * half clock counter compare value + */ +#define PWM_CMP_CMPHLF_MASK (0x8U) +#define PWM_CMP_CMPHLF_SHIFT (3U) +#define PWM_CMP_CMPHLF_SET(x) (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK) +#define PWM_CMP_CMPHLF_GET(x) (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT) + +/* + * CMPJIT (RW) + * + * jitter counter compare value + */ +#define PWM_CMP_CMPJIT_MASK (0x7U) +#define PWM_CMP_CMPJIT_SHIFT (0U) +#define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) +#define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) + +/* Bitfield definition for register: FRCMD */ +/* + * FRCMD (RW) + * + * 2bit for each PWM output channel (0~7); + * 00: force output 0 + * 01: force output 1 + * 10: output highz + * 11: no force + */ +#define PWM_FRCMD_FRCMD_MASK (0xFFFFU) +#define PWM_FRCMD_FRCMD_SHIFT (0U) +#define PWM_FRCMD_FRCMD_SET(x) (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK) +#define PWM_FRCMD_FRCMD_GET(x) (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT) + +/* Bitfield definition for register: SHLK */ +/* + * SHLK (RW) + * + * write 1 to lock all shawdow register, wirte access is not permitted + */ +#define PWM_SHLK_SHLK_MASK (0x80000000UL) +#define PWM_SHLK_SHLK_SHIFT (31U) +#define PWM_SHLK_SHLK_SET(x) (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK) +#define PWM_SHLK_SHLK_GET(x) (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT) + +/* Bitfield definition for register array: CHCFG */ +/* + * CMPSELEND (RW) + * + * assign the last comparator for this output channel + */ +#define PWM_CHCFG_CMPSELEND_MASK (0x1F000000UL) +#define PWM_CHCFG_CMPSELEND_SHIFT (24U) +#define PWM_CHCFG_CMPSELEND_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK) +#define PWM_CHCFG_CMPSELEND_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT) + +/* + * CMPSELBEG (RW) + * + * assign the first comparator for this output channel + */ +#define PWM_CHCFG_CMPSELBEG_MASK (0x1F0000UL) +#define PWM_CHCFG_CMPSELBEG_SHIFT (16U) +#define PWM_CHCFG_CMPSELBEG_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK) +#define PWM_CHCFG_CMPSELBEG_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT) + +/* + * OUTPOL (RW) + * + * output polarity, set to 1 will invert the output + */ +#define PWM_CHCFG_OUTPOL_MASK (0x2U) +#define PWM_CHCFG_OUTPOL_SHIFT (1U) +#define PWM_CHCFG_OUTPOL_SET(x) (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK) +#define PWM_CHCFG_OUTPOL_GET(x) (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT) + +/* Bitfield definition for register: GCR */ +/* + * FAULTI3EN (RW) + * + * 1- enable the internal fault input 3 + */ +#define PWM_GCR_FAULTI3EN_MASK (0x80000000UL) +#define PWM_GCR_FAULTI3EN_SHIFT (31U) +#define PWM_GCR_FAULTI3EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK) +#define PWM_GCR_FAULTI3EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT) + +/* + * FAULTI2EN (RW) + * + * 1- enable the internal fault input 2 + */ +#define PWM_GCR_FAULTI2EN_MASK (0x40000000UL) +#define PWM_GCR_FAULTI2EN_SHIFT (30U) +#define PWM_GCR_FAULTI2EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK) +#define PWM_GCR_FAULTI2EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT) + +/* + * FAULTI1EN (RW) + * + * 1- enable the internal fault input 1 + */ +#define PWM_GCR_FAULTI1EN_MASK (0x20000000UL) +#define PWM_GCR_FAULTI1EN_SHIFT (29U) +#define PWM_GCR_FAULTI1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK) +#define PWM_GCR_FAULTI1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT) + +/* + * FAULTI0EN (RW) + * + * 1- enable the internal fault input 0 + */ +#define PWM_GCR_FAULTI0EN_MASK (0x10000000UL) +#define PWM_GCR_FAULTI0EN_SHIFT (28U) +#define PWM_GCR_FAULTI0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK) +#define PWM_GCR_FAULTI0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT) + +/* + * DEBUGFAULT (RW) + * + * 1- enable debug mode output protection + */ +#define PWM_GCR_DEBUGFAULT_MASK (0x8000000UL) +#define PWM_GCR_DEBUGFAULT_SHIFT (27U) +#define PWM_GCR_DEBUGFAULT_SET(x) (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK) +#define PWM_GCR_DEBUGFAULT_GET(x) (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT) + +/* + * FRCPOL (RW) + * + * polarity of input pwm_force, + * 1- active low + * 0- active high + */ +#define PWM_GCR_FRCPOL_MASK (0x4000000UL) +#define PWM_GCR_FRCPOL_SHIFT (26U) +#define PWM_GCR_FRCPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK) +#define PWM_GCR_FRCPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT) + +/* + * HWSHDWEDG (RW) + * + * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as shadow register hardware load event. + * 1- Falling edge + * 0- Rising edge + */ +#define PWM_GCR_HWSHDWEDG_MASK (0x1000000UL) +#define PWM_GCR_HWSHDWEDG_SHIFT (24U) +#define PWM_GCR_HWSHDWEDG_SET(x) (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK) +#define PWM_GCR_HWSHDWEDG_GET(x) (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT) + +/* + * CMPSHDWSEL (RW) + * + * This bitfield select one of the comparators as hardware event time to load comparator shadow registers + */ +#define PWM_GCR_CMPSHDWSEL_MASK (0xF80000UL) +#define PWM_GCR_CMPSHDWSEL_SHIFT (19U) +#define PWM_GCR_CMPSHDWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK) +#define PWM_GCR_CMPSHDWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT) + +/* + * FAULTRECEDG (RW) + * + * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. + * 1- Falling edge + * 0- Rising edge + */ +#define PWM_GCR_FAULTRECEDG_MASK (0x40000UL) +#define PWM_GCR_FAULTRECEDG_SHIFT (18U) +#define PWM_GCR_FAULTRECEDG_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK) +#define PWM_GCR_FAULTRECEDG_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT) + +/* + * FAULTRECHWSEL (RW) + * + * Selec one of the 24 comparators as fault output recover trigger. + */ +#define PWM_GCR_FAULTRECHWSEL_MASK (0x3E000UL) +#define PWM_GCR_FAULTRECHWSEL_SHIFT (13U) +#define PWM_GCR_FAULTRECHWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK) +#define PWM_GCR_FAULTRECHWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT) + +/* + * FAULTE1EN (RW) + * + * 1- enable the external fault input 1 + */ +#define PWM_GCR_FAULTE1EN_MASK (0x1000U) +#define PWM_GCR_FAULTE1EN_SHIFT (12U) +#define PWM_GCR_FAULTE1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK) +#define PWM_GCR_FAULTE1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT) + +/* + * FAULTE0EN (RW) + * + * 1- enable the external fault input 0 + */ +#define PWM_GCR_FAULTE0EN_MASK (0x800U) +#define PWM_GCR_FAULTE0EN_SHIFT (11U) +#define PWM_GCR_FAULTE0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK) +#define PWM_GCR_FAULTE0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT) + +/* + * FAULTEXPOL (RW) + * + * external fault polarity + * 1-active low + * 0-active high + */ +#define PWM_GCR_FAULTEXPOL_MASK (0x600U) +#define PWM_GCR_FAULTEXPOL_SHIFT (9U) +#define PWM_GCR_FAULTEXPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK) +#define PWM_GCR_FAULTEXPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT) + +/* + * RLDSYNCEN (RW) + * + * 1- pwm timer counter reset to reload value (rld) by synci is enabled + */ +#define PWM_GCR_RLDSYNCEN_MASK (0x100U) +#define PWM_GCR_RLDSYNCEN_SHIFT (8U) +#define PWM_GCR_RLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK) +#define PWM_GCR_RLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT) + +/* + * CEN (RW) + * + * 1- enable the pwm timer counter + * 0- stop the pwm timer counter + */ +#define PWM_GCR_CEN_MASK (0x80U) +#define PWM_GCR_CEN_SHIFT (7U) +#define PWM_GCR_CEN_SET(x) (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK) +#define PWM_GCR_CEN_GET(x) (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT) + +/* + * FAULTCLR (RW) + * + * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + */ +#define PWM_GCR_FAULTCLR_MASK (0x40U) +#define PWM_GCR_FAULTCLR_SHIFT (6U) +#define PWM_GCR_FAULTCLR_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK) +#define PWM_GCR_FAULTCLR_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT) + +/* + * XRLDSYNCEN (RW) + * + * 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled + */ +#define PWM_GCR_XRLDSYNCEN_MASK (0x20U) +#define PWM_GCR_XRLDSYNCEN_SHIFT (5U) +#define PWM_GCR_XRLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK) +#define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) + +/* + * FRCTIME (RW) + * + * This bit field select the force effective time + * 00: force immediately + * 01: force at main counter reload time + * 10: force at FRCSYNCI + * 11: no force + */ +#define PWM_GCR_FRCTIME_MASK (0x6U) +#define PWM_GCR_FRCTIME_SHIFT (1U) +#define PWM_GCR_FRCTIME_SET(x) (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK) +#define PWM_GCR_FRCTIME_GET(x) (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT) + +/* + * SWFRC (RW) + * + * 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect + */ +#define PWM_GCR_SWFRC_MASK (0x1U) +#define PWM_GCR_SWFRC_SHIFT (0U) +#define PWM_GCR_SWFRC_SET(x) (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK) +#define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) + +/* Bitfield definition for register: SHCR */ +/* + * FRCSHDWSEL (RW) + * + * This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers + */ +#define PWM_SHCR_FRCSHDWSEL_MASK (0x1F00U) +#define PWM_SHCR_FRCSHDWSEL_SHIFT (8U) +#define PWM_SHCR_FRCSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK) +#define PWM_SHCR_FRCSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT) + +/* + * CNTSHDWSEL (RW) + * + * This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) + */ +#define PWM_SHCR_CNTSHDWSEL_MASK (0xF8U) +#define PWM_SHCR_CNTSHDWSEL_SHIFT (3U) +#define PWM_SHCR_CNTSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK) +#define PWM_SHCR_CNTSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT) + +/* + * CNTSHDWUPT (RW) + * + * This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register + * 00: after software set shlk bit of shlk register + * 01: immediately after the register being modified + * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. + * 11: after SHSYNCI assert + */ +#define PWM_SHCR_CNTSHDWUPT_MASK (0x6U) +#define PWM_SHCR_CNTSHDWUPT_SHIFT (1U) +#define PWM_SHCR_CNTSHDWUPT_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK) +#define PWM_SHCR_CNTSHDWUPT_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT) + +/* + * SHLKEN (RW) + * + * 1- enable shadow registers lock feature, + * 0- disable shadow registers lock, shlk bit will always be 0 + */ +#define PWM_SHCR_SHLKEN_MASK (0x1U) +#define PWM_SHCR_SHLKEN_SHIFT (0U) +#define PWM_SHCR_SHLKEN_SET(x) (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK) +#define PWM_SHCR_SHLKEN_GET(x) (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT) + +/* Bitfield definition for register array: CAPPOS */ +/* + * CAPPOS (RO) + * + * counter value captured at input posedge + */ +#define PWM_CAPPOS_CAPPOS_MASK (0xFFFFFFF0UL) +#define PWM_CAPPOS_CAPPOS_SHIFT (4U) +#define PWM_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT) + +/* Bitfield definition for register: CNT */ +/* + * XCNT (RO) + * + * current extended counter value + */ +#define PWM_CNT_XCNT_MASK (0xF0000000UL) +#define PWM_CNT_XCNT_SHIFT (28U) +#define PWM_CNT_XCNT_GET(x) (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT) + +/* + * CNT (RO) + * + * current clock counter value + */ +#define PWM_CNT_CNT_MASK (0xFFFFFF0UL) +#define PWM_CNT_CNT_SHIFT (4U) +#define PWM_CNT_CNT_GET(x) (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT) + +/* Bitfield definition for register array: CAPNEG */ +/* + * CAPNEG (RO) + * + * counter value captured at input signal falling edge + */ +#define PWM_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) +#define PWM_CAPNEG_CAPNEG_SHIFT (0U) +#define PWM_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT) + +/* Bitfield definition for register: CNTCOPY */ +/* + * XCNT (RO) + * + * current extended counter value + */ +#define PWM_CNTCOPY_XCNT_MASK (0xF0000000UL) +#define PWM_CNTCOPY_XCNT_SHIFT (28U) +#define PWM_CNTCOPY_XCNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT) + +/* + * CNT (RO) + * + * current clock counter value + */ +#define PWM_CNTCOPY_CNT_MASK (0xFFFFFF0UL) +#define PWM_CNTCOPY_CNT_SHIFT (4U) +#define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) + +/* Bitfield definition for register array: PWMCFG */ +/* + * OEN (RW) + * + * PWM output enable + * 1- output is enabled + * 0- output is disabled + */ +#define PWM_PWMCFG_OEN_MASK (0x10000000UL) +#define PWM_PWMCFG_OEN_SHIFT (28U) +#define PWM_PWMCFG_OEN_SET(x) (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK) +#define PWM_PWMCFG_OEN_GET(x) (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT) + +/* + * FRCSHDWUPT (RW) + * + * This bitfield select when the FRCMD shadow register will be loaded to its work register + * 00: after software set shlk bit of shlk register + * 01: immediately after the register being modified + * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. + * 11: after SHSYNCI assert + */ +#define PWM_PWMCFG_FRCSHDWUPT_MASK (0xC000000UL) +#define PWM_PWMCFG_FRCSHDWUPT_SHIFT (26U) +#define PWM_PWMCFG_FRCSHDWUPT_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK) +#define PWM_PWMCFG_FRCSHDWUPT_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT) + +/* + * FAULTMODE (RW) + * + * This bitfield defines the PWM output status when fault condition happen + * 00: force output 0 + * 01: force output 1 + * 1x: output highz + */ +#define PWM_PWMCFG_FAULTMODE_MASK (0x3000000UL) +#define PWM_PWMCFG_FAULTMODE_SHIFT (24U) +#define PWM_PWMCFG_FAULTMODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK) +#define PWM_PWMCFG_FAULTMODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT) + +/* + * FAULTRECTIME (RW) + * + * This bitfield select when to recover PWM output after fault condition removed. + * 00: immediately + * 01: after pwm timer counter reload time + * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. + * 11: after software write faultclr bit in GCR register + */ +#define PWM_PWMCFG_FAULTRECTIME_MASK (0xC00000UL) +#define PWM_PWMCFG_FAULTRECTIME_SHIFT (22U) +#define PWM_PWMCFG_FAULTRECTIME_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK) +#define PWM_PWMCFG_FAULTRECTIME_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT) + +/* + * FRCSRCSEL (RW) + * + * Select sources for force output + * 0- force output is enabled when FRCI assert + * 1- force output is enabled by software write swfrc to 1 + */ +#define PWM_PWMCFG_FRCSRCSEL_MASK (0x200000UL) +#define PWM_PWMCFG_FRCSRCSEL_SHIFT (21U) +#define PWM_PWMCFG_FRCSRCSEL_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK) +#define PWM_PWMCFG_FRCSRCSEL_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT) + +/* + * PAIR (RW) + * + * 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. + * 0- PWM output is in indepandent mode. + */ +#define PWM_PWMCFG_PAIR_MASK (0x100000UL) +#define PWM_PWMCFG_PAIR_SHIFT (20U) +#define PWM_PWMCFG_PAIR_SET(x) (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK) +#define PWM_PWMCFG_PAIR_GET(x) (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT) + +/* + * DEADAREA (RW) + * + * This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. + * Note: user should configure pair bit and this bitfield before PWM output is enabled. + */ +#define PWM_PWMCFG_DEADAREA_MASK (0xFFFFFUL) +#define PWM_PWMCFG_DEADAREA_SHIFT (0U) +#define PWM_PWMCFG_DEADAREA_SET(x) (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK) +#define PWM_PWMCFG_DEADAREA_GET(x) (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT) + +/* Bitfield definition for register: SR */ +/* + * FAULTF (W1C) + * + * fault condition flag + */ +#define PWM_SR_FAULTF_MASK (0x8000000UL) +#define PWM_SR_FAULTF_SHIFT (27U) +#define PWM_SR_FAULTF_SET(x) (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK) +#define PWM_SR_FAULTF_GET(x) (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT) + +/* + * XRLDF (W1C) + * + * extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + */ +#define PWM_SR_XRLDF_MASK (0x4000000UL) +#define PWM_SR_XRLDF_SHIFT (26U) +#define PWM_SR_XRLDF_SET(x) (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK) +#define PWM_SR_XRLDF_GET(x) (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT) + +/* + * HALFRLDF (W1C) + * + * half reload flag, this flag set when cnt count to rld/2 + */ +#define PWM_SR_HALFRLDF_MASK (0x2000000UL) +#define PWM_SR_HALFRLDF_SHIFT (25U) +#define PWM_SR_HALFRLDF_SET(x) (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK) +#define PWM_SR_HALFRLDF_GET(x) (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT) + +/* + * RLDF (W1C) + * + * reload flag, this flag set when cnt count to rld value or when SYNCI assert + */ +#define PWM_SR_RLDF_MASK (0x1000000UL) +#define PWM_SR_RLDF_SHIFT (24U) +#define PWM_SR_RLDF_SET(x) (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK) +#define PWM_SR_RLDF_GET(x) (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT) + +/* + * CMPFX (W1C) + * + * comparator output compare or input capture flag + */ +#define PWM_SR_CMPFX_MASK (0xFFFFFFUL) +#define PWM_SR_CMPFX_SHIFT (0U) +#define PWM_SR_CMPFX_SET(x) (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK) +#define PWM_SR_CMPFX_GET(x) (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT) + +/* Bitfield definition for register: IRQEN */ +/* + * FAULTIRQE (RW) + * + * fault condition interrupt enable + */ +#define PWM_IRQEN_FAULTIRQE_MASK (0x8000000UL) +#define PWM_IRQEN_FAULTIRQE_SHIFT (27U) +#define PWM_IRQEN_FAULTIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK) +#define PWM_IRQEN_FAULTIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT) + +/* + * XRLDIRQE (RW) + * + * extended reload flag interrupt enable + */ +#define PWM_IRQEN_XRLDIRQE_MASK (0x4000000UL) +#define PWM_IRQEN_XRLDIRQE_SHIFT (26U) +#define PWM_IRQEN_XRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK) +#define PWM_IRQEN_XRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT) + +/* + * HALFRLDIRQE (RW) + * + * half reload flag interrupt enable + */ +#define PWM_IRQEN_HALFRLDIRQE_MASK (0x2000000UL) +#define PWM_IRQEN_HALFRLDIRQE_SHIFT (25U) +#define PWM_IRQEN_HALFRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK) +#define PWM_IRQEN_HALFRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT) + +/* + * RLDIRQE (RW) + * + * reload flag interrupt enable + */ +#define PWM_IRQEN_RLDIRQE_MASK (0x1000000UL) +#define PWM_IRQEN_RLDIRQE_SHIFT (24U) +#define PWM_IRQEN_RLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK) +#define PWM_IRQEN_RLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT) + +/* + * CMPIRQEX (RW) + * + * comparator output compare or input capture flag interrupt enable + */ +#define PWM_IRQEN_CMPIRQEX_MASK (0xFFFFFFUL) +#define PWM_IRQEN_CMPIRQEX_SHIFT (0U) +#define PWM_IRQEN_CMPIRQEX_SET(x) (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK) +#define PWM_IRQEN_CMPIRQEX_GET(x) (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT) + +/* Bitfield definition for register: DMAEN */ +/* + * FAULTEN (RW) + * + * fault condition DMA request enable + */ +#define PWM_DMAEN_FAULTEN_MASK (0x8000000UL) +#define PWM_DMAEN_FAULTEN_SHIFT (27U) +#define PWM_DMAEN_FAULTEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK) +#define PWM_DMAEN_FAULTEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT) + +/* + * XRLDEN (RW) + * + * extended reload flag DMA request enable + */ +#define PWM_DMAEN_XRLDEN_MASK (0x4000000UL) +#define PWM_DMAEN_XRLDEN_SHIFT (26U) +#define PWM_DMAEN_XRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK) +#define PWM_DMAEN_XRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT) + +/* + * HALFRLDEN (RW) + * + * half reload flag DMA request enable + */ +#define PWM_DMAEN_HALFRLDEN_MASK (0x2000000UL) +#define PWM_DMAEN_HALFRLDEN_SHIFT (25U) +#define PWM_DMAEN_HALFRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK) +#define PWM_DMAEN_HALFRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT) + +/* + * RLDEN (RW) + * + * reload flag DMA request enable + */ +#define PWM_DMAEN_RLDEN_MASK (0x1000000UL) +#define PWM_DMAEN_RLDEN_SHIFT (24U) +#define PWM_DMAEN_RLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK) +#define PWM_DMAEN_RLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT) + +/* + * CMPENX (RW) + * + * comparator output compare or input capture flag DMA request enable + */ +#define PWM_DMAEN_CMPENX_MASK (0xFFFFFFUL) +#define PWM_DMAEN_CMPENX_SHIFT (0U) +#define PWM_DMAEN_CMPENX_SET(x) (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK) +#define PWM_DMAEN_CMPENX_GET(x) (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT) + +/* Bitfield definition for register array: CMPCFG */ +/* + * XCNTCMPEN (RW) + * + * This bitfield enable the comparator to compare xcmp with xcnt. + */ +#define PWM_CMPCFG_XCNTCMPEN_MASK (0xF0U) +#define PWM_CMPCFG_XCNTCMPEN_SHIFT (4U) +#define PWM_CMPCFG_XCNTCMPEN_SET(x) (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK) +#define PWM_CMPCFG_XCNTCMPEN_GET(x) (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT) + +/* + * CMPSHDWUPT (RW) + * + * This bitfield select when the comparator shadow register will be loaded to its work register + * 00: after software set shlk bit of shlk register + * 01: immediately after the register being modified + * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. + * 11: after SHSYNCI assert + */ +#define PWM_CMPCFG_CMPSHDWUPT_MASK (0xCU) +#define PWM_CMPCFG_CMPSHDWUPT_SHIFT (2U) +#define PWM_CMPCFG_CMPSHDWUPT_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK) +#define PWM_CMPCFG_CMPSHDWUPT_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT) + +/* + * CMPMODE (RW) + * + * comparator mode + * 0- output compare mode + * 1- input capture mode + */ +#define PWM_CMPCFG_CMPMODE_MASK (0x2U) +#define PWM_CMPCFG_CMPMODE_SHIFT (1U) +#define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) +#define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) + + + +/* CMP register group index macro definition */ +#define PWM_CMP_0 (0UL) +#define PWM_CMP_1 (1UL) +#define PWM_CMP_2 (2UL) +#define PWM_CMP_3 (3UL) +#define PWM_CMP_4 (4UL) +#define PWM_CMP_5 (5UL) +#define PWM_CMP_6 (6UL) +#define PWM_CMP_7 (7UL) +#define PWM_CMP_8 (8UL) +#define PWM_CMP_9 (9UL) +#define PWM_CMP_10 (10UL) +#define PWM_CMP_11 (11UL) +#define PWM_CMP_12 (12UL) +#define PWM_CMP_13 (13UL) +#define PWM_CMP_14 (14UL) +#define PWM_CMP_15 (15UL) +#define PWM_CMP_16 (16UL) +#define PWM_CMP_17 (17UL) +#define PWM_CMP_18 (18UL) +#define PWM_CMP_19 (19UL) +#define PWM_CMP_20 (20UL) +#define PWM_CMP_21 (21UL) +#define PWM_CMP_22 (22UL) +#define PWM_CMP_23 (23UL) + +/* CHCFG register group index macro definition */ +#define PWM_CHCFG_0 (0UL) +#define PWM_CHCFG_1 (1UL) +#define PWM_CHCFG_2 (2UL) +#define PWM_CHCFG_3 (3UL) +#define PWM_CHCFG_4 (4UL) +#define PWM_CHCFG_5 (5UL) +#define PWM_CHCFG_6 (6UL) +#define PWM_CHCFG_7 (7UL) +#define PWM_CHCFG_8 (8UL) +#define PWM_CHCFG_9 (9UL) +#define PWM_CHCFG_10 (10UL) +#define PWM_CHCFG_11 (11UL) +#define PWM_CHCFG_12 (12UL) +#define PWM_CHCFG_13 (13UL) +#define PWM_CHCFG_14 (14UL) +#define PWM_CHCFG_15 (15UL) +#define PWM_CHCFG_16 (16UL) +#define PWM_CHCFG_17 (17UL) +#define PWM_CHCFG_18 (18UL) +#define PWM_CHCFG_19 (19UL) +#define PWM_CHCFG_20 (20UL) +#define PWM_CHCFG_21 (21UL) +#define PWM_CHCFG_22 (22UL) +#define PWM_CHCFG_23 (23UL) + +/* CAPPOS register group index macro definition */ +#define PWM_CAPPOS_0 (0UL) +#define PWM_CAPPOS_1 (1UL) +#define PWM_CAPPOS_2 (2UL) +#define PWM_CAPPOS_3 (3UL) +#define PWM_CAPPOS_4 (4UL) +#define PWM_CAPPOS_5 (5UL) +#define PWM_CAPPOS_6 (6UL) +#define PWM_CAPPOS_7 (7UL) +#define PWM_CAPPOS_8 (8UL) +#define PWM_CAPPOS_9 (9UL) +#define PWM_CAPPOS_10 (10UL) +#define PWM_CAPPOS_11 (11UL) +#define PWM_CAPPOS_12 (12UL) +#define PWM_CAPPOS_13 (13UL) +#define PWM_CAPPOS_14 (14UL) +#define PWM_CAPPOS_15 (15UL) +#define PWM_CAPPOS_16 (16UL) +#define PWM_CAPPOS_17 (17UL) +#define PWM_CAPPOS_18 (18UL) +#define PWM_CAPPOS_19 (19UL) +#define PWM_CAPPOS_20 (20UL) +#define PWM_CAPPOS_21 (21UL) +#define PWM_CAPPOS_22 (22UL) +#define PWM_CAPPOS_23 (23UL) + +/* CAPNEG register group index macro definition */ +#define PWM_CAPNEG_0 (0UL) +#define PWM_CAPNEG_1 (1UL) +#define PWM_CAPNEG_2 (2UL) +#define PWM_CAPNEG_3 (3UL) +#define PWM_CAPNEG_4 (4UL) +#define PWM_CAPNEG_5 (5UL) +#define PWM_CAPNEG_6 (6UL) +#define PWM_CAPNEG_7 (7UL) +#define PWM_CAPNEG_8 (8UL) +#define PWM_CAPNEG_9 (9UL) +#define PWM_CAPNEG_10 (10UL) +#define PWM_CAPNEG_11 (11UL) +#define PWM_CAPNEG_12 (12UL) +#define PWM_CAPNEG_13 (13UL) +#define PWM_CAPNEG_14 (14UL) +#define PWM_CAPNEG_15 (15UL) +#define PWM_CAPNEG_16 (16UL) +#define PWM_CAPNEG_17 (17UL) +#define PWM_CAPNEG_18 (18UL) +#define PWM_CAPNEG_19 (19UL) +#define PWM_CAPNEG_20 (20UL) +#define PWM_CAPNEG_21 (21UL) +#define PWM_CAPNEG_22 (22UL) +#define PWM_CAPNEG_23 (23UL) + +/* PWMCFG register group index macro definition */ +#define PWM_PWMCFG_0 (0UL) +#define PWM_PWMCFG_1 (1UL) +#define PWM_PWMCFG_2 (2UL) +#define PWM_PWMCFG_3 (3UL) +#define PWM_PWMCFG_4 (4UL) +#define PWM_PWMCFG_5 (5UL) +#define PWM_PWMCFG_6 (6UL) +#define PWM_PWMCFG_7 (7UL) + +/* CMPCFG register group index macro definition */ +#define PWM_CMPCFG_CMPCFG0 (0UL) +#define PWM_CMPCFG_1 (1UL) +#define PWM_CMPCFG_2 (2UL) +#define PWM_CMPCFG_3 (3UL) +#define PWM_CMPCFG_4 (4UL) +#define PWM_CMPCFG_5 (5UL) +#define PWM_CMPCFG_6 (6UL) +#define PWM_CMPCFG_7 (7UL) +#define PWM_CMPCFG_8 (8UL) +#define PWM_CMPCFG_9 (9UL) +#define PWM_CMPCFG_10 (10UL) +#define PWM_CMPCFG_11 (11UL) +#define PWM_CMPCFG_12 (12UL) +#define PWM_CMPCFG_13 (13UL) +#define PWM_CMPCFG_14 (14UL) +#define PWM_CMPCFG_15 (15UL) +#define PWM_CMPCFG_16 (16UL) +#define PWM_CMPCFG_17 (17UL) +#define PWM_CMPCFG_18 (18UL) +#define PWM_CMPCFG_19 (19UL) +#define PWM_CMPCFG_20 (20UL) +#define PWM_CMPCFG_21 (21UL) +#define PWM_CMPCFG_22 (22UL) +#define PWM_CMPCFG_23 (23UL) + + +#endif /* HPM_PWM_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qei_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qei_regs.h new file mode 100644 index 0000000000..64a3076195 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qei_regs.h @@ -0,0 +1,636 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_QEI_H +#define HPM_QEI_H + +typedef struct { + __RW uint32_t CR; /* 0x0: Control register */ + __RW uint32_t PHCFG; /* 0x4: Phase configure register */ + __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ + __RW uint32_t PHIDX; /* 0xC: Phase index register */ + __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ + __RW uint32_t READEN; /* 0x14: Read event enable register */ + __RW uint32_t ZCMP; /* 0x18: Z comparator */ + __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ + __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ + __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ + __RW uint32_t SR; /* 0x28: Status register */ + __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ + struct { + __RW uint32_t Z; /* 0x30: Z counter */ + __R uint32_t PH; /* 0x34: Phase counter */ + __RW uint32_t SPD; /* 0x38: Speed counter */ + __R uint32_t TMR; /* 0x3C: Timer counter */ + } COUNT[4]; + __R uint32_t SPDHIS[4]; /* 0x70 - 0x7C: Speed history */ +} QEI_Type; + + +/* Bitfield definition for register: CR */ +/* + * READ (WO) + * + * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + */ +#define QEI_CR_READ_MASK (0x80000000UL) +#define QEI_CR_READ_SHIFT (31U) +#define QEI_CR_READ_SET(x) (((uint32_t)(x) << QEI_CR_READ_SHIFT) & QEI_CR_READ_MASK) +#define QEI_CR_READ_GET(x) (((uint32_t)(x) & QEI_CR_READ_MASK) >> QEI_CR_READ_SHIFT) + +/* + * HRSTSPD (RW) + * + * 1- reset spdcnt when H assert + */ +#define QEI_CR_HRSTSPD_MASK (0x40000UL) +#define QEI_CR_HRSTSPD_SHIFT (18U) +#define QEI_CR_HRSTSPD_SET(x) (((uint32_t)(x) << QEI_CR_HRSTSPD_SHIFT) & QEI_CR_HRSTSPD_MASK) +#define QEI_CR_HRSTSPD_GET(x) (((uint32_t)(x) & QEI_CR_HRSTSPD_MASK) >> QEI_CR_HRSTSPD_SHIFT) + +/* + * HRSTPH (RW) + * + * 1- reset phcnt when H assert + */ +#define QEI_CR_HRSTPH_MASK (0x20000UL) +#define QEI_CR_HRSTPH_SHIFT (17U) +#define QEI_CR_HRSTPH_SET(x) (((uint32_t)(x) << QEI_CR_HRSTPH_SHIFT) & QEI_CR_HRSTPH_MASK) +#define QEI_CR_HRSTPH_GET(x) (((uint32_t)(x) & QEI_CR_HRSTPH_MASK) >> QEI_CR_HRSTPH_SHIFT) + +/* + * HRSTZ (RW) + * + * 1- reset zcnt when H assert + */ +#define QEI_CR_HRSTZ_MASK (0x10000UL) +#define QEI_CR_HRSTZ_SHIFT (16U) +#define QEI_CR_HRSTZ_SET(x) (((uint32_t)(x) << QEI_CR_HRSTZ_SHIFT) & QEI_CR_HRSTZ_MASK) +#define QEI_CR_HRSTZ_GET(x) (((uint32_t)(x) & QEI_CR_HRSTZ_MASK) >> QEI_CR_HRSTZ_SHIFT) + +/* + * PAUSESPD (RW) + * + * 1- pause spdcnt when PAUSE assert + */ +#define QEI_CR_PAUSESPD_MASK (0x4000U) +#define QEI_CR_PAUSESPD_SHIFT (14U) +#define QEI_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEI_CR_PAUSESPD_SHIFT) & QEI_CR_PAUSESPD_MASK) +#define QEI_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEI_CR_PAUSESPD_MASK) >> QEI_CR_PAUSESPD_SHIFT) + +/* + * PAUSEPH (RW) + * + * 1- pause phcnt when PAUSE assert + */ +#define QEI_CR_PAUSEPH_MASK (0x2000U) +#define QEI_CR_PAUSEPH_SHIFT (13U) +#define QEI_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEPH_SHIFT) & QEI_CR_PAUSEPH_MASK) +#define QEI_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEPH_MASK) >> QEI_CR_PAUSEPH_SHIFT) + +/* + * PAUSEZ (RW) + * + * 1- pause zcnt when PAUSE assert + */ +#define QEI_CR_PAUSEZ_MASK (0x1000U) +#define QEI_CR_PAUSEZ_SHIFT (12U) +#define QEI_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEZ_SHIFT) & QEI_CR_PAUSEZ_MASK) +#define QEI_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEZ_MASK) >> QEI_CR_PAUSEZ_SHIFT) + +/* + * HRDIR1 (RW) + * + * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + */ +#define QEI_CR_HRDIR1_MASK (0x800U) +#define QEI_CR_HRDIR1_SHIFT (11U) +#define QEI_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR1_SHIFT) & QEI_CR_HRDIR1_MASK) +#define QEI_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR1_MASK) >> QEI_CR_HRDIR1_SHIFT) + +/* + * HRDIR0 (RW) + * + * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + */ +#define QEI_CR_HRDIR0_MASK (0x400U) +#define QEI_CR_HRDIR0_SHIFT (10U) +#define QEI_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR0_SHIFT) & QEI_CR_HRDIR0_MASK) +#define QEI_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR0_MASK) >> QEI_CR_HRDIR0_SHIFT) + +/* + * HFDIR1 (RW) + * + * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + */ +#define QEI_CR_HFDIR1_MASK (0x200U) +#define QEI_CR_HFDIR1_SHIFT (9U) +#define QEI_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR1_SHIFT) & QEI_CR_HFDIR1_MASK) +#define QEI_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR1_MASK) >> QEI_CR_HFDIR1_SHIFT) + +/* + * HFDIR0 (RW) + * + * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + */ +#define QEI_CR_HFDIR0_MASK (0x100U) +#define QEI_CR_HFDIR0_SHIFT (8U) +#define QEI_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR0_SHIFT) & QEI_CR_HFDIR0_MASK) +#define QEI_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR0_MASK) >> QEI_CR_HFDIR0_SHIFT) + +/* + * SNAPEN (RW) + * + * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + */ +#define QEI_CR_SNAPEN_MASK (0x20U) +#define QEI_CR_SNAPEN_SHIFT (5U) +#define QEI_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEI_CR_SNAPEN_SHIFT) & QEI_CR_SNAPEN_MASK) +#define QEI_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEI_CR_SNAPEN_MASK) >> QEI_CR_SNAPEN_SHIFT) + +/* + * RSTCNT (RW) + * + * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + */ +#define QEI_CR_RSTCNT_MASK (0x10U) +#define QEI_CR_RSTCNT_SHIFT (4U) +#define QEI_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEI_CR_RSTCNT_SHIFT) & QEI_CR_RSTCNT_MASK) +#define QEI_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEI_CR_RSTCNT_MASK) >> QEI_CR_RSTCNT_SHIFT) + +/* + * ENCTYP (RW) + * + * 00-abz; 01-pd; 10-ud; 11-reserved + */ +#define QEI_CR_ENCTYP_MASK (0x3U) +#define QEI_CR_ENCTYP_SHIFT (0U) +#define QEI_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEI_CR_ENCTYP_SHIFT) & QEI_CR_ENCTYP_MASK) +#define QEI_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEI_CR_ENCTYP_MASK) >> QEI_CR_ENCTYP_SHIFT) + +/* Bitfield definition for register: PHCFG */ +/* + * ZCNTCFG (RW) + * + * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 + * 0- zcnt will increment or decrement when Z input assert + */ +#define QEI_PHCFG_ZCNTCFG_MASK (0x400000UL) +#define QEI_PHCFG_ZCNTCFG_SHIFT (22U) +#define QEI_PHCFG_ZCNTCFG_SET(x) (((uint32_t)(x) << QEI_PHCFG_ZCNTCFG_SHIFT) & QEI_PHCFG_ZCNTCFG_MASK) +#define QEI_PHCFG_ZCNTCFG_GET(x) (((uint32_t)(x) & QEI_PHCFG_ZCNTCFG_MASK) >> QEI_PHCFG_ZCNTCFG_SHIFT) + +/* + * PHCALIZ (RW) + * + * 1- phcnt will set to phidx when Z input assert + */ +#define QEI_PHCFG_PHCALIZ_MASK (0x200000UL) +#define QEI_PHCFG_PHCALIZ_SHIFT (21U) +#define QEI_PHCFG_PHCALIZ_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHCALIZ_SHIFT) & QEI_PHCFG_PHCALIZ_MASK) +#define QEI_PHCFG_PHCALIZ_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHCALIZ_MASK) >> QEI_PHCFG_PHCALIZ_SHIFT) + +/* + * PHMAX (RW) + * + * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + */ +#define QEI_PHCFG_PHMAX_MASK (0x1FFFFFUL) +#define QEI_PHCFG_PHMAX_SHIFT (0U) +#define QEI_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHMAX_SHIFT) & QEI_PHCFG_PHMAX_MASK) +#define QEI_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHMAX_MASK) >> QEI_PHCFG_PHMAX_SHIFT) + +/* Bitfield definition for register: WDGCFG */ +/* + * WDGEN (RW) + * + * 1- enable wdog counter + */ +#define QEI_WDGCFG_WDGEN_MASK (0x80000000UL) +#define QEI_WDGCFG_WDGEN_SHIFT (31U) +#define QEI_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGEN_SHIFT) & QEI_WDGCFG_WDGEN_MASK) +#define QEI_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGEN_MASK) >> QEI_WDGCFG_WDGEN_SHIFT) + +/* + * WDGTO (RW) + * + * watch dog timeout value + */ +#define QEI_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) +#define QEI_WDGCFG_WDGTO_SHIFT (0U) +#define QEI_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGTO_SHIFT) & QEI_WDGCFG_WDGTO_MASK) +#define QEI_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGTO_MASK) >> QEI_WDGCFG_WDGTO_SHIFT) + +/* Bitfield definition for register: PHIDX */ +/* + * PHIDX (RW) + * + * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + */ +#define QEI_PHIDX_PHIDX_MASK (0x1FFFFFUL) +#define QEI_PHIDX_PHIDX_SHIFT (0U) +#define QEI_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEI_PHIDX_PHIDX_SHIFT) & QEI_PHIDX_PHIDX_MASK) +#define QEI_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEI_PHIDX_PHIDX_MASK) >> QEI_PHIDX_PHIDX_SHIFT) + +/* Bitfield definition for register: TRGOEN */ +/* + * WDGFEN (RW) + * + * 1- enable trigger output when wdg flag set + */ +#define QEI_TRGOEN_WDGFEN_MASK (0x80000000UL) +#define QEI_TRGOEN_WDGFEN_SHIFT (31U) +#define QEI_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_WDGFEN_SHIFT) & QEI_TRGOEN_WDGFEN_MASK) +#define QEI_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_WDGFEN_MASK) >> QEI_TRGOEN_WDGFEN_SHIFT) + +/* + * HOMEFEN (RW) + * + * 1- enable trigger output when homef flag set + */ +#define QEI_TRGOEN_HOMEFEN_MASK (0x40000000UL) +#define QEI_TRGOEN_HOMEFEN_SHIFT (30U) +#define QEI_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_HOMEFEN_SHIFT) & QEI_TRGOEN_HOMEFEN_MASK) +#define QEI_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_HOMEFEN_MASK) >> QEI_TRGOEN_HOMEFEN_SHIFT) + +/* + * POSCMPFEN (RW) + * + * 1- enable trigger output when poscmpf flag set + */ +#define QEI_TRGOEN_POSCMPFEN_MASK (0x20000000UL) +#define QEI_TRGOEN_POSCMPFEN_SHIFT (29U) +#define QEI_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_POSCMPFEN_SHIFT) & QEI_TRGOEN_POSCMPFEN_MASK) +#define QEI_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_POSCMPFEN_MASK) >> QEI_TRGOEN_POSCMPFEN_SHIFT) + +/* + * ZPHFEN (RW) + * + * 1- enable trigger output when zphf flag set + */ +#define QEI_TRGOEN_ZPHFEN_MASK (0x10000000UL) +#define QEI_TRGOEN_ZPHFEN_SHIFT (28U) +#define QEI_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_ZPHFEN_SHIFT) & QEI_TRGOEN_ZPHFEN_MASK) +#define QEI_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_ZPHFEN_MASK) >> QEI_TRGOEN_ZPHFEN_SHIFT) + +/* Bitfield definition for register: READEN */ +/* + * WDGFEN (RW) + * + * 1- load counters to their read registers when wdg flag set + */ +#define QEI_READEN_WDGFEN_MASK (0x80000000UL) +#define QEI_READEN_WDGFEN_SHIFT (31U) +#define QEI_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_READEN_WDGFEN_SHIFT) & QEI_READEN_WDGFEN_MASK) +#define QEI_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_READEN_WDGFEN_MASK) >> QEI_READEN_WDGFEN_SHIFT) + +/* + * HOMEFEN (RW) + * + * 1- load counters to their read registers when homef flag set + */ +#define QEI_READEN_HOMEFEN_MASK (0x40000000UL) +#define QEI_READEN_HOMEFEN_SHIFT (30U) +#define QEI_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_READEN_HOMEFEN_SHIFT) & QEI_READEN_HOMEFEN_MASK) +#define QEI_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_READEN_HOMEFEN_MASK) >> QEI_READEN_HOMEFEN_SHIFT) + +/* + * POSCMPFEN (RW) + * + * 1- load counters to their read registers when poscmpf flag set + */ +#define QEI_READEN_POSCMPFEN_MASK (0x20000000UL) +#define QEI_READEN_POSCMPFEN_SHIFT (29U) +#define QEI_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_READEN_POSCMPFEN_SHIFT) & QEI_READEN_POSCMPFEN_MASK) +#define QEI_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_READEN_POSCMPFEN_MASK) >> QEI_READEN_POSCMPFEN_SHIFT) + +/* + * ZPHFEN (RW) + * + * 1- load counters to their read registers when zphf flag set + */ +#define QEI_READEN_ZPHFEN_MASK (0x10000000UL) +#define QEI_READEN_ZPHFEN_SHIFT (28U) +#define QEI_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_READEN_ZPHFEN_SHIFT) & QEI_READEN_ZPHFEN_MASK) +#define QEI_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_READEN_ZPHFEN_MASK) >> QEI_READEN_ZPHFEN_SHIFT) + +/* Bitfield definition for register: ZCMP */ +/* + * ZCMP (RW) + * + * zcnt postion compare value + */ +#define QEI_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) +#define QEI_ZCMP_ZCMP_SHIFT (0U) +#define QEI_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEI_ZCMP_ZCMP_SHIFT) & QEI_ZCMP_ZCMP_MASK) +#define QEI_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEI_ZCMP_ZCMP_MASK) >> QEI_ZCMP_ZCMP_SHIFT) + +/* Bitfield definition for register: PHCMP */ +/* + * ZCMPDIS (RW) + * + * 1- postion compare not include zcnt + */ +#define QEI_PHCMP_ZCMPDIS_MASK (0x80000000UL) +#define QEI_PHCMP_ZCMPDIS_SHIFT (31U) +#define QEI_PHCMP_ZCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_ZCMPDIS_SHIFT) & QEI_PHCMP_ZCMPDIS_MASK) +#define QEI_PHCMP_ZCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_ZCMPDIS_MASK) >> QEI_PHCMP_ZCMPDIS_SHIFT) + +/* + * DIRCMPDIS (RW) + * + * 1- postion compare not include rotation direction + */ +#define QEI_PHCMP_DIRCMPDIS_MASK (0x40000000UL) +#define QEI_PHCMP_DIRCMPDIS_SHIFT (30U) +#define QEI_PHCMP_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMPDIS_SHIFT) & QEI_PHCMP_DIRCMPDIS_MASK) +#define QEI_PHCMP_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMPDIS_MASK) >> QEI_PHCMP_DIRCMPDIS_SHIFT) + +/* + * DIRCMP (RW) + * + * 0- position compare need positive rotation + * 1- position compare need negative rotation + */ +#define QEI_PHCMP_DIRCMP_MASK (0x20000000UL) +#define QEI_PHCMP_DIRCMP_SHIFT (29U) +#define QEI_PHCMP_DIRCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMP_SHIFT) & QEI_PHCMP_DIRCMP_MASK) +#define QEI_PHCMP_DIRCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMP_MASK) >> QEI_PHCMP_DIRCMP_SHIFT) + +/* + * PHCMP (RW) + * + * phcnt position compare value + */ +#define QEI_PHCMP_PHCMP_MASK (0x1FFFFFUL) +#define QEI_PHCMP_PHCMP_SHIFT (0U) +#define QEI_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_PHCMP_SHIFT) & QEI_PHCMP_PHCMP_MASK) +#define QEI_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_PHCMP_MASK) >> QEI_PHCMP_PHCMP_SHIFT) + +/* Bitfield definition for register: SPDCMP */ +/* + * SPDCMP (RW) + * + * spdcnt position compare value + */ +#define QEI_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) +#define QEI_SPDCMP_SPDCMP_SHIFT (0U) +#define QEI_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEI_SPDCMP_SPDCMP_SHIFT) & QEI_SPDCMP_SPDCMP_MASK) +#define QEI_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEI_SPDCMP_SPDCMP_MASK) >> QEI_SPDCMP_SPDCMP_SHIFT) + +/* Bitfield definition for register: DMAEN */ +/* + * WDGFEN (RW) + * + * 1- generate dma request when wdg flag set + */ +#define QEI_DMAEN_WDGFEN_MASK (0x80000000UL) +#define QEI_DMAEN_WDGFEN_SHIFT (31U) +#define QEI_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_WDGFEN_SHIFT) & QEI_DMAEN_WDGFEN_MASK) +#define QEI_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_WDGFEN_MASK) >> QEI_DMAEN_WDGFEN_SHIFT) + +/* + * HOMEFEN (RW) + * + * 1- generate dma request when homef flag set + */ +#define QEI_DMAEN_HOMEFEN_MASK (0x40000000UL) +#define QEI_DMAEN_HOMEFEN_SHIFT (30U) +#define QEI_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_HOMEFEN_SHIFT) & QEI_DMAEN_HOMEFEN_MASK) +#define QEI_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_HOMEFEN_MASK) >> QEI_DMAEN_HOMEFEN_SHIFT) + +/* + * POSCMPFEN (RW) + * + * 1- generate dma request when poscmpf flag set + */ +#define QEI_DMAEN_POSCMPFEN_MASK (0x20000000UL) +#define QEI_DMAEN_POSCMPFEN_SHIFT (29U) +#define QEI_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_POSCMPFEN_SHIFT) & QEI_DMAEN_POSCMPFEN_MASK) +#define QEI_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_POSCMPFEN_MASK) >> QEI_DMAEN_POSCMPFEN_SHIFT) + +/* + * ZPHFEN (RW) + * + * 1- generate dma request when zphf flag set + */ +#define QEI_DMAEN_ZPHFEN_MASK (0x10000000UL) +#define QEI_DMAEN_ZPHFEN_SHIFT (28U) +#define QEI_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_ZPHFEN_SHIFT) & QEI_DMAEN_ZPHFEN_MASK) +#define QEI_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_ZPHFEN_MASK) >> QEI_DMAEN_ZPHFEN_SHIFT) + +/* Bitfield definition for register: SR */ +/* + * WDGF (RW) + * + * watchdog flag + */ +#define QEI_SR_WDGF_MASK (0x80000000UL) +#define QEI_SR_WDGF_SHIFT (31U) +#define QEI_SR_WDGF_SET(x) (((uint32_t)(x) << QEI_SR_WDGF_SHIFT) & QEI_SR_WDGF_MASK) +#define QEI_SR_WDGF_GET(x) (((uint32_t)(x) & QEI_SR_WDGF_MASK) >> QEI_SR_WDGF_SHIFT) + +/* + * HOMEF (RW) + * + * home flag + */ +#define QEI_SR_HOMEF_MASK (0x40000000UL) +#define QEI_SR_HOMEF_SHIFT (30U) +#define QEI_SR_HOMEF_SET(x) (((uint32_t)(x) << QEI_SR_HOMEF_SHIFT) & QEI_SR_HOMEF_MASK) +#define QEI_SR_HOMEF_GET(x) (((uint32_t)(x) & QEI_SR_HOMEF_MASK) >> QEI_SR_HOMEF_SHIFT) + +/* + * POSCMPF (RW) + * + * postion compare match flag + */ +#define QEI_SR_POSCMPF_MASK (0x20000000UL) +#define QEI_SR_POSCMPF_SHIFT (29U) +#define QEI_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEI_SR_POSCMPF_SHIFT) & QEI_SR_POSCMPF_MASK) +#define QEI_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEI_SR_POSCMPF_MASK) >> QEI_SR_POSCMPF_SHIFT) + +/* + * ZPHF (RW) + * + * z input flag + */ +#define QEI_SR_ZPHF_MASK (0x10000000UL) +#define QEI_SR_ZPHF_SHIFT (28U) +#define QEI_SR_ZPHF_SET(x) (((uint32_t)(x) << QEI_SR_ZPHF_SHIFT) & QEI_SR_ZPHF_MASK) +#define QEI_SR_ZPHF_GET(x) (((uint32_t)(x) & QEI_SR_ZPHF_MASK) >> QEI_SR_ZPHF_SHIFT) + +/* Bitfield definition for register: IRQEN */ +/* + * WDGIE (RW) + * + * 1- generate interrupt when wdg flag set + */ +#define QEI_IRQEN_WDGIE_MASK (0x80000000UL) +#define QEI_IRQEN_WDGIE_SHIFT (31U) +#define QEI_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_WDGIE_SHIFT) & QEI_IRQEN_WDGIE_MASK) +#define QEI_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_WDGIE_MASK) >> QEI_IRQEN_WDGIE_SHIFT) + +/* + * HOMEIE (RW) + * + * 1- generate interrupt when homef flag set + */ +#define QEI_IRQEN_HOMEIE_MASK (0x40000000UL) +#define QEI_IRQEN_HOMEIE_SHIFT (30U) +#define QEI_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_HOMEIE_SHIFT) & QEI_IRQEN_HOMEIE_MASK) +#define QEI_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_HOMEIE_MASK) >> QEI_IRQEN_HOMEIE_SHIFT) + +/* + * POSCMPIE (RW) + * + * 1- generate interrupt when poscmpf flag set + */ +#define QEI_IRQEN_POSCMPIE_MASK (0x20000000UL) +#define QEI_IRQEN_POSCMPIE_SHIFT (29U) +#define QEI_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_POSCMPIE_SHIFT) & QEI_IRQEN_POSCMPIE_MASK) +#define QEI_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_POSCMPIE_MASK) >> QEI_IRQEN_POSCMPIE_SHIFT) + +/* + * ZPHIE (RW) + * + * 1- generate interrupt when zphf flag set + */ +#define QEI_IRQEN_ZPHIE_MASK (0x10000000UL) +#define QEI_IRQEN_ZPHIE_SHIFT (28U) +#define QEI_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_ZPHIE_SHIFT) & QEI_IRQEN_ZPHIE_MASK) +#define QEI_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_ZPHIE_MASK) >> QEI_IRQEN_ZPHIE_SHIFT) + +/* Bitfield definition for register of struct array COUNT: Z */ +/* + * ZCNT (RW) + * + * zcnt value + */ +#define QEI_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) +#define QEI_COUNT_Z_ZCNT_SHIFT (0U) +#define QEI_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEI_COUNT_Z_ZCNT_SHIFT) & QEI_COUNT_Z_ZCNT_MASK) +#define QEI_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_Z_ZCNT_MASK) >> QEI_COUNT_Z_ZCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: PH */ +/* + * DIR (RO) + * + * 1- reverse rotation + * 0- forward rotation + */ +#define QEI_COUNT_PH_DIR_MASK (0x40000000UL) +#define QEI_COUNT_PH_DIR_SHIFT (30U) +#define QEI_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_DIR_MASK) >> QEI_COUNT_PH_DIR_SHIFT) + +/* + * ASTAT (RO) + * + * 1- a input is high + * 0- a input is low + */ +#define QEI_COUNT_PH_ASTAT_MASK (0x4000000UL) +#define QEI_COUNT_PH_ASTAT_SHIFT (26U) +#define QEI_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_ASTAT_MASK) >> QEI_COUNT_PH_ASTAT_SHIFT) + +/* + * BSTAT (RO) + * + * 1- b input is high + * 0- b input is low + */ +#define QEI_COUNT_PH_BSTAT_MASK (0x2000000UL) +#define QEI_COUNT_PH_BSTAT_SHIFT (25U) +#define QEI_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_BSTAT_MASK) >> QEI_COUNT_PH_BSTAT_SHIFT) + +/* + * PHCNT (RO) + * + * phcnt value + */ +#define QEI_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) +#define QEI_COUNT_PH_PHCNT_SHIFT (0U) +#define QEI_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_PHCNT_MASK) >> QEI_COUNT_PH_PHCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: SPD */ +/* + * DIR (RO) + * + * 1- reverse rotation + * 0- forward rotation + */ +#define QEI_COUNT_SPD_DIR_MASK (0x80000000UL) +#define QEI_COUNT_SPD_DIR_SHIFT (31U) +#define QEI_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_DIR_MASK) >> QEI_COUNT_SPD_DIR_SHIFT) + +/* + * ASTAT (RO) + * + * 1- a input is high + * 0- a input is low + */ +#define QEI_COUNT_SPD_ASTAT_MASK (0x40000000UL) +#define QEI_COUNT_SPD_ASTAT_SHIFT (30U) +#define QEI_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_ASTAT_MASK) >> QEI_COUNT_SPD_ASTAT_SHIFT) + +/* + * BSTAT (RW) + * + * 1- b input is high + * 0- b input is low + */ +#define QEI_COUNT_SPD_BSTAT_MASK (0x20000000UL) +#define QEI_COUNT_SPD_BSTAT_SHIFT (29U) +#define QEI_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEI_COUNT_SPD_BSTAT_SHIFT) & QEI_COUNT_SPD_BSTAT_MASK) +#define QEI_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_BSTAT_MASK) >> QEI_COUNT_SPD_BSTAT_SHIFT) + +/* + * SPDCNT (RO) + * + * spdcnt value + */ +#define QEI_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) +#define QEI_COUNT_SPD_SPDCNT_SHIFT (0U) +#define QEI_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_SPDCNT_MASK) >> QEI_COUNT_SPD_SPDCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: TMR */ +/* + * TMRCNT (RO) + * + * 32 bit free run timer + */ +#define QEI_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) +#define QEI_COUNT_TMR_TMRCNT_SHIFT (0U) +#define QEI_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_TMR_TMRCNT_MASK) >> QEI_COUNT_TMR_TMRCNT_SHIFT) + +/* Bitfield definition for register array: SPDHIS */ +/* + * SPDHIS0 (RO) + * + * copy of spdcnt, load from spdcnt after any transition from a = low, b = low + */ +#define QEI_SPDHIS_SPDHIS0_MASK (0xFFFFFFFFUL) +#define QEI_SPDHIS_SPDHIS0_SHIFT (0U) +#define QEI_SPDHIS_SPDHIS0_GET(x) (((uint32_t)(x) & QEI_SPDHIS_SPDHIS0_MASK) >> QEI_SPDHIS_SPDHIS0_SHIFT) + + + +/* COUNT register group index macro definition */ +#define QEI_COUNT_CURRENT (0UL) +#define QEI_COUNT_READ (1UL) +#define QEI_COUNT_SNAP0 (2UL) +#define QEI_COUNT_SNAP1 (3UL) + +/* SPDHIS register group index macro definition */ +#define QEI_SPDHIS_SPDHIS0 (0UL) +#define QEI_SPDHIS_SPDHIS1 (1UL) +#define QEI_SPDHIS_SPDHIS2 (2UL) +#define QEI_SPDHIS_SPDHIS3 (3UL) + + +#endif /* HPM_QEI_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rng_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rng_regs.h new file mode 100644 index 0000000000..c58a7ecd9f --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rng_regs.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_RNG_H +#define HPM_RNG_H + +typedef struct { + __RW uint32_t CMD; /* 0x0: Command Register */ + __RW uint32_t CTRL; /* 0x4: Control Register */ + __R uint32_t STA; /* 0x8: Status Register */ + __R uint32_t ERR; /* 0xC: Error Registers */ + __R uint32_t FO2B; /* 0x10: FIFO out to bus/cpu */ + __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ + __R uint32_t R2SK[8]; /* 0x20 - 0x3C: FIFO out to SDP as AES engine key */ +} RNG_Type; + + +/* Bitfield definition for register: CMD */ +/* + * SFTRST (RW) + * + * Soft Reset, Perform a software reset of the RNG This bit is self-clearing. + * 0 Do not perform a software reset. + * 1 Software reset + */ +#define RNG_CMD_SFTRST_MASK (0x40U) +#define RNG_CMD_SFTRST_SHIFT (6U) +#define RNG_CMD_SFTRST_SET(x) (((uint32_t)(x) << RNG_CMD_SFTRST_SHIFT) & RNG_CMD_SFTRST_MASK) +#define RNG_CMD_SFTRST_GET(x) (((uint32_t)(x) & RNG_CMD_SFTRST_MASK) >> RNG_CMD_SFTRST_SHIFT) + +/* + * CLRERR (RW) + * + * Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. + * 0 Do not clear the errors and the interrupt. + * 1 Clear the errors and the interrupt. + */ +#define RNG_CMD_CLRERR_MASK (0x20U) +#define RNG_CMD_CLRERR_SHIFT (5U) +#define RNG_CMD_CLRERR_SET(x) (((uint32_t)(x) << RNG_CMD_CLRERR_SHIFT) & RNG_CMD_CLRERR_MASK) +#define RNG_CMD_CLRERR_GET(x) (((uint32_t)(x) & RNG_CMD_CLRERR_MASK) >> RNG_CMD_CLRERR_SHIFT) + +/* + * CLRINT (RW) + * + * Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. + * 0 Do not clear the interrupt. + * 1 Clear the interrupt + */ +#define RNG_CMD_CLRINT_MASK (0x10U) +#define RNG_CMD_CLRINT_SHIFT (4U) +#define RNG_CMD_CLRINT_SET(x) (((uint32_t)(x) << RNG_CMD_CLRINT_SHIFT) & RNG_CMD_CLRINT_MASK) +#define RNG_CMD_CLRINT_GET(x) (((uint32_t)(x) & RNG_CMD_CLRINT_MASK) >> RNG_CMD_CLRINT_SHIFT) + +/* + * GENSD (RW) + * + * Generate Seed, when both ST and GS triggered, ST first and GS next. + */ +#define RNG_CMD_GENSD_MASK (0x2U) +#define RNG_CMD_GENSD_SHIFT (1U) +#define RNG_CMD_GENSD_SET(x) (((uint32_t)(x) << RNG_CMD_GENSD_SHIFT) & RNG_CMD_GENSD_MASK) +#define RNG_CMD_GENSD_GET(x) (((uint32_t)(x) & RNG_CMD_GENSD_MASK) >> RNG_CMD_GENSD_SHIFT) + +/* + * SLFCHK (RW) + * + * Self Test, when both ST and GS triggered, ST first and GS next. + */ +#define RNG_CMD_SLFCHK_MASK (0x1U) +#define RNG_CMD_SLFCHK_SHIFT (0U) +#define RNG_CMD_SLFCHK_SET(x) (((uint32_t)(x) << RNG_CMD_SLFCHK_SHIFT) & RNG_CMD_SLFCHK_MASK) +#define RNG_CMD_SLFCHK_GET(x) (((uint32_t)(x) & RNG_CMD_SLFCHK_MASK) >> RNG_CMD_SLFCHK_SHIFT) + +/* Bitfield definition for register: CTRL */ +/* + * MIRQERR (RW) + * + * Mask Interrupt Request for Error + */ +#define RNG_CTRL_MIRQERR_MASK (0x40U) +#define RNG_CTRL_MIRQERR_SHIFT (6U) +#define RNG_CTRL_MIRQERR_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQERR_SHIFT) & RNG_CTRL_MIRQERR_MASK) +#define RNG_CTRL_MIRQERR_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQERR_MASK) >> RNG_CTRL_MIRQERR_SHIFT) + +/* + * MIRQDN (RW) + * + * Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: + * • Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). + * • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + */ +#define RNG_CTRL_MIRQDN_MASK (0x20U) +#define RNG_CTRL_MIRQDN_SHIFT (5U) +#define RNG_CTRL_MIRQDN_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQDN_SHIFT) & RNG_CTRL_MIRQDN_MASK) +#define RNG_CTRL_MIRQDN_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQDN_MASK) >> RNG_CTRL_MIRQDN_SHIFT) + +/* + * AUTRSD (RW) + * + * Auto Reseed + */ +#define RNG_CTRL_AUTRSD_MASK (0x10U) +#define RNG_CTRL_AUTRSD_SHIFT (4U) +#define RNG_CTRL_AUTRSD_SET(x) (((uint32_t)(x) << RNG_CTRL_AUTRSD_SHIFT) & RNG_CTRL_AUTRSD_MASK) +#define RNG_CTRL_AUTRSD_GET(x) (((uint32_t)(x) & RNG_CTRL_AUTRSD_MASK) >> RNG_CTRL_AUTRSD_SHIFT) + +/* + * FUFMOD (RW) + * + * FIFO underflow response mode + * 00 Return all zeros and set the ESR[FUFE]. + * 01 Return all zeros and set the ESR[FUFE]. + * 10 Generate the bus transfer error + * 11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + */ +#define RNG_CTRL_FUFMOD_MASK (0x3U) +#define RNG_CTRL_FUFMOD_SHIFT (0U) +#define RNG_CTRL_FUFMOD_SET(x) (((uint32_t)(x) << RNG_CTRL_FUFMOD_SHIFT) & RNG_CTRL_FUFMOD_MASK) +#define RNG_CTRL_FUFMOD_GET(x) (((uint32_t)(x) & RNG_CTRL_FUFMOD_MASK) >> RNG_CTRL_FUFMOD_SHIFT) + +/* Bitfield definition for register: STA */ +/* + * SCPF (RO) + * + * Self Check Pass Fail + */ +#define RNG_STA_SCPF_MASK (0xE00000UL) +#define RNG_STA_SCPF_SHIFT (21U) +#define RNG_STA_SCPF_GET(x) (((uint32_t)(x) & RNG_STA_SCPF_MASK) >> RNG_STA_SCPF_SHIFT) + +/* + * FUNCERR (RO) + * + * Error was detected, check ESR register for details + */ +#define RNG_STA_FUNCERR_MASK (0x10000UL) +#define RNG_STA_FUNCERR_SHIFT (16U) +#define RNG_STA_FUNCERR_GET(x) (((uint32_t)(x) & RNG_STA_FUNCERR_MASK) >> RNG_STA_FUNCERR_SHIFT) + +/* + * FSIZE (RO) + * + * Fifo Size, it is 5 in this design. + */ +#define RNG_STA_FSIZE_MASK (0xF000U) +#define RNG_STA_FSIZE_SHIFT (12U) +#define RNG_STA_FSIZE_GET(x) (((uint32_t)(x) & RNG_STA_FSIZE_MASK) >> RNG_STA_FSIZE_SHIFT) + +/* + * FRNNU (RO) + * + * Fifo Level, Indicates the number of random words currently in the output FIFO + */ +#define RNG_STA_FRNNU_MASK (0xF00U) +#define RNG_STA_FRNNU_SHIFT (8U) +#define RNG_STA_FRNNU_GET(x) (((uint32_t)(x) & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT) + +/* + * NSDDN (RO) + * + * New seed done. + */ +#define RNG_STA_NSDDN_MASK (0x40U) +#define RNG_STA_NSDDN_SHIFT (6U) +#define RNG_STA_NSDDN_GET(x) (((uint32_t)(x) & RNG_STA_NSDDN_MASK) >> RNG_STA_NSDDN_SHIFT) + +/* + * FSDDN (RO) + * + * 1st Seed done + * When "1", Indicates that the RNG generated the first seed. + */ +#define RNG_STA_FSDDN_MASK (0x20U) +#define RNG_STA_FSDDN_SHIFT (5U) +#define RNG_STA_FSDDN_GET(x) (((uint32_t)(x) & RNG_STA_FSDDN_MASK) >> RNG_STA_FSDDN_SHIFT) + +/* + * SCDN (RO) + * + * Self Check Done + * Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is + * initiated by setting the CMD[ST]. + * 0 Self test not completed + * 1 Completed a self test since the last reset. + */ +#define RNG_STA_SCDN_MASK (0x10U) +#define RNG_STA_SCDN_SHIFT (4U) +#define RNG_STA_SCDN_GET(x) (((uint32_t)(x) & RNG_STA_SCDN_MASK) >> RNG_STA_SCDN_SHIFT) + +/* + * RSDREQ (RO) + * + * Reseed needed + * Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or + * automatically if the CTRL[ARS] is set. + */ +#define RNG_STA_RSDREQ_MASK (0x8U) +#define RNG_STA_RSDREQ_SHIFT (3U) +#define RNG_STA_RSDREQ_GET(x) (((uint32_t)(x) & RNG_STA_RSDREQ_MASK) >> RNG_STA_RSDREQ_SHIFT) + +/* + * IDLE (RO) + * + * Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + */ +#define RNG_STA_IDLE_MASK (0x4U) +#define RNG_STA_IDLE_SHIFT (2U) +#define RNG_STA_IDLE_GET(x) (((uint32_t)(x) & RNG_STA_IDLE_MASK) >> RNG_STA_IDLE_SHIFT) + +/* + * BUSY (RO) + * + * when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + */ +#define RNG_STA_BUSY_MASK (0x2U) +#define RNG_STA_BUSY_SHIFT (1U) +#define RNG_STA_BUSY_GET(x) (((uint32_t)(x) & RNG_STA_BUSY_MASK) >> RNG_STA_BUSY_SHIFT) + +/* Bitfield definition for register: ERR */ +/* + * FUFE (RO) + * + * FIFO access error(underflow) + */ +#define RNG_ERR_FUFE_MASK (0x20U) +#define RNG_ERR_FUFE_SHIFT (5U) +#define RNG_ERR_FUFE_GET(x) (((uint32_t)(x) & RNG_ERR_FUFE_MASK) >> RNG_ERR_FUFE_SHIFT) + +/* + * SCKERR (RO) + * + * Self-test error + * Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a + * hardware reset or by writing 1 to the CMD[CE] + */ +#define RNG_ERR_SCKERR_MASK (0x8U) +#define RNG_ERR_SCKERR_SHIFT (3U) +#define RNG_ERR_SCKERR_GET(x) (((uint32_t)(x) & RNG_ERR_SCKERR_MASK) >> RNG_ERR_SCKERR_SHIFT) + +/* Bitfield definition for register: FO2B */ +/* + * FO2B (RO) + * + * SW read the FIFO output. + */ +#define RNG_FO2B_FO2B_MASK (0xFFFFFFFFUL) +#define RNG_FO2B_FO2B_SHIFT (0U) +#define RNG_FO2B_FO2B_GET(x) (((uint32_t)(x) & RNG_FO2B_FO2B_MASK) >> RNG_FO2B_FO2B_SHIFT) + +/* Bitfield definition for register array: R2SK */ +/* + * FO2S0 (RO) + * + * FIFO out to KMAN, will be SDP engine key. + */ +#define RNG_R2SK_FO2S0_MASK (0xFFFFFFFFUL) +#define RNG_R2SK_FO2S0_SHIFT (0U) +#define RNG_R2SK_FO2S0_GET(x) (((uint32_t)(x) & RNG_R2SK_FO2S0_MASK) >> RNG_R2SK_FO2S0_SHIFT) + + + +/* R2SK register group index macro definition */ +#define RNG_R2SK_FO2S0 (0UL) +#define RNG_R2SK_FO2S1 (1UL) +#define RNG_R2SK_FO2S2 (2UL) +#define RNG_R2SK_FO2S3 (3UL) +#define RNG_R2SK_FO2S4 (4UL) +#define RNG_R2SK_FO2S5 (5UL) +#define RNG_R2SK_FO2S6 (6UL) +#define RNG_R2SK_FO2S7 (7UL) + + +#endif /* HPM_RNG_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rtc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rtc_regs.h new file mode 100644 index 0000000000..e796e9c761 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rtc_regs.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_RTC_H +#define HPM_RTC_H + +typedef struct { + __RW uint32_t SECOND; /* 0x0: Second counter */ + __R uint32_t SUBSEC; /* 0x4: Sub-second counter */ + __RW uint32_t SEC_SNAP; /* 0x8: Second counter snap shot */ + __RW uint32_t SUB_SNAP; /* 0xC: Sub-second counter snap shot */ + __RW uint32_t ALARM0; /* 0x10: RTC alarm0 */ + __RW uint32_t ALARM0_INC; /* 0x14: Alarm0 incremental */ + __RW uint32_t ALARM1; /* 0x18: RTC alarm1 */ + __RW uint32_t ALARM1_INC; /* 0x1C: Alarm1 incremental */ + __RW uint32_t ALARM_FLAG; /* 0x20: RTC alarm flag */ + __RW uint32_t ALARM_EN; /* 0x24: RTC alarm enable */ +} RTC_Type; + + +/* Bitfield definition for register: SECOND */ +/* + * SECOND (RW) + * + * second counter + */ +#define RTC_SECOND_SECOND_MASK (0xFFFFFFFFUL) +#define RTC_SECOND_SECOND_SHIFT (0U) +#define RTC_SECOND_SECOND_SET(x) (((uint32_t)(x) << RTC_SECOND_SECOND_SHIFT) & RTC_SECOND_SECOND_MASK) +#define RTC_SECOND_SECOND_GET(x) (((uint32_t)(x) & RTC_SECOND_SECOND_MASK) >> RTC_SECOND_SECOND_SHIFT) + +/* Bitfield definition for register: SUBSEC */ +/* + * SUBSEC (RO) + * + * sub second counter + */ +#define RTC_SUBSEC_SUBSEC_MASK (0xFFFFFFFFUL) +#define RTC_SUBSEC_SUBSEC_SHIFT (0U) +#define RTC_SUBSEC_SUBSEC_GET(x) (((uint32_t)(x) & RTC_SUBSEC_SUBSEC_MASK) >> RTC_SUBSEC_SUBSEC_SHIFT) + +/* Bitfield definition for register: SEC_SNAP */ +/* + * SEC_SNAP (RW) + * + * second snap shot, write to take snap shot + */ +#define RTC_SEC_SNAP_SEC_SNAP_MASK (0xFFFFFFFFUL) +#define RTC_SEC_SNAP_SEC_SNAP_SHIFT (0U) +#define RTC_SEC_SNAP_SEC_SNAP_SET(x) (((uint32_t)(x) << RTC_SEC_SNAP_SEC_SNAP_SHIFT) & RTC_SEC_SNAP_SEC_SNAP_MASK) +#define RTC_SEC_SNAP_SEC_SNAP_GET(x) (((uint32_t)(x) & RTC_SEC_SNAP_SEC_SNAP_MASK) >> RTC_SEC_SNAP_SEC_SNAP_SHIFT) + +/* Bitfield definition for register: SUB_SNAP */ +/* + * SUB_SNAP (RW) + * + * sub second snap shot, write to take snap shot + */ +#define RTC_SUB_SNAP_SUB_SNAP_MASK (0xFFFFFFFFUL) +#define RTC_SUB_SNAP_SUB_SNAP_SHIFT (0U) +#define RTC_SUB_SNAP_SUB_SNAP_SET(x) (((uint32_t)(x) << RTC_SUB_SNAP_SUB_SNAP_SHIFT) & RTC_SUB_SNAP_SUB_SNAP_MASK) +#define RTC_SUB_SNAP_SUB_SNAP_GET(x) (((uint32_t)(x) & RTC_SUB_SNAP_SUB_SNAP_MASK) >> RTC_SUB_SNAP_SUB_SNAP_SHIFT) + +/* Bitfield definition for register: ALARM0 */ +/* + * ALARM (RW) + * + * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + */ +#define RTC_ALARM0_ALARM_MASK (0xFFFFFFFFUL) +#define RTC_ALARM0_ALARM_SHIFT (0U) +#define RTC_ALARM0_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM0_ALARM_SHIFT) & RTC_ALARM0_ALARM_MASK) +#define RTC_ALARM0_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM0_ALARM_MASK) >> RTC_ALARM0_ALARM_SHIFT) + +/* Bitfield definition for register: ALARM0_INC */ +/* + * INCREASE (RW) + * + * adder when ARLAM0 happen, helps to create periodical alarm + */ +#define RTC_ALARM0_INC_INCREASE_MASK (0xFFFFFFFFUL) +#define RTC_ALARM0_INC_INCREASE_SHIFT (0U) +#define RTC_ALARM0_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM0_INC_INCREASE_SHIFT) & RTC_ALARM0_INC_INCREASE_MASK) +#define RTC_ALARM0_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM0_INC_INCREASE_MASK) >> RTC_ALARM0_INC_INCREASE_SHIFT) + +/* Bitfield definition for register: ALARM1 */ +/* + * ALARM (RW) + * + * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + */ +#define RTC_ALARM1_ALARM_MASK (0xFFFFFFFFUL) +#define RTC_ALARM1_ALARM_SHIFT (0U) +#define RTC_ALARM1_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM1_ALARM_SHIFT) & RTC_ALARM1_ALARM_MASK) +#define RTC_ALARM1_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM1_ALARM_MASK) >> RTC_ALARM1_ALARM_SHIFT) + +/* Bitfield definition for register: ALARM1_INC */ +/* + * INCREASE (RW) + * + * adder when ARLAM0 happen, helps to create periodical alarm + */ +#define RTC_ALARM1_INC_INCREASE_MASK (0xFFFFFFFFUL) +#define RTC_ALARM1_INC_INCREASE_SHIFT (0U) +#define RTC_ALARM1_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM1_INC_INCREASE_SHIFT) & RTC_ALARM1_INC_INCREASE_MASK) +#define RTC_ALARM1_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM1_INC_INCREASE_MASK) >> RTC_ALARM1_INC_INCREASE_SHIFT) + +/* Bitfield definition for register: ALARM_FLAG */ +/* + * ALARM1 (RW) + * + * alarm1 happen + */ +#define RTC_ALARM_FLAG_ALARM1_MASK (0x2U) +#define RTC_ALARM_FLAG_ALARM1_SHIFT (1U) +#define RTC_ALARM_FLAG_ALARM1_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM1_SHIFT) & RTC_ALARM_FLAG_ALARM1_MASK) +#define RTC_ALARM_FLAG_ALARM1_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM1_MASK) >> RTC_ALARM_FLAG_ALARM1_SHIFT) + +/* + * ALARM0 (RW) + * + * alarm0 happen + */ +#define RTC_ALARM_FLAG_ALARM0_MASK (0x1U) +#define RTC_ALARM_FLAG_ALARM0_SHIFT (0U) +#define RTC_ALARM_FLAG_ALARM0_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM0_SHIFT) & RTC_ALARM_FLAG_ALARM0_MASK) +#define RTC_ALARM_FLAG_ALARM0_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM0_MASK) >> RTC_ALARM_FLAG_ALARM0_SHIFT) + +/* Bitfield definition for register: ALARM_EN */ +/* + * ENABLE1 (RW) + * + * alarm1 mask + * 0: alarm1 disabled + * 1: alarm1 enabled + */ +#define RTC_ALARM_EN_ENABLE1_MASK (0x2U) +#define RTC_ALARM_EN_ENABLE1_SHIFT (1U) +#define RTC_ALARM_EN_ENABLE1_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE1_SHIFT) & RTC_ALARM_EN_ENABLE1_MASK) +#define RTC_ALARM_EN_ENABLE1_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE1_MASK) >> RTC_ALARM_EN_ENABLE1_SHIFT) + +/* + * ENABLE0 (RW) + * + * alarm0 mask + * 0: alarm0 disabled + * 1: alarm0 enabled + */ +#define RTC_ALARM_EN_ENABLE0_MASK (0x1U) +#define RTC_ALARM_EN_ENABLE0_SHIFT (0U) +#define RTC_ALARM_EN_ENABLE0_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE0_SHIFT) & RTC_ALARM_EN_ENABLE0_MASK) +#define RTC_ALARM_EN_ENABLE0_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE0_MASK) >> RTC_ALARM_EN_ENABLE0_SHIFT) + + + + +#endif /* HPM_RTC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h new file mode 100644 index 0000000000..d2548d27e0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h @@ -0,0 +1,672 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SDP_H +#define HPM_SDP_H + +typedef struct { + __RW uint32_t SDPCR; /* 0x0: SDP control register */ + __RW uint32_t MODCTRL; /* 0x4: Mod control register. */ + __RW uint32_t PKTCNT; /* 0x8: packet counter registers. */ + __RW uint32_t STA; /* 0xC: Status Registers */ + __RW uint32_t KEYADDR; /* 0x10: Key Address */ + __RW uint32_t KEYDAT; /* 0x14: Key Data */ + __RW uint32_t CIPHIV[4]; /* 0x18 - 0x24: Cipher Initializtion Vector 0 */ + __RW uint32_t HASWRD[8]; /* 0x28 - 0x44: Hash Data Word 0 */ + __RW uint32_t CMDPTR; /* 0x48: Command Pointer */ + __RW uint32_t NPKTPTR; /* 0x4C: Next Packet Address Pointer */ + __RW uint32_t PKTCTL; /* 0x50: Packet Control Registers */ + __RW uint32_t PKTSRC; /* 0x54: Packet Memory Source Address */ + __RW uint32_t PKTDST; /* 0x58: Packet Memory Destination Address */ + __RW uint32_t PKTBUF; /* 0x5C: Packet buffer size. */ +} SDP_Type; + + +/* Bitfield definition for register: SDPCR */ +/* + * SFTRST (RW) + * + * soft reset. + * Write 1 then 0, to reset the SDP block. + */ +#define SDP_SDPCR_SFTRST_MASK (0x80000000UL) +#define SDP_SDPCR_SFTRST_SHIFT (31U) +#define SDP_SDPCR_SFTRST_SET(x) (((uint32_t)(x) << SDP_SDPCR_SFTRST_SHIFT) & SDP_SDPCR_SFTRST_MASK) +#define SDP_SDPCR_SFTRST_GET(x) (((uint32_t)(x) & SDP_SDPCR_SFTRST_MASK) >> SDP_SDPCR_SFTRST_SHIFT) + +/* + * CLKGAT (RW) + * + * Clock Gate for the SDP main logic. + * Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + */ +#define SDP_SDPCR_CLKGAT_MASK (0x40000000UL) +#define SDP_SDPCR_CLKGAT_SHIFT (30U) +#define SDP_SDPCR_CLKGAT_SET(x) (((uint32_t)(x) << SDP_SDPCR_CLKGAT_SHIFT) & SDP_SDPCR_CLKGAT_MASK) +#define SDP_SDPCR_CLKGAT_GET(x) (((uint32_t)(x) & SDP_SDPCR_CLKGAT_MASK) >> SDP_SDPCR_CLKGAT_SHIFT) + +/* + * CIPDIS (RO) + * + * Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. + * 1, Cipher is disabled in this chip. + * 0, Cipher is enabled in this chip. + */ +#define SDP_SDPCR_CIPDIS_MASK (0x20000000UL) +#define SDP_SDPCR_CIPDIS_SHIFT (29U) +#define SDP_SDPCR_CIPDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPDIS_MASK) >> SDP_SDPCR_CIPDIS_SHIFT) + +/* + * HASDIS (RO) + * + * HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. + * 1, HASH is disabled in this chip. + * 0, HASH is enabled in this chip. + */ +#define SDP_SDPCR_HASDIS_MASK (0x10000000UL) +#define SDP_SDPCR_HASDIS_SHIFT (28U) +#define SDP_SDPCR_HASDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASDIS_MASK) >> SDP_SDPCR_HASDIS_SHIFT) + +/* + * CIPHEN (RW) + * + * Cipher Enablement, controlled by SW. + * 1, Cipher is Enabled. + * 0, Cipher is Disabled. + */ +#define SDP_SDPCR_CIPHEN_MASK (0x800000UL) +#define SDP_SDPCR_CIPHEN_SHIFT (23U) +#define SDP_SDPCR_CIPHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CIPHEN_SHIFT) & SDP_SDPCR_CIPHEN_MASK) +#define SDP_SDPCR_CIPHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPHEN_MASK) >> SDP_SDPCR_CIPHEN_SHIFT) + +/* + * HASHEN (RW) + * + * HASH Enablement, controlled by SW. + * 1, HASH is Enabled. + * 0, HASH is Disabled. + */ +#define SDP_SDPCR_HASHEN_MASK (0x400000UL) +#define SDP_SDPCR_HASHEN_SHIFT (22U) +#define SDP_SDPCR_HASHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_HASHEN_SHIFT) & SDP_SDPCR_HASHEN_MASK) +#define SDP_SDPCR_HASHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASHEN_MASK) >> SDP_SDPCR_HASHEN_SHIFT) + +/* + * MCPEN (RW) + * + * Memory Copy Enablement, controlled by SW. + * 1, Memory copy is Enabled. + * 0, Memory copy is Disabled. + */ +#define SDP_SDPCR_MCPEN_MASK (0x200000UL) +#define SDP_SDPCR_MCPEN_SHIFT (21U) +#define SDP_SDPCR_MCPEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_MCPEN_SHIFT) & SDP_SDPCR_MCPEN_MASK) +#define SDP_SDPCR_MCPEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_MCPEN_MASK) >> SDP_SDPCR_MCPEN_SHIFT) + +/* + * CONFEN (RW) + * + * Constant Fill to memory, controlled by SW. + * 1, Constant fill is Enabled. + * 0, Constant fill is Disabled. + */ +#define SDP_SDPCR_CONFEN_MASK (0x100000UL) +#define SDP_SDPCR_CONFEN_SHIFT (20U) +#define SDP_SDPCR_CONFEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CONFEN_SHIFT) & SDP_SDPCR_CONFEN_MASK) +#define SDP_SDPCR_CONFEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CONFEN_MASK) >> SDP_SDPCR_CONFEN_SHIFT) + +/* + * DCRPDI (RW) + * + * Decryption Disable bit, Write to 1 to disable the decryption. + */ +#define SDP_SDPCR_DCRPDI_MASK (0x80000UL) +#define SDP_SDPCR_DCRPDI_SHIFT (19U) +#define SDP_SDPCR_DCRPDI_SET(x) (((uint32_t)(x) << SDP_SDPCR_DCRPDI_SHIFT) & SDP_SDPCR_DCRPDI_MASK) +#define SDP_SDPCR_DCRPDI_GET(x) (((uint32_t)(x) & SDP_SDPCR_DCRPDI_MASK) >> SDP_SDPCR_DCRPDI_SHIFT) + +/* + * TSTPKT0IRQ (RW) + * + * Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + */ +#define SDP_SDPCR_TSTPKT0IRQ_MASK (0x20000UL) +#define SDP_SDPCR_TSTPKT0IRQ_SHIFT (17U) +#define SDP_SDPCR_TSTPKT0IRQ_SET(x) (((uint32_t)(x) << SDP_SDPCR_TSTPKT0IRQ_SHIFT) & SDP_SDPCR_TSTPKT0IRQ_MASK) +#define SDP_SDPCR_TSTPKT0IRQ_GET(x) (((uint32_t)(x) & SDP_SDPCR_TSTPKT0IRQ_MASK) >> SDP_SDPCR_TSTPKT0IRQ_SHIFT) + +/* + * RDSCEN (RW) + * + * when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) + * when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + */ +#define SDP_SDPCR_RDSCEN_MASK (0x100U) +#define SDP_SDPCR_RDSCEN_SHIFT (8U) +#define SDP_SDPCR_RDSCEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_RDSCEN_SHIFT) & SDP_SDPCR_RDSCEN_MASK) +#define SDP_SDPCR_RDSCEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_RDSCEN_MASK) >> SDP_SDPCR_RDSCEN_SHIFT) + +/* + * INTEN (RW) + * + * Interrupt Enablement, controlled by SW. + * 1, SDP interrupt is enabled. + * 0, SDP interrupt is disabled. + */ +#define SDP_SDPCR_INTEN_MASK (0x1U) +#define SDP_SDPCR_INTEN_SHIFT (0U) +#define SDP_SDPCR_INTEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_INTEN_SHIFT) & SDP_SDPCR_INTEN_MASK) +#define SDP_SDPCR_INTEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_INTEN_MASK) >> SDP_SDPCR_INTEN_SHIFT) + +/* Bitfield definition for register: MODCTRL */ +/* + * AESALG (RW) + * + * AES algorithem selection. + * 0x0 = AES 128; + * 0x1 = AES 256; + * Others, reserved. + */ +#define SDP_MODCTRL_AESALG_MASK (0xF0000000UL) +#define SDP_MODCTRL_AESALG_SHIFT (28U) +#define SDP_MODCTRL_AESALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESALG_SHIFT) & SDP_MODCTRL_AESALG_MASK) +#define SDP_MODCTRL_AESALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESALG_MASK) >> SDP_MODCTRL_AESALG_SHIFT) + +/* + * AESMOD (RW) + * + * AES mode selection. + * 0x0 = ECB; + * 0x1 = CBC; + * Others, reserved. + */ +#define SDP_MODCTRL_AESMOD_MASK (0xF000000UL) +#define SDP_MODCTRL_AESMOD_SHIFT (24U) +#define SDP_MODCTRL_AESMOD_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESMOD_SHIFT) & SDP_MODCTRL_AESMOD_MASK) +#define SDP_MODCTRL_AESMOD_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESMOD_MASK) >> SDP_MODCTRL_AESMOD_SHIFT) + +/* + * AESKS (RW) + * + * AES Key Selection. + * These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: + * 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. + * 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. + * .... + * 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. + * 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. + * 0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. + * 0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. + * 0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. + * 0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. + * 0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. + * 0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. + * 0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. + * 0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. + * 0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. + * 0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. + * 0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. + * 0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. + * Other values, reserved. + */ +#define SDP_MODCTRL_AESKS_MASK (0xFC0000UL) +#define SDP_MODCTRL_AESKS_SHIFT (18U) +#define SDP_MODCTRL_AESKS_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESKS_SHIFT) & SDP_MODCTRL_AESKS_MASK) +#define SDP_MODCTRL_AESKS_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESKS_MASK) >> SDP_MODCTRL_AESKS_SHIFT) + +/* + * AESDIR (RW) + * + * AES direction + * 1x1, AES Decryption + * 1x0, AES Encryption. + */ +#define SDP_MODCTRL_AESDIR_MASK (0x10000UL) +#define SDP_MODCTRL_AESDIR_SHIFT (16U) +#define SDP_MODCTRL_AESDIR_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESDIR_SHIFT) & SDP_MODCTRL_AESDIR_MASK) +#define SDP_MODCTRL_AESDIR_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESDIR_MASK) >> SDP_MODCTRL_AESDIR_SHIFT) + +/* + * HASALG (RW) + * + * HASH Algorithem selection. + * 0x0 SHA1 — + * 0x1 CRC32 — + * 0x2 SHA256 — + */ +#define SDP_MODCTRL_HASALG_MASK (0xF000U) +#define SDP_MODCTRL_HASALG_SHIFT (12U) +#define SDP_MODCTRL_HASALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASALG_SHIFT) & SDP_MODCTRL_HASALG_MASK) +#define SDP_MODCTRL_HASALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASALG_MASK) >> SDP_MODCTRL_HASALG_SHIFT) + +/* + * CRCEN (RW) + * + * CRC enable. + * 1x1, CRC is enabled. + * 1x0, CRC is disabled. + */ +#define SDP_MODCTRL_CRCEN_MASK (0x800U) +#define SDP_MODCTRL_CRCEN_SHIFT (11U) +#define SDP_MODCTRL_CRCEN_SET(x) (((uint32_t)(x) << SDP_MODCTRL_CRCEN_SHIFT) & SDP_MODCTRL_CRCEN_MASK) +#define SDP_MODCTRL_CRCEN_GET(x) (((uint32_t)(x) & SDP_MODCTRL_CRCEN_MASK) >> SDP_MODCTRL_CRCEN_SHIFT) + +/* + * HASCHK (RW) + * + * HASH Check Enable Bit. + * 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; + * 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. + * For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + */ +#define SDP_MODCTRL_HASCHK_MASK (0x400U) +#define SDP_MODCTRL_HASCHK_SHIFT (10U) +#define SDP_MODCTRL_HASCHK_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASCHK_SHIFT) & SDP_MODCTRL_HASCHK_MASK) +#define SDP_MODCTRL_HASCHK_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASCHK_MASK) >> SDP_MODCTRL_HASCHK_SHIFT) + +/* + * HASOUT (RW) + * + * When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. + * 0 INPUT HASH + * 1 OUTPUT HASH + */ +#define SDP_MODCTRL_HASOUT_MASK (0x200U) +#define SDP_MODCTRL_HASOUT_SHIFT (9U) +#define SDP_MODCTRL_HASOUT_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASOUT_SHIFT) & SDP_MODCTRL_HASOUT_MASK) +#define SDP_MODCTRL_HASOUT_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASOUT_MASK) >> SDP_MODCTRL_HASOUT_SHIFT) + +/* + * DINSWP (RW) + * + * Decide whether the SDP byteswaps the input data (big-endian data); + * When all bits are set, the data is assumed to be in the big-endian format + */ +#define SDP_MODCTRL_DINSWP_MASK (0x30U) +#define SDP_MODCTRL_DINSWP_SHIFT (4U) +#define SDP_MODCTRL_DINSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DINSWP_SHIFT) & SDP_MODCTRL_DINSWP_MASK) +#define SDP_MODCTRL_DINSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DINSWP_MASK) >> SDP_MODCTRL_DINSWP_SHIFT) + +/* + * DOUTSWP (RW) + * + * Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + */ +#define SDP_MODCTRL_DOUTSWP_MASK (0xCU) +#define SDP_MODCTRL_DOUTSWP_SHIFT (2U) +#define SDP_MODCTRL_DOUTSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DOUTSWP_SHIFT) & SDP_MODCTRL_DOUTSWP_MASK) +#define SDP_MODCTRL_DOUTSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DOUTSWP_MASK) >> SDP_MODCTRL_DOUTSWP_SHIFT) + +/* + * KEYSWP (RW) + * + * Decide whether the SDP byteswaps the Key (big-endian data). + * When all bits are set, the data is assumed to be in the big-endian format + */ +#define SDP_MODCTRL_KEYSWP_MASK (0x3U) +#define SDP_MODCTRL_KEYSWP_SHIFT (0U) +#define SDP_MODCTRL_KEYSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_KEYSWP_SHIFT) & SDP_MODCTRL_KEYSWP_MASK) +#define SDP_MODCTRL_KEYSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_KEYSWP_MASK) >> SDP_MODCTRL_KEYSWP_SHIFT) + +/* Bitfield definition for register: PKTCNT */ +/* + * CNTVAL (RO) + * + * This read-only field shows the current (instantaneous) value of the packet counter + */ +#define SDP_PKTCNT_CNTVAL_MASK (0xFF0000UL) +#define SDP_PKTCNT_CNTVAL_SHIFT (16U) +#define SDP_PKTCNT_CNTVAL_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTVAL_MASK) >> SDP_PKTCNT_CNTVAL_SHIFT) + +/* + * CNTINCR (RW) + * + * The value written to this field is added to the spacket count. + */ +#define SDP_PKTCNT_CNTINCR_MASK (0xFFU) +#define SDP_PKTCNT_CNTINCR_SHIFT (0U) +#define SDP_PKTCNT_CNTINCR_SET(x) (((uint32_t)(x) << SDP_PKTCNT_CNTINCR_SHIFT) & SDP_PKTCNT_CNTINCR_MASK) +#define SDP_PKTCNT_CNTINCR_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTINCR_MASK) >> SDP_PKTCNT_CNTINCR_SHIFT) + +/* Bitfield definition for register: STA */ +/* + * TAG (RO) + * + * packet tag. + */ +#define SDP_STA_TAG_MASK (0xFF000000UL) +#define SDP_STA_TAG_SHIFT (24U) +#define SDP_STA_TAG_GET(x) (((uint32_t)(x) & SDP_STA_TAG_MASK) >> SDP_STA_TAG_SHIFT) + +/* + * IRQ (W1C) + * + * interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + */ +#define SDP_STA_IRQ_MASK (0x800000UL) +#define SDP_STA_IRQ_SHIFT (23U) +#define SDP_STA_IRQ_SET(x) (((uint32_t)(x) << SDP_STA_IRQ_SHIFT) & SDP_STA_IRQ_MASK) +#define SDP_STA_IRQ_GET(x) (((uint32_t)(x) & SDP_STA_IRQ_MASK) >> SDP_STA_IRQ_SHIFT) + +/* + * CHN1PKT0 (W1C) + * + * the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + */ +#define SDP_STA_CHN1PKT0_MASK (0x100000UL) +#define SDP_STA_CHN1PKT0_SHIFT (20U) +#define SDP_STA_CHN1PKT0_SET(x) (((uint32_t)(x) << SDP_STA_CHN1PKT0_SHIFT) & SDP_STA_CHN1PKT0_MASK) +#define SDP_STA_CHN1PKT0_GET(x) (((uint32_t)(x) & SDP_STA_CHN1PKT0_MASK) >> SDP_STA_CHN1PKT0_SHIFT) + +/* + * AESBSY (RO) + * + * AES Busy + */ +#define SDP_STA_AESBSY_MASK (0x80000UL) +#define SDP_STA_AESBSY_SHIFT (19U) +#define SDP_STA_AESBSY_GET(x) (((uint32_t)(x) & SDP_STA_AESBSY_MASK) >> SDP_STA_AESBSY_SHIFT) + +/* + * HASBSY (RO) + * + * Hashing Busy + */ +#define SDP_STA_HASBSY_MASK (0x40000UL) +#define SDP_STA_HASBSY_SHIFT (18U) +#define SDP_STA_HASBSY_GET(x) (((uint32_t)(x) & SDP_STA_HASBSY_MASK) >> SDP_STA_HASBSY_SHIFT) + +/* + * PKTCNT0 (W1C) + * + * Packet Counter registers reachs to ZERO now. + */ +#define SDP_STA_PKTCNT0_MASK (0x20000UL) +#define SDP_STA_PKTCNT0_SHIFT (17U) +#define SDP_STA_PKTCNT0_SET(x) (((uint32_t)(x) << SDP_STA_PKTCNT0_SHIFT) & SDP_STA_PKTCNT0_MASK) +#define SDP_STA_PKTCNT0_GET(x) (((uint32_t)(x) & SDP_STA_PKTCNT0_MASK) >> SDP_STA_PKTCNT0_SHIFT) + +/* + * PKTDON (W1C) + * + * Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + */ +#define SDP_STA_PKTDON_MASK (0x10000UL) +#define SDP_STA_PKTDON_SHIFT (16U) +#define SDP_STA_PKTDON_SET(x) (((uint32_t)(x) << SDP_STA_PKTDON_SHIFT) & SDP_STA_PKTDON_MASK) +#define SDP_STA_PKTDON_GET(x) (((uint32_t)(x) & SDP_STA_PKTDON_MASK) >> SDP_STA_PKTDON_SHIFT) + +/* + * ERRSET (W1C) + * + * Working mode setup error. + */ +#define SDP_STA_ERRSET_MASK (0x20U) +#define SDP_STA_ERRSET_SHIFT (5U) +#define SDP_STA_ERRSET_SET(x) (((uint32_t)(x) << SDP_STA_ERRSET_SHIFT) & SDP_STA_ERRSET_MASK) +#define SDP_STA_ERRSET_GET(x) (((uint32_t)(x) & SDP_STA_ERRSET_MASK) >> SDP_STA_ERRSET_SHIFT) + +/* + * ERRPKT (W1C) + * + * Packet head access error, or status update error. + */ +#define SDP_STA_ERRPKT_MASK (0x10U) +#define SDP_STA_ERRPKT_SHIFT (4U) +#define SDP_STA_ERRPKT_SET(x) (((uint32_t)(x) << SDP_STA_ERRPKT_SHIFT) & SDP_STA_ERRPKT_MASK) +#define SDP_STA_ERRPKT_GET(x) (((uint32_t)(x) & SDP_STA_ERRPKT_MASK) >> SDP_STA_ERRPKT_SHIFT) + +/* + * ERRSRC (W1C) + * + * Source Buffer Access Error + */ +#define SDP_STA_ERRSRC_MASK (0x8U) +#define SDP_STA_ERRSRC_SHIFT (3U) +#define SDP_STA_ERRSRC_SET(x) (((uint32_t)(x) << SDP_STA_ERRSRC_SHIFT) & SDP_STA_ERRSRC_MASK) +#define SDP_STA_ERRSRC_GET(x) (((uint32_t)(x) & SDP_STA_ERRSRC_MASK) >> SDP_STA_ERRSRC_SHIFT) + +/* + * ERRDST (W1C) + * + * Destination Buffer Error + */ +#define SDP_STA_ERRDST_MASK (0x4U) +#define SDP_STA_ERRDST_SHIFT (2U) +#define SDP_STA_ERRDST_SET(x) (((uint32_t)(x) << SDP_STA_ERRDST_SHIFT) & SDP_STA_ERRDST_MASK) +#define SDP_STA_ERRDST_GET(x) (((uint32_t)(x) & SDP_STA_ERRDST_MASK) >> SDP_STA_ERRDST_SHIFT) + +/* + * ERRHAS (W1C) + * + * Hashing Check Error + */ +#define SDP_STA_ERRHAS_MASK (0x2U) +#define SDP_STA_ERRHAS_SHIFT (1U) +#define SDP_STA_ERRHAS_SET(x) (((uint32_t)(x) << SDP_STA_ERRHAS_SHIFT) & SDP_STA_ERRHAS_MASK) +#define SDP_STA_ERRHAS_GET(x) (((uint32_t)(x) & SDP_STA_ERRHAS_MASK) >> SDP_STA_ERRHAS_SHIFT) + +/* + * ERRCHAIN (W1C) + * + * buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + */ +#define SDP_STA_ERRCHAIN_MASK (0x1U) +#define SDP_STA_ERRCHAIN_SHIFT (0U) +#define SDP_STA_ERRCHAIN_SET(x) (((uint32_t)(x) << SDP_STA_ERRCHAIN_SHIFT) & SDP_STA_ERRCHAIN_MASK) +#define SDP_STA_ERRCHAIN_GET(x) (((uint32_t)(x) & SDP_STA_ERRCHAIN_MASK) >> SDP_STA_ERRCHAIN_SHIFT) + +/* Bitfield definition for register: KEYADDR */ +/* + * INDEX (RW) + * + * To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. + * Key index pointer. The valid indices are 0-[number_keys]. + * In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + */ +#define SDP_KEYADDR_INDEX_MASK (0xFF0000UL) +#define SDP_KEYADDR_INDEX_SHIFT (16U) +#define SDP_KEYADDR_INDEX_SET(x) (((uint32_t)(x) << SDP_KEYADDR_INDEX_SHIFT) & SDP_KEYADDR_INDEX_MASK) +#define SDP_KEYADDR_INDEX_GET(x) (((uint32_t)(x) & SDP_KEYADDR_INDEX_MASK) >> SDP_KEYADDR_INDEX_SHIFT) + +/* + * SUBWRD (RW) + * + * Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field + * increments; To write a key, the software must first write the desired key index/subword to this register. + */ +#define SDP_KEYADDR_SUBWRD_MASK (0x3U) +#define SDP_KEYADDR_SUBWRD_SHIFT (0U) +#define SDP_KEYADDR_SUBWRD_SET(x) (((uint32_t)(x) << SDP_KEYADDR_SUBWRD_SHIFT) & SDP_KEYADDR_SUBWRD_MASK) +#define SDP_KEYADDR_SUBWRD_GET(x) (((uint32_t)(x) & SDP_KEYADDR_SUBWRD_MASK) >> SDP_KEYADDR_SUBWRD_SHIFT) + +/* Bitfield definition for register: KEYDAT */ +/* + * KEYDAT (RW) + * + * This register provides the write access to the key/key subword specified by the key index register. + * Writing this location updates the selected subword for the key located at the index + * specified by the key index register. The write also triggers the SUBWORD field of the + * KEY register to increment to the next higher word in the key + */ +#define SDP_KEYDAT_KEYDAT_MASK (0xFFFFFFFFUL) +#define SDP_KEYDAT_KEYDAT_SHIFT (0U) +#define SDP_KEYDAT_KEYDAT_SET(x) (((uint32_t)(x) << SDP_KEYDAT_KEYDAT_SHIFT) & SDP_KEYDAT_KEYDAT_MASK) +#define SDP_KEYDAT_KEYDAT_GET(x) (((uint32_t)(x) & SDP_KEYDAT_KEYDAT_MASK) >> SDP_KEYDAT_KEYDAT_SHIFT) + +/* Bitfield definition for register array: CIPHIV */ +/* + * CIPHIV (RW) + * + * cipher initialization vector. + */ +#define SDP_CIPHIV_CIPHIV_MASK (0xFFFFFFFFUL) +#define SDP_CIPHIV_CIPHIV_SHIFT (0U) +#define SDP_CIPHIV_CIPHIV_SET(x) (((uint32_t)(x) << SDP_CIPHIV_CIPHIV_SHIFT) & SDP_CIPHIV_CIPHIV_MASK) +#define SDP_CIPHIV_CIPHIV_GET(x) (((uint32_t)(x) & SDP_CIPHIV_CIPHIV_MASK) >> SDP_CIPHIV_CIPHIV_SHIFT) + +/* Bitfield definition for register array: HASWRD */ +/* + * HASWRD (RW) + * + * Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. + * If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + */ +#define SDP_HASWRD_HASWRD_MASK (0xFFFFFFFFUL) +#define SDP_HASWRD_HASWRD_SHIFT (0U) +#define SDP_HASWRD_HASWRD_SET(x) (((uint32_t)(x) << SDP_HASWRD_HASWRD_SHIFT) & SDP_HASWRD_HASWRD_MASK) +#define SDP_HASWRD_HASWRD_GET(x) (((uint32_t)(x) & SDP_HASWRD_HASWRD_MASK) >> SDP_HASWRD_HASWRD_SHIFT) + +/* Bitfield definition for register: CMDPTR */ +/* + * CMDPTR (RW) + * + * current command addresses the register points to the multiword + * descriptor that is to be executed (or is currently being executed) + */ +#define SDP_CMDPTR_CMDPTR_MASK (0xFFFFFFFFUL) +#define SDP_CMDPTR_CMDPTR_SHIFT (0U) +#define SDP_CMDPTR_CMDPTR_SET(x) (((uint32_t)(x) << SDP_CMDPTR_CMDPTR_SHIFT) & SDP_CMDPTR_CMDPTR_MASK) +#define SDP_CMDPTR_CMDPTR_GET(x) (((uint32_t)(x) & SDP_CMDPTR_CMDPTR_MASK) >> SDP_CMDPTR_CMDPTR_SHIFT) + +/* Bitfield definition for register: NPKTPTR */ +/* + * NPKTPTR (RW) + * + * Next Packet Address Pointer + */ +#define SDP_NPKTPTR_NPKTPTR_MASK (0xFFFFFFFFUL) +#define SDP_NPKTPTR_NPKTPTR_SHIFT (0U) +#define SDP_NPKTPTR_NPKTPTR_SET(x) (((uint32_t)(x) << SDP_NPKTPTR_NPKTPTR_SHIFT) & SDP_NPKTPTR_NPKTPTR_MASK) +#define SDP_NPKTPTR_NPKTPTR_GET(x) (((uint32_t)(x) & SDP_NPKTPTR_NPKTPTR_MASK) >> SDP_NPKTPTR_NPKTPTR_SHIFT) + +/* Bitfield definition for register: PKTCTL */ +/* + * PKTTAG (RW) + * + * packet tag + */ +#define SDP_PKTCTL_PKTTAG_MASK (0xFF000000UL) +#define SDP_PKTCTL_PKTTAG_SHIFT (24U) +#define SDP_PKTCTL_PKTTAG_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTTAG_SHIFT) & SDP_PKTCTL_PKTTAG_MASK) +#define SDP_PKTCTL_PKTTAG_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTTAG_MASK) >> SDP_PKTCTL_PKTTAG_SHIFT) + +/* + * CIPHIV (RW) + * + * Load Initial Vector for the AES in this packet. + */ +#define SDP_PKTCTL_CIPHIV_MASK (0x40U) +#define SDP_PKTCTL_CIPHIV_SHIFT (6U) +#define SDP_PKTCTL_CIPHIV_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CIPHIV_SHIFT) & SDP_PKTCTL_CIPHIV_MASK) +#define SDP_PKTCTL_CIPHIV_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CIPHIV_MASK) >> SDP_PKTCTL_CIPHIV_SHIFT) + +/* + * HASFNL (RW) + * + * Hash Termination packet + */ +#define SDP_PKTCTL_HASFNL_MASK (0x20U) +#define SDP_PKTCTL_HASFNL_SHIFT (5U) +#define SDP_PKTCTL_HASFNL_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASFNL_SHIFT) & SDP_PKTCTL_HASFNL_MASK) +#define SDP_PKTCTL_HASFNL_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASFNL_MASK) >> SDP_PKTCTL_HASFNL_SHIFT) + +/* + * HASINI (RW) + * + * Hash Initialization packat + */ +#define SDP_PKTCTL_HASINI_MASK (0x10U) +#define SDP_PKTCTL_HASINI_SHIFT (4U) +#define SDP_PKTCTL_HASINI_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASINI_SHIFT) & SDP_PKTCTL_HASINI_MASK) +#define SDP_PKTCTL_HASINI_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASINI_MASK) >> SDP_PKTCTL_HASINI_SHIFT) + +/* + * CHAIN (RW) + * + * whether the next command pointer register must be loaded into the channel's current descriptor + * pointer. + */ +#define SDP_PKTCTL_CHAIN_MASK (0x8U) +#define SDP_PKTCTL_CHAIN_SHIFT (3U) +#define SDP_PKTCTL_CHAIN_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CHAIN_SHIFT) & SDP_PKTCTL_CHAIN_MASK) +#define SDP_PKTCTL_CHAIN_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CHAIN_MASK) >> SDP_PKTCTL_CHAIN_SHIFT) + +/* + * DCRSEMA (RW) + * + * whether the channel's semaphore must be decremented at the end of the current operation. + * When the semaphore reaches a value of zero, no more operations are issued from the channel. + */ +#define SDP_PKTCTL_DCRSEMA_MASK (0x4U) +#define SDP_PKTCTL_DCRSEMA_SHIFT (2U) +#define SDP_PKTCTL_DCRSEMA_SET(x) (((uint32_t)(x) << SDP_PKTCTL_DCRSEMA_SHIFT) & SDP_PKTCTL_DCRSEMA_MASK) +#define SDP_PKTCTL_DCRSEMA_GET(x) (((uint32_t)(x) & SDP_PKTCTL_DCRSEMA_MASK) >> SDP_PKTCTL_DCRSEMA_SHIFT) + +/* + * PKTINT (RW) + * + * Reflects whether the channel must issue an interrupt upon the completion of the packet + */ +#define SDP_PKTCTL_PKTINT_MASK (0x2U) +#define SDP_PKTCTL_PKTINT_SHIFT (1U) +#define SDP_PKTCTL_PKTINT_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTINT_SHIFT) & SDP_PKTCTL_PKTINT_MASK) +#define SDP_PKTCTL_PKTINT_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTINT_MASK) >> SDP_PKTCTL_PKTINT_SHIFT) + +/* Bitfield definition for register: PKTSRC */ +/* + * PKTSRC (RW) + * + * Packet Memory Source Address + */ +#define SDP_PKTSRC_PKTSRC_MASK (0xFFFFFFFFUL) +#define SDP_PKTSRC_PKTSRC_SHIFT (0U) +#define SDP_PKTSRC_PKTSRC_SET(x) (((uint32_t)(x) << SDP_PKTSRC_PKTSRC_SHIFT) & SDP_PKTSRC_PKTSRC_MASK) +#define SDP_PKTSRC_PKTSRC_GET(x) (((uint32_t)(x) & SDP_PKTSRC_PKTSRC_MASK) >> SDP_PKTSRC_PKTSRC_SHIFT) + +/* Bitfield definition for register: PKTDST */ +/* + * PKTDST (RW) + * + * Packet Memory Destination Address + */ +#define SDP_PKTDST_PKTDST_MASK (0xFFFFFFFFUL) +#define SDP_PKTDST_PKTDST_SHIFT (0U) +#define SDP_PKTDST_PKTDST_SET(x) (((uint32_t)(x) << SDP_PKTDST_PKTDST_SHIFT) & SDP_PKTDST_PKTDST_MASK) +#define SDP_PKTDST_PKTDST_GET(x) (((uint32_t)(x) & SDP_PKTDST_PKTDST_MASK) >> SDP_PKTDST_PKTDST_SHIFT) + +/* Bitfield definition for register: PKTBUF */ +/* + * PKTBUF (RW) + * + */ +#define SDP_PKTBUF_PKTBUF_MASK (0xFFFFFFFFUL) +#define SDP_PKTBUF_PKTBUF_SHIFT (0U) +#define SDP_PKTBUF_PKTBUF_SET(x) (((uint32_t)(x) << SDP_PKTBUF_PKTBUF_SHIFT) & SDP_PKTBUF_PKTBUF_MASK) +#define SDP_PKTBUF_PKTBUF_GET(x) (((uint32_t)(x) & SDP_PKTBUF_PKTBUF_MASK) >> SDP_PKTBUF_PKTBUF_SHIFT) + + + +/* CIPHIV register group index macro definition */ +#define SDP_CIPHIV_CIPHIV0 (0UL) +#define SDP_CIPHIV_CIPHIV1 (1UL) +#define SDP_CIPHIV_CIPHIV2 (2UL) +#define SDP_CIPHIV_CIPHIV3 (3UL) + +/* HASWRD register group index macro definition */ +#define SDP_HASWRD_HASWRD0 (0UL) +#define SDP_HASWRD_HASWRD1 (1UL) +#define SDP_HASWRD_HASWRD2 (2UL) +#define SDP_HASWRD_HASWRD3 (3UL) +#define SDP_HASWRD_HASWRD4 (4UL) +#define SDP_HASWRD_HASWRD5 (5UL) +#define SDP_HASWRD_HASWRD6 (6UL) +#define SDP_HASWRD_HASWRD7 (7UL) + + +#endif /* HPM_SDP_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h new file mode 100644 index 0000000000..2404466293 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdxc_regs.h @@ -0,0 +1,4421 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SDXC_H +#define HPM_SDXC_H + +typedef struct { + __RW uint32_t SDMASA; /* 0x0: */ + __RW uint32_t BLK_ATTR; /* 0x4: */ + __RW uint32_t CMD_ARG; /* 0x8: */ + __RW uint32_t CMD_XFER; /* 0xC: */ + __R uint32_t RESP[4]; /* 0x10 - 0x1C: */ + __RW uint32_t BUF_DATA; /* 0x20: */ + __R uint32_t PSTATE; /* 0x24: */ + __RW uint32_t PROT_CTRL; /* 0x28: */ + __RW uint32_t SYS_CTRL; /* 0x2C: */ + __RW uint32_t INT_STAT; /* 0x30: */ + __RW uint32_t INT_STAT_EN; /* 0x34: */ + __RW uint32_t INT_SIGNAL_EN; /* 0x38: */ + __RW uint32_t AC_HOST_CTRL; /* 0x3C: */ + __R uint32_t CAPABILITIES1; /* 0x40: */ + __R uint32_t CAPABILITIES2; /* 0x44: */ + __R uint32_t CURR_CAPABILITIES1; /* 0x48: */ + __R uint32_t CURR_CAPABILITIES2; /* 0x4C: */ + __RW uint32_t FORCE_EVENT; /* 0x50: */ + __R uint32_t ADMA_ERR_STAT; /* 0x54: */ + __RW uint32_t ADMA_SYS_ADDR; /* 0x58: */ + __R uint8_t RESERVED0[4]; /* 0x5C - 0x5F: Reserved */ + __R uint16_t PRESET[11]; /* 0x60 - 0x74: */ + __R uint8_t RESERVED1[2]; /* 0x76 - 0x77: Reserved */ + __RW uint32_t ADMA_ID_ADDR; /* 0x78: */ + __R uint8_t RESERVED2[106]; /* 0x7C - 0xE5: Reserved */ + __R uint16_t P_EMBEDDED_CNTRL; /* 0xE6: */ + __R uint16_t P_VENDOR_SPECIFIC_AREA; /* 0xE8: */ + __R uint16_t P_VENDOR2_SPECIFIC_AREA; /* 0xEA: */ + __R uint8_t RESERVED3[16]; /* 0xEC - 0xFB: Reserved */ + __R uint16_t SLOT_INTR_STATUS; /* 0xFC: */ + __R uint8_t RESERVED4[130]; /* 0xFE - 0x17F: Reserved */ + __R uint32_t CQVER; /* 0x180: */ + __R uint32_t CQCAP; /* 0x184: */ + __RW uint32_t CQCFG; /* 0x188: */ + __RW uint32_t CQCTL; /* 0x18C: */ + __RW uint32_t CQIS; /* 0x190: */ + __RW uint32_t CQISE; /* 0x194: */ + __RW uint32_t CQISGE; /* 0x198: */ + __RW uint32_t CQIC; /* 0x19C: */ + __RW uint32_t CQTDLBA; /* 0x1A0: */ + __R uint8_t RESERVED5[4]; /* 0x1A4 - 0x1A7: Reserved */ + __RW uint32_t CQTDBR; /* 0x1A8: */ + __RW uint32_t CQTCN; /* 0x1AC: */ + __RW uint32_t CQDQS; /* 0x1B0: */ + __RW uint32_t CQDPT; /* 0x1B4: */ + __RW uint32_t CQTCLR; /* 0x1B8: */ + __R uint8_t RESERVED6[4]; /* 0x1BC - 0x1BF: Reserved */ + __RW uint32_t CQSSC1; /* 0x1C0: */ + __RW uint32_t CQSSC2; /* 0x1C4: */ + __R uint32_t CQCRDCT; /* 0x1C8: */ + __R uint8_t RESERVED7[4]; /* 0x1CC - 0x1CF: Reserved */ + __RW uint32_t CQRMEM; /* 0x1D0: */ + __R uint32_t CQTERRI; /* 0x1D4: */ + __R uint32_t CQCRI; /* 0x1D8: */ + __R uint32_t CQCRA; /* 0x1DC: */ + __R uint8_t RESERVED8[800]; /* 0x1E0 - 0x4FF: Reserved */ + __R uint32_t MSHC_VER_ID; /* 0x500: */ + __R uint32_t MSHC_VER_TYPE; /* 0x504: */ + __R uint8_t RESERVED9[8]; /* 0x508 - 0x50F: Reserved */ + __RW uint32_t MBIU_CTRL; /* 0x510: Y */ + __R uint8_t RESERVED10[24]; /* 0x514 - 0x52B: Reserved */ + __RW uint32_t EMMC_BOOT_CTRL; /* 0x52C: */ + __R uint8_t RESERVED11[16]; /* 0x530 - 0x53F: Reserved */ + __RW uint32_t AUTO_TUNING_CTRL; /* 0x540: */ + __RW uint32_t AUTO_TUNING_STAT; /* 0x544: */ + __R uint8_t RESERVED12[10936]; /* 0x548 - 0x2FFF: Reserved */ + __RW uint32_t MISC_CTRL0; /* 0x3000: */ + __RW uint32_t MISC_CTRL1; /* 0x3004: */ +} SDXC_Type; + + +/* Bitfield definition for register: SDMASA */ +/* + * BLOCKCNT_SDMASA (RW) + * + * 32-bit Block Count (SDMA System Address) + * - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. + * When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. + * It can be accessed only if no transaction is executing. Reading this register during data transfers may + * return an invalid value. + * - 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. + * The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. + * This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. + * Following are the values for BLOCKCNT_SDMASA: + * - 0xFFFF_FFFF: 4G - 1 Block + * - + * - 0x0000_0002: 2 Blocks + * - 0x0000_0001: 1 Block + * - 0x0000_0000: Stop Count + * Note: + * - For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. + * The system address must be programmed in the ADMA System Address register. + * - For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. + * Auto CMD23 cannot be used with SDMA. + * - This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. + */ +#define SDXC_SDMASA_BLOCKCNT_SDMASA_MASK (0xFFFFFFFFUL) +#define SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT (0U) +#define SDXC_SDMASA_BLOCKCNT_SDMASA_SET(x) (((uint32_t)(x) << SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) +#define SDXC_SDMASA_BLOCKCNT_SDMASA_GET(x) (((uint32_t)(x) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) >> SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) + +/* Bitfield definition for register: BLK_ATTR */ +/* + * BLOCK_CNT (RW) + * + * 16-bit Block Count + * - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. + * - If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. + * Following are the values for BLOCK_CNT: + * - 0x0: Stop Count + * - 0x1: 1 Block + * - 0x2: 2 Blocks + * - . + * - 0xFFFF: 65535 Blocks + * Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. + */ +#define SDXC_BLK_ATTR_BLOCK_CNT_MASK (0xFFFF0000UL) +#define SDXC_BLK_ATTR_BLOCK_CNT_SHIFT (16U) +#define SDXC_BLK_ATTR_BLOCK_CNT_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) +#define SDXC_BLK_ATTR_BLOCK_CNT_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) >> SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) + +/* + * SDMA_BUF_BDARY (RW) + * + * SDMA Buffer Boundary + * These bits specify the size of contiguous buffer in system memory. + * The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. + * Values: + * - 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary + * - 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary + * - 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary + * - 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary + * - 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary + * - 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary + * - 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary + * - 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + */ +#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK (0x7000U) +#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT (12U) +#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) +#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) >> SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) + +/* + * XFER_BLOCK_SIZE (RW) + * + * Transfer Block Size + * These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. + * Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: + * - 0x1: 1 byte + * - 0x2: 2 bytes + * - 0x3: 3 bytes + * - . + * - 0x1FF: 511 byte + * - 0x200: 512 byt es + * - . + * - 0x800: 2048 bytes + * Note: This register must be programmed with a non-zero value for data transfer. + */ +#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK (0xFFFU) +#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT (0U) +#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) +#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) >> SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) + +/* Bitfield definition for register: CMD_ARG */ +/* + * ARGUMNET (RW) + * + * Command Argument + * These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. + */ +#define SDXC_CMD_ARG_ARGUMNET_MASK (0xFFFFFFFFUL) +#define SDXC_CMD_ARG_ARGUMNET_SHIFT (0U) +#define SDXC_CMD_ARG_ARGUMNET_SET(x) (((uint32_t)(x) << SDXC_CMD_ARG_ARGUMNET_SHIFT) & SDXC_CMD_ARG_ARGUMNET_MASK) +#define SDXC_CMD_ARG_ARGUMNET_GET(x) (((uint32_t)(x) & SDXC_CMD_ARG_ARGUMNET_MASK) >> SDXC_CMD_ARG_ARGUMNET_SHIFT) + +/* Bitfield definition for register: CMD_XFER */ +/* + * CMD_INDEX (RW) + * + * Command Index + * These bits are set to the command number that is specified in bits 45-40 of the Command Format. + */ +#define SDXC_CMD_XFER_CMD_INDEX_MASK (0x3F000000UL) +#define SDXC_CMD_XFER_CMD_INDEX_SHIFT (24U) +#define SDXC_CMD_XFER_CMD_INDEX_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_INDEX_SHIFT) & SDXC_CMD_XFER_CMD_INDEX_MASK) +#define SDXC_CMD_XFER_CMD_INDEX_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_INDEX_MASK) >> SDXC_CMD_XFER_CMD_INDEX_SHIFT) + +/* + * CMD_TYPE (RW) + * + * Command Type + * These bits indicate the command type. + * Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. + * Values: + * 0x3 (ABORT_CMD): Abort + * 0x2 (RESUME_CMD): Resume + * 0x1 (SUSPEND_CMD): Suspend + * 0x0 (NORMAL_CMD): Normal + */ +#define SDXC_CMD_XFER_CMD_TYPE_MASK (0xC00000UL) +#define SDXC_CMD_XFER_CMD_TYPE_SHIFT (22U) +#define SDXC_CMD_XFER_CMD_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_TYPE_SHIFT) & SDXC_CMD_XFER_CMD_TYPE_MASK) +#define SDXC_CMD_XFER_CMD_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_TYPE_MASK) >> SDXC_CMD_XFER_CMD_TYPE_SHIFT) + +/* + * DATA_PRESENT_SEL (RW) + * + * Data Present Select + * This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: + * Command using the CMD line + * Command with no data transfer but using busy signal on the DAT[0] line + * Resume Command + * Values: + * 0x0 (NO_DATA): No Data Present + * 0x1 (DATA): Data Present + */ +#define SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK (0x200000UL) +#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT (21U) +#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) +#define SDXC_CMD_XFER_DATA_PRESENT_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) >> SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) + +/* + * CMD_IDX_CHK_ENABLE (RW) + * + * Command Index Check Enable + * This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. + * If the value is not the same, it is reported as a Command Index error. + * Note: + * Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. + * For the tuning command, this bit must always be set to enable the index check. + * Values: + * 0x0 (DISABLED): Disable + * 0x1 (ENABLED): Enable + */ +#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK (0x100000UL) +#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT (20U) +#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) +#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) + +/* + * CMD_CRC_CHK_ENABLE (RW) + * + * Command CRC Check Enable + * This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. + * Note: + * CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. + * For the tuning command, this bit must always be set to 1 to enable the CRC check. + * Values: + * 0x0 (DISABLED): Disable + * 0x1 (ENABLED): Enable + */ +#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK (0x80000UL) +#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT (19U) +#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) +#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) + +/* + * SUB_CMD_FLAG (RW) + * + * Sub Command Flag + * This bit distinguishes between a main command and a sub command. + * Values: + * 0x0 (MAIN): Main Command + * 0x1 (SUB): Sub Command + */ +#define SDXC_CMD_XFER_SUB_CMD_FLAG_MASK (0x40000UL) +#define SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT (18U) +#define SDXC_CMD_XFER_SUB_CMD_FLAG_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) +#define SDXC_CMD_XFER_SUB_CMD_FLAG_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) >> SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) + +/* + * RESP_TYPE_SELECT (RW) + * + * Response Type Select + * This bit indicates the type of response expected from the card. + * Values: + * 0x0 (NO_RESP): No Response + * 0x1 (RESP_LEN_136): Response Length 136 + * 0x2 (RESP_LEN_48): Response Length 48 + * 0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response + */ +#define SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK (0x30000UL) +#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT (16U) +#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) +#define SDXC_CMD_XFER_RESP_TYPE_SELECT_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) + +/* + * RESP_INT_DISABLE (RW) + * + * Response Interrupt Disable + * The Host Controller supports response check function to avoid overhead of response error check by the Host driver. + * Response types of only R1 and R5 can be checked by the Controller. + * If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. + * If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. + * The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. + * Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. + * Values: + * - 0x0 (ENABLED): Response Interrupt is enabled + * - 0x1 (DISABLED): Response Interrupt is disabled + */ +#define SDXC_CMD_XFER_RESP_INT_DISABLE_MASK (0x100U) +#define SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT (8U) +#define SDXC_CMD_XFER_RESP_INT_DISABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) +#define SDXC_CMD_XFER_RESP_INT_DISABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) >> SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) + +/* + * RESP_ERR_CHK_ENABLE (RW) + * + * Response Error Check Enable + * The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. + * Note: + * - Response error check must not be enabled for any response type other than R1 and R5. + * - Response check must not be enabled for the tuning command. + * Values: + * - 0x0 (DISABLED): Response Error Check is disabled + * - 0x1 (ENABLED): Response Error Check is enabled + */ +#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK (0x80U) +#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT (7U) +#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) +#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) + +/* + * RESP_TYPE (RW) + * + * Response Type R1/R5 + * This bit selects either R1 or R5 as a response type when the Response Error Check is selected. + * Error statuses checked in R1: + * OUT_OF_RANGE + * ADDRESS_ERROR + * BLOCK_LEN_ERROR + * WP_VIOLATION + * CARD_IS_LOCKED + * COM_CRC_ERROR + * CARD_ECC_FAILED + * CC_ERROR + * ERROR + * Response Flags checked in R5: + * COM_CRC_ERROR + * ERROR + * FUNCTION_NUMBER + * OUT_OF_RANGE + * Values: + * 0x0 (RESP_R1): R1 (Memory) + * 0x1 (RESP_R5): R5 (SDIO) + */ +#define SDXC_CMD_XFER_RESP_TYPE_MASK (0x40U) +#define SDXC_CMD_XFER_RESP_TYPE_SHIFT (6U) +#define SDXC_CMD_XFER_RESP_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_MASK) +#define SDXC_CMD_XFER_RESP_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SHIFT) + +/* + * MULTI_BLK_SEL (RW) + * + * Multi/Single Block Select + * This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. + * Values: + * 0x0 (SINGLE): Single Block + * 0x1 (MULTI): Multiple Block + */ +#define SDXC_CMD_XFER_MULTI_BLK_SEL_MASK (0x20U) +#define SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT (5U) +#define SDXC_CMD_XFER_MULTI_BLK_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) +#define SDXC_CMD_XFER_MULTI_BLK_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) >> SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) + +/* + * DATA_XFER_DIR (RW) + * + * Data Transfer Direction Select + * This bit defines the direction of DAT line data transfers. + * This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. + * Values: + * 0x1 (READ): Read (Card to Host) + * 0x0 (WRITE): Write (Host to Card) + */ +#define SDXC_CMD_XFER_DATA_XFER_DIR_MASK (0x10U) +#define SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT (4U) +#define SDXC_CMD_XFER_DATA_XFER_DIR_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) +#define SDXC_CMD_XFER_DATA_XFER_DIR_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) >> SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) + +/* + * AUTO_CMD_ENABLE (RW) + * + * Auto Command Enable + * This field determines use of Auto Command functions. + * Note: In SDIO, this field must be set as 00b (Auto Command Disabled). + * Values: + * 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled + * 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable + * 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable + * 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel + */ +#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK (0xCU) +#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT (2U) +#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) +#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) >> SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) + +/* + * BLOCK_COUNT_ENABLE (RW) + * + * Block Count Enable + * This bit is used to enable the Block Count register, which is relevant for multiple block transfers. + * If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. + * The Host Driver must set this bit to 0 when ADMA is used. + * Values: + * 0x1 (ENABLED): Enable + * 0x0 (DISABLED): Disable + */ +#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK (0x2U) +#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT (1U) +#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) +#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) >> SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) + +/* + * DMA_ENABLE (RW) + * + * DMA Enable + * This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. + * You can select one of the DMA modes by using DMA Select in the Host Control 1 register. + * Values: + * 0x1 (ENABLED): DMA Data transfer + * 0x0 (DISABLED): No data transfer or Non-DMA data transfer + */ +#define SDXC_CMD_XFER_DMA_ENABLE_MASK (0x1U) +#define SDXC_CMD_XFER_DMA_ENABLE_SHIFT (0U) +#define SDXC_CMD_XFER_DMA_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DMA_ENABLE_SHIFT) & SDXC_CMD_XFER_DMA_ENABLE_MASK) +#define SDXC_CMD_XFER_DMA_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DMA_ENABLE_MASK) >> SDXC_CMD_XFER_DMA_ENABLE_SHIFT) + +/* Bitfield definition for register array: RESP */ +/* + * RESP01 (R) + * + * Command Response + * These bits reflect 39-8 bits of SD/eMMC Response Field. + * Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + */ +#define SDXC_RESP_RESP01_MASK (0xFFFFFFFFUL) +#define SDXC_RESP_RESP01_SHIFT (0U) +#define SDXC_RESP_RESP01_GET(x) (((uint32_t)(x) & SDXC_RESP_RESP01_MASK) >> SDXC_RESP_RESP01_SHIFT) + +/* Bitfield definition for register: BUF_DATA */ +/* + * BUF_DATA (RW) + * + * Buffer Data + * These bits enable access to the Host Controller packet buffer. + */ +#define SDXC_BUF_DATA_BUF_DATA_MASK (0xFFFFFFFFUL) +#define SDXC_BUF_DATA_BUF_DATA_SHIFT (0U) +#define SDXC_BUF_DATA_BUF_DATA_SET(x) (((uint32_t)(x) << SDXC_BUF_DATA_BUF_DATA_SHIFT) & SDXC_BUF_DATA_BUF_DATA_MASK) +#define SDXC_BUF_DATA_BUF_DATA_GET(x) (((uint32_t)(x) & SDXC_BUF_DATA_BUF_DATA_MASK) >> SDXC_BUF_DATA_BUF_DATA_SHIFT) + +/* Bitfield definition for register: PSTATE */ +/* + * SUB_CMD_STAT (R) + * + * Sub Command Status + * This bit is used to distinguish between a main command and a sub command status. + * Values: + * 0x0 (FALSE): Main Command Status + * 0x1 (TRUE): Sub Command Status + */ +#define SDXC_PSTATE_SUB_CMD_STAT_MASK (0x10000000UL) +#define SDXC_PSTATE_SUB_CMD_STAT_SHIFT (28U) +#define SDXC_PSTATE_SUB_CMD_STAT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_SUB_CMD_STAT_MASK) >> SDXC_PSTATE_SUB_CMD_STAT_SHIFT) + +/* + * CMD_ISSUE_ERR (R) + * + * Command Not Issued by Error + * This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. + * Values: + * 0x0 (FALSE): No error for issuing a command + * 0x1 (TRUE): Command cannot be issued + */ +#define SDXC_PSTATE_CMD_ISSUE_ERR_MASK (0x8000000UL) +#define SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT (27U) +#define SDXC_PSTATE_CMD_ISSUE_ERR_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_ISSUE_ERR_MASK) >> SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT) + +/* + * CMD_LINE_LVL (R) + * + * Command-Line Signal Level + * This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. + */ +#define SDXC_PSTATE_CMD_LINE_LVL_MASK (0x1000000UL) +#define SDXC_PSTATE_CMD_LINE_LVL_SHIFT (24U) +#define SDXC_PSTATE_CMD_LINE_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_LINE_LVL_MASK) >> SDXC_PSTATE_CMD_LINE_LVL_SHIFT) + +/* + * DAT_3_0 (R) + * + * DAT[3:0] Line Signal Level + * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. + */ +#define SDXC_PSTATE_DAT_3_0_MASK (0xF00000UL) +#define SDXC_PSTATE_DAT_3_0_SHIFT (20U) +#define SDXC_PSTATE_DAT_3_0_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_3_0_MASK) >> SDXC_PSTATE_DAT_3_0_SHIFT) + +/* + * WR_PROTECT_SW_LVL (R) + * + * Write Protect Switch Pin Level + * This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. + * Values: + * 0x0 (FALSE): Write protected + * 0x1 (TRUE): Write enabled + */ +#define SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK (0x80000UL) +#define SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT (19U) +#define SDXC_PSTATE_WR_PROTECT_SW_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK) >> SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT) + +/* + * CARD_DETECT_PIN_LEVEL (R) + * + * Card Detect Pin Level + * This bit reflects the inverse synchronized value of the card_detect_n signal. + * Values: + * 0x0 (FALSE): No card present + * 0x1 (TRUE): Card Present + */ +#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK (0x40000UL) +#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT (18U) +#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK) >> SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT) + +/* + * CARD_STABLE (R) + * + * Card Stable + * This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. + * Values: + * 0x0 (FALSE): Reset or Debouncing + * 0x1 (TRUE): No Card or Inserted + */ +#define SDXC_PSTATE_CARD_STABLE_MASK (0x20000UL) +#define SDXC_PSTATE_CARD_STABLE_SHIFT (17U) +#define SDXC_PSTATE_CARD_STABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_STABLE_MASK) >> SDXC_PSTATE_CARD_STABLE_SHIFT) + +/* + * CARD_INSERTED (R) + * + * Card Inserted + * This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. + * Values: + * 0x0 (FALSE): Reset, Debouncing, or No card + * 0x1 (TRUE): Card Inserted + */ +#define SDXC_PSTATE_CARD_INSERTED_MASK (0x10000UL) +#define SDXC_PSTATE_CARD_INSERTED_SHIFT (16U) +#define SDXC_PSTATE_CARD_INSERTED_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_INSERTED_MASK) >> SDXC_PSTATE_CARD_INSERTED_SHIFT) + +/* + * BUF_RD_ENABLE (R) + * + * Buffer Read Enable + * This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. + * Values: + * 0x0 (DISABLED): Read disable + * 0x1 (ENABLED): Read enable + */ +#define SDXC_PSTATE_BUF_RD_ENABLE_MASK (0x800U) +#define SDXC_PSTATE_BUF_RD_ENABLE_SHIFT (11U) +#define SDXC_PSTATE_BUF_RD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_RD_ENABLE_MASK) >> SDXC_PSTATE_BUF_RD_ENABLE_SHIFT) + +/* + * BUF_WR_ENABLE (R) + * + * Buffer Write Enable + * This bit is used for non-DMA transfers. This bit is set if space is available for writing data. + * Values: + * 0x0 (DISABLED): Write disable + * 0x1 (ENABLED): Write enable + */ +#define SDXC_PSTATE_BUF_WR_ENABLE_MASK (0x400U) +#define SDXC_PSTATE_BUF_WR_ENABLE_SHIFT (10U) +#define SDXC_PSTATE_BUF_WR_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_WR_ENABLE_MASK) >> SDXC_PSTATE_BUF_WR_ENABLE_SHIFT) + +/* + * RD_XFER_ACTIVE (R) + * + * Read Transfer Active + * This bit indicates whether a read transfer is active for SD/eMMC mode. + * Values: + * 0x0 (INACTIVE): No valid data + * 0x1 (ACTIVE): Transferring data + */ +#define SDXC_PSTATE_RD_XFER_ACTIVE_MASK (0x200U) +#define SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT (9U) +#define SDXC_PSTATE_RD_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RD_XFER_ACTIVE_MASK) >> SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT) + +/* + * WR_XFER_ACTIVE (R) + * + * Write Transfer Active + * This status indicates whether a write transfer is active for SD/eMMC mode. + * Values: + * 0x0 (INACTIVE): No valid data + * 0x1 (ACTIVE): Transferring data + */ +#define SDXC_PSTATE_WR_XFER_ACTIVE_MASK (0x100U) +#define SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT (8U) +#define SDXC_PSTATE_WR_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_XFER_ACTIVE_MASK) >> SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT) + +/* + * DAT_7_4 (R) + * + * DAT[7:4] Line Signal Level + * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. + */ +#define SDXC_PSTATE_DAT_7_4_MASK (0xF0U) +#define SDXC_PSTATE_DAT_7_4_SHIFT (4U) +#define SDXC_PSTATE_DAT_7_4_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_7_4_MASK) >> SDXC_PSTATE_DAT_7_4_SHIFT) + +/* + * RE_TUNE_REQ (R) + * + * Re-Tuning Request + * SDXC does not generate retuning request. The software must maintain the Retuning timer. + */ +#define SDXC_PSTATE_RE_TUNE_REQ_MASK (0x8U) +#define SDXC_PSTATE_RE_TUNE_REQ_SHIFT (3U) +#define SDXC_PSTATE_RE_TUNE_REQ_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RE_TUNE_REQ_MASK) >> SDXC_PSTATE_RE_TUNE_REQ_SHIFT) + +/* + * DAT_LINE_ACTIVE (R) + * + * DAT Line Active ( + * This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. + * In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. + * In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. + * For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. + * Values: + * 0x0 (INACTIVE): DAT Line Inactive + * 0x1 (ACTIVE): DAT Line Active + */ +#define SDXC_PSTATE_DAT_LINE_ACTIVE_MASK (0x4U) +#define SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT (2U) +#define SDXC_PSTATE_DAT_LINE_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_LINE_ACTIVE_MASK) >> SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT) + +/* + * DAT_INHIBIT (R) + * + * Command Inhibit (DAT) + * This bit is generated if either DAT line active or Read transfer active is set to 1. + * If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. + * Values: + * 0x0 (READY): Can issue command which used DAT line + * 0x1 (NOT_READY): Cannot issue command which used DAT line + */ +#define SDXC_PSTATE_DAT_INHIBIT_MASK (0x2U) +#define SDXC_PSTATE_DAT_INHIBIT_SHIFT (1U) +#define SDXC_PSTATE_DAT_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_INHIBIT_MASK) >> SDXC_PSTATE_DAT_INHIBIT_SHIFT) + +/* + * CMD_INHIBIT (R) + * + * Command Inhibit (CMD) + * This bit indicates the following : + * If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. + * This bit is set when the command register is written. This bit is cleared when the command response is received. + * This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. + * Values: + * 0x0 (READY): Host Controller is ready to issue a command + * 0x1 (NOT_READY): Host Controller is not ready to issue a command + */ +#define SDXC_PSTATE_CMD_INHIBIT_MASK (0x1U) +#define SDXC_PSTATE_CMD_INHIBIT_SHIFT (0U) +#define SDXC_PSTATE_CMD_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_INHIBIT_MASK) >> SDXC_PSTATE_CMD_INHIBIT_SHIFT) + +/* Bitfield definition for register: PROT_CTRL */ +/* + * CARD_REMOVAL (RW) + * + * Wakeup Event Enable on SD Card Removal + * This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. + * For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. + * Values: + * 0x0 (DISABLED): Disable + * 0x1 (ENABLED): Enable + */ +#define SDXC_PROT_CTRL_CARD_REMOVAL_MASK (0x4000000UL) +#define SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT (26U) +#define SDXC_PROT_CTRL_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) +#define SDXC_PROT_CTRL_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) >> SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) + +/* + * CARD_INSERT (RW) + * + * Wakeup Event Enable on SD Card Insertion + * This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. + * FN_WUS (Wake Up Support) in CIS does not affect this bit. + * Values: + * 0x0 (DISABLED): Disable + * 0x1 (ENABLED): Enable + */ +#define SDXC_PROT_CTRL_CARD_INSERT_MASK (0x2000000UL) +#define SDXC_PROT_CTRL_CARD_INSERT_SHIFT (25U) +#define SDXC_PROT_CTRL_CARD_INSERT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INSERT_SHIFT) & SDXC_PROT_CTRL_CARD_INSERT_MASK) +#define SDXC_PROT_CTRL_CARD_INSERT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INSERT_MASK) >> SDXC_PROT_CTRL_CARD_INSERT_SHIFT) + +/* + * CARD_INT (RW) + * + * Wakeup Event Enable on Card Interrupt + * This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. + * This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. + * Values: + * 0x0 (DISABLED): Disable + * 0x1 (ENABLED): Enable + */ +#define SDXC_PROT_CTRL_CARD_INT_MASK (0x1000000UL) +#define SDXC_PROT_CTRL_CARD_INT_SHIFT (24U) +#define SDXC_PROT_CTRL_CARD_INT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INT_SHIFT) & SDXC_PROT_CTRL_CARD_INT_MASK) +#define SDXC_PROT_CTRL_CARD_INT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INT_MASK) >> SDXC_PROT_CTRL_CARD_INT_SHIFT) + +/* + * INT_AT_BGAP (RW) + * + * Interrupt At Block Gap + * This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. + * Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. + * Values: + * 0x0 (DISABLE): Disabled + * 0x1 (ENABLE): Enabled + */ +#define SDXC_PROT_CTRL_INT_AT_BGAP_MASK (0x80000UL) +#define SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT (19U) +#define SDXC_PROT_CTRL_INT_AT_BGAP_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) +#define SDXC_PROT_CTRL_INT_AT_BGAP_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) >> SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) + +/* + * RD_WAIT_CTRL (RW) + * + * Read Wait Control + * This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. + * Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. + * Values: + * 0x0 (DISABLE): Disable Read Wait Control + * 0x1 (ENABLE): Enable Read Wait Control + */ +#define SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK (0x40000UL) +#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT (18U) +#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) +#define SDXC_PROT_CTRL_RD_WAIT_CTRL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) >> SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) + +/* + * CONTINUE_REQ (RW) + * + * Continue Request + * This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. + * The Host Controller automatically clears this bit when the transaction restarts. + * If stop at block gap request is set to 1, any write to this bit is ignored. + * Values: + * 0x0 (NO_AFFECT): No Affect + * 0x1 (RESTART): Restart + */ +#define SDXC_PROT_CTRL_CONTINUE_REQ_MASK (0x20000UL) +#define SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT (17U) +#define SDXC_PROT_CTRL_CONTINUE_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) +#define SDXC_PROT_CTRL_CONTINUE_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) >> SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) + +/* + * STOP_BG_REQ (RW) + * + * Stop At Block Gap Request + * This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. + * Values: + * 0x0 (XFER): Transfer + * 0x1 (STOP): Stop + */ +#define SDXC_PROT_CTRL_STOP_BG_REQ_MASK (0x10000UL) +#define SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT (16U) +#define SDXC_PROT_CTRL_STOP_BG_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) +#define SDXC_PROT_CTRL_STOP_BG_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) >> SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) + +/* + * SD_BUS_VOL_VDD1 (RW) + * + * SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD + * These bits enable the Host Driver to select the voltage level for an SD/eMMC card. + * Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. + * If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. + * The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. + * SD Bus Voltage Select options: + * 0x7 : 3.3V(Typical) + * 0x6 : 3.0V(Typical) + * 0x5 : 1.8V(Typical) for Embedded + * 0x4 : 0x0 - Reserved + * eMMC Bus Voltage Select options: + * 0x7 : 3.3V(Typical) + * 0x6 : 1.8V(Typical) + * 0x5 : 1.2V(Typical) + * 0x4 : 0x0 - Reserved + * Values: + * 0x7 (V_3_3): 3.3V (Typ.) + * 0x6 (V_3_0): 3.0V (Typ.) + * 0x5 (V_1_8): 1.8V (Typ.) for Embedded + * 0x4 (RSVD4): Reserved + * 0x3 (RSVD3): Reserved + * 0x2 (RSVD2): Reserved + * 0x1 (RSVD1): Reserved + * 0x0 (RSVD0): Reserved + */ +#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK (0xE00U) +#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT (9U) +#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) +#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) + +/* + * EXT_DAT_XFER (RW) + * + * Extended Data Transfer Width + * This bit controls 8-bit bus width mode of embedded device. + * Values: + * 0x1 (EIGHT_BIT): 8-bit Bus Width + * 0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width + */ +#define SDXC_PROT_CTRL_EXT_DAT_XFER_MASK (0x20U) +#define SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT (5U) +#define SDXC_PROT_CTRL_EXT_DAT_XFER_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) +#define SDXC_PROT_CTRL_EXT_DAT_XFER_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) >> SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) + +/* + * DMA_SEL (RW) + * + * DMA Select + * This field is used to select the DMA type. + * When Host Version 4 Enable is 1 in Host Control 2 register: + * 0x0 : SDMA is selected + * 0x1 : Reserved + * 0x2 : ADMA2 is selected + * 0x3 : ADMA2 or ADMA3 is selected + * When Host Version 4 Enable is 0 in Host Control 2 register: + * 0x0 : SDMA is selected + * 0x1 : Reserved + * 0x2 : 32-bit Address ADMA2 is selected + * 0x3 : 64-bit Address ADMA2 is selected + * Values: + * 0x0 (SDMA): SDMA is selected + * 0x1 (RSVD_BIT): Reserved + * 0x2 (ADMA2): ADMA2 is selected + * 0x3 (ADMA2_3): ADMA2 or ADMA3 is selected + */ +#define SDXC_PROT_CTRL_DMA_SEL_MASK (0x18U) +#define SDXC_PROT_CTRL_DMA_SEL_SHIFT (3U) +#define SDXC_PROT_CTRL_DMA_SEL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DMA_SEL_SHIFT) & SDXC_PROT_CTRL_DMA_SEL_MASK) +#define SDXC_PROT_CTRL_DMA_SEL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DMA_SEL_MASK) >> SDXC_PROT_CTRL_DMA_SEL_SHIFT) + +/* + * HIGH_SPEED_EN (RW) + * + * High Speed Enable + * this bit is used to determine the selection of preset value for High Speed mode. + * Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. + * Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. + * Values: + * 0x1 (HIGH_SPEED): High Speed mode + * 0x0 (NORMAL_SPEED): Normal Speed mode + */ +#define SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK (0x4U) +#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT (2U) +#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) +#define SDXC_PROT_CTRL_HIGH_SPEED_EN_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) >> SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) + +/* + * DAT_XFER_WIDTH (RW) + * + * Data Transfer Width + * For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. + * The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. + * Values: + * 0x1 (FOUR_BIT): 4-bit mode + * 0x0 (ONE_BIT): 1-bit mode + */ +#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK (0x2U) +#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT (1U) +#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) +#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) >> SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) + +/* Bitfield definition for register: SYS_CTRL */ +/* + * SW_RST_DAT (RW) + * + * Software Reset For DAT line + * This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. + * The following registers and bits are cleared by this bit: + * Buffer Data Port register + * -Buffer is cleared and initialized. + * Present state register + * -Buffer Read Enable + * -Buffer Write Enable + * -Read Transfer Active + * -Write Transfer Active + * -DAT Line Active + * -Command Inhibit (DAT) + * Block Gap Control register + * -Continue Request + * -Stop At Block Gap Request + * Normal Interrupt status register + * -Buffer Read Ready + * -Buffer Write Ready + * -DMA Interrupt + * -Block Gap Event + * -Transfer Complete + * In UHS-II mode, this bit shall be set to 0 + * Values: + * 0x0 (FALSE): Work + * 0x1 (TRUE): Reset + */ +#define SDXC_SYS_CTRL_SW_RST_DAT_MASK (0x4000000UL) +#define SDXC_SYS_CTRL_SW_RST_DAT_SHIFT (26U) +#define SDXC_SYS_CTRL_SW_RST_DAT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) +#define SDXC_SYS_CTRL_SW_RST_DAT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) >> SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) + +/* + * SW_RST_CMD (RW) + * + * Software Reset For CMD line + * This bit resets only a part of the command circuit to be able to issue a command. + * It bit is also used to initialize a UHS-II command circuit. + * This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. + * Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. + * The following registers and bits are cleared by this bit: + * Present State register : Command Inhibit (CMD) bit + * Normal Interrupt Status register : Command Complete bit + * Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit + * Values: + * 0x0 (FALSE): Work + * 0x1 (TRUE): Reset + */ +#define SDXC_SYS_CTRL_SW_RST_CMD_MASK (0x2000000UL) +#define SDXC_SYS_CTRL_SW_RST_CMD_SHIFT (25U) +#define SDXC_SYS_CTRL_SW_RST_CMD_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) +#define SDXC_SYS_CTRL_SW_RST_CMD_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) >> SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) + +/* + * SW_RST_ALL (RW) + * + * Software Reset For All + * This reset affects the entire Host Controller except for the card detection circuit. + * During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. + * All registers are reset except the capabilities register. + * If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. + * Values: + * 0x0 (FALSE): Work + * 0x1 (TRUE): Reset + */ +#define SDXC_SYS_CTRL_SW_RST_ALL_MASK (0x1000000UL) +#define SDXC_SYS_CTRL_SW_RST_ALL_SHIFT (24U) +#define SDXC_SYS_CTRL_SW_RST_ALL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) +#define SDXC_SYS_CTRL_SW_RST_ALL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) >> SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) + +/* + * TOUT_CNT (RW) + * + * Data Timeout Counter Value. + * This value determines the interval by which DAT line timeouts are detected. + * The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. + * When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). + * The values for these bits are: + * 0xF : Reserved + * 0xE : TMCLK x 2^27 + * ......... + * 0x1 : TMCLK x 2^14 + * 0x0 : TMCLK x 2^13 + * Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. + */ +#define SDXC_SYS_CTRL_TOUT_CNT_MASK (0xF0000UL) +#define SDXC_SYS_CTRL_TOUT_CNT_SHIFT (16U) +#define SDXC_SYS_CTRL_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_TOUT_CNT_SHIFT) & SDXC_SYS_CTRL_TOUT_CNT_MASK) +#define SDXC_SYS_CTRL_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_TOUT_CNT_MASK) >> SDXC_SYS_CTRL_TOUT_CNT_SHIFT) + +/* + * FREQ_SEL (RW) + * + * SDCLK/RCLK Frequency Select + * These bits are used to select the frequency of the SDCLK signal. + * These bits depend on setting of Preset Value Enable in the Host Control 2 register. + * If Preset Value Enable = 0, these bits are set by the Host Driver. + * If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. + * The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. + * 10-bit Divided Clock Mode: + * 0x3FF : 1/2046 Divided clock + * .......... + * N : 1/2N Divided Clock + * .......... + * 0x002 : 1/4 Divided Clock + * 0x001 : 1/2 Divided Clock + * 0x000 : Base clock (10MHz - 255 MHz) + * Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: + * 0x3FF : Base clock * M /1024 + * .......... + * N-1 : Base clock * M /N + * .......... + * 0x002 : Base clock * M /3 + * 0x001 : Base clock * M /2 + * 0x000 : Base clock * M + */ +#define SDXC_SYS_CTRL_FREQ_SEL_MASK (0xFF00U) +#define SDXC_SYS_CTRL_FREQ_SEL_SHIFT (8U) +#define SDXC_SYS_CTRL_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_FREQ_SEL_MASK) +#define SDXC_SYS_CTRL_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_FREQ_SEL_SHIFT) + +/* + * UPPER_FREQ_SEL (RW) + * + * These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. + * The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. + */ +#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK (0xC0U) +#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT (6U) +#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) +#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) + +/* + * CLK_GEN_SELECT (RW) + * + * Clock Generator Select + * This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. + * If Preset Value Enable = 0, this bit is set by the Host Driver. + * If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. + * The value is reflected on the card_clk_gen_sel signal. + * Values: + * 0x0 (FALSE): Divided Clock Mode + * 0x1 (TRUE): Programmable Clock Mode + */ +#define SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK (0x20U) +#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT (5U) +#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) +#define SDXC_SYS_CTRL_CLK_GEN_SELECT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) >> SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) + +/* + * PLL_ENABLE (RW) + * + * PLL Enable + * This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). + * When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. + * Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . + * Values: + * 0x0 (FALSE): PLL is in low power mode + * 0x1 (TRUE): PLL is enabled + */ +#define SDXC_SYS_CTRL_PLL_ENABLE_MASK (0x8U) +#define SDXC_SYS_CTRL_PLL_ENABLE_SHIFT (3U) +#define SDXC_SYS_CTRL_PLL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) +#define SDXC_SYS_CTRL_PLL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) >> SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) + +/* + * SD_CLK_EN (RW) + * + * SD/eMMC Clock Enable + * This bit stops the SDCLK or RCLK when set to 0. + * The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. + * The value is reflected on the clk2card_on pin. + * Values: + * 0x0 (FALSE): Disable providing SDCLK/RCLK + * 0x1 (TRUE): Enable providing SDCLK/RCLK + */ +#define SDXC_SYS_CTRL_SD_CLK_EN_MASK (0x4U) +#define SDXC_SYS_CTRL_SD_CLK_EN_SHIFT (2U) +#define SDXC_SYS_CTRL_SD_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) +#define SDXC_SYS_CTRL_SD_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) >> SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) + +/* + * INTERNAL_CLK_STABLE (RW) + * + * Internal Clock Stable + * This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. + * This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, + * and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. + * Values: + * 0x0 (FALSE): Not Ready + * 0x1 (TRUE): Ready + */ +#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK (0x2U) +#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT (1U) +#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) +#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) + +/* + * INTERNAL_CLK_EN (RW) + * + * Internal Clock Enable + * This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. + * The Host Controller must stop its internal clock to enter a very low power state. + * However, registers can still be read and written to. The value is reflected on the intclk_en signal. + * Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . + * Values: + * 0x0 (FALSE): Stop + * 0x1 (TRUE): Oscillate + */ +#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK (0x1U) +#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT (0U) +#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) +#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) + +/* Bitfield definition for register: INT_STAT */ +/* + * BOOT_ACK_ERR (R/W1C) + * + * Boot Acknowledgement Error + * This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. + * In SD/UHS-II mode, this bit is irrelevant. + */ +#define SDXC_INT_STAT_BOOT_ACK_ERR_MASK (0x10000000UL) +#define SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT (28U) +#define SDXC_INT_STAT_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) +#define SDXC_INT_STAT_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) >> SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) + +/* + * RESP_ERR (R/W1C) + * + * Response Error + * Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Error + */ +#define SDXC_INT_STAT_RESP_ERR_MASK (0x8000000UL) +#define SDXC_INT_STAT_RESP_ERR_SHIFT (27U) +#define SDXC_INT_STAT_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_RESP_ERR_SHIFT) & SDXC_INT_STAT_RESP_ERR_MASK) +#define SDXC_INT_STAT_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RESP_ERR_MASK) >> SDXC_INT_STAT_RESP_ERR_SHIFT) + +/* + * TUNING_ERR (R/W1C) + * + * Tuning Error + * This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure + * (occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). + * By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. + * To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. + * The Tuning Error is higher priority than the other error interrupts generated during data transfer. + * By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. + * This is applicable in SD/eMMC mode. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Error + */ +#define SDXC_INT_STAT_TUNING_ERR_MASK (0x4000000UL) +#define SDXC_INT_STAT_TUNING_ERR_SHIFT (26U) +#define SDXC_INT_STAT_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_TUNING_ERR_SHIFT) & SDXC_INT_STAT_TUNING_ERR_MASK) +#define SDXC_INT_STAT_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_TUNING_ERR_MASK) >> SDXC_INT_STAT_TUNING_ERR_SHIFT) + +/* + * ADMA_ERR (R/W1C) + * + * ADMA Error + * This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: + * Error response received from System bus (Master I/F) + * ADMA3,ADMA2 Descriptors invalid + * CQE Task or Transfer descriptors invalid + * When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. + * In eMMC CQE mode: + * The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. + * ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. + * The Host Driver may find that Valid bit is not set at the error descriptor. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Error + */ +#define SDXC_INT_STAT_ADMA_ERR_MASK (0x2000000UL) +#define SDXC_INT_STAT_ADMA_ERR_SHIFT (25U) +#define SDXC_INT_STAT_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_ADMA_ERR_SHIFT) & SDXC_INT_STAT_ADMA_ERR_MASK) +#define SDXC_INT_STAT_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ADMA_ERR_MASK) >> SDXC_INT_STAT_ADMA_ERR_SHIFT) + +/* + * AUTO_CMD_ERR (R/W1C) + * + * Auto CMD Error + * This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. + * This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. + * D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Error + */ +#define SDXC_INT_STAT_AUTO_CMD_ERR_MASK (0x1000000UL) +#define SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT (24U) +#define SDXC_INT_STAT_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) +#define SDXC_INT_STAT_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) >> SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) + +/* + * CUR_LMT_ERR (R/W1C) + * + * Current Limit Error + * By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. + * If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. + * A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. + * A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. + * The Host Controller may require some sampling time to detect the current limit. + * SDXC Host Controller does not support this function, this bit is always set to 0. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Power Fail + */ +#define SDXC_INT_STAT_CUR_LMT_ERR_MASK (0x800000UL) +#define SDXC_INT_STAT_CUR_LMT_ERR_SHIFT (23U) +#define SDXC_INT_STAT_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) +#define SDXC_INT_STAT_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) >> SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) + +/* + * DATA_END_BIT_ERR (R/W1C) + * + * Data End Bit Error + * This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Error + */ +#define SDXC_INT_STAT_DATA_END_BIT_ERR_MASK (0x400000UL) +#define SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT (22U) +#define SDXC_INT_STAT_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) +#define SDXC_INT_STAT_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) >> SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) + +/* + * DATA_CRC_ERR (R/W1C) + * + * Data CRC Error + * This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, + * when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Error + */ +#define SDXC_INT_STAT_DATA_CRC_ERR_MASK (0x200000UL) +#define SDXC_INT_STAT_DATA_CRC_ERR_SHIFT (21U) +#define SDXC_INT_STAT_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) +#define SDXC_INT_STAT_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) >> SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) + +/* + * DATA_TOUT_ERR (R/W1C) + * + * Data Timeout Error + * This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: + * Busy timeout for R1b, R5b type + * Busy timeout after Write CRC status + * Write CRC Status timeout + * Read Data timeout + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Time out + */ +#define SDXC_INT_STAT_DATA_TOUT_ERR_MASK (0x100000UL) +#define SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT (20U) +#define SDXC_INT_STAT_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) +#define SDXC_INT_STAT_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) >> SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) + +/* + * CMD_IDX_ERR (R/W1C) + * + * Command Index Error + * This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Error + */ +#define SDXC_INT_STAT_CMD_IDX_ERR_MASK (0x80000UL) +#define SDXC_INT_STAT_CMD_IDX_ERR_SHIFT (19U) +#define SDXC_INT_STAT_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) +#define SDXC_INT_STAT_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) >> SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) + +/* + * CMD_END_BIT_ERR (R/W1C) + * + * Command End Bit Error + * This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): End Bit error generated + */ +#define SDXC_INT_STAT_CMD_END_BIT_ERR_MASK (0x40000UL) +#define SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT (18U) +#define SDXC_INT_STAT_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) +#define SDXC_INT_STAT_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) >> SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) + +/* + * CMD_CRC_ERR (R/W1C) + * + * Command CRC Error + * Command CRC Error is generated in SD/eMMC mode for following two cases. + * If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. + * The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. + * If the Host Controller drives the CMD line to 1 level, + * but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. + * The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): CRC error generated + */ +#define SDXC_INT_STAT_CMD_CRC_ERR_MASK (0x20000UL) +#define SDXC_INT_STAT_CMD_CRC_ERR_SHIFT (17U) +#define SDXC_INT_STAT_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) +#define SDXC_INT_STAT_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) >> SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) + +/* + * CMD_TOUT_ERR (R/W1C) + * + * Command Timeout Error + * In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. + * If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Time out + */ +#define SDXC_INT_STAT_CMD_TOUT_ERR_MASK (0x10000UL) +#define SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT (16U) +#define SDXC_INT_STAT_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) +#define SDXC_INT_STAT_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) >> SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) + +/* + * ERR_INTERRUPT (R) + * + * Error Interrupt + * If any of the bits in the Error Interrupt Status register are set, then this bit is set. + * Values: + * 0x0 (FALSE): No Error + * 0x1 (TRUE): Error + */ +#define SDXC_INT_STAT_ERR_INTERRUPT_MASK (0x8000U) +#define SDXC_INT_STAT_ERR_INTERRUPT_SHIFT (15U) +#define SDXC_INT_STAT_ERR_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ERR_INTERRUPT_MASK) >> SDXC_INT_STAT_ERR_INTERRUPT_SHIFT) + +/* + * CQE_EVENT (R/W1C) + * + * Command Queuing Event + * This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. + * Values: + * 0x0 (FALSE): No Event + * 0x1 (TRUE): Command Queuing Event is detected + */ +#define SDXC_INT_STAT_CQE_EVENT_MASK (0x4000U) +#define SDXC_INT_STAT_CQE_EVENT_SHIFT (14U) +#define SDXC_INT_STAT_CQE_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CQE_EVENT_SHIFT) & SDXC_INT_STAT_CQE_EVENT_MASK) +#define SDXC_INT_STAT_CQE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CQE_EVENT_MASK) >> SDXC_INT_STAT_CQE_EVENT_SHIFT) + +/* + * FX_EVENT (R) + * + * FX Event + * This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. + * Values: + * 0x0 (FALSE): No Event + * 0x1 (TRUE): FX Event is detected + */ +#define SDXC_INT_STAT_FX_EVENT_MASK (0x2000U) +#define SDXC_INT_STAT_FX_EVENT_SHIFT (13U) +#define SDXC_INT_STAT_FX_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_FX_EVENT_MASK) >> SDXC_INT_STAT_FX_EVENT_SHIFT) + +/* + * RE_TUNE_EVENT (R) + * + * Re-tuning Event + * This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. + */ +#define SDXC_INT_STAT_RE_TUNE_EVENT_MASK (0x1000U) +#define SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT (12U) +#define SDXC_INT_STAT_RE_TUNE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RE_TUNE_EVENT_MASK) >> SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT) + +/* + * CARD_INTERRUPT (R) + * + * Card Interrupt + * This bit reflects the synchronized value of: + * DAT[1] Interrupt Input for SD Mode + * DAT[2] Interrupt Input for UHS-II Mode + * Values: + * 0x0 (FALSE): No Card Interrupt + * 0x1 (TRUE): Generate Card Interrupt + */ +#define SDXC_INT_STAT_CARD_INTERRUPT_MASK (0x100U) +#define SDXC_INT_STAT_CARD_INTERRUPT_SHIFT (8U) +#define SDXC_INT_STAT_CARD_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INTERRUPT_MASK) >> SDXC_INT_STAT_CARD_INTERRUPT_SHIFT) + +/* + * CARD_REMOVAL (R/W1C) + * + * Card Removal + * This bit is set if the Card Inserted in the Present State register changes from 1 to 0. + * Values: + * 0x0 (FALSE): Card state stable or Debouncing + * 0x1 (TRUE): Card Removed + */ +#define SDXC_INT_STAT_CARD_REMOVAL_MASK (0x80U) +#define SDXC_INT_STAT_CARD_REMOVAL_SHIFT (7U) +#define SDXC_INT_STAT_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_REMOVAL_SHIFT) & SDXC_INT_STAT_CARD_REMOVAL_MASK) +#define SDXC_INT_STAT_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_REMOVAL_MASK) >> SDXC_INT_STAT_CARD_REMOVAL_SHIFT) + +/* + * CARD_INSERTION (R/W1C) + * + * Card Insertion + * This bit is set if the Card Inserted in the Present State register changes from 0 to 1. + * Values: + * 0x0 (FALSE): Card state stable or Debouncing + * 0x1 (TRUE): Card Inserted + */ +#define SDXC_INT_STAT_CARD_INSERTION_MASK (0x40U) +#define SDXC_INT_STAT_CARD_INSERTION_SHIFT (6U) +#define SDXC_INT_STAT_CARD_INSERTION_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_INSERTION_SHIFT) & SDXC_INT_STAT_CARD_INSERTION_MASK) +#define SDXC_INT_STAT_CARD_INSERTION_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INSERTION_MASK) >> SDXC_INT_STAT_CARD_INSERTION_SHIFT) + +/* + * BUF_RD_READY (R/W1C) + * + * Buffer Read Ready + * This bit is set if the Buffer Read Enable changes from 0 to 1. + * Values: + * 0x0 (FALSE): Not ready to read buffer + * 0x1 (TRUE): Ready to read buffer + */ +#define SDXC_INT_STAT_BUF_RD_READY_MASK (0x20U) +#define SDXC_INT_STAT_BUF_RD_READY_SHIFT (5U) +#define SDXC_INT_STAT_BUF_RD_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_RD_READY_SHIFT) & SDXC_INT_STAT_BUF_RD_READY_MASK) +#define SDXC_INT_STAT_BUF_RD_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_RD_READY_MASK) >> SDXC_INT_STAT_BUF_RD_READY_SHIFT) + +/* + * BUF_WR_READY (R/W1C) + * + * Buffer Write Ready + * This bit is set if the Buffer Write Enable changes from 0 to 1. + * Values: + * 0x0 (FALSE): Not ready to write buffer + * 0x1 (TRUE): Ready to write buffer + */ +#define SDXC_INT_STAT_BUF_WR_READY_MASK (0x10U) +#define SDXC_INT_STAT_BUF_WR_READY_SHIFT (4U) +#define SDXC_INT_STAT_BUF_WR_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_WR_READY_SHIFT) & SDXC_INT_STAT_BUF_WR_READY_MASK) +#define SDXC_INT_STAT_BUF_WR_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_WR_READY_MASK) >> SDXC_INT_STAT_BUF_WR_READY_SHIFT) + +/* + * DMA_INTERRUPT (R/W1C) + * + * DMA Interrupt + * This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. + * In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. + * This interrupt is not generated after a Transfer Complete. + * Values: + * 0x0 (FALSE): No DMA Interrupt + * 0x1 (TRUE): DMA Interrupt is generated + */ +#define SDXC_INT_STAT_DMA_INTERRUPT_MASK (0x8U) +#define SDXC_INT_STAT_DMA_INTERRUPT_SHIFT (3U) +#define SDXC_INT_STAT_DMA_INTERRUPT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) +#define SDXC_INT_STAT_DMA_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) >> SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) + +/* + * BGAP_EVENT (R/W1C) + * + * Block Gap Event + * This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. + * Values: + * 0x0 (FALSE): No Block Gap Event + * 0x1 (TRUE): Transaction stopped at block gap + */ +#define SDXC_INT_STAT_BGAP_EVENT_MASK (0x4U) +#define SDXC_INT_STAT_BGAP_EVENT_SHIFT (2U) +#define SDXC_INT_STAT_BGAP_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BGAP_EVENT_SHIFT) & SDXC_INT_STAT_BGAP_EVENT_MASK) +#define SDXC_INT_STAT_BGAP_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BGAP_EVENT_MASK) >> SDXC_INT_STAT_BGAP_EVENT_SHIFT) + +/* + * XFER_COMPLETE (R/W1C) + * + * Transfer Complete + * This bit is set when a read/write transfer and a command with status busy is completed. + * Values: + * 0x0 (FALSE): Not complete + * 0x1 (TRUE): Command execution is completed + */ +#define SDXC_INT_STAT_XFER_COMPLETE_MASK (0x2U) +#define SDXC_INT_STAT_XFER_COMPLETE_SHIFT (1U) +#define SDXC_INT_STAT_XFER_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_XFER_COMPLETE_SHIFT) & SDXC_INT_STAT_XFER_COMPLETE_MASK) +#define SDXC_INT_STAT_XFER_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_XFER_COMPLETE_MASK) >> SDXC_INT_STAT_XFER_COMPLETE_SHIFT) + +/* + * CMD_COMPLETE (R/W1C) + * + * Command Complete + * In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. + * This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. + * Values: + * 0x0 (FALSE): No command complete + * 0x1 (TRUE): Command Complete + */ +#define SDXC_INT_STAT_CMD_COMPLETE_MASK (0x1U) +#define SDXC_INT_STAT_CMD_COMPLETE_SHIFT (0U) +#define SDXC_INT_STAT_CMD_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_COMPLETE_SHIFT) & SDXC_INT_STAT_CMD_COMPLETE_MASK) +#define SDXC_INT_STAT_CMD_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_COMPLETE_MASK) >> SDXC_INT_STAT_CMD_COMPLETE_SHIFT) + +/* Bitfield definition for register: INT_STAT_EN */ +/* + * BOOT_ACK_ERR_STAT_EN (RW) + * + * Boot Acknowledgment Error (eMMC Mode only) + * Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK (0x10000000UL) +#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT (28U) +#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) + +/* + * RESP_ERR_STAT_EN (RW) + * + * Response Error Status Enable (SD Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK (0x8000000UL) +#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT (27U) +#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) + +/* + * TUNING_ERR_STAT_EN (RW) + * + * Tuning Error Status Enable (UHS-I Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK (0x4000000UL) +#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT (26U) +#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) + +/* + * ADMA_ERR_STAT_EN (RW) + * + * ADMA Error Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK (0x2000000UL) +#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT (25U) +#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) + +/* + * AUTO_CMD_ERR_STAT_EN (RW) + * + * Auto CMD Error Status Enable (SD/eMMC Mode only). + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK (0x1000000UL) +#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT (24U) +#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) + +/* + * CUR_LMT_ERR_STAT_EN (RW) + * + * Current Limit Error Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK (0x800000UL) +#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT (23U) +#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) + +/* + * DATA_END_BIT_ERR_STAT_EN (RW) + * + * Data End Bit Error Status Enable (SD/eMMC Mode only). + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK (0x400000UL) +#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT (22U) +#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) + +/* + * DATA_CRC_ERR_STAT_EN (RW) + * + * Data CRC Error Status Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK (0x200000UL) +#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT (21U) +#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) + +/* + * DATA_TOUT_ERR_STAT_EN (RW) + * + * Data Timeout Error Status Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK (0x100000UL) +#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT (20U) +#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) + +/* + * CMD_IDX_ERR_STAT_EN (RW) + * + * Command Index Error Status Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK (0x80000UL) +#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT (19U) +#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) + +/* + * CMD_END_BIT_ERR_STAT_EN (RW) + * + * Command End Bit Error Status Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK (0x40000UL) +#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT (18U) +#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) + +/* + * CMD_CRC_ERR_STAT_EN (RW) + * + * Command CRC Error Status Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK (0x20000UL) +#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT (17U) +#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) + +/* + * CMD_TOUT_ERR_STAT_EN (RW) + * + * Command Timeout Error Status Enable (SD/eMMC Mode only). + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK (0x10000UL) +#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT (16U) +#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) + +/* + * CQE_EVENT_STAT_EN (RW) + * + * CQE Event Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK (0x4000U) +#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT (14U) +#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) + +/* + * FX_EVENT_STAT_EN (RW) + * + * FX Event Status Enable + * This bit is added from Version 4.10. + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK (0x2000U) +#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT (13U) +#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) + +/* + * RE_TUNE_EVENT_STAT_EN (RW) + * + * Re-Tuning Event (UHS-I only) Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK (0x1000U) +#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT (12U) +#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) + +/* + * CARD_INTERRUPT_STAT_EN (RW) + * + * Card Interrupt Status Enable + * If this bit is set to 0, the Host Controller clears the interrupt request to the System. + * The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. + * The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. + * By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK (0x100U) +#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT (8U) +#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) + +/* + * CARD_REMOVAL_STAT_EN (RW) + * + * Card Removal Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK (0x80U) +#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT (7U) +#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) + +/* + * CARD_INSERTION_STAT_EN (RW) + * + * Card Insertion Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK (0x40U) +#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT (6U) +#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) + +/* + * BUF_RD_READY_STAT_EN (RW) + * + * Buffer Read Ready Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK (0x20U) +#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT (5U) +#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) + +/* + * BUF_WR_READY_STAT_EN (RW) + * + * Buffer Write Ready Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK (0x10U) +#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT (4U) +#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) + +/* + * DMA_INTERRUPT_STAT_EN (RW) + * + * DMA Interrupt Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK (0x8U) +#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT (3U) +#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) + +/* + * BGAP_EVENT_STAT_EN (RW) + * + * Block Gap Event Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK (0x4U) +#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT (2U) +#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) + +/* + * XFER_COMPLETE_STAT_EN (RW) + * + * Transfer Complete Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK (0x2U) +#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT (1U) +#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) + +/* + * CMD_COMPLETE_STAT_EN (RW) + * + * Command Complete Status Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK (0x1U) +#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT (0U) +#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) +#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) + +/* Bitfield definition for register: INT_SIGNAL_EN */ +/* + * BOOT_ACK_ERR_SIGNAL_EN (RW) + * + * Boot Acknowledgment Error (eMMC Mode only). + * Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgement Error in Error Interrupt Status register is set. + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK (0x10000000UL) +#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT (28U) +#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) + +/* + * RESP_ERR_SIGNAL_EN (RW) + * + * Response Error Signal Enable (SD Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK (0x8000000UL) +#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT (27U) +#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) + +/* + * TUNING_ERR_SIGNAL_EN (RW) + * + * Tuning Error Signal Enable (UHS-I Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK (0x4000000UL) +#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT (26U) +#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) + +/* + * ADMA_ERR_SIGNAL_EN (RW) + * + * ADMA Error Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK (0x2000000UL) +#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT (25U) +#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) + +/* + * AUTO_CMD_ERR_SIGNAL_EN (RW) + * + * Auto CMD Error Signal Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK (0x1000000UL) +#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT (24U) +#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) + +/* + * CUR_LMT_ERR_SIGNAL_EN (RW) + * + * Current Limit Error Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK (0x800000UL) +#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT (23U) +#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) + +/* + * DATA_END_BIT_ERR_SIGNAL_EN (RW) + * + * Data End Bit Error Signal Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK (0x400000UL) +#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT (22U) +#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) + +/* + * DATA_CRC_ERR_SIGNAL_EN (RW) + * + * Data CRC Error Signal Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK (0x200000UL) +#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT (21U) +#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) + +/* + * DATA_TOUT_ERR_SIGNAL_EN (RW) + * + * Data Timeout Error Signal Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK (0x100000UL) +#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT (20U) +#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) + +/* + * CMD_IDX_ERR_SIGNAL_EN (RW) + * + * Command Index Error Signal Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): No error + * 0x1 (TRUE): Error + */ +#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK (0x80000UL) +#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT (19U) +#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) + +/* + * CMD_END_BIT_ERR_SIGNAL_EN (RW) + * + * Command End Bit Error Signal Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK (0x40000UL) +#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT (18U) +#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) + +/* + * CMD_CRC_ERR_SIGNAL_EN (RW) + * + * Command CRC Error Signal Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK (0x20000UL) +#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT (17U) +#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) + +/* + * CMD_TOUT_ERR_SIGNAL_EN (RW) + * + * Command Timeout Error Signal Enable (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK (0x10000UL) +#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT (16U) +#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) + +/* + * CQE_EVENT_SIGNAL_EN (RW) + * + * Command Queuing Engine Event Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK (0x4000U) +#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT (14U) +#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) + +/* + * FX_EVENT_SIGNAL_EN (RW) + * + * FX Event Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK (0x2000U) +#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT (13U) +#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) + +/* + * RE_TUNE_EVENT_SIGNAL_EN (RW) + * + * Re-Tuning Event (UHS-I only) Signal Enable. + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK (0x1000U) +#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT (12U) +#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) + +/* + * CARD_INTERRUPT_SIGNAL_EN (RW) + * + * Card Interrupt Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK (0x100U) +#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT (8U) +#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) + +/* + * CARD_REMOVAL_SIGNAL_EN (RW) + * + * Card Removal Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK (0x80U) +#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT (7U) +#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) + +/* + * CARD_INSERTION_SIGNAL_EN (RW) + * + * Card Insertion Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK (0x40U) +#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT (6U) +#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) + +/* + * BUF_RD_READY_SIGNAL_EN (RW) + * + * Buffer Read Ready Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK (0x20U) +#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT (5U) +#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) + +/* + * BUF_WR_READY_SIGNAL_EN (RW) + * + * Buffer Write Ready Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK (0x10U) +#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT (4U) +#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) + +/* + * DMA_INTERRUPT_SIGNAL_EN (RW) + * + * DMA Interrupt Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK (0x8U) +#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT (3U) +#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) + +/* + * BGAP_EVENT_SIGNAL_EN (RW) + * + * Block Gap Event Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK (0x4U) +#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT (2U) +#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) + +/* + * XFER_COMPLETE_SIGNAL_EN (RW) + * + * Transfer Complete Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK (0x2U) +#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT (1U) +#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) + +/* + * CMD_COMPLETE_SIGNAL_EN (RW) + * + * Command Complete Signal Enable + * Values: + * 0x0 (FALSE): Masked + * 0x1 (TRUE): Enabled + */ +#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK (0x1U) +#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT (0U) +#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) +#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) + +/* Bitfield definition for register: AC_HOST_CTRL */ +/* + * PRESET_VAL_ENABLE (RW) + * + * Preset Value Enable + * This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. + * When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. + * These values are selected from set of Preset Value registers based on selected speed mode. + * Values: + * 0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver + * 0x1 (TRUE): Automatic Selection by Preset Value are Enabled + */ +#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK (0x80000000UL) +#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT (31U) +#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) +#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) + +/* + * ASYNC_INT_ENABLE (RW) + * + * Asynchronous Interrupt Enable + * This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. + * Values: + * 0x0 (FALSE): Disabled + * 0x1 (TRUE): Enabled + */ +#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK (0x40000000UL) +#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT (30U) +#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) +#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) + +/* + * HOST_VER4_ENABLE (RW) + * + * Host Version 4 Enable + * This bit selects either Version 3.00 compatible mode or Version 4 mode. + * Functions of following fields are modified for Host Version 4 mode: + * SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) + * ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register + * 64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 + * Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register + * 32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register + * Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, + * UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). + * Values: + * 0x0 (FALSE): Version 3.00 compatible mode + * 0x1 (TRUE): Version 4 mode + */ +#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK (0x10000000UL) +#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT (28U) +#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) +#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) + +/* + * CMD23_ENABLE (RW) + * + * CMD23 Enable + * If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. + * Values: + * 0x0 (FALSE): Auto CMD23 is disabled + * 0x1 (TRUE): Auto CMD23 is enabled + */ +#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK (0x8000000UL) +#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT (27U) +#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) +#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) + +/* + * ADMA2_LEN_MODE (RW) + * + * ADMA2 Length Mode + * This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. + * Values: + * 0x0 (FALSE): 16-bit Data Length Mode + * 0x1 (TRUE): 26-bit Data Length Mode + */ +#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK (0x4000000UL) +#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT (26U) +#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) +#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) >> SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) + +/* + * SAMPLE_CLK_SEL (RW) + * + * Sampling Clock Select + * This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. + * This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). + * Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. + * The value is reflected on the sample_cclk_sel pin. + * Values: + * 0x0 (FALSE): Fixed clock is used to sample data + * 0x1 (TRUE): Tuned clock is used to sample data + */ +#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK (0x800000UL) +#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT (23U) +#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) +#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) >> SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) + +/* + * EXEC_TUNING (RW) + * + * Execute Tuning + * This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. + * Values: + * 0x0 (FALSE): Not Tuned or Tuning completed + * 0x1 (TRUE): Execute Tuning + */ +#define SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK (0x400000UL) +#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT (22U) +#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) +#define SDXC_AC_HOST_CTRL_EXEC_TUNING_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) >> SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) + +/* + * SIGNALING_EN (RW) + * + * 1.8V Signaling Enable + * This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. + * Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. + * Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. + * Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). + * Values: + * 0x0 (V_3_3): 3.3V Signalling + * 0x1 (V_1_8): 1.8V Signalling + */ +#define SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK (0x80000UL) +#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT (19U) +#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) +#define SDXC_AC_HOST_CTRL_SIGNALING_EN_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) >> SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) + +/* + * UHS_MODE_SEL (RW) + * + * UHS Mode/eMMC Speed Mode Select + * These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. + * UHS Mode (SD/UHS-II mode only): + * 0x0 (SDR12): SDR12/Legacy + * 0x1 (SDR25): SDR25/High Speed SDR + * 0x2 (SDR50): SDR50 + * 0x3 (SDR104): SDR104/HS200 + * 0x4 (DDR50): DDR50/High Speed DDR + * 0x5 (RSVD5): Reserved + * 0x6 (RSVD6): Reserved + * 0x7 (UHS2): UHS-II/HS400 + * eMMC Speed Mode (eMMC mode only): + * 0x0: Legacy + * 0x1: High Speed SDR + * 0x2: Reserved + * 0x3: HS200 + * 0x4: High Speed DDR + * 0x5: Reserved + * 0x6: Reserved + * 0x7: HS400 + */ +#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK (0x70000UL) +#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT (16U) +#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) +#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) >> SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) + +/* + * CMD_NOT_ISSUED_AUTO_CMD12 (R) + * + * Command Not Issued By Auto CMD12 Error + * If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. + * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. + * Values: + * 0x1 (TRUE): Not Issued + * 0x0 (FALSE): No Error + */ +#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U) +#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U) +#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) + +/* + * AUTO_CMD_RESP_ERR (R) + * + * Auto CMD Response Error + * This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. + * This status is ignored if any bit between D00 to D04 is set to 1. + * Values: + * 0x1 (TRUE): Error + * 0x0 (FALSE): No Error + */ +#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK (0x20U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT (5U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT) + +/* + * AUTO_CMD_IDX_ERR (R) + * + * Auto CMD Index Error + * This bit is set if the command index error occurs in response to a command. + * Values: + * 0x1 (TRUE): Error + * 0x0 (FALSE): No Error + */ +#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK (0x10U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT (4U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT) + +/* + * AUTO_CMD_EBIT_ERR (R) + * + * Auto CMD End Bit Error + * This bit is set when detecting that the end bit of command response is 0. + * Values: + * 0x1 (TRUE): End Bit Error Generated + * 0x0 (FALSE): No Error + */ +#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK (0x8U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT (3U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT) + +/* + * AUTO_CMD_CRC_ERR (R) + * + * Auto CMD CRC Error + * This bit is set when detecting a CRC error in the command response. + * Values: + * 0x1 (TRUE): CRC Error Generated + * 0x0 (FALSE): No Error + */ +#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK (0x4U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT (2U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT) + +/* + * AUTO_CMD_TOUT_ERR (R) + * + * Auto CMD Timeout Error + * This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. + * If this bit is set to 1, error status bits (D04-D01) are meaningless. + * Values: + * 0x1 (TRUE): Time out + * 0x0 (FALSE): No Error + */ +#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK (0x2U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT (1U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT) + +/* + * AUTO_CMD12_NOT_EXEC (R) + * + * Auto CMD12 Not Executed + * If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. + * Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. + * If this bit is set to 1, error status bits (D04-D01) is meaningless. + * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. + * Values: + * 0x1 (TRUE): Not Executed + * 0x0 (FALSE): Executed + */ +#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK (0x1U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT (0U) +#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT) + +/* Bitfield definition for register: CAPABILITIES1 */ +/* + * SLOT_TYPE_R (R) + * + * Slot Type + * These bits indicate usage of a slot by a specific Host System. + * Values: + * 0x0 (REMOVABLE_SLOT): Removable Card Slot + * 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device + * 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) + * 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices + */ +#define SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK (0xC0000000UL) +#define SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT (30U) +#define SDXC_CAPABILITIES1_SLOT_TYPE_R_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK) >> SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT) + +/* + * ASYNC_INT_SUPPORT (R) + * + * Asynchronous Interrupt Support (SD Mode only) + * Values: + * 0x0 (FALSE): Asynchronous Interrupt Not Supported + * 0x1 (TRUE): Asynchronous Interrupt Supported + */ +#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK (0x20000000UL) +#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT (29U) +#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT) + +/* + * VOLT_18 (R) + * + * Voltage Support for 1.8V + * Values: + * 0x0 (FALSE): 1.8V Not Supported + * 0x1 (TRUE): 1.8V Supported + */ +#define SDXC_CAPABILITIES1_VOLT_18_MASK (0x4000000UL) +#define SDXC_CAPABILITIES1_VOLT_18_SHIFT (26U) +#define SDXC_CAPABILITIES1_VOLT_18_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_18_MASK) >> SDXC_CAPABILITIES1_VOLT_18_SHIFT) + +/* + * VOLT_30 (R) + * + * Voltage Support for SD 3.0V or Embedded 1.2V + * Values: + * 0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported + * 0x1 (TRUE): SD 3.0V or Embedded Supported + */ +#define SDXC_CAPABILITIES1_VOLT_30_MASK (0x2000000UL) +#define SDXC_CAPABILITIES1_VOLT_30_SHIFT (25U) +#define SDXC_CAPABILITIES1_VOLT_30_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_30_MASK) >> SDXC_CAPABILITIES1_VOLT_30_SHIFT) + +/* + * VOLT_33 (R) + * + * Voltage Support for 3.3V + * Values: + * 0x0 (FALSE): 3.3V Not Supported + * 0x1 (TRUE): 3.3V Supported + */ +#define SDXC_CAPABILITIES1_VOLT_33_MASK (0x1000000UL) +#define SDXC_CAPABILITIES1_VOLT_33_SHIFT (24U) +#define SDXC_CAPABILITIES1_VOLT_33_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_33_MASK) >> SDXC_CAPABILITIES1_VOLT_33_SHIFT) + +/* + * SUS_RES_SUPPORT (R) + * + * Suspense/Resume Support + * This bit indicates whether the Host Controller supports Suspend/Resume functionality. + * If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. + * Values: + * 0x0 (FALSE): Not Supported + * 0x1 (TRUE): Supported + */ +#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK (0x800000UL) +#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT (23U) +#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT) + +/* + * SDMA_SUPPORT (R) + * + * SDMA Support + * This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. + * Values: + * 0x0 (FALSE): SDMA not Supported + * 0x1 (TRUE): SDMA Supported + */ +#define SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK (0x400000UL) +#define SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT (22U) +#define SDXC_CAPABILITIES1_SDMA_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT) + +/* + * HIGH_SPEED_SUPPORT (R) + * + * High Speed Support + * This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. + * Values: + * 0x0 (FALSE): High Speed not Supported + * 0x1 (TRUE): High Speed Supported + */ +#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK (0x200000UL) +#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT (21U) +#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK) >> SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT) + +/* + * ADMA2_SUPPORT (R) + * + * ADMA2 Support + * This bit indicates whether the Host Controller is capable of using ADMA2. + * Values: + * 0x0 (FALSE): ADMA2 not Supported + * 0x1 (TRUE): ADMA2 Supported + */ +#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK (0x80000UL) +#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT (19U) +#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT) + +/* + * EMBEDDED_8_BIT (R) + * + * 8-bit Support for Embedded Device + * This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. + * Values: + * 0x0 (FALSE): 8-bit Bus Width not Supported + * 0x1 (TRUE): 8-bit Bus Width Supported + */ +#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK (0x40000UL) +#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT (18U) +#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK) >> SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT) + +/* + * MAX_BLK_LEN (R) + * + * Maximum Block Length + * This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. + * The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit + * Values: + * 0x0 (ZERO): 512 Byte + * 0x1 (ONE): 1024 Byte + * 0x2 (TWO): 2048 Byte + * 0x3 (THREE): Reserved + */ +#define SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK (0x30000UL) +#define SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT (16U) +#define SDXC_CAPABILITIES1_MAX_BLK_LEN_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK) >> SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT) + +/* + * BASE_CLK_FREQ (R) + * + * Base Clock Frequency for SD clock + * These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. + * 6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. + * The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. + * -0x00 : Get information through another method + * -0x01 : 1 MHz + * -0x02 : 2 MHz + * -............. + * -0x3F : 63 MHz + * -0x40-0xFF : Not Supported + * 8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. + * -0x00 : Get information through another method + * -0x01 : 1 MHz + * -0x02 : 2 MHz + * -............ + * -0xFF : 255 MHz + * If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. + * If these bits are all 0, the Host system has to get information using a different method. + */ +#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK (0xFF00U) +#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT (8U) +#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT) + +/* + * TOUT_CLK_UNIT (R) + * + * Timeout Clock Unit + * This bit shows the unit of base clock frequency used to detect Data TImeout Error. + * Values: + * 0x0 (KHZ): KHz + * 0x1 (MHZ): MHz + */ +#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK (0x80U) +#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT (7U) +#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT) + +/* + * TOUT_CLK_FREQ (R) + * + * Timeout Clock Frequency + * This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. + * 0x00 : Get information through another method + * 0x01 : 1KHz / 1MHz + * 0x02 : 2KHz / 2MHz + * 0x03 : 3KHz / 3MHz + * ........... + * 0x3F : 63KHz / 63MHz + */ +#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK (0x3FU) +#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT (0U) +#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT) + +/* Bitfield definition for register: CAPABILITIES2 */ +/* + * VDD2_18V_SUPPORT (R) + * + * 1.8V VDD2 Support + * This bit indicates support of VDD2 for the Host System. + * 0x0 (FALSE): 1.8V VDD2 is not Supported + * 0x1 (TRUE): 1.8V VDD2 is Supported + */ +#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK (0x10000000UL) +#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT (28U) +#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK) >> SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT) + +/* + * ADMA3_SUPPORT (R) + * + * ADMA3 Support + * This bit indicates whether the Host Controller is capable of using ADMA3. + * Values: + * 0x0 (FALSE): ADMA3 not Supported + * 0x1 (TRUE): ADMA3 Supported + */ +#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK (0x8000000UL) +#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT (27U) +#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK) >> SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT) + +/* + * CLK_MUL (R) + * + * Clock Multiplier + * These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. + * 0x0: Clock Multiplier is not Supported + * 0x1: Clock Multiplier M = 2 + * 0x2: Clock Multiplier M = 3 + * ......... + * 0xFF: Clock Multiplier M = 256 + */ +#define SDXC_CAPABILITIES2_CLK_MUL_MASK (0xFF0000UL) +#define SDXC_CAPABILITIES2_CLK_MUL_SHIFT (16U) +#define SDXC_CAPABILITIES2_CLK_MUL_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_CLK_MUL_MASK) >> SDXC_CAPABILITIES2_CLK_MUL_SHIFT) + +/* + * RE_TUNING_MODES (R) + * + * Re-Tuning Modes (UHS-I only) + * These bits select the re-tuning method and limit the maximum data length. + * Values: + * 0x0 (MODE1): Timer + * 0x1 (MODE2): Timer and Re-Tuning Request (Not supported) + * 0x2 (MODE3): Auto Re-Tuning (for transfer) + * 0x3 (RSVD_MODE): Reserved + */ +#define SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK (0xC000U) +#define SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT (14U) +#define SDXC_CAPABILITIES2_RE_TUNING_MODES_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK) >> SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT) + +/* + * USE_TUNING_SDR50 (R) + * + * Use Tuning for SDR50 (UHS-I only) + * Values: + * 0x0 (ZERO): SDR50 does not require tuning + * 0x1 (ONE): SDR50 requires tuning + */ +#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK (0x2000U) +#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT (13U) +#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK) >> SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT) + +/* + * RETUNE_CNT (R) + * + * Timer Count for Re-Tuning (UHS-I only) + * 0x0: Re-Tuning Timer disabled + * 0x1: 1 seconds + * 0x2: 2 seconds + * 0x3: 4 seconds + * ........ + * 0xB: 1024 seconds + * 0xC: Reserved + * 0xD: Reserved + * 0xE: Reserved + * 0xF: Get information from other source + */ +#define SDXC_CAPABILITIES2_RETUNE_CNT_MASK (0xF00U) +#define SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT (8U) +#define SDXC_CAPABILITIES2_RETUNE_CNT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RETUNE_CNT_MASK) >> SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT) + +/* + * DRV_TYPED (R) + * + * Driver Type D Support (UHS-I only) + * This bit indicates support of Driver Type D for 1.8 Signaling. + * Values: + * 0x0 (FALSE): Driver Type D is not supported + * 0x1 (TRUE): Driver Type D is supported + */ +#define SDXC_CAPABILITIES2_DRV_TYPED_MASK (0x40U) +#define SDXC_CAPABILITIES2_DRV_TYPED_SHIFT (6U) +#define SDXC_CAPABILITIES2_DRV_TYPED_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPED_MASK) >> SDXC_CAPABILITIES2_DRV_TYPED_SHIFT) + +/* + * DRV_TYPEC (R) + * + * Driver Type C Support (UHS-I only) + * This bit indicates support of Driver Type C for 1.8 Signaling. + * Values: + * 0x0 (FALSE): Driver Type C is not supported + * 0x1 (TRUE): Driver Type C is supported + */ +#define SDXC_CAPABILITIES2_DRV_TYPEC_MASK (0x20U) +#define SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT (5U) +#define SDXC_CAPABILITIES2_DRV_TYPEC_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEC_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT) + +/* + * DRV_TYPEA (R) + * + * Driver Type A Support (UHS-I only) + * This bit indicates support of Driver Type A for 1.8 Signaling. + * Values: + * 0x0 (FALSE): Driver Type A is not supported + * 0x1 (TRUE): Driver Type A is supported + */ +#define SDXC_CAPABILITIES2_DRV_TYPEA_MASK (0x10U) +#define SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT (4U) +#define SDXC_CAPABILITIES2_DRV_TYPEA_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEA_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT) + +/* + * UHS2_SUPPORT (R) + * + * UHS-II Support (UHS-II only) + * This bit indicates whether Host Controller supports UHS-II. + * Values: + * 0x0 (FALSE): UHS-II is not supported + * 0x1 (TRUE): UHS-II is supported + */ +#define SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK (0x8U) +#define SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT (3U) +#define SDXC_CAPABILITIES2_UHS2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK) >> SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT) + +/* + * DDR50_SUPPORT (R) + * + * DDR50 Support (UHS-I only) + * Values: + * 0x0 (FALSE): DDR50 is not supported + * 0x1 (TRUE): DDR50 is supported + */ +#define SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK (0x4U) +#define SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT (2U) +#define SDXC_CAPABILITIES2_DDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT) + +/* + * SDR104_SUPPORT (R) + * + * SDR104 Support (UHS-I only) + * This bit mentions that SDR104 requires tuning. + * Values: + * 0x0 (FALSE): SDR104 is not supported + * 0x1 (TRUE): SDR104 is supported + */ +#define SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK (0x2U) +#define SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT (1U) +#define SDXC_CAPABILITIES2_SDR104_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT) + +/* + * SDR50_SUPPORT (R) + * + * SDR50 Support (UHS-I only) + * This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. + * Values: + * 0x0 (FALSE): SDR50 is not supported + * 0x1 (TRUE): SDR50 is supported + */ +#define SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK (0x1U) +#define SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT (0U) +#define SDXC_CAPABILITIES2_SDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT) + +/* Bitfield definition for register: CURR_CAPABILITIES1 */ +/* + * MAX_CUR_18V (R) + * + * Maximum Current for 1.8V + * This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. + * 0: Get information through another method + * 1: 4mA + * 2: 8mA + * 3: 13mA + * ....... + * 255: 1020mA + */ +#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK (0xFF0000UL) +#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT (16U) +#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT) + +/* + * MAX_CUR_30V (R) + * + * Maximum Current for 3.0V + * This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. + * 0: Get information through another method + * 1: 4mA + * 2: 8mA + * 3: 13mA + * ....... + * 255: 1020mA + */ +#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK (0xFF00U) +#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT (8U) +#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT) + +/* + * MAX_CUR_33V (R) + * + * Maximum Current for 3.3V + * This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. + * 0: Get information through another method + * 1: 4mA + * 2: 8mA + * 3: 13mA + * ....... + * 255: 1020mA + */ +#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK (0xFFU) +#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT (0U) +#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT) + +/* Bitfield definition for register: CURR_CAPABILITIES2 */ +/* + * MAX_CUR_VDD2_18V (R) + * + * Maximum Current for 1.8V VDD2 + * This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. + * 0: Get information through another method + * 1: 4mA + * 2: 8mA + * 3: 13mA + * ....... + * 255: 1020mA + */ +#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK (0xFFU) +#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT (0U) +#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK) >> SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT) + +/* Bitfield definition for register: FORCE_EVENT */ +/* + * FORCE_BOOT_ACK_ERR (W) + * + * Force Event for Boot Ack error + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Boot ack Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK (0x10000000UL) +#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT (28U) +#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) + +/* + * FORCE_RESP_ERR (W) + * + * Force Event for Response Error (SD Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Response Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK (0x8000000UL) +#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT (27U) +#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) + +/* + * FORCE_TUNING_ERR (W) + * + * Force Event for Tuning Error (UHS-I Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Tuning Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK (0x4000000UL) +#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT (26U) +#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) + +/* + * FORCE_ADMA_ERR (W) + * + * Force Event for ADMA Error + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): ADMA Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK (0x2000000UL) +#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT (25U) +#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) + +/* + * FORCE_AUTO_CMD_ERR (W) + * + * Force Event for Auto CMD Error (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Auto CMD Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK (0x1000000UL) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT (24U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) + +/* + * FORCE_CUR_LMT_ERR (W) + * + * Force Event for Current Limit Error + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Current Limit Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK (0x800000UL) +#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT (23U) +#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) + +/* + * FORCE_DATA_END_BIT_ERR (W) + * + * Force Event for Data End Bit Error (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Data End Bit Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK (0x400000UL) +#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT (22U) +#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) + +/* + * FORCE_DATA_CRC_ERR (W) + * + * Force Event for Data CRC Error (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Data CRC Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK (0x200000UL) +#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT (21U) +#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) + +/* + * FORCE_DATA_TOUT_ERR (W) + * + * Force Event for Data Timeout Error (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Data Timeout Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK (0x100000UL) +#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT (20U) +#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) + +/* + * FORCE_CMD_IDX_ERR (W) + * + * Force Event for Command Index Error (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Command Index Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK (0x80000UL) +#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT (19U) +#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) + +/* + * FORCE_CMD_END_BIT_ERR (W) + * + * Force Event for Command End Bit Error (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Command End Bit Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK (0x40000UL) +#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT (18U) +#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) + +/* + * FORCE_CMD_CRC_ERR (W) + * + * Force Event for Command CRC Error (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Command CRC Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK (0x20000UL) +#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT (17U) +#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) + +/* + * FORCE_CMD_TOUT_ERR (W) + * + * Force Event for Command Timeout Error (SD/eMMC Mode only) + * Values: + * 0x0 (FALSE): Not Affected + * 0x1 (TRUE): Command Timeout Error Status is set + */ +#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK (0x10000UL) +#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT (16U) +#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) + +/* + * FORCE_CMD_NOT_ISSUED_AUTO_CMD12 (W) + * + * Force Event for Command Not Issued By Auto CMD12 Error + * Values: + * 0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set + * 0x0 (FALSE): Not Affected + */ +#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U) +#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U) +#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) +#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) + +/* + * FORCE_AUTO_CMD_RESP_ERR (W) + * + * Force Event for Auto CMD Response Error + * Values: + * 0x1 (TRUE): Auto CMD Response Error Status is set + * 0x0 (FALSE): Not Affected + */ +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK (0x20U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT (5U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) + +/* + * FORCE_AUTO_CMD_IDX_ERR (W) + * + * Force Event for Auto CMD Index Error + * Values: + * 0x1 (TRUE): Auto CMD Index Error Status is set + * 0x0 (FALSE): Not Affected + */ +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK (0x10U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT (4U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) + +/* + * FORCE_AUTO_CMD_EBIT_ERR (W) + * + * Force Event for Auto CMD End Bit Error + * Values: + * 0x1 (TRUE): Auto CMD End Bit Error Status is set + * 0x0 (FALSE): Not Affected + */ +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK (0x8U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT (3U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) + +/* + * FORCE_AUTO_CMD_CRC_ERR (W) + * + * Force Event for Auto CMD CRC Error + * Values: + * 0x1 (TRUE): Auto CMD CRC Error Status is set + * 0x0 (FALSE): Not Affected + */ +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK (0x4U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT (2U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) + +/* + * FORCE_AUTO_CMD_TOUT_ERR (W) + * + * Force Event for Auto CMD Timeout Error + * Values: + * 0x1 (TRUE): Auto CMD Timeout Error Status is set + * 0x0 (FALSE): Not Affected + */ +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK (0x2U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT (1U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) + +/* + * FORCE_AUTO_CMD12_NOT_EXEC (W) + * + * Force Event for Auto CMD12 Not Executed + * Values: + * 0x1 (TRUE): Auto CMD12 Not Executed Status is set + * 0x0 (FALSE): Not Affected + */ +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK (0x1U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT (0U) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) +#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) + +/* Bitfield definition for register: ADMA_ERR_STAT */ +/* + * ADMA_LEN_ERR (R) + * + * ADMA Length Mismatch Error States + * This error occurs in the following instances: + * While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length + * When the total data length cannot be divided by the block length + * Values: + * 0x0 (NO_ERR): No Error + * 0x1 (ERROR): Error + */ +#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK (0x4U) +#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT (2U) +#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT) + +/* + * ADMA_ERR_STATES (R) + * + * ADMA Error States + * These bits indicate the state of ADMA when an error occurs during ADMA data transfer. + * Values: + * 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor + * 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor + * 0x2 (UNUSED): Never set this state + * 0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor + */ +#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK (0x3U) +#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT (0U) +#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT) + +/* Bitfield definition for register: ADMA_SYS_ADDR */ +/* + * ADMA_SA (RW) + * + * ADMA System Address + * These bits indicate the lower 32 bits of the ADMA system address. + * SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location + * ADMA2: This register stores the byte address of the executing command of the descriptor table + * ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. + */ +#define SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK (0xFFFFFFFFUL) +#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT (0U) +#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SET(x) (((uint32_t)(x) << SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) +#define SDXC_ADMA_SYS_ADDR_ADMA_SA_GET(x) (((uint32_t)(x) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) >> SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) + +/* Bitfield definition for register array: PRESET */ +/* + * CLK_GEN_SEL_VAL (R) + * + * Clock Generator Select Value + * This bit is effective when the Host Controller supports a programmable clock generator. + * Values: + * 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator + * 0x1 (PROG): Programmable Clock Generator + */ +#define SDXC_PRESET_CLK_GEN_SEL_VAL_MASK (0x400U) +#define SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT (10U) +#define SDXC_PRESET_CLK_GEN_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_CLK_GEN_SEL_VAL_MASK) >> SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT) + +/* + * FREQ_SEL_VAL (R) + * + * SDCLK/RCLK Frequency Select Value + * 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + */ +#define SDXC_PRESET_FREQ_SEL_VAL_MASK (0x3FFU) +#define SDXC_PRESET_FREQ_SEL_VAL_SHIFT (0U) +#define SDXC_PRESET_FREQ_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_FREQ_SEL_VAL_MASK) >> SDXC_PRESET_FREQ_SEL_VAL_SHIFT) + +/* Bitfield definition for register: ADMA_ID_ADDR */ +/* + * ADMA_ID_ADDR (RW) + * + * ADMA Integrated Descriptor Address + * These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. + * The start address of Integrated Descriptor is set to these register bits. + * The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. + */ +#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK (0xFFFFFFFFUL) +#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT (0U) +#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SET(x) (((uint32_t)(x) << SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) +#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) >> SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) + +/* Bitfield definition for register: P_EMBEDDED_CNTRL */ +/* + * REG_OFFSET_ADDR (R) + * + * Offset Address of Embedded Control register. + */ +#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK (0xFFFU) +#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT (0U) +#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK) >> SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT) + +/* Bitfield definition for register: P_VENDOR_SPECIFIC_AREA */ +/* + * REG_OFFSET_ADDR (R) + * + * Base offset Address for Vendor-Specific registers. + */ +#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFU) +#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U) +#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT) + +/* Bitfield definition for register: P_VENDOR2_SPECIFIC_AREA */ +/* + * REG_OFFSET_ADDR (R) + * + * Base offset Address for Command Queuing registers. + */ +#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFFU) +#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U) +#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT) + +/* Bitfield definition for register: SLOT_INTR_STATUS */ +/* + * INTR_SLOT (R) + * + * Interrupt signal for each Slot + * These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. + * A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. + * By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. + * Bit 00: Slot 1 + * Bit 01: Slot 2 + * Bit 02: Slot 3 + * .......... + * .......... + * Bit 07: Slot 8 + * Note: MSHC Host Controller support single card slot. This register shall always return 0. + */ +#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK (0xFFU) +#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT (0U) +#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_GET(x) (((uint16_t)(x) & SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK) >> SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT) + +/* Bitfield definition for register: CQVER */ +/* + * EMMC_VER_MAHOR (R) + * + * This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. + */ +#define SDXC_CQVER_EMMC_VER_MAHOR_MASK (0xF00U) +#define SDXC_CQVER_EMMC_VER_MAHOR_SHIFT (8U) +#define SDXC_CQVER_EMMC_VER_MAHOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MAHOR_MASK) >> SDXC_CQVER_EMMC_VER_MAHOR_SHIFT) + +/* + * EMMC_VER_MINOR (R) + * + * This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. + */ +#define SDXC_CQVER_EMMC_VER_MINOR_MASK (0xF0U) +#define SDXC_CQVER_EMMC_VER_MINOR_SHIFT (4U) +#define SDXC_CQVER_EMMC_VER_MINOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MINOR_MASK) >> SDXC_CQVER_EMMC_VER_MINOR_SHIFT) + +/* + * EMMC_VER_SUFFIX (R) + * + * This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. + */ +#define SDXC_CQVER_EMMC_VER_SUFFIX_MASK (0xFU) +#define SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT (0U) +#define SDXC_CQVER_EMMC_VER_SUFFIX_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_SUFFIX_MASK) >> SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT) + +/* Bitfield definition for register: CQCAP */ +/* + * CRYPTO_SUPPORT (R) + * + * Crypto Support + * This bit indicates whether the Host Controller supports cryptographic operations. + * Values: + * 0x0 (FALSE): Crypto not Supported + * 0x1 (TRUE): Crypto Supported + */ +#define SDXC_CQCAP_CRYPTO_SUPPORT_MASK (0x10000000UL) +#define SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT (28U) +#define SDXC_CQCAP_CRYPTO_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CQCAP_CRYPTO_SUPPORT_MASK) >> SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT) + +/* + * ITCFMUL (R) + * + * Internal Timer Clock Frequency Multiplier (ITCFMUL) + * This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS + * polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. + * Values: + * 0x0 (CLK_1KHz): 1KHz clock + * 0x1 (CLK_10KHz): 10KHz clock + * 0x2 (CLK_100KHz): 100KHz clock + * 0x3 (CLK_1MHz): 1MHz clock + * 0x4 (CLK_10MHz): 10MHz clock + */ +#define SDXC_CQCAP_ITCFMUL_MASK (0xF000U) +#define SDXC_CQCAP_ITCFMUL_SHIFT (12U) +#define SDXC_CQCAP_ITCFMUL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFMUL_MASK) >> SDXC_CQCAP_ITCFMUL_SHIFT) + +/* + * ITCFVAL (R) + * + * Internal Timer Clock Frequency Value (ITCFVAL) + * This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. + */ +#define SDXC_CQCAP_ITCFVAL_MASK (0x3FFU) +#define SDXC_CQCAP_ITCFVAL_SHIFT (0U) +#define SDXC_CQCAP_ITCFVAL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFVAL_MASK) >> SDXC_CQCAP_ITCFVAL_SHIFT) + +/* Bitfield definition for register: CQCFG */ +/* + * DCMD_EN (RW) + * + * This bit indicates to the hardware whether the Task + * Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. + * Values: + * 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor + * 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor + */ +#define SDXC_CQCFG_DCMD_EN_MASK (0x1000U) +#define SDXC_CQCFG_DCMD_EN_SHIFT (12U) +#define SDXC_CQCFG_DCMD_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_DCMD_EN_SHIFT) & SDXC_CQCFG_DCMD_EN_MASK) +#define SDXC_CQCFG_DCMD_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_DCMD_EN_MASK) >> SDXC_CQCFG_DCMD_EN_SHIFT) + +/* + * TASK_DESC_SIZE (RW) + * + * Bit Value Description + * This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). + * Values: + * 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits + * 0x0 (TASK_DESC_64b): Task descriptor size is 64 bit + */ +#define SDXC_CQCFG_TASK_DESC_SIZE_MASK (0x100U) +#define SDXC_CQCFG_TASK_DESC_SIZE_SHIFT (8U) +#define SDXC_CQCFG_TASK_DESC_SIZE_SET(x) (((uint32_t)(x) << SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) +#define SDXC_CQCFG_TASK_DESC_SIZE_GET(x) (((uint32_t)(x) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) >> SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) + +/* + * CQ_EN (RW) + * + */ +#define SDXC_CQCFG_CQ_EN_MASK (0x1U) +#define SDXC_CQCFG_CQ_EN_SHIFT (0U) +#define SDXC_CQCFG_CQ_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_CQ_EN_SHIFT) & SDXC_CQCFG_CQ_EN_MASK) +#define SDXC_CQCFG_CQ_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_CQ_EN_MASK) >> SDXC_CQCFG_CQ_EN_SHIFT) + +/* Bitfield definition for register: CQCTL */ +/* + * CLR_ALL_TASKS (RW) + * + * Clear all tasks + * This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. + * Values: + * 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller + * 0x0 (NO_EFFECT): Programming 0 has no effect + */ +#define SDXC_CQCTL_CLR_ALL_TASKS_MASK (0x100U) +#define SDXC_CQCTL_CLR_ALL_TASKS_SHIFT (8U) +#define SDXC_CQCTL_CLR_ALL_TASKS_SET(x) (((uint32_t)(x) << SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) +#define SDXC_CQCTL_CLR_ALL_TASKS_GET(x) (((uint32_t)(x) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) >> SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) + +/* + * HALT (RW) + * + * Halt request and resume + * Values: + * 0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. + * For example, issuing a Discard Task command (CMDQ_TASK_MGMT). + * When the software writes 1, CQE completes the ongoing task (if any in progress). + * After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. + * The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. + * 0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity + */ +#define SDXC_CQCTL_HALT_MASK (0x1U) +#define SDXC_CQCTL_HALT_SHIFT (0U) +#define SDXC_CQCTL_HALT_SET(x) (((uint32_t)(x) << SDXC_CQCTL_HALT_SHIFT) & SDXC_CQCTL_HALT_MASK) +#define SDXC_CQCTL_HALT_GET(x) (((uint32_t)(x) & SDXC_CQCTL_HALT_MASK) >> SDXC_CQCTL_HALT_SHIFT) + +/* Bitfield definition for register: CQIS */ +/* + * TCL (RW) + * + * Task cleared interrupt + * This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. + * The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). + * A value of 1 clears this status bit. + * Values: + * 0x1 (SET): TCL Interrupt is set + * 0x0 (NOTSET): TCL Interrupt is not set + */ +#define SDXC_CQIS_TCL_MASK (0x8U) +#define SDXC_CQIS_TCL_SHIFT (3U) +#define SDXC_CQIS_TCL_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCL_SHIFT) & SDXC_CQIS_TCL_MASK) +#define SDXC_CQIS_TCL_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCL_MASK) >> SDXC_CQIS_TCL_SHIFT) + +/* + * RED (RW) + * + * Response error detected interrupt + * This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status + * field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. + * A value of 1 clears this status bit. + * Values: + * 0x1 (SET): RED Interrupt is set + * 0x0 (NOTSET): RED Interrupt is not set + */ +#define SDXC_CQIS_RED_MASK (0x4U) +#define SDXC_CQIS_RED_SHIFT (2U) +#define SDXC_CQIS_RED_SET(x) (((uint32_t)(x) << SDXC_CQIS_RED_SHIFT) & SDXC_CQIS_RED_MASK) +#define SDXC_CQIS_RED_GET(x) (((uint32_t)(x) & SDXC_CQIS_RED_MASK) >> SDXC_CQIS_RED_SHIFT) + +/* + * TCC (RW) + * + * Task complete interrupt + * This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: + * A task is completed and the INT bit is set in its Task Descriptor + * Interrupt caused by Interrupt Coalescing logic due to timeout + * Interrupt Coalescing logic reached the configured threshold + * A value of 1 clears this status bit + */ +#define SDXC_CQIS_TCC_MASK (0x2U) +#define SDXC_CQIS_TCC_SHIFT (1U) +#define SDXC_CQIS_TCC_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCC_SHIFT) & SDXC_CQIS_TCC_MASK) +#define SDXC_CQIS_TCC_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCC_MASK) >> SDXC_CQIS_TCC_SHIFT) + +/* + * HAC (RW) + * + * Halt complete interrupt + * This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. + * A value of 1 clears this status bit. + * Values: + * 0x1 (SET): HAC Interrupt is set + * 0x0 (NOTSET): HAC Interrupt is not set + */ +#define SDXC_CQIS_HAC_MASK (0x1U) +#define SDXC_CQIS_HAC_SHIFT (0U) +#define SDXC_CQIS_HAC_SET(x) (((uint32_t)(x) << SDXC_CQIS_HAC_SHIFT) & SDXC_CQIS_HAC_MASK) +#define SDXC_CQIS_HAC_GET(x) (((uint32_t)(x) & SDXC_CQIS_HAC_MASK) >> SDXC_CQIS_HAC_SHIFT) + +/* Bitfield definition for register: CQISE */ +/* + * TCL_STE (RW) + * + * Task cleared interrupt status enable + * Values: + * 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active + * 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + */ +#define SDXC_CQISE_TCL_STE_MASK (0x8U) +#define SDXC_CQISE_TCL_STE_SHIFT (3U) +#define SDXC_CQISE_TCL_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCL_STE_SHIFT) & SDXC_CQISE_TCL_STE_MASK) +#define SDXC_CQISE_TCL_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCL_STE_MASK) >> SDXC_CQISE_TCL_STE_SHIFT) + +/* + * RED_STE (RW) + * + * Response error detected interrupt status enable + * Values: + * 0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active + * 0x0 (INT_STS_DISABLE): CQIS.RED is disabled + */ +#define SDXC_CQISE_RED_STE_MASK (0x4U) +#define SDXC_CQISE_RED_STE_SHIFT (2U) +#define SDXC_CQISE_RED_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_RED_STE_SHIFT) & SDXC_CQISE_RED_STE_MASK) +#define SDXC_CQISE_RED_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_RED_STE_MASK) >> SDXC_CQISE_RED_STE_SHIFT) + +/* + * TCC_STE (RW) + * + * Task complete interrupt status enable + * Values: + * 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active + * 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + */ +#define SDXC_CQISE_TCC_STE_MASK (0x2U) +#define SDXC_CQISE_TCC_STE_SHIFT (1U) +#define SDXC_CQISE_TCC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCC_STE_SHIFT) & SDXC_CQISE_TCC_STE_MASK) +#define SDXC_CQISE_TCC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCC_STE_MASK) >> SDXC_CQISE_TCC_STE_SHIFT) + +/* + * HAC_STE (RW) + * + * Halt complete interrupt status enable + * Values: + * 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active + * 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled + */ +#define SDXC_CQISE_HAC_STE_MASK (0x1U) +#define SDXC_CQISE_HAC_STE_SHIFT (0U) +#define SDXC_CQISE_HAC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_HAC_STE_SHIFT) & SDXC_CQISE_HAC_STE_MASK) +#define SDXC_CQISE_HAC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_HAC_STE_MASK) >> SDXC_CQISE_HAC_STE_SHIFT) + +/* Bitfield definition for register: CQISGE */ +/* + * TCL_SGE (RW) + * + * Task cleared interrupt signal enable + * Values: + * 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active + * 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled + */ +#define SDXC_CQISGE_TCL_SGE_MASK (0x8U) +#define SDXC_CQISGE_TCL_SGE_SHIFT (3U) +#define SDXC_CQISGE_TCL_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCL_SGE_SHIFT) & SDXC_CQISGE_TCL_SGE_MASK) +#define SDXC_CQISGE_TCL_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCL_SGE_MASK) >> SDXC_CQISGE_TCL_SGE_SHIFT) + +/* + * RED_SGE (RW) + * + * Response error detected interrupt signal enable + * Values: + * 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active + * 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled + */ +#define SDXC_CQISGE_RED_SGE_MASK (0x4U) +#define SDXC_CQISGE_RED_SGE_SHIFT (2U) +#define SDXC_CQISGE_RED_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_RED_SGE_SHIFT) & SDXC_CQISGE_RED_SGE_MASK) +#define SDXC_CQISGE_RED_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_RED_SGE_MASK) >> SDXC_CQISGE_RED_SGE_SHIFT) + +/* + * TCC_SGE (RW) + * + * Task complete interrupt signal enable + * Values: + * 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active + * 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled + */ +#define SDXC_CQISGE_TCC_SGE_MASK (0x2U) +#define SDXC_CQISGE_TCC_SGE_SHIFT (1U) +#define SDXC_CQISGE_TCC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCC_SGE_SHIFT) & SDXC_CQISGE_TCC_SGE_MASK) +#define SDXC_CQISGE_TCC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCC_SGE_MASK) >> SDXC_CQISGE_TCC_SGE_SHIFT) + +/* + * HAC_SGE (RW) + * + * Halt complete interrupt signal enable + * Values: + * 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active + * 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled + */ +#define SDXC_CQISGE_HAC_SGE_MASK (0x1U) +#define SDXC_CQISGE_HAC_SGE_SHIFT (0U) +#define SDXC_CQISGE_HAC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_HAC_SGE_SHIFT) & SDXC_CQISGE_HAC_SGE_MASK) +#define SDXC_CQISGE_HAC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_HAC_SGE_MASK) >> SDXC_CQISGE_HAC_SGE_SHIFT) + +/* Bitfield definition for register: CQIC */ +/* + * INTC_EN (RW) + * + * Interrupt Coalescing Enable Bit + * Values: + * 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated + * 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) + */ +#define SDXC_CQIC_INTC_EN_MASK (0x80000000UL) +#define SDXC_CQIC_INTC_EN_SHIFT (31U) +#define SDXC_CQIC_INTC_EN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_EN_SHIFT) & SDXC_CQIC_INTC_EN_MASK) +#define SDXC_CQIC_INTC_EN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_EN_MASK) >> SDXC_CQIC_INTC_EN_SHIFT) + +/* + * INTC_STAT (R) + * + * Interrupt Coalescing Status Bit + * This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt + * coalescing (that is, this is set if and only if INTC counter > 0). + * Values: + * 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) + * 0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) + */ +#define SDXC_CQIC_INTC_STAT_MASK (0x100000UL) +#define SDXC_CQIC_INTC_STAT_SHIFT (20U) +#define SDXC_CQIC_INTC_STAT_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_STAT_MASK) >> SDXC_CQIC_INTC_STAT_SHIFT) + +/* + * INTC_RST (W) + * + * Counter and Timer Reset + * When host driver writes 1, the interrupt coalescing timer and counter are reset. + * Values: + * 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset + * 0x0 (NO_EFFECT): No Effect + */ +#define SDXC_CQIC_INTC_RST_MASK (0x10000UL) +#define SDXC_CQIC_INTC_RST_SHIFT (16U) +#define SDXC_CQIC_INTC_RST_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_RST_SHIFT) & SDXC_CQIC_INTC_RST_MASK) +#define SDXC_CQIC_INTC_RST_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_RST_MASK) >> SDXC_CQIC_INTC_RST_SHIFT) + +/* + * INTC_TH_WEN (W) + * + * Interrupt Coalescing Counter Threshold Write Enable + * When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. + * Values: + * 0x1 (WEN_SET): Sets INTC_TH_WEN + * 0x0 (WEN_CLR): Clears INTC_TH_WEN + */ +#define SDXC_CQIC_INTC_TH_WEN_MASK (0x8000U) +#define SDXC_CQIC_INTC_TH_WEN_SHIFT (15U) +#define SDXC_CQIC_INTC_TH_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_WEN_SHIFT) & SDXC_CQIC_INTC_TH_WEN_MASK) +#define SDXC_CQIC_INTC_TH_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_WEN_MASK) >> SDXC_CQIC_INTC_TH_WEN_SHIFT) + +/* + * INTC_TH (W) + * + * Interrupt Coalescing Counter Threshold filed + * Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. + * Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. + * The counter is reset by software during the interrupt service routine. + * The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. + * 0x0: Interrupt coalescing feature disabled + * 0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes + * 0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes + * ........ + * 0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes + * To write to this field, the INTC_TH_WEN bit must be set during the same write operation. + */ +#define SDXC_CQIC_INTC_TH_MASK (0x1F00U) +#define SDXC_CQIC_INTC_TH_SHIFT (8U) +#define SDXC_CQIC_INTC_TH_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_SHIFT) & SDXC_CQIC_INTC_TH_MASK) +#define SDXC_CQIC_INTC_TH_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_MASK) >> SDXC_CQIC_INTC_TH_SHIFT) + +/* + * TOUT_VAL_WEN (W) + * + * When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. + * Values: + * 0x1 (WEN_SET): Sets TOUT_VAL_WEN + * 0x0 (WEN_CLR): clears TOUT_VAL_WEN + */ +#define SDXC_CQIC_TOUT_VAL_WEN_MASK (0x80U) +#define SDXC_CQIC_TOUT_VAL_WEN_SHIFT (7U) +#define SDXC_CQIC_TOUT_VAL_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_WEN_SHIFT) & SDXC_CQIC_TOUT_VAL_WEN_MASK) +#define SDXC_CQIC_TOUT_VAL_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_WEN_MASK) >> SDXC_CQIC_TOUT_VAL_WEN_SHIFT) + +/* + * TOUT_VAL (RW) + * + * Interrupt Coalescing Timeout Value + * Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. + * Timer Operation: The timer is reset by software during the interrupt service routine. + * It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. + * When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. + * The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. + * 0x0: Timer is disabled. Timeout-based interrupt is not generated + * 0x1: Timeout on 01x1024 cycles of timer clock frequency + * 0x2: Timeout on 02x1024 cycles of timer clock frequency + * ........ + * 0x7f: Timeout on 127x1024 cycles of timer clock frequency + * In order to write to this field, the TOUT_VAL_WEN bit must + * be set at the same write operation. + */ +#define SDXC_CQIC_TOUT_VAL_MASK (0x7FU) +#define SDXC_CQIC_TOUT_VAL_SHIFT (0U) +#define SDXC_CQIC_TOUT_VAL_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_SHIFT) & SDXC_CQIC_TOUT_VAL_MASK) +#define SDXC_CQIC_TOUT_VAL_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_MASK) >> SDXC_CQIC_TOUT_VAL_SHIFT) + +/* Bitfield definition for register: CQTDLBA */ +/* + * TDLBA (RW) + * + * This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. + * The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. + * This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE + */ +#define SDXC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFUL) +#define SDXC_CQTDLBA_TDLBA_SHIFT (0U) +#define SDXC_CQTDLBA_TDLBA_SET(x) (((uint32_t)(x) << SDXC_CQTDLBA_TDLBA_SHIFT) & SDXC_CQTDLBA_TDLBA_MASK) +#define SDXC_CQTDLBA_TDLBA_GET(x) (((uint32_t)(x) & SDXC_CQTDLBA_TDLBA_MASK) >> SDXC_CQTDLBA_TDLBA_SHIFT) + +/* Bitfield definition for register: CQTDBR */ +/* + * DBR (RW) + * + * The software configures TDLBA and TDLBAU, and enable + * CQE in CQCFG before using this register. + * Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. + * Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. + * CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. + * CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to + * the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. + * The corresponding bit is cleared to 0 by CQE in one of the following events: + * A task execution is completed (with success or error). + * The task is cleared using CQTCLR register. + * All tasks are cleared using CQCTL register. + * CQE is disabled using CQCFG register. + * Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. + * In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. + * If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. + */ +#define SDXC_CQTDBR_DBR_MASK (0xFFFFFFFFUL) +#define SDXC_CQTDBR_DBR_SHIFT (0U) +#define SDXC_CQTDBR_DBR_SET(x) (((uint32_t)(x) << SDXC_CQTDBR_DBR_SHIFT) & SDXC_CQTDBR_DBR_MASK) +#define SDXC_CQTDBR_DBR_GET(x) (((uint32_t)(x) & SDXC_CQTDBR_DBR_MASK) >> SDXC_CQTDBR_DBR_SHIFT) + +/* Bitfield definition for register: CQTCN */ +/* + * TCN (RW) + * + * Task Completion Notification + * Each of the 32 bits are bit mapped to the 32 tasks. + * Bit-N(1): Task-N has completed execution (with success or errors) + * Bit-N(0): Task-N has not completed, could be pending or not submitted. + * On task completion, software may read this register to know tasks that have completed. After reading this register, + * software may clear the relevant bit fields by writing 1 to the corresponding bits. + */ +#define SDXC_CQTCN_TCN_MASK (0xFFFFFFFFUL) +#define SDXC_CQTCN_TCN_SHIFT (0U) +#define SDXC_CQTCN_TCN_SET(x) (((uint32_t)(x) << SDXC_CQTCN_TCN_SHIFT) & SDXC_CQTCN_TCN_MASK) +#define SDXC_CQTCN_TCN_GET(x) (((uint32_t)(x) & SDXC_CQTCN_TCN_MASK) >> SDXC_CQTCN_TCN_SHIFT) + +/* Bitfield definition for register: CQDQS */ +/* + * DQS (RW) + * + * Device Queue Status + * Each of the 32 bits are bit mapped to the 32 tasks. + * Bit-N(1): Device has marked task N as ready for execution + * Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. + * Host controller updates this register with response of the Device Queue Status command. + */ +#define SDXC_CQDQS_DQS_MASK (0xFFFFFFFFUL) +#define SDXC_CQDQS_DQS_SHIFT (0U) +#define SDXC_CQDQS_DQS_SET(x) (((uint32_t)(x) << SDXC_CQDQS_DQS_SHIFT) & SDXC_CQDQS_DQS_MASK) +#define SDXC_CQDQS_DQS_GET(x) (((uint32_t)(x) & SDXC_CQDQS_DQS_MASK) >> SDXC_CQDQS_DQS_SHIFT) + +/* Bitfield definition for register: CQDPT */ +/* + * DPT (RW) + * + * Device-Pending Tasks + * Each of the 32 bits are bit mapped to the 32 tasks. + * Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution + * Bit-N(0): Task-N is not yet queued. + * Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. + * The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. + * Software reads this register in the task-discard procedure to determine if the task is queued in the device + */ +#define SDXC_CQDPT_DPT_MASK (0xFFFFFFFFUL) +#define SDXC_CQDPT_DPT_SHIFT (0U) +#define SDXC_CQDPT_DPT_SET(x) (((uint32_t)(x) << SDXC_CQDPT_DPT_SHIFT) & SDXC_CQDPT_DPT_MASK) +#define SDXC_CQDPT_DPT_GET(x) (((uint32_t)(x) & SDXC_CQDPT_DPT_MASK) >> SDXC_CQDPT_DPT_SHIFT) + +/* Bitfield definition for register: CQTCLR */ +/* + * TCLR (RW) + * + * Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. + * This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. + * When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. + * CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. + * Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. + */ +#define SDXC_CQTCLR_TCLR_MASK (0xFFFFFFFFUL) +#define SDXC_CQTCLR_TCLR_SHIFT (0U) +#define SDXC_CQTCLR_TCLR_SET(x) (((uint32_t)(x) << SDXC_CQTCLR_TCLR_SHIFT) & SDXC_CQTCLR_TCLR_MASK) +#define SDXC_CQTCLR_TCLR_GET(x) (((uint32_t)(x) & SDXC_CQTCLR_TCLR_MASK) >> SDXC_CQTCLR_TCLR_SHIFT) + +/* Bitfield definition for register: CQSSC1 */ +/* + * SQSCMD_BLK_CNT (RW) + * + * This field indicates when SQS CMD is sent while data transfer is in progress. + * A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. + * 0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. + * 0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. + * 0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. + * 0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. + * ........ + * 0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. + * Should be programmed only when CQCFG.CQ_EN is 0 + */ +#define SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK (0xF0000UL) +#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT (16U) +#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) +#define SDXC_CQSSC1_SQSCMD_BLK_CNT_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) >> SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) + +/* + * SQSCMD_IDLE_TMR (RW) + * + * This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. + * Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. + * When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. + * Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. + * The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). + * For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). + * If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. + * Should be programmed only when CQCFG.CQ_EN is '0' + */ +#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK (0xFFFFU) +#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT (0U) +#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) +#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) >> SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) + +/* Bitfield definition for register: CQSSC2 */ +/* + * SQSCMD_RCA (RW) + * + * This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. + * CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. + */ +#define SDXC_CQSSC2_SQSCMD_RCA_MASK (0xFFFFU) +#define SDXC_CQSSC2_SQSCMD_RCA_SHIFT (0U) +#define SDXC_CQSSC2_SQSCMD_RCA_SET(x) (((uint32_t)(x) << SDXC_CQSSC2_SQSCMD_RCA_SHIFT) & SDXC_CQSSC2_SQSCMD_RCA_MASK) +#define SDXC_CQSSC2_SQSCMD_RCA_GET(x) (((uint32_t)(x) & SDXC_CQSSC2_SQSCMD_RCA_MASK) >> SDXC_CQSSC2_SQSCMD_RCA_SHIFT) + +/* Bitfield definition for register: CQCRDCT */ +/* + * DCMD_RESP (R) + * + * This register contains the response of the command generated by the last direct command (DCMD) task that was sent. + * Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. + */ +#define SDXC_CQCRDCT_DCMD_RESP_MASK (0xFFFFFFFFUL) +#define SDXC_CQCRDCT_DCMD_RESP_SHIFT (0U) +#define SDXC_CQCRDCT_DCMD_RESP_GET(x) (((uint32_t)(x) & SDXC_CQCRDCT_DCMD_RESP_MASK) >> SDXC_CQCRDCT_DCMD_RESP_SHIFT) + +/* Bitfield definition for register: CQRMEM */ +/* + * RESP_ERR_MASK (RW) + * + * The bits of this field are bit mapped to the device response. + * This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. + * 1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. + * 0: When a R1/R1b response is received, bit i in the device status is ignored. + * The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. + * Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. + */ +#define SDXC_CQRMEM_RESP_ERR_MASK_MASK (0xFFFFFFFFUL) +#define SDXC_CQRMEM_RESP_ERR_MASK_SHIFT (0U) +#define SDXC_CQRMEM_RESP_ERR_MASK_SET(x) (((uint32_t)(x) << SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) +#define SDXC_CQRMEM_RESP_ERR_MASK_GET(x) (((uint32_t)(x) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) >> SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) + +/* Bitfield definition for register: CQTERRI */ +/* + * TRANS_ERR_TASKID (R) + * + * This field captures the ID of the task that was executed and whose data transfer has errors. + */ +#define SDXC_CQTERRI_TRANS_ERR_TASKID_MASK (0x1F000000UL) +#define SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT (24U) +#define SDXC_CQTERRI_TRANS_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_TASKID_MASK) >> SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT) + +/* + * TRANS_ERR_CMD_INDX (R) + * + * This field captures the index of the command that was executed and whose data transfer has errors. + */ +#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK (0x3F0000UL) +#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT (16U) +#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT) + +/* + * RESP_ERR_FIELDS_VALID (R) + * + * This bit is updated when an error is detected while a command transaction was in progress. + * Values: + * 0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields + * 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX + */ +#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK (0x8000U) +#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT (15U) +#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK) >> SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT) + +/* + * RESP_ERR_TASKID (R) + * + * This field captures the ID of the task which was executed on the command line when the error occurred. + */ +#define SDXC_CQTERRI_RESP_ERR_TASKID_MASK (0x1F00U) +#define SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT (8U) +#define SDXC_CQTERRI_RESP_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_TASKID_MASK) >> SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT) + +/* + * RESP_ERR_CMD_INDX (R) + * + * This field captures the index of the command that was executed on the command line when the error occurred + */ +#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK (0x3FU) +#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT (0U) +#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT) + +/* Bitfield definition for register: CQCRI */ +/* + * CMD_RESP_INDX (R) + * + * Last Command Response index + * This field stores the index of the last received command response. Controller updates the value every time a command response is received + */ +#define SDXC_CQCRI_CMD_RESP_INDX_MASK (0x3FU) +#define SDXC_CQCRI_CMD_RESP_INDX_SHIFT (0U) +#define SDXC_CQCRI_CMD_RESP_INDX_GET(x) (((uint32_t)(x) & SDXC_CQCRI_CMD_RESP_INDX_MASK) >> SDXC_CQCRI_CMD_RESP_INDX_SHIFT) + +/* Bitfield definition for register: CQCRA */ +/* + * CMD_RESP_ARG (R) + * + * Last Command Response argument + * This field stores the argument of the last received command response. Controller updates the value every time a command response is received. + */ +#define SDXC_CQCRA_CMD_RESP_ARG_MASK (0xFFFFFFFFUL) +#define SDXC_CQCRA_CMD_RESP_ARG_SHIFT (0U) +#define SDXC_CQCRA_CMD_RESP_ARG_GET(x) (((uint32_t)(x) & SDXC_CQCRA_CMD_RESP_ARG_MASK) >> SDXC_CQCRA_CMD_RESP_ARG_SHIFT) + +/* Bitfield definition for register: MSHC_VER_ID */ +/* + * VER_ID (R) + * + */ +#define SDXC_MSHC_VER_ID_VER_ID_MASK (0xFFFFFFFFUL) +#define SDXC_MSHC_VER_ID_VER_ID_SHIFT (0U) +#define SDXC_MSHC_VER_ID_VER_ID_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_ID_VER_ID_MASK) >> SDXC_MSHC_VER_ID_VER_ID_SHIFT) + +/* Bitfield definition for register: MSHC_VER_TYPE */ +/* + * VER_TYPE (R) + * + */ +#define SDXC_MSHC_VER_TYPE_VER_TYPE_MASK (0xFFFFFFFFUL) +#define SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT (0U) +#define SDXC_MSHC_VER_TYPE_VER_TYPE_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_TYPE_VER_TYPE_MASK) >> SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT) + +/* Bitfield definition for register: MBIU_CTRL */ +/* + * BURST_INCR16_EN (RW) + * + */ +#define SDXC_MBIU_CTRL_BURST_INCR16_EN_MASK (0x8U) +#define SDXC_MBIU_CTRL_BURST_INCR16_EN_SHIFT (3U) +#define SDXC_MBIU_CTRL_BURST_INCR16_EN_SET(x) (((uint32_t)(x) << SDXC_MBIU_CTRL_BURST_INCR16_EN_SHIFT) & SDXC_MBIU_CTRL_BURST_INCR16_EN_MASK) +#define SDXC_MBIU_CTRL_BURST_INCR16_EN_GET(x) (((uint32_t)(x) & SDXC_MBIU_CTRL_BURST_INCR16_EN_MASK) >> SDXC_MBIU_CTRL_BURST_INCR16_EN_SHIFT) + +/* + * BURST_INCR8_EN (RW) + * + */ +#define SDXC_MBIU_CTRL_BURST_INCR8_EN_MASK (0x4U) +#define SDXC_MBIU_CTRL_BURST_INCR8_EN_SHIFT (2U) +#define SDXC_MBIU_CTRL_BURST_INCR8_EN_SET(x) (((uint32_t)(x) << SDXC_MBIU_CTRL_BURST_INCR8_EN_SHIFT) & SDXC_MBIU_CTRL_BURST_INCR8_EN_MASK) +#define SDXC_MBIU_CTRL_BURST_INCR8_EN_GET(x) (((uint32_t)(x) & SDXC_MBIU_CTRL_BURST_INCR8_EN_MASK) >> SDXC_MBIU_CTRL_BURST_INCR8_EN_SHIFT) + +/* + * BUSRT_INCR4_EN (RW) + * + */ +#define SDXC_MBIU_CTRL_BUSRT_INCR4_EN_MASK (0x2U) +#define SDXC_MBIU_CTRL_BUSRT_INCR4_EN_SHIFT (1U) +#define SDXC_MBIU_CTRL_BUSRT_INCR4_EN_SET(x) (((uint32_t)(x) << SDXC_MBIU_CTRL_BUSRT_INCR4_EN_SHIFT) & SDXC_MBIU_CTRL_BUSRT_INCR4_EN_MASK) +#define SDXC_MBIU_CTRL_BUSRT_INCR4_EN_GET(x) (((uint32_t)(x) & SDXC_MBIU_CTRL_BUSRT_INCR4_EN_MASK) >> SDXC_MBIU_CTRL_BUSRT_INCR4_EN_SHIFT) + +/* + * UNDEFL_INCR_EN (RW) + * + */ +#define SDXC_MBIU_CTRL_UNDEFL_INCR_EN_MASK (0x1U) +#define SDXC_MBIU_CTRL_UNDEFL_INCR_EN_SHIFT (0U) +#define SDXC_MBIU_CTRL_UNDEFL_INCR_EN_SET(x) (((uint32_t)(x) << SDXC_MBIU_CTRL_UNDEFL_INCR_EN_SHIFT) & SDXC_MBIU_CTRL_UNDEFL_INCR_EN_MASK) +#define SDXC_MBIU_CTRL_UNDEFL_INCR_EN_GET(x) (((uint32_t)(x) & SDXC_MBIU_CTRL_UNDEFL_INCR_EN_MASK) >> SDXC_MBIU_CTRL_UNDEFL_INCR_EN_SHIFT) + +/* Bitfield definition for register: EMMC_BOOT_CTRL */ +/* + * BOOT_TOUT_CNT (RW) + * + * Boot Ack Timeout Counter Value. + * This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. + * 0xF : Reserved + * 0xE : TMCLK x 2^27 + * ............ + * 0x1 : TMCLK x 2^14 + * 0x0 : TMCLK x 2^13 + */ +#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK (0xF0000000UL) +#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT (28U) +#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) +#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) + +/* + * BOOT_ACK_ENABLE (RW) + * + * Boot Acknowledge Enable + * When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. + * Values: + * 0x1 (TRUE): Boot Ack enable + * 0x0 (FALSE): Boot Ack disable + */ +#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK (0x1000000UL) +#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT (24U) +#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) +#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) + +/* + * VALIDATE_BOOT (W) + * + * Validate Mandatory Boot Enable bit + * This bit is used to validate the MAN_BOOT_EN bit. + * Values: + * 0x1 (TRUE): Validate Mandatory boot enable bit + * 0x0 (FALSE): Ignore Mandatory boot Enable bit + */ +#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK (0x800000UL) +#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT (23U) +#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) +#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) >> SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) + +/* + * MAN_BOOT_EN (RW) + * + * Mandatory Boot Enable + * This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. + * Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. + * Values: + * 0x1 (MAN_BOOT_EN): Mandatory boot enable + * 0x0 (MAN_BOOT_DIS): Mandatory boot disable + */ +#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK (0x10000UL) +#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT (16U) +#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) +#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) >> SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) + +/* + * CQE_PREFETCH_DISABLE (RW) + * + * Enable or Disable CQE's PREFETCH feature + * This field allows Software to disable CQE's data prefetch feature when set to 1. + * Values: + * 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers + * 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled + */ +#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK (0x400U) +#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT (10U) +#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) +#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) + +/* + * CQE_ALGO_SEL (RW) + * + * Scheduler algorithm selected for execution + * This bit selects the Algorithm used for selecting one of the many ready tasks for execution. + * Values: + * 0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks + * 0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings + */ +#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK (0x200U) +#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT (9U) +#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) +#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) + +/* + * ENH_STROBE_ENABLE (RW) + * + * Enhanced Strobe Enable + * This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. + * Values: + * 0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode + * 0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode + */ +#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK (0x100U) +#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT (8U) +#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) +#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) + +/* + * EMMC_RST_N_OE (RW) + * + * Output Enable control for EMMC Device Reset signal PAD + * control. + * This field drived sd_rst_n_oe output of SDXC + * Values: + * 0x1 (ENABLE): sd_rst_n_oe is 1 + * 0x0 (DISABLE): sd_rst_n_oe is 0 + */ +#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK (0x8U) +#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT (3U) +#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) +#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) + +/* + * EMMC_RST_N (RW) + * + * EMMC Device Reset signal control. + * This register field controls the sd_rst_n output of SDXC + * Values: + * 0x1 (RST_DEASSERT): Reset to eMMC device is deasserted + * 0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) + */ +#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK (0x4U) +#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT (2U) +#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) +#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) + +/* + * DISABLE_DATA_CRC_CHK (RW) + * + * Disable Data CRC Check + * This bit controls masking of CRC16 error for Card Write in eMMC mode. + * This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, + * which may generate CRC error. This CRC error can be masked using this bit during bus testing. + * Values: + * 0x1 (DISABLE): DATA CRC check is disabled + * 0x0 (ENABLE): DATA CRC check is enabled + */ +#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK (0x2U) +#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT (1U) +#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) +#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) >> SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) + +/* + * CARD_IS_EMMC (RW) + * + * eMMC Card present + * This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. + * Values: + * 0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card + * 0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card + */ +#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK (0x1U) +#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT (0U) +#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) +#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) >> SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) + +/* Bitfield definition for register: AUTO_TUNING_CTRL */ +/* + * SWIN_TH_VAL (RW) + * + * Sampling window threshold value setting + * The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps + * can use values from 0x0 to 0x1F. + * This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' + * 0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. + * 0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. + * 0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. + * ........ + * 0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. + */ +#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK (0x7F000000UL) +#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT (24U) +#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) +#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) + +/* + * POST_CHANGE_DLY (RW) + * + * Time taken for phase switching and stable clock output. + * Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. + * Values: + * 0x0 (LATENCY_LT_1): Less than 1-cycle latency + * 0x1 (LATENCY_LT_2): Less than 2-cycle latency + * 0x2 (LATENCY_LT_3): Less than 3-cycle latency + * 0x3 (LATENCY_LT_4): Less than 4-cycle latency + */ +#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK (0x180000UL) +#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT (19U) +#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) +#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) + +/* + * PRE_CHANGE_DLY (RW) + * + * Maximum Latency specification between cclk_tx and cclk_rx. + * Values: + * 0x0 (LATENCY_LT_1): Less than 1-cycle latency + * 0x1 (LATENCY_LT_2): Less than 2-cycle latency + * 0x2 (LATENCY_LT_3): Less than 3-cycle latency + * 0x3 (LATENCY_LT_4): Less than 4-cycle latency + */ +#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK (0x60000UL) +#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT (17U) +#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) +#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) + +/* + * TUNE_CLK_STOP_EN (RW) + * + * Clock stopping control for Tuning and auto-tuning circuit. + * When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. + * This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. + * Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. + * Values: + * 0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change + * 0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching + */ +#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK (0x10000UL) +#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT (16U) +#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) +#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) + +/* + * WIN_EDGE_SEL (RW) + * + * This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. + * 0x0: User selection disabled. Tuning calculated edges are used. + * 0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. + * 0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess + * ... + * 0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. + */ +#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK (0xF00U) +#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT (8U) +#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) +#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) + +/* + * SW_TUNE_EN (RW) + * + * This fields enables software-managed tuning flow. + * Values: + * 0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable. + * 0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled + */ +#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK (0x10U) +#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT (4U) +#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) +#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) + +/* + * RPT_TUNE_ERR (RW) + * + * Framing errors are not generated when executing tuning. + * This debug bit allows users to report these errors. + * Values: + * 0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors + * 0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. + */ +#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK (0x8U) +#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT (3U) +#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) +#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) >> SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) + +/* + * SWIN_TH_EN (RW) + * + * Sampling window Threshold enable + * Selects the tuning mode + * Field should be programmed only when SAMPLE_CLK_SEL is '0' + * Values: + * 0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold + * set by SWIN_TH_VAL field + * 0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window + */ +#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK (0x4U) +#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT (2U) +#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) +#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) + +/* + * CI_SEL (RW) + * + * Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. + * Values: + * 0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval + * 0x1 (WHEN_IN_IDLE): Driven at the end of the transfer + */ +#define SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK (0x2U) +#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT (1U) +#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) +#define SDXC_AUTO_TUNING_CTRL_CI_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) + +/* + * AT_EN (RW) + * + * Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. + * Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. + * This field should be programmed only when CLK_CTRL_R.SD_CLK_EN is 0. + * Values: + * 0x1 (AT_ENABLE): AutoTuning is enabled + * 0x0 (AT_DISABLE): AutoTuning is disabled + */ +#define SDXC_AUTO_TUNING_CTRL_AT_EN_MASK (0x1U) +#define SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT (0U) +#define SDXC_AUTO_TUNING_CTRL_AT_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) +#define SDXC_AUTO_TUNING_CTRL_AT_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) + +/* Bitfield definition for register: AUTO_TUNING_STAT */ +/* + * L_EDGE_PH_CODE (R) + * + * Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. + */ +#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK (0xFF0000UL) +#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT (16U) +#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT) + +/* + * R_EDGE_PH_CODE (R) + * + * Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. + */ +#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK (0xFF00U) +#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT (8U) +#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT) + +/* + * CENTER_PH_CODE (RW) + * + * Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel + */ +#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK (0xFFU) +#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT (0U) +#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) +#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) + +/* Bitfield definition for register: MISC_CTRL0 */ +/* + * IRQ_EN (RW) + * + */ +#define SDXC_MISC_CTRL0_IRQ_EN_MASK (0xC0000000UL) +#define SDXC_MISC_CTRL0_IRQ_EN_SHIFT (30U) +#define SDXC_MISC_CTRL0_IRQ_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_IRQ_EN_SHIFT) & SDXC_MISC_CTRL0_IRQ_EN_MASK) +#define SDXC_MISC_CTRL0_IRQ_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_IRQ_EN_MASK) >> SDXC_MISC_CTRL0_IRQ_EN_SHIFT) + +/* + * CARDCLK_INV_EN (RW) + * + */ +#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK (0x10000000UL) +#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT (28U) +#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) +#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) >> SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT) + +/* + * PAD_CLK_SEL_B (RW) + * + */ +#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK (0x20000UL) +#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT (17U) +#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) +#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) >> SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) + +/* + * CARDCLK_EN_SW (RW) + * + */ +#define SDXC_MISC_CTRL0_CARDCLK_EN_SW_MASK (0x1000U) +#define SDXC_MISC_CTRL0_CARDCLK_EN_SW_SHIFT (12U) +#define SDXC_MISC_CTRL0_CARDCLK_EN_SW_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_CARDCLK_EN_SW_SHIFT) & SDXC_MISC_CTRL0_CARDCLK_EN_SW_MASK) +#define SDXC_MISC_CTRL0_CARDCLK_EN_SW_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_CARDCLK_EN_SW_MASK) >> SDXC_MISC_CTRL0_CARDCLK_EN_SW_SHIFT) + +/* + * FREQ_SEL_SW_EN (RW) + * + */ +#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK (0x800U) +#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT (11U) +#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK) +#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT) + +/* + * TMCLK_EN (RW) + * + */ +#define SDXC_MISC_CTRL0_TMCLK_EN_MASK (0x400U) +#define SDXC_MISC_CTRL0_TMCLK_EN_SHIFT (10U) +#define SDXC_MISC_CTRL0_TMCLK_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_TMCLK_EN_SHIFT) & SDXC_MISC_CTRL0_TMCLK_EN_MASK) +#define SDXC_MISC_CTRL0_TMCLK_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_TMCLK_EN_MASK) >> SDXC_MISC_CTRL0_TMCLK_EN_SHIFT) + +/* + * FREQ_SEL_SW (RW) + * + */ +#define SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK (0x3FFU) +#define SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT (0U) +#define SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) +#define SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT) + +/* Bitfield definition for register: MISC_CTRL1 */ +/* + * CARD_ACTIVE (RW) + * + */ +#define SDXC_MISC_CTRL1_CARD_ACTIVE_MASK (0x80000000UL) +#define SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT (31U) +#define SDXC_MISC_CTRL1_CARD_ACTIVE_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK) +#define SDXC_MISC_CTRL1_CARD_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT) + +/* + * CARD_ACTIVE_PERIOD_SEL (RW) + * + */ +#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK (0x30000000UL) +#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT (28U) +#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) +#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) + + + +/* RESP register group index macro definition */ +#define SDXC_RESP_RESP01 (0UL) +#define SDXC_RESP_RESP23 (1UL) +#define SDXC_RESP_RESP45 (2UL) +#define SDXC_RESP_RESP67 (3UL) + +/* PRESET register group index macro definition */ +#define SDXC_PRESET_INIT (0UL) +#define SDXC_PRESET_DS (1UL) +#define SDXC_PRESET_HS (2UL) +#define SDXC_PRESET_SDR12 (3UL) +#define SDXC_PRESET_SDR25 (4UL) +#define SDXC_PRESET_SDR50 (5UL) +#define SDXC_PRESET_SDR104 (6UL) +#define SDXC_PRESET_DDR50 (7UL) +#define SDXC_PRESET_UHS2 (10UL) + + +#endif /* HPM_SDXC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h new file mode 100644 index 0000000000..444df301a0 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SEC_H +#define HPM_SEC_H + +typedef struct { + __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ + __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ + __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ + __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ + __R uint32_t EVENT; /* 0x10: Event and escalate status */ + __R uint32_t LIFECYCLE; /* 0x14: Lifecycle */ +} SEC_Type; + + +/* Bitfield definition for register: SECURE_STATE */ +/* + * ALLOW_NSC (RO) + * + * Non-secure state allow + * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state + * 1: system is healthy to enter non-secure state + */ +#define SEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) +#define SEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) +#define SEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_NSC_MASK) >> SEC_SECURE_STATE_ALLOW_NSC_SHIFT) + +/* + * ALLOW_SEC (RO) + * + * Secure state allow + * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state + * 1: system is healthy to enter secure state + */ +#define SEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) +#define SEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) +#define SEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_SEC_MASK) >> SEC_SECURE_STATE_ALLOW_SEC_SHIFT) + +/* + * PMIC_FAIL (RW) + * + * PMIC secure state one hot indicator + * 0: secure state is not in fail state + * 1: secure state is in fail state + */ +#define SEC_SECURE_STATE_PMIC_FAIL_MASK (0x80U) +#define SEC_SECURE_STATE_PMIC_FAIL_SHIFT (7U) +#define SEC_SECURE_STATE_PMIC_FAIL_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_FAIL_SHIFT) & SEC_SECURE_STATE_PMIC_FAIL_MASK) +#define SEC_SECURE_STATE_PMIC_FAIL_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_FAIL_MASK) >> SEC_SECURE_STATE_PMIC_FAIL_SHIFT) + +/* + * PMIC_NSC (RW) + * + * PMIC secure state one hot indicator + * 0: secure state is not in non-secure state + * 1: secure state is in non-secure state + */ +#define SEC_SECURE_STATE_PMIC_NSC_MASK (0x40U) +#define SEC_SECURE_STATE_PMIC_NSC_SHIFT (6U) +#define SEC_SECURE_STATE_PMIC_NSC_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_NSC_SHIFT) & SEC_SECURE_STATE_PMIC_NSC_MASK) +#define SEC_SECURE_STATE_PMIC_NSC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_NSC_MASK) >> SEC_SECURE_STATE_PMIC_NSC_SHIFT) + +/* + * PMIC_SEC (RW) + * + * PMIC secure state one hot indicator + * 0: secure state is not in secure state + * 1: secure state is in secure state + */ +#define SEC_SECURE_STATE_PMIC_SEC_MASK (0x20U) +#define SEC_SECURE_STATE_PMIC_SEC_SHIFT (5U) +#define SEC_SECURE_STATE_PMIC_SEC_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_SEC_SHIFT) & SEC_SECURE_STATE_PMIC_SEC_MASK) +#define SEC_SECURE_STATE_PMIC_SEC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_SEC_MASK) >> SEC_SECURE_STATE_PMIC_SEC_SHIFT) + +/* + * PMIC_INS (RW) + * + * PMIC secure state one hot indicator + * 0: secure state is not in inspect state + * 1: secure state is in inspect state + */ +#define SEC_SECURE_STATE_PMIC_INS_MASK (0x10U) +#define SEC_SECURE_STATE_PMIC_INS_SHIFT (4U) +#define SEC_SECURE_STATE_PMIC_INS_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_INS_SHIFT) & SEC_SECURE_STATE_PMIC_INS_MASK) +#define SEC_SECURE_STATE_PMIC_INS_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_INS_MASK) >> SEC_SECURE_STATE_PMIC_INS_SHIFT) + +/* Bitfield definition for register: SECURE_STATE_CONFIG */ +/* + * LOCK (RW) + * + * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset + * 0: not locked, register can be modified + * 1: register locked, write access to the register is ignored + */ +#define SEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) +#define SEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) +#define SEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) +#define SEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) >> SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) + +/* + * ALLOW_RESTART (RW) + * + * allow secure state restart from fail state + * 0: restart is not allowed, only hardware reset can recover secure state + * 1: software is allowed to switch to inspect state from fail state + */ +#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) +#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) +#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) +#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) + +/* Bitfield definition for register: VIOLATION_CONFIG */ +/* + * LOCK_NSC (RW) + * + * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define SEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) +#define SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) +#define SEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) +#define SEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) + +/* + * NSC_VIO_CFG (RW) + * + * configuration of non-secure state violations, each bit represents one security event + * 0: event is not a security violation + * 1: event is a security violation + */ +#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) +#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) +#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) +#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) + +/* + * LOCK_SEC (RW) + * + * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define SEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) +#define SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) +#define SEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) +#define SEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) + +/* + * SEC_VIO_CFG (RW) + * + * configuration of secure state violations, each bit represents one security event + * 0: event is not a security violation + * 1: event is a security violation + */ +#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) +#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) +#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) +#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) + +/* Bitfield definition for register: ESCALATE_CONFIG */ +/* + * LOCK_NSC (RW) + * + * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define SEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) +#define SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) +#define SEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) +#define SEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) + +/* + * NSC_VIO_CFG (RW) + * + * configuration of non-secure state escalates, each bit represents one security event + * 0: event is not a security escalate + * 1: event is a security escalate + */ +#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) +#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) +#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) +#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) + +/* + * LOCK_SEC (RW) + * + * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset + * 0: not locked, configuration can be modified + * 1: register locked, write access to the configuration is ignored + */ +#define SEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) +#define SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) +#define SEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) +#define SEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) + +/* + * SEC_VIO_CFG (RW) + * + * configuration of secure state escalates, each bit represents one security event + * 0: event is not a security escalate + * 1: event is a security escalate + */ +#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) +#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) +#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) +#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) + +/* Bitfield definition for register: EVENT */ +/* + * EVENT (RO) + * + * local event statue, each bit represents one security event + */ +#define SEC_EVENT_EVENT_MASK (0xFFFF0000UL) +#define SEC_EVENT_EVENT_SHIFT (16U) +#define SEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & SEC_EVENT_EVENT_MASK) >> SEC_EVENT_EVENT_SHIFT) + +/* + * PMIC_ESC_NSC (RO) + * + * PMIC is escalating non-secure event + */ +#define SEC_EVENT_PMIC_ESC_NSC_MASK (0x8U) +#define SEC_EVENT_PMIC_ESC_NSC_SHIFT (3U) +#define SEC_EVENT_PMIC_ESC_NSC_GET(x) (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_NSC_MASK) >> SEC_EVENT_PMIC_ESC_NSC_SHIFT) + +/* + * PMIC_ESC_SEC (RO) + * + * PMIC is escalting secure event + */ +#define SEC_EVENT_PMIC_ESC_SEC_MASK (0x4U) +#define SEC_EVENT_PMIC_ESC_SEC_SHIFT (2U) +#define SEC_EVENT_PMIC_ESC_SEC_GET(x) (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_SEC_MASK) >> SEC_EVENT_PMIC_ESC_SEC_SHIFT) + +/* Bitfield definition for register: LIFECYCLE */ +/* + * LIFECYCLE (RO) + * + * lifecycle status, + * bit7: lifecycle_debate, + * bit6: lifecycle_scribe, + * bit5: lifecycle_no_ret, + * bit4: lifecycle_return, + * bit3: lifecycle_secure, + * bit2: lifecycle_nonsec, + * bit1: lifecycle_create, + * bit0: lifecycle_unknow + */ +#define SEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) +#define SEC_LIFECYCLE_LIFECYCLE_SHIFT (0U) +#define SEC_LIFECYCLE_LIFECYCLE_GET(x) (((uint32_t)(x) & SEC_LIFECYCLE_LIFECYCLE_MASK) >> SEC_LIFECYCLE_LIFECYCLE_SHIFT) + + + + +#endif /* HPM_SEC_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h new file mode 100644 index 0000000000..182b415f3e --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h @@ -0,0 +1,980 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SPI_H +#define HPM_SPI_H + +typedef struct { + __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ + __RW uint32_t DIRECTIO; /* 0x14: Direct IO Control Register */ + __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ + __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ + __RW uint32_t CMD; /* 0x24: Command Register */ + __RW uint32_t ADDR; /* 0x28: Address Register */ + __RW uint32_t DATA; /* 0x2C: Data Register */ + __RW uint32_t CTRL; /* 0x30: Control Register */ + __R uint32_t STATUS; /* 0x34: Status Register */ + __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ + __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ + __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ + __R uint8_t RESERVED2[28]; /* 0x44 - 0x5F: Reserved */ + __RW uint32_t SLVST; /* 0x60: Slave Status Register */ + __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ + __R uint8_t RESERVED3[20]; /* 0x68 - 0x7B: Reserved */ + __R uint32_t CONFIG; /* 0x7C: Configuration Register */ +} SPI_Type; + + +/* Bitfield definition for register: TRANSFMT */ +/* + * ADDRLEN (RW) + * + * Address length in bytes + * 0x0: 1 byte + * 0x1: 2 bytes + * 0x2: 3 bytes + * 0x3: 4 bytes + */ +#define SPI_TRANSFMT_ADDRLEN_MASK (0x30000UL) +#define SPI_TRANSFMT_ADDRLEN_SHIFT (16U) +#define SPI_TRANSFMT_ADDRLEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_ADDRLEN_SHIFT) & SPI_TRANSFMT_ADDRLEN_MASK) +#define SPI_TRANSFMT_ADDRLEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_ADDRLEN_MASK) >> SPI_TRANSFMT_ADDRLEN_SHIFT) + +/* + * DATALEN (RW) + * + * The length of each data unit in bits + * The actual bit number of a data unit is (DataLen + 1) + */ +#define SPI_TRANSFMT_DATALEN_MASK (0x1F00U) +#define SPI_TRANSFMT_DATALEN_SHIFT (8U) +#define SPI_TRANSFMT_DATALEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATALEN_SHIFT) & SPI_TRANSFMT_DATALEN_MASK) +#define SPI_TRANSFMT_DATALEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) + +/* + * DATAMERGE (RW) + * + * Enable Data Merge mode, which does automatic data split on write and data coalescing on read. + * This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. + * When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + */ +#define SPI_TRANSFMT_DATAMERGE_MASK (0x80U) +#define SPI_TRANSFMT_DATAMERGE_SHIFT (7U) +#define SPI_TRANSFMT_DATAMERGE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATAMERGE_SHIFT) & SPI_TRANSFMT_DATAMERGE_MASK) +#define SPI_TRANSFMT_DATAMERGE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATAMERGE_MASK) >> SPI_TRANSFMT_DATAMERGE_SHIFT) + +/* + * MOSIBIDIR (RW) + * + * Bi-directional MOSI in regular (single) mode + * 0x0: MOSI is uni-directional signal in regular mode. + * 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + */ +#define SPI_TRANSFMT_MOSIBIDIR_MASK (0x10U) +#define SPI_TRANSFMT_MOSIBIDIR_SHIFT (4U) +#define SPI_TRANSFMT_MOSIBIDIR_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_MOSIBIDIR_SHIFT) & SPI_TRANSFMT_MOSIBIDIR_MASK) +#define SPI_TRANSFMT_MOSIBIDIR_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_MOSIBIDIR_MASK) >> SPI_TRANSFMT_MOSIBIDIR_SHIFT) + +/* + * LSB (RW) + * + * Transfer data with the least significant bit first + * 0x0: Most significant bit first + * 0x1: Least significant bit first + */ +#define SPI_TRANSFMT_LSB_MASK (0x8U) +#define SPI_TRANSFMT_LSB_SHIFT (3U) +#define SPI_TRANSFMT_LSB_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_LSB_SHIFT) & SPI_TRANSFMT_LSB_MASK) +#define SPI_TRANSFMT_LSB_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_LSB_MASK) >> SPI_TRANSFMT_LSB_SHIFT) + +/* + * SLVMODE (RW) + * + * SPI Master/Slave mode selection + * 0x0: Master mode + * 0x1: Slave mode + */ +#define SPI_TRANSFMT_SLVMODE_MASK (0x4U) +#define SPI_TRANSFMT_SLVMODE_SHIFT (2U) +#define SPI_TRANSFMT_SLVMODE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_SLVMODE_SHIFT) & SPI_TRANSFMT_SLVMODE_MASK) +#define SPI_TRANSFMT_SLVMODE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT) + +/* + * CPOL (RW) + * + * SPI Clock Polarity + * 0x0: SCLK is LOW in the idle states + * 0x1: SCLK is HIGH in the idle states + */ +#define SPI_TRANSFMT_CPOL_MASK (0x2U) +#define SPI_TRANSFMT_CPOL_SHIFT (1U) +#define SPI_TRANSFMT_CPOL_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPOL_SHIFT) & SPI_TRANSFMT_CPOL_MASK) +#define SPI_TRANSFMT_CPOL_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPOL_MASK) >> SPI_TRANSFMT_CPOL_SHIFT) + +/* + * CPHA (RW) + * + * SPI Clock Phase + * 0x0: Sampling data at odd SCLK edges + * 0x1: Sampling data at even SCLK edges + */ +#define SPI_TRANSFMT_CPHA_MASK (0x1U) +#define SPI_TRANSFMT_CPHA_SHIFT (0U) +#define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) +#define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) + +/* Bitfield definition for register: DIRECTIO */ +/* + * DIRECTIOEN (RW) + * + * Enable Direct IO + * 0x0: Disable + * 0x1: Enable + */ +#define SPI_DIRECTIO_DIRECTIOEN_MASK (0x1000000UL) +#define SPI_DIRECTIO_DIRECTIOEN_SHIFT (24U) +#define SPI_DIRECTIO_DIRECTIOEN_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_DIRECTIOEN_SHIFT) & SPI_DIRECTIO_DIRECTIOEN_MASK) +#define SPI_DIRECTIO_DIRECTIOEN_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_DIRECTIOEN_MASK) >> SPI_DIRECTIO_DIRECTIOEN_SHIFT) + +/* + * HOLD_OE (RW) + * + * Output enable for the SPI Flash hold signal + */ +#define SPI_DIRECTIO_HOLD_OE_MASK (0x200000UL) +#define SPI_DIRECTIO_HOLD_OE_SHIFT (21U) +#define SPI_DIRECTIO_HOLD_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_OE_SHIFT) & SPI_DIRECTIO_HOLD_OE_MASK) +#define SPI_DIRECTIO_HOLD_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_OE_MASK) >> SPI_DIRECTIO_HOLD_OE_SHIFT) + +/* + * WP_OE (RW) + * + * Output enable for the SPI Flash write protect signal + */ +#define SPI_DIRECTIO_WP_OE_MASK (0x100000UL) +#define SPI_DIRECTIO_WP_OE_SHIFT (20U) +#define SPI_DIRECTIO_WP_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_OE_SHIFT) & SPI_DIRECTIO_WP_OE_MASK) +#define SPI_DIRECTIO_WP_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_OE_MASK) >> SPI_DIRECTIO_WP_OE_SHIFT) + +/* + * MISO_OE (RW) + * + * Output enable fo the SPI MISO signal + */ +#define SPI_DIRECTIO_MISO_OE_MASK (0x80000UL) +#define SPI_DIRECTIO_MISO_OE_SHIFT (19U) +#define SPI_DIRECTIO_MISO_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_OE_SHIFT) & SPI_DIRECTIO_MISO_OE_MASK) +#define SPI_DIRECTIO_MISO_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_OE_MASK) >> SPI_DIRECTIO_MISO_OE_SHIFT) + +/* + * MOSI_OE (RW) + * + * Output enable for the SPI MOSI signal + */ +#define SPI_DIRECTIO_MOSI_OE_MASK (0x40000UL) +#define SPI_DIRECTIO_MOSI_OE_SHIFT (18U) +#define SPI_DIRECTIO_MOSI_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_OE_SHIFT) & SPI_DIRECTIO_MOSI_OE_MASK) +#define SPI_DIRECTIO_MOSI_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_OE_MASK) >> SPI_DIRECTIO_MOSI_OE_SHIFT) + +/* + * SCLK_OE (RW) + * + * Output enable for the SPI SCLK signal + */ +#define SPI_DIRECTIO_SCLK_OE_MASK (0x20000UL) +#define SPI_DIRECTIO_SCLK_OE_SHIFT (17U) +#define SPI_DIRECTIO_SCLK_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_OE_SHIFT) & SPI_DIRECTIO_SCLK_OE_MASK) +#define SPI_DIRECTIO_SCLK_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_OE_MASK) >> SPI_DIRECTIO_SCLK_OE_SHIFT) + +/* + * CS_OE (RW) + * + * Output enable for SPI CS (chip select) signal + */ +#define SPI_DIRECTIO_CS_OE_MASK (0x10000UL) +#define SPI_DIRECTIO_CS_OE_SHIFT (16U) +#define SPI_DIRECTIO_CS_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_OE_SHIFT) & SPI_DIRECTIO_CS_OE_MASK) +#define SPI_DIRECTIO_CS_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_OE_MASK) >> SPI_DIRECTIO_CS_OE_SHIFT) + +/* + * HOLD_O (RW) + * + * Output value for the SPI Flash hold signal + */ +#define SPI_DIRECTIO_HOLD_O_MASK (0x2000U) +#define SPI_DIRECTIO_HOLD_O_SHIFT (13U) +#define SPI_DIRECTIO_HOLD_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_O_SHIFT) & SPI_DIRECTIO_HOLD_O_MASK) +#define SPI_DIRECTIO_HOLD_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_O_MASK) >> SPI_DIRECTIO_HOLD_O_SHIFT) + +/* + * WP_O (RW) + * + * Output value for the SPI Flash write protect signal + */ +#define SPI_DIRECTIO_WP_O_MASK (0x1000U) +#define SPI_DIRECTIO_WP_O_SHIFT (12U) +#define SPI_DIRECTIO_WP_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_O_SHIFT) & SPI_DIRECTIO_WP_O_MASK) +#define SPI_DIRECTIO_WP_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_O_MASK) >> SPI_DIRECTIO_WP_O_SHIFT) + +/* + * MISO_O (RW) + * + * Output value for the SPI MISO signal + */ +#define SPI_DIRECTIO_MISO_O_MASK (0x800U) +#define SPI_DIRECTIO_MISO_O_SHIFT (11U) +#define SPI_DIRECTIO_MISO_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_O_SHIFT) & SPI_DIRECTIO_MISO_O_MASK) +#define SPI_DIRECTIO_MISO_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_O_MASK) >> SPI_DIRECTIO_MISO_O_SHIFT) + +/* + * MOSI_O (RW) + * + * Output value for the SPI MOSI signal + */ +#define SPI_DIRECTIO_MOSI_O_MASK (0x400U) +#define SPI_DIRECTIO_MOSI_O_SHIFT (10U) +#define SPI_DIRECTIO_MOSI_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_O_SHIFT) & SPI_DIRECTIO_MOSI_O_MASK) +#define SPI_DIRECTIO_MOSI_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_O_MASK) >> SPI_DIRECTIO_MOSI_O_SHIFT) + +/* + * SCLK_O (RW) + * + * Output value for the SPI SCLK signal + */ +#define SPI_DIRECTIO_SCLK_O_MASK (0x200U) +#define SPI_DIRECTIO_SCLK_O_SHIFT (9U) +#define SPI_DIRECTIO_SCLK_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_O_SHIFT) & SPI_DIRECTIO_SCLK_O_MASK) +#define SPI_DIRECTIO_SCLK_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_O_MASK) >> SPI_DIRECTIO_SCLK_O_SHIFT) + +/* + * CS_O (RW) + * + * Output value for the SPI CS (chip select) signal + */ +#define SPI_DIRECTIO_CS_O_MASK (0x100U) +#define SPI_DIRECTIO_CS_O_SHIFT (8U) +#define SPI_DIRECTIO_CS_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_O_SHIFT) & SPI_DIRECTIO_CS_O_MASK) +#define SPI_DIRECTIO_CS_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_O_MASK) >> SPI_DIRECTIO_CS_O_SHIFT) + +/* + * HOLD_I (RO) + * + * Status of the SPI Flash hold signal + */ +#define SPI_DIRECTIO_HOLD_I_MASK (0x20U) +#define SPI_DIRECTIO_HOLD_I_SHIFT (5U) +#define SPI_DIRECTIO_HOLD_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_I_MASK) >> SPI_DIRECTIO_HOLD_I_SHIFT) + +/* + * WP_I (RO) + * + * Status of the SPI Flash write protect signal + */ +#define SPI_DIRECTIO_WP_I_MASK (0x10U) +#define SPI_DIRECTIO_WP_I_SHIFT (4U) +#define SPI_DIRECTIO_WP_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_I_MASK) >> SPI_DIRECTIO_WP_I_SHIFT) + +/* + * MISO_I (RO) + * + * Status of the SPI MISO signal + */ +#define SPI_DIRECTIO_MISO_I_MASK (0x8U) +#define SPI_DIRECTIO_MISO_I_SHIFT (3U) +#define SPI_DIRECTIO_MISO_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_I_MASK) >> SPI_DIRECTIO_MISO_I_SHIFT) + +/* + * MOSI_I (RO) + * + * Status of the SPI MOSI signal + */ +#define SPI_DIRECTIO_MOSI_I_MASK (0x4U) +#define SPI_DIRECTIO_MOSI_I_SHIFT (2U) +#define SPI_DIRECTIO_MOSI_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_I_MASK) >> SPI_DIRECTIO_MOSI_I_SHIFT) + +/* + * SCLK_I (RO) + * + * Status of the SPI SCLK signal + */ +#define SPI_DIRECTIO_SCLK_I_MASK (0x2U) +#define SPI_DIRECTIO_SCLK_I_SHIFT (1U) +#define SPI_DIRECTIO_SCLK_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_I_MASK) >> SPI_DIRECTIO_SCLK_I_SHIFT) + +/* + * CS_I (RO) + * + * Status of the SPI CS (chip select) signal + */ +#define SPI_DIRECTIO_CS_I_MASK (0x1U) +#define SPI_DIRECTIO_CS_I_SHIFT (0U) +#define SPI_DIRECTIO_CS_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_I_MASK) >> SPI_DIRECTIO_CS_I_SHIFT) + +/* Bitfield definition for register: TRANSCTRL */ +/* + * SLVDATAONLY (RW) + * + * Data-only mode (slave mode only) + * 0x0: Disable the data-only mode + * 0x1: Enable the data-only mode + * Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + */ +#define SPI_TRANSCTRL_SLVDATAONLY_MASK (0x80000000UL) +#define SPI_TRANSCTRL_SLVDATAONLY_SHIFT (31U) +#define SPI_TRANSCTRL_SLVDATAONLY_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_SLVDATAONLY_SHIFT) & SPI_TRANSCTRL_SLVDATAONLY_MASK) +#define SPI_TRANSCTRL_SLVDATAONLY_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_SLVDATAONLY_MASK) >> SPI_TRANSCTRL_SLVDATAONLY_SHIFT) + +/* + * CMDEN (RW) + * + * SPI command phase enable (Master mode only) + * 0x0: Disable the command phase + * 0x1: Enable the command phase + */ +#define SPI_TRANSCTRL_CMDEN_MASK (0x40000000UL) +#define SPI_TRANSCTRL_CMDEN_SHIFT (30U) +#define SPI_TRANSCTRL_CMDEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_CMDEN_SHIFT) & SPI_TRANSCTRL_CMDEN_MASK) +#define SPI_TRANSCTRL_CMDEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_CMDEN_MASK) >> SPI_TRANSCTRL_CMDEN_SHIFT) + +/* + * ADDREN (RW) + * + * SPI address phase enable (Master mode only) + * 0x0: Disable the address phase + * 0x1: Enable the address phase + */ +#define SPI_TRANSCTRL_ADDREN_MASK (0x20000000UL) +#define SPI_TRANSCTRL_ADDREN_SHIFT (29U) +#define SPI_TRANSCTRL_ADDREN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDREN_SHIFT) & SPI_TRANSCTRL_ADDREN_MASK) +#define SPI_TRANSCTRL_ADDREN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDREN_MASK) >> SPI_TRANSCTRL_ADDREN_SHIFT) + +/* + * ADDRFMT (RW) + * + * SPI address phase format (Master mode only) + * 0x0: Address phase is the regular (single) mode + * 0x1: The format of the address phase is the same as the data phase (DualQuad). + */ +#define SPI_TRANSCTRL_ADDRFMT_MASK (0x10000000UL) +#define SPI_TRANSCTRL_ADDRFMT_SHIFT (28U) +#define SPI_TRANSCTRL_ADDRFMT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDRFMT_SHIFT) & SPI_TRANSCTRL_ADDRFMT_MASK) +#define SPI_TRANSCTRL_ADDRFMT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDRFMT_MASK) >> SPI_TRANSCTRL_ADDRFMT_SHIFT) + +/* + * TRANSMODE (RW) + * + * Transfer mode + * The transfer sequence could be + * 0x0: Write and read at the same time + * 0x1: Write only + * 0x2: Read only + * 0x3: Write, Read + * 0x4: Read, Write + * 0x5: Write, Dummy, Read + * 0x6: Read, Dummy, Write + * 0x7: None Data (must enable CmdEn or AddrEn in master mode) + * 0x8: Dummy, Write + * 0x9: Dummy, Read + * 0xa~0xf: Reserved + */ +#define SPI_TRANSCTRL_TRANSMODE_MASK (0xF000000UL) +#define SPI_TRANSCTRL_TRANSMODE_SHIFT (24U) +#define SPI_TRANSCTRL_TRANSMODE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TRANSMODE_SHIFT) & SPI_TRANSCTRL_TRANSMODE_MASK) +#define SPI_TRANSCTRL_TRANSMODE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TRANSMODE_MASK) >> SPI_TRANSCTRL_TRANSMODE_SHIFT) + +/* + * DUALQUAD (RW) + * + * SPI data phase format + * 0x0: Regular (Single) mode + * 0x1: Dual I/O mode + * 0x2: Quad I/O mode + * 0x3: Reserved + */ +#define SPI_TRANSCTRL_DUALQUAD_MASK (0xC00000UL) +#define SPI_TRANSCTRL_DUALQUAD_SHIFT (22U) +#define SPI_TRANSCTRL_DUALQUAD_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUALQUAD_SHIFT) & SPI_TRANSCTRL_DUALQUAD_MASK) +#define SPI_TRANSCTRL_DUALQUAD_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUALQUAD_MASK) >> SPI_TRANSCTRL_DUALQUAD_SHIFT) + +/* + * TOKENEN (RW) + * + * Token transfer enable (Master mode only) + * Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. + * 0x0: Disable the one-byte special token + * 0x1: Enable the one-byte special token + */ +#define SPI_TRANSCTRL_TOKENEN_MASK (0x200000UL) +#define SPI_TRANSCTRL_TOKENEN_SHIFT (21U) +#define SPI_TRANSCTRL_TOKENEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENEN_SHIFT) & SPI_TRANSCTRL_TOKENEN_MASK) +#define SPI_TRANSCTRL_TOKENEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENEN_MASK) >> SPI_TRANSCTRL_TOKENEN_SHIFT) + +/* + * WRTRANCNT (RW) + * + * Transfer count for write data + * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). + * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. + * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. + * For TransMode 0, WrTranCnt must be equal to RdTranCnt. + */ +#define SPI_TRANSCTRL_WRTRANCNT_MASK (0x1FF000UL) +#define SPI_TRANSCTRL_WRTRANCNT_SHIFT (12U) +#define SPI_TRANSCTRL_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_WRTRANCNT_SHIFT) & SPI_TRANSCTRL_WRTRANCNT_MASK) +#define SPI_TRANSCTRL_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_WRTRANCNT_MASK) >> SPI_TRANSCTRL_WRTRANCNT_SHIFT) + +/* + * TOKENVALUE (RW) + * + * Token value (Master mode only) + * The value of the one-byte special token following the address phase for SPI read transfers. + * 0x0: token value = 0x00 + * 0x1: token value = 0x69 + */ +#define SPI_TRANSCTRL_TOKENVALUE_MASK (0x800U) +#define SPI_TRANSCTRL_TOKENVALUE_SHIFT (11U) +#define SPI_TRANSCTRL_TOKENVALUE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENVALUE_SHIFT) & SPI_TRANSCTRL_TOKENVALUE_MASK) +#define SPI_TRANSCTRL_TOKENVALUE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENVALUE_MASK) >> SPI_TRANSCTRL_TOKENVALUE_SHIFT) + +/* + * DUMMYCNT (RW) + * + * Dummy data count. The actual dummy count is (DummyCnt +1). + * The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) + * The Data pins are put into the high impedance during the dummy data phase. + * DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + */ +#define SPI_TRANSCTRL_DUMMYCNT_MASK (0x600U) +#define SPI_TRANSCTRL_DUMMYCNT_SHIFT (9U) +#define SPI_TRANSCTRL_DUMMYCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUMMYCNT_SHIFT) & SPI_TRANSCTRL_DUMMYCNT_MASK) +#define SPI_TRANSCTRL_DUMMYCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUMMYCNT_MASK) >> SPI_TRANSCTRL_DUMMYCNT_SHIFT) + +/* + * RDTRANCNT (RW) + * + * Transfer count for read data + * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). + * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. + * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. + * For TransMode 0, WrTranCnt must equal RdTranCnt. + */ +#define SPI_TRANSCTRL_RDTRANCNT_MASK (0x1FFU) +#define SPI_TRANSCTRL_RDTRANCNT_SHIFT (0U) +#define SPI_TRANSCTRL_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_RDTRANCNT_SHIFT) & SPI_TRANSCTRL_RDTRANCNT_MASK) +#define SPI_TRANSCTRL_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_RDTRANCNT_MASK) >> SPI_TRANSCTRL_RDTRANCNT_SHIFT) + +/* Bitfield definition for register: CMD */ +/* + * CMD (RW) + * + * SPI Command + */ +#define SPI_CMD_CMD_MASK (0xFFU) +#define SPI_CMD_CMD_SHIFT (0U) +#define SPI_CMD_CMD_SET(x) (((uint32_t)(x) << SPI_CMD_CMD_SHIFT) & SPI_CMD_CMD_MASK) +#define SPI_CMD_CMD_GET(x) (((uint32_t)(x) & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT) + +/* Bitfield definition for register: ADDR */ +/* + * ADDR (RW) + * + * SPI Address + * (Master mode only) + */ +#define SPI_ADDR_ADDR_MASK (0xFFFFFFFFUL) +#define SPI_ADDR_ADDR_SHIFT (0U) +#define SPI_ADDR_ADDR_SET(x) (((uint32_t)(x) << SPI_ADDR_ADDR_SHIFT) & SPI_ADDR_ADDR_MASK) +#define SPI_ADDR_ADDR_GET(x) (((uint32_t)(x) & SPI_ADDR_ADDR_MASK) >> SPI_ADDR_ADDR_SHIFT) + +/* Bitfield definition for register: DATA */ +/* + * DATA (RW) + * + * Data to transmit or the received data + * For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. + * For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. + * The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. + * If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + */ +#define SPI_DATA_DATA_MASK (0xFFFFFFFFUL) +#define SPI_DATA_DATA_SHIFT (0U) +#define SPI_DATA_DATA_SET(x) (((uint32_t)(x) << SPI_DATA_DATA_SHIFT) & SPI_DATA_DATA_MASK) +#define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) + +/* Bitfield definition for register: CTRL */ +/* + * TXTHRES (RW) + * + * Transmit (TX) FIFO Threshold + * The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + */ +#define SPI_CTRL_TXTHRES_MASK (0xFF0000UL) +#define SPI_CTRL_TXTHRES_SHIFT (16U) +#define SPI_CTRL_TXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_TXTHRES_SHIFT) & SPI_CTRL_TXTHRES_MASK) +#define SPI_CTRL_TXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_TXTHRES_MASK) >> SPI_CTRL_TXTHRES_SHIFT) + +/* + * RXTHRES (RW) + * + * Receive (RX) FIFO Threshold + * The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + */ +#define SPI_CTRL_RXTHRES_MASK (0xFF00U) +#define SPI_CTRL_RXTHRES_SHIFT (8U) +#define SPI_CTRL_RXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_RXTHRES_SHIFT) & SPI_CTRL_RXTHRES_MASK) +#define SPI_CTRL_RXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_RXTHRES_MASK) >> SPI_CTRL_RXTHRES_SHIFT) + +/* + * TXDMAEN (RW) + * + * TX DMA enable + */ +#define SPI_CTRL_TXDMAEN_MASK (0x10U) +#define SPI_CTRL_TXDMAEN_SHIFT (4U) +#define SPI_CTRL_TXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_TXDMAEN_SHIFT) & SPI_CTRL_TXDMAEN_MASK) +#define SPI_CTRL_TXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_TXDMAEN_MASK) >> SPI_CTRL_TXDMAEN_SHIFT) + +/* + * RXDMAEN (RW) + * + * RX DMA enable + */ +#define SPI_CTRL_RXDMAEN_MASK (0x8U) +#define SPI_CTRL_RXDMAEN_SHIFT (3U) +#define SPI_CTRL_RXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_RXDMAEN_SHIFT) & SPI_CTRL_RXDMAEN_MASK) +#define SPI_CTRL_RXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_RXDMAEN_MASK) >> SPI_CTRL_RXDMAEN_SHIFT) + +/* + * TXFIFORST (RW) + * + * Transmit FIFO reset + * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + */ +#define SPI_CTRL_TXFIFORST_MASK (0x4U) +#define SPI_CTRL_TXFIFORST_SHIFT (2U) +#define SPI_CTRL_TXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_TXFIFORST_SHIFT) & SPI_CTRL_TXFIFORST_MASK) +#define SPI_CTRL_TXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_TXFIFORST_MASK) >> SPI_CTRL_TXFIFORST_SHIFT) + +/* + * RXFIFORST (RW) + * + * Receive FIFO reset + * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + */ +#define SPI_CTRL_RXFIFORST_MASK (0x2U) +#define SPI_CTRL_RXFIFORST_SHIFT (1U) +#define SPI_CTRL_RXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_RXFIFORST_SHIFT) & SPI_CTRL_RXFIFORST_MASK) +#define SPI_CTRL_RXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_RXFIFORST_MASK) >> SPI_CTRL_RXFIFORST_SHIFT) + +/* + * SPIRST (RW) + * + * SPI reset + * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + */ +#define SPI_CTRL_SPIRST_MASK (0x1U) +#define SPI_CTRL_SPIRST_SHIFT (0U) +#define SPI_CTRL_SPIRST_SET(x) (((uint32_t)(x) << SPI_CTRL_SPIRST_SHIFT) & SPI_CTRL_SPIRST_MASK) +#define SPI_CTRL_SPIRST_GET(x) (((uint32_t)(x) & SPI_CTRL_SPIRST_MASK) >> SPI_CTRL_SPIRST_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * TXNUM_7_6 (RO) + * + * Number of valid entries in the Transmit FIFO + */ +#define SPI_STATUS_TXNUM_7_6_MASK (0x30000000UL) +#define SPI_STATUS_TXNUM_7_6_SHIFT (28U) +#define SPI_STATUS_TXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_7_6_MASK) >> SPI_STATUS_TXNUM_7_6_SHIFT) + +/* + * RXNUM_7_6 (RO) + * + * Number of valid entries in the Receive FIFO + */ +#define SPI_STATUS_RXNUM_7_6_MASK (0x3000000UL) +#define SPI_STATUS_RXNUM_7_6_SHIFT (24U) +#define SPI_STATUS_RXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_7_6_MASK) >> SPI_STATUS_RXNUM_7_6_SHIFT) + +/* + * TXFULL (RO) + * + * Transmit FIFO Full flag + */ +#define SPI_STATUS_TXFULL_MASK (0x800000UL) +#define SPI_STATUS_TXFULL_SHIFT (23U) +#define SPI_STATUS_TXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_TXFULL_MASK) >> SPI_STATUS_TXFULL_SHIFT) + +/* + * TXEMPTY (RO) + * + * Transmit FIFO Empty flag + */ +#define SPI_STATUS_TXEMPTY_MASK (0x400000UL) +#define SPI_STATUS_TXEMPTY_SHIFT (22U) +#define SPI_STATUS_TXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_TXEMPTY_MASK) >> SPI_STATUS_TXEMPTY_SHIFT) + +/* + * TXNUM_5_0 (RO) + * + * Number of valid entries in the Transmit FIFO + */ +#define SPI_STATUS_TXNUM_5_0_MASK (0x3F0000UL) +#define SPI_STATUS_TXNUM_5_0_SHIFT (16U) +#define SPI_STATUS_TXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_5_0_MASK) >> SPI_STATUS_TXNUM_5_0_SHIFT) + +/* + * RXFULL (RO) + * + * Receive FIFO Full flag + */ +#define SPI_STATUS_RXFULL_MASK (0x8000U) +#define SPI_STATUS_RXFULL_SHIFT (15U) +#define SPI_STATUS_RXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_RXFULL_MASK) >> SPI_STATUS_RXFULL_SHIFT) + +/* + * RXEMPTY (RO) + * + * Receive FIFO Empty flag + */ +#define SPI_STATUS_RXEMPTY_MASK (0x4000U) +#define SPI_STATUS_RXEMPTY_SHIFT (14U) +#define SPI_STATUS_RXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_RXEMPTY_MASK) >> SPI_STATUS_RXEMPTY_SHIFT) + +/* + * RXNUM_5_0 (RO) + * + * Number of valid entries in the Receive FIFO + */ +#define SPI_STATUS_RXNUM_5_0_MASK (0x3F00U) +#define SPI_STATUS_RXNUM_5_0_SHIFT (8U) +#define SPI_STATUS_RXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_5_0_MASK) >> SPI_STATUS_RXNUM_5_0_SHIFT) + +/* + * SPIACTIVE (RO) + * + * SPI register programming is in progress. + * In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. + * In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. + * Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. + * Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + */ +#define SPI_STATUS_SPIACTIVE_MASK (0x1U) +#define SPI_STATUS_SPIACTIVE_SHIFT (0U) +#define SPI_STATUS_SPIACTIVE_GET(x) (((uint32_t)(x) & SPI_STATUS_SPIACTIVE_MASK) >> SPI_STATUS_SPIACTIVE_SHIFT) + +/* Bitfield definition for register: INTREN */ +/* + * SLVCMDEN (RW) + * + * Enable the Slave Command Interrupt. + * Control whether interrupts are triggered whenever slave commands are received. + * (Slave mode only) + */ +#define SPI_INTREN_SLVCMDEN_MASK (0x20U) +#define SPI_INTREN_SLVCMDEN_SHIFT (5U) +#define SPI_INTREN_SLVCMDEN_SET(x) (((uint32_t)(x) << SPI_INTREN_SLVCMDEN_SHIFT) & SPI_INTREN_SLVCMDEN_MASK) +#define SPI_INTREN_SLVCMDEN_GET(x) (((uint32_t)(x) & SPI_INTREN_SLVCMDEN_MASK) >> SPI_INTREN_SLVCMDEN_SHIFT) + +/* + * ENDINTEN (RW) + * + * Enable the End of SPI Transfer interrupt. + * Control whether interrupts are triggered when SPI transfers end. + * (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + */ +#define SPI_INTREN_ENDINTEN_MASK (0x10U) +#define SPI_INTREN_ENDINTEN_SHIFT (4U) +#define SPI_INTREN_ENDINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_ENDINTEN_SHIFT) & SPI_INTREN_ENDINTEN_MASK) +#define SPI_INTREN_ENDINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_ENDINTEN_MASK) >> SPI_INTREN_ENDINTEN_SHIFT) + +/* + * TXFIFOINTEN (RW) + * + * Enable the SPI Transmit FIFO Threshold interrupt. + * Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + */ +#define SPI_INTREN_TXFIFOINTEN_MASK (0x8U) +#define SPI_INTREN_TXFIFOINTEN_SHIFT (3U) +#define SPI_INTREN_TXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOINTEN_SHIFT) & SPI_INTREN_TXFIFOINTEN_MASK) +#define SPI_INTREN_TXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOINTEN_MASK) >> SPI_INTREN_TXFIFOINTEN_SHIFT) + +/* + * RXFIFOINTEN (RW) + * + * Enable the SPI Receive FIFO Threshold interrupt. + * Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + */ +#define SPI_INTREN_RXFIFOINTEN_MASK (0x4U) +#define SPI_INTREN_RXFIFOINTEN_SHIFT (2U) +#define SPI_INTREN_RXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOINTEN_SHIFT) & SPI_INTREN_RXFIFOINTEN_MASK) +#define SPI_INTREN_RXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOINTEN_MASK) >> SPI_INTREN_RXFIFOINTEN_SHIFT) + +/* + * TXFIFOURINTEN (RW) + * + * Enable the SPI Transmit FIFO Underrun interrupt. + * Control whether interrupts are triggered when the Transmit FIFO run out of data. + * (Slave mode only) + */ +#define SPI_INTREN_TXFIFOURINTEN_MASK (0x2U) +#define SPI_INTREN_TXFIFOURINTEN_SHIFT (1U) +#define SPI_INTREN_TXFIFOURINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOURINTEN_SHIFT) & SPI_INTREN_TXFIFOURINTEN_MASK) +#define SPI_INTREN_TXFIFOURINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOURINTEN_MASK) >> SPI_INTREN_TXFIFOURINTEN_SHIFT) + +/* + * RXFIFOORINTEN (RW) + * + * Enable the SPI Receive FIFO Overrun interrupt. + * Control whether interrupts are triggered when the Receive FIFO overflows. + * (Slave mode only) + */ +#define SPI_INTREN_RXFIFOORINTEN_MASK (0x1U) +#define SPI_INTREN_RXFIFOORINTEN_SHIFT (0U) +#define SPI_INTREN_RXFIFOORINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOORINTEN_SHIFT) & SPI_INTREN_RXFIFOORINTEN_MASK) +#define SPI_INTREN_RXFIFOORINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOORINTEN_MASK) >> SPI_INTREN_RXFIFOORINTEN_SHIFT) + +/* Bitfield definition for register: INTRST */ +/* + * SLVCMDINT (W1C) + * + * Slave Command Interrupt. + * This bit is set when Slave Command interrupts occur. + * (Slave mode only) + */ +#define SPI_INTRST_SLVCMDINT_MASK (0x20U) +#define SPI_INTRST_SLVCMDINT_SHIFT (5U) +#define SPI_INTRST_SLVCMDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_SLVCMDINT_SHIFT) & SPI_INTRST_SLVCMDINT_MASK) +#define SPI_INTRST_SLVCMDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_SLVCMDINT_MASK) >> SPI_INTRST_SLVCMDINT_SHIFT) + +/* + * ENDINT (W1C) + * + * End of SPI Transfer interrupt. + * This bit is set when End of SPI Transfer interrupts occur. + */ +#define SPI_INTRST_ENDINT_MASK (0x10U) +#define SPI_INTRST_ENDINT_SHIFT (4U) +#define SPI_INTRST_ENDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_ENDINT_SHIFT) & SPI_INTRST_ENDINT_MASK) +#define SPI_INTRST_ENDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_ENDINT_MASK) >> SPI_INTRST_ENDINT_SHIFT) + +/* + * TXFIFOINT (W1C) + * + * TX FIFO Threshold interrupt. + * This bit is set when TX FIFO Threshold interrupts occur. + */ +#define SPI_INTRST_TXFIFOINT_MASK (0x8U) +#define SPI_INTRST_TXFIFOINT_SHIFT (3U) +#define SPI_INTRST_TXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOINT_SHIFT) & SPI_INTRST_TXFIFOINT_MASK) +#define SPI_INTRST_TXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOINT_MASK) >> SPI_INTRST_TXFIFOINT_SHIFT) + +/* + * RXFIFOINT (W1C) + * + * RX FIFO Threshold interrupt. + * This bit is set when RX FIFO Threshold interrupts occur. + */ +#define SPI_INTRST_RXFIFOINT_MASK (0x4U) +#define SPI_INTRST_RXFIFOINT_SHIFT (2U) +#define SPI_INTRST_RXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOINT_SHIFT) & SPI_INTRST_RXFIFOINT_MASK) +#define SPI_INTRST_RXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOINT_MASK) >> SPI_INTRST_RXFIFOINT_SHIFT) + +/* + * TXFIFOURINT (W1C) + * + * TX FIFO Underrun interrupt. + * This bit is set when TX FIFO Underrun interrupts occur. + * (Slave mode only) + */ +#define SPI_INTRST_TXFIFOURINT_MASK (0x2U) +#define SPI_INTRST_TXFIFOURINT_SHIFT (1U) +#define SPI_INTRST_TXFIFOURINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOURINT_SHIFT) & SPI_INTRST_TXFIFOURINT_MASK) +#define SPI_INTRST_TXFIFOURINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOURINT_MASK) >> SPI_INTRST_TXFIFOURINT_SHIFT) + +/* + * RXFIFOORINT (W1C) + * + * RX FIFO Overrun interrupt. + * This bit is set when RX FIFO Overrun interrupts occur. + * (Slave mode only) + */ +#define SPI_INTRST_RXFIFOORINT_MASK (0x1U) +#define SPI_INTRST_RXFIFOORINT_SHIFT (0U) +#define SPI_INTRST_RXFIFOORINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOORINT_SHIFT) & SPI_INTRST_RXFIFOORINT_MASK) +#define SPI_INTRST_RXFIFOORINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOORINT_MASK) >> SPI_INTRST_RXFIFOORINT_SHIFT) + +/* Bitfield definition for register: TIMING */ +/* + * CS2SCLK (RW) + * + * The minimum time between the edges of SPI CS and the edges of SCLK. + * SCLK_period * (CS2SCLK + 1) / 2 + */ +#define SPI_TIMING_CS2SCLK_MASK (0x3000U) +#define SPI_TIMING_CS2SCLK_SHIFT (12U) +#define SPI_TIMING_CS2SCLK_SET(x) (((uint32_t)(x) << SPI_TIMING_CS2SCLK_SHIFT) & SPI_TIMING_CS2SCLK_MASK) +#define SPI_TIMING_CS2SCLK_GET(x) (((uint32_t)(x) & SPI_TIMING_CS2SCLK_MASK) >> SPI_TIMING_CS2SCLK_SHIFT) + +/* + * CSHT (RW) + * + * The minimum time that SPI CS should stay HIGH. + * SCLK_period * (CSHT + 1) / 2 + */ +#define SPI_TIMING_CSHT_MASK (0xF00U) +#define SPI_TIMING_CSHT_SHIFT (8U) +#define SPI_TIMING_CSHT_SET(x) (((uint32_t)(x) << SPI_TIMING_CSHT_SHIFT) & SPI_TIMING_CSHT_MASK) +#define SPI_TIMING_CSHT_GET(x) (((uint32_t)(x) & SPI_TIMING_CSHT_MASK) >> SPI_TIMING_CSHT_SHIFT) + +/* + * SCLK_DIV (RW) + * + * The clock frequency ratio between the clock source and SPI interface SCLK. + * SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) + * The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + */ +#define SPI_TIMING_SCLK_DIV_MASK (0xFFU) +#define SPI_TIMING_SCLK_DIV_SHIFT (0U) +#define SPI_TIMING_SCLK_DIV_SET(x) (((uint32_t)(x) << SPI_TIMING_SCLK_DIV_SHIFT) & SPI_TIMING_SCLK_DIV_MASK) +#define SPI_TIMING_SCLK_DIV_GET(x) (((uint32_t)(x) & SPI_TIMING_SCLK_DIV_MASK) >> SPI_TIMING_SCLK_DIV_SHIFT) + +/* Bitfield definition for register: SLVST */ +/* + * UNDERRUN (R1C) + * + * Data underrun occurs in the last transaction + */ +#define SPI_SLVST_UNDERRUN_MASK (0x40000UL) +#define SPI_SLVST_UNDERRUN_SHIFT (18U) +#define SPI_SLVST_UNDERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_UNDERRUN_MASK) >> SPI_SLVST_UNDERRUN_SHIFT) + +/* + * OVERRUN (RW) + * + * Data overrun occurs in the last transaction + */ +#define SPI_SLVST_OVERRUN_MASK (0x20000UL) +#define SPI_SLVST_OVERRUN_SHIFT (17U) +#define SPI_SLVST_OVERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_OVERRUN_SHIFT) & SPI_SLVST_OVERRUN_MASK) +#define SPI_SLVST_OVERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_OVERRUN_MASK) >> SPI_SLVST_OVERRUN_SHIFT) + +/* + * READY (RW) + * + * Set this bit to indicate that the ATCSPI200 is ready for data transaction. + * When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + */ +#define SPI_SLVST_READY_MASK (0x10000UL) +#define SPI_SLVST_READY_SHIFT (16U) +#define SPI_SLVST_READY_SET(x) (((uint32_t)(x) << SPI_SLVST_READY_SHIFT) & SPI_SLVST_READY_MASK) +#define SPI_SLVST_READY_GET(x) (((uint32_t)(x) & SPI_SLVST_READY_MASK) >> SPI_SLVST_READY_SHIFT) + +/* + * USR_STATUS (RW) + * + * User defined status flags + */ +#define SPI_SLVST_USR_STATUS_MASK (0xFFFFU) +#define SPI_SLVST_USR_STATUS_SHIFT (0U) +#define SPI_SLVST_USR_STATUS_SET(x) (((uint32_t)(x) << SPI_SLVST_USR_STATUS_SHIFT) & SPI_SLVST_USR_STATUS_MASK) +#define SPI_SLVST_USR_STATUS_GET(x) (((uint32_t)(x) & SPI_SLVST_USR_STATUS_MASK) >> SPI_SLVST_USR_STATUS_SHIFT) + +/* Bitfield definition for register: SLVDATACNT */ +/* + * WCNT (RO) + * + * Slave transmitted data count + */ +#define SPI_SLVDATACNT_WCNT_MASK (0x3FF0000UL) +#define SPI_SLVDATACNT_WCNT_SHIFT (16U) +#define SPI_SLVDATACNT_WCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_WCNT_MASK) >> SPI_SLVDATACNT_WCNT_SHIFT) + +/* + * RCNT (RO) + * + * Slave received data count + */ +#define SPI_SLVDATACNT_RCNT_MASK (0x3FFU) +#define SPI_SLVDATACNT_RCNT_SHIFT (0U) +#define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) + +/* Bitfield definition for register: CONFIG */ +/* + * SLAVE (RO) + * + * Support for SPI Slave mode + */ +#define SPI_CONFIG_SLAVE_MASK (0x4000U) +#define SPI_CONFIG_SLAVE_SHIFT (14U) +#define SPI_CONFIG_SLAVE_GET(x) (((uint32_t)(x) & SPI_CONFIG_SLAVE_MASK) >> SPI_CONFIG_SLAVE_SHIFT) + +/* + * DIRECTIO (RO) + * + * Support for Direct SPI IO + */ +#define SPI_CONFIG_DIRECTIO_MASK (0x800U) +#define SPI_CONFIG_DIRECTIO_SHIFT (11U) +#define SPI_CONFIG_DIRECTIO_GET(x) (((uint32_t)(x) & SPI_CONFIG_DIRECTIO_MASK) >> SPI_CONFIG_DIRECTIO_SHIFT) + +/* + * QUADSPI (RO) + * + * Support for Quad I/O SPI + */ +#define SPI_CONFIG_QUADSPI_MASK (0x200U) +#define SPI_CONFIG_QUADSPI_SHIFT (9U) +#define SPI_CONFIG_QUADSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_QUADSPI_MASK) >> SPI_CONFIG_QUADSPI_SHIFT) + +/* + * DUALSPI (RO) + * + * Support for Dual I/O SPI + */ +#define SPI_CONFIG_DUALSPI_MASK (0x100U) +#define SPI_CONFIG_DUALSPI_SHIFT (8U) +#define SPI_CONFIG_DUALSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_DUALSPI_MASK) >> SPI_CONFIG_DUALSPI_SHIFT) + +/* + * TXFIFOSIZE (RO) + * + * Depth of TX FIFO + * 0x0: 2 words + * 0x1: 4 words + * 0x2: 8 words + * 0x3: 16 words + * 0x4: 32 words + * 0x5: 64 words + * 0x6: 128 words + */ +#define SPI_CONFIG_TXFIFOSIZE_MASK (0xF0U) +#define SPI_CONFIG_TXFIFOSIZE_SHIFT (4U) +#define SPI_CONFIG_TXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_TXFIFOSIZE_MASK) >> SPI_CONFIG_TXFIFOSIZE_SHIFT) + +/* + * RXFIFOSIZE (RO) + * + * Depth of RX FIFO + * 0x0: 2 words + * 0x1: 4 words + * 0x2: 8 words + * 0x3: 16 words + * 0x4: 32 words + * 0x5: 64 words + * 0x6: 128 words + */ +#define SPI_CONFIG_RXFIFOSIZE_MASK (0xFU) +#define SPI_CONFIG_RXFIFOSIZE_SHIFT (0U) +#define SPI_CONFIG_RXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_RXFIFOSIZE_MASK) >> SPI_CONFIG_RXFIFOSIZE_SHIFT) + + + + +#endif /* HPM_SPI_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h new file mode 100644 index 0000000000..08eef5ce87 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SYNT_H +#define HPM_SYNT_H + +typedef struct { + __RW uint32_t GCR; /* 0x0: Global control register */ + __RW uint32_t RLD; /* 0x4: Counter reload register */ + __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ + __R uint32_t CNT; /* 0xC: Counter */ + __R uint8_t RESERVED1[16]; /* 0x10 - 0x1F: Reserved */ + __RW uint32_t CMP[4]; /* 0x20 - 0x2C: Comparator */ +} SYNT_Type; + + +/* Bitfield definition for register: GCR */ +/* + * CRST (RW) + * + * 1- Reset counter + */ +#define SYNT_GCR_CRST_MASK (0x2U) +#define SYNT_GCR_CRST_SHIFT (1U) +#define SYNT_GCR_CRST_SET(x) (((uint32_t)(x) << SYNT_GCR_CRST_SHIFT) & SYNT_GCR_CRST_MASK) +#define SYNT_GCR_CRST_GET(x) (((uint32_t)(x) & SYNT_GCR_CRST_MASK) >> SYNT_GCR_CRST_SHIFT) + +/* + * CEN (RW) + * + * 1- Enable counter + */ +#define SYNT_GCR_CEN_MASK (0x1U) +#define SYNT_GCR_CEN_SHIFT (0U) +#define SYNT_GCR_CEN_SET(x) (((uint32_t)(x) << SYNT_GCR_CEN_SHIFT) & SYNT_GCR_CEN_MASK) +#define SYNT_GCR_CEN_GET(x) (((uint32_t)(x) & SYNT_GCR_CEN_MASK) >> SYNT_GCR_CEN_SHIFT) + +/* Bitfield definition for register: RLD */ +/* + * RLD (RW) + * + * counter reload value + */ +#define SYNT_RLD_RLD_MASK (0xFFFFFFFFUL) +#define SYNT_RLD_RLD_SHIFT (0U) +#define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK) +#define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT) + +/* Bitfield definition for register: CNT */ +/* + * CNT (RO) + * + * counter + */ +#define SYNT_CNT_CNT_MASK (0xFFFFFFFFUL) +#define SYNT_CNT_CNT_SHIFT (0U) +#define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT) + +/* Bitfield definition for register array: CMP */ +/* + * CMP (RW) + * + * comparator value, the output will assert when counter count to this value + */ +#define SYNT_CMP_CMP_MASK (0xFFFFFFFFUL) +#define SYNT_CMP_CMP_SHIFT (0U) +#define SYNT_CMP_CMP_SET(x) (((uint32_t)(x) << SYNT_CMP_CMP_SHIFT) & SYNT_CMP_CMP_MASK) +#define SYNT_CMP_CMP_GET(x) (((uint32_t)(x) & SYNT_CMP_CMP_MASK) >> SYNT_CMP_CMP_SHIFT) + + + +/* CMP register group index macro definition */ +#define SYNT_CMP_0 (0UL) +#define SYNT_CMP_1 (1UL) +#define SYNT_CMP_2 (2UL) +#define SYNT_CMP_3 (3UL) + + +#endif /* HPM_SYNT_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tamp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tamp_regs.h new file mode 100644 index 0000000000..38204bbaf4 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tamp_regs.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TAMP_H +#define HPM_TAMP_H + +typedef struct { + struct { + __RW uint32_t CONTROL; /* 0x0: Tamper n control */ + __RW uint32_t POLY; /* 0x4: Tamper n Polynomial of LFSR */ + __W uint32_t LFSR; /* 0x8: Tamper n LFSR shift register */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + } TAMP[6]; + __R uint8_t RESERVED0[32]; /* 0x60 - 0x7F: Reserved */ + __RW uint32_t TAMP_FLAG; /* 0x80: Tamper flag */ + __RW uint32_t IRQ_EN; /* 0x84: Tamper interrupt enable */ +} TAMP_Type; + + +/* Bitfield definition for register of struct array TAMP: CONTROL */ +/* + * LOCK (RW) + * + * lock tamper setting + * 0: tamper setting can be changed + * 1: tamper setting will last to next battery domain power cycle + */ +#define TAMP_TAMP_CONTROL_LOCK_MASK (0x80000000UL) +#define TAMP_TAMP_CONTROL_LOCK_SHIFT (31U) +#define TAMP_TAMP_CONTROL_LOCK_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_LOCK_SHIFT) & TAMP_TAMP_CONTROL_LOCK_MASK) +#define TAMP_TAMP_CONTROL_LOCK_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_LOCK_MASK) >> TAMP_TAMP_CONTROL_LOCK_SHIFT) + +/* + * BYPASS (RW) + * + * bypass tamper violation filter + * 0: filter applied + * 1: filter not used + */ +#define TAMP_TAMP_CONTROL_BYPASS_MASK (0x100000UL) +#define TAMP_TAMP_CONTROL_BYPASS_SHIFT (20U) +#define TAMP_TAMP_CONTROL_BYPASS_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_BYPASS_SHIFT) & TAMP_TAMP_CONTROL_BYPASS_MASK) +#define TAMP_TAMP_CONTROL_BYPASS_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_BYPASS_MASK) >> TAMP_TAMP_CONTROL_BYPASS_SHIFT) + +/* + * FILTER (RW) + * + * filter length + * 0: 1 cycle + * 1: 2 cycle + * 15: 65526 cycle + */ +#define TAMP_TAMP_CONTROL_FILTER_MASK (0xF0000UL) +#define TAMP_TAMP_CONTROL_FILTER_SHIFT (16U) +#define TAMP_TAMP_CONTROL_FILTER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_FILTER_SHIFT) & TAMP_TAMP_CONTROL_FILTER_MASK) +#define TAMP_TAMP_CONTROL_FILTER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_FILTER_MASK) >> TAMP_TAMP_CONTROL_FILTER_SHIFT) + +/* + * VALUE (RW) + * + * pin value for passive tamper + */ +#define TAMP_TAMP_CONTROL_VALUE_MASK (0x300U) +#define TAMP_TAMP_CONTROL_VALUE_SHIFT (8U) +#define TAMP_TAMP_CONTROL_VALUE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_VALUE_SHIFT) & TAMP_TAMP_CONTROL_VALUE_MASK) +#define TAMP_TAMP_CONTROL_VALUE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_VALUE_MASK) >> TAMP_TAMP_CONTROL_VALUE_SHIFT) + +/* + * SPEED (RW) + * + * tamper speed selection, (2^SPEED) changes per second + * 0: 1 shift per second + * 1: 2 shifts per second + * . . . + * 15: 32768 shifts per second + */ +#define TAMP_TAMP_CONTROL_SPEED_MASK (0xF0U) +#define TAMP_TAMP_CONTROL_SPEED_SHIFT (4U) +#define TAMP_TAMP_CONTROL_SPEED_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_SPEED_SHIFT) & TAMP_TAMP_CONTROL_SPEED_MASK) +#define TAMP_TAMP_CONTROL_SPEED_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_SPEED_MASK) >> TAMP_TAMP_CONTROL_SPEED_SHIFT) + +/* + * RECOVER (RW) + * + * tamper will recover itself if tamper LFSR goes wrong + * 0: tamper will not recover + * 1: tamper will recover + */ +#define TAMP_TAMP_CONTROL_RECOVER_MASK (0x4U) +#define TAMP_TAMP_CONTROL_RECOVER_SHIFT (2U) +#define TAMP_TAMP_CONTROL_RECOVER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_RECOVER_SHIFT) & TAMP_TAMP_CONTROL_RECOVER_MASK) +#define TAMP_TAMP_CONTROL_RECOVER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_RECOVER_MASK) >> TAMP_TAMP_CONTROL_RECOVER_SHIFT) + +/* + * ACTIVE (RW) + * + * select active or passive tamper + * 0: passive tamper + * 1: active tamper + */ +#define TAMP_TAMP_CONTROL_ACTIVE_MASK (0x2U) +#define TAMP_TAMP_CONTROL_ACTIVE_SHIFT (1U) +#define TAMP_TAMP_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ACTIVE_SHIFT) & TAMP_TAMP_CONTROL_ACTIVE_MASK) +#define TAMP_TAMP_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ACTIVE_MASK) >> TAMP_TAMP_CONTROL_ACTIVE_SHIFT) + +/* + * ENABLE (RW) + * + * enable tamper + * 0: tamper disableed + * 1: tamper enabled + */ +#define TAMP_TAMP_CONTROL_ENABLE_MASK (0x1U) +#define TAMP_TAMP_CONTROL_ENABLE_SHIFT (0U) +#define TAMP_TAMP_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ENABLE_SHIFT) & TAMP_TAMP_CONTROL_ENABLE_MASK) +#define TAMP_TAMP_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ENABLE_MASK) >> TAMP_TAMP_CONTROL_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array TAMP: POLY */ +/* + * POLY (RW) + * + * tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + */ +#define TAMP_TAMP_POLY_POLY_MASK (0xFFFFFFFFUL) +#define TAMP_TAMP_POLY_POLY_SHIFT (0U) +#define TAMP_TAMP_POLY_POLY_SET(x) (((uint32_t)(x) << TAMP_TAMP_POLY_POLY_SHIFT) & TAMP_TAMP_POLY_POLY_MASK) +#define TAMP_TAMP_POLY_POLY_GET(x) (((uint32_t)(x) & TAMP_TAMP_POLY_POLY_MASK) >> TAMP_TAMP_POLY_POLY_SHIFT) + +/* Bitfield definition for register of struct array TAMP: LFSR */ +/* + * LFSR (WO) + * + * LFSR for active tamper, write only register, always read 0 + */ +#define TAMP_TAMP_LFSR_LFSR_MASK (0xFFFFFFFFUL) +#define TAMP_TAMP_LFSR_LFSR_SHIFT (0U) +#define TAMP_TAMP_LFSR_LFSR_SET(x) (((uint32_t)(x) << TAMP_TAMP_LFSR_LFSR_SHIFT) & TAMP_TAMP_LFSR_LFSR_MASK) +#define TAMP_TAMP_LFSR_LFSR_GET(x) (((uint32_t)(x) & TAMP_TAMP_LFSR_LFSR_MASK) >> TAMP_TAMP_LFSR_LFSR_SHIFT) + +/* Bitfield definition for register: TAMP_FLAG */ +/* + * FLAG (RW) + * + * tamper flag, each bit represents one tamper pin, write 1 to clear the flag + * Note, clear can only be cleared when tamper disapeared + */ +#define TAMP_TAMP_FLAG_FLAG_MASK (0xFFFU) +#define TAMP_TAMP_FLAG_FLAG_SHIFT (0U) +#define TAMP_TAMP_FLAG_FLAG_SET(x) (((uint32_t)(x) << TAMP_TAMP_FLAG_FLAG_SHIFT) & TAMP_TAMP_FLAG_FLAG_MASK) +#define TAMP_TAMP_FLAG_FLAG_GET(x) (((uint32_t)(x) & TAMP_TAMP_FLAG_FLAG_MASK) >> TAMP_TAMP_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: IRQ_EN */ +/* + * LOCK (RW) + * + * lock bit for IRQ enable + * 0: enable bits can be changed + * 1: enable bits hold until next battery domain power cycle + */ +#define TAMP_IRQ_EN_LOCK_MASK (0x80000000UL) +#define TAMP_IRQ_EN_LOCK_SHIFT (31U) +#define TAMP_IRQ_EN_LOCK_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_LOCK_SHIFT) & TAMP_IRQ_EN_LOCK_MASK) +#define TAMP_IRQ_EN_LOCK_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_LOCK_MASK) >> TAMP_IRQ_EN_LOCK_SHIFT) + +/* + * IRQ_EN (RW) + * + * interrupt enable, each bit represents one tamper pin + * 0: interrupt disabled + * 1: interrupt enabled + */ +#define TAMP_IRQ_EN_IRQ_EN_MASK (0xFFFU) +#define TAMP_IRQ_EN_IRQ_EN_SHIFT (0U) +#define TAMP_IRQ_EN_IRQ_EN_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_IRQ_EN_SHIFT) & TAMP_IRQ_EN_IRQ_EN_MASK) +#define TAMP_IRQ_EN_IRQ_EN_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_IRQ_EN_MASK) >> TAMP_IRQ_EN_IRQ_EN_SHIFT) + + + +/* TAMP register group index macro definition */ +#define TAMP_TAMP_TAMP0 (0UL) +#define TAMP_TAMP_TAMP1 (1UL) +#define TAMP_TAMP_TAMP2 (2UL) +#define TAMP_TAMP_TAMP3 (3UL) +#define TAMP_TAMP_TAMP4 (4UL) +#define TAMP_TAMP_TAMP5 (5UL) + + +#endif /* HPM_TAMP_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tsns_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tsns_regs.h new file mode 100644 index 0000000000..d92ee0dc19 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_tsns_regs.h @@ -0,0 +1,389 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TSNS_H +#define HPM_TSNS_H + +typedef struct { + __R uint32_t T; /* 0x0: */ + __R uint32_t TMAX; /* 0x4: */ + __R uint32_t TMIN; /* 0x8: */ + __R uint32_t AGE; /* 0xC: */ + __RW uint32_t STATUS; /* 0x10: */ + __RW uint32_t CONFIG; /* 0x14: */ + __RW uint32_t VALIDITY; /* 0x18: */ + __RW uint32_t FLAG; /* 0x1C: */ + __RW uint32_t UPPER_LIM_IRQ; /* 0x20: */ + __RW uint32_t LOWER_LIM_IRQ; /* 0x24: */ + __RW uint32_t UPPER_LIM_RST; /* 0x28: */ + __RW uint32_t LOWER_LIM_RST; /* 0x2C: */ + __RW uint32_t ASYNC; /* 0x30: */ + __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ + __RW uint32_t ADVAN; /* 0x38: */ +} TSNS_Type; + + +/* Bitfield definition for register: T */ +/* + * T (RO) + * + * Signed number of temperature in 256 x celsius degree + */ +#define TSNS_T_T_MASK (0xFFFFFFFFUL) +#define TSNS_T_T_SHIFT (0U) +#define TSNS_T_T_GET(x) (((uint32_t)(x) & TSNS_T_T_MASK) >> TSNS_T_T_SHIFT) + +/* Bitfield definition for register: TMAX */ +/* + * T (RO) + * + * maximum temperature ever found + */ +#define TSNS_TMAX_T_MASK (0xFFFFFFFFUL) +#define TSNS_TMAX_T_SHIFT (0U) +#define TSNS_TMAX_T_GET(x) (((uint32_t)(x) & TSNS_TMAX_T_MASK) >> TSNS_TMAX_T_SHIFT) + +/* Bitfield definition for register: TMIN */ +/* + * T (RO) + * + * minimum temperature ever found + */ +#define TSNS_TMIN_T_MASK (0xFFFFFFFFUL) +#define TSNS_TMIN_T_SHIFT (0U) +#define TSNS_TMIN_T_GET(x) (((uint32_t)(x) & TSNS_TMIN_T_MASK) >> TSNS_TMIN_T_SHIFT) + +/* Bitfield definition for register: AGE */ +/* + * AGE (RO) + * + * age of T register in 24MHz clock cycles + */ +#define TSNS_AGE_AGE_MASK (0xFFFFFFFFUL) +#define TSNS_AGE_AGE_SHIFT (0U) +#define TSNS_AGE_AGE_GET(x) (((uint32_t)(x) & TSNS_AGE_AGE_MASK) >> TSNS_AGE_AGE_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * VALID (RO) + * + * indicate value in T is valid or not + * 0: not valid + * 1:valid + */ +#define TSNS_STATUS_VALID_MASK (0x80000000UL) +#define TSNS_STATUS_VALID_SHIFT (31U) +#define TSNS_STATUS_VALID_GET(x) (((uint32_t)(x) & TSNS_STATUS_VALID_MASK) >> TSNS_STATUS_VALID_SHIFT) + +/* + * TRIGGER (W1C) + * + * Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode + */ +#define TSNS_STATUS_TRIGGER_MASK (0x1U) +#define TSNS_STATUS_TRIGGER_SHIFT (0U) +#define TSNS_STATUS_TRIGGER_SET(x) (((uint32_t)(x) << TSNS_STATUS_TRIGGER_SHIFT) & TSNS_STATUS_TRIGGER_MASK) +#define TSNS_STATUS_TRIGGER_GET(x) (((uint32_t)(x) & TSNS_STATUS_TRIGGER_MASK) >> TSNS_STATUS_TRIGGER_SHIFT) + +/* Bitfield definition for register: CONFIG */ +/* + * IRQ_EN (RW) + * + * Enable interrupt + */ +#define TSNS_CONFIG_IRQ_EN_MASK (0x80000000UL) +#define TSNS_CONFIG_IRQ_EN_SHIFT (31U) +#define TSNS_CONFIG_IRQ_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_IRQ_EN_SHIFT) & TSNS_CONFIG_IRQ_EN_MASK) +#define TSNS_CONFIG_IRQ_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_IRQ_EN_MASK) >> TSNS_CONFIG_IRQ_EN_SHIFT) + +/* + * RST_EN (RW) + * + * Enable reset + */ +#define TSNS_CONFIG_RST_EN_MASK (0x40000000UL) +#define TSNS_CONFIG_RST_EN_SHIFT (30U) +#define TSNS_CONFIG_RST_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_RST_EN_SHIFT) & TSNS_CONFIG_RST_EN_MASK) +#define TSNS_CONFIG_RST_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_RST_EN_MASK) >> TSNS_CONFIG_RST_EN_SHIFT) + +/* + * COMPARE_MIN_EN (RW) + * + * Enable compare for minimum temperature + */ +#define TSNS_CONFIG_COMPARE_MIN_EN_MASK (0x2000000UL) +#define TSNS_CONFIG_COMPARE_MIN_EN_SHIFT (25U) +#define TSNS_CONFIG_COMPARE_MIN_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) +#define TSNS_CONFIG_COMPARE_MIN_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) >> TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) + +/* + * COMPARE_MAX_EN (RW) + * + * Enable compare for maximum temperature + */ +#define TSNS_CONFIG_COMPARE_MAX_EN_MASK (0x1000000UL) +#define TSNS_CONFIG_COMPARE_MAX_EN_SHIFT (24U) +#define TSNS_CONFIG_COMPARE_MAX_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) +#define TSNS_CONFIG_COMPARE_MAX_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) >> TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) + +/* + * SPEED (RW) + * + * cycles of a progressive step in 24M clock, valide from 24-255, default 63 + * 24: 24 cycle for a step + * 25: 25 cycle for a step + * 26: 26 cycle for a step + * ... + * 255: 255 cycle for a step + */ +#define TSNS_CONFIG_SPEED_MASK (0xFF0000UL) +#define TSNS_CONFIG_SPEED_SHIFT (16U) +#define TSNS_CONFIG_SPEED_SET(x) (((uint32_t)(x) << TSNS_CONFIG_SPEED_SHIFT) & TSNS_CONFIG_SPEED_MASK) +#define TSNS_CONFIG_SPEED_GET(x) (((uint32_t)(x) & TSNS_CONFIG_SPEED_MASK) >> TSNS_CONFIG_SPEED_SHIFT) + +/* + * AVERAGE (RW) + * + * Average time, defaul tin 2 + * 0: measure and return + * 1: twice and average + * 2: 4 times and average(default) + * . . . + * 7: 128 times and average + */ +#define TSNS_CONFIG_AVERAGE_MASK (0x700U) +#define TSNS_CONFIG_AVERAGE_SHIFT (8U) +#define TSNS_CONFIG_AVERAGE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_AVERAGE_SHIFT) & TSNS_CONFIG_AVERAGE_MASK) +#define TSNS_CONFIG_AVERAGE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_AVERAGE_MASK) >> TSNS_CONFIG_AVERAGE_SHIFT) + +/* + * CONTINUOUS (RW) + * + * continuous mode that keep sampling temperature peridically + * 0: trigger mode + * 1: continuous mode + */ +#define TSNS_CONFIG_CONTINUOUS_MASK (0x10U) +#define TSNS_CONFIG_CONTINUOUS_SHIFT (4U) +#define TSNS_CONFIG_CONTINUOUS_SET(x) (((uint32_t)(x) << TSNS_CONFIG_CONTINUOUS_SHIFT) & TSNS_CONFIG_CONTINUOUS_MASK) +#define TSNS_CONFIG_CONTINUOUS_GET(x) (((uint32_t)(x) & TSNS_CONFIG_CONTINUOUS_MASK) >> TSNS_CONFIG_CONTINUOUS_SHIFT) + +/* + * ASYNC (RW) + * + * Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value + * 0: active mode + * 1: Async mode + */ +#define TSNS_CONFIG_ASYNC_MASK (0x2U) +#define TSNS_CONFIG_ASYNC_SHIFT (1U) +#define TSNS_CONFIG_ASYNC_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ASYNC_SHIFT) & TSNS_CONFIG_ASYNC_MASK) +#define TSNS_CONFIG_ASYNC_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ASYNC_MASK) >> TSNS_CONFIG_ASYNC_SHIFT) + +/* + * ENABLE (RW) + * + * Enable temperature + * 0: disable, temperature sensor is shut down + * 1: enable. Temperature sensor enabled + */ +#define TSNS_CONFIG_ENABLE_MASK (0x1U) +#define TSNS_CONFIG_ENABLE_SHIFT (0U) +#define TSNS_CONFIG_ENABLE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ENABLE_SHIFT) & TSNS_CONFIG_ENABLE_MASK) +#define TSNS_CONFIG_ENABLE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ENABLE_MASK) >> TSNS_CONFIG_ENABLE_SHIFT) + +/* Bitfield definition for register: VALIDITY */ +/* + * VALIDITY (RW) + * + * time for temperature values to expire in 24M clock cycles + */ +#define TSNS_VALIDITY_VALIDITY_MASK (0xFFFFFFFFUL) +#define TSNS_VALIDITY_VALIDITY_SHIFT (0U) +#define TSNS_VALIDITY_VALIDITY_SET(x) (((uint32_t)(x) << TSNS_VALIDITY_VALIDITY_SHIFT) & TSNS_VALIDITY_VALIDITY_MASK) +#define TSNS_VALIDITY_VALIDITY_GET(x) (((uint32_t)(x) & TSNS_VALIDITY_VALIDITY_MASK) >> TSNS_VALIDITY_VALIDITY_SHIFT) + +/* Bitfield definition for register: FLAG */ +/* + * RECORD_MIN_CLR (RW) + * + * Clear minimum recorder of temerature, write 1 to clear + */ +#define TSNS_FLAG_RECORD_MIN_CLR_MASK (0x200000UL) +#define TSNS_FLAG_RECORD_MIN_CLR_SHIFT (21U) +#define TSNS_FLAG_RECORD_MIN_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MIN_CLR_SHIFT) & TSNS_FLAG_RECORD_MIN_CLR_MASK) +#define TSNS_FLAG_RECORD_MIN_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MIN_CLR_MASK) >> TSNS_FLAG_RECORD_MIN_CLR_SHIFT) + +/* + * RECORD_MAX_CLR (RW) + * + * Clear maximum recorder of temerature, write 1 to clear + */ +#define TSNS_FLAG_RECORD_MAX_CLR_MASK (0x100000UL) +#define TSNS_FLAG_RECORD_MAX_CLR_SHIFT (20U) +#define TSNS_FLAG_RECORD_MAX_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MAX_CLR_SHIFT) & TSNS_FLAG_RECORD_MAX_CLR_MASK) +#define TSNS_FLAG_RECORD_MAX_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MAX_CLR_MASK) >> TSNS_FLAG_RECORD_MAX_CLR_SHIFT) + +/* + * UNDER_TEMP (RW) + * + * Clear under temperature status, write 1 to clear + */ +#define TSNS_FLAG_UNDER_TEMP_MASK (0x20000UL) +#define TSNS_FLAG_UNDER_TEMP_SHIFT (17U) +#define TSNS_FLAG_UNDER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_UNDER_TEMP_SHIFT) & TSNS_FLAG_UNDER_TEMP_MASK) +#define TSNS_FLAG_UNDER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_UNDER_TEMP_MASK) >> TSNS_FLAG_UNDER_TEMP_SHIFT) + +/* + * OVER_TEMP (RW) + * + * Clear over temperature status, write 1 to clear + */ +#define TSNS_FLAG_OVER_TEMP_MASK (0x10000UL) +#define TSNS_FLAG_OVER_TEMP_SHIFT (16U) +#define TSNS_FLAG_OVER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_OVER_TEMP_SHIFT) & TSNS_FLAG_OVER_TEMP_MASK) +#define TSNS_FLAG_OVER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_OVER_TEMP_MASK) >> TSNS_FLAG_OVER_TEMP_SHIFT) + +/* + * IRQ (RW) + * + * IRQ flag, write 1 to clear + */ +#define TSNS_FLAG_IRQ_MASK (0x1U) +#define TSNS_FLAG_IRQ_SHIFT (0U) +#define TSNS_FLAG_IRQ_SET(x) (((uint32_t)(x) << TSNS_FLAG_IRQ_SHIFT) & TSNS_FLAG_IRQ_MASK) +#define TSNS_FLAG_IRQ_GET(x) (((uint32_t)(x) & TSNS_FLAG_IRQ_MASK) >> TSNS_FLAG_IRQ_SHIFT) + +/* Bitfield definition for register: UPPER_LIM_IRQ */ +/* + * T (RW) + * + * Maximum temperature for compare + */ +#define TSNS_UPPER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) +#define TSNS_UPPER_LIM_IRQ_T_SHIFT (0U) +#define TSNS_UPPER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_IRQ_T_SHIFT) & TSNS_UPPER_LIM_IRQ_T_MASK) +#define TSNS_UPPER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_IRQ_T_MASK) >> TSNS_UPPER_LIM_IRQ_T_SHIFT) + +/* Bitfield definition for register: LOWER_LIM_IRQ */ +/* + * T (RW) + * + * Minimum temperature for compare + */ +#define TSNS_LOWER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) +#define TSNS_LOWER_LIM_IRQ_T_SHIFT (0U) +#define TSNS_LOWER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_IRQ_T_SHIFT) & TSNS_LOWER_LIM_IRQ_T_MASK) +#define TSNS_LOWER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_IRQ_T_MASK) >> TSNS_LOWER_LIM_IRQ_T_SHIFT) + +/* Bitfield definition for register: UPPER_LIM_RST */ +/* + * T (RW) + * + * Maximum temperature for compare + */ +#define TSNS_UPPER_LIM_RST_T_MASK (0xFFFFFFFFUL) +#define TSNS_UPPER_LIM_RST_T_SHIFT (0U) +#define TSNS_UPPER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_RST_T_SHIFT) & TSNS_UPPER_LIM_RST_T_MASK) +#define TSNS_UPPER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_RST_T_MASK) >> TSNS_UPPER_LIM_RST_T_SHIFT) + +/* Bitfield definition for register: LOWER_LIM_RST */ +/* + * T (RW) + * + * Minimum temperature for compare + */ +#define TSNS_LOWER_LIM_RST_T_MASK (0xFFFFFFFFUL) +#define TSNS_LOWER_LIM_RST_T_SHIFT (0U) +#define TSNS_LOWER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_RST_T_SHIFT) & TSNS_LOWER_LIM_RST_T_MASK) +#define TSNS_LOWER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_RST_T_MASK) >> TSNS_LOWER_LIM_RST_T_SHIFT) + +/* Bitfield definition for register: ASYNC */ +/* + * ASYNC_TYPE (RW) + * + * Compare hotter than or colder than in asynchoronous mode + * 0: hotter than + * 1: colder than + */ +#define TSNS_ASYNC_ASYNC_TYPE_MASK (0x1000000UL) +#define TSNS_ASYNC_ASYNC_TYPE_SHIFT (24U) +#define TSNS_ASYNC_ASYNC_TYPE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_ASYNC_TYPE_SHIFT) & TSNS_ASYNC_ASYNC_TYPE_MASK) +#define TSNS_ASYNC_ASYNC_TYPE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_ASYNC_TYPE_MASK) >> TSNS_ASYNC_ASYNC_TYPE_SHIFT) + +/* + * POLARITY (RW) + * + */ +#define TSNS_ASYNC_POLARITY_MASK (0x10000UL) +#define TSNS_ASYNC_POLARITY_SHIFT (16U) +#define TSNS_ASYNC_POLARITY_SET(x) (((uint32_t)(x) << TSNS_ASYNC_POLARITY_SHIFT) & TSNS_ASYNC_POLARITY_MASK) +#define TSNS_ASYNC_POLARITY_GET(x) (((uint32_t)(x) & TSNS_ASYNC_POLARITY_MASK) >> TSNS_ASYNC_POLARITY_SHIFT) + +/* + * VALUE (RW) + * + * Value of async mode to compare + */ +#define TSNS_ASYNC_VALUE_MASK (0x7FFU) +#define TSNS_ASYNC_VALUE_SHIFT (0U) +#define TSNS_ASYNC_VALUE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_VALUE_SHIFT) & TSNS_ASYNC_VALUE_MASK) +#define TSNS_ASYNC_VALUE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_VALUE_MASK) >> TSNS_ASYNC_VALUE_SHIFT) + +/* Bitfield definition for register: ADVAN */ +/* + * ASYNC_IRQ (RO) + * + * interrupt status of asynchronous mode + */ +#define TSNS_ADVAN_ASYNC_IRQ_MASK (0x2000000UL) +#define TSNS_ADVAN_ASYNC_IRQ_SHIFT (25U) +#define TSNS_ADVAN_ASYNC_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ASYNC_IRQ_MASK) >> TSNS_ADVAN_ASYNC_IRQ_SHIFT) + +/* + * ACTIVE_IRQ (RO) + * + * interrupt status of active mode + */ +#define TSNS_ADVAN_ACTIVE_IRQ_MASK (0x1000000UL) +#define TSNS_ADVAN_ACTIVE_IRQ_SHIFT (24U) +#define TSNS_ADVAN_ACTIVE_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ACTIVE_IRQ_MASK) >> TSNS_ADVAN_ACTIVE_IRQ_SHIFT) + +/* + * SAMPLING (RO) + * + * temperature sampling is working + */ +#define TSNS_ADVAN_SAMPLING_MASK (0x10000UL) +#define TSNS_ADVAN_SAMPLING_SHIFT (16U) +#define TSNS_ADVAN_SAMPLING_GET(x) (((uint32_t)(x) & TSNS_ADVAN_SAMPLING_MASK) >> TSNS_ADVAN_SAMPLING_SHIFT) + +/* + * NEG_ONLY (RW) + * + * use negative compare polarity only + */ +#define TSNS_ADVAN_NEG_ONLY_MASK (0x2U) +#define TSNS_ADVAN_NEG_ONLY_SHIFT (1U) +#define TSNS_ADVAN_NEG_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_NEG_ONLY_SHIFT) & TSNS_ADVAN_NEG_ONLY_MASK) +#define TSNS_ADVAN_NEG_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_NEG_ONLY_MASK) >> TSNS_ADVAN_NEG_ONLY_SHIFT) + +/* + * POS_ONLY (RW) + * + * use positive compare polarity only + */ +#define TSNS_ADVAN_POS_ONLY_MASK (0x1U) +#define TSNS_ADVAN_POS_ONLY_SHIFT (0U) +#define TSNS_ADVAN_POS_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_POS_ONLY_SHIFT) & TSNS_ADVAN_POS_ONLY_MASK) +#define TSNS_ADVAN_POS_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_POS_ONLY_MASK) >> TSNS_ADVAN_POS_ONLY_SHIFT) + + + + +#endif /* HPM_TSNS_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h new file mode 100644 index 0000000000..cf1c0c6787 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h @@ -0,0 +1,515 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_UART_H +#define HPM_UART_H + +typedef struct { + __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __RW uint32_t CFG; /* 0x10: Configuration Register */ + __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ + __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ + union { + __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ + __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ + __RW uint32_t DLL; /* 0x20: Divisor Latch LSB (when DLAB = 1) */ + }; + union { + __RW uint32_t IER; /* 0x24: Interrupt Enable Register (when DLAB = 0) */ + __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ + }; + union { + __R uint32_t IIR; /* 0x28: Interrupt Identification Register */ + __W uint32_t FCR; /* 0x28: FIFO Control Register */ + }; + __RW uint32_t LCR; /* 0x2C: Line Control Register */ + __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ + __R uint32_t LSR; /* 0x34: Line Status Register */ + __R uint32_t MSR; /* 0x38: Modem Status Register */ +} UART_Type; + + +/* Bitfield definition for register: CFG */ +/* + * FIFOSIZE (RO) + * + * The depth of RXFIFO and TXFIFO + * 0: 16-byte FIFO + * 1: 32-byte FIFO + * 2: 64-byte FIFO + * 3: 128-byte FIFO + */ +#define UART_CFG_FIFOSIZE_MASK (0x3U) +#define UART_CFG_FIFOSIZE_SHIFT (0U) +#define UART_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT) + +/* Bitfield definition for register: OSCR */ +/* + * OSC (RW) + * + * Over-sample control + * The value must be an even number; any odd value + * writes to this field will be converted to an even value. + * OSC=0: The over-sample ratio is 32 + * OSC<=8: The over-sample ratio is 8 + * 8 < OSC< 32: The over sample ratio is OSC + */ +#define UART_OSCR_OSC_MASK (0x1FU) +#define UART_OSCR_OSC_SHIFT (0U) +#define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) +#define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) + +/* Bitfield definition for register: RBR */ +/* + * RBR (RO) + * + * Receive data read port + */ +#define UART_RBR_RBR_MASK (0xFFU) +#define UART_RBR_RBR_SHIFT (0U) +#define UART_RBR_RBR_GET(x) (((uint32_t)(x) & UART_RBR_RBR_MASK) >> UART_RBR_RBR_SHIFT) + +/* Bitfield definition for register: THR */ +/* + * THR (WO) + * + * Transmit data write port + */ +#define UART_THR_THR_MASK (0xFFU) +#define UART_THR_THR_SHIFT (0U) +#define UART_THR_THR_SET(x) (((uint32_t)(x) << UART_THR_THR_SHIFT) & UART_THR_THR_MASK) +#define UART_THR_THR_GET(x) (((uint32_t)(x) & UART_THR_THR_MASK) >> UART_THR_THR_SHIFT) + +/* Bitfield definition for register: DLL */ +/* + * DLL (RW) + * + * Least significant byte of the Divisor Latch + */ +#define UART_DLL_DLL_MASK (0xFFU) +#define UART_DLL_DLL_SHIFT (0U) +#define UART_DLL_DLL_SET(x) (((uint32_t)(x) << UART_DLL_DLL_SHIFT) & UART_DLL_DLL_MASK) +#define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) + +/* Bitfield definition for register: IER */ +/* + * EMSI (RW) + * + * Enable modem status interrupt + * The interrupt asserts when the status of one of the + * following occurs: + * The status of modem_rin, modem_dcdn, + * modem_dsrn or modem_ctsn (If the auto-cts mode is + * disabled) has been changed. + * If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), + * modem_ctsn would be used to control the transmitter. + */ +#define UART_IER_EMSI_MASK (0x8U) +#define UART_IER_EMSI_SHIFT (3U) +#define UART_IER_EMSI_SET(x) (((uint32_t)(x) << UART_IER_EMSI_SHIFT) & UART_IER_EMSI_MASK) +#define UART_IER_EMSI_GET(x) (((uint32_t)(x) & UART_IER_EMSI_MASK) >> UART_IER_EMSI_SHIFT) + +/* + * ELSI (RW) + * + * Enable receiver line status interrupt + */ +#define UART_IER_ELSI_MASK (0x4U) +#define UART_IER_ELSI_SHIFT (2U) +#define UART_IER_ELSI_SET(x) (((uint32_t)(x) << UART_IER_ELSI_SHIFT) & UART_IER_ELSI_MASK) +#define UART_IER_ELSI_GET(x) (((uint32_t)(x) & UART_IER_ELSI_MASK) >> UART_IER_ELSI_SHIFT) + +/* + * ETHEI (RW) + * + * Enable transmitter holding register interrupt + */ +#define UART_IER_ETHEI_MASK (0x2U) +#define UART_IER_ETHEI_SHIFT (1U) +#define UART_IER_ETHEI_SET(x) (((uint32_t)(x) << UART_IER_ETHEI_SHIFT) & UART_IER_ETHEI_MASK) +#define UART_IER_ETHEI_GET(x) (((uint32_t)(x) & UART_IER_ETHEI_MASK) >> UART_IER_ETHEI_SHIFT) + +/* + * ERBI (RW) + * + * Enable received data available interrupt and the + * character timeout interrupt + * 0: Disable + * 1: Enable + */ +#define UART_IER_ERBI_MASK (0x1U) +#define UART_IER_ERBI_SHIFT (0U) +#define UART_IER_ERBI_SET(x) (((uint32_t)(x) << UART_IER_ERBI_SHIFT) & UART_IER_ERBI_MASK) +#define UART_IER_ERBI_GET(x) (((uint32_t)(x) & UART_IER_ERBI_MASK) >> UART_IER_ERBI_SHIFT) + +/* Bitfield definition for register: DLM */ +/* + * DLM (RW) + * + * Most significant byte of the Divisor Latch + */ +#define UART_DLM_DLM_MASK (0xFFU) +#define UART_DLM_DLM_SHIFT (0U) +#define UART_DLM_DLM_SET(x) (((uint32_t)(x) << UART_DLM_DLM_SHIFT) & UART_DLM_DLM_MASK) +#define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) + +/* Bitfield definition for register: IIR */ +/* + * FIFOED (RO) + * + * FIFOs enabled + * These two bits are 1 when bit 0 of the FIFO Control + * Register (FIFOE) is set to 1. + */ +#define UART_IIR_FIFOED_MASK (0xC0U) +#define UART_IIR_FIFOED_SHIFT (6U) +#define UART_IIR_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR_FIFOED_MASK) >> UART_IIR_FIFOED_SHIFT) + +/* + * INTRID (RO) + * + * Interrupt ID + */ +#define UART_IIR_INTRID_MASK (0xFU) +#define UART_IIR_INTRID_SHIFT (0U) +#define UART_IIR_INTRID_GET(x) (((uint32_t)(x) & UART_IIR_INTRID_MASK) >> UART_IIR_INTRID_SHIFT) + +/* Bitfield definition for register: FCR */ +/* + * RFIFOT (WO) + * + * Receiver FIFO trigger level + */ +#define UART_FCR_RFIFOT_MASK (0xC0U) +#define UART_FCR_RFIFOT_SHIFT (6U) +#define UART_FCR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_RFIFOT_SHIFT) & UART_FCR_RFIFOT_MASK) +#define UART_FCR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_RFIFOT_MASK) >> UART_FCR_RFIFOT_SHIFT) + +/* + * TFIFOT (WO) + * + * Transmitter FIFO trigger level + */ +#define UART_FCR_TFIFOT_MASK (0x30U) +#define UART_FCR_TFIFOT_SHIFT (4U) +#define UART_FCR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_TFIFOT_SHIFT) & UART_FCR_TFIFOT_MASK) +#define UART_FCR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_TFIFOT_MASK) >> UART_FCR_TFIFOT_SHIFT) + +/* + * DMAE (WO) + * + * DMA enable + * 0: Disable + * 1: Enable + */ +#define UART_FCR_DMAE_MASK (0x8U) +#define UART_FCR_DMAE_SHIFT (3U) +#define UART_FCR_DMAE_SET(x) (((uint32_t)(x) << UART_FCR_DMAE_SHIFT) & UART_FCR_DMAE_MASK) +#define UART_FCR_DMAE_GET(x) (((uint32_t)(x) & UART_FCR_DMAE_MASK) >> UART_FCR_DMAE_SHIFT) + +/* + * TFIFORST (WO) + * + * Transmitter FIFO reset + * Write 1 to clear all bytes in the TXFIFO and resets its + * counter. The Transmitter Shift Register is not cleared. + * This bit will automatically be cleared. + */ +#define UART_FCR_TFIFORST_MASK (0x4U) +#define UART_FCR_TFIFORST_SHIFT (2U) +#define UART_FCR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_TFIFORST_SHIFT) & UART_FCR_TFIFORST_MASK) +#define UART_FCR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_TFIFORST_MASK) >> UART_FCR_TFIFORST_SHIFT) + +/* + * RFIFORST (WO) + * + * Receiver FIFO reset + * Write 1 to clear all bytes in the RXFIFO and resets its + * counter. The Receiver Shift Register is not cleared. + * This bit will automatically be cleared. + */ +#define UART_FCR_RFIFORST_MASK (0x2U) +#define UART_FCR_RFIFORST_SHIFT (1U) +#define UART_FCR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_RFIFORST_SHIFT) & UART_FCR_RFIFORST_MASK) +#define UART_FCR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_RFIFORST_MASK) >> UART_FCR_RFIFORST_SHIFT) + +/* + * FIFOE (WO) + * + * FIFO enable + * Write 1 to enable both the transmitter and receiver + * FIFOs. + * The FIFOs are reset when the value of this bit toggles. + */ +#define UART_FCR_FIFOE_MASK (0x1U) +#define UART_FCR_FIFOE_SHIFT (0U) +#define UART_FCR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCR_FIFOE_SHIFT) & UART_FCR_FIFOE_MASK) +#define UART_FCR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCR_FIFOE_MASK) >> UART_FCR_FIFOE_SHIFT) + +/* Bitfield definition for register: LCR */ +/* + * DLAB (RW) + * + * Divisor latch access bit + */ +#define UART_LCR_DLAB_MASK (0x80U) +#define UART_LCR_DLAB_SHIFT (7U) +#define UART_LCR_DLAB_SET(x) (((uint32_t)(x) << UART_LCR_DLAB_SHIFT) & UART_LCR_DLAB_MASK) +#define UART_LCR_DLAB_GET(x) (((uint32_t)(x) & UART_LCR_DLAB_MASK) >> UART_LCR_DLAB_SHIFT) + +/* + * BC (RW) + * + * Break control + */ +#define UART_LCR_BC_MASK (0x40U) +#define UART_LCR_BC_SHIFT (6U) +#define UART_LCR_BC_SET(x) (((uint32_t)(x) << UART_LCR_BC_SHIFT) & UART_LCR_BC_MASK) +#define UART_LCR_BC_GET(x) (((uint32_t)(x) & UART_LCR_BC_MASK) >> UART_LCR_BC_SHIFT) + +/* + * SPS (RW) + * + * Stick parity + * 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). + * 0: Disable the sticky bit parity. + */ +#define UART_LCR_SPS_MASK (0x20U) +#define UART_LCR_SPS_SHIFT (5U) +#define UART_LCR_SPS_SET(x) (((uint32_t)(x) << UART_LCR_SPS_SHIFT) & UART_LCR_SPS_MASK) +#define UART_LCR_SPS_GET(x) (((uint32_t)(x) & UART_LCR_SPS_MASK) >> UART_LCR_SPS_SHIFT) + +/* + * EPS (RW) + * + * Even parity select + * 1: Even parity (an even number of logic-1 is in the data + * and parity bits) + * 0: Old parity. + */ +#define UART_LCR_EPS_MASK (0x10U) +#define UART_LCR_EPS_SHIFT (4U) +#define UART_LCR_EPS_SET(x) (((uint32_t)(x) << UART_LCR_EPS_SHIFT) & UART_LCR_EPS_MASK) +#define UART_LCR_EPS_GET(x) (((uint32_t)(x) & UART_LCR_EPS_MASK) >> UART_LCR_EPS_SHIFT) + +/* + * PEN (RW) + * + * Parity enable + * When this bit is set, a parity bit is generated in + * transmitted data before the first STOP bit and the parity + * bit would be checked for the received data. + */ +#define UART_LCR_PEN_MASK (0x8U) +#define UART_LCR_PEN_SHIFT (3U) +#define UART_LCR_PEN_SET(x) (((uint32_t)(x) << UART_LCR_PEN_SHIFT) & UART_LCR_PEN_MASK) +#define UART_LCR_PEN_GET(x) (((uint32_t)(x) & UART_LCR_PEN_MASK) >> UART_LCR_PEN_SHIFT) + +/* + * STB (RW) + * + * Number of STOP bits + * 0: 1 bits + * 1: The number of STOP bit is based on the WLS setting + * When WLS = 0, STOP bit is 1.5 bits + * When WLS = 1, 2, 3, STOP bit is 2 bits + */ +#define UART_LCR_STB_MASK (0x4U) +#define UART_LCR_STB_SHIFT (2U) +#define UART_LCR_STB_SET(x) (((uint32_t)(x) << UART_LCR_STB_SHIFT) & UART_LCR_STB_MASK) +#define UART_LCR_STB_GET(x) (((uint32_t)(x) & UART_LCR_STB_MASK) >> UART_LCR_STB_SHIFT) + +/* + * WLS (RW) + * + * Word length setting + * 0: 5 bits + * 1: 6 bits + * 2: 7 bits + * 3: 8 bits + */ +#define UART_LCR_WLS_MASK (0x3U) +#define UART_LCR_WLS_SHIFT (0U) +#define UART_LCR_WLS_SET(x) (((uint32_t)(x) << UART_LCR_WLS_SHIFT) & UART_LCR_WLS_MASK) +#define UART_LCR_WLS_GET(x) (((uint32_t)(x) & UART_LCR_WLS_MASK) >> UART_LCR_WLS_SHIFT) + +/* Bitfield definition for register: MCR */ +/* + * AFE (RW) + * + * Auto flow control enable + * 0: Disable + * 1: The auto-CTS and auto-RTS setting is based on the + * RTS bit setting: + * When RTS = 0, auto-CTS only + * When RTS = 1, auto-CTS and auto-RTS + */ +#define UART_MCR_AFE_MASK (0x20U) +#define UART_MCR_AFE_SHIFT (5U) +#define UART_MCR_AFE_SET(x) (((uint32_t)(x) << UART_MCR_AFE_SHIFT) & UART_MCR_AFE_MASK) +#define UART_MCR_AFE_GET(x) (((uint32_t)(x) & UART_MCR_AFE_MASK) >> UART_MCR_AFE_SHIFT) + +/* + * LOOP (RW) + * + * Enable loopback mode + * 0: Disable + * 1: Enable + */ +#define UART_MCR_LOOP_MASK (0x10U) +#define UART_MCR_LOOP_SHIFT (4U) +#define UART_MCR_LOOP_SET(x) (((uint32_t)(x) << UART_MCR_LOOP_SHIFT) & UART_MCR_LOOP_MASK) +#define UART_MCR_LOOP_GET(x) (((uint32_t)(x) & UART_MCR_LOOP_MASK) >> UART_MCR_LOOP_SHIFT) + +/* + * RTS (RW) + * + * Request to send + * This bit controls the modem_rtsn output. + * 0: The modem_rtsn output signal will be driven HIGH + * 1: The modem_rtsn output signal will be driven LOW + */ +#define UART_MCR_RTS_MASK (0x2U) +#define UART_MCR_RTS_SHIFT (1U) +#define UART_MCR_RTS_SET(x) (((uint32_t)(x) << UART_MCR_RTS_SHIFT) & UART_MCR_RTS_MASK) +#define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) + +/* Bitfield definition for register: LSR */ +/* + * ERRF (RO) + * + * Error in RXFIFO + * In the FIFO mode, this bit is set when there is at least + * one parity error, framing error, or line break + * associated with data in the RXFIFO. It is cleared when + * this register is read and there is no more error for the + * rest of data in the RXFIFO. + */ +#define UART_LSR_ERRF_MASK (0x80U) +#define UART_LSR_ERRF_SHIFT (7U) +#define UART_LSR_ERRF_GET(x) (((uint32_t)(x) & UART_LSR_ERRF_MASK) >> UART_LSR_ERRF_SHIFT) + +/* + * TEMT (RO) + * + * Transmitter empty + * This bit is 1 when the THR (TXFIFO in the FIFO + * mode) and the Transmitter Shift Register (TSR) are + * both empty. Otherwise, it is zero. + */ +#define UART_LSR_TEMT_MASK (0x40U) +#define UART_LSR_TEMT_SHIFT (6U) +#define UART_LSR_TEMT_GET(x) (((uint32_t)(x) & UART_LSR_TEMT_MASK) >> UART_LSR_TEMT_SHIFT) + +/* + * THRE (RO) + * + * Transmitter Holding Register empty + * This bit is 1 when the THR (TXFIFO in the FIFO + * mode) is empty. Otherwise, it is zero. + * If the THRE interrupt is enabled, an interrupt is + * triggered when THRE becomes 1. + */ +#define UART_LSR_THRE_MASK (0x20U) +#define UART_LSR_THRE_SHIFT (5U) +#define UART_LSR_THRE_GET(x) (((uint32_t)(x) & UART_LSR_THRE_MASK) >> UART_LSR_THRE_SHIFT) + +/* + * LBREAK (RO) + * + * Line break + * This bit is set when the uart_sin input signal was held + * LOWfor longer than the time for a full-word + * transmission. A full-word transmission is the + * transmission of the START, data, parity, and STOP + * bits. It is cleared when this register is read. + * In the FIFO mode, this bit indicates the line break for + * the received data at the top of the RXFIFO. + */ +#define UART_LSR_LBREAK_MASK (0x10U) +#define UART_LSR_LBREAK_SHIFT (4U) +#define UART_LSR_LBREAK_GET(x) (((uint32_t)(x) & UART_LSR_LBREAK_MASK) >> UART_LSR_LBREAK_SHIFT) + +/* + * FE (RO) + * + * Framing error + * This bit is set when the received STOP bit is not + * HIGH. It is cleared when this register is read. + * In the FIFO mode, this bit indicates the framing error + * for the received data at the top of the RXFIFO. + */ +#define UART_LSR_FE_MASK (0x8U) +#define UART_LSR_FE_SHIFT (3U) +#define UART_LSR_FE_GET(x) (((uint32_t)(x) & UART_LSR_FE_MASK) >> UART_LSR_FE_SHIFT) + +/* + * PE (RO) + * + * Parity error + * This bit is set when the received parity does not match + * with the parity selected in the LCR[5:4]. It is cleared + * when this register is read. + * In the FIFO mode, this bit indicates the parity error + * for the received data at the top of the RXFIFO. + */ +#define UART_LSR_PE_MASK (0x4U) +#define UART_LSR_PE_SHIFT (2U) +#define UART_LSR_PE_GET(x) (((uint32_t)(x) & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT) + +/* + * OE (RO) + * + * Overrun error + * This bit indicates that data in the Receiver Buffer + * Register (RBR) is overrun. + */ +#define UART_LSR_OE_MASK (0x2U) +#define UART_LSR_OE_SHIFT (1U) +#define UART_LSR_OE_GET(x) (((uint32_t)(x) & UART_LSR_OE_MASK) >> UART_LSR_OE_SHIFT) + +/* + * DR (RO) + * + * Data ready. + * This bit is set when there are incoming received data + * in the Receiver Buffer Register (RBR). It is cleared + * when all of the received data are read. + */ +#define UART_LSR_DR_MASK (0x1U) +#define UART_LSR_DR_SHIFT (0U) +#define UART_LSR_DR_GET(x) (((uint32_t)(x) & UART_LSR_DR_MASK) >> UART_LSR_DR_SHIFT) + +/* Bitfield definition for register: MSR */ +/* + * CTS (RO) + * + * Clear to send + * 0: The modem_ctsn input signal is HIGH. + * 1: The modem_ctsn input signal is LOW. + */ +#define UART_MSR_CTS_MASK (0x10U) +#define UART_MSR_CTS_SHIFT (4U) +#define UART_MSR_CTS_GET(x) (((uint32_t)(x) & UART_MSR_CTS_MASK) >> UART_MSR_CTS_SHIFT) + +/* + * DCTS (RC) + * + * Delta clear to send + * This bit is set when the state of the modem_ctsn input + * signal has been changed since the last time this + * register is read. + */ +#define UART_MSR_DCTS_MASK (0x1U) +#define UART_MSR_DCTS_SHIFT (0U) +#define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) + + + + +#endif /* HPM_UART_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h new file mode 100644 index 0000000000..72fdc9dcd2 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_usb_regs.h @@ -0,0 +1,2197 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_USB_H +#define HPM_USB_H + +typedef struct { + __R uint8_t RESERVED0[128]; /* 0x0 - 0x7F: Reserved */ + __RW uint32_t GPTIMER0LD; /* 0x80: General Purpose Timer #0 Load Register */ + __RW uint32_t GPTIMER0CTRL; /* 0x84: General Purpose Timer #0 Controller Register */ + __RW uint32_t GPTIMER1LD; /* 0x88: General Purpose Timer #1 Load Register */ + __RW uint32_t GPTIMER1CTRL; /* 0x8C: General Purpose Timer #1 Controller Register */ + __RW uint32_t SBUSCFG; /* 0x90: System Bus Config Register */ + __R uint8_t RESERVED1[172]; /* 0x94 - 0x13F: Reserved */ + __RW uint32_t USBCMD; /* 0x140: USB Command Register */ + __RW uint32_t USBSTS; /* 0x144: USB Status Register */ + __RW uint32_t USBINTR; /* 0x148: Interrupt Enable Register */ + __RW uint32_t FRINDEX; /* 0x14C: USB Frame Index Register */ + __R uint8_t RESERVED2[4]; /* 0x150 - 0x153: Reserved */ + union { + __RW uint32_t DEVICEADDR; /* 0x154: Device Address Register */ + __RW uint32_t PERIODICLISTBASE; /* 0x154: Frame List Base Address Register */ + }; + union { + __RW uint32_t ASYNCLISTADDR; /* 0x158: Next Asynch. Address Register */ + __RW uint32_t ENDPTLISTADDR; /* 0x158: Endpoint List Address Register */ + }; + __R uint8_t RESERVED3[4]; /* 0x15C - 0x15F: Reserved */ + __RW uint32_t BURSTSIZE; /* 0x160: Programmable Burst Size Register */ + __RW uint32_t TXFILLTUNING; /* 0x164: TX FIFO Fill Tuning Register */ + __R uint8_t RESERVED4[16]; /* 0x168 - 0x177: Reserved */ + __RW uint32_t ENDPTNAK; /* 0x178: Endpoint NAK Register */ + __RW uint32_t ENDPTNAKEN; /* 0x17C: Endpoint NAK Enable Register */ + __R uint8_t RESERVED5[4]; /* 0x180 - 0x183: Reserved */ + __RW uint32_t PORTSC1; /* 0x184: Port Status & Control */ + __R uint8_t RESERVED6[28]; /* 0x188 - 0x1A3: Reserved */ + __RW uint32_t OTGSC; /* 0x1A4: On-The-Go Status & control Register */ + __RW uint32_t USBMODE; /* 0x1A8: USB Device Mode Register */ + __RW uint32_t ENDPTSETUPSTAT; /* 0x1AC: Endpoint Setup Status Register */ + __RW uint32_t ENDPTPRIME; /* 0x1B0: Endpoint Prime Register */ + __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ + __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ + __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ + __RW uint32_t ENDPTCTRL[8]; /* 0x1C0 - 0x1DC: Endpoint Control0 Register... Endpoint Control7 Register */ + __R uint8_t RESERVED7[32]; /* 0x1E0 - 0x1FF: Reserved */ + __RW uint32_t OTG_CTRL0; /* 0x200: */ + __R uint8_t RESERVED8[12]; /* 0x204 - 0x20F: Reserved */ + __RW uint32_t PHY_CTRL0; /* 0x210: */ + __RW uint32_t PHY_CTRL1; /* 0x214: */ + __R uint8_t RESERVED9[8]; /* 0x218 - 0x21F: Reserved */ + __RW uint32_t TOP_STATUS; /* 0x220: */ + __RW uint32_t PHY_STATUS; /* 0x224: */ +} USB_Type; + + +/* Bitfield definition for register: GPTIMER0LD */ +/* + * GPTLD (RW) + * + * GPTLD + * General Purpose Timer Load Value + * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. + * This value represents the time in microseconds minus 1 for the timer duration. + * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. + * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFUL) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER0LD_GPTLD_SHIFT) & USB_GPTIMER0LD_GPTLD_MASK) +#define USB_GPTIMER0LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER0LD_GPTLD_MASK) >> USB_GPTIMER0LD_GPTLD_SHIFT) + +/* Bitfield definition for register: GPTIMER0CTRL */ +/* + * GPTRUN (RW) + * + * GPTRUN + * General Purpose Timer Run + * GPTCNT bits are not effected when setting or clearing this bit. + * 0 - Stop counting + * 1 - Run + */ +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000UL) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER0CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRUN_SHIFT) & USB_GPTIMER0CTRL_GPTRUN_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRUN_MASK) >> USB_GPTIMER0CTRL_GPTRUN_SHIFT) + +/* + * GPTRST (WO) + * + * GPTRST + * General Purpose Timer Reset + * 0 - No action + * 1 - Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000UL) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER0CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRST_SHIFT) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRST_MASK) >> USB_GPTIMER0CTRL_GPTRST_SHIFT) + +/* + * GPTMODE (RW) + * + * GPTMODE + * General Purpose Timer Mode + * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is + * reset by software; + * In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the + * counter value from GPTLD bits to start again. + * 0 - One Shot Mode + * 1 - Repeat Mode + */ +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000UL) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER0CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTMODE_SHIFT) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTMODE_MASK) >> USB_GPTIMER0CTRL_GPTMODE_SHIFT) + +/* + * GPTCNT (RO) + * + * GPTCNT + * General Purpose Timer Counter. + * This field is the count value of the countdown timer. + */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFUL) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTCNT_MASK) >> USB_GPTIMER0CTRL_GPTCNT_SHIFT) + +/* Bitfield definition for register: GPTIMER1LD */ +/* + * GPTLD (RW) + * + * GPTLD + * General Purpose Timer Load Value + * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. + * This value represents the time in microseconds minus 1 for the timer duration. + * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. + * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFUL) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER1LD_GPTLD_SHIFT) & USB_GPTIMER1LD_GPTLD_MASK) +#define USB_GPTIMER1LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER1LD_GPTLD_MASK) >> USB_GPTIMER1LD_GPTLD_SHIFT) + +/* Bitfield definition for register: GPTIMER1CTRL */ +/* + * GPTRUN (RW) + * + * GPTRUN + * General Purpose Timer Run + * GPTCNT bits are not effected when setting or clearing this bit. + * 0 - Stop counting + * 1 - Run + */ +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000UL) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER1CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRUN_SHIFT) & USB_GPTIMER1CTRL_GPTRUN_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRUN_MASK) >> USB_GPTIMER1CTRL_GPTRUN_SHIFT) + +/* + * GPTRST (WO) + * + * GPTRST + * General Purpose Timer Reset + * 0 - No action + * 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + */ +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000UL) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER1CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRST_SHIFT) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRST_MASK) >> USB_GPTIMER1CTRL_GPTRST_SHIFT) + +/* + * GPTMODE (RW) + * + * GPTMODE + * General Purpose Timer Mode + * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is + * reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and + * automatically reload the counter value from GPTLD bits to start again. + * 0 - One Shot Mode + * 1 - Repeat Mode + */ +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000UL) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER1CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTMODE_SHIFT) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTMODE_MASK) >> USB_GPTIMER1CTRL_GPTMODE_SHIFT) + +/* + * GPTCNT (RO) + * + * GPTCNT + * General Purpose Timer Counter. + * This field is the count value of the countdown timer. + */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFUL) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTCNT_MASK) >> USB_GPTIMER1CTRL_GPTCNT_SHIFT) + +/* Bitfield definition for register: SBUSCFG */ +/* + * AHBBRST (RW) + * + * AHBBRST + * AHB master interface Burst configuration + * These bits control AHB master transfer type sequence (or priority). + * NOTE: This register overrides n_BURSTSIZE register when its value is not zero. + * 000 - Incremental burst of unspecified length only + * 001 - INCR4 burst, then single transfer + * 010 - INCR8 burst, INCR4 burst, then single transfer + * 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 100 - Reserved, don't use + * 101 - INCR4 burst, then incremental burst of unspecified length + * 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +#define USB_SBUSCFG_AHBBRST_SET(x) (((uint32_t)(x) << USB_SBUSCFG_AHBBRST_SHIFT) & USB_SBUSCFG_AHBBRST_MASK) +#define USB_SBUSCFG_AHBBRST_GET(x) (((uint32_t)(x) & USB_SBUSCFG_AHBBRST_MASK) >> USB_SBUSCFG_AHBBRST_SHIFT) + +/* Bitfield definition for register: USBCMD */ +/* + * ITC (RW) + * + * ITC + * Interrupt Threshold Control -Read/Write. + * The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are + * shown below. + * Value Maximum Interrupt Interval + * 00000000 - Immediate (no threshold) + * 00000001 - 1 micro-frame + * 00000010 - 2 micro-frames + * 00000100 - 4 micro-frames + * 00001000 - 8 micro-frames + * 00010000 - 16 micro-frames + * 00100000 - 32 micro-frames + * 01000000 - 64 micro-frames + */ +#define USB_USBCMD_ITC_MASK (0xFF0000UL) +#define USB_USBCMD_ITC_SHIFT (16U) +#define USB_USBCMD_ITC_SET(x) (((uint32_t)(x) << USB_USBCMD_ITC_SHIFT) & USB_USBCMD_ITC_MASK) +#define USB_USBCMD_ITC_GET(x) (((uint32_t)(x) & USB_USBCMD_ITC_MASK) >> USB_USBCMD_ITC_SHIFT) + +/* + * FS_2 (RW) + * + * FS_2 + * Frame List Size - (Read/Write or Read Only). [host mode only] + * This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. + * This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. + * NOTE: This field is made up from USBCMD bits 15, 3 and 2. + * Value Meaning + * 0b000 - 1024 elements (4096 bytes) Default value + * 0b001 - 512 elements (2048 bytes) + * 0b010 - 256 elements (1024 bytes) + * 0b011 - 128 elements (512 bytes) + * 0b100 - 64 elements (256 bytes) + * 0b101 - 32 elements (128 bytes) + * 0b110 - 16 elements (64 bytes) + * 0b111 - 8 elements (32 bytes) + */ +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +#define USB_USBCMD_FS_2_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_2_SHIFT) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_FS_2_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_2_MASK) >> USB_USBCMD_FS_2_SHIFT) + +/* + * ATDTW (RW) + * + * ATDTW + * Add dTD TripWire - Read/Write. [device mode only] + * This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's + * linked list. This bit is set and cleared by software. + * This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD + * to a primed endpoint may go unrecognized. + */ +#define USB_USBCMD_ATDTW_MASK (0x4000U) +#define USB_USBCMD_ATDTW_SHIFT (14U) +#define USB_USBCMD_ATDTW_SET(x) (((uint32_t)(x) << USB_USBCMD_ATDTW_SHIFT) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_ATDTW_GET(x) (((uint32_t)(x) & USB_USBCMD_ATDTW_MASK) >> USB_USBCMD_ATDTW_SHIFT) + +/* + * SUTW (RW) + * + * SUTW + * Setup TripWire - Read/Write. [device mode only] + * This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. + * If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. + * This bit would also be cleared by hardware when a hazard detected. + */ +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW_SET(x) (((uint32_t)(x) << USB_USBCMD_SUTW_SHIFT) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_SUTW_GET(x) (((uint32_t)(x) & USB_USBCMD_SUTW_MASK) >> USB_USBCMD_SUTW_SHIFT) + +/* + * ASPE (RW) + * + * ASPE + * Asynchronous Schedule Park Mode Enable - Read/Write. + * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. + * NOTE: ASPE bit reset value: '0b' for OTG controller . + */ +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASPE_SHIFT) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ASPE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASPE_MASK) >> USB_USBCMD_ASPE_SHIFT) + +/* + * ASP (RW) + * + * ASP + * Asynchronous Schedule Park Mode Count - Read/Write. + * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. + * It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. + * Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. + * This field is set to 3h in all controller core. + */ +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP_SET(x) (((uint32_t)(x) << USB_USBCMD_ASP_SHIFT) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASP_GET(x) (((uint32_t)(x) & USB_USBCMD_ASP_MASK) >> USB_USBCMD_ASP_SHIFT) + +/* + * IAA (RW) + * + * IAA + * Interrupt on Async Advance Doorbell - Read/Write. + * This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. + * When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. + * The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. + * This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + */ +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA_SET(x) (((uint32_t)(x) << USB_USBCMD_IAA_SHIFT) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_IAA_GET(x) (((uint32_t)(x) & USB_USBCMD_IAA_MASK) >> USB_USBCMD_IAA_SHIFT) + +/* + * ASE (RW) + * + * ASE + * Asynchronous Schedule Enable - Read/Write. Default 0b. + * This bit controls whether the host controller skips processing the Asynchronous Schedule. + * Only the host controller uses this bit. + * Values Meaning + * 0 - Do not process the Asynchronous Schedule. + * 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +#define USB_USBCMD_ASE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASE_SHIFT) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_ASE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASE_MASK) >> USB_USBCMD_ASE_SHIFT) + +/* + * PSE (RW) + * + * PSE + * Periodic Schedule Enable- Read/Write. Default 0b. + * This bit controls whether the host controller skips processing the Periodic Schedule. + * Only the host controller uses this bit. + * Values Meaning + * 0 - Do not process the Periodic Schedule + * 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +#define USB_USBCMD_PSE_SET(x) (((uint32_t)(x) << USB_USBCMD_PSE_SHIFT) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_PSE_GET(x) (((uint32_t)(x) & USB_USBCMD_PSE_MASK) >> USB_USBCMD_PSE_SHIFT) + +/* + * FS_1 (RW) + * + * FS_1 + * See description at bit 15 + */ +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_1_SHIFT) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_FS_1_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_1_MASK) >> USB_USBCMD_FS_1_SHIFT) + +/* + * RST (RW) + * + * RST + * Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. + * Host operation mode: + * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. + * Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. + * Attempting to reset an actively running host controller will result in undefined behavior. + * Device operation mode: + * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. + * Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + */ +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST_SET(x) (((uint32_t)(x) << USB_USBCMD_RST_SHIFT) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_RST_GET(x) (((uint32_t)(x) & USB_USBCMD_RST_MASK) >> USB_USBCMD_RST_SHIFT) + +/* + * RS (RW) + * + * RS + * Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. + * Host operation mode: + * When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. + * Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). + * Device operation mode: + * Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. + * This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS_SET(x) (((uint32_t)(x) << USB_USBCMD_RS_SHIFT) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RS_GET(x) (((uint32_t)(x) & USB_USBCMD_RS_MASK) >> USB_USBCMD_RS_SHIFT) + +/* Bitfield definition for register: USBSTS */ +/* + * TI1 (RWC) + * + * TI1 + * General Purpose Timer Interrupt 1(GPTINT1)--R/WC. + * This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this + * bit will clear it. + */ +#define USB_USBSTS_TI1_MASK (0x2000000UL) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1_SET(x) (((uint32_t)(x) << USB_USBSTS_TI1_SHIFT) & USB_USBSTS_TI1_MASK) +#define USB_USBSTS_TI1_GET(x) (((uint32_t)(x) & USB_USBSTS_TI1_MASK) >> USB_USBSTS_TI1_SHIFT) + +/* + * TI0 (RWC) + * + * TI0 + * General Purpose Timer Interrupt 0(GPTINT0)--R/WC. + * This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this + * bit clears it. + */ +#define USB_USBSTS_TI0_MASK (0x1000000UL) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0_SET(x) (((uint32_t)(x) << USB_USBSTS_TI0_SHIFT) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI0_GET(x) (((uint32_t)(x) & USB_USBSTS_TI0_MASK) >> USB_USBSTS_TI0_SHIFT) + +/* + * UPI (RWC) + * + * USB Host Periodic Interrupt – RWC. Default = 0b. + * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. + * This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. + * This bit is not used by the device controller and will always be zero. + */ +#define USB_USBSTS_UPI_MASK (0x80000UL) +#define USB_USBSTS_UPI_SHIFT (19U) +#define USB_USBSTS_UPI_SET(x) (((uint32_t)(x) << USB_USBSTS_UPI_SHIFT) & USB_USBSTS_UPI_MASK) +#define USB_USBSTS_UPI_GET(x) (((uint32_t)(x) & USB_USBSTS_UPI_MASK) >> USB_USBSTS_UPI_SHIFT) + +/* + * UAI (RWC) + * + * USB Host Asynchronous Interrupt – RWC. Default = 0b. + * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. + * This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. + * This bit is not used by the device controller and will always be zero + */ +#define USB_USBSTS_UAI_MASK (0x40000UL) +#define USB_USBSTS_UAI_SHIFT (18U) +#define USB_USBSTS_UAI_SET(x) (((uint32_t)(x) << USB_USBSTS_UAI_SHIFT) & USB_USBSTS_UAI_MASK) +#define USB_USBSTS_UAI_GET(x) (((uint32_t)(x) & USB_USBSTS_UAI_MASK) >> USB_USBSTS_UAI_SHIFT) + +/* + * NAKI (RO) + * + * NAKI + * NAK Interrupt Bit--RO. + * This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and + * corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware + * when all Enabled TX/RX Endpoint NAK bits are cleared. + */ +#define USB_USBSTS_NAKI_MASK (0x10000UL) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI_GET(x) (((uint32_t)(x) & USB_USBSTS_NAKI_MASK) >> USB_USBSTS_NAKI_SHIFT) + +/* + * AS (RO) + * + * AS + * Asynchronous Schedule Status - Read Only. + * This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. + * The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. + * When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). + * Only used in the host operation mode. + */ +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS_GET(x) (((uint32_t)(x) & USB_USBSTS_AS_MASK) >> USB_USBSTS_AS_SHIFT) + +/* + * PS (RO) + * + * PS + * Periodic Schedule Status - Read Only. + * This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). + * Only used in the host operation mode. + */ +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS_GET(x) (((uint32_t)(x) & USB_USBSTS_PS_MASK) >> USB_USBSTS_PS_SHIFT) + +/* + * RCL (RO) + * + * RCL + * Reclamation - Read Only. + * This is a read-only status bit used to detect an empty asynchronous schedule. + * Only used in the host operation mode. + */ +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL_GET(x) (((uint32_t)(x) & USB_USBSTS_RCL_MASK) >> USB_USBSTS_RCL_SHIFT) + +/* + * HCH (RO) + * + * HCH + * HCHaIted - Read Only. + * This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). + * Only used in the host operation mode. + * Default value is '0b' for OTG core . + * This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE + * register. + * NOTE: HCH bit reset value: '0b' for OTG controller core . + */ +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH_GET(x) (((uint32_t)(x) & USB_USBSTS_HCH_MASK) >> USB_USBSTS_HCH_SHIFT) + +/* + * SLI (RWC) + * + * SLI + * DCSuspend - R/WC. + * When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. + * Only used in device operation mode. + */ +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI_SET(x) (((uint32_t)(x) << USB_USBSTS_SLI_SHIFT) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_SLI_GET(x) (((uint32_t)(x) & USB_USBSTS_SLI_MASK) >> USB_USBSTS_SLI_SHIFT) + +/* + * SRI (RWC) + * + * SRI + * SOF Received - R/WC. + * When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. + * Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. + * Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. + * In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. + * Software writes a 1 to this bit to clear it. + */ +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI_SET(x) (((uint32_t)(x) << USB_USBSTS_SRI_SHIFT) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SRI_GET(x) (((uint32_t)(x) & USB_USBSTS_SRI_MASK) >> USB_USBSTS_SRI_SHIFT) + +/* + * URI (RWC) + * + * URI + * USB Reset Received - R/WC. + * When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. + * Software can write a 1 to this bit to clear the USB Reset Received status bit. + * Only used in device operation mode. + */ +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI_SET(x) (((uint32_t)(x) << USB_USBSTS_URI_SHIFT) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_URI_GET(x) (((uint32_t)(x) & USB_USBSTS_URI_MASK) >> USB_USBSTS_URI_SHIFT) + +/* + * AAI (RWC) + * + * AAI + * Interrupt on Async Advance - R/WC. + * System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. + * Only used in host operation mode. + */ +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI_SET(x) (((uint32_t)(x) << USB_USBSTS_AAI_SHIFT) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_AAI_GET(x) (((uint32_t)(x) & USB_USBSTS_AAI_MASK) >> USB_USBSTS_AAI_SHIFT) + +/* + * SEI (RWC) + * + * System Error – RWC. Default = 0b. + * In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + */ +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI_SET(x) (((uint32_t)(x) << USB_USBSTS_SEI_SHIFT) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_SEI_GET(x) (((uint32_t)(x) & USB_USBSTS_SEI_MASK) >> USB_USBSTS_SEI_SHIFT) + +/* + * FRI (RWC) + * + * FRI + * Frame List Rollover - R/WC. + * The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to + * zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the + * frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the + * Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host + * Controller sets this bit to a one every time FHINDEX [12] toggles. + * Only used in host operation mode. + */ +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI_SET(x) (((uint32_t)(x) << USB_USBSTS_FRI_SHIFT) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_FRI_GET(x) (((uint32_t)(x) & USB_USBSTS_FRI_MASK) >> USB_USBSTS_FRI_SHIFT) + +/* + * PCI (RWC) + * + * PCI + * Port Change Detect - R/WC. + * The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. + * The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + */ +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI_SET(x) (((uint32_t)(x) << USB_USBSTS_PCI_SHIFT) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_PCI_GET(x) (((uint32_t)(x) & USB_USBSTS_PCI_MASK) >> USB_USBSTS_PCI_SHIFT) + +/* + * UEI (RWC) + * + * UEI + * USB Error Interrupt (USBERRINT) - R/WC. + * When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + */ +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI_SET(x) (((uint32_t)(x) << USB_USBSTS_UEI_SHIFT) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_UEI_GET(x) (((uint32_t)(x) & USB_USBSTS_UEI_MASK) >> USB_USBSTS_UEI_SHIFT) + +/* + * UI (RWC) + * + * UI + * USB Interrupt (USBINT) - R/WC. + * This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB + * transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. + * This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when + * the actual number of bytes received was less than the expected number of bytes. + */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI_SET(x) (((uint32_t)(x) << USB_USBSTS_UI_SHIFT) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UI_GET(x) (((uint32_t)(x) & USB_USBSTS_UI_MASK) >> USB_USBSTS_UI_SHIFT) + +/* Bitfield definition for register: USBINTR */ +/* + * TIE1 (RW) + * + * TIE1 + * General Purpose Timer #1 Interrupt Enable + * When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_TIE1_MASK (0x2000000UL) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE1_SHIFT) & USB_USBINTR_TIE1_MASK) +#define USB_USBINTR_TIE1_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE1_MASK) >> USB_USBINTR_TIE1_SHIFT) + +/* + * TIE0 (RW) + * + * TIE0 + * General Purpose Timer #0 Interrupt Enable + * When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_TIE0_MASK (0x1000000UL) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE0_SHIFT) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE0_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE0_MASK) >> USB_USBINTR_TIE0_SHIFT) + +/* + * UPIE (RW) + * + * UPIE + * USB Host Periodic Interrupt Enable + * When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an + * interrupt at the next interrupt threshold. + */ +#define USB_USBINTR_UPIE_MASK (0x80000UL) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UPIE_SHIFT) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_UPIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UPIE_MASK) >> USB_USBINTR_UPIE_SHIFT) + +/* + * UAIE (RW) + * + * UAIE + * USB Host Asynchronous Interrupt Enable + * When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an + * interrupt at the next interrupt threshold. + */ +#define USB_USBINTR_UAIE_MASK (0x40000UL) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UAIE_SHIFT) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UAIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UAIE_MASK) >> USB_USBINTR_UAIE_SHIFT) + +/* + * NAKE (RO) + * + * NAKE + * NAK Interrupt Enable + * When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_NAKE_MASK (0x10000UL) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE_GET(x) (((uint32_t)(x) & USB_USBINTR_NAKE_MASK) >> USB_USBINTR_NAKE_SHIFT) + +/* + * SLE (RW) + * + * SLE + * Sleep Interrupt Enable + * When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. + * Only used in device operation mode. + */ +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE_SET(x) (((uint32_t)(x) << USB_USBINTR_SLE_SHIFT) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_SLE_GET(x) (((uint32_t)(x) & USB_USBINTR_SLE_MASK) >> USB_USBINTR_SLE_SHIFT) + +/* + * SRE (RW) + * + * SRE + * SOF Received Interrupt Enable + * When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE_SET(x) (((uint32_t)(x) << USB_USBINTR_SRE_SHIFT) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SRE_GET(x) (((uint32_t)(x) & USB_USBINTR_SRE_MASK) >> USB_USBINTR_SRE_SHIFT) + +/* + * URE (RW) + * + * URE + * USB Reset Interrupt Enable + * When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in device operation mode. + */ +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE_SET(x) (((uint32_t)(x) << USB_USBINTR_URE_SHIFT) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_URE_GET(x) (((uint32_t)(x) & USB_USBINTR_URE_MASK) >> USB_USBINTR_URE_SHIFT) + +/* + * AAE (RW) + * + * AAE + * Async Advance Interrupt Enable + * When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in host operation mode. + */ +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE_SET(x) (((uint32_t)(x) << USB_USBINTR_AAE_SHIFT) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_AAE_GET(x) (((uint32_t)(x) & USB_USBINTR_AAE_MASK) >> USB_USBINTR_AAE_SHIFT) + +/* + * SEE (RW) + * + * SEE + * System Error Interrupt Enable + * When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in host operation mode. + */ +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE_SET(x) (((uint32_t)(x) << USB_USBINTR_SEE_SHIFT) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_SEE_GET(x) (((uint32_t)(x) & USB_USBINTR_SEE_MASK) >> USB_USBINTR_SEE_SHIFT) + +/* + * FRE (RW) + * + * FRE + * Frame List Rollover Interrupt Enable + * When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. + * Only used in host operation mode. + */ +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE_SET(x) (((uint32_t)(x) << USB_USBINTR_FRE_SHIFT) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_FRE_GET(x) (((uint32_t)(x) & USB_USBINTR_FRE_MASK) >> USB_USBINTR_FRE_SHIFT) + +/* + * PCE (RW) + * + * PCE + * Port Change Detect Interrupt Enable + * When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE_SET(x) (((uint32_t)(x) << USB_USBINTR_PCE_SHIFT) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_PCE_GET(x) (((uint32_t)(x) & USB_USBINTR_PCE_MASK) >> USB_USBINTR_PCE_SHIFT) + +/* + * UEE (RWC) + * + * UEE + * USB Error Interrupt Enable + * When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE_SET(x) (((uint32_t)(x) << USB_USBINTR_UEE_SHIFT) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_UEE_GET(x) (((uint32_t)(x) & USB_USBINTR_UEE_MASK) >> USB_USBINTR_UEE_SHIFT) + +/* + * UE (RW) + * + * UE + * USB Interrupt Enable + * When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE_SET(x) (((uint32_t)(x) << USB_USBINTR_UE_SHIFT) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UE_GET(x) (((uint32_t)(x) & USB_USBINTR_UE_MASK) >> USB_USBINTR_UE_SHIFT) + +/* Bitfield definition for register: FRINDEX */ +/* + * FRINDEX (RW) + * + * FRINDEX + * Frame Index. + * The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. + * The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. + * USBCMD [Frame List Size] Number Elements N + * In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. + * In either mode bits 2:0 indicate the current microframe. + * The bit field values description below is represented as (Frame List Size) Number Elements N. + * 00000000000000 - (1024) 12 + * 00000000000001 - (512) 11 + * 00000000000010 - (256) 10 + * 00000000000011 - (128) 9 + * 00000000000100 - (64) 8 + * 00000000000101 - (32) 7 + * 00000000000110 - (16) 6 + * 00000000000111 - (8) 5 + */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +#define USB_FRINDEX_FRINDEX_SET(x) (((uint32_t)(x) << USB_FRINDEX_FRINDEX_SHIFT) & USB_FRINDEX_FRINDEX_MASK) +#define USB_FRINDEX_FRINDEX_GET(x) (((uint32_t)(x) & USB_FRINDEX_FRINDEX_MASK) >> USB_FRINDEX_FRINDEX_SHIFT) + +/* Bitfield definition for register: DEVICEADDR */ +/* + * USBADR (RW) + * + * USBADR + * Device Address. + * These bits correspond to the USB device address + */ +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000UL) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADR_SHIFT) & USB_DEVICEADDR_USBADR_MASK) +#define USB_DEVICEADDR_USBADR_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADR_MASK) >> USB_DEVICEADDR_USBADR_SHIFT) + +/* + * USBADRA (RW) + * + * USBADRA + * Device Address Advance. Default=0. + * When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. + * After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. + * Hardware will automatically clear this bit on the following conditions: + * 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). + * 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). + * 3) Device Reset occurs (USBADR is reset to 0). + * NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. + * If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000UL) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADRA_SHIFT) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADRA_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADRA_MASK) >> USB_DEVICEADDR_USBADRA_SHIFT) + +/* Bitfield definition for register: PERIODICLISTBASE */ +/* + * BASEADR (RW) + * + * BASEADR + * Base Address (Low). + * These bits correspond to memory address signals [31:12], respectively. + * Only used by the host controller. + */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000UL) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR_SET(x) (((uint32_t)(x) << USB_PERIODICLISTBASE_BASEADR_SHIFT) & USB_PERIODICLISTBASE_BASEADR_MASK) +#define USB_PERIODICLISTBASE_BASEADR_GET(x) (((uint32_t)(x) & USB_PERIODICLISTBASE_BASEADR_MASK) >> USB_PERIODICLISTBASE_BASEADR_SHIFT) + +/* Bitfield definition for register: ASYNCLISTADDR */ +/* + * ASYBASE (RW) + * + * ASYBASE + * Link Pointer Low (LPL). + * These bits correspond to memory address signals [31:5], respectively. This field may only reference a + * Queue Head (QH). + * Only used by the host controller. + */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0UL) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE_SET(x) (((uint32_t)(x) << USB_ASYNCLISTADDR_ASYBASE_SHIFT) & USB_ASYNCLISTADDR_ASYBASE_MASK) +#define USB_ASYNCLISTADDR_ASYBASE_GET(x) (((uint32_t)(x) & USB_ASYNCLISTADDR_ASYBASE_MASK) >> USB_ASYNCLISTADDR_ASYBASE_SHIFT) + +/* Bitfield definition for register: ENDPTLISTADDR */ +/* + * EPBASE (RW) + * + * EPBASE + * Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800UL) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE_SET(x) (((uint32_t)(x) << USB_ENDPTLISTADDR_EPBASE_SHIFT) & USB_ENDPTLISTADDR_EPBASE_MASK) +#define USB_ENDPTLISTADDR_EPBASE_GET(x) (((uint32_t)(x) & USB_ENDPTLISTADDR_EPBASE_MASK) >> USB_ENDPTLISTADDR_EPBASE_SHIFT) + +/* Bitfield definition for register: BURSTSIZE */ +/* + * TXPBURST (RW) + * + * TXPBURST + * Programmable TX Burst Size. + * Default value is determined by TXBURST bits in n_HWTXBUF. + * This register represents the maximum length of a the burst in 32-bit words while moving data from system + * memory to the USB bus. + */ +#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_TXPBURST_SHIFT) & USB_BURSTSIZE_TXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_TXPBURST_MASK) >> USB_BURSTSIZE_TXPBURST_SHIFT) + +/* + * RXPBURST (RW) + * + * RXPBURST + * Programmable RX Burst Size. + * Default value is determined by TXBURST bits in n_HWRXBUF. + * This register represents the maximum length of a the burst in 32-bit words while moving data from the + * USB bus to system memory. + */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_RXPBURST_SHIFT) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_RXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_RXPBURST_MASK) >> USB_BURSTSIZE_RXPBURST_SHIFT) + +/* Bitfield definition for register: TXFILLTUNING */ +/* + * TXFIFOTHRES (RW) + * + * TXFIFOTHRES + * FIFO Burst Threshold. (Read/Write) + * This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. + * The minimum value is 2 and this value should be a low as possible to maximize USB performance. + * A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. + * This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + */ +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000UL) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) >> USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) + +/* + * TXSCHHEALTH (RWC) + * + * TXSCHHEALTH + * Scheduler Health Counter. (Read/Write To Clear) + * Table continues on the next page + * This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. + */ +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) >> USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) + +/* + * TXSCHOH (RW) + * + * TXSCHOH + * Scheduler Overhead. (Read/Write) [Default = 0] + * This register adds an additional fixed offset to the schedule time estimator described above as Tff. + * As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. + * Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. + * The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. + * The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. + * Default value is '08h' for OTG controller core . + */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHOH_SHIFT) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHOH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHOH_MASK) >> USB_TXFILLTUNING_TXSCHOH_SHIFT) + +/* Bitfield definition for register: ENDPTNAK */ +/* + * EPTN (RWC) + * + * EPTN + * TX Endpoint NAK - R/WC. + * Each TX endpoint has 1 bit in this field. The bit is set when the + * device sends a NAK handshake on a received IN token for the corresponding endpoint. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000UL) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) +#define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) + +/* + * EPRN (RWC) + * + * EPRN + * RX Endpoint NAK - R/WC. + * Each RX endpoint has 1 bit in this field. The bit is set when the + * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) + +/* Bitfield definition for register: ENDPTNAKEN */ +/* + * EPTNE (RW) + * + * EPTNE + * TX Endpoint NAK Enable - R/W. + * Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the + * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000UL) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) + +/* + * EPRNE (RW) + * + * EPRNE + * RX Endpoint NAK Enable - R/W. + * Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the + * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. + * Bit [N] - Endpoint #[N], N is 0-7 + */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) + +/* Bitfield definition for register: PORTSC1 */ +/* + * STS (RW) + * + * STS + * Serial Transceiver Select + * 1 Serial Interface Engine is selected + * 0 Parallel Interface signals is selected + * Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. + * When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + */ +#define USB_PORTSC1_STS_MASK (0x20000000UL) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS_SET(x) (((uint32_t)(x) << USB_PORTSC1_STS_SHIFT) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_STS_GET(x) (((uint32_t)(x) & USB_PORTSC1_STS_MASK) >> USB_PORTSC1_STS_SHIFT) + +/* + * PTW (RW) + * + * PTW + * Parallel Transceiver Width + * This bit has no effect if serial interface engine is used. + * 0 - Select the 8-bit UTMI interface [60MHz] + * 1 - Select the 16-bit UTMI interface [30MHz] + */ +#define USB_PORTSC1_PTW_MASK (0x10000000UL) +#define USB_PORTSC1_PTW_SHIFT (28U) +#define USB_PORTSC1_PTW_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTW_SHIFT) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_PTW_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTW_MASK) >> USB_PORTSC1_PTW_SHIFT) + +/* + * PSPD (RO) + * + * PSPD + * Port Speed - Read Only. + * This register field indicates the speed at which the port is operating. + * 00 - Full Speed + * 01 - Low Speed + * 10 - High Speed + * 11 - Undefined + */ +#define USB_PORTSC1_PSPD_MASK (0xC000000UL) +#define USB_PORTSC1_PSPD_SHIFT (26U) +#define USB_PORTSC1_PSPD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT) + +/* + * PFSC (RW) + * + * PFSC + * Port Force Full Speed Connect - Read/Write. Default = 0b. + * When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp + * sequence that allows the port to identify itself as High Speed. + * 0 - Normal operation + * 1 - Forced to full speed + */ +#define USB_PORTSC1_PFSC_MASK (0x1000000UL) +#define USB_PORTSC1_PFSC_SHIFT (24U) +#define USB_PORTSC1_PFSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PFSC_SHIFT) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PFSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PFSC_MASK) >> USB_PORTSC1_PFSC_SHIFT) + +/* + * PHCD (RW) + * + * PHCD + * PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. + * When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY + * clock. + * NOTE: The PHY clock cannot be disabled if it is being used as the system clock. + * In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD + * Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend + * will be cleared automatically when the host initials resume. Before forcing a resume from the device, the + * device controller driver must clear this bit. + * In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put + * into suspend mode or when no downstream device is connected. Low power suspend is completely + * under the control of software. + * 0 - Enable PHY clock + * 1 - Disable PHY clock + */ +#define USB_PORTSC1_PHCD_MASK (0x800000UL) +#define USB_PORTSC1_PHCD_SHIFT (23U) +#define USB_PORTSC1_PHCD_SET(x) (((uint32_t)(x) << USB_PORTSC1_PHCD_SHIFT) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PHCD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PHCD_MASK) >> USB_PORTSC1_PHCD_SHIFT) + +/* + * WKOC (RW) + * + * WKOC + * Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. + * Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. + * This field is zero if Port Power(PORTSC1) is zero. + */ +#define USB_PORTSC1_WKOC_MASK (0x400000UL) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKOC_SHIFT) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_WKOC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKOC_MASK) >> USB_PORTSC1_WKOC_SHIFT) + +/* + * WKDC (RW) + * + * WKDC + * Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables + * the port to be sensitive to device disconnects as wake-up events. + * This field is zero if Port Power(PORTSC1) is zero or in device mode. + */ +#define USB_PORTSC1_WKDC_MASK (0x200000UL) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKDC_SHIFT) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKDC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKDC_MASK) >> USB_PORTSC1_WKDC_SHIFT) + +/* + * WKCN (RW) + * + * WKCN + * Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. + * Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. + * This field is zero if Port Power(PORTSC1) is zero or in device mode. + */ +#define USB_PORTSC1_WKCN_MASK (0x100000UL) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKCN_SHIFT) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKCN_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKCN_MASK) >> USB_PORTSC1_WKCN_SHIFT) + +/* + * PTC (RW) + * + * PTC + * Port Test Control - Read/Write. Default = 0000b. + * Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. + * The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. + * NOTE: Low speed operations are not supported as a peripheral device. + * Any other value than zero indicates that the port is operating in test mode. + * Value Specific Test + * 0000 - TEST_MODE_DISABLE + * 0001 - J_STATE + * 0010 - K_STATE + * 0011 - SE0 (host) / NAK (device) + * 0100 - Packet + * 0101 - FORCE_ENABLE_HS + * 0110 - FORCE_ENABLE_FS + * 0111 - FORCE_ENABLE_LS + * 1000-1111 - Reserved + */ +#define USB_PORTSC1_PTC_MASK (0xF0000UL) +#define USB_PORTSC1_PTC_SHIFT (16U) +#define USB_PORTSC1_PTC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTC_SHIFT) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_PTC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTC_MASK) >> USB_PORTSC1_PTC_SHIFT) + +/* + * PP (RW) + * + * PP + * Port Power (PP)-Read/Write or Read Only. + * The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: + * PPC + * PP Operation + * 0 + * 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. + * 1 + * 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. + * When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). + * This feature is implemented in all controller cores (PPC = 1). + */ +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP_SET(x) (((uint32_t)(x) << USB_PORTSC1_PP_SHIFT) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PP_GET(x) (((uint32_t)(x) & USB_PORTSC1_PP_MASK) >> USB_PORTSC1_PP_SHIFT) + +/* + * LS (RO) + * + * LS + * Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal + * lines. + * In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because + * the port controller state machine and the port routing manage the connection of LS and FS. + * In device mode, the use of linestate by the device controller driver is not necessary. + * The encoding of the bits are: + * Bits [11:10] Meaning + * 00 - SE0 + * 01 - K-state + * 10 - J-state + * 11 - Undefined + */ +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +#define USB_PORTSC1_LS_GET(x) (((uint32_t)(x) & USB_PORTSC1_LS_MASK) >> USB_PORTSC1_LS_SHIFT) + +/* + * HSP (RO) + * + * HSP + * High-Speed Port - Read Only. Default = 0b. + * When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the + * host/device connected to the port is not in a high-speed mode. + * NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + */ +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_HSP_MASK) >> USB_PORTSC1_HSP_SHIFT) + +/* + * PR (RW) + * + * PR + * Port Reset - Read/Write or Read Only. Default = 0b. + * In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. + * When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. + * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. + * In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + */ +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR_SET(x) (((uint32_t)(x) << USB_PORTSC1_PR_SHIFT) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_PR_GET(x) (((uint32_t)(x) & USB_PORTSC1_PR_MASK) >> USB_PORTSC1_PR_SHIFT) + +/* + * SUSP (RW) + * + * SUSP + * Suspend - Read/Write or Read Only. Default = 0b. + * 1=Port in suspend state. 0=Port not in suspend state. + * In Host Mode: Read/Write. + * Port Enabled Bit and Suspend bit of this register define the port states as follows: + * Bits [Port Enabled, Suspend] Port State + * 0x Disable + * 10 Enable + * 11 Suspend + * When in suspend state, downstream propagation of data is blocked on this port, except for port reset. + * The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. + * The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. + * If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: Read Only. + * In device mode this bit is a read only status bit. + */ +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP_SET(x) (((uint32_t)(x) << USB_PORTSC1_SUSP_SHIFT) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_SUSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_SUSP_MASK) >> USB_PORTSC1_SUSP_SHIFT) + +/* + * FPR (RW) + * + * FPR + * Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. + * In Host Mode: + * Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. + * When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. + * This bit will automatically change to zero after the resume sequence is complete. + * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. + * Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. + * The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. + * Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * This bit is not-EHCI compatible. + * In Device mode: + * After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. + * The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. + * The bit will be cleared when the device returns to normal operation. + * Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + */ +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR_SET(x) (((uint32_t)(x) << USB_PORTSC1_FPR_SHIFT) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_FPR_GET(x) (((uint32_t)(x) & USB_PORTSC1_FPR_MASK) >> USB_PORTSC1_FPR_SHIFT) + +/* + * OCC (RW) + * + * OCC + * Over-current Change-R/WC. Default=0. + * This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + */ +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC_SET(x) (((uint32_t)(x) << USB_PORTSC1_OCC_SHIFT) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_OCC_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCC_MASK) >> USB_PORTSC1_OCC_SHIFT) + +/* + * OCA (RO) + * + * OCA + * Over-current Active-Read Only. Default 0. + * This bit will automatically transition from one to zero when the over current condition is removed. + * 0 - This port does not have an over-current condition. + * 1 - This port currently has an over-current condition + */ +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +#define USB_PORTSC1_OCA_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCA_MASK) >> USB_PORTSC1_OCA_SHIFT) + +/* + * PEC (RWC) + * + * PEC + * Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. + * In Host Mode: + * For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). + * Software clears this by writing a one to it. + * This field is zero if Port Power(PORTSC1) is zero. + * In Device mode: + * The device port is always enabled, so this bit is always '0b'. + */ +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PEC_SHIFT) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_PEC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PEC_MASK) >> USB_PORTSC1_PEC_SHIFT) + +/* + * PE (RWC) + * + * PE + * Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. + * In Host Mode: + * Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. + * Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. + * Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. + * When the port is disabled, (0b) downstream propagation of data is blocked except for reset. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: + * The device port is always enabled, so this bit is always '1b'. + */ +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE_SET(x) (((uint32_t)(x) << USB_PORTSC1_PE_SHIFT) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PE_GET(x) (((uint32_t)(x) & USB_PORTSC1_PE_MASK) >> USB_PORTSC1_PE_SHIFT) + +/* + * CSC (RWC) + * + * CSC + * Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. + * In Host Mode: + * Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. + * For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: + * This bit is undefined in device controller mode. + */ +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_CSC_SHIFT) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_CSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_CSC_MASK) >> USB_PORTSC1_CSC_SHIFT) + +/* + * CCS (RWC) + * + * CCS + * Current Connect Status-Read Only. + * In Host Mode: + * 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. + * This field is zero if Port Power(PORTSC1) is zero in host mode. + * In Device Mode: + * 1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. + */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS_SET(x) (((uint32_t)(x) << USB_PORTSC1_CCS_SHIFT) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CCS_GET(x) (((uint32_t)(x) & USB_PORTSC1_CCS_MASK) >> USB_PORTSC1_CCS_SHIFT) + +/* Bitfield definition for register: OTGSC */ +/* + * ASVIE (RW) + * + * ASVIE + * A Session Valid Interrupt Enable - Read/Write. + */ +#define USB_OTGSC_ASVIE_MASK (0x4000000UL) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIE_SHIFT) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_ASVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIE_MASK) >> USB_OTGSC_ASVIE_SHIFT) + +/* + * AVVIE (RW) + * + * AVVIE + * A VBus Valid Interrupt Enable - Read/Write. + * Setting this bit enables the A VBus valid interrupt. + */ +#define USB_OTGSC_AVVIE_MASK (0x2000000UL) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIE_SHIFT) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_AVVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIE_MASK) >> USB_OTGSC_AVVIE_SHIFT) + +/* + * IDIE (RW) + * + * IDIE + * USB ID Interrupt Enable - Read/Write. + * Setting this bit enables the USB ID interrupt. + */ +#define USB_OTGSC_IDIE_MASK (0x1000000UL) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIE_SHIFT) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_IDIE_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIE_MASK) >> USB_OTGSC_IDIE_SHIFT) + +/* + * ASVIS (RWC) + * + * ASVIS + * A Session Valid Interrupt Status - Read/Write to Clear. + * This bit is set when VBus has either risen above or fallen below the A session valid threshold. + * Software must write a one to clear this bit. + */ +#define USB_OTGSC_ASVIS_MASK (0x40000UL) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIS_SHIFT) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_ASVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIS_MASK) >> USB_OTGSC_ASVIS_SHIFT) + +/* + * AVVIS (RWC) + * + * AVVIS + * A VBus Valid Interrupt Status - Read/Write to Clear. + * This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. + * Software must write a one to clear this bit. + */ +#define USB_OTGSC_AVVIS_MASK (0x20000UL) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIS_SHIFT) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_AVVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIS_MASK) >> USB_OTGSC_AVVIS_SHIFT) + +/* + * IDIS (RWC) + * + * IDIS + * USB ID Interrupt Status - Read/Write. + * This bit is set when a change on the ID input has been detected. + * Software must write a one to clear this bit. + */ +#define USB_OTGSC_IDIS_MASK (0x10000UL) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIS_SHIFT) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_IDIS_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIS_MASK) >> USB_OTGSC_IDIS_SHIFT) + +/* + * ASV (RO) + * + * ASV + * A Session Valid - Read Only. + * Indicates VBus is above the A session valid threshold. + */ +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV_GET(x) (((uint32_t)(x) & USB_OTGSC_ASV_MASK) >> USB_OTGSC_ASV_SHIFT) + +/* + * AVV (RO) + * + * AVV + * A VBus Valid - Read Only. + * Indicates VBus is above the A VBus valid threshold. + */ +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV_GET(x) (((uint32_t)(x) & USB_OTGSC_AVV_MASK) >> USB_OTGSC_AVV_SHIFT) + +/* + * ID (RO) + * + * ID + * USB ID - Read Only. + * 0 = A device, 1 = B device + */ +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID_GET(x) (((uint32_t)(x) & USB_OTGSC_ID_MASK) >> USB_OTGSC_ID_SHIFT) + +/* + * IDPU (RW) + * + * IDPU + * ID Pullup - Read/Write + * This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input + * will not be sampled. + */ +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU_SET(x) (((uint32_t)(x) << USB_OTGSC_IDPU_SHIFT) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_IDPU_GET(x) (((uint32_t)(x) & USB_OTGSC_IDPU_MASK) >> USB_OTGSC_IDPU_SHIFT) + +/* + * VC (RW) + * + * VC + * VBUS Charge - Read/Write. + * Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + */ +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC_SET(x) (((uint32_t)(x) << USB_OTGSC_VC_SHIFT) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_VC_GET(x) (((uint32_t)(x) & USB_OTGSC_VC_MASK) >> USB_OTGSC_VC_SHIFT) + +/* + * VD (RW) + * + * VD + * VBUS_Discharge - Read/Write. + * Setting this bit causes VBus to discharge through a resistor. + */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD_SET(x) (((uint32_t)(x) << USB_OTGSC_VD_SHIFT) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VD_GET(x) (((uint32_t)(x) & USB_OTGSC_VD_MASK) >> USB_OTGSC_VD_SHIFT) + +/* Bitfield definition for register: USBMODE */ +/* + * SDIS (RW) + * + * SDIS + * Stream Disable Mode. (0 - Inactive [default]; 1 - Active) + * Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. + * This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. + * Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. + * Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. + * NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for + * the scheduler when using this feature. + * NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + */ +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS_SET(x) (((uint32_t)(x) << USB_USBMODE_SDIS_SHIFT) & USB_USBMODE_SDIS_MASK) +#define USB_USBMODE_SDIS_GET(x) (((uint32_t)(x) & USB_USBMODE_SDIS_MASK) >> USB_USBMODE_SDIS_SHIFT) + +/* + * SLOM (RW) + * + * SLOM + * Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . + * 0 - Setup Lockouts On (default); + * 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + */ +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +#define USB_USBMODE_SLOM_SET(x) (((uint32_t)(x) << USB_USBMODE_SLOM_SHIFT) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SLOM_GET(x) (((uint32_t)(x) & USB_USBMODE_SLOM_MASK) >> USB_USBMODE_SLOM_SHIFT) + +/* + * ES (RW) + * + * ES + * Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the + * host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected + * by the value of this bit because they are based upon the 32-bit word. + * Bit Meaning + * 0 - Little Endian [Default] + * 1 - Big Endian + */ +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +#define USB_USBMODE_ES_SET(x) (((uint32_t)(x) << USB_USBMODE_ES_SHIFT) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_ES_GET(x) (((uint32_t)(x) & USB_USBMODE_ES_MASK) >> USB_USBMODE_ES_SHIFT) + +/* + * CM (RW) + * + * CM + * Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only + * implementations. For those designs that contain both host & device capability, the controller defaults to + * an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ + * device controllers, this register can only be written once after reset. If it is necessary to switch modes, + * software must reset the controller by writing to the RESET bit in the USBCMD register before + * reprogramming this register. + * For OTG controller core, reset value is '00b'. + * 00 - Idle [Default for combination host/device] + * 01 - Reserved + * 10 - Device Controller [Default for device only controller] + * 11 - Host Controller [Default for host only controller] + */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +#define USB_USBMODE_CM_SET(x) (((uint32_t)(x) << USB_USBMODE_CM_SHIFT) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_CM_GET(x) (((uint32_t)(x) & USB_USBMODE_CM_MASK) >> USB_USBMODE_CM_SHIFT) + +/* Bitfield definition for register: ENDPTSETUPSTAT */ +/* + * ENDPTSETUPSTAT (RWC) + * + * ENDPTSETUPSTAT + * Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. + * Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. + * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. + * This register is only used in device mode. + */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) + +/* Bitfield definition for register: ENDPTPRIME */ +/* + * PETB (RWS) + * + * PETB + * Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a + * buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. + * Software should write a one to the corresponding bit when posting a new transfer descriptor to an + * endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor + * from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated + * endpoint(s) is (are) successfully primed. + * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD + * is retired, and the dQH is updated. + * PETB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000UL) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) +#define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) + +/* + * PERB (RWS) + * + * PERB + * Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. + * Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. + * Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. + * Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. + * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD + * is retired, and the dQH is updated. + * PERB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) + +/* Bitfield definition for register: ENDPTFLUSH */ +/* + * FETB (RWS) + * + * FETB + * Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. + * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. + * Hardware clears this register after the endpoint flush operation is successful. + * FETB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000UL) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) +#define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) + +/* + * FERB (RWS) + * + * FERB + * Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. + * Hardware clears this register after the endpoint flush operation is successful. + * FERB[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) + +/* Bitfield definition for register: ENDPTSTAT */ +/* + * ETBR (RO) + * + * ETBR + * Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. + * This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. + * There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. + * This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. + * Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. + * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. + * ETBR[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000UL) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) + +/* + * ERBR (RO) + * + * ERBR + * Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective + * endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a + * corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the + * ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB + * traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the + * USB DMA system, or through the ENDPTFLUSH register. + * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations + * when a dTD is retired, and the dQH is updated. + * ERBR[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) + +/* Bitfield definition for register: ENDPTCOMPLETE */ +/* + * ETCE (RWC) + * + * ETCE + * Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. + * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. + * ETCE[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000UL) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) + +/* + * ERCE (RWC) + * + * ERCE + * Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred + * and software should read the corresponding endpoint queue to determine the transfer status. If the + * corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the + * USBINT . Writing one clears the corresponding bit in this register. + * ERCE[N] - Endpoint #N, N is in 0..7 + */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) + +/* Bitfield definition for register array: ENDPTCTRL */ +/* + * TXE (RW) + * + * TXE + * TX Endpoint Enable + * 0 Disabled [Default] + * 1 Enabled + * An Endpoint should be enabled only after it has been configured. + */ +#define USB_ENDPTCTRL_TXE_MASK (0x800000UL) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXE_SHIFT) & USB_ENDPTCTRL_TXE_MASK) +#define USB_ENDPTCTRL_TXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXE_MASK) >> USB_ENDPTCTRL_TXE_SHIFT) + +/* + * TXR (WS) + * + * TXR + * TX Data Toggle Reset (WS) + * Write 1 - Reset PID Sequence + * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order + * to synchronize the data PID's between the Host and device. + */ +#define USB_ENDPTCTRL_TXR_MASK (0x400000UL) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXR_SHIFT) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXR_MASK) >> USB_ENDPTCTRL_TXR_SHIFT) + +/* + * TXT (RW) + * + * TXT + * TX Endpoint Type - Read/Write + * 00 Control + * 01 Isochronous + * 10 Bulk + * 11 Interrupt + */ +#define USB_ENDPTCTRL_TXT_MASK (0xC0000UL) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXT_SHIFT) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXT_MASK) >> USB_ENDPTCTRL_TXT_SHIFT) + +/* + * TXS (RW) + * + * TXS + * TX Endpoint Stall - Read/Write + * 0 End Point OK + * 1 End Point Stalled + * This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. + * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. + * This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. + * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. + * In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: + * continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + */ +#define USB_ENDPTCTRL_TXS_MASK (0x10000UL) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXS_SHIFT) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXS_MASK) >> USB_ENDPTCTRL_TXS_SHIFT) + +/* + * RXE (RW) + * + * RXE + * RX Endpoint Enable + * 0 Disabled [Default] + * 1 Enabled + * An Endpoint should be enabled only after it has been configured. + */ +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXE_SHIFT) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_RXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXE_MASK) >> USB_ENDPTCTRL_RXE_SHIFT) + +/* + * RXR (WS) + * + * RXR + * RX Data Toggle Reset (WS) + * Write 1 - Reset PID Sequence + * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order + * to synchronize the data PID's between the host and device. + */ +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXR_SHIFT) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXR_MASK) >> USB_ENDPTCTRL_RXR_SHIFT) + +/* + * RXT (RW) + * + * RXT + * RX Endpoint Type - Read/Write + * 00 Control + * 01 Isochronous + * 10 Bulk + * 11 Interrupt + */ +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXT_SHIFT) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXT_MASK) >> USB_ENDPTCTRL_RXT_SHIFT) + +/* + * RXS (RW) + * + * RXS + * RX Endpoint Stall - Read/Write + * 0 End Point OK. [Default] + * 1 End Point Stalled + * This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control + * Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit + * is cleared. + * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This + * control will continue to STALL until this bit is either cleared by software or automatically cleared as above + * for control endpoints. + * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the + * ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it + * is unlikely the DCD software will observe this delay. However, should the DCD observe that the + * stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit + * until it is set or until a new setup has been received by checking the associated endptsetupstat + * Bit. + */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXS_SHIFT) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXS_MASK) >> USB_ENDPTCTRL_RXS_SHIFT) + +/* Bitfield definition for register: OTG_CTRL0 */ +/* + * OTG_WKDPDMCHG_EN (RW) + * + */ +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK (0x2000000UL) +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT (25U) +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) +#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) >> USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) + +/* + * AUTORESUME_EN (RW) + * + */ +#define USB_OTG_CTRL0_AUTORESUME_EN_MASK (0x80000UL) +#define USB_OTG_CTRL0_AUTORESUME_EN_SHIFT (19U) +#define USB_OTG_CTRL0_AUTORESUME_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) +#define USB_OTG_CTRL0_AUTORESUME_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) >> USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) + +/* + * OTG_VBUS_WAKEUP_EN (RW) + * + */ +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK (0x20000UL) +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT (17U) +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) +#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) + +/* + * OTG_ID_WAKEUP_EN (RW) + * + */ +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK (0x10000UL) +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT (16U) +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) +#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) + +/* + * OTG_VBUS_SOURCE_SEL (RW) + * + */ +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK (0x2000U) +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT (13U) +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) +#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) >> USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) + +/* + * OTG_UTMI_SUSPENDM_SW (RW) + * + * default 0 for naneng usbphy + */ +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK (0x1000U) +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT (12U) +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) +#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) + +/* + * OTG_UTMI_RESET_SW (RW) + * + * default 1 for naneng usbphy + */ +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK (0x800U) +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT (11U) +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) +#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) + +/* + * OTG_WAKEUP_INT_ENABLE (RW) + * + */ +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK (0x400U) +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT (10U) +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) +#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) >> USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) + +/* + * OTG_POWER_MASK (RW) + * + */ +#define USB_OTG_CTRL0_OTG_POWER_MASK_MASK (0x200U) +#define USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT (9U) +#define USB_OTG_CTRL0_OTG_POWER_MASK_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) +#define USB_OTG_CTRL0_OTG_POWER_MASK_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) >> USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) + +/* + * OTG_OVER_CUR_POL (RW) + * + */ +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK (0x100U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT (8U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) +#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) + +/* + * OTG_OVER_CUR_DIS (RW) + * + */ +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK (0x80U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT (7U) +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) +#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) + +/* + * SER_MODE_SUSPEND_EN (RW) + * + * for naneng usbphy, only switch to serial mode when suspend + */ +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK (0x10U) +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT (4U) +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) +#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) >> USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) + +/* Bitfield definition for register: PHY_CTRL0 */ +/* + * GPIO_ID_SEL_N (RW) + * + */ +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK (0x2000000UL) +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT (25U) +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) +#define USB_PHY_CTRL0_GPIO_ID_SEL_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) >> USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) + +/* + * ID_DIG_OVERRIDE (RW) + * + */ +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK (0x4000U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT (14U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) + +/* + * SESS_VALID_OVERRIDE (RW) + * + */ +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK (0x2000U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT (13U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) + +/* + * VBUS_VALID_OVERRIDE (RW) + * + */ +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK (0x1000U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT (12U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) + +/* + * ID_DIG_OVERRIDE_EN (RW) + * + */ +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK (0x4U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT (2U) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) +#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) + +/* + * SESS_VALID_OVERRIDE_EN (RW) + * + */ +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK (0x2U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT (1U) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) +#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) + +/* + * VBUS_VALID_OVERRIDE_EN (RW) + * + */ +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK (0x1U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT (0U) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) +#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) + +/* Bitfield definition for register: PHY_CTRL1 */ +/* + * UTMI_CFG_RST_N (RW) + * + */ +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK (0x100000UL) +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT (20U) +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) +#define USB_PHY_CTRL1_UTMI_CFG_RST_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) >> USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) + +/* + * UTMI_OTG_SUSPENDM (RW) + * + * OTG suspend, not utmi_suspendm + */ +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK (0x2U) +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT (1U) +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) +#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) >> USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) + +/* Bitfield definition for register: TOP_STATUS */ +/* + * WAKEUP_INT_STATUS (RW) + * + */ +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK (0x80000000UL) +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT (31U) +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SET(x) (((uint32_t)(x) << USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) +#define USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(x) (((uint32_t)(x) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) >> USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) + +/* Bitfield definition for register: PHY_STATUS */ +/* + * UTMI_CLK_VALID (RW) + * + */ +#define USB_PHY_STATUS_UTMI_CLK_VALID_MASK (0x80000000UL) +#define USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT (31U) +#define USB_PHY_STATUS_UTMI_CLK_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) +#define USB_PHY_STATUS_UTMI_CLK_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) >> USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) + +/* + * LINE_STATE (RW) + * + */ +#define USB_PHY_STATUS_LINE_STATE_MASK (0xC0U) +#define USB_PHY_STATUS_LINE_STATE_SHIFT (6U) +#define USB_PHY_STATUS_LINE_STATE_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_LINE_STATE_SHIFT) & USB_PHY_STATUS_LINE_STATE_MASK) +#define USB_PHY_STATUS_LINE_STATE_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_LINE_STATE_MASK) >> USB_PHY_STATUS_LINE_STATE_SHIFT) + +/* + * HOST_DISCONNECT (RW) + * + */ +#define USB_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) +#define USB_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) +#define USB_PHY_STATUS_HOST_DISCONNECT_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) +#define USB_PHY_STATUS_HOST_DISCONNECT_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) >> USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) + +/* + * ID_DIG (RW) + * + */ +#define USB_PHY_STATUS_ID_DIG_MASK (0x10U) +#define USB_PHY_STATUS_ID_DIG_SHIFT (4U) +#define USB_PHY_STATUS_ID_DIG_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_ID_DIG_SHIFT) & USB_PHY_STATUS_ID_DIG_MASK) +#define USB_PHY_STATUS_ID_DIG_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_ID_DIG_MASK) >> USB_PHY_STATUS_ID_DIG_SHIFT) + +/* + * UTMI_SESS_VALID (RW) + * + */ +#define USB_PHY_STATUS_UTMI_SESS_VALID_MASK (0x4U) +#define USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT (2U) +#define USB_PHY_STATUS_UTMI_SESS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) +#define USB_PHY_STATUS_UTMI_SESS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) >> USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) + +/* + * VBUS_VALID (RW) + * + */ +#define USB_PHY_STATUS_VBUS_VALID_MASK (0x1U) +#define USB_PHY_STATUS_VBUS_VALID_SHIFT (0U) +#define USB_PHY_STATUS_VBUS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_VBUS_VALID_SHIFT) & USB_PHY_STATUS_VBUS_VALID_MASK) +#define USB_PHY_STATUS_VBUS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_VBUS_VALID_MASK) >> USB_PHY_STATUS_VBUS_VALID_SHIFT) + + + +/* ENDPTCTRL register group index macro definition */ +#define USB_ENDPTCTRL_ENDPTCTRL0 (0UL) +#define USB_ENDPTCTRL_ENDPTCTRL1 (1UL) +#define USB_ENDPTCTRL_ENDPTCTRL2 (2UL) +#define USB_ENDPTCTRL_ENDPTCTRL3 (3UL) +#define USB_ENDPTCTRL_ENDPTCTRL4 (4UL) +#define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) +#define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) +#define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) + + +#endif /* HPM_USB_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_vad_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_vad_regs.h new file mode 100644 index 0000000000..624f748fd7 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_vad_regs.h @@ -0,0 +1,441 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_VAD_H +#define HPM_VAD_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: Control Register */ + __RW uint32_t FILTCTRL; /* 0x4: Filter Control Register */ + __RW uint32_t DEC_CTRL0; /* 0x8: Decision Control Register 0 */ + __RW uint32_t DEC_CTRL1; /* 0xC: Decision Control Register 1 */ + __RW uint32_t DEC_CTRL2; /* 0x10: Decision Control Register 2 */ + __R uint8_t RESERVED0[4]; /* 0x14 - 0x17: Reserved */ + __RW uint32_t ST; /* 0x18: Status */ + __RW uint32_t OFIFO; /* 0x1C: Out FIFO */ + __RW uint32_t RUN; /* 0x20: Run Command Register */ + __RW uint32_t OFIFO_CTRL; /* 0x24: Out FIFO Control Register */ + __RW uint32_t CIC_CFG; /* 0x28: CIC Configuration Register */ + __R uint8_t RESERVED1[116]; /* 0x2C - 0x9F: Reserved */ + __R uint32_t COEF[1]; /* 0xA0: Short Time Energy Register */ +} VAD_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * CAPT_DLY (RW) + * + * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV + */ +#define VAD_CTRL_CAPT_DLY_MASK (0xF000000UL) +#define VAD_CTRL_CAPT_DLY_SHIFT (24U) +#define VAD_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << VAD_CTRL_CAPT_DLY_SHIFT) & VAD_CTRL_CAPT_DLY_MASK) +#define VAD_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & VAD_CTRL_CAPT_DLY_MASK) >> VAD_CTRL_CAPT_DLY_SHIFT) + +/* + * PDM_CLK_HFDIV (RW) + * + * The clock divider will work at least 4. + * 0: div-by-2, + * 1: div-by-4 + * . . . + * n: div-by-2*(n+1) + */ +#define VAD_CTRL_PDM_CLK_HFDIV_MASK (0xF00000UL) +#define VAD_CTRL_PDM_CLK_HFDIV_SHIFT (20U) +#define VAD_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_HFDIV_SHIFT) & VAD_CTRL_PDM_CLK_HFDIV_MASK) +#define VAD_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_HFDIV_MASK) >> VAD_CTRL_PDM_CLK_HFDIV_SHIFT) + +/* + * VAD_IE (RW) + * + * VAD event interrupt enable + */ +#define VAD_CTRL_VAD_IE_MASK (0x40000UL) +#define VAD_CTRL_VAD_IE_SHIFT (18U) +#define VAD_CTRL_VAD_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_VAD_IE_SHIFT) & VAD_CTRL_VAD_IE_MASK) +#define VAD_CTRL_VAD_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_VAD_IE_MASK) >> VAD_CTRL_VAD_IE_SHIFT) + +/* + * OFIFO_AV_IE (RW) + * + * OFIFO data available interrupt enable + */ +#define VAD_CTRL_OFIFO_AV_IE_MASK (0x20000UL) +#define VAD_CTRL_OFIFO_AV_IE_SHIFT (17U) +#define VAD_CTRL_OFIFO_AV_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_OFIFO_AV_IE_SHIFT) & VAD_CTRL_OFIFO_AV_IE_MASK) +#define VAD_CTRL_OFIFO_AV_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_OFIFO_AV_IE_MASK) >> VAD_CTRL_OFIFO_AV_IE_SHIFT) + +/* + * MEMBUF_EMPTY_IE (RW) + * + * Buf empty interrupt enable + */ +#define VAD_CTRL_MEMBUF_EMPTY_IE_MASK (0x10000UL) +#define VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT (16U) +#define VAD_CTRL_MEMBUF_EMPTY_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) +#define VAD_CTRL_MEMBUF_EMPTY_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) >> VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) + +/* + * OFIFO_OVFL_ERR_IE (RW) + * + * OFIFO overflow error interrupt enable + */ +#define VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x8000U) +#define VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (15U) +#define VAD_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) +#define VAD_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) + +/* + * IIR_OVLD_ERR_IE (RW) + * + * IIR overload error interrupt enable + */ +#define VAD_CTRL_IIR_OVLD_ERR_IE_MASK (0x4000U) +#define VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT (14U) +#define VAD_CTRL_IIR_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) +#define VAD_CTRL_IIR_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) >> VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) + +/* + * IIR_OVFL_ERR_IE (RW) + * + * IIR overflow error interrupt enable + */ +#define VAD_CTRL_IIR_OVFL_ERR_IE_MASK (0x2000U) +#define VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT (13U) +#define VAD_CTRL_IIR_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) +#define VAD_CTRL_IIR_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) >> VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) + +/* + * CIC_OVLD_ERR_IE (RW) + * + * CIC overload Interrupt Enable + */ +#define VAD_CTRL_CIC_OVLD_ERR_IE_MASK (0x1000U) +#define VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT (12U) +#define VAD_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) +#define VAD_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) >> VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) + +/* + * CIC_SAT_ERR_IE (RW) + * + * CIC saturation Interrupt Enable + */ +#define VAD_CTRL_CIC_SAT_ERR_IE_MASK (0x800U) +#define VAD_CTRL_CIC_SAT_ERR_IE_SHIFT (11U) +#define VAD_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) +#define VAD_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) >> VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) + +/* + * MEMBUF_DISABLE (RW) + * + * asserted to disable membuf + */ +#define VAD_CTRL_MEMBUF_DISABLE_MASK (0x200U) +#define VAD_CTRL_MEMBUF_DISABLE_SHIFT (9U) +#define VAD_CTRL_MEMBUF_DISABLE_SET(x) (((uint32_t)(x) << VAD_CTRL_MEMBUF_DISABLE_SHIFT) & VAD_CTRL_MEMBUF_DISABLE_MASK) +#define VAD_CTRL_MEMBUF_DISABLE_GET(x) (((uint32_t)(x) & VAD_CTRL_MEMBUF_DISABLE_MASK) >> VAD_CTRL_MEMBUF_DISABLE_SHIFT) + +/* + * FIFO_THRSH (RW) + * + * OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) + */ +#define VAD_CTRL_FIFO_THRSH_MASK (0x1E0U) +#define VAD_CTRL_FIFO_THRSH_SHIFT (5U) +#define VAD_CTRL_FIFO_THRSH_SET(x) (((uint32_t)(x) << VAD_CTRL_FIFO_THRSH_SHIFT) & VAD_CTRL_FIFO_THRSH_MASK) +#define VAD_CTRL_FIFO_THRSH_GET(x) (((uint32_t)(x) & VAD_CTRL_FIFO_THRSH_MASK) >> VAD_CTRL_FIFO_THRSH_SHIFT) + +/* + * PDM_CLK_DIV_BYPASS (RW) + * + * asserted to bypass the pdm clock divider + */ +#define VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x10U) +#define VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (4U) +#define VAD_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) +#define VAD_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) + +/* + * PDM_CLK_OE (RW) + * + * pdm_clk_output_en + */ +#define VAD_CTRL_PDM_CLK_OE_MASK (0x8U) +#define VAD_CTRL_PDM_CLK_OE_SHIFT (3U) +#define VAD_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_OE_SHIFT) & VAD_CTRL_PDM_CLK_OE_MASK) +#define VAD_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_OE_MASK) >> VAD_CTRL_PDM_CLK_OE_SHIFT) + +/* + * CH_POL (RW) + * + * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. + */ +#define VAD_CTRL_CH_POL_MASK (0x6U) +#define VAD_CTRL_CH_POL_SHIFT (1U) +#define VAD_CTRL_CH_POL_SET(x) (((uint32_t)(x) << VAD_CTRL_CH_POL_SHIFT) & VAD_CTRL_CH_POL_MASK) +#define VAD_CTRL_CH_POL_GET(x) (((uint32_t)(x) & VAD_CTRL_CH_POL_MASK) >> VAD_CTRL_CH_POL_SHIFT) + +/* + * CHNUM (RW) + * + * the number of channels to be stored in buffer. Asserted to enable 2 channels. + */ +#define VAD_CTRL_CHNUM_MASK (0x1U) +#define VAD_CTRL_CHNUM_SHIFT (0U) +#define VAD_CTRL_CHNUM_SET(x) (((uint32_t)(x) << VAD_CTRL_CHNUM_SHIFT) & VAD_CTRL_CHNUM_MASK) +#define VAD_CTRL_CHNUM_GET(x) (((uint32_t)(x) & VAD_CTRL_CHNUM_MASK) >> VAD_CTRL_CHNUM_SHIFT) + +/* Bitfield definition for register: FILTCTRL */ +/* + * DECRATIO (RW) + * + * the decimation ratio of iir after CIC -1 + * 2: means dec-by-3 + */ +#define VAD_FILTCTRL_DECRATIO_MASK (0x700U) +#define VAD_FILTCTRL_DECRATIO_SHIFT (8U) +#define VAD_FILTCTRL_DECRATIO_SET(x) (((uint32_t)(x) << VAD_FILTCTRL_DECRATIO_SHIFT) & VAD_FILTCTRL_DECRATIO_MASK) +#define VAD_FILTCTRL_DECRATIO_GET(x) (((uint32_t)(x) & VAD_FILTCTRL_DECRATIO_MASK) >> VAD_FILTCTRL_DECRATIO_SHIFT) + +/* + * IIR_SLOT_EN (RW) + * + * IIR slot enable + */ +#define VAD_FILTCTRL_IIR_SLOT_EN_MASK (0xFFU) +#define VAD_FILTCTRL_IIR_SLOT_EN_SHIFT (0U) +#define VAD_FILTCTRL_IIR_SLOT_EN_SET(x) (((uint32_t)(x) << VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) +#define VAD_FILTCTRL_IIR_SLOT_EN_GET(x) (((uint32_t)(x) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) >> VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) + +/* Bitfield definition for register: DEC_CTRL0 */ +/* + * NOISE_TOL (RW) + * + * the value of amplitude for noise determination when calculationg ZCR + */ +#define VAD_DEC_CTRL0_NOISE_TOL_MASK (0xFFFF0000UL) +#define VAD_DEC_CTRL0_NOISE_TOL_SHIFT (16U) +#define VAD_DEC_CTRL0_NOISE_TOL_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_NOISE_TOL_SHIFT) & VAD_DEC_CTRL0_NOISE_TOL_MASK) +#define VAD_DEC_CTRL0_NOISE_TOL_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_NOISE_TOL_MASK) >> VAD_DEC_CTRL0_NOISE_TOL_SHIFT) + +/* + * BLK_CFG (RW) + * + * asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks + */ +#define VAD_DEC_CTRL0_BLK_CFG_MASK (0x200U) +#define VAD_DEC_CTRL0_BLK_CFG_SHIFT (9U) +#define VAD_DEC_CTRL0_BLK_CFG_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_BLK_CFG_SHIFT) & VAD_DEC_CTRL0_BLK_CFG_MASK) +#define VAD_DEC_CTRL0_BLK_CFG_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_BLK_CFG_MASK) >> VAD_DEC_CTRL0_BLK_CFG_SHIFT) + +/* + * SUBBLK_LEN (RW) + * + * length of sub-block + */ +#define VAD_DEC_CTRL0_SUBBLK_LEN_MASK (0x1FFU) +#define VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT (0U) +#define VAD_DEC_CTRL0_SUBBLK_LEN_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) +#define VAD_DEC_CTRL0_SUBBLK_LEN_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) >> VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) + +/* Bitfield definition for register: DEC_CTRL1 */ +/* + * ZCR_HIGH (RW) + * + * ZCR high limit + */ +#define VAD_DEC_CTRL1_ZCR_HIGH_MASK (0x3FF800UL) +#define VAD_DEC_CTRL1_ZCR_HIGH_SHIFT (11U) +#define VAD_DEC_CTRL1_ZCR_HIGH_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) +#define VAD_DEC_CTRL1_ZCR_HIGH_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) >> VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) + +/* + * ZCR_LOW (RW) + * + * ZCR low limit + */ +#define VAD_DEC_CTRL1_ZCR_LOW_MASK (0x7FFU) +#define VAD_DEC_CTRL1_ZCR_LOW_SHIFT (0U) +#define VAD_DEC_CTRL1_ZCR_LOW_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_LOW_SHIFT) & VAD_DEC_CTRL1_ZCR_LOW_MASK) +#define VAD_DEC_CTRL1_ZCR_LOW_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_LOW_MASK) >> VAD_DEC_CTRL1_ZCR_LOW_SHIFT) + +/* Bitfield definition for register: DEC_CTRL2 */ +/* + * AMP_HIGH (RW) + * + * amplitude high limit + */ +#define VAD_DEC_CTRL2_AMP_HIGH_MASK (0xFFFF0000UL) +#define VAD_DEC_CTRL2_AMP_HIGH_SHIFT (16U) +#define VAD_DEC_CTRL2_AMP_HIGH_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_HIGH_SHIFT) & VAD_DEC_CTRL2_AMP_HIGH_MASK) +#define VAD_DEC_CTRL2_AMP_HIGH_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_HIGH_MASK) >> VAD_DEC_CTRL2_AMP_HIGH_SHIFT) + +/* + * AMP_LOW (RW) + * + * amplitude low limit + */ +#define VAD_DEC_CTRL2_AMP_LOW_MASK (0xFFFFU) +#define VAD_DEC_CTRL2_AMP_LOW_SHIFT (0U) +#define VAD_DEC_CTRL2_AMP_LOW_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_LOW_SHIFT) & VAD_DEC_CTRL2_AMP_LOW_MASK) +#define VAD_DEC_CTRL2_AMP_LOW_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_LOW_MASK) >> VAD_DEC_CTRL2_AMP_LOW_SHIFT) + +/* Bitfield definition for register: ST */ +/* + * VAD (W1C) + * + * VAD event found + */ +#define VAD_ST_VAD_MASK (0x80U) +#define VAD_ST_VAD_SHIFT (7U) +#define VAD_ST_VAD_SET(x) (((uint32_t)(x) << VAD_ST_VAD_SHIFT) & VAD_ST_VAD_MASK) +#define VAD_ST_VAD_GET(x) (((uint32_t)(x) & VAD_ST_VAD_MASK) >> VAD_ST_VAD_SHIFT) + +/* + * OFIFO_AV (ROI) + * + * OFIFO data available + */ +#define VAD_ST_OFIFO_AV_MASK (0x40U) +#define VAD_ST_OFIFO_AV_SHIFT (6U) +#define VAD_ST_OFIFO_AV_GET(x) (((uint32_t)(x) & VAD_ST_OFIFO_AV_MASK) >> VAD_ST_OFIFO_AV_SHIFT) + +/* + * MEMBUF_EMPTY (W1C) + * + * Buf empty + */ +#define VAD_ST_MEMBUF_EMPTY_MASK (0x20U) +#define VAD_ST_MEMBUF_EMPTY_SHIFT (5U) +#define VAD_ST_MEMBUF_EMPTY_SET(x) (((uint32_t)(x) << VAD_ST_MEMBUF_EMPTY_SHIFT) & VAD_ST_MEMBUF_EMPTY_MASK) +#define VAD_ST_MEMBUF_EMPTY_GET(x) (((uint32_t)(x) & VAD_ST_MEMBUF_EMPTY_MASK) >> VAD_ST_MEMBUF_EMPTY_SHIFT) + +/* + * OFIFO_OVFL (W1C) + * + * OFIFO overflow + */ +#define VAD_ST_OFIFO_OVFL_MASK (0x10U) +#define VAD_ST_OFIFO_OVFL_SHIFT (4U) +#define VAD_ST_OFIFO_OVFL_SET(x) (((uint32_t)(x) << VAD_ST_OFIFO_OVFL_SHIFT) & VAD_ST_OFIFO_OVFL_MASK) +#define VAD_ST_OFIFO_OVFL_GET(x) (((uint32_t)(x) & VAD_ST_OFIFO_OVFL_MASK) >> VAD_ST_OFIFO_OVFL_SHIFT) + +/* + * IIR_OVLD (W1C) + * + * IIR overloading + */ +#define VAD_ST_IIR_OVLD_MASK (0x8U) +#define VAD_ST_IIR_OVLD_SHIFT (3U) +#define VAD_ST_IIR_OVLD_SET(x) (((uint32_t)(x) << VAD_ST_IIR_OVLD_SHIFT) & VAD_ST_IIR_OVLD_MASK) +#define VAD_ST_IIR_OVLD_GET(x) (((uint32_t)(x) & VAD_ST_IIR_OVLD_MASK) >> VAD_ST_IIR_OVLD_SHIFT) + +/* + * IIR_OVFL (W1C) + * + * IIR oberflow + */ +#define VAD_ST_IIR_OVFL_MASK (0x4U) +#define VAD_ST_IIR_OVFL_SHIFT (2U) +#define VAD_ST_IIR_OVFL_SET(x) (((uint32_t)(x) << VAD_ST_IIR_OVFL_SHIFT) & VAD_ST_IIR_OVFL_MASK) +#define VAD_ST_IIR_OVFL_GET(x) (((uint32_t)(x) & VAD_ST_IIR_OVFL_MASK) >> VAD_ST_IIR_OVFL_SHIFT) + +/* + * CIC_OVLD_ERR (W1C) + * + * CIC overload + */ +#define VAD_ST_CIC_OVLD_ERR_MASK (0x2U) +#define VAD_ST_CIC_OVLD_ERR_SHIFT (1U) +#define VAD_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << VAD_ST_CIC_OVLD_ERR_SHIFT) & VAD_ST_CIC_OVLD_ERR_MASK) +#define VAD_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & VAD_ST_CIC_OVLD_ERR_MASK) >> VAD_ST_CIC_OVLD_ERR_SHIFT) + +/* + * CIC_SAT_ERR (W1C) + * + * CIC saturation + */ +#define VAD_ST_CIC_SAT_ERR_MASK (0x1U) +#define VAD_ST_CIC_SAT_ERR_SHIFT (0U) +#define VAD_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << VAD_ST_CIC_SAT_ERR_SHIFT) & VAD_ST_CIC_SAT_ERR_MASK) +#define VAD_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & VAD_ST_CIC_SAT_ERR_MASK) >> VAD_ST_CIC_SAT_ERR_SHIFT) + +/* Bitfield definition for register: OFIFO */ +/* + * D (RW) + * + * The PCM data. + * When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). + * When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). + */ +#define VAD_OFIFO_D_MASK (0xFFFFFFFFUL) +#define VAD_OFIFO_D_SHIFT (0U) +#define VAD_OFIFO_D_SET(x) (((uint32_t)(x) << VAD_OFIFO_D_SHIFT) & VAD_OFIFO_D_MASK) +#define VAD_OFIFO_D_GET(x) (((uint32_t)(x) & VAD_OFIFO_D_MASK) >> VAD_OFIFO_D_SHIFT) + +/* Bitfield definition for register: RUN */ +/* + * SFTRST (RW) + * + * software reset. Self-clear + */ +#define VAD_RUN_SFTRST_MASK (0x2U) +#define VAD_RUN_SFTRST_SHIFT (1U) +#define VAD_RUN_SFTRST_SET(x) (((uint32_t)(x) << VAD_RUN_SFTRST_SHIFT) & VAD_RUN_SFTRST_MASK) +#define VAD_RUN_SFTRST_GET(x) (((uint32_t)(x) & VAD_RUN_SFTRST_MASK) >> VAD_RUN_SFTRST_SHIFT) + +/* + * VAD_EN (RW) + * + * module enable + */ +#define VAD_RUN_VAD_EN_MASK (0x1U) +#define VAD_RUN_VAD_EN_SHIFT (0U) +#define VAD_RUN_VAD_EN_SET(x) (((uint32_t)(x) << VAD_RUN_VAD_EN_SHIFT) & VAD_RUN_VAD_EN_MASK) +#define VAD_RUN_VAD_EN_GET(x) (((uint32_t)(x) & VAD_RUN_VAD_EN_MASK) >> VAD_RUN_VAD_EN_SHIFT) + +/* Bitfield definition for register: OFIFO_CTRL */ +/* + * EN (RW) + * + * Asserted to enable OFIFO + */ +#define VAD_OFIFO_CTRL_EN_MASK (0x1U) +#define VAD_OFIFO_CTRL_EN_SHIFT (0U) +#define VAD_OFIFO_CTRL_EN_SET(x) (((uint32_t)(x) << VAD_OFIFO_CTRL_EN_SHIFT) & VAD_OFIFO_CTRL_EN_MASK) +#define VAD_OFIFO_CTRL_EN_GET(x) (((uint32_t)(x) & VAD_OFIFO_CTRL_EN_MASK) >> VAD_OFIFO_CTRL_EN_SHIFT) + +/* Bitfield definition for register: CIC_CFG */ +/* + * POST_SCALE (RW) + * + * the shift value after CIC results. + */ +#define VAD_CIC_CFG_POST_SCALE_MASK (0xFC00U) +#define VAD_CIC_CFG_POST_SCALE_SHIFT (10U) +#define VAD_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << VAD_CIC_CFG_POST_SCALE_SHIFT) & VAD_CIC_CFG_POST_SCALE_MASK) +#define VAD_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & VAD_CIC_CFG_POST_SCALE_MASK) >> VAD_CIC_CFG_POST_SCALE_SHIFT) + +/* Bitfield definition for register array: COEF */ +/* + * VAL (ROI) + * + * The current detected short time energy + */ +#define VAD_COEF_VAL_MASK (0xFFFFFFFFUL) +#define VAD_COEF_VAL_SHIFT (0U) +#define VAD_COEF_VAL_GET(x) (((uint32_t)(x) & VAD_COEF_VAL_MASK) >> VAD_COEF_VAL_SHIFT) + + + +/* COEF register group index macro definition */ +#define VAD_COEF_STE_ACT (0UL) + + +#endif /* HPM_VAD_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_wdg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_wdg_regs.h new file mode 100644 index 0000000000..5f99205e46 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_wdg_regs.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_WDG_H +#define HPM_WDG_H + +typedef struct { + __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __RW uint32_t CTRL; /* 0x10: Control Register */ + __W uint32_t RESTART; /* 0x14: Restart Register */ + __W uint32_t WREN; /* 0x18: Write Protection Register */ + __W uint32_t ST; /* 0x1C: Status Register */ +} WDG_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * RSTTIME (RW) + * + * The time interval of the reset stage: + * 0: Clock period x 2^7 + * 1: Clock period x 2^8 + * 2: Clock period x 2^9 + * 3: Clock period x 2^10 + * 4: Clock period x 2^11 + * 5: Clock period x 2^12 + * 6: Clock period x 2^13 + * 7: Clock period x 2^14 + */ +#define WDG_CTRL_RSTTIME_MASK (0x700U) +#define WDG_CTRL_RSTTIME_SHIFT (8U) +#define WDG_CTRL_RSTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTTIME_SHIFT) & WDG_CTRL_RSTTIME_MASK) +#define WDG_CTRL_RSTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTTIME_MASK) >> WDG_CTRL_RSTTIME_SHIFT) + +/* + * INTTIME (RW) + * + * The timer interval of the interrupt stage: + * 0: Clock period x 2^6 + * 1: Clock period x 2^8 + * 2: Clock period x 2^10 + * 3: Clock period x 2^11 + * 4: Clock period x 2^12 + * 5: Clock period x 2^13 + * 6: Clock period x 2^14 + * 7: Clock period x 2^15 + * 8: Clock period x 2^17 + * 9: Clock period x 2^19 + * 10: Clock period x 2^21 + * 11: Clock period x 2^23 + * 12: Clock period x 2^25 + * 13: Clock period x 2^27 + * 14: Clock period x 2^29 + * 15: Clock period x 2^31 + */ +#define WDG_CTRL_INTTIME_MASK (0xF0U) +#define WDG_CTRL_INTTIME_SHIFT (4U) +#define WDG_CTRL_INTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_INTTIME_SHIFT) & WDG_CTRL_INTTIME_MASK) +#define WDG_CTRL_INTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_INTTIME_MASK) >> WDG_CTRL_INTTIME_SHIFT) + +/* + * RSTEN (RW) + * + * Enable or disable the watchdog reset + * 0: Disable + * 1: Enable + */ +#define WDG_CTRL_RSTEN_MASK (0x8U) +#define WDG_CTRL_RSTEN_SHIFT (3U) +#define WDG_CTRL_RSTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTEN_SHIFT) & WDG_CTRL_RSTEN_MASK) +#define WDG_CTRL_RSTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTEN_MASK) >> WDG_CTRL_RSTEN_SHIFT) + +/* + * INTEN (RW) + * + * Enable or disable the watchdog interrupt + * 0: Disable + * 1: Enable + */ +#define WDG_CTRL_INTEN_MASK (0x4U) +#define WDG_CTRL_INTEN_SHIFT (2U) +#define WDG_CTRL_INTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_INTEN_SHIFT) & WDG_CTRL_INTEN_MASK) +#define WDG_CTRL_INTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_INTEN_MASK) >> WDG_CTRL_INTEN_SHIFT) + +/* + * CLKSEL (RW) + * + * Clock source of timer: + * 0: EXTCLK + * 1: PCLK + */ +#define WDG_CTRL_CLKSEL_MASK (0x2U) +#define WDG_CTRL_CLKSEL_SHIFT (1U) +#define WDG_CTRL_CLKSEL_SET(x) (((uint32_t)(x) << WDG_CTRL_CLKSEL_SHIFT) & WDG_CTRL_CLKSEL_MASK) +#define WDG_CTRL_CLKSEL_GET(x) (((uint32_t)(x) & WDG_CTRL_CLKSEL_MASK) >> WDG_CTRL_CLKSEL_SHIFT) + +/* + * EN (RW) + * + * Enable or disable the watchdog timer + * 0: Disable + * 1: Enable + */ +#define WDG_CTRL_EN_MASK (0x1U) +#define WDG_CTRL_EN_SHIFT (0U) +#define WDG_CTRL_EN_SET(x) (((uint32_t)(x) << WDG_CTRL_EN_SHIFT) & WDG_CTRL_EN_MASK) +#define WDG_CTRL_EN_GET(x) (((uint32_t)(x) & WDG_CTRL_EN_MASK) >> WDG_CTRL_EN_SHIFT) + +/* Bitfield definition for register: RESTART */ +/* + * RESTART (WO) + * + * Write the magic number + * ATCWDT200_RESTART_NUM to restart the + * watchdog timer. + */ +#define WDG_RESTART_RESTART_MASK (0xFFFFU) +#define WDG_RESTART_RESTART_SHIFT (0U) +#define WDG_RESTART_RESTART_SET(x) (((uint32_t)(x) << WDG_RESTART_RESTART_SHIFT) & WDG_RESTART_RESTART_MASK) +#define WDG_RESTART_RESTART_GET(x) (((uint32_t)(x) & WDG_RESTART_RESTART_MASK) >> WDG_RESTART_RESTART_SHIFT) + +/* Bitfield definition for register: WREN */ +/* + * WEN (WO) + * + * Write the magic code to disable the write + * protection of the Control Register and the + * Restart Register. + */ +#define WDG_WREN_WEN_MASK (0xFFFFU) +#define WDG_WREN_WEN_SHIFT (0U) +#define WDG_WREN_WEN_SET(x) (((uint32_t)(x) << WDG_WREN_WEN_SHIFT) & WDG_WREN_WEN_MASK) +#define WDG_WREN_WEN_GET(x) (((uint32_t)(x) & WDG_WREN_WEN_MASK) >> WDG_WREN_WEN_SHIFT) + +/* Bitfield definition for register: ST */ +/* + * INTEXPIRED (W1C) + * + * The status of the watchdog interrupt timer + * 0: timer is not expired yet + * 1: timer is expired + */ +#define WDG_ST_INTEXPIRED_MASK (0x1U) +#define WDG_ST_INTEXPIRED_SHIFT (0U) +#define WDG_ST_INTEXPIRED_SET(x) (((uint32_t)(x) << WDG_ST_INTEXPIRED_SHIFT) & WDG_ST_INTEXPIRED_MASK) +#define WDG_ST_INTEXPIRED_GET(x) (((uint32_t)(x) & WDG_ST_INTEXPIRED_MASK) >> WDG_ST_INTEXPIRED_SHIFT) + + + + +#endif /* HPM_WDG_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c new file mode 100644 index 0000000000..3db7cd3651 --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" + +int __ffssi2(int x) +{ + int i = 0; + if (!x) { + return 0; + } + for (i = 0; (i < sizeof(x) * 8 - 1); i++) { + if ((x >> i) & 1) { + break; + } + } + return i + 1; +} diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c new file mode 100644 index 0000000000..8c4a9590fb --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifdef __GNUC__ +#include +#include +#include "hpm_common.h" + +void *_sbrk(int incr) +{ + extern char __heap_start__, __heap_end__; + static char *heap_end; + char *prev_heap_end; + void *ret; + + if (heap_end == NULL) + { + heap_end = &__heap_start__; + } + + prev_heap_end = heap_end; + + if ((unsigned int)heap_end + (unsigned int)incr > (unsigned int)(&__heap_end__)) + { + errno = ENOMEM; + + ret = (void *)-1; + } + else + { + heap_end = (char *)((unsigned int)heap_end + (unsigned int)incr); + + ret = (void *)prev_heap_end; + } + + return ret; +} +#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c new file mode 100644 index 0000000000..b728f257ae --- /dev/null +++ b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" + +uint32_t __bswapsi2 (uint32_t u) +{ + return ((((u) & 0xff000000) >> 24) + | (((u) & 0x00ff0000) >> 8) + | (((u) & 0x0000ff00) << 8) + | (((u) & 0x000000ff) << 24)); +} + +uint64_t __bswapdi2 (uint64_t u) +{ + return ((((u) & 0xff00000000000000ull) >> 56) + | (((u) & 0x00ff000000000000ull) >> 40) + | (((u) & 0x0000ff0000000000ull) >> 24) + | (((u) & 0x000000ff00000000ull) >> 8) + | (((u) & 0x00000000ff000000ull) << 8) + | (((u) & 0x0000000000ff0000ull) << 24) + | (((u) & 0x000000000000ff00ull) << 40) + | (((u) & 0x00000000000000ffull) << 56)); +} diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index b9bb14c511..6ddfe7ecb3 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -20,6 +20,8 @@ elif rtconfig.CPU == "ch32v1" : group = group elif rtconfig.CPU == "ch32v3" : group = group +elif rtconfig.CPU == "hpmicro": + group = group else : group = group + SConscript(os.path.join('common', 'SConscript')) diff --git a/libcpu/risc-v/hpmicro/SConscript b/libcpu/risc-v/hpmicro/SConscript new file mode 100644 index 0000000000..1570a1895b --- /dev/null +++ b/libcpu/risc-v/hpmicro/SConscript @@ -0,0 +1,18 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_gcc.S') + +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/hpmicro/context_gcc.S b/libcpu/risc-v/hpmicro/context_gcc.S new file mode 100644 index 0000000000..e5fc8536ea --- /dev/null +++ b/libcpu/risc-v/hpmicro/context_gcc.S @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting implementation + * 2018/12/27 Jesven Add SMP support + * 2020/11/20 BalanceTWK Add FPU support + */ + +#include "cpuport.h" + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + +/* + * rt_base_t rt_hw_interrupt_disable(void); + */ + .globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + csrrci a0, mstatus, 8 + ret + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + csrw mstatus, a0 + ret + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_to(rt_ubase_t to); + * #endif + * a0 --> to + * a1 --> to_thread + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LOAD sp, (a0) + +#ifdef RT_USING_SMP + mv a0, a1 + call rt_cpus_lock_status_restore +#endif + LOAD a0, 2 * REGBYTES(sp) + csrw mstatus, a0 + j rt_hw_context_switch_exit + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * #endif + * + * a0 --> from + * a1 --> to + * a2 --> to_thread + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + /* saved from thread context + * x1/ra -> sp(0) + * x1/ra -> sp(1) + * mstatus.mie -> sp(2) + * x(i) -> sp(i-4) + */ +#ifdef ARCH_RISCV_FPU + addi sp, sp, -32 * FREGBYTES + + FSTORE f0, 0 * FREGBYTES(sp) + FSTORE f1, 1 * FREGBYTES(sp) + FSTORE f2, 2 * FREGBYTES(sp) + FSTORE f3, 3 * FREGBYTES(sp) + FSTORE f4, 4 * FREGBYTES(sp) + FSTORE f5, 5 * FREGBYTES(sp) + FSTORE f6, 6 * FREGBYTES(sp) + FSTORE f7, 7 * FREGBYTES(sp) + FSTORE f8, 8 * FREGBYTES(sp) + FSTORE f9, 9 * FREGBYTES(sp) + FSTORE f10, 10 * FREGBYTES(sp) + FSTORE f11, 11 * FREGBYTES(sp) + FSTORE f12, 12 * FREGBYTES(sp) + FSTORE f13, 13 * FREGBYTES(sp) + FSTORE f14, 14 * FREGBYTES(sp) + FSTORE f15, 15 * FREGBYTES(sp) + FSTORE f16, 16 * FREGBYTES(sp) + FSTORE f17, 17 * FREGBYTES(sp) + FSTORE f18, 18 * FREGBYTES(sp) + FSTORE f19, 19 * FREGBYTES(sp) + FSTORE f20, 20 * FREGBYTES(sp) + FSTORE f21, 21 * FREGBYTES(sp) + FSTORE f22, 22 * FREGBYTES(sp) + FSTORE f23, 23 * FREGBYTES(sp) + FSTORE f24, 24 * FREGBYTES(sp) + FSTORE f25, 25 * FREGBYTES(sp) + FSTORE f26, 26 * FREGBYTES(sp) + FSTORE f27, 27 * FREGBYTES(sp) + FSTORE f28, 28 * FREGBYTES(sp) + FSTORE f29, 29 * FREGBYTES(sp) + FSTORE f30, 30 * FREGBYTES(sp) + FSTORE f31, 31 * FREGBYTES(sp) + +#endif + addi sp, sp, -32 * REGBYTES + STORE sp, (a0) + + STORE x1, 0 * REGBYTES(sp) + STORE x1, 1 * REGBYTES(sp) + + csrr a0, mstatus + andi a0, a0, 8 + beqz a0, save_mpie + li a0, 0x80 +save_mpie: + STORE a0, 2 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + /* restore to thread context + * sp(0) -> epc; + * sp(1) -> ra; + * sp(i) -> x(i+2) + */ + LOAD sp, (a1) + +#ifdef RT_USING_SMP + mv a0, a2 + call rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + + j rt_hw_context_switch_exit + +#ifdef RT_USING_SMP +/* + * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * + * a0 --> context + * a1 --> from + * a2 --> to + * a3 --> to_thread + */ + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + + STORE a0, 0(a1) + + LOAD sp, 0(a2) + move a0, a3 + call rt_cpus_lock_status_restore + + j rt_hw_context_switch_exit + +#endif + +.global rt_hw_context_switch_exit +rt_hw_context_switch_exit: +#ifdef RT_USING_SMP +#ifdef RT_USING_SIGNALS + mv a0, sp + + csrr t0, mhartid + /* switch interrupt stack of current cpu */ + la sp, __stack_start__ + addi t1, t0, 1 + li t2, __STACKSIZE__ + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ + + call rt_signal_check + mv sp, a0 +#endif +#endif + /* resw ra to mepc */ + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + + LOAD x1, 1 * REGBYTES(sp) + + li t0, 0x00007800 + csrw mstatus, t0 + LOAD a0, 2 * REGBYTES(sp) + csrs mstatus, a0 + + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + +#ifdef ARCH_RISCV_FPU + FLOAD f0, 0 * FREGBYTES(sp) + FLOAD f1, 1 * FREGBYTES(sp) + FLOAD f2, 2 * FREGBYTES(sp) + FLOAD f3, 3 * FREGBYTES(sp) + FLOAD f4, 4 * FREGBYTES(sp) + FLOAD f5, 5 * FREGBYTES(sp) + FLOAD f6, 6 * FREGBYTES(sp) + FLOAD f7, 7 * FREGBYTES(sp) + FLOAD f8, 8 * FREGBYTES(sp) + FLOAD f9, 9 * FREGBYTES(sp) + FLOAD f10, 10 * FREGBYTES(sp) + FLOAD f11, 11 * FREGBYTES(sp) + FLOAD f12, 12 * FREGBYTES(sp) + FLOAD f13, 13 * FREGBYTES(sp) + FLOAD f14, 14 * FREGBYTES(sp) + FLOAD f15, 15 * FREGBYTES(sp) + FLOAD f16, 16 * FREGBYTES(sp) + FLOAD f17, 17 * FREGBYTES(sp) + FLOAD f18, 18 * FREGBYTES(sp) + FLOAD f19, 19 * FREGBYTES(sp) + FLOAD f20, 20 * FREGBYTES(sp) + FLOAD f21, 21 * FREGBYTES(sp) + FLOAD f22, 22 * FREGBYTES(sp) + FLOAD f23, 23 * FREGBYTES(sp) + FLOAD f24, 24 * FREGBYTES(sp) + FLOAD f25, 25 * FREGBYTES(sp) + FLOAD f26, 26 * FREGBYTES(sp) + FLOAD f27, 27 * FREGBYTES(sp) + FLOAD f28, 28 * FREGBYTES(sp) + FLOAD f29, 29 * FREGBYTES(sp) + FLOAD f30, 30 * FREGBYTES(sp) + FLOAD f31, 31 * FREGBYTES(sp) + + addi sp, sp, 32 * FREGBYTES +#endif + + mret diff --git a/libcpu/risc-v/hpmicro/cpuport.c b/libcpu/risc-v/hpmicro/cpuport.c new file mode 100644 index 0000000000..8063e4bc45 --- /dev/null +++ b/libcpu/risc-v/hpmicro/cpuport.c @@ -0,0 +1,90 @@ +/* +#include +#include + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + * 2020/11/20 BalanceTWK Add FPU support + */ + +#include +#include +#include "riscv-stackframe.h" + + +volatile rt_ubase_t rt_interrupt_from_thread = 0; +volatile rt_ubase_t rt_interrupt_to_thread = 0; +volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; + + + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; + } + + frame->ra = (rt_ubase_t)texit; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + + /* force to machine mode(MPP=11) and set MPIE to 1 */ + frame->mstatus = 0x00007880; + + return stk; +} + +/* + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + */ +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + + return ; +} + +/** shutdown CPU */ +RT_WEAK void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} diff --git a/libcpu/risc-v/hpmicro/cpuport.h b/libcpu/risc-v/hpmicro/cpuport.h new file mode 100644 index 0000000000..204d367473 --- /dev/null +++ b/libcpu/risc-v/hpmicro/cpuport.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + * 2020/11/20 BalanceTWK Add FPU support + */ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#include + +/* bytes of register width */ +#define STORE sw +#define LOAD lw +#define REGBYTES 4 + +#ifdef __riscv_flen +#define ARCH_RISCV_FPU + +#if __riscv_flen == 32 +#define ARCH_RISCV_FPU_S +#endif + +#if __riscv_flen == 64 +#define ARCH_RISCV_FPU_D +#endif +#endif + +#ifdef ARCH_RISCV_FPU +#ifdef ARCH_RISCV_FPU_D +#define FSTORE fsd +#define FLOAD fld +#define FREGBYTES 8 +#define rv_floatreg_t rt_int64_t +#endif +#ifdef ARCH_RISCV_FPU_S +#define FSTORE fsw +#define FLOAD flw +#define FREGBYTES 4 +#define rv_floatreg_t rt_int32_t +#endif +#endif + +#endif diff --git a/libcpu/risc-v/hpmicro/riscv-stackframe.h b/libcpu/risc-v/hpmicro/riscv-stackframe.h new file mode 100644 index 0000000000..0b2449d6bb --- /dev/null +++ b/libcpu/risc-v/hpmicro/riscv-stackframe.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-03 Bernard The first version + */ +#ifndef RISCV_STACKFRAME_H + +#define RISCV_STACKFRAME_H + +#include "cpuport.h" + +typedef struct rt_hw_stack_frame +{ + rt_ubase_t epc; /* epc - epc - program counter */ + rt_ubase_t ra; /* x1 - ra - return address for jumps */ + rt_ubase_t mstatus; /* - machine status register */ + rt_ubase_t gp; /* x3 - gp - global pointer */ + rt_ubase_t tp; /* x4 - tp - thread pointer */ + rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /* x9 - s1 - saved register 1 */ + rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /* x12 - a2 - function argument 2 */ + rt_ubase_t a3; /* x13 - a3 - function argument 3 */ + rt_ubase_t a4; /* x14 - a4 - function argument 4 */ + rt_ubase_t a5; /* x15 - a5 - function argument 5 */ + rt_ubase_t a6; /* x16 - a6 - function argument 6 */ + rt_ubase_t a7; /* x17 - a7 - function argument 7 */ + rt_ubase_t s2; /* x18 - s2 - saved register 2 */ + rt_ubase_t s3; /* x19 - s3 - saved register 3 */ + rt_ubase_t s4; /* x20 - s4 - saved register 4 */ + rt_ubase_t s5; /* x21 - s5 - saved register 5 */ + rt_ubase_t s6; /* x22 - s6 - saved register 6 */ + rt_ubase_t s7; /* x23 - s7 - saved register 7 */ + rt_ubase_t s8; /* x24 - s8 - saved register 8 */ + rt_ubase_t s9; /* x25 - s9 - saved register 9 */ + rt_ubase_t s10; /* x26 - s10 - saved register 10 */ + rt_ubase_t s11; /* x27 - s11 - saved register 11 */ + rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ +#ifdef ARCH_RISCV_FPU + rv_floatreg_t f0; /* f0 */ + rv_floatreg_t f1; /* f1 */ + rv_floatreg_t f2; /* f2 */ + rv_floatreg_t f3; /* f3 */ + rv_floatreg_t f4; /* f4 */ + rv_floatreg_t f5; /* f5 */ + rv_floatreg_t f6; /* f6 */ + rv_floatreg_t f7; /* f7 */ + rv_floatreg_t f8; /* f8 */ + rv_floatreg_t f9; /* f9 */ + rv_floatreg_t f10; /* f10 */ + rv_floatreg_t f11; /* f11 */ + rv_floatreg_t f12; /* f12 */ + rv_floatreg_t f13; /* f13 */ + rv_floatreg_t f14; /* f14 */ + rv_floatreg_t f15; /* f15 */ + rv_floatreg_t f16; /* f16 */ + rv_floatreg_t f17; /* f17 */ + rv_floatreg_t f18; /* f18 */ + rv_floatreg_t f19; /* f19 */ + rv_floatreg_t f20; /* f20 */ + rv_floatreg_t f21; /* f21 */ + rv_floatreg_t f22; /* f22 */ + rv_floatreg_t f23; /* f23 */ + rv_floatreg_t f24; /* f24 */ + rv_floatreg_t f25; /* f25 */ + rv_floatreg_t f26; /* f26 */ + rv_floatreg_t f27; /* f27 */ + rv_floatreg_t f28; /* f28 */ + rv_floatreg_t f29; /* f29 */ + rv_floatreg_t f30; /* f30 */ + rv_floatreg_t f31; /* f31 */ +#endif +}rt_hw_stack_frame_t; + + +#endif /* RISCV_STACKFRAME_H */ diff --git a/libcpu/risc-v/hpmicro/trap_entry_gcc.S b/libcpu/risc-v/hpmicro/trap_entry_gcc.S new file mode 100644 index 0000000000..63b79711a7 --- /dev/null +++ b/libcpu/risc-v/hpmicro/trap_entry_gcc.S @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022/01/16 HPMicro The first version + * 2020/04/27 HPMicro Bugfix for interrupt management + */ + +#include "cpuport.h" + + .section .isr_vector, "ax" + .global irq_handler_trap + .align 2 +irq_handler_trap: +#ifdef ARCH_RISCV_FPU + addi sp, sp, -32 * FREGBYTES + FSTORE f0, 0 * FREGBYTES(sp) + FSTORE f1, 1 * FREGBYTES(sp) + FSTORE f2, 2 * FREGBYTES(sp) + FSTORE f3, 3 * FREGBYTES(sp) + FSTORE f4, 4 * FREGBYTES(sp) + FSTORE f5, 5 * FREGBYTES(sp) + FSTORE f6, 6 * FREGBYTES(sp) + FSTORE f7, 7 * FREGBYTES(sp) + FSTORE f8, 8 * FREGBYTES(sp) + FSTORE f9, 9 * FREGBYTES(sp) + FSTORE f10, 10 * FREGBYTES(sp) + FSTORE f11, 11 * FREGBYTES(sp) + FSTORE f12, 12 * FREGBYTES(sp) + FSTORE f13, 13 * FREGBYTES(sp) + FSTORE f14, 14 * FREGBYTES(sp) + FSTORE f15, 15 * FREGBYTES(sp) + FSTORE f16, 16 * FREGBYTES(sp) + FSTORE f17, 17 * FREGBYTES(sp) + FSTORE f18, 18 * FREGBYTES(sp) + FSTORE f19, 19 * FREGBYTES(sp) + FSTORE f20, 20 * FREGBYTES(sp) + FSTORE f21, 21 * FREGBYTES(sp) + FSTORE f22, 22 * FREGBYTES(sp) + FSTORE f23, 23 * FREGBYTES(sp) + FSTORE f24, 24 * FREGBYTES(sp) + FSTORE f25, 25 * FREGBYTES(sp) + FSTORE f26, 26 * FREGBYTES(sp) + FSTORE f27, 27 * FREGBYTES(sp) + FSTORE f28, 28 * FREGBYTES(sp) + FSTORE f29, 29 * FREGBYTES(sp) + FSTORE f30, 30 * FREGBYTES(sp) + FSTORE f31, 31 * FREGBYTES(sp) +#endif + /* save all from thread context */ + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) // ra + li t0, 0x80 + STORE t0, 2 * REGBYTES(sp) // mstatus + + STORE x4, 4 * REGBYTES(sp) // tp - thread pointer + STORE x5, 5 * REGBYTES(sp) // t0 + STORE x6, 6 * REGBYTES(sp) // t1 + STORE x7, 7 * REGBYTES(sp) // t2 + STORE x8, 8 * REGBYTES(sp) // s0/fp + STORE x9, 9 * REGBYTES(sp) // s1 + STORE x10, 10 * REGBYTES(sp) // a0 + STORE x11, 11 * REGBYTES(sp) // a1 + STORE x12, 12 * REGBYTES(sp) // a2 + STORE x13, 13 * REGBYTES(sp) // a3 + STORE x14, 14 * REGBYTES(sp) // a4 + STORE x15, 15 * REGBYTES(sp) // a5 + STORE x16, 16 * REGBYTES(sp) // a6 + STORE x17, 17 * REGBYTES(sp) // a7 + STORE x18, 18 * REGBYTES(sp) // s2 + STORE x19, 19 * REGBYTES(sp) // s3 + STORE x20, 20 * REGBYTES(sp) // s4 + STORE x21, 21 * REGBYTES(sp) // s5 + STORE x22, 22 * REGBYTES(sp) // s6 + STORE x23, 23 * REGBYTES(sp) // s7 + STORE x24, 24 * REGBYTES(sp) // s8 + STORE x25, 25 * REGBYTES(sp) // s9 + STORE x26, 26 * REGBYTES(sp) // s10 + STORE x27, 27 * REGBYTES(sp) // s11 + STORE x28, 28 * REGBYTES(sp) // t3 + STORE x29, 29 * REGBYTES(sp) // t4 + STORE x30, 30 * REGBYTES(sp) // t5 + STORE x31, 31 * REGBYTES(sp) // t6 + + /* Save the thread stack frame base to mscratch */ + csrw mscratch, sp + + /* switch to interrupt stack */ + la sp, _stack + + /* interrupt handle */ + call rt_interrupt_enter + /* Get the thread stack frame base from mscratch */ + csrr a0, mscratch + call trap_entry + call rt_interrupt_leave + + /* switch to thread stack */ + csrr sp, mscratch + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + lw s2, 0(s0) + beqz s2, spurious_interrupt + /* clear switch interrupt flag */ + sw zero, 0(s0) + + csrr a0, mepc + STORE a0, 0 * REGBYTES(sp) + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + +spurious_interrupt: + LOAD x1, 1 * REGBYTES(sp) // ra + /* Remain in M-mode after mret */ + li t0, 0x00001800 + csrs mstatus, t0 + LOAD t0, 2 * REGBYTES(sp) + csrs mstatus, t0 // mstatus.mpie + + LOAD x4, 4 * REGBYTES(sp) // tp + LOAD x5, 5 * REGBYTES(sp) // t0 + LOAD x6, 6 * REGBYTES(sp) // t1 + LOAD x7, 7 * REGBYTES(sp) // t2 + LOAD x8, 8 * REGBYTES(sp) // s0/fp + LOAD x9, 9 * REGBYTES(sp) // s1 + LOAD x10, 10 * REGBYTES(sp) // a0 + LOAD x11, 11 * REGBYTES(sp) // a1 + LOAD x12, 12 * REGBYTES(sp) // a2 + LOAD x13, 13 * REGBYTES(sp) // a3 + LOAD x14, 14 * REGBYTES(sp) // a4 + LOAD x15, 15 * REGBYTES(sp) // a5 + LOAD x16, 16 * REGBYTES(sp) // a6 + LOAD x17, 17 * REGBYTES(sp) // a7 + LOAD x18, 18 * REGBYTES(sp) // s2 + LOAD x19, 19 * REGBYTES(sp) // s3 + LOAD x20, 20 * REGBYTES(sp) // s4 + LOAD x21, 21 * REGBYTES(sp) // s5 + LOAD x22, 22 * REGBYTES(sp) // s6 + LOAD x23, 23 * REGBYTES(sp) // s7 + LOAD x24, 24 * REGBYTES(sp) // s8 + LOAD x25, 25 * REGBYTES(sp) // s9 + LOAD x26, 26 * REGBYTES(sp) // s10 + LOAD x27, 27 * REGBYTES(sp) // s11 + LOAD x28, 28 * REGBYTES(sp) // t3 + LOAD x29, 29 * REGBYTES(sp) // t4 + LOAD x30, 30 * REGBYTES(sp) // t5 + LOAD x31, 31 * REGBYTES(sp) // t6 + + addi sp, sp, 32 * REGBYTES + +#ifdef ARCH_RISCV_FPU + FLOAD f0, 0 * FREGBYTES(sp) + FLOAD f1, 1 * FREGBYTES(sp) + FLOAD f2, 2 * FREGBYTES(sp) + FLOAD f3, 3 * FREGBYTES(sp) + FLOAD f4, 4 * FREGBYTES(sp) + FLOAD f5, 5 * FREGBYTES(sp) + FLOAD f6, 6 * FREGBYTES(sp) + FLOAD f7, 7 * FREGBYTES(sp) + FLOAD f8, 8 * FREGBYTES(sp) + FLOAD f9, 9 * FREGBYTES(sp) + FLOAD f10, 10 * FREGBYTES(sp) + FLOAD f11, 11 * FREGBYTES(sp) + FLOAD f12, 12 * FREGBYTES(sp) + FLOAD f13, 13 * FREGBYTES(sp) + FLOAD f14, 14 * FREGBYTES(sp) + FLOAD f15, 15 * FREGBYTES(sp) + FLOAD f16, 16 * FREGBYTES(sp) + FLOAD f17, 17 * FREGBYTES(sp) + FLOAD f18, 18 * FREGBYTES(sp) + FLOAD f19, 19 * FREGBYTES(sp) + FLOAD f20, 20 * FREGBYTES(sp) + FLOAD f21, 21 * FREGBYTES(sp) + FLOAD f22, 22 * FREGBYTES(sp) + FLOAD f23, 23 * FREGBYTES(sp) + FLOAD f24, 24 * FREGBYTES(sp) + FLOAD f25, 25 * FREGBYTES(sp) + FLOAD f26, 26 * FREGBYTES(sp) + FLOAD f27, 27 * FREGBYTES(sp) + FLOAD f28, 28 * FREGBYTES(sp) + FLOAD f29, 29 * FREGBYTES(sp) + FLOAD f30, 30 * FREGBYTES(sp) + FLOAD f31, 31 * FREGBYTES(sp) + + addi sp, sp, 32 * FREGBYTES +#endif + + mret