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[DM/FEATURE] Support DMA management (#9682)
1. DMA pool management for platform. 2. DMA engine driver API. Signed-off-by: GuEe-GUI <2991707448@qq.com>
This commit is contained in:
GUI
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-02-25 GuEe-GUI the first version
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*/
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#ifndef __DMA_H__
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#define __DMA_H__
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#include <rtthread.h>
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#include <drivers/ofw.h>
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#include <drivers/misc.h>
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#include <drivers/core/dm.h>
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#include <mmu.h>
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#include <mm_page.h>
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#include <bitmap.h>
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struct rt_dma_chan;
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struct rt_dma_controller_ops;
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enum rt_dma_transfer_direction
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{
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RT_DMA_MEM_TO_MEM,
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RT_DMA_MEM_TO_DEV,
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RT_DMA_DEV_TO_MEM,
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RT_DMA_DEV_TO_DEV,
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RT_DMA_DIR_MAX,
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};
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enum rt_dma_slave_buswidth
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{
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RT_DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
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RT_DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
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RT_DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
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RT_DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
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RT_DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
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RT_DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
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RT_DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
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RT_DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
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RT_DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
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RT_DMA_SLAVE_BUSWIDTH_128_BYTES = 128,
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RT_DMA_SLAVE_BUSWIDTH_BYTES_MAX,
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};
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struct rt_dma_slave_config
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{
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enum rt_dma_transfer_direction direction;
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enum rt_dma_slave_buswidth src_addr_width;
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enum rt_dma_slave_buswidth dst_addr_width;
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rt_ubase_t src_addr;
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rt_ubase_t dst_addr;
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rt_uint32_t src_maxburst;
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rt_uint32_t dst_maxburst;
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rt_uint32_t src_port_window_size;
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rt_uint32_t dst_port_window_size;
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};
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struct rt_dma_slave_transfer
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{
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rt_ubase_t src_addr;
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rt_ubase_t dst_addr;
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void *buffer;
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rt_ubase_t dma_handle;
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rt_size_t buffer_len;
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rt_size_t period_len;
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};
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struct rt_dma_controller
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{
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rt_list_t list;
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struct rt_device *dev;
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RT_BITMAP_DECLARE(dir_cap, RT_DMA_DIR_MAX);
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const struct rt_dma_controller_ops *ops;
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rt_list_t channels_nodes;
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struct rt_mutex mutex;
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};
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struct rt_dma_controller_ops
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{
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struct rt_dma_chan *(*request_chan)(struct rt_dma_controller *ctrl, struct rt_device *slave);
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rt_err_t (*release_chan)(struct rt_dma_chan *chan);
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rt_err_t (*start)(struct rt_dma_chan *chan);
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rt_err_t (*stop)(struct rt_dma_chan *chan);
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rt_err_t (*config)(struct rt_dma_chan *chan, struct rt_dma_slave_config *conf);
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rt_err_t (*prep_memcpy)(struct rt_dma_chan *chan,
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rt_ubase_t dma_addr_src, rt_ubase_t dma_addr_dst, rt_size_t len);
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rt_err_t (*prep_cyclic)(struct rt_dma_chan *chan,
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rt_ubase_t dma_buf_addr, rt_size_t buf_len, rt_size_t period_len,
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enum rt_dma_transfer_direction dir);
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rt_err_t (*prep_single)(struct rt_dma_chan *chan,
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rt_ubase_t dma_buf_addr, rt_size_t buf_len,
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enum rt_dma_transfer_direction dir);
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rt_err_t (*ofw_parse)(struct rt_dma_controller *ctrl, struct rt_ofw_cell_args *dma_args);
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};
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struct rt_dma_chan
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{
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const char *name;
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struct rt_dma_controller *ctrl;
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struct rt_device *slave;
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rt_list_t list;
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rt_err_t conf_err;
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rt_err_t prep_err;
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struct rt_dma_slave_config conf;
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struct rt_dma_slave_transfer transfer;
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void (*callback)(struct rt_dma_chan *chan, rt_size_t size);
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void *priv;
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};
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struct rt_dma_pool
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{
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rt_region_t region;
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rt_list_t list;
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rt_ubase_t flags;
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rt_bitmap_t *map;
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rt_size_t bits;
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rt_ubase_t start;
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struct rt_device *dev;
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};
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struct rt_dma_map_ops
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{
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void *(*alloc)(struct rt_device *dev, rt_size_t size,
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rt_ubase_t *dma_handle, rt_ubase_t flags);
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void (*free)(struct rt_device *dev, rt_size_t size,
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void *cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags);
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rt_err_t (*sync_out_data)(struct rt_device *dev, void *data, rt_size_t size,
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rt_ubase_t *dma_handle, rt_ubase_t flags);
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rt_err_t (*sync_in_data)(struct rt_device *dev, void *out_data, rt_size_t size,
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rt_ubase_t dma_handle, rt_ubase_t flags);
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};
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rt_inline void rt_dma_controller_add_direction(struct rt_dma_controller *ctrl,
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enum rt_dma_transfer_direction dir)
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{
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RT_ASSERT(ctrl != RT_NULL);
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RT_ASSERT(dir < RT_DMA_DIR_MAX);
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rt_bitmap_set_bit(ctrl->dir_cap, dir);
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}
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rt_err_t rt_dma_controller_register(struct rt_dma_controller *ctrl);
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rt_err_t rt_dma_controller_unregister(struct rt_dma_controller *ctrl);
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rt_err_t rt_dma_chan_start(struct rt_dma_chan *chan);
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rt_err_t rt_dma_chan_stop(struct rt_dma_chan *chan);
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rt_err_t rt_dma_chan_config(struct rt_dma_chan *chan,
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struct rt_dma_slave_config *conf);
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rt_err_t rt_dma_chan_done(struct rt_dma_chan *chan, rt_size_t size);
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rt_err_t rt_dma_prep_memcpy(struct rt_dma_chan *chan,
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struct rt_dma_slave_transfer *transfer);
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rt_err_t rt_dma_prep_cyclic(struct rt_dma_chan *chan,
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struct rt_dma_slave_transfer *transfer);
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rt_err_t rt_dma_prep_single(struct rt_dma_chan *chan,
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struct rt_dma_slave_transfer *transfer);
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struct rt_dma_chan *rt_dma_chan_request(struct rt_device *dev, const char *name);
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rt_err_t rt_dma_chan_release(struct rt_dma_chan *chan);
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#define RT_DMA_F_LINEAR RT_BIT(0)
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#define RT_DMA_F_32BITS RT_BIT(1)
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#define RT_DMA_F_NOCACHE RT_BIT(2)
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#define RT_DMA_F_DEVICE RT_BIT(3)
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#define RT_DMA_F_NOMAP RT_BIT(4)
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#define RT_DMA_PAGE_SIZE ARCH_PAGE_SIZE
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void *rt_dma_alloc(struct rt_device *dev, rt_size_t size,
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rt_ubase_t *dma_handle, rt_ubase_t flags);
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void rt_dma_free(struct rt_device *dev, rt_size_t size,
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void *cpu_addr, rt_ubase_t dma_handle, rt_ubase_t flags);
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rt_inline void *rt_dma_alloc_coherent(struct rt_device *dev, rt_size_t size,
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rt_ubase_t *dma_handle)
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{
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return rt_dma_alloc(dev, size, dma_handle,
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RT_DMA_F_NOCACHE | RT_DMA_F_LINEAR);
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}
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rt_inline void rt_dma_free_coherent(struct rt_device *dev, rt_size_t size,
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void *cpu_addr, rt_ubase_t dma_handle)
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{
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rt_dma_free(dev, size, cpu_addr, dma_handle,
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RT_DMA_F_NOCACHE | RT_DMA_F_LINEAR);
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}
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rt_err_t rt_dma_sync_out_data(struct rt_device *dev, void *data, rt_size_t size,
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rt_ubase_t *dma_handle, rt_ubase_t flags);
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rt_err_t rt_dma_sync_in_data(struct rt_device *dev, void *out_data, rt_size_t size,
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rt_ubase_t dma_handle, rt_ubase_t flags);
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rt_inline rt_bool_t rt_dma_device_is_coherent(struct rt_device *dev)
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{
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return rt_dm_dev_prop_read_bool(dev, "dma-coherent");
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}
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rt_inline void rt_dma_device_set_ops(struct rt_device *dev,
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const struct rt_dma_map_ops *ops)
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{
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dev->dma_ops = ops;
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}
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struct rt_dma_pool *rt_dma_pool_install(rt_region_t *region);
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rt_err_t rt_dma_pool_extract(rt_region_t *region_list, rt_size_t list_len,
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rt_size_t cma_size, rt_size_t coherent_pool_size);
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#endif /* __DMA_H__ */
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@@ -49,6 +49,10 @@ extern "C" {
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#include "drivers/blk.h"
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#endif
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#ifdef RT_USING_DMA
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#include "drivers/dma.h"
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#endif
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#include "drivers/iio.h"
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#ifdef RT_USING_OFW
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