diff --git a/bsp/imxrt/imxrt1052-nxp-evk/.config b/bsp/imxrt/imxrt1052-nxp-evk/.config index 22f25240aa..6c073109cc 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/.config +++ b/bsp/imxrt/imxrt1052-nxp-evk/.config @@ -7,6 +7,7 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -63,7 +64,8 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x40003 +# CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # @@ -108,6 +110,7 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 @@ -115,12 +118,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set CONFIG_RT_USING_CPUTIME=y # CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PHY=y CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -128,10 +132,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -145,6 +149,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set # # Network @@ -155,15 +160,26 @@ CONFIG_RT_USING_LIBC=y # # CONFIG_RT_USING_SAL is not set +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set + # # light weight TCP/IP stack # # CONFIG_RT_USING_LWIP is not set - -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP202 is not set +# CONFIG_RT_USING_LWIP212 is not set # # AT commands @@ -178,7 +194,6 @@ CONFIG_RT_USING_LIBC=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set @@ -230,13 +245,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOTKIT is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set # CONFIG_PKG_USING_LSSDP is not set # CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set # # security packages @@ -294,6 +308,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AP3216C is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -310,7 +325,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set # # miscellaneous packages @@ -354,10 +368,13 @@ CONFIG_BSP_USING_LPUART=y CONFIG_BSP_USING_LPUART1=y # CONFIG_BSP_LPUART1_RX_USING_DMA is not set # CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART3 is not set # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_ETH is not set # # Board extended module Drivers diff --git a/bsp/imxrt/imxrt1052-nxp-evk/SConstruct b/bsp/imxrt/imxrt1052-nxp-evk/SConstruct index 9e5cd55bc0..f9ddc50fa3 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/SConstruct +++ b/bsp/imxrt/imxrt1052-nxp-evk/SConstruct @@ -67,5 +67,8 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SCons # include drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) +# include peripherals +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'peripherals', 'SConscript'))) + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig b/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig index 14a282f3b5..257e979204 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig @@ -225,7 +225,6 @@ menu "Onboard Peripheral Drivers" menuconfig BSP_USING_ETH bool "Enable Ethernet" - select PHY_USING_KSZ8081 select RT_USING_NETDEV default n @@ -238,14 +237,36 @@ menu "Onboard Peripheral Drivers" default n if BSP_USING_ETH - config PHY_USING_KSZ8081 - bool "i.MX RT1050EVKB uses ksz8081 phy" + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" default y - config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE - bool "Enable the PHY ksz8081 RMII50M mode" - depends on PHY_USING_KSZ8081 - default y + if BSP_USING_PHY + config PHY_DEVICE_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_USING_KSZ8081 + bool "i.MX RT1064EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_RESET_PORT + int "indicate port of reset" + default 1 + + config PHY_RESET_PIN + int "indicate pin of reset" + default 9 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + + endif endif config BSP_USING_RGB bool "Enable RGB LED (PWM1_CH3A, PWM4_CH0A and PWM4_CH1A)" diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/SConscript b/bsp/imxrt/imxrt1052-nxp-evk/board/SConscript index 468395b44d..a338eca9fa 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/SConscript +++ b/bsp/imxrt/imxrt1052-nxp-evk/board/SConscript @@ -12,10 +12,6 @@ MCUX_Config/pin_mux.c CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1'] -if GetDepend(['PHY_USING_KSZ8081']): - src += Glob('ports/phyksz8081/fsl_phy.c') - CPPPATH += [cwd + '/ports/phyksz8081'] - group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c b/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c deleted file mode 100644 index 4197514aa5..0000000000 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_phy.h" -#include -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Defines the timeout macro. */ -#define PHY_TIMEOUT_COUNT 0x3FFFFFFU - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/*! - * @brief Get the ENET instance from peripheral base address. - * - * @param base ENET peripheral base address. - * @return ENET instance. - */ -extern uint32_t ENET_GetInstance(ENET_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to enet clocks for each instance. */ -extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) -{ - uint32_t bssReg; - uint32_t counter = PHY_TIMEOUT_COUNT; - uint32_t idReg = 0; - status_t result = kStatus_Success; - uint32_t instance = ENET_GetInstance(base); - uint32_t timeDelay; - uint32_t ctlReg = 0; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Set SMI first. */ - CLOCK_EnableClock(s_enetClock[instance]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - ENET_SetSMI(base, srcClock_Hz, false); - - /* Initialization after PHY stars to work. */ - while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) - { - PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); - counter --; - } - - if (!counter) - { - return kStatus_Fail; - } - - /* Reset PHY. */ - counter = PHY_TIMEOUT_COUNT; - result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); - if (result == kStatus_Success) - { - -#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) - uint32_t data = 0; - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if ( result != kStatus_Success) - { - return result; - } - result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); - if (result != kStatus_Success) - { - return result; - } -#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ - - /* Set the negotiation. */ - result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, - (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | - PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); - if (result == kStatus_Success) - { - result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, - (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); - if (result == kStatus_Success) - { - /* Check auto negotiation complete. */ - while (counter --) - { - result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); - if ( result == kStatus_Success) - { - PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); - if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK)) - { - /* Wait a moment for Phy status stable. */ - for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++) - { - __ASM("nop"); - } - break; - } - } - - if (!counter) - { - return kStatus_PHY_AutoNegotiateFail; - } - } - } - } - } - - return result; -} - -status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) -{ - uint32_t counter; - - /* Clear the SMI interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - /* Starts a SMI write command. */ - ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); - - /* Wait for SMI complete. */ - for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) - { - if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) - { - break; - } - } - - /* Check for timeout. */ - if (!counter) - { - return kStatus_PHY_SMIVisitTimeout; - } - - /* Clear MII interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - return kStatus_Success; -} - -status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) -{ - assert(dataPtr); - - uint32_t counter; - - /* Clear the MII interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - /* Starts a SMI read command operation. */ - ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); - - /* Wait for MII complete. */ - for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) - { - if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) - { - break; - } - } - - /* Check for timeout. */ - if (!counter) - { - return kStatus_PHY_SMIVisitTimeout; - } - - /* Get data from MII register. */ - *dataPtr = ENET_ReadSMIData(base); - - /* Clear MII interrupt event. */ - ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); - - return kStatus_Success; -} - -status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable) -{ - status_t result; - uint32_t data = 0; - - /* Set the loop mode. */ - if (enable) - { - if (mode == kPHY_LocalLoop) - { - if (speed == kPHY_Speed100M) - { - data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; - } - else - { - data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; - } - return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data); - } - else - { - /* First read the current status in control register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if (result == kStatus_Success) - { - return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); - } - } - } - else - { - /* Disable the loop mode. */ - if (mode == kPHY_LocalLoop) - { - /* First read the current status in control register. */ - result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); - if (result == kStatus_Success) - { - data &= ~PHY_BCTL_LOOP_MASK; - return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK)); - } - } - else - { - /* First read the current status in control one register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); - if (result == kStatus_Success) - { - return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); - } - } - } - return result; -} - -status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) -{ - assert(status); - - status_t result = kStatus_Success; - uint32_t data; - - /* Read the basic status register. */ - result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); - if (result == kStatus_Success) - { - if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) - { - /* link down. */ - *status = false; - } - else - { - /* link up. */ - *status = true; - } - } - return result; -} - -status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) -{ - assert(duplex); - - status_t result = kStatus_Success; - uint32_t data, ctlReg; - - /* Read the control two register. */ - result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); - if (result == kStatus_Success) - { - data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; - if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) - { - /* Full duplex. */ - *duplex = kPHY_FullDuplex; - } - else - { - /* Half duplex. */ - *duplex = kPHY_HalfDuplex; - } - - data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; - if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) - { - /* 100M speed. */ - *speed = kPHY_Speed100M; - } - else - { /* 10M speed. */ - *speed = kPHY_Speed10M; - } - } - - return result; -} diff --git a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h b/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h deleted file mode 100644 index a1eff6d723..0000000000 --- a/bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_PHY_H_ -#define _FSL_PHY_H_ - -#include "fsl_enet.h" - -/*! - * @addtogroup phy_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief PHY driver version */ -#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - -/*! @brief Defines the PHY registers. */ -#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ -#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ -#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ -#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ -#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ -#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ -#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ - -#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ - -/*! @brief Defines the mask flag in basic control register. */ -#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ -#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ -#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ -#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ -#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ -#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ -#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ - -/*!@brief Defines the mask flag of operation mode in control two register*/ -#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ -#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ -#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ -#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ -#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ -#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ -#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ -#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ -#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ -#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) - -/*! @brief Defines the mask flag in basic status register. */ -#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ -#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ -#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ - -/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ -#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ -#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ -#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ -#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ -#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ - -/*! @brief Defines the PHY status. */ -enum _phy_status -{ - kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ - kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ -}; - -/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ -typedef enum _phy_speed -{ - kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ - kPHY_Speed100M /*!< ENET PHY 100M speed. */ -} phy_speed_t; - -/*! @brief Defines the PHY link duplex. */ -typedef enum _phy_duplex -{ - kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ - kPHY_FullDuplex /*!< ENET PHY full duplex. */ -} phy_duplex_t; - -/*! @brief Defines the PHY loopback mode. */ -typedef enum _phy_loop -{ - kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ - kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ -} phy_loop_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name PHY Driver - * @{ - */ - -/*! - * @brief Initializes PHY. - * - * This function initialize the SMI interface and initialize PHY. - * The SMI is the MII management interface between PHY and MAC, which should be - * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. - * @retval kStatus_Success PHY initialize success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail - */ -status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); - -/*! - * @brief PHY Write function. This function write data over the SMI to - * the specified PHY register. This function is called by all PHY interfaces. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - * @param data The data written to the PHY register. - * @retval kStatus_Success PHY write success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); - -/*! - * @brief PHY Read function. This interface read data over the SMI from the - * specified PHY register. This function is called by all PHY interfaces. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param phyReg The PHY register. - * @param dataPtr The address to store the data read from the PHY register. - * @retval kStatus_Success PHY read success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); - -/*! - * @brief Enables/disables PHY loopback. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param mode The loopback mode to be enabled, please see "phy_loop_t". - * the two loopback mode should not be both set. when one loopback mode is set - * the other one should be disabled. - * @param speed PHY speed for loopback mode. - * @param enable True to enable, false to disable. - * @retval kStatus_Success PHY loopback success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable); - -/*! - * @brief Gets the PHY link status. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param status The link up or down status of the PHY. - * - true the link is up. - * - false the link is down. - * @retval kStatus_Success PHY get link status success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); - -/*! - * @brief Gets the PHY link speed and duplex. - * - * @param base ENET peripheral base address. - * @param phyAddr The PHY address. - * @param speed The address of PHY link speed. - * @param duplex The link duplex of PHY. - * @retval kStatus_Success PHY get link speed and duplex success - * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out - */ -status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_PHY_H_ */ diff --git a/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h b/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h index b2aafbad7b..1ed1ff6671 100644 --- a/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h +++ b/bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h @@ -40,7 +40,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x40003 /* RT-Thread Components */ @@ -78,11 +78,9 @@ #define RT_USING_SERIAL #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_CPUTIME +#define RT_USING_PHY #define RT_USING_PIN -/* Using WiFi */ - - /* Using USB */ @@ -95,12 +93,19 @@ /* Socket abstraction layer */ +/* Network interface device */ + +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 + /* light weight TCP/IP stack */ -/* Modbus master and slave stack */ - - /* AT commands */ @@ -163,6 +168,7 @@ /* Onboard Peripheral Drivers */ + /* Board extended module Drivers */ diff --git a/bsp/imxrt/imxrt1064-nxp-evk/README.md b/bsp/imxrt/imxrt1064-nxp-evk/README.md index 37a5e3d1dd..e5b51dbe0d 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/README.md +++ b/bsp/imxrt/imxrt1064-nxp-evk/README.md @@ -39,7 +39,7 @@ | :----------------- | :----------: | :------------------------------------- | | USB 转串口 | 支持 | | | SPI Flash | 支持 | | -| 以太网 | 暂不支持 | | +| 以太网 | 支持 | | | SD卡 | 暂不支持 | | | CAN | 暂不支持 | | | **片上外设** | **支持情况** | **备注** | diff --git a/bsp/imxrt/imxrt1064-nxp-evk/SConstruct b/bsp/imxrt/imxrt1064-nxp-evk/SConstruct index 01c823f118..92ab729ed1 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/SConstruct +++ b/bsp/imxrt/imxrt1064-nxp-evk/SConstruct @@ -66,5 +66,8 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SCons # include drivers objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) +# include peripherals +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'peripherals', 'SConscript'))) + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c b/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c index 12c9d0df52..1b373138f2 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c +++ b/bsp/imxrt/imxrt1064-nxp-evk/applications/main.c @@ -18,6 +18,7 @@ int main(void) { +#ifndef PHY_USING_KSZ8081 /* set LED0 pin mode to output */ rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); @@ -28,6 +29,7 @@ int main(void) rt_pin_write(LED0_PIN, PIN_LOW); rt_thread_mdelay(500); } +#endif } void reboot(void) diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig b/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig index 7bfd46cf4b..5c660b91c7 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig @@ -37,7 +37,49 @@ menu "On-chip Peripheral Drivers" endmenu menu "Onboard Peripheral Drivers" + + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_NETDEV + default n + + + if BSP_USING_ETH + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y + + if BSP_USING_PHY + config PHY_DEVICE_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_USING_KSZ8081 + bool "i.MX RT1064EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_RESET_PORT + int "indicate port of reset" + default 1 + + config PHY_RESET_PIN + int "indicate pin of reset" + default 9 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + + endif + endif endmenu menu "Board extended module Drivers" diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c b/bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c index 88dc4624c3..c26370df1c 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c @@ -1,3 +1,10 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + /* * How to setup clock using clock driver functions: * @@ -15,15 +22,15 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v5.0 +product: Clocks v4.1 processor: MIMXRT1064xxxxA package_id: MIMXRT1064DVL6A mcu_data: ksdk2_0 -processor_version: 5.0.1 +processor_version: 0.0.0 +board: MIMXRT1064-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "clock_config.h" -#include "fsl_iomuxc.h" /******************************************************************************* * Definitions @@ -57,35 +64,23 @@ outputs: - {id: CLK_1M.outFreq, value: 1 MHz} - {id: CLK_24M.outFreq, value: 24 MHz} - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} -- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz} - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 264 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2880/11 MHz} - {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} @@ -95,10 +90,10 @@ outputs: settings: - {id: CCM.AHB_PODF.scale, value: '1', locked: true} - {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI2_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} - {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true} - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} -- {id: CCM.LCDIF_PODF.scale, value: '8', locked: true} -- {id: CCM.LCDIF_PRED.scale, value: '7', locked: true} - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} - {id: CCM.SEMC_PODF.scale, value: '8'} @@ -107,6 +102,7 @@ settings: - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.div, value: '22'} - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} @@ -182,6 +178,77 @@ void BOARD_BootClockRUN(void) while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { } + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; /* Set AHB_PODF. */ CLOCK_SetDiv(kCLOCK_AhbDiv, 0); /* Disable IPG clock gate. */ @@ -193,8 +260,14 @@ void BOARD_BootClockRUN(void) CLOCK_SetDiv(kCLOCK_IpgDiv, 3); /* Set ARM_PODF. */ CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); /* Set PERIPH_CLK2_PODF. */ CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); /* Disable PERCLK clock gate. */ CLOCK_DisableClock(kCLOCK_Gpt1); CLOCK_DisableClock(kCLOCK_Gpt1S); @@ -203,6 +276,8 @@ void BOARD_BootClockRUN(void) CLOCK_DisableClock(kCLOCK_Pit); /* Set PERCLK_PODF. */ CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); /* Disable USDHC1 clock gate. */ CLOCK_DisableClock(kCLOCK_Usdhc1); /* Set USDHC1_PODF. */ @@ -241,9 +316,9 @@ void BOARD_BootClockRUN(void) /* Disable Flexspi2 clock gate. */ CLOCK_DisableClock(kCLOCK_FlexSpi2); /* Set FLEXSPI2_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 0); /* Set Flexspi2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3); + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); #endif /* Disable CSI clock gate. */ CLOCK_DisableClock(kCLOCK_Csi); @@ -325,9 +400,9 @@ void BOARD_BootClockRUN(void) /* Disable LCDIF clock gate. */ CLOCK_DisableClock(kCLOCK_LcdPixel); /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 6); + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 7); + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); /* Set Lcdif pre clock source. */ CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); /* Disable SPDIF clock gate. */ @@ -356,85 +431,6 @@ void BOARD_BootClockRUN(void) CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); /* Set Pll3 sw clock source. */ CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); -#endif - /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged. - * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Set Enet2 output divider. */ - CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); - /* Enable Enet2 output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); /* Set lvds1 clock source. */ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); /* Set clock out1 divider. */ @@ -451,26 +447,6 @@ void BOARD_BootClockRUN(void) CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; /* Disable clock out2. */ CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET1 Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); - /* Set ENET2 Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; } diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/SConscript b/bsp/imxrt/imxrt1064-nxp-evk/board/SConscript index 4f8e797f9a..050a6c10bc 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/SConscript +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/SConscript @@ -13,7 +13,7 @@ MCUX_Config/pin_mux.c CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] -CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'STD=C99', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1'] +CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1'] if rtconfig.CROSS_TOOL == 'keil': CPPDEFINES.append('__FPU_PRESENT=1') diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/board.c b/bsp/imxrt/imxrt1064-nxp-evk/board/board.c index a56282ea00..603cd856c5 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/board.c +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/board.c @@ -12,6 +12,8 @@ #include #include "board.h" #include "pin_mux.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" #ifdef BSP_USING_DMA #include "fsl_dmamux.h" @@ -109,6 +111,347 @@ void imxrt_dma_init(void) EDMA_Init(DMA0, &config); } #endif + +#ifdef BSP_USING_LPUART +void imxrt_uart_pins_init(void) +{ +#ifdef BSP_USING_LPUART1 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +#endif +#ifdef BSP_USING_LPUART2 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_02_LPUART2_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_03_LPUART2_RX, + 0x10B0u); + +#endif +#ifdef BSP_USING_LPUART3 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_06_LPUART3_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_07_LPUART3_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART4 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_00_LPUART4_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_01_LPUART4_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART5 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_12_LPUART5_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_13_LPUART5_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_12_LPUART5_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_13_LPUART5_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART6 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_02_LPUART6_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_03_LPUART6_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_02_LPUART6_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_03_LPUART6_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART7 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_31_LPUART7_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_32_LPUART7_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_31_LPUART7_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_32_LPUART7_RX, + 0x10B0u); +#endif +#ifdef BSP_USING_LPUART8 + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_10_LPUART8_TX, + 0x10B0u); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B1_11_LPUART8_RX, + 0x10B0u); +#endif +} +#endif /* BSP_USING_LPUART */ + +#ifdef BSP_USING_ETH +void imxrt_enet_pins_init(void) +{ + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x31u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/6 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Disabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ + 0xB829u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ +} + +#ifndef BSP_USING_PHY +void imxrt_enet_phy_reset_by_gpio(void) +{ + gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; + + GPIO_PinInit(GPIO1, 9, &gpio_config); + GPIO_PinInit(GPIO1, 10, &gpio_config); + /* pull up the ENET_INT before RESET. */ + GPIO_WritePinOutput(GPIO1, 10, 1); + GPIO_WritePinOutput(GPIO1, 9, 0); + rt_thread_delay(100); + GPIO_WritePinOutput(GPIO1, 9, 1); +} +#endif /* BSP_USING_PHY */ + +#endif /* BSP_USING_ETH */ + +#ifdef BSP_USING_PHY +void imxrt_phy_pins_init( void ) +{ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_B0_00 PAD functional properties : */ + 0x10B0u); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +} +#endif /* BSP_USING_PHY */ + /** * This function will initial rt1050 board. */ @@ -121,6 +464,18 @@ void rt_hw_board_init() NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); +#ifdef BSP_USING_LPUART + imxrt_uart_pins_init(); +#endif + +#ifdef BSP_USING_ETH + imxrt_enet_pins_init(); +#endif + +#ifdef BSP_USING_PHY + imxrt_phy_pins_init(); +#endif + #ifdef BSP_USING_DMA imxrt_dma_init(); #endif diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/board.h b/bsp/imxrt/imxrt1064-nxp-evk/board/board.h index 692569842b..dd7b7d3e56 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/board.h +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/board.h @@ -45,5 +45,11 @@ extern int heap_end; void rt_hw_board_init(void); +#ifdef BSP_USING_ETH +void imxrt_enet_pins_init(void); +void imxrt_enet_phy_reset_by_gpio(void); + +#endif + #endif diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct index 7b7bf4fbba..f36201c200 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct @@ -66,6 +66,8 @@ #define m_data3_start 0x00000000 ; ITCM 128KB #define m_data3_size 0x00020000 +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 /* Sizes */ #if (defined(__stack_size__)) @@ -124,7 +126,7 @@ LR_IROM1 m_text_start m_text_size RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} ; ncache RW data - RW_m_ncache m_data2_start m_data2_size + RW_m_ncache m_ncache_start m_ncache_size { * (NonCacheable.init) * (NonCacheable) diff --git a/bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h b/bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h new file mode 100644 index 0000000000..477987b4e7 --- /dev/null +++ b/bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-05 zylx The first version for STM32F4xx + * 2019-4-25 misonyo port to IMXRT + */ + +#ifndef SDRAM_PORT_H__ +#define SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U) +/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */ +#define SDRAM_REGION kSEMC_SDRAM_CS0 +/* CS pin: kSEMC_MUXCSX0/1/2/3 */ +#define SDRAM_CS_PIN kSEMC_MUXCSX0 +/* size(kbyte):32MB = 32*1024*1KBytes */ +#define SDRAM_SIZE ((uint32_t)0x8000) +/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */ +#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit +/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */ +#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit +/* cas latency clock number: kSEMC_LatencyOne/Two/Three */ +#define SDRAM_CAS_LATENCY kSEMC_LatencyThree + +/* Timing configuration for W9825G6KH */ +/* TRP:precharge to active command time (ns) */ +#define SDRAM_TRP 18 +/* TRCD:active to read/write command delay time (ns) */ +#define SDRAM_TRCD 18 +/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */ +#define SDRAM_REFRESH_RECOVERY 67 +/* TWR:write recovery time (ns). */ +#define SDRAM_TWR 12 +/* TRAS:active to precharge command time (ns). */ +#define SDRAM_TRAS 42 +/* TRC time (ns). */ +#define SDRAM_TRC 60 +/* active to active time (ns). */ +#define SDRAM_ACT2ACT 60 +/* refresh time (ns). 64ms */ +#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192 + +#endif /* SDRAM_PORT_H__ */ diff --git a/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py b/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py index eeef72b0c6..9689ac0bcb 100644 --- a/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py +++ b/bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py @@ -48,7 +48,7 @@ if PLATFORM == 'gcc': DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' - LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds -Xlinker -print-memory-usage' CPATH = '' LPATH = '' @@ -57,8 +57,8 @@ if PLATFORM == 'gcc': AFLAGS += ' -D__STARTUP_CLEAR_BSS' if BUILD == 'debug': - CFLAGS += ' -gdwarf-2' - AFLAGS += ' -gdwarf-2' + CFLAGS += ' -g' + AFLAGS += ' -g' CFLAGS += ' -O0' else: CFLAGS += ' -O2 -Os' diff --git a/bsp/imxrt/libraries/drivers/SConscript b/bsp/imxrt/libraries/drivers/SConscript index 893a25b3a7..3328d2af08 100644 --- a/bsp/imxrt/libraries/drivers/SConscript +++ b/bsp/imxrt/libraries/drivers/SConscript @@ -44,6 +44,9 @@ if GetDepend('BSP_USING_LCD'): if GetDepend('BSP_USING_ETH'): src += ['drv_eth.c'] + +if GetDepend('BSP_USING_PHY'): + src += ['drv_mdio.c'] if GetDepend('BSP_USING_AUDIO'): src += ['drv_sai.c'] diff --git a/bsp/imxrt/libraries/drivers/drv_eth.c b/bsp/imxrt/libraries/drivers/drv_eth.c index 4558312be8..ecff2bb6ab 100644 --- a/bsp/imxrt/libraries/drivers/drv_eth.c +++ b/bsp/imxrt/libraries/drivers/drv_eth.c @@ -7,6 +7,7 @@ * Date Author Notes * 2017-10-10 Tanek the first version * 2019-5-10 misonyo add DMA TX and RX function + * 2020-10-14 wangqiang use phy device in phy monitor thread */ #include @@ -19,7 +20,6 @@ #include "fsl_enet.h" #include "fsl_gpio.h" -#include "fsl_phy.h" #include "fsl_cache.h" #include "fsl_iomuxc.h" #include "fsl_common.h" @@ -537,31 +537,47 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) return NULL; } +#ifdef BSP_USING_PHY +static struct rt_phy_device *phy_dev = RT_NULL; static void phy_monitor_thread_entry(void *parameter) { - phy_speed_t speed; - phy_duplex_t duplex; - bool link = false; + rt_uint32_t speed; + rt_uint32_t duplex; + rt_bool_t link = RT_FALSE; - imxrt_enet_phy_reset_by_gpio(); - - PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); + phy_dev = (struct rt_phy_device *)rt_device_find("rtt-phy"); + if ((RT_NULL == phy_dev) || (RT_NULL == phy_dev->ops)) + { + // TODO print warning information + LOG_E("Can not find phy device called \"rtt-phy\""); + return ; + } + if (RT_NULL == phy_dev->ops->init) + { + LOG_E("phy driver error!"); + return ; + } + rt_phy_status status = phy_dev->ops->init(imxrt_eth_device.enet_base, PHY_DEVICE_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk)); + if (PHY_STATUS_OK != status) + { + LOG_E("Phy device initialize unsuccessful!\n"); + return ; + } while (1) { - bool new_link = false; - status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link); + rt_bool_t new_link = RT_FALSE; + rt_phy_status status = phy_dev->ops->get_link_status(&new_link); - if ((status == kStatus_Success) && (link != new_link)) + if ((PHY_STATUS_OK == status) && (link != new_link)) { link = new_link; - if (link) // link up + if (link) // link up { - PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, - PHY_ADDRESS, &speed, &duplex); + phy_dev->ops->get_link_speed_duplex(&speed, &duplex); - if (kPHY_Speed10M == speed) + if (PHY_SPEED_10M == speed) { dbg_log(DBG_LOG, "10M\n"); } @@ -570,7 +586,7 @@ static void phy_monitor_thread_entry(void *parameter) dbg_log(DBG_LOG, "100M\n"); } - if (kPHY_HalfDuplex == duplex) + if (PHY_HALF_DUPLEX == duplex) { dbg_log(DBG_LOG, "half dumplex\n"); } @@ -579,8 +595,7 @@ static void phy_monitor_thread_entry(void *parameter) dbg_log(DBG_LOG, "full dumplex\n"); } - if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) - || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) + if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) { imxrt_eth_device.speed = (enet_mii_speed_t)speed; imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; @@ -605,6 +620,7 @@ static void phy_monitor_thread_entry(void *parameter) rt_thread_delay(RT_TICK_PER_SECOND * 2); } } +#endif static int rt_hw_imxrt_eth_init(void) { @@ -657,6 +673,7 @@ static int rt_hw_imxrt_eth_init(void) /* start phy monitor */ { + #ifdef BSP_USING_PHY rt_thread_t tid; tid = rt_thread_create("phy", phy_monitor_thread_entry, @@ -666,6 +683,7 @@ static int rt_hw_imxrt_eth_init(void) 2); if (tid != RT_NULL) rt_thread_startup(tid); + #endif } return state; @@ -673,50 +691,47 @@ static int rt_hw_imxrt_eth_init(void) INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init); #endif -#ifdef RT_USING_FINSH +#if defined(RT_USING_FINSH) && defined(RT_USING_PHY) #include -void phy_read(uint32_t phyReg) +void phy_read(rt_uint32_t phy_reg) { - uint32_t data; - status_t status; + rt_uint32_t data; - status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data); - if (kStatus_Success == status) + rt_phy_status status = phy_dev->ops->read(phy_reg, &data); + if (PHY_STATUS_OK == status) { - rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data); + rt_kprintf("PHY_Read: %02X --> %08X", phy_reg, data); } else { - rt_kprintf("PHY_Read: %02X --> faild", phyReg); + rt_kprintf("PHY_Read: %02X --> faild", phy_reg); } } -void phy_write(uint32_t phyReg, uint32_t data) +void phy_write(rt_uint32_t phy_reg, rt_uint32_t data) { - status_t status; - - status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data); - if (kStatus_Success == status) + rt_phy_status status = phy_dev->ops->write(phy_reg, data); + if (PHY_STATUS_OK == status) { - rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data); + rt_kprintf("PHY_Write: %02X --> %08X\n", phy_reg, data); } else { - rt_kprintf("PHY_Write: %02X --> faild\n", phyReg); + rt_kprintf("PHY_Write: %02X --> faild\n", phy_reg); } } void phy_dump(void) { - uint32_t data; - status_t status; + rt_uint32_t data; + rt_phy_status status; int i; for (i = 0; i < 32; i++) { - status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data); - if (kStatus_Success != status) + status = phy_dev->ops->read(i, &data); + if (PHY_STATUS_OK != status) { rt_kprintf("phy_dump: %02X --> faild", i); break; @@ -730,10 +745,11 @@ void phy_dump(void) { rt_kprintf("%02X --> %08X\n", i, data); } - } } +#endif +#if defined(RT_USING_FINSH) && defined(RT_USING_LWIP) void enet_reg_dump(void) { ENET_Type *enet_base = imxrt_eth_device.enet_base; diff --git a/bsp/imxrt/libraries/drivers/drv_mdio.c b/bsp/imxrt/libraries/drivers/drv_mdio.c new file mode 100644 index 0000000000..3e98d57f29 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/drv_mdio.c @@ -0,0 +1,160 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-29 WangQiang the first version + * + */ + +#include + +#ifdef BSP_USING_PHY + +#define LOG_TAG "drv.mdio" +#include + +#include +#include "drv_mdio.h" + + + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0x3FFFFFFU + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +extern uint32_t ENET_GetInstance(ENET_Type *base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +static rt_bool_t rt_hw_mdio_init(void *bus, rt_uint32_t src_clock_hz) +{ + struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus; + uint32_t instance = ENET_GetInstance((ENET_Type *)(bus_obj->hw_obj)); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set SMI first. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + ENET_SetSMI((ENET_Type *)(bus_obj->hw_obj), src_clock_hz, RT_FALSE); + + return RT_TRUE; +} + +static rt_size_t rt_hw_mdio_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + RT_ASSERT(data); + struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus; + + rt_uint32_t counter; + rt_uint32_t *data_ptr = (rt_uint32_t *)data; + + if (4 != size) + { + return 0; + } + + /* Clear the MII interrupt event. */ + ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead((ENET_Type *)(bus_obj->hw_obj), addr, reg, kENET_MiiReadValidFrame); + + /* Wait for MII complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus((ENET_Type *)(bus_obj->hw_obj)) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + // return kStatus_PHY_SMIVisitTimeout; + return 0; + } + + /* Get data from MII register. */ + *data_ptr = ENET_ReadSMIData((ENET_Type *)(bus_obj->hw_obj)); + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus((ENET_Type *)bus_obj->hw_obj, ENET_EIR_MII_MASK); + + return 4; +} + + +static rt_size_t rt_hw_mdio_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus; + uint32_t counter; + rt_uint32_t *data_ptr = (rt_uint32_t *)data; + + if (4 != size) + { + return 0; + } + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite((ENET_Type *)(bus_obj->hw_obj), addr, reg, kENET_MiiWriteValidFrame, *data_ptr); + + /* Wait for SMI complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--) + { + if (ENET_GetInterruptStatus((ENET_Type *)(bus_obj->hw_obj)) & ENET_EIR_MII_MASK) + { + break; + } + } + + /* Check for timeout. */ + if (!counter) + { + return 0; + } + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK); + + return size; +} + +static struct rt_mdio_bus_ops imxrt_mdio_ops = +{ + .init = rt_hw_mdio_init, + .read = rt_hw_mdio_read, + .write = rt_hw_mdio_write, + .uninit = RT_NULL, +}; + +static rt_mdio_t mdio_bus; + +rt_mdio_t *rt_hw_mdio_register(void *hw_obj, char *name) +{ + mdio_bus.hw_obj = hw_obj; + mdio_bus.name = name; + mdio_bus.ops = &imxrt_mdio_ops; + return &mdio_bus; +} + +rt_mdio_t *rt_hw_mdio_get(void) +{ + return &mdio_bus; +} + +#endif diff --git a/bsp/imxrt/libraries/drivers/drv_mdio.h b/bsp/imxrt/libraries/drivers/drv_mdio.h new file mode 100644 index 0000000000..a1623cfc2c --- /dev/null +++ b/bsp/imxrt/libraries/drivers/drv_mdio.h @@ -0,0 +1,25 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-29 WangQiang the first version + * + */ + +#ifndef DRV_MDIO_H__ +#define DRV_MDIO_H__ + +#include + +#include "fsl_enet.h" + + +rt_mdio_t *rt_hw_mdio_register(void *hw_obj, char *name); + +rt_mdio_t *rt_hw_mdio_get(void); + +#endif /*DRV_MDIO_H__*/ diff --git a/bsp/imxrt/libraries/peripherals/SConscript b/bsp/imxrt/libraries/peripherals/SConscript new file mode 100644 index 0000000000..13d040cf2b --- /dev/null +++ b/bsp/imxrt/libraries/peripherals/SConscript @@ -0,0 +1,16 @@ +from building import * + +src = [] +cwd = [] +CPPDEFINES = [] + +cwd = GetCurrentDir() + +if GetDepend('BSP_USING_PHY') and GetDepend('PHY_USING_KSZ8081'): + src += ['phyksz8081.c'] + +path = [cwd] + +group = DefineGroup('Peripherals', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/libraries/peripherals/phyksz8081.c b/bsp/imxrt/libraries/peripherals/phyksz8081.c new file mode 100644 index 0000000000..3735965663 --- /dev/null +++ b/bsp/imxrt/libraries/peripherals/phyksz8081.c @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-14 wangqiang the first version + */ + +#include + +#ifdef PHY_USING_KSZ8081 + +#include +#include "drv_gpio.h" +#include "drv_mdio.h" + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ +#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ + +#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ + +/*! @brief Defines the mask flag in basic control register. */ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ +#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ + +/*!@brief Defines the mask flag of operation mode in control two register*/ +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ +#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ +#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ +#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) + +/*! @brief Defines the mask flag in basic status register. */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ + + + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 0x3FFFFFFU + +/* defined the Reset pin, PORT and PIN config by menuconfig */ +#define RESET_PIN GET_PIN(PHY_RESET_PORT, PHY_RESET_PIN) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + + +/******************************************************************************* + * Variables + ******************************************************************************/ +static struct rt_phy_device phy_ksz8081; + +/******************************************************************************* + * Code + ******************************************************************************/ + + + +static inline rt_bool_t read_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t *value) +{ + if (4 != bus->ops->read(bus, addr, reg_id, value, 4)) + { + return RT_FALSE; + } + return RT_TRUE; +} + +static inline rt_bool_t write_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t value) +{ + if (4 != bus->ops->write(bus, addr, reg_id, &value, 4)) + { + return RT_FALSE; + } + return RT_TRUE; +} + +static rt_phy_status rt_phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) +{ + rt_bool_t ret; + rt_phy_status result; + rt_uint32_t counter = PHY_TIMEOUT_COUNT; + rt_uint32_t id_reg = 0; + rt_uint32_t time_delay; + rt_uint32_t bss_reg; + rt_uint32_t ctl_reg = 0; + + // reset phy device by gpio + rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT); + rt_pin_write(RESET_PIN, PIN_LOW); + rt_thread_mdelay(100); + rt_pin_write(RESET_PIN, PIN_HIGH); + + rt_mdio_t *mdio_bus = rt_hw_mdio_register(object, "phy_mdio"); + if (RT_NULL == mdio_bus) + { + return PHY_STATUS_FAIL; + } + phy_ksz8081.bus = mdio_bus; + phy_ksz8081.addr = phy_addr; + ret = mdio_bus->ops->init(mdio_bus, src_clock_hz); + if ( !ret ) + { + return PHY_STATUS_FAIL; + } + + /* Initialization after PHY stars to work. */ + while ((id_reg != PHY_CONTROL_ID1) && (counter != 0)) + { + phy_ksz8081.ops->read(PHY_ID1_REG, &id_reg); + counter--; + } + + if (!counter) + { + return PHY_STATUS_FAIL; + } + + /* Reset PHY. */ + counter = PHY_TIMEOUT_COUNT; + result = phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (PHY_STATUS_OK == result) + { + #if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) + rt_uint32_t data = 0; + result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data); + if (PHY_STATUS_FAIL == result) + { + return PHY_STATUS_FAIL; + } + result = phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); + if (PHY_STATUS_FAIL == result) + { + return PHY_STATUS_FAIL; + } + #endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ + + /* Set the negotiation. */ + result = phy_ksz8081.ops->write(PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); + if (PHY_STATUS_OK == result) + { + result = phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + if (PHY_STATUS_OK == result) + { + /* Check auto negotiation complete. */ + while (counter--) + { + result = phy_ksz8081.ops->read(PHY_BASICSTATUS_REG, &bss_reg); + if (PHY_STATUS_OK == result) + { + phy_ksz8081.ops->read(PHY_CONTROL1_REG, &ctl_reg); + if (((bss_reg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctl_reg & PHY_LINK_READY_MASK)) + { + /* Wait a moment for Phy status stable. */ + for (time_delay = 0; time_delay < PHY_TIMEOUT_COUNT; time_delay++) + { + __ASM("nop"); + } + break; + } + } + + if (!counter) + { + return PHY_STATUS_FAIL; + } + } + } + } + } + + return PHY_STATUS_OK; +} + + +static rt_phy_status rt_phy_read(rt_uint32_t reg, rt_uint32_t *data) +{ + rt_mdio_t *mdio_bus = phy_ksz8081.bus; + rt_uint32_t device_id = phy_ksz8081.addr; + + if (read_reg(mdio_bus, device_id, reg, data)) + { + return PHY_STATUS_OK; + } + return PHY_STATUS_FAIL; +} + +static rt_phy_status rt_phy_write(rt_uint32_t reg, rt_uint32_t data) +{ + rt_mdio_t *mdio_bus = phy_ksz8081.bus; + rt_uint32_t device_id = phy_ksz8081.addr; + + if (write_reg(mdio_bus, device_id, reg, data)) + { + return PHY_STATUS_OK; + } + return PHY_STATUS_FAIL; +} + +static rt_phy_status rt_phy_loopback(rt_uint32_t mode, rt_uint32_t speed, rt_bool_t enable) +{ + rt_uint32_t data = 0; + rt_phy_status result; + + /* Set the loop mode. */ + if (enable) + { + if (PHY_LOCAL_LOOP == mode) + { + if (PHY_SPEED_100M == speed) + { + data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + else + { + data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + return phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, data); + } + else + { + /* First read the current status in control register. */ + result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data); + if (PHY_STATUS_OK == result) + { + return phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (PHY_LOCAL_LOOP == mode) + { + /* First read the current status in control register. */ + result = phy_ksz8081.ops->read(PHY_BASICCONTROL_REG, &data); + if (PHY_STATUS_OK == result) + { + data &= ~PHY_BCTL_LOOP_MASK; + return phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data); + if (PHY_STATUS_OK == result) + { + return phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + return result; +} + +static rt_phy_status get_link_status(rt_bool_t *status) +{ + rt_phy_status result; + rt_uint32_t data; + + /* Read the basic status register. */ + result = phy_ksz8081.ops->read(PHY_BASICSTATUS_REG, &data); + if (PHY_STATUS_OK == result) + { + if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) + { + /* link down. */ + *status = RT_FALSE; + } + else + { + /* link up. */ + *status = RT_TRUE; + } + } + return result; +} +static rt_phy_status get_link_speed_duplex(rt_uint32_t *speed, rt_uint32_t *duplex) +{ + rt_phy_status result = PHY_STATUS_OK; + rt_uint32_t data, ctl_reg; + + /* Read the control two register. */ + result = phy_ksz8081.ops->read(PHY_CONTROL1_REG, &ctl_reg); + if (PHY_STATUS_OK == result) + { + data = ctl_reg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* Full duplex. */ + *duplex = PHY_FULL_DUPLEX; + } + else + { + /* Half duplex. */ + *duplex = PHY_HALF_DUPLEX; + } + + data = ctl_reg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* 100M speed. */ + *speed = PHY_SPEED_100M; + } + else + { /* 10M speed. */ + *speed = PHY_SPEED_10M; + } + } + + return result; +} + +static struct rt_phy_ops phy_ops = +{ + .init = rt_phy_init, + .read = rt_phy_read, + .write = rt_phy_write, + .loopback = rt_phy_loopback, + .get_link_status = get_link_status, + .get_link_speed_duplex = get_link_speed_duplex, +}; + +static int rt_phy_ksz8081_register( void ) +{ + phy_ksz8081.ops = &phy_ops; + rt_hw_phy_register(&phy_ksz8081, "rtt-phy"); + return 1; +} + +INIT_DEVICE_EXPORT(rt_phy_ksz8081_register); + + + +#endif /* PHY_USING_KSZ8081 */ diff --git a/bsp/imxrt/tools/sdk_dist.py b/bsp/imxrt/tools/sdk_dist.py index 89b7da4356..b663628504 100644 --- a/bsp/imxrt/tools/sdk_dist.py +++ b/bsp/imxrt/tools/sdk_dist.py @@ -21,3 +21,6 @@ def dist_do_building(BSP_ROOT, dist_dir=None): print("=> copy bsp drivers") bsp_copy_files(os.path.join(library_path, 'drivers'), os.path.join(library_dir, 'drivers')) shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig')) + + print("=> copy bsp peripherals") + bsp_copy_files(os.path.join(library_path, 'peripherals'), os.path.join(library_dir, 'peripherals')) diff --git a/bsp/nrf5x/libraries/drivers/SConscript b/bsp/nrf5x/libraries/drivers/SConscript index f8629162f2..611b52d993 100644 --- a/bsp/nrf5x/libraries/drivers/SConscript +++ b/bsp/nrf5x/libraries/drivers/SConscript @@ -9,8 +9,10 @@ src = Split(""" """) if GetDepend(['BSP_USING_UART']): - src += ['drv_uart.c'] - + if GetDepend(['NRFX_USING_UART']): + src += ['drv_uart.c'] + else: + src += ['drv_uarte.c'] if GetDepend(['BSP_USING_ON_CHIP_FLASH']): src += ['drv_flash.c'] diff --git a/bsp/nrf5x/libraries/drivers/drv_spi.c b/bsp/nrf5x/libraries/drivers/drv_spi.c index a77be4b26d..ce4bfeb575 100644 --- a/bsp/nrf5x/libraries/drivers/drv_spi.c +++ b/bsp/nrf5x/libraries/drivers/drv_spi.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2020-05-22 Sherman first version + * 2020-11-02 xckhmf fixed bug */ #include @@ -19,6 +20,7 @@ #ifdef BSP_USING_SPI +#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) static struct nrfx_drv_spi_config spi_config[] = { #ifdef BSP_USING_SPI0 @@ -117,12 +119,12 @@ static rt_err_t spi_configure(struct rt_spi_device *device, nrfx_spi_t spi = spi_bus_obj[index].spi; nrfx_spi_config_t config = NRFX_SPI_DEFAULT_CONFIG(bsp_spi_pin[index].sck_pin, - bsp_spi_pin[index].mosi_pin, bsp_spi_pin[index].miso_pin, bsp_spi_pin[index].ss_pin); + bsp_spi_pin[index].mosi_pin, bsp_spi_pin[index].miso_pin, NRFX_SPI_PIN_NOT_USED); /* spi config ss pin */ - if(device->user_data != RT_NULL) + if(device->parent.user_data != RT_NULL) { - config.ss_pin = (rt_uint8_t)device->user_data; + nrf_gpio_cfg_output((uint32_t)device->parent.user_data); } /* spi config bit order */ if(configuration->mode & RT_SPI_MSB) @@ -198,32 +200,43 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * RT_ASSERT(device->bus->parent.user_data != RT_NULL); rt_uint8_t index = spi_index_find(device->bus); + nrfx_err_t nrf_ret; RT_ASSERT(index != 0xFF); nrfx_spi_t * p_instance = &spi_bus_obj[index].spi; nrfx_spi_xfer_desc_t p_xfer_desc; + + if(message->cs_take == 1) + { + nrf_gpio_pin_clear((uint32_t)device->parent.user_data); + } + p_xfer_desc.p_rx_buffer = message->recv_buf; + p_xfer_desc.rx_length = message->length; + p_xfer_desc.p_tx_buffer = message->send_buf; + p_xfer_desc.tx_length = message->length ; if(message->send_buf == RT_NULL) { - p_xfer_desc.p_rx_buffer = message->recv_buf; - p_xfer_desc.rx_length = message->length; - - p_xfer_desc.p_tx_buffer = RT_NULL; p_xfer_desc.tx_length = 0; } + if(message->recv_buf == RT_NULL) + { + p_xfer_desc.rx_length = 0; + } + + nrf_ret = nrfx_spi_xfer(p_instance, &p_xfer_desc, 0); + if(message->cs_release == 1) + { + nrf_gpio_pin_set((uint32_t)device->parent.user_data); + } + + if( NRFX_SUCCESS != nrf_ret) + { + return 0; + } else { - p_xfer_desc.p_tx_buffer = message->send_buf; - p_xfer_desc.tx_length = message->length ; - - p_xfer_desc.p_rx_buffer = RT_NULL; - p_xfer_desc.rx_length = 0; + return message->length; } - - nrfx_err_t nrf_ret = nrfx_spi_xfer(p_instance, &p_xfer_desc, 0); - if( NRFX_SUCCESS == nrf_ret) - return message->length; - else - return 0; } /* spi bus callback function */ @@ -260,6 +273,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, { RT_ASSERT(bus_name != RT_NULL); RT_ASSERT(device_name != RT_NULL); + RT_ASSERT(ss_pin != RT_NULL); rt_err_t result; struct rt_spi_device *spi_device; @@ -267,8 +281,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); /* initialize the cs pin */ - spi_device->user_data = (void*)ss_pin; - result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, RT_NULL); + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void*)ss_pin); if (result != RT_EOK) { LOG_E("%s attach to %s faild, %d", device_name, bus_name, result); @@ -278,4 +291,5 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, return result; } +#endif /* BSP_USING_SPI0 || BSP_USING_SPI1 || BSP_USING_SPI2 */ #endif /*BSP_USING_SPI*/ diff --git a/bsp/nrf5x/libraries/drivers/drv_uart.c b/bsp/nrf5x/libraries/drivers/drv_uart.c index 08c7148353..7f7d4ba7d6 100644 --- a/bsp/nrf5x/libraries/drivers/drv_uart.c +++ b/bsp/nrf5x/libraries/drivers/drv_uart.c @@ -165,7 +165,10 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg) return RT_EOK; } - +RT_WEAK int uart_putc_hook(rt_uint8_t *ch) +{ + return -1; +} static int _uart_putc(struct rt_serial_device *serial, char c) { drv_uart_cfg_t *instance = NULL; @@ -180,6 +183,7 @@ static int _uart_putc(struct rt_serial_device *serial, char c) nrf_uart_event_clear(instance->uart.p_reg, NRF_UART_EVENT_TXDRDY); nrf_uart_task_trigger(instance->uart.p_reg, NRF_UART_TASK_STARTTX); nrf_uart_txd_set(instance->uart.p_reg, (uint8_t)c); + uart_putc_hook((rt_uint8_t *)&c); while (!nrf_uart_event_check(instance->uart.p_reg, NRF_UART_EVENT_TXDRDY)) { //wait for TXD send @@ -187,6 +191,11 @@ static int _uart_putc(struct rt_serial_device *serial, char c) return rtn; } +RT_WEAK int uart_getc_hook(rt_uint8_t *ch) +{ + return -1; +}; + static int _uart_getc(struct rt_serial_device *serial) { int ch = -1; @@ -202,7 +211,22 @@ static int _uart_getc(struct rt_serial_device *serial) ch = instance->rx_byte; instance->rx_length--; } - return ch; + + if (-1 != ch) + { + return ch; + } + else + { + if (-1 == uart_getc_hook((rt_uint8_t *)&ch)) + { + return -1; + } + else + { + return ch; + } + } } static struct rt_uart_ops _uart_ops = { diff --git a/bsp/nrf5x/libraries/drivers/drv_uarte.c b/bsp/nrf5x/libraries/drivers/drv_uarte.c new file mode 100644 index 0000000000..680ae599f3 --- /dev/null +++ b/bsp/nrf5x/libraries/drivers/drv_uarte.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-28 xckhmf Modify for + * 2020-10-31 xckhmf Support for UART1 + * + */ +#include +#include +#include "drv_uart.h" + +#ifdef BSP_USING_UART +#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) +typedef struct +{ + struct rt_serial_device *serial; + nrfx_uarte_t uarte_instance; + uint8_t rx_length; + uint8_t tx_buffer[1]; + uint8_t rx_buffer[1]; + bool isInit; + uint32_t rx_pin; + uint32_t tx_pin; +} drv_uart_cb_t; + +#ifdef BSP_USING_UART0 +static struct rt_serial_device m_serial_0; +drv_uart_cb_t m_uarte0_cb = { + .uarte_instance = NRFX_UARTE_INSTANCE(0), + .rx_length = 0, + .rx_pin = BSP_UART0_RX_PIN, + .tx_pin = BSP_UART0_TX_PIN, + .isInit = false +}; +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +static struct rt_serial_device m_serial_1; +drv_uart_cb_t m_uarte1_cb = { + .uarte_instance = NRFX_UARTE_INSTANCE(1), + .rx_length = 0, + .rx_pin = BSP_UART1_RX_PIN, + .tx_pin = BSP_UART1_TX_PIN, + .isInit = false +}; +#endif /* BSP_USING_UART1 */ + +static void uarte_evt_handler(nrfx_uarte_event_t const * p_event, + void * p_context) +{ + drv_uart_cb_t *p_cb = RT_NULL; + p_cb = (drv_uart_cb_t*)p_context; + switch (p_event->type) + { + case NRFX_UARTE_EVT_RX_DONE: + p_cb->rx_length = p_event->data.rxtx.bytes; + if(p_cb->serial->parent.open_flag&RT_DEVICE_FLAG_INT_RX) + { + rt_hw_serial_isr(p_cb->serial, RT_SERIAL_EVENT_RX_IND); + } + (void)nrfx_uarte_rx(&(p_cb->uarte_instance), p_cb->rx_buffer, 1); + break; + + case NRFX_UARTE_EVT_ERROR: + (void)nrfx_uarte_rx(&(p_cb->uarte_instance), p_cb->rx_buffer, 1); + break; + + case NRFX_UARTE_EVT_TX_DONE: + if(p_cb->serial->parent.open_flag&RT_DEVICE_FLAG_INT_TX) + { + rt_hw_serial_isr(p_cb->serial, RT_SERIAL_EVENT_TX_DONE); + } + break; + + default: + break; + } +} + +static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + nrfx_uarte_config_t config = NRFX_UARTE_DEFAULT_CONFIG(NRF_UARTE_PSEL_DISCONNECTED,\ + NRF_UARTE_PSEL_DISCONNECTED); + + drv_uart_cb_t *p_cb = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + if (serial->parent.user_data == RT_NULL) + { + return -RT_ERROR; + } + p_cb = (drv_uart_cb_t*)serial->parent.user_data; + if(p_cb->isInit) + { + nrfx_uarte_uninit(&(p_cb->uarte_instance)); + p_cb->isInit = false; + } + + switch (cfg->baud_rate) + { + case BAUD_RATE_2400: + config.baudrate = NRF_UARTE_BAUDRATE_2400; + break; + case BAUD_RATE_4800: + config.baudrate = NRF_UARTE_BAUDRATE_4800; + break; + case BAUD_RATE_9600: + config.baudrate = NRF_UARTE_BAUDRATE_9600; + break; + case BAUD_RATE_19200: + config.baudrate = NRF_UARTE_BAUDRATE_19200; + break; + case BAUD_RATE_38400: + config.baudrate = NRF_UARTE_BAUDRATE_38400; + break; + case BAUD_RATE_57600: + config.baudrate = NRF_UARTE_BAUDRATE_57600; + break; + case BAUD_RATE_115200: + config.baudrate = NRF_UARTE_BAUDRATE_115200; + break; + case BAUD_RATE_230400: + config.baudrate = NRF_UARTE_BAUDRATE_230400; + break; + case BAUD_RATE_460800: + config.baudrate = NRF_UARTE_BAUDRATE_460800; + break; + case BAUD_RATE_921600: + config.baudrate = NRF_UARTE_BAUDRATE_921600; + break; + case BAUD_RATE_2000000: + case BAUD_RATE_3000000: + return -RT_EINVAL; + default: + config.baudrate = NRF_UARTE_BAUDRATE_115200; + break; + } + config.hal_cfg.parity = (cfg->parity == PARITY_NONE)?\ + NRF_UARTE_PARITY_EXCLUDED:NRF_UARTE_PARITY_INCLUDED; + config.hal_cfg.hwfc = NRF_UARTE_HWFC_DISABLED; + config.pselrxd = p_cb->rx_pin; + config.pseltxd = p_cb->tx_pin; + config.p_context = (void *)p_cb; + + nrfx_uarte_init(&(p_cb->uarte_instance),(nrfx_uarte_config_t const *)&config,uarte_evt_handler); + nrfx_uarte_rx(&(p_cb->uarte_instance),p_cb->rx_buffer,1); + p_cb->isInit = true; + return RT_EOK; +} + +static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg) +{ + drv_uart_cb_t *p_cb = RT_NULL; + RT_ASSERT(serial != RT_NULL); + + if (serial->parent.user_data == RT_NULL) + { + return -RT_ERROR; + } + p_cb = (drv_uart_cb_t*)serial->parent.user_data; + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + break; + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + break; + + case RT_DEVICE_CTRL_CUSTOM: + if ((rt_uint32_t)(arg) == UART_CONFIG_BAUD_RATE_9600) + { + p_cb->serial->config.baud_rate = 9600; + } + else if ((rt_uint32_t)(arg) == UART_CONFIG_BAUD_RATE_115200) + { + p_cb->serial->config.baud_rate = 115200; + } + _uart_cfg(serial, &(serial->config)); + break; + + case RT_DEVICE_CTRL_PIN: + _uart_cfg(serial, &(serial->config)); + break; + + case RT_DEVICE_POWERSAVE: + if(p_cb->isInit) + { + nrfx_uarte_uninit(&(p_cb->uarte_instance)); + p_cb->isInit = false; + } + break; + + case RT_DEVICE_WAKEUP: + _uart_cfg(serial, &(serial->config)); + break; + + default: + return -RT_ERROR; + } + + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial, char c) +{ + drv_uart_cb_t *p_cb = RT_NULL; + int rtn = -1; + RT_ASSERT(serial != RT_NULL); + + if (serial->parent.user_data != RT_NULL) + { + p_cb = (drv_uart_cb_t*)serial->parent.user_data; + } + p_cb->tx_buffer[0] = c; + nrfx_uarte_tx(&(p_cb->uarte_instance),p_cb->tx_buffer,1); + if(!(serial->parent.open_flag&RT_DEVICE_FLAG_INT_TX)) + { + while(nrfx_uarte_tx_in_progress(&(p_cb->uarte_instance))) + { + } + } + return rtn; +} + +static int _uart_getc(struct rt_serial_device *serial) +{ + int ch = -1; + drv_uart_cb_t *p_cb = RT_NULL; + RT_ASSERT(serial != RT_NULL); + + if (serial->parent.user_data != RT_NULL) + { + p_cb = (drv_uart_cb_t*)serial->parent.user_data; + } + if(p_cb->rx_length) + { + ch = p_cb->rx_buffer[0]; + p_cb->rx_length--; + } + return ch; +} + +static struct rt_uart_ops _uart_ops = { + _uart_cfg, + _uart_ctrl, + _uart_putc, + _uart_getc +}; + +void rt_hw_uart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef BSP_USING_UART0 + m_serial_0.config = config; + m_serial_0.ops = &_uart_ops; + m_uarte0_cb.serial = &m_serial_0; + rt_hw_serial_register(&m_serial_0, "uart0", \ + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX , &m_uarte0_cb); +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 + m_serial_1.config = config; + m_serial_1.ops = &_uart_ops; + m_uarte1_cb.serial = &m_serial_1; + rt_hw_serial_register(&m_serial_1, "uart1", \ + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |RT_DEVICE_FLAG_INT_TX, &m_uarte1_cb); +#endif /* BSP_USING_UART1 */ + +} +#endif /* defined(BSP_USING_UART0) || defined(BSP_USING_UART1) */ +#endif /* BSP_USING_UART */ diff --git a/bsp/nrf5x/libraries/drivers/drv_uarte.h b/bsp/nrf5x/libraries/drivers/drv_uarte.h new file mode 100644 index 0000000000..f07ddafd79 --- /dev/null +++ b/bsp/nrf5x/libraries/drivers/drv_uarte.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-28 xckhmf Modify for + * 2020-10-31 xckhmf Support for UART1 + * + */ +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define RT_DEVICE_CTRL_CUSTOM 0x20 +#define RT_DEVICE_CTRL_PIN 0x21 +#define RT_DEVICE_POWERSAVE 0x22 +#define RT_DEVICE_WAKEUP 0x23 + +#define UART_CONFIG_BAUD_RATE_9600 1 +#define UART_CONFIG_BAUD_RATE_115200 2 + +void rt_hw_uart_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/nrf5x/nrf52832/.config b/bsp/nrf5x/nrf52832/.config index 0638293bd5..dcc634dfbc 100644 --- a/bsp/nrf5x/nrf52832/.config +++ b/bsp/nrf5x/nrf52832/.config @@ -120,6 +120,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -195,15 +196,12 @@ CONFIG_RT_USING_LIBC=y # # IoT - internet of things # -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -230,7 +228,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -243,7 +240,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -265,7 +262,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set # # security packages @@ -274,7 +270,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -309,8 +304,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set # # system packages @@ -321,7 +314,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -334,9 +326,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set # # peripheral libraries and drivers @@ -378,7 +367,6 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set @@ -386,11 +374,6 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set # # miscellaneous packages @@ -427,31 +410,36 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set # # Hardware Drivers Config # CONFIG_SOC_NRF52832=y +CONFIG_NRFX_CLOCK_ENABLED=1 +CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7 +CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1 CONFIG_SOC_NORDIC=y # # Onboard Peripheral Drivers # # CONFIG_BSP_USING_JLINK_TO_USART is not set -# CONFIG_BSP_USING_QSPI_FLASH is not set # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_NRFX_GPIOTE_ENABLED=1 +# CONFIG_BSP_USING_SAADC is not set # CONFIG_BSP_USING_PWM is not set -# CONFIG_BSP_USING_SOFTDEVICE is not set CONFIG_BSP_USING_UART=y +CONFIG_NRFX_USING_UART=y +# CONFIG_NRFX_USING_UARTE is not set +CONFIG_NRFX_UART_ENABLED=1 CONFIG_BSP_USING_UART0=y +CONFIG_NRFX_UART0_ENABLED=1 CONFIG_BSP_UART0_RX_PIN=8 CONFIG_BSP_UART0_TX_PIN=6 -# CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set @@ -463,3 +451,8 @@ CONFIG_MCU_FLASH_SIZE_KB=1024 CONFIG_MCU_SRAM_START_ADDRESS=0x20000000 CONFIG_MCU_SRAM_SIZE_KB=256 CONFIG_MCU_FLASH_PAGE_SIZE=0x1000 +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +CONFIG_BLE_STACK_USING_NULL=y +# CONFIG_BSP_USING_SOFTDEVICE is not set +# CONFIG_BSP_USING_NIMBLE is not set diff --git a/bsp/nrf5x/nrf52832/board/Kconfig b/bsp/nrf5x/nrf52832/board/Kconfig index 2750ceacc2..9f7b1e89d7 100644 --- a/bsp/nrf5x/nrf52832/board/Kconfig +++ b/bsp/nrf5x/nrf52832/board/Kconfig @@ -157,12 +157,24 @@ menu "On-chip Peripheral Drivers" endif - menuconfig BSP_USING_UART - bool "Enable UART" + config BSP_USING_UART + bool "Enable UART" default y select RT_USING_SERIAL - - if BSP_USING_UART + if BSP_USING_UART + choice + prompt "UART or UARTE" + default NRFX_USING_UART + help + Select the UART or UARTE + config NRFX_USING_UART + bool "UART" + + config NRFX_USING_UARTE + bool "UARTE" + endchoice + endif + if BSP_USING_UART&&NRFX_USING_UART config NRFX_UART_ENABLED int default 1 @@ -183,9 +195,28 @@ menu "On-chip Peripheral Drivers" range 0 31 default 6 endif - config BSP_USING_UART1 - bool "Enable UART1" - default n + endif + if BSP_USING_UART&&NRFX_USING_UARTE + config NRFX_UARTE_ENABLED + int + default 1 + + config BSP_USING_UART0 + bool "Enable UARTE0" + default n + if BSP_USING_UART0 + config NRFX_UARTE0_ENABLED + int + default 1 + config BSP_UART0_RX_PIN + int "uarte0 rx pin number" + range 0 31 + default 8 + config BSP_UART0_TX_PIN + int "uarte0 tx pin number" + range 0 31 + default 6 + endif endif config BSP_USING_SPI diff --git a/bsp/nrf5x/nrf52832/rtconfig.h b/bsp/nrf5x/nrf52832/rtconfig.h index a42405872e..2626384351 100644 --- a/bsp/nrf5x/nrf52832/rtconfig.h +++ b/bsp/nrf5x/nrf52832/rtconfig.h @@ -152,6 +152,9 @@ /* Hardware Drivers Config */ #define SOC_NRF52832 +#define NRFX_CLOCK_ENABLED 1 +#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#define NRFX_CLOCK_CONFIG_LF_SRC 1 #define SOC_NORDIC /* Onboard Peripheral Drivers */ @@ -160,8 +163,12 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define NRFX_GPIOTE_ENABLED 1 #define BSP_USING_UART +#define NRFX_USING_UART +#define NRFX_UART_ENABLED 1 #define BSP_USING_UART0 +#define NRFX_UART0_ENABLED 1 #define BSP_UART0_RX_PIN 8 #define BSP_UART0_TX_PIN 6 @@ -172,5 +179,6 @@ #define MCU_SRAM_START_ADDRESS 0x20000000 #define MCU_SRAM_SIZE_KB 256 #define MCU_FLASH_PAGE_SIZE 0x1000 +#define BLE_STACK_USING_NULL #endif diff --git a/bsp/nrf5x/nrf52840/.config b/bsp/nrf5x/nrf52840/.config index 3c4fb174f4..27b3c06963 100644 --- a/bsp/nrf5x/nrf52840/.config +++ b/bsp/nrf5x/nrf52840/.config @@ -65,7 +65,7 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x40003 # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -120,6 +120,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set # CONFIG_RT_USING_DAC is not set @@ -195,15 +196,12 @@ CONFIG_RT_USING_LIBC=y # # IoT - internet of things # -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -230,7 +228,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set @@ -243,7 +240,7 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -273,7 +270,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -308,7 +304,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_URLENCODE is not set # # system packages @@ -319,7 +314,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -332,8 +326,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set # # peripheral libraries and drivers @@ -353,8 +345,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LITTLED is not set # CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRF5X_SDK_V1300 is not set -# CONFIG_PKG_USING_NRF5X_SDK_LATEST_VERSION is not set CONFIG_PKG_USING_NRFX=y CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx" CONFIG_PKG_USING_NRFX_V210=y @@ -384,10 +374,6 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set # # miscellaneous packages @@ -429,6 +415,10 @@ CONFIG_PKG_NRFX_VER="v2.1.0" # Hardware Drivers Config # CONFIG_SOC_NRF52840=y +CONFIG_NRFX_CLOCK_ENABLED=1 +CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7 +CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1 +CONFIG_SOC_NORDIC=y # # Onboard Peripheral Drivers @@ -440,12 +430,17 @@ CONFIG_SOC_NRF52840=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_SOFTDEVICE is not set +CONFIG_NRFX_GPIOTE_ENABLED=1 +# CONFIG_BSP_USING_SAADC is not set +# CONFIG_BSP_USING_PWM is not set CONFIG_BSP_USING_UART=y +CONFIG_NRFX_USING_UART=y +# CONFIG_NRFX_USING_UARTE is not set +CONFIG_NRFX_UART_ENABLED=1 CONFIG_BSP_USING_UART0=y +CONFIG_NRFX_UART0_ENABLED=1 CONFIG_BSP_UART0_RX_PIN=8 CONFIG_BSP_UART0_TX_PIN=6 -# CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set @@ -457,3 +452,8 @@ CONFIG_MCU_FLASH_SIZE_KB=1024 CONFIG_MCU_SRAM_START_ADDRESS=0x20000000 CONFIG_MCU_SRAM_SIZE_KB=256 CONFIG_MCU_FLASH_PAGE_SIZE=0x1000 +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +CONFIG_BLE_STACK_USING_NULL=y +# CONFIG_BSP_USING_SOFTDEVICE is not set +# CONFIG_BSP_USING_NIMBLE is not set diff --git a/bsp/nrf5x/nrf52840/board/Kconfig b/bsp/nrf5x/nrf52840/board/Kconfig index 9ec3b5c71f..4015c3fa95 100644 --- a/bsp/nrf5x/nrf52840/board/Kconfig +++ b/bsp/nrf5x/nrf52840/board/Kconfig @@ -194,12 +194,24 @@ menu "On-chip Peripheral Drivers" endif - menuconfig BSP_USING_UART - bool "Enable UART" + config BSP_USING_UART + bool "Enable UART" default y select RT_USING_SERIAL - - if BSP_USING_UART + if BSP_USING_UART + choice + prompt "UART or UARTE" + default NRFX_USING_UART + help + Select the UART or UARTE + config NRFX_USING_UART + bool "UART" + + config NRFX_USING_UARTE + bool "UARTE" + endchoice + endif + if BSP_USING_UART&&NRFX_USING_UART config NRFX_UART_ENABLED int default 1 @@ -220,9 +232,44 @@ menu "On-chip Peripheral Drivers" range 0 31 default 6 endif + endif + if BSP_USING_UART&&NRFX_USING_UARTE + config NRFX_UARTE_ENABLED + int + default 1 + + config BSP_USING_UART0 + bool "Enable UARTE0" + default n + if BSP_USING_UART0 + config NRFX_UARTE0_ENABLED + int + default 1 + config BSP_UART0_RX_PIN + int "uarte0 rx pin number" + range 0 31 + default 8 + config BSP_UART0_TX_PIN + int "uarte0 tx pin number" + range 0 31 + default 6 + endif config BSP_USING_UART1 - bool "Enable UART1" - default n + bool "Enable UARTE1" + default n + if BSP_USING_UART1 + config NRFX_UARTE1_ENABLED + int + default 1 + config BSP_UART1_RX_PIN + int "uarte1 rx pin number" + range 0 31 + default 7 + config BSP_UART1_TX_PIN + int "uarte1 tx pin number" + range 0 31 + default 5 + endif endif config BSP_USING_SPI diff --git a/bsp/nrf5x/nrf52840/rtconfig.h b/bsp/nrf5x/nrf52840/rtconfig.h index 225164b8ed..f283b19f71 100644 --- a/bsp/nrf5x/nrf52840/rtconfig.h +++ b/bsp/nrf5x/nrf52840/rtconfig.h @@ -152,6 +152,10 @@ /* Hardware Drivers Config */ #define SOC_NRF52840 +#define NRFX_CLOCK_ENABLED 1 +#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#define SOC_NORDIC /* Onboard Peripheral Drivers */ @@ -159,8 +163,12 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define NRFX_GPIOTE_ENABLED 1 #define BSP_USING_UART +#define NRFX_USING_UART +#define NRFX_UART_ENABLED 1 #define BSP_USING_UART0 +#define NRFX_UART0_ENABLED 1 #define BSP_UART0_RX_PIN 8 #define BSP_UART0_TX_PIN 6 @@ -171,5 +179,6 @@ #define MCU_SRAM_START_ADDRESS 0x20000000 #define MCU_SRAM_SIZE_KB 256 #define MCU_FLASH_PAGE_SIZE 0x1000 +#define BLE_STACK_USING_NULL #endif diff --git a/bsp/raspberry-pi/raspi4-32/.config b/bsp/raspberry-pi/raspi4-32/.config index e0db6a3e95..60727061a2 100644 --- a/bsp/raspberry-pi/raspi4-32/.config +++ b/bsp/raspberry-pi/raspi4-32/.config @@ -112,12 +112,29 @@ CONFIG_DFS_FILESYSTEMS_MAX=2 CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 CONFIG_DFS_FD_MAX=16 # CONFIG_RT_USING_DFS_MNTTABLE is not set -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS_NFS is not set # # Device Drivers @@ -140,14 +157,20 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set CONFIG_RT_USING_SPI=y # CONFIG_RT_USING_QSPI is not set # CONFIG_RT_USING_SPI_MSD is not set # CONFIG_RT_USING_SFUD is not set # CONFIG_RT_USING_ENC28J60 is not set # CONFIG_RT_USING_SPI_WIFI is not set -# CONFIG_RT_USING_WDT is not set +CONFIG_RT_USING_WDT=y # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_TOUCH is not set @@ -170,6 +193,7 @@ CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set @@ -185,17 +209,79 @@ CONFIG_RT_USING_POSIX=y # # Network interface device # -# CONFIG_RT_USING_NETDEV is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set # # light weight TCP/IP stack # -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP141 is not set +CONFIG_RT_USING_LWIP202=y +# CONFIG_RT_USING_LWIP212 is not set +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_RT_LWIP_DEBUG is not set # # AT commands # # CONFIG_RT_USING_AT is not set +# CONFIG_LWIP_USING_DHCPD is not set # # VBUS(Virtual Software BUS) @@ -216,7 +302,9 @@ CONFIG_RT_USING_POSIX=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set @@ -262,7 +350,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set @@ -284,6 +372,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_CAPNP is not set # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set # CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set # # security packages @@ -292,6 +384,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -308,6 +401,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set # # tools packages @@ -326,7 +420,9 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set # CONFIG_PKG_USING_LUNAR_CALENDAR is not set # CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set # CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set # # system packages @@ -337,6 +433,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set @@ -349,6 +446,11 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SYSWATCH is not set # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set # CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_PPOOL is not set # # peripheral libraries and drivers @@ -386,6 +488,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_RPLIDAR is not set # CONFIG_PKG_USING_AS608 is not set # CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set # CONFIG_PKG_USING_MULTI_RTIMER is not set @@ -393,6 +496,15 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_BEEP is not set # CONFIG_PKG_USING_EASYBLINK is not set # CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set # # miscellaneous packages @@ -429,6 +541,11 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_VT100 is not set # CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set # # Privated Packages of RealThread @@ -443,6 +560,8 @@ CONFIG_RT_USING_POSIX=y # # Network Utilities # +# CONFIG_PKG_USING_MDNS is not set +# CONFIG_PKG_USING_UPNP is not set # CONFIG_PKG_USING_WICED is not set # CONFIG_PKG_USING_CLOUDSDK is not set # CONFIG_PKG_USING_POWER_MANAGER is not set @@ -461,6 +580,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_ZBAR is not set # CONFIG_PKG_USING_MCF is not set # CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set CONFIG_BCM2711_SOC=y # CONFIG_BSP_SUPPORT_FPU is not set @@ -487,11 +610,13 @@ CONFIG_BSP_USING_SPI0_DEVICE0=y # CONFIG_BSP_USING_SPI0_DEVICE1 is not set CONFIG_BSP_USING_CORETIMER=y # CONFIG_BSP_USING_SYSTIMER is not set -# CONFIG_BSP_USING_WDT is not set +CONFIG_BSP_USING_WDT=y # CONFIG_BSP_USING_RTC is not set -# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDIO0=y # # Board Peripheral Drivers # -# CONFIG_BSP_USING_HDMI is not set +CONFIG_BSP_USING_HDMI=y +CONFIG_BSP_USING_HDMI_DISPLAY=y diff --git a/bsp/raspberry-pi/raspi4-32/README.md b/bsp/raspberry-pi/raspi4-32/README.md index 1034b3f467..94eac22e67 100644 --- a/bsp/raspberry-pi/raspi4-32/README.md +++ b/bsp/raspberry-pi/raspi4-32/README.md @@ -20,17 +20,8 @@ scons 来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、kernel7.img文件。 -## 3. 执行 - -### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡 - -首先下载镜像 - -* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb) -* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe) -* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg) - -### 3.2 准备好串口线 +## 3. 环境搭建 +### 3.1 准备好串口线 目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示： @@ -38,27 +29,90 @@ scons 串口参数： 115200 8N1 ，硬件和软件流控为关。 -### 3.3 程序下载 +### 3.2 RTT固件放在SD卡运行 -当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下： +首先需要准备一张空的32GB以下的SD卡，如果不想自己制作启动固件，可以直接从百度网盘上下载boot的固件。 ``` -enable_uart=1 -arm_64bit=0 -kernel_addr=0x8000 -kernel=kernel7.img -core_freq=250 +链接：https://pan.baidu.com/s/1PxgvXAChUIOgueNXhgMs8w +提取码：pioj ``` -按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息： +解压后将sd目录下的文件拷贝到sd卡即可。以后每次编译后，将生成的kernel7.img进行替换即可。上电后可以看到程序正常运行。 -```text -heap: 0x00044270 - 0x04044270 +### 3.3 RTT程序用uboot加载 + +为了调试方便，已经将uboot引导程序放入uboot目录下，直接将这些文件放到sd卡中即可。 + +需要注意的以下步骤： + +**1.电脑上启动tftp服务器** + +windows系统电脑上可以安装tftpd搭建tftp服务器。将目录指定到`bsp\raspberry-pi\raspi4-32`。 + +**2.修改设置uboot** + +在控制台输入下列命令： + +``` +setenv bootcmd "dhcp 0x00200000 x.x.x.x:kernel7.img;dcache flush;go 0x00200000" +saveenv +reset +``` + +其中`x.x.x.x`为tftp服务器的pc的ip地址。 + +**3.修改链接脚本** + +将树莓派`bsp\raspberry-pi\raspi4-32\link.ld`的文件链接地址改为`0x200000`。 + +``` +SECTIONS +{ + . = 0x8000; + . = ALIGN(4096); + . + . + . +} +``` + +改为 + +``` +SECTIONS +{ + . = 0x200000; + . = ALIGN(4096); + . + . + . +} +``` + +重新编译程序： + +``` +scons -c +scons +``` + +**3.插入网线** + +上述准备完成后，将网线插入，保证开发板和tftp服务器在同一个网段的路由器上。上电后uboot可以自动从tftp服务器上获取固件，然后开始执行了。 + +完成后可以看到串口的输出信息 + +``` +heap: 0x000607e8 - 0x040607e8 \ | / - RT - Thread Operating System - / | \ 4.0.3 build May 25 2020 + / | \ 4.0.3 build Oct 27 2020 2006 - 2020 Copyright by rt-thread team +[I/SDIO] SD card capacity 31205376 KB. +found part[0], begin: 1048576, size: 29.777GB +file system initialization done! Hi, this is RT-Thread!! msh /> ``` @@ -71,8 +125,16 @@ msh /> | GPIO | 支持 | - | | SPI | 支持 | SPI0 | | MAILBOX | 支持 | - | +| WATCHDOG | 支持 | - | +| HDMI | 支持 | - | +| SDIO | 支持 | - | +| ETH | 支持 | - | -## 5. 联系人信息 +## 5. 注意事项 + +目前rt-thread程序可以使用的内存在100MB以内，可以通过调整`board.c`中`platform_mem_desc`表的数据进行相关内存的映射以及修改`board.h`来确定程序使用的堆栈大小。目前在地址`0x08000000`处的1M空间被映射成非cache区供树莓派4的CPU与GPU通信的消息管道。若需要扩大系统内存使用，可自行修改代码进行调整。 + +## 6. 联系人信息 维护人：[bernard][5] diff --git a/bsp/raspberry-pi/raspi4-32/applications/main.c b/bsp/raspberry-pi/raspi4-32/applications/main.c index 9664e67d01..15dc74dc58 100644 --- a/bsp/raspberry-pi/raspi4-32/applications/main.c +++ b/bsp/raspberry-pi/raspi4-32/applications/main.c @@ -12,8 +12,20 @@ #include #include +#define ACTLED (42) + int main(int argc, char** argv) { rt_kprintf("Hi, this is RT-Thread!!\n"); - return 0; + + rt_pin_mode(ACTLED, PIN_MODE_OUTPUT); + + while(1) + { + rt_pin_write(ACTLED, PIN_HIGH); + rt_thread_mdelay(1000); + rt_pin_write(ACTLED, PIN_LOW); + rt_thread_mdelay(1000); + } + return RT_EOK; } diff --git a/bsp/raspberry-pi/raspi4-32/applications/mnt.c b/bsp/raspberry-pi/raspi4-32/applications/mnt.c new file mode 100644 index 0000000000..ae224e8e89 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/applications/mnt.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 bernard the first version + */ + +#include + +#ifdef BSP_USING_SDIO0 +#include + +int mnt_init(void) +{ + rt_thread_delay(RT_TICK_PER_SECOND); + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("file system initialization done!\n"); + } + + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.c b/bsp/raspberry-pi/raspi4-32/driver/board.c index 7a3524126d..ed25fa4176 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/board.c +++ b/bsp/raspberry-pi/raspi4-32/driver/board.c @@ -19,8 +19,11 @@ struct mem_desc platform_mem_desc[] = { {0x0, 0x6400000, 0x0, NORMAL_MEM}, - {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM},//uart gpio - {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic + {0x8000000, 0x8800000, 0x8000000, DEVICE_MEM}, //mbox msg + {0x0EA00000, 0x0EE00000, 0x0EA00000, DEVICE_MEM}, //framebuffer + {0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac + {0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM}, //peripheral + {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic }; const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c new file mode 100644 index 0000000000..a26c3c8519 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c @@ -0,0 +1,637 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 bigmagic first version + */ + +#include +#include +#include +#include +#include + +#include "mbox.h" +#include "raspi4.h" +#include "drv_eth.h" + +#define RECV_CACHE_BUF (1024) +#define SEND_DATA_NO_CACHE (0x08200000) +#define RECV_DATA_NO_CACHE (0x08400000) +#define DMA_DISC_ADDR_SIZE (4 * 1024 *1024) + +#define RX_DESC_BASE (MAC_REG + GENET_RX_OFF) +#define TX_DESC_BASE (MAC_REG + GENET_TX_OFF) + +#define MAX_ADDR_LEN (6) + +#define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16)) +#define lower_32_bits(n) ((rt_uint32_t)(n)) + +#define BIT(nr) (1UL << (nr)) + +static rt_uint32_t tx_index = 0; +static rt_uint32_t rx_index = 0; +static rt_uint32_t index_flag = 0; + +static rt_uint32_t send_cache_pbuf[RECV_CACHE_BUF]; + +struct rt_eth_dev +{ + struct eth_device parent; + rt_uint8_t dev_addr[MAX_ADDR_LEN]; + char *name; + void *iobase; + int state; + int index; + struct rt_timer link_timer; + struct rt_timer rx_poll_timer; + void *priv; +}; +static struct rt_eth_dev eth_dev; +static struct rt_semaphore sem_lock; + +static inline rt_uint32_t read32(void *addr) +{ + return (*((volatile unsigned int*)(addr))); +} + +static inline void write32(void *addr, rt_uint32_t value) +{ + (*((volatile unsigned int*)(addr))) = value; +} + +void eth_rx_irq(void *param) +{ + eth_device_ready(ð_dev.parent); +} + +/* We only support RGMII (as used on the RPi4). */ +static int bcmgenet_interface_set(void) +{ + int phy_mode = PHY_INTERFACE_MODE_RGMII; + switch (phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + write32(MAC_REG + SYS_PORT_CTRL,PORT_MODE_EXT_GPHY); + break; + default: + rt_kprintf("unknown phy mode: %d\n", MAC_REG); + return -1; + } + return 0; +} + +static void bcmgenet_umac_reset(void) +{ + rt_uint32_t reg; + reg = read32(MAC_REG + SYS_RBUF_FLUSH_CTRL); + reg |= BIT(1); + write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg); + + reg &= ~BIT(1); + write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),reg); + + DELAY_MICROS(10); + write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),0); + DELAY_MICROS(10); + write32(MAC_REG + UMAC_CMD, 0); + write32(MAC_REG + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN)); + DELAY_MICROS(2); + write32(MAC_REG + UMAC_CMD, 0); + /* clear tx/rx counter */ + write32(MAC_REG + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT); + write32(MAC_REG + UMAC_MIB_CTRL, 0); + write32(MAC_REG + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE); + /* init rx registers, enable ip header optimization */ + reg = read32(MAC_REG + RBUF_CTRL); + reg |= RBUF_ALIGN_2B; + write32(MAC_REG + RBUF_CTRL, reg); + write32(MAC_REG + RBUF_TBUF_SIZE_CTRL, 1); +} + +static void bcmgenet_disable_dma(void) +{ + rt_uint32_t tdma_reg = 0, rdma_reg = 0; + + tdma_reg = read32(MAC_REG + TDMA_REG_BASE + DMA_CTRL); + tdma_reg &= ~(1UL << DMA_EN); + write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, tdma_reg); + rdma_reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL); + rdma_reg &= ~(1UL << DMA_EN); + write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, rdma_reg); + write32(MAC_REG + UMAC_TX_FLUSH, 1); + DELAY_MICROS(100); + write32(MAC_REG + UMAC_TX_FLUSH, 0); +} + +static void bcmgenet_enable_dma(void) +{ + rt_uint32_t reg = 0; + rt_uint32_t dma_ctrl = 0; + + dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; + write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, dma_ctrl); + + reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL); + write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg); +} + +static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value) +{ + int count = 10000; + rt_uint32_t val; + val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |(reg << MDIO_REG_SHIFT) | (0xffff & value); + write32(MAC_REG + MDIO_CMD, val); + + rt_uint32_t reg_val = read32(MAC_REG + MDIO_CMD); + reg_val = reg_val | MDIO_START_BUSY; + write32(MAC_REG + MDIO_CMD, reg_val); + + while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + DELAY_MICROS(1); + + reg_val = read32(MAC_REG + MDIO_CMD); + + return reg_val & 0xffff; + +} + +static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg) +{ + int count = 10000; + rt_uint32_t val = 0; + rt_uint32_t reg_val = 0; + + val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); + write32(MAC_REG + MDIO_CMD, val); + + reg_val = read32(MAC_REG + MDIO_CMD); + reg_val = reg_val | MDIO_START_BUSY; + write32(MAC_REG + MDIO_CMD, reg_val); + + while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count)) + DELAY_MICROS(1); + + reg_val = read32(MAC_REG + MDIO_CMD); + + return reg_val & 0xffff; +} + +static int bcmgenet_gmac_write_hwaddr(void) +{ + //{0xdc,0xa6,0x32,0x28,0x22,0x50}; + rt_uint8_t addr[6]; + rt_uint32_t reg; + bcm271x_mbox_hardware_get_mac_address(&addr[0]); + + reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; + write32(MAC_REG + UMAC_MAC0, reg); + + reg = addr[4] << 8 | addr[5]; + write32(MAC_REG + UMAC_MAC1, reg); + return 0; +} + +static int get_ethernet_uid(void) +{ + rt_uint32_t uid_high = 0; + rt_uint32_t uid_low = 0; + rt_uint32_t uid = 0; + + uid_high = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_HIGH); + uid_low = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_LOW); + uid = (uid_high << 16 | uid_low); + + if(BCM54213PE_VERSION_B1 == uid) + { + rt_kprintf("version is B1\n"); + } + return uid; +} + +static void bcmgenet_mdio_init(void) +{ + rt_uint32_t ret = 0; + /*get ethernet uid*/ + ret = get_ethernet_uid(); + if(ret == 0) + { + return; + } + /* reset phy */ + bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET); + /* read control reg */ + bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL); + /* reset phy again */ + bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET); + /* read control reg */ + bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL); + /* read status reg */ + bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS); + /* read status reg */ + bcmgenet_mdio_read(1, BCM54213PE_IEEE_EXTENDED_STATUS); + bcmgenet_mdio_read(1, BCM54213PE_AUTO_NEGOTIATION_ADV); + bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS); + bcmgenet_mdio_read(1, BCM54213PE_CONTROL); + /* half full duplex capability */ + bcmgenet_mdio_write(1, BCM54213PE_CONTROL, (CONTROL_HALF_DUPLEX_CAPABILITY | CONTROL_FULL_DUPLEX_CAPABILITY)); + bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL); + /* set mii control */ + bcmgenet_mdio_write(1,BCM54213PE_MII_CONTROL,(MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART| MII_CONTROL_PHY_FULL_DUPLEX| MII_CONTROL_SPEED_SELECTION)); +} + +static void rx_ring_init(void) +{ + write32(MAC_REG + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR,0x0 ); + write32(MAC_REG + RDMA_READ_PTR, 0x0); + write32(MAC_REG + RDMA_WRITE_PTR, 0x0); + write32(MAC_REG + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1); + + write32(MAC_REG + RDMA_PROD_INDEX, 0x0); + write32(MAC_REG + RDMA_CONS_INDEX, 0x0); + write32(MAC_REG + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(MAC_REG + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE); + write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q); +} + +static void tx_ring_init(void) +{ + write32(MAC_REG + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH); + write32(MAC_REG + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0); + write32(MAC_REG + TDMA_READ_PTR, 0x0); + write32(MAC_REG + TDMA_READ_PTR, 0x0); + write32(MAC_REG + TDMA_READ_PTR, 0x0); + write32(MAC_REG + TDMA_WRITE_PTR, 0x0); + write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR,TX_DESCS * DMA_DESC_SIZE / 4 - 1); + write32(MAC_REG + TDMA_PROD_INDEX, 0x0); + write32(MAC_REG + TDMA_CONS_INDEX, 0x0); + write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH,0x1); + write32(MAC_REG + TDMA_FLOW_PERIOD,0x0); + write32(MAC_REG + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH); + write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q); +} + +static void rx_descs_init(void) +{ + char *rxbuffs = (char *)RECV_DATA_NO_CACHE; + rt_uint32_t len_stat, i; + void *desc_base = (void *)RX_DESC_BASE; + + len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; + for (i = 0; i < RX_DESCS; i++) { + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO), lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI),upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH])); + write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS),len_stat); + } +} + +static int phy_startup(void) +{ + int count = 1000000; + while ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) && (--count)) + DELAY_MICROS(1); + if(count > 0) + { + rt_kprintf("bcmgenet: PHY startup ok!\n"); + } + else + { + rt_kprintf("bcmgenet: PHY startup err!\n"); + return 1; + } + + if(bcmgenet_mdio_read(1, BCM54213PE_STATUS) == 0) + { + //todo + } + else + { + rt_kprintf("bcmgenet: BCM54213PE_STATUS err!\n"); + } + + if(bcmgenet_mdio_read(1, BCM54213PE_CONTROL) == (CONTROL_FULL_DUPLEX_CAPABILITY| CONTROL_HALF_DUPLEX_CAPABILITY)) + { + //todo + } + else + { + rt_kprintf("bcmgenet: BCM54213PE_CONTROL err!\n"); + } + + return 0; +} + +static int bcmgenet_adjust_link(void) +{ + rt_uint32_t speed; + rt_uint32_t phy_dev_speed = SPEED_100; + + switch (phy_dev_speed) { + case SPEED_1000: + speed = UMAC_SPEED_1000; + break; + case SPEED_100: + speed = UMAC_SPEED_100; + break; + case SPEED_10: + speed = UMAC_SPEED_10; + break; + default: + rt_kprintf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev_speed); + return -1; + } + + rt_uint32_t reg1 = read32(MAC_REG + EXT_RGMII_OOB_CTRL); + //reg1 &= ~(1UL << OOB_DISABLE); + + //rt_kprintf("OOB_DISABLE is %d\n", OOB_DISABLE); + reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); + write32(MAC_REG + EXT_RGMII_OOB_CTRL, reg1); + DELAY_MICROS(1000); + write32(MAC_REG + UMAC_CMD, speed << CMD_SPEED_SHIFT); + return 0; +} + +static int bcmgenet_gmac_eth_start(void) +{ + rt_uint32_t ret; + rt_uint32_t count = 10000; + + bcmgenet_umac_reset(); + + bcmgenet_gmac_write_hwaddr(); + /* Disable RX/TX DMA and flush TX queues */ + bcmgenet_disable_dma(); + rx_ring_init(); + rx_descs_init(); + tx_ring_init(); + + /* Enable RX/TX DMA */ + bcmgenet_enable_dma(); + + /* read PHY properties over the wire from generic PHY set-up */ + ret = phy_startup(); + if (ret) { + rt_kprintf("bcmgenet: PHY startup failed: %d\n", ret); + return ret; + } + + /* Update MAC registers based on PHY property */ + ret = bcmgenet_adjust_link(); + if (ret) { + rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret); + return ret; + } + + /* wait tx index clear */ + while ((read32(MAC_REG + TDMA_CONS_INDEX) != 0) && (--count)) + DELAY_MICROS(1); + + tx_index = read32(MAC_REG + TDMA_CONS_INDEX); + write32(MAC_REG + TDMA_PROD_INDEX, tx_index); + + index_flag = read32(MAC_REG + RDMA_PROD_INDEX); + + rx_index = index_flag % 256; + + write32(MAC_REG + RDMA_CONS_INDEX, index_flag); + write32(MAC_REG + RDMA_PROD_INDEX, index_flag); + + /* Enable Rx/Tx */ + rt_uint32_t rx_tx_en; + rx_tx_en = read32(MAC_REG + UMAC_CMD); + + rx_tx_en |= (CMD_TX_EN | CMD_RX_EN); + + write32(MAC_REG + UMAC_CMD, rx_tx_en); + return 0; +} + +static rt_uint32_t prev_recv_cnt = 0; +static rt_uint32_t cur_recv_cnt = 0; +static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp) +{ + void* desc_base; + rt_uint32_t length = 0, addr = 0; + rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX); + //get next + if(prod_index == index_flag) + { + cur_recv_cnt = index_flag; + //no buff + return 0; + } + else + { + if(prev_recv_cnt == prod_index) + { + return 0; + } + + desc_base = RX_DESC_BASE + rx_index * DMA_DESC_SIZE; + length = read32(desc_base + DMA_DESC_LENGTH_STATUS); + length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; + addr = read32(desc_base + DMA_DESC_ADDRESS_LO); + /* To cater for the IP headepr alignment the hardware does. + * This would actually not be needed if we don't program + * RBUF_ALIGN_2B + */ + *packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET); + + rx_index = rx_index + 1; + if(rx_index >= 256) + { + rx_index = 0; + } + write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt); + + cur_recv_cnt = cur_recv_cnt + 1; + prev_recv_cnt = cur_recv_cnt; + + return length; + } +} + +static int bcmgenet_gmac_eth_send(void *packet, int length) +{ + void* desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE); + rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT; + + rt_uint32_t prod_index, cons; + rt_uint32_t tries = 100; + + prod_index = read32(MAC_REG + TDMA_PROD_INDEX); + + len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; + len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; + + write32((desc_base + DMA_DESC_ADDRESS_LO),SEND_DATA_NO_CACHE); + write32((desc_base + DMA_DESC_ADDRESS_HI),0); + write32((desc_base + DMA_DESC_LENGTH_STATUS),len_stat); + + if(++tx_index>= TX_DESCS) + { + tx_index = 0; + } + prod_index++; + /* Start Transmisson */ + write32(MAC_REG + TDMA_PROD_INDEX,prod_index); + + do { + cons = read32(MAC_REG + TDMA_CONS_INDEX); + } while ((cons & 0xffff) < prod_index && --tries); + if (!tries) + { + return -1; + } + return 0; +} + +static rt_err_t bcmgenet_eth_init(rt_device_t device) +{ + struct eth_device *eth_device = (struct eth_device *)device; + RT_ASSERT(eth_device != RT_NULL); + rt_uint32_t ret = 0; + rt_uint32_t hw_reg = 0; + struct rt_eth_dev *dev = ð_dev; + + /* Read GENET HW version */ + rt_uint8_t major = 0; + hw_reg = read32(MAC_REG + SYS_REV_CTRL); + major = (hw_reg >> 24) & 0x0f; + if (major != 6) { + if (major == 5) + major = 4; + else if (major == 0) + major = 1; + + rt_kprintf("Uns upported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f); + return RT_ERROR; + } + + /* set interface */ + ret = bcmgenet_interface_set(); + if (ret) + { + return ret; + } + + /* rbuf clear */ + write32(MAC_REG + SYS_RBUF_FLUSH_CTRL, 0); + + /* disable MAC while updating its registers */ + write32(MAC_REG + UMAC_CMD, 0); + /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ + write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN); + + bcmgenet_mdio_init(); + + bcmgenet_gmac_write_hwaddr(); + bcmgenet_gmac_write_hwaddr(); + + bcmgenet_gmac_eth_start(); + + //irq or poll + rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer", + eth_rx_irq, + NULL, + 1, + RT_TIMER_FLAG_PERIODIC); + + rt_timer_start(&dev->rx_poll_timer); + + return RT_EOK; +} + +static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) + { + case NIOCTL_GADDR: + if (args) rt_memcpy(args, eth_dev.dev_addr, 6); + else return -RT_ERROR; + break; + default : + break; + } + return RT_EOK; +} + +rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p) +{ + rt_uint32_t sendbuf = SEND_DATA_NO_CACHE; + /* lock eth device */ + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + //struct rt_eth_dev *dev = (struct rt_eth_dev *) device; + pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0); + rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len); + + bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len); + rt_sem_release(&sem_lock); + return RT_EOK; +} + +char recv_data[RX_BUF_LENGTH]; +struct pbuf *rt_eth_rx(rt_device_t device) +{ + int recv_len = 0; + rt_uint32_t addr_point[8]; + struct pbuf *pbuf = RT_NULL; + rt_sem_take(&sem_lock, RT_WAITING_FOREVER); + + recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]); + + if(recv_len > 0) + { + pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM); + rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len); + } + rt_sem_release(&sem_lock); + return pbuf; +} + +int rt_hw_eth_init(void) +{ + rt_uint8_t mac_addr[6]; + + rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO); + + memset(ð_dev, 0, sizeof(eth_dev)); + memset((void *)SEND_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE)); + memset((void *)RECV_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE)); + + bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]); + + eth_dev.iobase = MAC_REG; + eth_dev.name = "e0"; + eth_dev.dev_addr[0] = mac_addr[0]; + eth_dev.dev_addr[1] = mac_addr[1]; + eth_dev.dev_addr[2] = mac_addr[2]; + eth_dev.dev_addr[3] = mac_addr[3]; + eth_dev.dev_addr[4] = mac_addr[4]; + eth_dev.dev_addr[5] = mac_addr[5]; + + eth_dev.parent.parent.type = RT_Device_Class_NetIf; + eth_dev.parent.parent.init = bcmgenet_eth_init; + eth_dev.parent.parent.open = RT_NULL; + eth_dev.parent.parent.close = RT_NULL; + eth_dev.parent.parent.read = RT_NULL; + eth_dev.parent.parent.write = RT_NULL; + eth_dev.parent.parent.control = bcmgenet_eth_control; + eth_dev.parent.parent.user_data = RT_NULL; + + eth_dev.parent.eth_tx = rt_eth_tx; + eth_dev.parent.eth_rx = rt_eth_rx; + + + eth_device_init(&(eth_dev.parent), "e0"); + eth_device_linkchange(ð_dev.parent, RT_TRUE); //linkup the e0 for lwip to check + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_eth_init); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h new file mode 100644 index 0000000000..708e626975 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h @@ -0,0 +1,214 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 bigmagic first version + */ + +#ifndef __DRV_ETH_H__ +#define __DRV_ETH_H__ + +#define MAC_REG (void *)(0xfd580000) + +//#define BIT(nr) (1UL << (nr)) + +#define SYS_REV_CTRL (0x00) +#define SYS_PORT_CTRL (0x04) +#define PORT_MODE_EXT_GPHY (3) + +#define GENET_SYS_OFF (0x0000) +#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) +#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) + +#define GENET_EXT_OFF (0x0080) +#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) +#define RGMII_LINK BIT(4) +#define OOB_DISABLE BIT(5) +#define RGMII_MODE_EN BIT(6) +#define ID_MODE_DIS BIT(16) + +#define GENET_RBUF_OFF (0x0300) +#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) +#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) +#define RBUF_ALIGN_2B BIT(1) + +#define GENET_UMAC_OFF (0x0800) +#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) +#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) +#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) +#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) +#define UMAC_CMD (GENET_UMAC_OFF + 0x008) +#define MDIO_CMD (GENET_UMAC_OFF + 0x614) +#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) +#define MDIO_START_BUSY BIT(29) +#define MDIO_READ_FAIL BIT(28) +#define MDIO_RD (2 << 26) +#define MDIO_WR BIT(26) +#define MDIO_PMD_SHIFT (21) +#define MDIO_PMD_MASK (0x1f) +#define MDIO_REG_SHIFT (16) +#define MDIO_REG_MASK (0x1f) + +#define CMD_TX_EN BIT(0) +#define CMD_RX_EN BIT(1) +#define UMAC_SPEED_10 (0) +#define UMAC_SPEED_100 (1) +#define UMAC_SPEED_1000 (2) +#define UMAC_SPEED_2500 (3) +#define CMD_SPEED_SHIFT (2) +#define CMD_SPEED_MASK (3) +#define CMD_SW_RESET BIT(13) +#define CMD_LCL_LOOP_EN BIT(15) +#define CMD_TX_EN BIT(0) +#define CMD_RX_EN BIT(1) + +#define MIB_RESET_RX BIT(0) +#define MIB_RESET_RUNT BIT(1) +#define MIB_RESET_TX BIT(2) + +/* total number of Buffer Descriptors, same for Rx/Tx */ +#define TOTAL_DESCS (256) +#define RX_DESCS TOTAL_DESCS +#define TX_DESCS TOTAL_DESCS + +#define DEFAULT_Q (0x10) + +#define ETH_DATA_LEN (1500) +#define ETH_HLEN (14) +#define VLAN_HLEN (4) +#define ETH_FCS_LEN (4) +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. + * 1536 is multiple of 256 bytes + */ +#define ENET_BRCM_TAG_LEN (6) +#define ENET_PAD (8) +#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ + VLAN_HLEN + ENET_BRCM_TAG_LEN + \ + ETH_FCS_LEN + ENET_PAD) + +/* Tx/Rx Dma Descriptor common bits */ +#define DMA_EN BIT(0) +#define DMA_RING_BUF_EN_SHIFT (0x01) +#define DMA_RING_BUF_EN_MASK (0xffff) +#define DMA_BUFLENGTH_MASK (0x0fff) +#define DMA_BUFLENGTH_SHIFT (16) +#define DMA_RING_SIZE_SHIFT (16) +#define DMA_OWN (0x8000) +#define DMA_EOP (0x4000) +#define DMA_SOP (0x2000) +#define DMA_WRAP (0x1000) +#define DMA_MAX_BURST_LENGTH (0x8) +/* Tx specific DMA descriptor bits */ +#define DMA_TX_UNDERRUN (0x0200) +#define DMA_TX_APPEND_CRC (0x0040) +#define DMA_TX_OW_CRC (0x0020) +#define DMA_TX_DO_CSUM (0x0010) +#define DMA_TX_QTAG_SHIFT (7) + +/* DMA rings size */ +#define DMA_RING_SIZE (0x40) +#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) + +/* DMA descriptor */ +#define DMA_DESC_LENGTH_STATUS (0x00) +#define DMA_DESC_ADDRESS_LO (0x04) +#define DMA_DESC_ADDRESS_HI (0x08) +#define DMA_DESC_SIZE (12) + +#define GENET_RX_OFF (0x2000) +#define GENET_RDMA_REG_OFF \ + (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) +#define GENET_TX_OFF (0x4000) +#define GENET_TDMA_REG_OFF \ + (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) + +#define DMA_FC_THRESH_HI (RX_DESCS >> 4) +#define DMA_FC_THRESH_LO (5) +#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ + DMA_FC_THRESH_HI) + +#define DMA_XOFF_THRESHOLD_SHIFT (16) + +#define TDMA_RING_REG_BASE \ + (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) +#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) +#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) +#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) +#define DMA_RING_BUF_SIZE (0x10) +#define DMA_START_ADDR (0x14) +#define DMA_END_ADDR (0x1c) +#define DMA_MBUF_DONE_THRESH (0x24) +#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) +#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) + +#define RDMA_RING_REG_BASE \ + (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) +#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) +#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) +#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) +#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) +#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) + +#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) +#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) +#define DMA_RING_CFG (0x00) +#define DMA_CTRL (0x04) +#define DMA_SCB_BURST_SIZE (0x0c) + +#define RX_BUF_LENGTH (2048) +#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) +#define RX_BUF_OFFSET (2) + +#define PHY_INTERFACE_MODE_RGMII (7) +#define PHY_INTERFACE_MODE_RGMII_RXID (9) + +#define BCM54213PE_MII_CONTROL (0x00) +#define BCM54213PE_MII_STATUS (0x01) +#define BCM54213PE_PHY_IDENTIFIER_HIGH (0x02) +#define BCM54213PE_PHY_IDENTIFIER_LOW (0x03) + +#define BCM54213PE_AUTO_NEGOTIATION_ADV (0x04) +#define BCM54213PE_AUTO_NEGOTIATION_LINK (0x05) +#define BCM54213PE_AUTO_NEGOTIATION_EXPANSION (0x06) + +#define BCM54213PE_NEXT_PAGE_TX (0x07) + +#define BCM54213PE_PARTNER_RX (0x08) + +#define BCM54213PE_CONTROL (0x09) +#define BCM54213PE_STATUS (0x0A) + +#define BCM54213PE_IEEE_EXTENDED_STATUS (0x0F) +#define BCM54213PE_PHY_EXTENDED_CONTROL (0x10) +#define BCM54213PE_PHY_EXTENDED_STATUS (0x11) + +#define BCM54213PE_RECEIVE_ERROR_COUNTER (0x12) +#define BCM54213PE_FALSE_C_S_COUNTER (0x13) +#define BCM54213PE_RECEIVE_NOT_OK_COUNTER (0x14) + +#define BCM54213PE_VERSION_B1 (0x600d84a2) +#define BCM54213PE_VERSION_X (0x600d84a0) + +//BCM54213PE_MII_CONTROL +#define MII_CONTROL_PHY_RESET (1 << 15) +#define MII_CONTROL_AUTO_NEGOTIATION_ENABLED (1 << 12) +#define MII_CONTROL_AUTO_NEGOTIATION_RESTART (1 << 9) +#define MII_CONTROL_PHY_FULL_DUPLEX (1 << 8) +#define MII_CONTROL_SPEED_SELECTION (1 << 6) + +//BCM54213PE_MII_STATUS +#define MII_STATUS_LINK_UP (1 << 2) + +//BCM54213PE_CONTROL +#define CONTROL_FULL_DUPLEX_CAPABILITY (1 << 9) +#define CONTROL_HALF_DUPLEX_CAPABILITY (1 << 8) + +#define SPEED_1000 (1000) +#define SPEED_100 (100) +#define SPEED_10 (10) + +#endif/* __DRV_ETH_H__ */ diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_hdmi.c b/bsp/raspberry-pi/raspi4-32/driver/drv_hdmi.c new file mode 100644 index 0000000000..a8d68fd9cf --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_hdmi.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-26 bigmagic first version + */ + +#include +#include +#include "mbox.h" +#include "drv_hdmi.h" + +#ifdef BSP_USING_HDMI +#define LCD_WIDTH (800) +#define LCD_HEIGHT (480) +#define LCD_DEPTH (32) +#define LCD_BPP (32) + +#define TAG_ALLOCATE_BUFFER 0x00040001 +#define TAG_SET_PHYS_WIDTH_HEIGHT 0x00048003 +#define TAG_SET_VIRT_WIDTH_HEIGHT 0x00048004 +#define TAG_SET_DEPTH 0x00048005 +#define TAG_SET_PIXEL_ORDER 0x00048006 +#define TAG_GET_PITCH 0x00040008 +#define TAG_SET_VIRT_OFFSET 0x00048009 +#define TAG_END 0x00000000 + + +enum { + MBOX_TAG_FB_GET_GPIOVIRT = 0x00040010, + MBOX_TAG_FB_ALLOCATE_BUFFER = 0x00040001, + MBOX_TAG_FB_RELEASE_BUFFER = 0x00048001, + MBOX_TAG_FB_BLANK_SCREEN = 0x00040002, + MBOX_TAG_FB_GET_PHYS_WH = 0x00040003, + MBOX_TAG_FB_TEST_PHYS_WH = 0x00044003, + MBOX_TAG_FB_SET_PHYS_WH = 0x00048003, + MBOX_TAG_FB_GET_VIRT_WH = 0x00040004, + MBOX_TAG_FB_TEST_VIRT_WH = 0x00044004, + MBOX_TAG_FB_SET_VIRT_WH = 0x00048004, + MBOX_TAG_FB_GET_DEPTH = 0x00040005, + MBOX_TAG_FB_TEST_DEPTH = 0x00044005, + MBOX_TAG_FB_SET_DEPTH = 0x00048005, + MBOX_TAG_FB_GET_PIXEL_ORDER = 0x00040006, + MBOX_TAG_FB_TEST_PIXEL_ORDER = 0x00044006, + MBOX_TAG_FB_SET_PIXEL_ORDER = 0x00048006, + MBOX_TAG_FB_GET_ALPHA_MODE = 0x00040007, + MBOX_TAG_FB_TEST_ALPHA_MODE = 0x00044007, + MBOX_TAG_FB_SET_ALPHA_MODE = 0x00048007, + MBOX_TAG_FB_GET_PITCH = 0x00040008, + MBOX_TAG_FB_GET_VIRT_OFFSET = 0x00040009, + MBOX_TAG_FB_TEST_VIRT_OFFSET = 0x00044009, + MBOX_TAG_FB_SET_VIRT_OFFSET = 0x00048009, + MBOX_TAG_FB_GET_OVERSCAN = 0x0004000a, + MBOX_TAG_FB_TEST_OVERSCAN = 0x0004400a, + MBOX_TAG_FB_SET_OVERSCAN = 0x0004800a, + MBOX_TAG_FB_GET_PALETTE = 0x0004000b, + MBOX_TAG_FB_TEST_PALETTE = 0x0004400b, + MBOX_TAG_FB_SET_PALETTE = 0x0004800b, +}; + +#define LCD_DEVICE(dev) (struct rt_hdmi_fb_device*)(dev) + +static struct rt_hdmi_fb_device _hdmi; + +typedef rt_uint16_t color_t; + +rt_err_t hdmi_fb_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +rt_err_t hdmi_fb_close(rt_device_t dev) +{ + return RT_EOK; +} + +rt_size_t hdmi_fb_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size) +{ + return 0; +} + +rt_size_t hdmi_fb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + return size; +} + +rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args) +{ + struct rt_hdmi_fb_device *lcd = LCD_DEVICE(dev); + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + { + struct rt_device_rect_info *info = (struct rt_device_rect_info*)args; + info = info; + } + break; + + case RTGRAPHIC_CTRL_GET_INFO: + { + struct rt_device_graphic_info* info = (struct rt_device_graphic_info*)args; + + RT_ASSERT(info != RT_NULL); + info->pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; + info->bits_per_pixel= LCD_DEPTH; + info->width = lcd->width; + info->height = lcd->height; + info->framebuffer = lcd->fb; + } + break; + } + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops hdmi_fb_ops = +{ + RT_NULL, + hdmi_fb_open, + hdmi_fb_close, + hdmi_fb_read, + hdmi_fb_write, + hdmi_fb_control, +}; +#endif + +rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *name) +{ + struct rt_device *device; + RT_ASSERT(hdmi_fb != RT_NULL); + + device = &hdmi_fb->parent; + + /* set device type */ + device->type = RT_Device_Class_Graphic; + /* initialize device interface */ +#ifdef RT_USING_DEVICE_OPS + device->ops = &hdmi_fb_ops; +#else + device->init = RT_NULL; + device->open = hdmi_fb_open; + device->close = hdmi_fb_close; + device->read = hdmi_fb_read; + device->write = hdmi_fb_write; + device->control = hdmi_fb_control; +#endif + + /* register to device manager */ + rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); + + return RT_EOK; +} + +rt_uint32_t bcm271x_mbox_fb_get_gpiovirt(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_GET_GPIOVIRT; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return (mbox[5] & 0x3fffffff); +} + +rt_uint32_t bcm271x_mbox_fb_get_pitch(void) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_GET_PITCH; + mbox[3] = 4; // buffer size + mbox[4] = 0; // len + + mbox[5] = 0; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return mbox[5]; +} + +void bcm271x_mbox_fb_set_porder(int rgb) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_SET_PIXEL_ORDER; + mbox[3] = 4; // buffer size + mbox[4] = 4; // len + + mbox[5] = rgb; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); +} + +void bcm271x_mbox_fb_setoffset(int xoffset, int yoffset) +{ + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_SET_VIRT_OFFSET; + mbox[3] = 8; // buffer size + mbox[4] = 8; // len + + mbox[5] = xoffset; // id + mbox[6] = yoffset; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); +} + + +void bcm271x_mbox_fb_setalpha(int alpha) +{ + + mbox[0] = 8*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_FB_SET_ALPHA_MODE; + mbox[3] = 4; // buffer size + mbox[4] = 4; // len + + mbox[5] = alpha; // id + mbox[6] = 0; + + mbox[7] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); +} + +void *bcm271x_mbox_fb_alloc(int width, int height, int bpp, int nrender) +{ + mbox[0] = 4 * 35; + mbox[1] = MBOX_REQUEST; + + mbox[2] = TAG_ALLOCATE_BUFFER;//get framebuffer, gets alignment on request + mbox[3] = 8; //size + mbox[4] = 4; //len + mbox[5] = 4096; //The design of MBOX driver forces us to give the virtual address 0x3C100000 + mbox[6] = 0; //FrameBufferInfo.size + + mbox[7] = TAG_SET_PHYS_WIDTH_HEIGHT; + mbox[8] = 8; + mbox[9] = 8; + mbox[10] = width; + mbox[11] = height; + + mbox[12] = TAG_SET_VIRT_WIDTH_HEIGHT; + mbox[13] = 8; + mbox[14] = 8; + mbox[15] = width; + mbox[16] = height * nrender; + + mbox[17] = TAG_SET_DEPTH; + mbox[18] = 4; + mbox[19] = 4; + mbox[20] = bpp; + + mbox[21] = TAG_SET_PIXEL_ORDER; + mbox[22] = 4; + mbox[23] = 0; + mbox[24] = 0; //RGB, not BGR preferably + + mbox[25] = TAG_GET_PITCH; + mbox[26] = 4; + mbox[27] = 0; + mbox[28] = 0; + + mbox[29] = TAG_SET_VIRT_OFFSET; + mbox[30] = 8; + mbox[31] = 8; + mbox[32] = 0; + mbox[33] = 0; + + mbox[34] = TAG_END; + + mbox_call(8, MMU_DISABLE); + return (void *)((rt_uint32_t)(mbox[5] & 0x3fffffff)); +} + +int hdmi_fb_init(void) +{ + _hdmi.fb = (rt_uint8_t *)bcm271x_mbox_fb_alloc(LCD_WIDTH, LCD_HEIGHT, LCD_BPP, 1); + bcm271x_mbox_fb_setoffset(0, 0); + bcm271x_mbox_fb_set_porder(0); + _hdmi.width = LCD_WIDTH; + _hdmi.height = LCD_HEIGHT; + _hdmi.depth = LCD_DEPTH; + _hdmi.pitch = 0; + _hdmi.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; + + //rt_kprintf("_hdmi.fb is %p\n", _hdmi.fb); + rt_hdmi_fb_device_init(&_hdmi, "lcd"); + + return 0; +} + +INIT_DEVICE_EXPORT(hdmi_fb_init); +#endif /*BSP_USING_HDMI */ diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_hdmi.h b/bsp/raspberry-pi/raspi4-32/driver/drv_hdmi.h new file mode 100644 index 0000000000..c9a06358d0 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_hdmi.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-26 bigmagic first version + */ +#ifndef __DRV_HDMI_H__ +#define __DRV_HDMI_H__ + +#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b))) + +struct rt_hdmi_fb_device +{ + struct rt_device parent; + + rt_uint32_t width; + rt_uint32_t height; + rt_uint32_t depth; + rt_uint32_t pitch; + rt_uint32_t pixel_format; + + rt_uint8_t *fb; +}; +#endif/* __DRV_HDMI_H__ */ diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c new file mode 100644 index 0000000000..8d34f3ab73 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c @@ -0,0 +1,656 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-27 bigmagic first version + */ + +#include "mbox.h" +#include "raspi4.h" +#include "drv_sdio.h" + +static rt_uint32_t mmc_base_clock = 0; + +static rt_uint32_t sdCommandTable[] = { + SD_CMD_INDEX(0), + SD_CMD_RESERVED(1), + SD_CMD_INDEX(2) | SD_RESP_R2, + SD_CMD_INDEX(3) | SD_RESP_R1, + SD_CMD_INDEX(4), + SD_CMD_RESERVED(5), //SD_CMD_INDEX(5) | SD_RESP_R4, + SD_CMD_INDEX(6) | SD_RESP_R1, + SD_CMD_INDEX(7) | SD_RESP_R1b, + SD_CMD_INDEX(8) | SD_RESP_R1, + SD_CMD_INDEX(9) | SD_RESP_R2, + SD_CMD_INDEX(10) | SD_RESP_R2, + SD_CMD_INDEX(11) | SD_RESP_R1, + SD_CMD_INDEX(12) | SD_RESP_R1b | SD_CMD_TYPE_ABORT, + SD_CMD_INDEX(13) | SD_RESP_R1, + SD_CMD_RESERVED(14), + SD_CMD_INDEX(15), + SD_CMD_INDEX(16) | SD_RESP_R1, + SD_CMD_INDEX(17) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_INDEX(18) | SD_RESP_R1 | SD_DATA_READ | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN, + SD_CMD_INDEX(19) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_INDEX(20) | SD_RESP_R1b, + SD_CMD_RESERVED(21), + SD_CMD_RESERVED(22), + SD_CMD_INDEX(23) | SD_RESP_R1, + SD_CMD_INDEX(24) | SD_RESP_R1 | SD_DATA_WRITE, + SD_CMD_INDEX(25) | SD_RESP_R1 | SD_DATA_WRITE | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN, + SD_CMD_INDEX(26) | SD_RESP_R1 | SD_DATA_WRITE, //add + SD_CMD_INDEX(27) | SD_RESP_R1 | SD_DATA_WRITE, + SD_CMD_INDEX(28) | SD_RESP_R1b, + SD_CMD_INDEX(29) | SD_RESP_R1b, + SD_CMD_INDEX(30) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_RESERVED(31), + SD_CMD_INDEX(32) | SD_RESP_R1, + SD_CMD_INDEX(33) | SD_RESP_R1, + SD_CMD_RESERVED(34), + SD_CMD_INDEX(35) | SD_RESP_R1, //add + SD_CMD_INDEX(36) | SD_RESP_R1, //add + SD_CMD_RESERVED(37), + SD_CMD_INDEX(38) | SD_RESP_R1b, + SD_CMD_INDEX(39) | SD_RESP_R4, //add + SD_CMD_INDEX(40) | SD_RESP_R5, //add + SD_CMD_INDEX(41) | SD_RESP_R3, //add, mov from harbote + SD_CMD_RESERVED(42) | SD_RESP_R1, + SD_CMD_RESERVED(43), + SD_CMD_RESERVED(44), + SD_CMD_RESERVED(45), + SD_CMD_RESERVED(46), + SD_CMD_RESERVED(47), + SD_CMD_RESERVED(48), + SD_CMD_RESERVED(49), + SD_CMD_RESERVED(50), + SD_CMD_INDEX(51) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_RESERVED(52), + SD_CMD_RESERVED(53), + SD_CMD_RESERVED(54), + SD_CMD_INDEX(55) | SD_RESP_R3, + SD_CMD_INDEX(56) | SD_RESP_R1 | SD_CMD_ISDATA, + SD_CMD_RESERVED(57), + SD_CMD_RESERVED(58), + SD_CMD_RESERVED(59), + SD_CMD_RESERVED(60), + SD_CMD_RESERVED(61), + SD_CMD_RESERVED(62), + SD_CMD_RESERVED(63) +}; + +static inline rt_uint32_t read32(rt_uint32_t addr) +{ + return (*((volatile unsigned int*)(addr))); +} + +static inline void write32(rt_uint32_t addr, rt_uint32_t value) +{ + (*((volatile unsigned int*)(addr))) = value; +} + +rt_err_t sd_int(struct sdhci_pdata_t * pdat, rt_uint32_t mask) +{ + rt_uint32_t r; + rt_uint32_t m = mask | INT_ERROR_MASK; + int cnt = 1000000; + while (!(read32(pdat->virt + EMMC_INTERRUPT) & (m | INT_ERROR_MASK)) && cnt--) + DELAY_MICROS(1); + r = read32(pdat->virt + EMMC_INTERRUPT); + if (cnt <= 0 || (r & INT_CMD_TIMEOUT) || (r & INT_DATA_TIMEOUT)) + { + write32(pdat->virt + EMMC_INTERRUPT, r); + //qemu maybe can not use sdcard + //rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS)); + //return -RT_ETIMEOUT; + } + else if (r & INT_ERROR_MASK) + { + write32(pdat->virt + EMMC_INTERRUPT, r); + rt_kprintf("send cmd/data error %x -> %x\n",r, read32(pdat->virt + EMMC_INTERRUPT)); + return -RT_ERROR; + } + write32(pdat->virt + EMMC_INTERRUPT, mask); + return RT_EOK; +} + +rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask) +{ + int cnt = 500000; + while ((read32(pdat->virt + EMMC_STATUS) & mask) && !(read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) && cnt--) + DELAY_MICROS(1); + if (cnt <= 0) + { + return -RT_ETIMEOUT; + } + else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t raspi_transfer_command(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd) +{ + rt_uint32_t cmdidx; + rt_err_t ret = RT_EOK; + ret = sd_status(pdat, SR_CMD_INHIBIT); + if (ret) + { + rt_kprintf("ERROR: EMMC busy %d\n", ret); + return ret; + } + + cmdidx = sdCommandTable[cmd->cmdidx]; + if (cmdidx == 0xFFFFFFFF) + return -RT_EINVAL; + if (cmd->datarw == DATA_READ) + cmdidx |= SD_DATA_READ; + if (cmd->datarw == DATA_WRITE) + cmdidx |= SD_DATA_WRITE; + mmcsd_dbg("transfer cmd %x(%d) %x %x\n", cmdidx, cmd->cmdidx, cmd->cmdarg, read32(pdat->virt + EMMC_INTERRUPT)); + write32(pdat->virt + EMMC_INTERRUPT,read32(pdat->virt + EMMC_INTERRUPT)); + write32(pdat->virt + EMMC_ARG1, cmd->cmdarg); + write32(pdat->virt + EMMC_CMDTM, cmdidx); + if (cmd->cmdidx == SD_APP_OP_COND) + DELAY_MICROS(1000); + else if ((cmd->cmdidx == SD_SEND_IF_COND) || (cmd->cmdidx == APP_CMD)) + DELAY_MICROS(100); + + ret = sd_int(pdat, INT_CMD_DONE); + if (ret) + { + return ret; + } + if (cmd->resptype & RESP_MASK) + { + + if (cmd->resptype & RESP_R2) + { + rt_uint32_t resp[4]; + resp[0] = read32(pdat->virt + EMMC_RESP0); + resp[1] = read32(pdat->virt + EMMC_RESP1); + resp[2] = read32(pdat->virt + EMMC_RESP2); + resp[3] = read32(pdat->virt + EMMC_RESP3); + if (cmd->resptype == RESP_R2) + { + cmd->response[0] = resp[3]<<8 |((resp[2]>>24)&0xff); + cmd->response[1] = resp[2]<<8 |((resp[1]>>24)&0xff); + cmd->response[2] = resp[1]<<8 |((resp[0]>>24)&0xff); + cmd->response[3] = resp[0]<<8 ; + } + else + { + cmd->response[0] = resp[0]; + cmd->response[1] = resp[1]; + cmd->response[2] = resp[2]; + cmd->response[3] = resp[3]; + } + } + else + cmd->response[0] = read32(pdat->virt + EMMC_RESP0); + } + mmcsd_dbg("response: %x: %x %x %x %x (%x, %x)\n", cmd->resptype, cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3], read32(pdat->virt + EMMC_STATUS),read32(pdat->virt + EMMC_INTERRUPT)); + return ret; +} + +static rt_err_t read_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize) +{ + int c = 0; + rt_err_t ret; + int d; + while (c < blkcount) + { + if ((ret = sd_int(pdat, INT_READ_RDY))) + { + rt_kprintf("timeout happens when reading block %d\n",c); + return ret; + } + for (d=0; d < blksize / 4; d++) + if (read32(pdat->virt + EMMC_STATUS) & SR_READ_AVAILABLE) + buf[d] = read32(pdat->virt + EMMC_DATA); + c++; + buf += blksize / 4; + } + return RT_EOK; +} + +static rt_err_t write_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize) +{ + int c = 0; + rt_err_t ret; + int d; + while (c < blkcount) + { + if ((ret = sd_int(pdat, INT_WRITE_RDY))) + { + return ret; + } + for (d=0; d < blksize / 4; d++) + write32(pdat->virt + EMMC_DATA, buf[d]); + c++; + buf += blksize / 4; + } + + if ((ret = sd_int(pdat, INT_DATA_DONE))) + { + return ret; + } + return RT_EOK; +} + +static rt_err_t raspi_transfer_data(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat) +{ + rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz); + rt_err_t ret = sd_status(pdat, SR_DAT_INHIBIT); + if (ret) + { + rt_kprintf("ERROR: EMMC busy\n"); + return ret; + } + if (dat->blkcnt > 1) + { + struct sdhci_cmd_t newcmd; + newcmd.cmdidx = SET_BLOCK_COUNT; + newcmd.cmdarg = dat->blkcnt; + newcmd.resptype = RESP_R1; + ret = raspi_transfer_command(pdat, &newcmd); + if (ret) return ret; + } + + if(dlen < 512) + { + write32(pdat->virt + EMMC_BLKSIZECNT, dlen | 1 << 16); + } + else + { + write32(pdat->virt + EMMC_BLKSIZECNT, 512 | (dat->blkcnt) << 16); + } + if (dat->flag & DATA_DIR_READ) + { + cmd->datarw = DATA_READ; + ret = raspi_transfer_command(pdat, cmd); + if (ret) return ret; + mmcsd_dbg("read_block %d, %d\n", dat->blkcnt, dat->blksz ); + ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz); + } + else if (dat->flag & DATA_DIR_WRITE) + { + cmd->datarw = DATA_WRITE; + ret = raspi_transfer_command(pdat, cmd); + if (ret) return ret; + mmcsd_dbg("write_block %d, %d", dat->blkcnt, dat->blksz ); + ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz); + } + return ret; +} + +static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat) +{ + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv; + if (!dat) + return raspi_transfer_command(pdat, cmd); + + return raspi_transfer_data(pdat, cmd, dat); +} + +static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data; + struct sdhci_cmd_t cmd; + struct sdhci_cmd_t stop; + struct sdhci_data_t dat; + rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t)); + rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t)); + rt_memset(&dat, 0, sizeof(struct sdhci_data_t)); + + cmd.cmdidx = req->cmd->cmd_code; + cmd.cmdarg = req->cmd->arg; + cmd.resptype =resp_type(req->cmd); + if (req->data) + { + dat.buf = (rt_uint8_t *)req->data->buf; + dat.flag = req->data->flags; + dat.blksz = req->data->blksize; + dat.blkcnt = req->data->blks; + + req->cmd->err = sdhci_transfer(sdhci, &cmd, &dat); + } + else + { + req->cmd->err = sdhci_transfer(sdhci, &cmd, RT_NULL); + } + + req->cmd->resp[3] = cmd.response[3]; + req->cmd->resp[2] = cmd.response[2]; + req->cmd->resp[1] = cmd.response[1]; + req->cmd->resp[0] = cmd.response[0]; + + if (req->stop) + { + stop.cmdidx = req->stop->cmd_code; + stop.cmdarg = req->stop->arg; + cmd.resptype =resp_type(req->stop); + req->stop->err = sdhci_transfer(sdhci, &stop, RT_NULL); + } + + mmcsd_req_complete(host); +} + +rt_int32_t mmc_card_status(struct rt_mmcsd_host *host) +{ + return 0; +} + +static rt_err_t sdhci_detect(struct sdhci_t * sdhci) +{ + return RT_EOK; +} + +static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width) +{ + rt_uint32_t temp = 0; + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv; + if (width == MMCSD_BUS_WIDTH_4) + { + temp = read32((pdat->virt + EMMC_CONTROL0)); + temp |= C0_HCTL_HS_EN; + temp |= C0_HCTL_DWITDH; // always use 4 data lines: + write32((pdat->virt + EMMC_CONTROL0), temp); + } + return RT_EOK; +} + + +static uint32_t sd_get_clock_divider(rt_uint32_t sdHostVer ,rt_uint32_t base_clock, rt_uint32_t target_rate) +{ + rt_uint32_t targetted_divisor = 0; + rt_uint32_t freq_select = 0; + rt_uint32_t upper_bits = 0; + rt_uint32_t ret = 0; + + if(target_rate > base_clock) + targetted_divisor = 1; + else + { + targetted_divisor = base_clock / target_rate; + rt_uint32_t mod = base_clock % target_rate; + if(mod) + targetted_divisor--; + } + + // Decide on the clock mode to use + + // Currently only 10-bit divided clock mode is supported + + // HCI version 3 or greater supports 10-bit divided clock mode + // This requires a power-of-two divider + + // Find the first bit set + int divisor = -1; + for(int first_bit = 31; first_bit >= 0; first_bit--) + { + rt_uint32_t bit_test = (1 << first_bit); + if(targetted_divisor & bit_test) + { + divisor = first_bit; + targetted_divisor &= ~bit_test; + if(targetted_divisor) + { + // The divisor is not a power-of-two, increase it + divisor++; + } + break; + } + } + + if(divisor == -1) + divisor = 31; + if(divisor >= 32) + divisor = 31; + + if(divisor != 0) + divisor = (1 << (divisor - 1)); + + if(divisor >= 0x400) + divisor = 0x3ff; + + freq_select = divisor & 0xff; + upper_bits = (divisor >> 8) & 0x3; + ret = (freq_select << 8) | (upper_bits << 6) | (0 << 5); + + return ret; +} + +static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock) +{ + rt_uint32_t temp = 0; + rt_uint32_t sdHostVer = 0; + int count = 100000; + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)(sdhci->priv); + + while ((read32(pdat->virt + EMMC_STATUS) & (SR_CMD_INHIBIT | SR_DAT_INHIBIT)) && (--count)) + DELAY_MICROS(1); + if (count <= 0) + { + rt_kprintf("EMMC: Set clock: timeout waiting for inhibit flags. Status %08x.\n",read32(pdat->virt + EMMC_STATUS)); + return RT_ERROR; + } + + // Switch clock off. + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp &= ~C1_CLK_EN; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + // Request the new clock setting and enable the clock + temp = read32(pdat->virt + EMMC_SLOTISR_VER); + sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT; + int cdiv = sd_get_clock_divider(sdHostVer, mmc_base_clock, clock); + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp |= 1; + temp |= cdiv; + temp |= (7 << 16); + + temp = (temp & 0xffff003f) | cdiv; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + + // Enable the clock. + temp = read32(pdat->virt + EMMC_CONTROL1); + temp |= C1_CLK_EN; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + + // Wait for clock to be stable. + count = 10000; + while (!(read32(pdat->virt + EMMC_CONTROL1) & C1_CLK_STABLE) && count--) + DELAY_MICROS(10); + if (count <= 0) + { + rt_kprintf("EMMC: ERROR: failed to get stable clock %d.\n", clock); + return RT_ERROR; + } + + mmcsd_dbg("set stable clock %d.\n", clock); + return RT_EOK; +} + +static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + struct sdhci_t * sdhci = (struct sdhci_t *)host->private_data; + sdhci_setclock(sdhci, io_cfg->clock); + sdhci_setwidth(sdhci, io_cfg->bus_width); +} + +static const struct rt_mmcsd_host_ops ops = +{ + mmc_request_send, + mmc_set_iocfg, + RT_NULL, + RT_NULL, +}; + +static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat) +{ + rt_uint32_t control1; + + //Reset the controller + control1 = read32((pdat->virt + EMMC_CONTROL1)); + control1 |= (1 << 24); + // Disable clock + control1 &= ~(1 << 2); + control1 &= ~(1 << 0); + //temp |= C1_CLK_INTLEN | C1_TOUNIT_MAX; + write32((pdat->virt + EMMC_CONTROL1),control1); + int cnt = 10000; + do + { + DELAY_MICROS(10); + cnt = cnt - 1; + if(cnt == 0) + { + break; + } + } while ((read32(pdat->virt + EMMC_CONTROL1) & (0x7 << 24)) != 0); + + // Enable SD Bus Power VDD1 at 3.3V + rt_uint32_t control0 = read32(pdat->virt + EMMC_CONTROL0); + control0 |= 0x0F << 8; + write32(pdat->virt + EMMC_CONTROL0, control0); + + rt_thread_delay(100); + //usleep(2000); + + + // Check for a valid card + mmcsd_dbg("EMMC: checking for an inserted card\n"); + cnt = 10000; + do + { + DELAY_MICROS(10); + cnt = cnt - 1; + if(cnt == 0) + { + break; + } + } while ((read32(pdat->virt + EMMC_STATUS) & (0x1 << 16)) == 0); + + rt_uint32_t status_reg = read32(pdat->virt + EMMC_STATUS); + + if((status_reg & (1 << 16)) == 0) + { + rt_kprintf("EMMC: no card inserted\n"); + return -1; + } + else + { + mmcsd_dbg("EMMC: status: %08x\n", status_reg); + } + + // Clear control2 + write32(pdat->virt + EMMC_CONTROL2, 0); + + // Get the base clock rate + mmc_base_clock = bcm271x_mbox_clock_get_rate(12); + if(mmc_base_clock == 0) + { + rt_kprintf("EMMC: assuming clock rate to be 100MHz\n"); + mmc_base_clock = 100000000; + } + mmcsd_dbg("EMMC: setting clock rate is %d\n", mmc_base_clock); + return RT_EOK; +} + +#ifdef RT_MMCSD_DBG +void dump_registers(struct sdhci_pdata_t * pdat) +{ + rt_kprintf("EMMC registers:"); + int i = EMMC_ARG2; + for (; i <= EMMC_CONTROL2; i += 4) + rt_kprintf("\t%x:%x\n", i, read32(pdat->virt + i)); + rt_kprintf("\t%x:%x\n", 0x50, read32(pdat->virt + 0x50)); + rt_kprintf("\t%x:%x\n", 0x70, read32(pdat->virt + 0x70)); + rt_kprintf("\t%x:%x\n", 0x74, read32(pdat->virt + 0x74)); + rt_kprintf("\t%x:%x\n", 0x80, read32(pdat->virt + 0x80)); + rt_kprintf("\t%x:%x\n", 0x84, read32(pdat->virt + 0x84)); + rt_kprintf("\t%x:%x\n", 0x88, read32(pdat->virt + 0x88)); + rt_kprintf("\t%x:%x\n", 0x8c, read32(pdat->virt + 0x8c)); + rt_kprintf("\t%x:%x\n", 0x90, read32(pdat->virt + 0x90)); + rt_kprintf("\t%x:%x\n", 0xf0, read32(pdat->virt + 0xf0)); + rt_kprintf("\t%x:%x\n", 0xfc, read32(pdat->virt + 0xfc)); +} +#endif + +int raspi_sdmmc_init(void) +{ + rt_uint32_t virt; + struct rt_mmcsd_host * host = RT_NULL; + struct sdhci_pdata_t * pdat = RT_NULL; + struct sdhci_t * sdhci = RT_NULL; + +#ifdef BSP_USING_SDIO0 + host = mmcsd_alloc_host(); + if (!host) + { + rt_kprintf("alloc host failed"); + goto err; + } + + sdhci = rt_malloc(sizeof(struct sdhci_t)); + if (!sdhci) + { + rt_kprintf("alloc sdhci failed"); + goto err; + } + rt_memset(sdhci, 0, sizeof(struct sdhci_t)); + + virt = MMC2_BASE_ADDR; + + pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t)); + RT_ASSERT(pdat != RT_NULL); + + pdat->virt = (rt_uint32_t)virt; + reset_emmc(pdat); + + sdhci->name = "sd0"; + sdhci->voltages = VDD_33_34; + sdhci->width = MMCSD_BUSWIDTH_4; + sdhci->clock = 250 * 1000 * 1000; + sdhci->removeable = RT_TRUE; + + sdhci->detect = sdhci_detect; + sdhci->setwidth = sdhci_setwidth; + sdhci->setclock = sdhci_setclock; + sdhci->transfer = sdhci_transfer; + sdhci->priv = pdat; + host->ops = &ops; + host->freq_min = 400000; + host->freq_max = 50000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4; + host->max_seg_size = 2048; + host->max_dma_segs = 10; + host->max_blk_size = 512; + host->max_blk_count = 4096; + + host->private_data = sdhci; + + write32((pdat->virt + EMMC_IRPT_EN),0xffffffff); + write32((pdat->virt + EMMC_IRPT_MASK),0xffffffff); +#ifdef RT_MMCSD_DBG + dump_registers(pdat); +#endif + mmcsd_change(host); +#endif + return RT_EOK; +err: + if (host) rt_free(host); + if (sdhci) rt_free(sdhci); + + return -RT_EIO; +} + +INIT_DEVICE_EXPORT(raspi_sdmmc_init); diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h new file mode 100644 index 0000000000..5919bd64d3 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-27 bigmagic first version + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +#include +#include +#include + +#include "board.h" +#include "raspi4.h" + +/* Struct for Intrrrupt Information */ +#define SDXC_CmdDone BIT(0) +#define SDXC_DataDone BIT(1) +#define SDXC_BlockGap BIT(2) +#define SDXC_WriteRdy BIT(4) +#define SDXC_ReadRdy BIT(5) +#define SDXC_Card BIT(8) +#define SDXC_Retune BIT(12) +#define SDXC_BootAck BIT(13) +#define SDXC_EndBoot BIT(14) +#define SDXC_Err BIT(15) +#define SDXC_CTOErr BIT(16) +#define SDXC_CCRCErr BIT(17) +#define SDXC_CENDErr BIT(18) +#define SDXC_CBADErr BIT(19) +#define SDXC_DTOErr BIT(20) +#define SDXC_DCRCErr BIT(21) +#define SDXC_DENDErr BIT(22) +#define SDXC_ACMDErr BIT(24) + +#define SDXC_BLKCNT_EN BIT(1) +#define SDXC_AUTO_CMD12_EN BIT(2) +#define SDXC_AUTO_CMD23_EN BIT(3) +#define SDXC_DAT_DIR BIT(4) //from card to host +#define SDXC_MULTI_BLOCK BIT(5) +#define SDXC_CMD_RSPNS_136 BIT(16) +#define SDXC_CMD_RSPNS_48 BIT(17) +#define SDXC_CMD_RSPNS_48busy BIT(16)|BIT(17) +#define SDXC_CHECK_CRC_CMD BIT(19) +#define SDXC_CMD_IXCHK_EN BIT(20) +#define SDXC_CMD_ISDATA BIT(21) +#define SDXC_CMD_SUSPEND BIT(22) +#define SDXC_CMD_RESUME BIT(23) +#define SDXC_CMD_ABORT BIT(23)|BIT(22) + +#define SDXC_CMD_INHIBIT BIT(0) +#define SDXC_DAT_INHIBIT BIT(1) +#define SDXC_DAT_ACTIVE BIT(2) +#define SDXC_WRITE_TRANSFER BIT(8) +#define SDXC_READ_TRANSFER BIT(9) + +struct sdhci_cmd_t +{ + rt_uint32_t cmdidx; + rt_uint32_t cmdarg; + rt_uint32_t resptype; + rt_uint32_t datarw; +#define DATA_READ 1 +#define DATA_WRITE 2 + rt_uint32_t response[4]; +}; + +struct sdhci_data_t +{ + rt_uint8_t * buf; + rt_uint32_t flag; + rt_uint32_t blksz; + rt_uint32_t blkcnt; +}; + +struct sdhci_t +{ + char * name; + rt_uint32_t voltages; + rt_uint32_t width; + rt_uint32_t clock; + rt_err_t removeable; + void * sdcard; + + rt_err_t (*detect)(struct sdhci_t * sdhci); + rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width); + rt_err_t (*setclock)(struct sdhci_t * sdhci, rt_uint32_t clock); + rt_err_t (*transfer)(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat); + void * priv; +}; + +struct sdhci_pdata_t +{ + rt_uint32_t virt; +}; + +// EMMC command flags +#define CMD_TYPE_NORMAL (0x00000000) +#define CMD_TYPE_SUSPEND (0x00400000) +#define CMD_TYPE_RESUME (0x00800000) +#define CMD_TYPE_ABORT (0x00c00000) +#define CMD_IS_DATA (0x00200000) +#define CMD_IXCHK_EN (0x00100000) +#define CMD_CRCCHK_EN (0x00080000) +#define CMD_RSPNS_NO (0x00000000) +#define CMD_RSPNS_136 (0x00010000) +#define CMD_RSPNS_48 (0x00020000) +#define CMD_RSPNS_48B (0x00030000) +#define TM_MULTI_BLOCK (0x00000020) +#define TM_DAT_DIR_HC (0x00000000) +#define TM_DAT_DIR_CH (0x00000010) +#define TM_AUTO_CMD23 (0x00000008) +#define TM_AUTO_CMD12 (0x00000004) +#define TM_BLKCNT_EN (0x00000002) +#define TM_MULTI_DATA (CMD_IS_DATA|TM_MULTI_BLOCK|TM_BLKCNT_EN) + +#define RCA_NO (1) +#define RCA_YES (2) + +// INTERRUPT register settings +#define INT_AUTO_ERROR (0x01000000) +#define INT_DATA_END_ERR (0x00400000) +#define INT_DATA_CRC_ERR (0x00200000) +#define INT_DATA_TIMEOUT (0x00100000) +#define INT_INDEX_ERROR (0x00080000) +#define INT_END_ERROR (0x00040000) +#define INT_CRC_ERROR (0x00020000) +#define INT_CMD_TIMEOUT (0x00010000) +#define INT_ERR (0x00008000) +#define INT_ENDBOOT (0x00004000) +#define INT_BOOTACK (0x00002000) +#define INT_RETUNE (0x00001000) +#define INT_CARD (0x00000100) +#define INT_READ_RDY (0x00000020) +#define INT_WRITE_RDY (0x00000010) +#define INT_BLOCK_GAP (0x00000004) +#define INT_DATA_DONE (0x00000002) +#define INT_CMD_DONE (0x00000001) +#define INT_ERROR_MASK (INT_CRC_ERROR|INT_END_ERROR|INT_INDEX_ERROR| \ + INT_DATA_TIMEOUT|INT_DATA_CRC_ERR|INT_DATA_END_ERR| \ + INT_ERR|INT_AUTO_ERROR) +#define INT_ALL_MASK (INT_CMD_DONE|INT_DATA_DONE|INT_READ_RDY|INT_WRITE_RDY|INT_ERROR_MASK) + +#define EMMC_ARG2 (0x00) +#define EMMC_BLKSIZECNT (0x04) +#define EMMC_ARG1 (0x08) +#define EMMC_CMDTM (0x0c) +#define EMMC_RESP0 (0x10) +#define EMMC_RESP1 (0x14) +#define EMMC_RESP2 (0x18) +#define EMMC_RESP3 (0x1c) +#define EMMC_DATA (0x20) +#define EMMC_STATUS (0x24) +#define EMMC_CONTROL0 (0x28) +#define EMMC_CONTROL1 (0x2c) +#define EMMC_INTERRUPT (0x30) +#define EMMC_IRPT_MASK (0x34) +#define EMMC_IRPT_EN (0x38) +#define EMMC_CONTROL2 (0x3c) +#define EMMC_CAPABILITIES_0 (0x40) +#define EMMC_CAPABILITIES_1 (0x44) +#define EMMC_BOOT_TIMEOUT (0x70) +#define EMMC_EXRDFIFO_EN (0x84) +#define EMMC_SPI_INT_SPT (0xf0) +#define EMMC_SLOTISR_VER (0xfc) + +// CONTROL register settings +#define C0_SPI_MODE_EN (0x00100000) +#define C0_HCTL_HS_EN (0x00000004) +#define C0_HCTL_DWITDH (0x00000002) + +#define C1_SRST_DATA (0x04000000) +#define C1_SRST_CMD (0x02000000) +#define C1_SRST_HC (0x01000000) +#define C1_TOUNIT_DIS (0x000f0000) +#define C1_TOUNIT_MAX (0x000e0000) +#define C1_CLK_GENSEL (0x00000020) +#define C1_CLK_EN (0x00000004) +#define C1_CLK_STABLE (0x00000002) +#define C1_CLK_INTLEN (0x00000001) + +#define FREQ_SETUP (400000) // 400 Khz +#define FREQ_NORMAL (25000000) // 25 Mhz + +// SLOTISR_VER values +#define HOST_SPEC_NUM 0x00ff0000 +#define HOST_SPEC_NUM_SHIFT 16 +#define HOST_SPEC_V3 2 +#define HOST_SPEC_V2 1 +#define HOST_SPEC_V1 0 + +// STATUS register settings +#define SR_DAT_LEVEL1 (0x1e000000) +#define SR_CMD_LEVEL (0x01000000) +#define SR_DAT_LEVEL0 (0x00f00000) +#define SR_DAT3 (0x00800000) +#define SR_DAT2 (0x00400000) +#define SR_DAT1 (0x00200000) +#define SR_DAT0 (0x00100000) +#define SR_WRITE_PROT (0x00080000) // From SDHC spec v2, BCM says reserved +#define SR_READ_AVAILABLE (0x00000800) // ???? undocumented +#define SR_WRITE_AVAILABLE (0x00000400) // ???? undocumented +#define SR_READ_TRANSFER (0x00000200) +#define SR_WRITE_TRANSFER (0x00000100) +#define SR_DAT_ACTIVE (0x00000004) +#define SR_DAT_INHIBIT (0x00000002) +#define SR_CMD_INHIBIT (0x00000001) + +#define CONFIG_MMC_USE_DMA +#define DMA_ALIGN (32U) + +#define SD_CMD_INDEX(a) ((a) << 24) +#define SD_CMD_RESERVED(a) (0xffffffff) +#define SD_CMD_INDEX(a) ((a) << 24) +#define SD_CMD_TYPE_NORMAL (0x0) +#define SD_CMD_TYPE_SUSPEND (1 << 22) +#define SD_CMD_TYPE_RESUME (2 << 22) +#define SD_CMD_TYPE_ABORT (3 << 22) +#define SD_CMD_TYPE_MASK (3 << 22) +#define SD_CMD_ISDATA (1 << 21) +#define SD_CMD_IXCHK_EN (1 << 20) +#define SD_CMD_CRCCHK_EN (1 << 19) +#define SD_CMD_RSPNS_TYPE_NONE (0) // For no response +#define SD_CMD_RSPNS_TYPE_136 (1 << 16) // For response R2 (with CRC), R3,4 (no CRC) +#define SD_CMD_RSPNS_TYPE_48 (2 << 16) // For responses R1, R5, R6, R7 (with CRC) +#define SD_CMD_RSPNS_TYPE_48B (3 << 16) // For responses R1b, R5b (with CRC) +#define SD_CMD_RSPNS_TYPE_MASK (3 << 16) +#define SD_CMD_MULTI_BLOCK (1 << 5) +#define SD_CMD_DAT_DIR_HC (0) +#define SD_CMD_DAT_DIR_CH (1 << 4) +#define SD_CMD_AUTO_CMD_EN_NONE (0) +#define SD_CMD_AUTO_CMD_EN_CMD12 (1 << 2) +#define SD_CMD_AUTO_CMD_EN_CMD23 (2 << 2) +#define SD_CMD_BLKCNT_EN (1 << 1) +#define SD_CMD_DMA (1) +#define SD_RESP_NONE SD_CMD_RSPNS_TYPE_NONE +#define SD_RESP_R1 (SD_CMD_RSPNS_TYPE_48) // | SD_CMD_CRCCHK_EN) +#define SD_RESP_R1b (SD_CMD_RSPNS_TYPE_48B) // | SD_CMD_CRCCHK_EN) +#define SD_RESP_R2 (SD_CMD_RSPNS_TYPE_136) // | SD_CMD_CRCCHK_EN) +#define SD_RESP_R3 SD_CMD_RSPNS_TYPE_48 +#define SD_RESP_R4 SD_CMD_RSPNS_TYPE_136 +#define SD_RESP_R5 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) +#define SD_RESP_R5b (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN) +#define SD_RESP_R6 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) +#define SD_RESP_R7 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) +#define SD_DATA_READ (SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH) +#define SD_DATA_WRITE (SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC) +#endif diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c new file mode 100644 index 0000000000..3c091354bb --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-26 bigmagic first version + */ +#include +#include "drv_wdt.h" +#include "raspi4.h" + +#ifdef BSP_USING_WDT + +#define SECS_TO_WDOG_TICKS(x) ((x) << 16) +#define WDOG_TICKS_TO_SECS(x) ((x) >> 16) + +static struct raspi_wdt_driver bcm_wdt; + +void raspi_watchdog_init(rt_uint32_t time_init) +{ + bcm_wdt.timeout = time_init; +} + +void raspi_watchdog_start() +{ + volatile rt_uint32_t cur; + PM_WDOG = PM_PASSWORD | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET); + cur = (PM_RSTC); + PM_RSTC = PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; +} + +void raspi_watchdog_stop() +{ + PM_RSTC = PM_PASSWORD | PM_RSTC_RESET; +} + +void raspi_watchdog_clr() +{ + bcm_wdt.timeout = 0; +} + +void raspi_watchdog_set_timeout(rt_uint32_t timeout_us) +{ + bcm_wdt.timeout = timeout_us; +} + +rt_uint64_t raspi_watchdog_get_timeout() +{ + return bcm_wdt.timeout; +} + +rt_uint64_t raspi_watchdog_get_timeleft() +{ + rt_uint32_t ret = (PM_WDOG); + return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET); +} + +static rt_err_t raspi_wdg_init(rt_watchdog_t *wdt) +{ + /*init for 10S*/ + raspi_watchdog_init(1000000); + raspi_watchdog_start(); + raspi_watchdog_stop(); + return RT_EOK; +} + +static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + rt_uint64_t timeout_us = 0; + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + timeout_us = *((rt_uint32_t *)arg) * 1000000; + if (timeout_us >= 0xFFFFFFFF) + timeout_us = 0xFFFFFFFF; + raspi_watchdog_set_timeout((rt_uint32_t)timeout_us); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + timeout_us = raspi_watchdog_get_timeout(); + *((rt_uint32_t *)arg) = timeout_us / 1000000; + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + timeout_us = raspi_watchdog_get_timeleft(); + *((rt_uint32_t *)arg) = timeout_us / 1000000; + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + raspi_watchdog_clr(); + break; + case RT_DEVICE_CTRL_WDT_START: + raspi_watchdog_start(); + break; + case RT_DEVICE_CTRL_WDT_STOP: + raspi_watchdog_stop(); + break; + default: + return RT_EIO; + } + return RT_EOK; +} + +static const struct rt_watchdog_ops raspi_wdg_pos = +{ + raspi_wdg_init, + raspi_wdg_control, +}; + +static rt_watchdog_t raspi_wdg; + +int rt_hw_wdt_init(void) +{ + raspi_wdg.ops = &raspi_wdg_pos; + rt_hw_watchdog_register(&raspi_wdg, "wdg", 0, RT_NULL); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_wdt_init); + +void reboot(void) +{ + unsigned int r; + + rt_kprintf("reboot system...\n"); + rt_thread_mdelay(100); + r = PM_RSTS; + // trigger a restart by instructing the GPU to boot from partition 0 + r &= ~0xfffffaaa; + PM_RSTS |= (PM_PASSWORD | r); // boot from partition 0 + PM_WDOG |= (PM_PASSWORD | 0x0A); + PM_RSTC |= (PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET); + + while (1); +} +MSH_CMD_EXPORT(reboot,reboot system...); +#endif /*BSP_USING_WDT */ diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h new file mode 100644 index 0000000000..4c9454ed91 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-26 bigmagic first version + */ +#ifndef __DRV_WDT_H__ +#define __DRV_WDT_H__ + +#include +#include + +#include "board.h" + +struct raspi_wdt_driver +{ + rt_uint32_t timeout; +}; + +int rt_hw_wdt_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.c b/bsp/raspberry-pi/raspi4-32/driver/mbox.c index 186440ffce..b0c79e09bd 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/mbox.c +++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.c @@ -49,6 +49,52 @@ int mbox_call(unsigned char ch, int mmu_enable) return 0; } +int bcm271x_notify_reboot(void) +{ + mbox[0] = 7*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + mbox[2] = MBOX_TAG_NOTIFY_REBOOT; // (the tag id) + mbox[3] = 0x00000004; // length + 4 + mbox[4] = 0x00000000; // size of the data + mbox[5] = 0x00000000; // request + + mbox[6] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return 0; +} + +int bcm271x_notify_xhci_reset(void) +{ + mbox[0] = 7*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + mbox[2] = MBOX_TAG_NOTIFY_XHCI_RESET; // (the tag id) + mbox[3] = 0x00000004; // length + 4 + mbox[4] = 0x00000004; // size of the data + mbox[5] = 0x00100000; // request + mbox[6] = MBOX_TAG_LAST; + mbox_call(8, MMU_DISABLE); + return 0; +} + +int bcm271x_gpu_enable(void) +{ + mbox[0] = 12*4; // length of the message + mbox[1] = MBOX_REQUEST; // this is a request message + + mbox[2] = MBOX_TAG_CLOCK_SET_RATE; + mbox[3] = 0x00000008; // (the tag id) + mbox[4] = 0x00000008; // (the tag id) + mbox[5] = 5; // V3D + mbox[6] = 250 * 1000 * 1000; + mbox[7] = MBOX_TAG_ENABLE_QPU; // (the tag id) + mbox[8] = 0x00000004; // (size of the buffer) + mbox[9] = 0x00000004; // (size of the data) + mbox[10] = 0x00000001; + mbox[11] = MBOX_TAG_LAST; // end tag + mbox_call(8, MMU_DISABLE); + return mbox[1]; +} + int bcm271x_mbox_hardware_get_model(void) { mbox[0] = 8*4; // length of the message diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.h b/bsp/raspberry-pi/raspi4-32/driver/mbox.h index bf9ac0e96d..ec31370f6b 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/mbox.h +++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.h @@ -35,7 +35,7 @@ extern volatile unsigned int* mbox; /* tags */ #define MBOX_TAG_SETPOWER 0x28001 #define MBOX_TAG_SETCLKRATE 0x38002 -#define MBOX_GET_MAC_ADDRESS 0x10003 +#define MBOX_GET_MAC_ADDRESS 0x10003 #define MBOX_TAG_LAST 0 #define MMIO_BASE 0xFE000000 @@ -50,14 +50,14 @@ extern volatile unsigned int* mbox; #define MBOX_FULL 0x80000000 #define MBOX_EMPTY 0x40000000 -#define DEVICE_ID_SD_CARD 0 -#define DEVICE_ID_USB_HCD 3 -#define POWER_STATE_OFF (0 << 0) -#define POWER_STATE_ON (1 << 0) -#define POWER_STATE_WAIT (1 << 1) -#define POWER_STATE_NO_DEVICE (1 << 1) // in response -#define MMU_ENABLE 1 -#define MMU_DISABLE 0 +#define DEVICE_ID_SD_CARD (0) +#define DEVICE_ID_USB_HCD (3) +#define POWER_STATE_OFF (0 << 0) +#define POWER_STATE_ON (1 << 0) +#define POWER_STATE_WAIT (1 << 1) +#define POWER_STATE_NO_DEVICE (1 << 1) // in response +#define MMU_ENABLE (1) +#define MMU_DISABLE (0) /* * raspi hardware info @@ -102,9 +102,42 @@ enum { MBOX_TAG_TEMP_GET_MAX = 0x0003000A, }; -#define MBOX_ADDR 0xc00000 +/* + * raspi Memory + */ +enum { + MBOX_TAG_ALLOCATE_MEMORY = 0x0003000C, // Memory: Allocates Contiguous Memory On The GPU (Response: Handle) + MBOX_TAG_LOCK_MEMORY = 0x0003000D, // Memory: Unlock Buffer (Response: Status) + MBOX_TAG_UNLOCK_MEMORY = 0x0003000E, // Memory: Unlock Buffer (Response: Status) + MBOX_TAG_RELEASE_MEMORY = 0x0003000F, // Memory: Free The Memory Buffer (Response: Status) + MBOX_TAG_EXECUTE_CODE = 0x00030010, // Memory: Calls The Function At Given (Bus) Address And With Arguments Given +}; + +/* + * raspi GPU + */ +enum { + MBOX_TAG_EXECUTE_QPU = 0x00030011, // QPU: Calls The QPU Function At Given (Bus) Address And With Arguments Given (Response: Number Of QPUs, Control, No Flush, Timeout In ms) + MBOX_TAG_ENABLE_QPU = 0x00030012, // QPU: Enables The QPU (Response: Enable State) +}; + +/* + * raspi HDMI + */ +#define MBOX_TAG_GET_EDID_BLOCK 0x00030020 // HDMI: Read Specificed EDID Block From Attached HDMI/DVI Device (Response: Block Number, Status, EDID Block (128 Bytes)) + +/* + * raspi NOTIFY + */ +#define MBOX_TAG_NOTIFY_REBOOT 0x00030048 +#define MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 + +#define MBOX_ADDR 0x08000000 int mbox_call(unsigned char ch, int mmu_enable); +int bcm271x_notify_reboot(void); +int bcm271x_notify_xhci_reset(void); +int bcm271x_gpu_enable(void); int bcm271x_mbox_hardware_get_model(void); int bcm271x_mbox_hardware_get_revison(void); int bcm271x_mbox_hardware_get_mac_address(uint8_t * mac); diff --git a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h index f874696705..5a91796d40 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h +++ b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h @@ -119,6 +119,39 @@ typedef enum { #define GIC_ACK_INTID_MASK 0x000003ff +//watchdog +#define PM_RSTC HWREG32(PER_BASE + 0x0010001c) +#define PM_RSTS HWREG32(PER_BASE + 0x00100020) +#define PM_WDOG HWREG32(PER_BASE + 0x00100024) + +#define PM_PASSWORD (0x5A000000) +#define PM_WDOG_TIME_SET (0x000fffff) +#define PM_RSTS_HADWRH_SET (0x00000040) +#define PM_RSTC_WRCFG_FULL_RESET (0x00000020) +#define PM_RSTC_WRCFG_CLR (0xffffffcf) +#define PM_RSTC_RESET (0x00000102) + +//timer +#define ST_BASE_OFFSET (0x003000) +#define STIMER_BASE (PER_BASE + ST_BASE_OFFSET) +#define STIMER_CS __REG32(STIMER_BASE + 0x0000) +#define STIMER_CLO __REG32(STIMER_BASE + 0x0004) +#define STIMER_CHI __REG32(STIMER_BASE + 0x0008) +#define STIMER_C0 __REG32(STIMER_BASE + 0x000C) +#define STIMER_C1 __REG32(STIMER_BASE + 0x0010) +#define STIMER_C2 __REG32(STIMER_BASE + 0x0014) +#define STIMER_C3 __REG32(STIMER_BASE + 0x0018) + +#define DELAY_MICROS(micros) \ + do{ \ + rt_uint32_t compare = STIMER_CLO + micros * 25; \ + while (STIMER_CLO < compare); \ + } while (0) \ + +//External Mass Media Controller (SD Card) +#define MMC0_BASE_ADDR (PER_BASE+0x300000) +#define MMC2_BASE_ADDR (PER_BASE+0x340000) + /* the basic constants and interfaces needed by gic */ rt_inline rt_uint32_t platform_get_gic_dist_base(void) { diff --git a/bsp/raspberry-pi/raspi4-32/rtconfig.h b/bsp/raspberry-pi/raspi4-32/rtconfig.h index c5ad40fc0b..1edd99a549 100644 --- a/bsp/raspberry-pi/raspi4-32/rtconfig.h +++ b/bsp/raspberry-pi/raspi4-32/rtconfig.h @@ -76,6 +76,18 @@ #define DFS_FILESYSTEMS_MAX 2 #define DFS_FILESYSTEM_TYPES_MAX 2 #define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT #define RT_USING_DFS_DEVFS /* Device Drivers */ @@ -86,7 +98,14 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_SPI +#define RT_USING_WDT /* Using USB */ @@ -103,9 +122,57 @@ /* Network interface device */ +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 /* light weight TCP/IP stack */ +#define RT_USING_LWIP +#define RT_USING_LWIP202 +#define RT_LWIP_MEM_ALIGNMENT 4 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING /* AT commands */ @@ -178,8 +245,13 @@ #define BSP_USING_SPI0_BUS #define BSP_USING_SPI0_DEVICE0 #define BSP_USING_CORETIMER +#define BSP_USING_WDT +#define BSP_USING_SDIO +#define BSP_USING_SDIO0 /* Board Peripheral Drivers */ +#define BSP_USING_HDMI +#define BSP_USING_HDMI_DISPLAY #endif diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index fae71750f1..a993ce3423 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -58,6 +58,8 @@ STM32 系列 BSP 目前支持情况如下表所示： | **MP1 系列** | | | [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-DK1 开发板 | | [stm32mp157a-st-ev1](stm32mp157a-st-ev1) | ST 官方 STM32MP157A-EV1 开发板 | +| **WB 系列** | | +| [stm32wb55-st-nucleo](stm32wb55-st-nucleo) | ST 官方 STM32WB55-nucleo 开发板 | 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示： diff --git a/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md b/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md new file mode 100644 index 0000000000..cb6e4f8f47 --- /dev/null +++ b/bsp/stm32/docs/STM32_Nucleo-144_BSP_Introduction.md @@ -0,0 +1,128 @@ +# STM32 Nucleo-144 BSP Introduction + +This document records the instruction of the BSP (board support package) that provided by the RT-Thread development team for the STM32 Nucleo-144 development boards. + +The document is covered in three parts: + +- Resources Introduction +- Quickly Get Started +- Advanced Features + +By reading the ***Quickly Get Started*** section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + + + +## Resources Introduction + +[board](figures/stm32-nucleo-144.jpg) + +### Description + +The STM32 Nucleo-144 board provides an affordable and flexible way for users to try out new concepts and build prototypes by choosing from the various combinations of performance and power consumption features, provided by the STM32 microcontroller. For the compatible boards, the internal or external SMPS significantly reduces power consumption in Run mode. The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and the ST morpho headers provide an easy means of expanding the functionality of the Nucleo open development platform with a wide choice of specialized shields. The STM32 Nucleo-144 board does not require any separate probe as it integrates the ST-LINK debugger/programmer. The STM32 Nucleo-144 board comes with the STM32 comprehensive free software libraries and examples available with the STM32Cube MCU Package. + +### Features + +- Common features + - STM32 microcontroller in LQFP144 package + - 3 user LEDs + - 2 user and reset push-buttons + - 32.768 kHz crystal oscillator + - Board connectors: + - SWD + - ST Zio expansion connector including ARDUINO® Uno V3 + - ST morpho expansion connector + - Flexible power-supply options: ST-LINK, USB VBUS or external sources + - On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port, and debug port + - Comprehensive free software libraries and examples available with the STM32Cube MCU Package + - Support of a wide choice of Integrated Development Environments (IDEs) including IAR™, Keil®, and STM32CubeIDE +- Board-specific features + - External or internal SMPS to generate Vcore logic supply + - Ethernet compliant with IEEE-802.3-2002 + - USB OTG full speed or device only + - Board connectors: + - USB with Micro-AB or USB Type-C™ + - Ethernet RJ45 + - Arm® Mbed Enabled™ compliant + +### **For more details about these boards, please refer to [ST Nucleo Official Website](https://www.st.com/en/evaluation-tools/stm32-nucleo-boards.html?querycriteria=productId=LN1847).** + + + +## Quickly Get Started + +This BSP provides MDK4, MDK5, and IAR projects for developers and it supports the GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system. + +![nucleo144_layout](figures/nucleo144_layout.jpg) + +### Hardware connection + +Use a Type-A to Mini-B cable to connect the development board to the PC and turn on the power switch. The LD3 (PWR) and LD1 (COM) will light. + +### Compile and Download + +- Double-click the `project.uvprojx` file to open the MDK-Keil5 project (**NOT** `template.uvprojx` file) +- Click the “option for target” button + - Debug: Choose "ST-LINK Debugger" and Click "Setting" button: + - Port: choose "SW (Serial Wire)" + - Flash Download: check "Reset and Run" + +- Compile and download the program to the board + +### Running Results + +After the program is successfully downloaded, the system runs automatically. Observe the running results of the LED on the development board, the LD3 and LD1 will light all the time, and LD2 will flash periodically. + +The USB virtual COM port connects to **USART2 by default**, and when the corresponding serial port (**115200-8-1-N**) is opened in the terminal tool, the output information of RT-Thread can be seen when the device is reset: + +```shell + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Dec 21 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` + +### Terminal tool - PuTTy + +If you don't have a terminal tool software available, you can download *PuTTy*: + +> https://www.chiark.greenend.org.uk/~sgtatham/putty/latest.html + +![putty](figures/putty.png) + + + +Follow these tutorial videos to learn PuTTy: + +> https://www.youtube.com/watch?v=ab4ilbsteWU +> +> https://www.youtube.com/watch?v=dO-BMOzNKcI + + + +## Advanced Features + +This BSP only enables GPIO and USART2 by default. If you need more advanced features such as SPI, I2C, you need to configure the BSP with RT-Thread [ENV tool](https://www.rt-thread.io/download.html?download=Env) , as follows: + +1. Open the Env tool under the specific BSP folder; +2. Enter `menuconfig` command to configure the project, then save and exit; +3. Enter `pkgs --update` command to update the package; +4. Enter `scons --target=mdk4/mdk5/iar` command to regenerate the project. + +Learn how to use RT-Thread Env, click [Here](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md). + + + +## Translated & Maintained By + +Cathy Lee @ RT-Thread Team + +> https://github.com/Cathy-lulu +> +> contact@rt-thread.org + +Meco Man @ RT-Thread Community + +> jiantingman@foxmail.com +> +> https://github.com/mysterywolf \ No newline at end of file diff --git a/bsp/stm32/docs/STM32_Nucleo-64_BSP_Introduction.md b/bsp/stm32/docs/STM32_Nucleo-64_BSP_Introduction.md new file mode 100644 index 0000000000..5cdddc3a2f --- /dev/null +++ b/bsp/stm32/docs/STM32_Nucleo-64_BSP_Introduction.md @@ -0,0 +1,126 @@ +# STM32 Nucleo-64 BSP Introduction + +This document records the instruction of the BSP (board support package) that provided by the RT-Thread development team for the STM32 Nucleo-64 development boards. + +The document is covered in three parts: + +- Resources Introduction +- Quickly Get Started +- Advanced Features + +By reading the ***Quickly Get Started*** section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + + + +## Resources Introduction + +[![board](figures/stm32-nucleo-64.jpg)](figures/stm32-nucleo-64.jpg) + +### Description + +The STM32 Nucleo-64 board provides an affordable and flexible way for users to try out new concepts and build prototypes by choosing from the various combinations of performance and power consumption features, provided by the STM32 microcontroller. For the compatible boards, the external SMPS significantly reduces power consumption in Run mode. The ARDUINO® Uno V3 connectivity support and the ST morpho headers allow the easy expansion of the functionality of the STM32 Nucleo open development platform with a wide choice of specialized shields. The STM32 Nucleo-64 board does not require any separate probe as it integrates the ST-LINK debugger/programmer. The STM32 Nucleo-64 board comes with the STM32 comprehensive free software libraries and examples available with the STM32Cube MCU Package. + +### Features + +- Common features + - STM32 microcontroller in LQFP64 package + - 1 user LED shared with ARDUINO® + - 1 user and 1 reset push-buttons + - 32.768 kHz crystal oscillator + - Board connectors: + - ARDUINO® Uno V3 expansion connector + - ST morpho extension pin headers for full access to all STM32 I/Os + - Flexible power-supply options: ST-LINK, USB VBUS, or external sources + - On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port and debug port + - Comprehensive free software libraries and examples available with the STM32Cube MCU Package + - Support of a wide choice of Integrated Development Environments (IDEs) including IAR Embedded Workbench®, MDK-ARM, and STM32CubeIDE +- Board-specific features + - External SMPS to generate Vcore logic supply + - 24 MHz HSE – Board connectors: + - External SMPS experimentation dedicated connector + - Micro-AB or Mini-AB USB connector for the ST-LINK + - MIPI® debug connector + - Arm® Mbed Enabled™ compliant + +### **For more details about these boards, please refer to [ST Nucleo Official Website](https://www.st.com/en/evaluation-tools/stm32-nucleo-boards.html?querycriteria=productId=LN1847).** + + + +## Quickly Get Started + +This BSP provides MDK4, MDK5, and IAR projects for developers and it supports the GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system. + +![nucleo64_layout](figures/nucleo64_layout.jpg) + +### Hardware connection + +Use a Type-A to Mini-B cable to connect the development board to the PC and turn on the power switch. The LD3 (PWR) and LD1 (COM) will light. + +### Compile and Download + +- Double-click the `project.uvprojx` file to open the MDK-Keil5 project (**NOT** `template.uvprojx` file) +- Click the “option for target” button + - Debug: Choose "ST-LINK Debugger" and Click "Setting" button: + - Port: choose "SW (Serial Wire)" + - Flash Download: check "Reset and Run" + +- Compile and download the program to the board + +### Running Results + +After the program is successfully downloaded, the system runs automatically. Observe the running results of the LED on the development board, the LD3 and LD1 will light all the time, and LD2 will flash periodically. + +The USB virtual COM port connects to **USART2 by default**, and when the corresponding serial port (**115200-8-1-N**) is opened in the terminal tool, the output information of RT-Thread can be seen when the device is reset: + +```shell + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Dec 21 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` + +### Terminal tool - PuTTy + +If you don't have a terminal tool software available, you can download *PuTTy*: + +> https://www.chiark.greenend.org.uk/~sgtatham/putty/latest.html + +![putty](figures/putty.png) + + + +Follow these tutorial videos to learn PuTTy: + +> https://www.youtube.com/watch?v=ab4ilbsteWU +> +> https://www.youtube.com/watch?v=dO-BMOzNKcI + + + +## Advanced Features + +This BSP only enables GPIO and USART2 by default. If you need more advanced features such as SPI, I2C, you need to configure the BSP with RT-Thread [ENV tool](https://www.rt-thread.io/download.html?download=Env) , as follows: + +1. Open the Env tool under the specific BSP folder; +2. Enter `menuconfig` command to configure the project, then save and exit; +3. Enter `pkgs --update` command to update the package; +4. Enter `scons --target=mdk4/mdk5/iar` command to regenerate the project. + +Learn how to use RT-Thread Env, click [Here](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md). + + + +## Translated & Maintained By + +Cathy Lee @ RT-Thread Team + +> https://github.com/Cathy-lulu +> +> contact@rt-thread.org + +Meco Man @ RT-Thread Community + +> jiantingman@foxmail.com +> +> https://github.com/mysterywolf \ No newline at end of file diff --git a/bsp/stm32/docs/STM32系列BSP外设驱动使用教程.md b/bsp/stm32/docs/STM32系列BSP外设驱动使用教程.md index 704cb13216..ad0e7b2ece 100644 --- a/bsp/stm32/docs/STM32系列BSP外设驱动使用教程.md +++ b/bsp/stm32/docs/STM32系列BSP外设驱动使用教程.md @@ -1,4 +1,4 @@ -# BSP 外设驱动使用教程 +# STM32系列BSP外设驱动使用教程 ## 简介 @@ -12,7 +12,7 @@ ## 前提要求 -- 学会如何使用 ENV 工具，参考：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/rtthread-development-guide/rtthread-tool-manual/env/env-user-manual/) +- 学会如何使用 ENV 工具，参考：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/programming-manual/env/env/) ## 如何使用更多的板载资源 diff --git a/bsp/stm32/docs/STM32系列驱动介绍.md b/bsp/stm32/docs/STM32系列驱动介绍.md index e974bd23b9..45c9ec391f 100644 --- a/bsp/stm32/docs/STM32系列驱动介绍.md +++ b/bsp/stm32/docs/STM32系列驱动介绍.md @@ -1,4 +1,4 @@ -# 外设驱动介绍与应用 +# STM32系列驱动介绍 在 RT-Thread 实时操作系统中，各种各样的设备驱动是通过一套 I/O 设备管理框架来管理的。设备管理框架给上层应用提供了一套标准的设备操作 API，开发者通过调用这些标准设备操作 API，可以高效地完成和底层硬件外设的交互。设备管理框架的结构如下图所示： diff --git a/bsp/stm32/docs/figures/nucleo144_layout.jpg b/bsp/stm32/docs/figures/nucleo144_layout.jpg new file mode 100644 index 0000000000..20fca67e07 Binary files /dev/null and b/bsp/stm32/docs/figures/nucleo144_layout.jpg differ diff --git a/bsp/stm32/docs/figures/nucleo64_layout.jpg b/bsp/stm32/docs/figures/nucleo64_layout.jpg new file mode 100644 index 0000000000..4c7737bb85 Binary files /dev/null and b/bsp/stm32/docs/figures/nucleo64_layout.jpg differ diff --git a/bsp/stm32/docs/figures/putty.png b/bsp/stm32/docs/figures/putty.png new file mode 100644 index 0000000000..e1905b231e Binary files /dev/null and b/bsp/stm32/docs/figures/putty.png differ diff --git a/bsp/stm32/docs/figures/stm32-nucleo-144.png b/bsp/stm32/docs/figures/stm32-nucleo-144.png new file mode 100644 index 0000000000..52c791b7fb Binary files /dev/null and b/bsp/stm32/docs/figures/stm32-nucleo-144.png differ diff --git a/bsp/stm32/docs/figures/stm32-nucleo-64.jpg b/bsp/stm32/docs/figures/stm32-nucleo-64.jpg new file mode 100644 index 0000000000..b9cf52c5a5 Binary files /dev/null and b/bsp/stm32/docs/figures/stm32-nucleo-64.jpg differ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c index 93d3008d7d..4d44c968fc 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c @@ -193,7 +193,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch return -RT_ERROR; } -#if defined(SOC_SERIES_STM32MP1) || defined (SOC_SERIES_STM32H7) +#if defined(SOC_SERIES_STM32MP1) || defined (SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB) ADC_ChanConf.Rank = ADC_REGULAR_RANK_1; #else ADC_ChanConf.Rank = 1; @@ -205,22 +205,24 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5; #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES; -#elif defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB) +#elif defined(SOC_SERIES_STM32L4) ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; #elif defined(SOC_SERIES_STM32MP1) ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_810CYCLES_5; #elif defined(SOC_SERIES_STM32H7) ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_64CYCLES_5; + #elif defined (SOC_SERIES_STM32WB) + ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; #endif #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB) ADC_ChanConf.Offset = 0; #endif -#if defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB) +#if defined(SOC_SERIES_STM32L4) ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE; ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED; -#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) +#elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB) ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE; /* ADC channel affected to offset number */ ADC_ChanConf.Offset = 0; ADC_ChanConf.SingleDiff = ADC_SINGLE_ENDED; /* ADC channel differential mode */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c index 8d1995c41b..67bed660c0 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c @@ -26,7 +26,7 @@ #define gpioz_port_base (175) /* PIN_STPORT_MAX * 16 - 16 */ #define PIN_STPORT(pin) ((pin > gpioz_port_base) ? ((GPIO_TypeDef *)(GPIOZ_BASE )) : ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin))))) #else -#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin))))) +#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x1000u * PIN_PORT(pin)))) #endif /* GPIOZ */ #else #define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/SConscript b/bsp/stm32/libraries/STM32WBxx_HAL/SConscript index a0353c076c..d2f47a473d 100644 --- a/bsp/stm32/libraries/STM32WBxx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32WBxx_HAL/SConscript @@ -8,73 +8,73 @@ cwd = GetCurrentDir() src = Split(''' CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_comp.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_cortex.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_crc.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_crc_ex.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_cryp.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_cryp_ex.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_dma.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_dma_ex.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_exti.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_pwr.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_pwr_ex.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rcc.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rcc_ex.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rng.c -STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_gpio.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_crc_ex.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp_ex.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_exti.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c +STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c ''') if GetDepend(['RT_USING_SERIAL']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_uart.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_uart_ex.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_usart.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_usart_ex.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart_ex.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c'] if GetDepend(['RT_USING_I2C']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_i2c.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_i2c_ex.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c_ex.c'] if GetDepend(['RT_USING_SPI']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_spi.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_spi_ex.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_qspi.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_spi_ex.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_qspi.c'] if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']): -# src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_hcd.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_pcd.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_pcd_ex.c'] -# src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_ll_usb.c'] +# src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hcd.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pcd_ex.c'] +# src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_usb.c'] if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_lptim.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_tim.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_tim_ex.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c'] if GetDepend(['RT_USING_ADC']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_adc.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_adc_ex.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c'] if GetDepend(['RT_USING_RTC']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rtc.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rtc_ex.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rtc_ex.c'] if GetDepend(['RT_USING_WDT']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_iwdg.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_wwdg.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_iwdg.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c'] if GetDepend(['RT_USING_AUDIO']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_sai.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_sai_ex.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_sai_ex.c'] if GetDepend(['RT_USING_PM']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_lptim.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_lptim.c'] if GetDepend(['BSP_USING_ON_CHIP_FLASH']): - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_flash.c'] - src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_flash_ex.c'] -# src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_flash_ramfunc.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c'] + src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c'] +# src += ['STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ramfunc.c'] diff --git a/bsp/stm32/stm32f072-st-nucleo/README.md b/bsp/stm32/stm32f072-st-nucleo/README.md index e2d1a3e0ac..70ccb00115 100644 --- a/bsp/stm32/stm32f072-st-nucleo/README.md +++ b/bsp/stm32/stm32f072-st-nucleo/README.md @@ -1,105 +1,110 @@ -# NUCLEO-F072RB 开发板 BSP 说明 +# STM32F072-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为刘恒为 NUCLEO-F072RB 开发板提供的 BSP (板级支持包) 说明。 +## MCU: STM32F072RB @48MHz, 128KB FLASH, 16KB RAM -主要内容如下： +The STM32F072x8/xB microcontrollers incorporate the high-performance ARM®Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (up to 128 Kbytes of Flash memory and 16 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (two I2Cs, two SPI/I2S, one HDMI CEC and four USARTs), one USB Full-speed device (crystal-less), one CAN, one 12-bit ADC, one 12-bit DAC with two channels, seven 16-bit timers, one 32-bit timer and an advanced-control PWM timer. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32F072x8/xB microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. +The STM32F072x8/xB microcontrollers include devices in seven different packages ranging from 48 pins to 100 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included. +These features make the STM32F072x8/xB microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 +- Core: ARM®32-bit Cortex®-M0 CPU, frequency up to 48 MHz -NUCLEO-F072RB 是 ST 官方推出的开发板，搭载 STM32F072RBT6 芯片，基于 ARM Cortex-M0 内核，最高主频 48 MHz，具有丰富的板载资源，可以充分发挥 STM32F072RBT6 的芯片性能。 +- Memories -开发板外观如下图所示： + - 64 to 128 Kbytes of Flash memory + - 16 Kbytes of SRAM with HW parity -![board](figures/board.jpg) +- CRC calculation unit -NUCLEO-F072RB 开发板常用 **板载资源** 如下： +- Reset and power management -- MCU：STM32F072RBT6，主频 48MHz，128KB FLASH ，16KB RAM -- 常用外设 - - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 - - 按键：2 个，USER and RESET 。 -- 常用接口：USB 转串口、Arduino Uno 和 ST morpho 两类扩展接口 -- 调试接口：板载 ST-LINK/V2-1 调试器。 + - Digital and I/O supply: VDD= 2.0 V to 3.6 V + - Analog supply: VDDA= VDDto 3.6 V + - Selected I/Os: VDDIO2= 1.65 V to 3.6 V + - Power-on/Power down reset (POR/PDR) + - Programmable voltage detector (PVD) + - Low power modes: Sleep, Stop, Standby + - VBATsupply for RTC and backup registers -开发板更多详细信息请参考意法半导体[NUCLEO-F072RB](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-f072rb.html) +- Clock management -## 外设支持 + - 4 to 32 MHz crystal oscillator + - 32 kHz oscillator for RTC with calibration + - Internal 8 MHz RC with x6 PLL option + - Internal 40 kHz RC oscillator + - Internal 48 MHz oscillator with automatic trimming based on ext. synchronization -本 BSP 目前对外设的支持情况如下： +- Up to 87 fast I/Os -| **片上外设** | **支持情况** | **备注** | -| :------------ | :----------: | :-----------------------------------: | -| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...63 | -| UART | 支持 | UART2 | -| LED | 支持 | LED2 | + - All mappable on external interrupt vectors + - Up to 68 I/Os with 5V tolerant capability and 19 with independent supply VDDIO2 -## 使用说明 +- Seven-channel DMA controller -使用说明分为如下两个章节： +- One 12-bit, 1.0 μs ADC (up to 16 channels) -- 快速上手 + - Conversion range: 0 to 3.6 V + - Separate analog supply: 2.4 V to 3.6 V - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +- One 12-bit D/A converter (with 2 channels) -- 进阶使用 +- Two fast low-power analog comparators with programmable input and output - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 +- Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors + +- Calendar RTC with alarm and periodic wakeup from Stop/Standby + +- 12 timers + + - One 16-bit advanced-control timer for six-channel PWM output + - One 32-bit and seven 16-bit timers, with up to four IC/OC, OCN, usable for IR control decoding or DAC control + - Independent and system watchdog timers + - SysTick timer + +- Communication interfaces + + - Two I2C interfaces supporting Fast Mode Plus (1 Mbit/s) with 20 mA current sink, one supporting SMBus/PMBus and wakeup + - Four USARTs supporting master synchronous SPI and modem control, two with ISO7816 interface, LIN, IrDA, auto baud rate detection and wakeup feature + - Two SPIs (18 Mbit/s) with 4 to 16 programmable bit frames, and with I2S interface multiplexed + - CAN interface + - USB 2.0 full-speed interface, able to run from internal 48 MHz oscillator and with BCD and LPM support + +- HDMI CEC wakeup on header reception + +- Serial wire debug (SWD) + +- 96-bit unique ID + +- All packages ECOPACK®2 -### 快速上手 -本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 +## Read more -#### 硬件连接 +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32F072RB ST Official Website](https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-mainstream-mcus/stm32f0-series/stm32f0x2/stm32f072rb.html#documentation) | STM32F072RB datasheet and other resources | -使用 Type-A to Mini-B 线连接开发板和 PC 供电，红色 LED LD3 (PWR) 和 LD1 (COM) 会点亮。 -#### 编译下载 -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 +## Maintained By -> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 +[刘恒](https://github.com/lhxzui) -#### 运行结果 +iuzxhl@qq.com -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、绿色 LD2 会周期性闪烁。 -USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: -``` - \ | / -- RT - Thread Operating System - / | \ 4.0.2 build May 30 2019 - 2006 - 2019 Copyright by rt-thread team -msh > -``` +## Translated By -### 进阶使用 +Meco Man @ RT-Thread Community -此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -## 联系人信息 - -维护人: - -- [刘恒](https://github.com/lhxzui), 邮箱： \ No newline at end of file +> jiantingman@foxmail.com +> +> https://github.com/mysterywolf \ No newline at end of file diff --git a/bsp/stm32/stm32f072-st-nucleo/README_zh.md b/bsp/stm32/stm32f072-st-nucleo/README_zh.md new file mode 100644 index 0000000000..e2d1a3e0ac --- /dev/null +++ b/bsp/stm32/stm32f072-st-nucleo/README_zh.md @@ -0,0 +1,105 @@ +# NUCLEO-F072RB 开发板 BSP 说明 + +## 简介 + +本文档为刘恒为 NUCLEO-F072RB 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +NUCLEO-F072RB 是 ST 官方推出的开发板，搭载 STM32F072RBT6 芯片，基于 ARM Cortex-M0 内核，最高主频 48 MHz，具有丰富的板载资源，可以充分发挥 STM32F072RBT6 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +NUCLEO-F072RB 开发板常用 **板载资源** 如下： + +- MCU：STM32F072RBT6，主频 48MHz，128KB FLASH ，16KB RAM +- 常用外设 + - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 + - 按键：2 个，USER and RESET 。 +- 常用接口：USB 转串口、Arduino Uno 和 ST morpho 两类扩展接口 +- 调试接口：板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考意法半导体[NUCLEO-F072RB](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-f072rb.html) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :----------: | :-----------------------------------: | +| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...63 | +| UART | 支持 | UART2 | +| LED | 支持 | LED2 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用 Type-A to Mini-B 线连接开发板和 PC 供电，红色 LED LD3 (PWR) 和 LD1 (COM) 会点亮。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、绿色 LD2 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build May 30 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +## 联系人信息 + +维护人: + +- [刘恒](https://github.com/lhxzui), 邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f091-st-nucleo/README.md b/bsp/stm32/stm32f091-st-nucleo/README.md index 00706886ad..d3c4da954d 100644 --- a/bsp/stm32/stm32f091-st-nucleo/README.md +++ b/bsp/stm32/stm32f091-st-nucleo/README.md @@ -1,4 +1,4 @@ -# STM32F091RC-Nucleo BSP (Board Support Package) Execution Instruction +# STM32F091-Nucleo BSP Introduction [中文页](README_zh.md) | @@ -14,11 +14,13 @@ The document is covered in three parts: By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + + ## STM32F091RC-Nucleo Resources Introduction The STM32F091RC-Nucleo is a development board that contains a ARM Cortex-M0. The maximum main frequency is 48 MHz, and it has a wealth of on-board resources that can take full advantage of the STM32F091's chip performance. -[![board](https://github.com/RT-Thread/rt-thread/raw/master/bsp/stm32/stm32f091-st-nucleo/figures/board.jpg)](https://github.com/RT-Thread/rt-thread/blob/master/bsp/stm32/stm32f091-st-nucleo/figures/board.jpg) +[![board](figures\board.jpg)](https://github.com/RT-Thread/rt-thread/blob/master/bsp/stm32/stm32f091-st-nucleo/figures/board.jpg) The mainly-used resources of this board are shown as follows: @@ -27,7 +29,11 @@ The mainly-used resources of this board are shown as follows: - External FLASH: None - Common peripherals -Button: one, user (has the wake-up feature, PC13) - Common-used interfaces: USB, Arduino interface, etc. -- Debug interface: standard SWD For more details about this board, please refer to [ST official](https://www.st.com/en/evaluation-tools/stm32-nucleo-boards.html?querycriteria=productId=LN1847). +- Debug interface: Standard SWD interface. + +### For more details about this board, please refer to [ST official](https://www.st.com/en/evaluation-tools/stm32-nucleo-boards.html?querycriteria=productId=LN1847). + + ## **Peripheral Condition** @@ -48,9 +54,9 @@ Each peripheral supporting condition for this BSP is as follows: | FLASH | Support | | | IWGSupport | | | -## Execution Instruction -### Quickly Get Started + +## Quickly Get Started This BSP provides MDK4, MDK5, and IAR projects for developers and it supports the GCC development environment. Here's an example of the MDK5 development environment, to introduce how to run the system. diff --git a/bsp/stm32/stm32f103-atk-warshipv3/project.uvoptx b/bsp/stm32/stm32f103-atk-warshipv3/project.uvoptx index a17f1c7696..dd79d25fae 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/project.uvoptx +++ b/bsp/stm32/stm32f103-atk-warshipv3/project.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -178,6 +178,7 @@ 1 + 0 0 2 10000000 @@ -186,7 +187,7 @@ - Kernel + Applications 0 0 0 @@ -198,194 +199,6 @@ 0 0 0 - ..\..\..\src\clock.c - clock.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - ..\..\..\src\components.c - components.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - ..\..\..\src\cpu.c - cpu.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - ..\..\..\src\device.c - device.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - ..\..\..\src\idle.c - idle.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - ..\..\..\src\mem.c - mem.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - ..\..\..\src\signal.c - signal.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 1 - 15 - 1 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c - 0 - 0 - - - - - Applications - 1 - 0 - 0 - 0 - - 2 - 16 - 1 - 0 - 0 - 0 applications\main.c main.c 0 @@ -393,86 +206,6 @@ - - Drivers - 0 - 0 - 0 - 0 - - 3 - 17 - 1 - 0 - 0 - 0 - board\board.c - board.c - 0 - 0 - - - 3 - 18 - 1 - 0 - 0 - 0 - board\CubeMX_Config\Src\stm32f1xx_hal_msp.c - stm32f1xx_hal_msp.c - 0 - 0 - - - 3 - 19 - 2 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xe.s - startup_stm32f103xe.s - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_gpio.c - drv_gpio.c - 0 - 0 - - - 3 - 21 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_usart.c - drv_usart.c - 0 - 0 - - - 3 - 22 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_common.c - drv_common.c - 0 - 0 - - - cpu 0 @@ -480,8 +213,8 @@ 0 0 - 4 - 23 + 2 + 2 1 0 0 @@ -492,8 +225,8 @@ 0 - 4 - 24 + 2 + 3 1 0 0 @@ -504,8 +237,8 @@ 0 - 4 - 25 + 2 + 4 1 0 0 @@ -516,8 +249,8 @@ 0 - 4 - 26 + 2 + 5 1 0 0 @@ -528,8 +261,8 @@ 0 - 4 - 27 + 2 + 6 2 0 0 @@ -548,8 +281,8 @@ 0 0 - 5 - 28 + 3 + 7 1 0 0 @@ -560,8 +293,8 @@ 0 - 5 - 29 + 3 + 8 1 0 0 @@ -572,8 +305,8 @@ 0 - 5 - 30 + 3 + 9 1 0 0 @@ -584,8 +317,8 @@ 0 - 5 - 31 + 3 + 10 1 0 0 @@ -596,8 +329,8 @@ 0 - 5 - 32 + 3 + 11 1 0 0 @@ -608,8 +341,8 @@ 0 - 5 - 33 + 3 + 12 1 0 0 @@ -620,8 +353,8 @@ 0 - 5 - 34 + 3 + 13 1 0 0 @@ -632,8 +365,8 @@ 0 - 5 - 35 + 3 + 14 1 0 0 @@ -644,8 +377,8 @@ 0 - 5 - 36 + 3 + 15 1 0 0 @@ -657,6 +390,86 @@ + + Drivers + 0 + 0 + 0 + 0 + + 4 + 16 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + board\CubeMX_Config\Src\stm32f1xx_hal_msp.c + stm32f1xx_hal_msp.c + 0 + 0 + + + 4 + 18 + 2 + 0 + 0 + 0 + ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xe.s + startup_stm32f103xe.s + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_usart.c + drv_usart.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_common.c + drv_common.c + 0 + 0 + + + finsh 0 @@ -664,8 +477,8 @@ 0 0 - 6 - 37 + 5 + 22 1 0 0 @@ -676,20 +489,8 @@ 0 - 6 - 38 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\symbol.c - symbol.c - 0 - 0 - - - 6 - 39 + 5 + 23 1 0 0 @@ -700,8 +501,8 @@ 0 - 6 - 40 + 5 + 24 1 0 0 @@ -711,27 +512,179 @@ 0 0 + + + + Kernel + 0 + 0 + 0 + 0 6 - 41 + 25 1 0 0 0 - ..\..\..\components\finsh\msh_cmd.c - msh_cmd.c + ..\..\..\src\clock.c + clock.c 0 0 6 - 42 + 26 1 0 0 0 - ..\..\..\components\finsh\msh_file.c - msh_file.c + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 27 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 6 + 28 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 29 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\signal.c + signal.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c 0 0 @@ -745,7 +698,7 @@ 0 7 - 43 + 39 1 0 0 @@ -757,7 +710,7 @@ 7 - 44 + 40 1 0 0 @@ -769,7 +722,7 @@ 7 - 45 + 41 1 0 0 @@ -781,7 +734,7 @@ 7 - 46 + 42 1 0 0 @@ -793,7 +746,7 @@ 7 - 47 + 43 1 0 0 @@ -805,7 +758,7 @@ 7 - 48 + 44 1 0 0 @@ -817,7 +770,7 @@ 7 - 49 + 45 1 0 0 @@ -829,7 +782,7 @@ 7 - 50 + 46 1 0 0 @@ -841,7 +794,7 @@ 7 - 51 + 47 1 0 0 @@ -853,19 +806,7 @@ 7 - 52 - 1 - 0 - 0 - 0 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_sram.c - stm32f1xx_hal_sram.c - 0 - 0 - - - 7 - 53 + 48 1 0 0 @@ -877,7 +818,7 @@ 7 - 54 + 49 1 0 0 @@ -889,7 +830,7 @@ 7 - 55 + 50 1 0 0 @@ -901,7 +842,7 @@ 7 - 56 + 51 1 0 0 diff --git a/bsp/stm32/stm32f103-atk-warshipv3/project.uvprojx b/bsp/stm32/stm32f103-atk-warshipv3/project.uvprojx index a6feed2fa2..365c095541 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/project.uvprojx +++ b/bsp/stm32/stm32f103-atk-warshipv3/project.uvprojx @@ -10,12 +10,13 @@ rt-thread 0x4 ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC 0 STM32F103ZE STMicroelectronics - Keil.STM32F1xx_DFP.2.2.0 + Keil.STM32F1xx_DFP.2.3.0 http://www.keil.com/pack/ IROM(0x08000000,0x80000) IRAM(0x20000000,0x10000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE @@ -51,7 +52,7 @@ rt-thread 1 0 - 1 + 0 1 0 .\build\keil\List\ @@ -183,6 +184,7 @@ 0 0 0 + 0 0 0 8 @@ -336,7 +338,7 @@ USE_HAL_DRIVER, STM32F103xE - .;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Include;..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Inc;..\libraries\STM32F1xx_HAL\CMSIS\Include + applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports\include;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Include;..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Inc;..\libraries\STM32F1xx_HAL\CMSIS\Include @@ -370,93 +372,13 @@ .\board\linker_scripts\link.sct - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c - - - cpu.c - 1 - ..\..\..\src\cpu.c - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c - 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - irq.c - 1 - ..\..\..\src\irq.c - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - mem.c - 1 - ..\..\..\src\mem.c - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - object.c - 1 - ..\..\..\src\object.c - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - signal.c - 1 - ..\..\..\src\signal.c - - - thread.c - 1 - ..\..\..\src\thread.c - - - timer.c - 1 - ..\..\..\src\timer.c - - - Applications @@ -467,41 +389,6 @@ - - Drivers - - - board.c - 1 - board\board.c - - - stm32f1xx_hal_msp.c - 1 - board\CubeMX_Config\Src\stm32f1xx_hal_msp.c - - - startup_stm32f103xe.s - 2 - ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xe.s - - - drv_gpio.c - 1 - ..\libraries\HAL_Drivers\drv_gpio.c - - - drv_usart.c - 1 - ..\libraries\HAL_Drivers\drv_usart.c - - - drv_common.c - 1 - ..\libraries\HAL_Drivers\drv_common.c - - - cpu @@ -582,6 +469,41 @@ + + Drivers + + + board.c + 1 + board\board.c + + + stm32f1xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f1xx_hal_msp.c + + + startup_stm32f103xe.s + 2 + ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xe.s + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + finsh @@ -590,11 +512,6 @@ 1 ..\..\..\components\finsh\shell.c - - symbol.c - 1 - ..\..\..\components\finsh\symbol.c - cmd.c 1 @@ -605,15 +522,80 @@ 1 ..\..\..\components\finsh\msh.c + + + + Kernel + - msh_cmd.c + clock.c 1 - ..\..\..\components\finsh\msh_cmd.c + ..\..\..\src\clock.c - msh_file.c + components.c 1 - ..\..\..\components\finsh\msh_file.c + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c @@ -665,11 +647,6 @@ 1 ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cec.c - - stm32f1xx_hal_sram.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_sram.c - stm32f1xx_hal_gpio.c 1 diff --git a/bsp/stm32/stm32f103-blue-pill/README.md b/bsp/stm32/stm32f103-blue-pill/README.md index 8a3dae848f..837b725768 100644 --- a/bsp/stm32/stm32f103-blue-pill/README.md +++ b/bsp/stm32/stm32f103-blue-pill/README.md @@ -15,9 +15,62 @@ By reading the ***Quickly Get Started*** section developers can quickly get thei -## Onboard Resources +## MCU Resources -The Blue Pill is a STM32F103 based development board with Cortex-M3 ARM CPU that runs at 72 MHz, 20 KB of RAM and 64 or 128 KB of flash memory. The microcontroller (MCU) has a USB port, two serial ports, 16 bit PWM pins and 12 bit ADC pins. It runs at 3.3V, but some of its pins are 5V tolerant. +The STM32F103xx medium-density performance line family incorporates the high-performance ARM®Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN. + +The devices operate from a 2.0 to 3.6 V power supply. They are available in both the –40 to +85 °C temperature range and the –40 to +105 °C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications. +The STM32F103xx medium-density performance line family includes devices in six different package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. +These features make the STM32F103xx medium-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs. + +KEY FEATURES + +- ARM® 32-bit Cortex®-M3 CPU Core + - 72 MHz maximum frequency,1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access + - Single-cycle multiplication and hardware division +- Memories + - 64 or 128 Kbytes of Flash memory + - 20 Kbytes of SRAM +- Clock, reset and supply management + - 2.0 to 3.6 V application supply and I/Os + - POR, PDR, and programmable voltage detector (PVD) + - 4-to-16 MHz crystal oscillator + - Internal 8 MHz factory-trimmed RC + - Internal 40 kHz RC + - PLL for CPU clock + - 32 kHz oscillator for RTC with calibration +- Low-power + - Sleep, Stop and Standby modes + - VBAT supply for RTC and backup registers +- 2 x 12-bit, 1 μs A/D converters (up to 16 channels) + - Conversion range: 0 to 3.6 V + - Dual-sample and hold capability + - Temperature sensor +- DMA + - 7-channel DMA controller + - Peripherals supported: Timers, ADC, SPIs, I2Cs and USARTs + +- Up to 80 fast I/O ports + - 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant +- Debug mode + - Serial wire debug (SWD) & JTAG interfaces +- 7 timers + - Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 16-bit, motor control PWM timer with dead-time generation and emergency stop + - 2 watchdog timers (Independent and Window) + - SysTick timer 24-bit downcounter +- Up to 9 communication interfaces + - Up to 2 x I2C interfaces (SMBus/PMBus) + - Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) + - Up to 2 SPIs (18 Mbit/s) + - CAN interface (2.0B Active) + - USB 2.0 full-speed interface +- CRC calculation unit, 96-bit unique ID +- Packages are ECOPACK® + + + +## Onboard Resources - MCU：STM32F103C8T6 @72MHz, 64KB FLASH , 20KB RAM @@ -40,7 +93,9 @@ This BSP provides MDK4, MDK5, and IAR projects for developers and it supports th ### Use ST-LINK Debugger to connect the Blue Pill Board -ST-LINK driver: https://www.st.com/en/development-tools/stsw-link009.html +ST-LINK driver: + +> https://www.st.com/en/development-tools/stsw-link009.html | ST-LINK Debugger | Blue Pill 4-Pin SWD | | :--------------: | :-----------------: | @@ -59,7 +114,9 @@ ST-LINK driver: https://www.st.com/en/development-tools/stsw-link009.html ### Use FTDI adapter(USB to UART) to connect the Blue Pill Board's PA9(Tx) and PA10(Rx) pins -FTDI adapter driver: https://www.ftdichip.com/FTDrivers.htm +FTDI adapter driver: + +> https://www.ftdichip.com/FTDrivers.htm You can use other USB to UART adapters to replace FTDI adapter. @@ -90,7 +147,7 @@ You can use other USB to UART adapters to replace FTDI adapter. ### Compile and Download -- Double-click the `project.uvprojx` file to open the MDK5 project (**NOT** `template.uvprojx` file) +- Double-click the `project.uvprojx` file to open the MDK-Keil5 project (**NOT** `template.uvprojx` file) - Click the “option for target” button - Debug: Choose "ST-LINK Debugger" and Click "Setting" button: - Port: choose "SW (Serial Wire)" @@ -98,13 +155,17 @@ You can use other USB to UART adapters to replace FTDI adapter. - Compile and download the program to the board +You can also follow this video to configurate *Blue Pill BSP* Keil5 project: + +> https://www.youtube.com/watch?v=0PwBBYXQ08g&t + ### Running Results After the program is successfully downloaded, the system runs automatically. Observe the running results of the LED on the development board, and you will see the LED is flashing periodically. -The USB virtual COM port connects to **USART1 (PA9-Tx, PA10-Rx) by default**, and when the corresponding serial port (**115200**-8-1-N) is opened in the terminal tool, the output information of RT-Thread can be seen when the device is reset: +The COM port connects to **USART1 (PA9-Tx, PA10-Rx) by default**, and when the corresponding serial port (**115200**-8-1-N) is opened in the terminal tool, the output information of RT-Thread can be seen when the device is reset: ```shell \ | / @@ -114,13 +175,29 @@ The USB virtual COM port connects to **USART1 (PA9-Tx, PA10-Rx) by default**, an msh > ``` -- If you have no terminal tool software available, you can download *Putty*: https://www.chiark.greenend.org.uk/~sgtatham/putty/latest.html + + +### Terminal tool - PuTTy + +If you have no terminal tool software available, you can download *PuTTy*: + +> https://www.chiark.greenend.org.uk/~sgtatham/putty/latest.html + +![putty](figures/putty.png) + + + +These two videos will show you how to use PuTTy: + +> https://www.youtube.com/watch?v=ab4ilbsteWU +> +> https://www.youtube.com/watch?v=dO-BMOzNKcI ## **Advanced Features** -This BSP only enables GPIO and USART1 by default. If you need more advanced features such as SPI, ADC, or to add software packages, you need to configure the BSP with RT-Thread [ENV tools](https://www.rt-thread.io/download.html?download=Env), as follows: +This BSP only enables GPIO and USART1 by default. If you need more advanced features such as SPI, ADC, or to add software packages, you need to configure the BSP with RT-Thread [ENV tool](https://www.rt-thread.io/download.html?download=Env), as follows: 1. Open the ENV tool under the specific BSP folder, eg: *bsp/stm32/stm32f103-blue-pill* ; 2. Enter `menuconfig` command to configure the project, then save and exit; @@ -133,10 +210,11 @@ Learn how to use RT-Thread ENV, click [Here](https://github.com/RT-Thread/rtthre ## Read more -- [[Schematic]](https://stm32duinoforum.com/forum/images/c/c1/wiki_subdomain/Vcc-gnd.com-STM32F103C8-schematic.pdf) +- [[STM32 Blue Pill Board Schematic]](https://stm32duinoforum.com/forum/images/c/c1/wiki_subdomain/Vcc-gnd.com-STM32F103C8-schematic.pdf) - [[STM32 Blue Pill vs Black Pill Microcontroller Boards]](https://www.youtube.com/watch?v=QCdnO43RBK4&t=875s) - [[STM32F103C8 datasheet]]( https://www.st.com/resource/en/datasheet/stm32f103c8.pdf) -- [[STM32F103C8 More Information]](https://www.st.com/en/microcontrollers-microprocessors/stm32f103c8.html#overview) +- [[STM32F103C8 More Information (ST official)]](https://www.st.com/en/microcontrollers-microprocessors/stm32f103c8.html#overview) +- [[RT-Thread document center]](https://www.rt-thread.io/document/site/introduction/introduction/) @@ -147,4 +225,4 @@ Meco Man @ RT-Thread Community jiantingman@foxmail.com -https://github.com/mysterywolf \ No newline at end of file +https://github.com/mysterywolf diff --git a/bsp/stm32/stm32f103-blue-pill/README.pdf b/bsp/stm32/stm32f103-blue-pill/README.pdf index 973eef4a39..69de85e9d8 100644 Binary files a/bsp/stm32/stm32f103-blue-pill/README.pdf and b/bsp/stm32/stm32f103-blue-pill/README.pdf differ diff --git a/bsp/stm32/stm32f103-blue-pill/README_zh.md b/bsp/stm32/stm32f103-blue-pill/README_zh.md index 4ff65a9908..422b06a0a4 100644 --- a/bsp/stm32/stm32f103-blue-pill/README_zh.md +++ b/bsp/stm32/stm32f103-blue-pill/README_zh.md @@ -111,9 +111,7 @@ msh > -## 联系人信息 +## 感谢 & 维护 -维护人: - -- [obito0](https://github.com/obito0), 邮箱：<496420502@qq.com> -- Meco Man: jiantingman@foxmail.com https://github.com/mysterywolf \ No newline at end of file +- 感谢[obito0](https://github.com/obito0)提供的[原始工程](../stm32f103-mini-system) +- [Meco Man](https://github.com/mysterywolf): jiantingman@foxmail.com \ No newline at end of file diff --git a/bsp/stm32/stm32f103-blue-pill/figures/jumper.jpg b/bsp/stm32/stm32f103-blue-pill/figures/jumper.jpg index 9b951363a2..5ce9b34745 100644 Binary files a/bsp/stm32/stm32f103-blue-pill/figures/jumper.jpg and b/bsp/stm32/stm32f103-blue-pill/figures/jumper.jpg differ diff --git a/bsp/stm32/stm32f103-blue-pill/figures/putty.png b/bsp/stm32/stm32f103-blue-pill/figures/putty.png new file mode 100644 index 0000000000..e1905b231e Binary files /dev/null and b/bsp/stm32/stm32f103-blue-pill/figures/putty.png differ diff --git a/bsp/stm32/stm32f410-st-nucleo/README.md b/bsp/stm32/stm32f410-st-nucleo/README.md index 5c4079d384..b75c883509 100644 --- a/bsp/stm32/stm32f410-st-nucleo/README.md +++ b/bsp/stm32/stm32f410-st-nucleo/README.md @@ -1,104 +1,88 @@ -# STM32F410-Nucleo-64 开发板 BSP 说明 +# STM32F410-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 RT-Thread 开发团队为 STM32F410-Nucleo-64 开发板提供的 BSP (板级支持包) 说明。 +## MCU: STM32F410RB @100MHz, 128KB FLASH, 32KB RAM -主要内容如下： +The STM32F410x8/B devices are based on the high-performance ARM®Cortex® -M4 32-bit RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32F410x8/B belong to the STM32 Dynamic Efficiency™ product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power consumption during data batching. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +The STM32F410x8/B incorporate high-speed embedded memories (up to 128 Kbytes of Flash memory, 32 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, one AHB bus and a 32-bit multi-AHB bus matrix. -## 开发板介绍 +All devices offer one 12-bit ADC, one 12-bit DAC, a low-power RTC, three general-purpose 16-bit timers, one PWM timer for motor control, one general-purpose 32-bit timers and one 16-bit low-power timer. They also feature standard and advanced communication interfaces. -探索者 STM32F410-Nucleo-64 是意法半导体推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 84Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F410RB 的芯片性能。 +#### KEY FEATURES -开发板外观如下图所示： +- Dynamic Efficiency Line with BAM (Batch Acquisition Mode) +- Core: ARM®32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit, 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions +- Memories + - Up to 128 Kbytes of Flash memory + - 512 bytes of OTP memory + - 32 Kbytes of SRAM +- Clock, reset and supply management + - 1.7 V to 3.6 V application supply and I/Os + - POR, PDR, PVD and BOR + - 4-to-26 MHz crystal oscillator + - Internal 16 MHz factory-trimmed RC + - 32 kHz oscillator for RTC with calibration + - Internal 32 kHz RC with calibration +- Power consumption + - Run: 89 μA/MHz (peripheral off) + - Stop (Flash in Stop mode, fast wakeup time): 40 μA Typ @ 25 °C; 49 μA max @25 °C + - Stop (Flash in Deep power down mode, fast wakeup time): down to 6 μA @ 25 °C; 14 μA max @25 °C + - Standby: 2.4 μA @25 °C / 1.7 V without RTC; 12 μA @85 °C @1.7 V + - VBATsupply for RTC: 1 μA @25 °C +- 1×12-bit, 2.4 MSPS ADC: up to 16 channels +- 1×12-bit D/A converter +- General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support +- Up to 9 timers + - One 16-bit advanced motor-control timer + - One low-power timer (available in Stop mode) + - Three 16-bit general purpose timers + - One 32-bit timer up to 100 MHz with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - Two watchdog timers (independent window) + - SysTick timer -![board](figures/board.png) - -该开发板常用 **板载资源** 如下： - -- MCU：STM32F410RBT6，主频 84MHz，128KB FLASH ，32KB RAM。 -- 常用外设 - - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 - - 按键，2 个，USER and RESET 。 -- 调试接口，板载 ST-LINK/V2-1 调试器。 - -开发板更多详细信息请参考意法半导体 [STM32F410-Nucleo-64 开发板介绍](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-f410rb.html)。 - -## 外设支持 - -本 BSP 目前对外设的支持情况如下： - -| **片上外设** | **支持情况** | **备注** | -| :------------ | :----------: | :-----------------------------------: | -| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...63 | -| UART | 支持 | UART2 | - -## 使用说明 - -使用说明分为如下两个章节： - -- 快速上手 - - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 +- Debug mode + - Serial wire debug (SWD) & JTAG interfaces + - Cortex®-M4 Embedded Trace Macrocell™ +- Up to 50 I/O ports with interrupt capability + - Up to 45 fast I/Os up to 100 MHz + - Up to 49 5 V-tolerant I/Os +- Up to 9 communication interfaces + - Up to 3x I2C interfaces (SMBus/PMBus) including 1x I2C Fast-mode at 1 MHz + - Up to 3 USARTs (2 x 12.5 Mbit/s, 1 x 6.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control) + - Up to 3 SPI/I2Ss (up to 50 Mbit/s SPI or I2S audio protocol) +- True random number generator +- CRC calculation unit +- 96-bit unique ID +- RTC: subsecond accuracy, hardware calendar +- All packages are ECOPACK®2 -### 快速上手 -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 +## Read more -#### 硬件连接 +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32F410RB ST Official Website](https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f4-series/stm32f410/stm32f410rb.html#documentation) | STM32F410RB datasheet and other resources | -使用 Type-A to Mini-B 线连接开发板和 PC 供电，红色 LED LD3 (PWR) 和 LD1 (COM) 会点亮。 -#### 编译下载 -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 +## Maintained By -> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 +[tanglj86](https://github.com/tanglj86/rt-thread) -#### 运行结果 +tanglj86@gmail.com -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、绿色 LD2 会周期性闪烁。 -USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.3 build Mar 7 2020 - 2006 - 2020 Copyright by rt-thread team -msh > -``` -### 进阶使用 +## Translated By -此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： +Meco Man @ RT-Thread Community -1. 在 BSP 下打开 env 工具。 - -2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 - -3. 输入 `pkgs --update` 命令更新软件包。 - -4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -暂无 - -## 联系人信息 - -维护人: - -- [tanglj86](https://github.com/tanglj86/rt-thread) ，邮箱： \ No newline at end of file +> jiantingman@foxmail.com +> +> https://github.com/mysterywolf \ No newline at end of file diff --git a/bsp/stm32/stm32f410-st-nucleo/README_zh.md b/bsp/stm32/stm32f410-st-nucleo/README_zh.md new file mode 100644 index 0000000000..02596fe98b --- /dev/null +++ b/bsp/stm32/stm32f410-st-nucleo/README_zh.md @@ -0,0 +1,104 @@ +# STM32F410-Nucleo-64 开发板 BSP 说明 + +## 简介 + +本文档为 RT-Thread 开发团队为 STM32F410-Nucleo-64 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +探索者 STM32F410-Nucleo-64 是意法半导体推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 84Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F410RB 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.png) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32F410RBT6，主频 100MHz，128KB FLASH ，32KB RAM。 +- 常用外设 + - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 + - 按键，2 个，USER and RESET 。 +- 调试接口，板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考意法半导体 [STM32F410-Nucleo-64 开发板介绍](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-f410rb.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :----------: | :-----------------------------------: | +| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...63 | +| UART | 支持 | UART2 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用 Type-A to Mini-B 线连接开发板和 PC 供电，红色 LED LD3 (PWR) 和 LD1 (COM) 会点亮。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、绿色 LD2 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Mar 7 2020 + 2006 - 2020 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 BSP 下打开 env 工具。 + +2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 + +3. 输入 `pkgs --update` 命令更新软件包。 + +4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [tanglj86](https://github.com/tanglj86/rt-thread) ，邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f411-atk-nano/project.ewp b/bsp/stm32/stm32f411-atk-nano/project.ewp index eb736f7ff9..6ccceff90f 100644 --- a/bsp/stm32/stm32f411-atk-nano/project.ewp +++ b/bsp/stm32/stm32f411-atk-nano/project.ewp @@ -215,6 +215,7 @@ @@ -342,19 +343,23 @@ @@ -1245,6 +1250,7 @@ @@ -1372,19 +1378,23 @@ @@ -2061,6 +2071,162 @@ + + Applications + + $PROJ_DIR$\applications\main.c + + + + cpu + + $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\rtc\rtc.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_flash_sfud.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\sfud\src\sfud.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\sfud\src\sfud_sfdp.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\watchdog\watchdog.c + + + + dlib + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\libc.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\rmtx.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\stdio.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\iar\startup_stm32f411xe.s + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_spi.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c + + + + finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + Kernel @@ -2106,93 +2272,6 @@ $PROJ_DIR$\..\..\..\src\timer.c - - Applications - - $PROJ_DIR$\applications\main.c - - - - Drivers - - $PROJ_DIR$\board\board.c - - - $PROJ_DIR$\board\CubeMX_Config\Src\stm32f4xx_hal_msp.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\iar\startup_stm32f411xe.s - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c - - - - cpu - - $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S - - - - DeviceDrivers - - $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c - - - $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\completion.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c - - - - finsh - - $PROJ_DIR$\..\..\..\components\finsh\shell.c - - - $PROJ_DIR$\..\..\..\components\finsh\cmd.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh.c - - libc @@ -2252,5 +2331,29 @@ $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rtc_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_iwdg.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + diff --git a/bsp/stm32/stm32f411-st-nucleo/README.md b/bsp/stm32/stm32f411-st-nucleo/README.md index ec84e51601..51f72e8a26 100644 --- a/bsp/stm32/stm32f411-st-nucleo/README.md +++ b/bsp/stm32/stm32f411-st-nucleo/README.md @@ -1,105 +1,82 @@ -# STM32F411-Nucleo-64 开发板 BSP 说明 +# STM32F411-Nucleo BSP Introduction -## 简介 +[中文](README_zh.md) -本文档为 RT-Thread 开发团队为 STM32F411-Nucleo-64 开发板提供的 BSP (板级支持包) 说明。 +## MCU: STM32F411RE @100MHz, 512KB FLASH, 128KB RAM -主要内容如下： +The STM32F411xC/xE devices are based on the high-performance Arm® Cortex® -M4 32-bit RISC core operating at a frequency of up to 100 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all Arm single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 +The STM32F411xC/xE belongs to the STM32 Dynamic Efficiency™ product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power consumption during data batching. +The STM32F411xC/xE incorporate high-speed embedded memories (up to 512 Kbytes of Flash memory, 128 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB bus and a 32-bit multi-AHB bus matrix. +All devices offer one 12-bit ADC, a low-power RTC, six general-purpose 16-bit timers including one PWM timer for motor control, two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces. +The STM32F411xC/xE operate in the - 40 to + 125 °C temperature range from a 1.7 (PDR OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. +These features make the STM32F411xC/xE microcontrollers suitable for a wide range of applications. -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 +#### KEY FEATURES -## 开发板介绍 - -探索者 STM32F411-Nucleo-64 是意法半导体推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 100Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F411RE 的芯片性能。 - -开发板外观如下图所示： - -![board](figures/board.png) - -该开发板常用 ** 板载资源 ** 如下： - -- MCU：STM32F407ZGT6，主频 100MHz，512KB FLASH ，128KB RAM。 -- 常用外设 - - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 - - 按键，2 个，USER and RESET 。 -- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 -- 调试接口，板载 ST-LINK/V2-1 调试器。 - -开发板更多详细信息请参考意法半导体 [STM32F411-Nucleo-64 开发板介绍](https://www.st.com/en/evaluation-tools/nucleo-f411re.html)。 - -## 外设支持 - -本 BSP 目前对外设的支持情况如下： - -| **片上外设** | **支持情况** | **备注** | -| :------------ | :----------: | :-----------------------------------: | -| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...63 | -| UART | 支持 | UART2 | - -## 使用说明 - -使用说明分为如下两个章节： - -- 快速上手 - - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 +- Dynamic Efficiency Line with BAM (Batch Acquisition Mode) + - 1.7 V to 3.6 V power supply + - 40°C to 85/105/125 °C temperature range +- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit, 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions +- Memories + - Up to 512 Kbytes of Flash memory + - 128 Kbytes of SRAM +- Clock, reset and supply management + - 1.7 V to 3.6 V application supply and I/Os + - POR, PDR, PVD and BOR + - 4-to-26 MHz crystal oscillator + - Internal 16 MHz factory-trimmed RC + - 32 kHz oscillator for RTC with calibration + - Internal 32 kHz RC with calibration +- Power consumption + - Run: 100 μA/MHz (peripheral off) + - Stop (Flash in Stop mode, fast wakeup time): 42 μA Typ @ 25C; 65 μA max @25 °C + - Stop (Flash in Deep power down mode, slow wakeup time): down to 9 μA @ 25 °C; 28 μA max @25 °C + - Standby: 1.8 μA @25 °C / 1.7 V without RTC; 11 μA @85 °C @1.7 V + - VBAT supply for RTC: 1 μA @25 °C +- 1×12-bit, 2.4 MSPS A/D converter: up to 16 channels +- General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support +- Up to 11 timers: up to six 16-bit, two 32-bit timers up to 100 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog timers (independent and window) and a SysTick timer +- Debug mode + - Serial wire debug (SWD) & JTAG interfaces + - Cortex®-M4 Embedded Trace Macrocell™ +- Up to 81 I/O ports with interrupt capability + - Up to 78 fast I/Os up to 100 MHz + - Up to 77 5 V-tolerant I/Os +- Up to 13 communication interfaces + - Up to 3 x I2C interfaces (SMBus/PMBus) + - Up to 3 USARTs (2 x 12.5 Mbit/s, 1 x 6.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control) + - Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or I2S audio protocol), SPI2 and SPI3 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock + - SDIO interface (SD/MMC/eMMC) + - Advanced connectivity: USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC: subsecond accuracy, hardware calendar +- All packages (WLCSP49, LQFP64/100, UFQFPN48, UFBGA100) are ECOPACK®2 -### 快速上手 -本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 +## Read more -#### 硬件连接 +| Documents | Description | +| :----------------------------------------------------------: | :----------------------------------------------------------: | +| [STM32_Nucleo-64_BSP_Introduction](../docs/STM32_Nucleo-64_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-64 boards (**Must-Read**) | +| [STM32F411RE ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32f411re.html#documentation) | STM32F411RE datasheet and other resources | -使用 Type-A to Mini-B 线连接开发板和 PC 供电，红色 LED LD3 (PWR) 和 LD1 (COM) 会点亮。 -#### 编译下载 -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 +## Maintained By -> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 +[misonyo](https://github.com/misonyo) -#### 运行结果 +misonyo@foxmail.com -下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、绿色 LD2 会周期性闪烁。 -USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: -```bash - \ | / -- RT - Thread Operating System - / | \ 3.1.1 build Nov 19 2018 - 2006 - 2018 Copyright by rt-thread team -msh > -``` -### 进阶使用 +## Translated By -此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： +Meco Man @ RT-Thread Community -1. 在 BSP 下打开 env 工具。 - -2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 - -3. 输入 `pkgs --update` 命令更新软件包。 - -4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32 系列 BSP 外设驱动使用教程. md)。 - -## 注意事项 - -暂无 - -## 联系人信息 - -维护人: - -- [misonyo](https://github.com/misonyo) ，邮箱： \ No newline at end of file +> jiantingman@foxmail.com +> +> https://github.com/mysterywolf \ No newline at end of file diff --git a/bsp/stm32/stm32f411-st-nucleo/README_zh.md b/bsp/stm32/stm32f411-st-nucleo/README_zh.md new file mode 100644 index 0000000000..ec84e51601 --- /dev/null +++ b/bsp/stm32/stm32f411-st-nucleo/README_zh.md @@ -0,0 +1,105 @@ +# STM32F411-Nucleo-64 开发板 BSP 说明 + +## 简介 + +本文档为 RT-Thread 开发团队为 STM32F411-Nucleo-64 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +探索者 STM32F411-Nucleo-64 是意法半导体推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 100Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F411RE 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.png) + +该开发板常用 ** 板载资源 ** 如下： + +- MCU：STM32F407ZGT6，主频 100MHz，512KB FLASH ，128KB RAM。 +- 常用外设 + - LED：3 个，USB communication (LD1), user LED (LD2), power LED (LD3) 。 + - 按键，2 个，USER and RESET 。 +- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口。 +- 调试接口，板载 ST-LINK/V2-1 调试器。 + +开发板更多详细信息请参考意法半导体 [STM32F411-Nucleo-64 开发板介绍](https://www.st.com/en/evaluation-tools/nucleo-f411re.html)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :----------: | :-----------------------------------: | +| GPIO | 支持 | PA0, PA1... PH1 ---> PIN: 0, 1...63 | +| UART | 支持 | UART2 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用 Type-A to Mini-B 线连接开发板和 PC 供电，红色 LED LD3 (PWR) 和 LD1 (COM) 会点亮。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 ST-LINK 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LD3 和 LD1 常亮、绿色 LD2 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 3.1.1 build Nov 19 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 BSP 下打开 env 工具。 + +2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 + +3. 输入 `pkgs --update` 命令更新软件包。 + +4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32 系列 BSP 外设驱动使用教程. md)。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [misonyo](https://github.com/misonyo) ，邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.icf b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.icf index 03094ef488..fe7f695495 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.icf @@ -18,7 +18,7 @@ define symbol __ICFEDIT_size_heap__ = 0x0000; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; diff --git a/bsp/stm32/stm32f429-st-disco/project.ewp b/bsp/stm32/stm32f429-st-disco/project.ewp index 98701564c3..94928771cc 100644 --- a/bsp/stm32/stm32f429-st-disco/project.ewp +++ b/bsp/stm32/stm32f429-st-disco/project.ewp @@ -1,2455 +1,2454 @@ - - 3 - - Debug - - ARM - + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 1 - - General - 3 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 35 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 10 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 23 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 0 - - General - 3 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 35 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 10 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 23 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Applications - - $PROJ_DIR$\applications\lcd_init.c - - - $PROJ_DIR$\applications\main.c - - - - cpu - - $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c - - - - DeviceDrivers - - $PROJ_DIR$\..\..\..\components\drivers\src\completion.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c-bit-ops.c - - - $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_core.c - - - $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_dev.c - - - $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c - - - $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c - - - - dlib - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\libc.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\rmtx.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\stdio.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - - Drivers - - $PROJ_DIR$\board\board.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\iar\startup_stm32f429xx.s - - - $PROJ_DIR$\board\CubeMX_Config\Src\stm32f4xx_hal_msp.c - - - - Filesystem - - $PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs\devfs.c - - - $PROJ_DIR$\..\..\..\components\dfs\src\dfs.c - - - $PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c - - - $PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c - - - $PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c - - - $PROJ_DIR$\..\..\..\components\dfs\src\poll.c - - - $PROJ_DIR$\..\..\..\components\dfs\src\select.c - - - - finsh - - $PROJ_DIR$\..\..\..\components\finsh\cmd.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_compiler.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_error.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_heap.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_init.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_node.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_ops.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_parser.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_token.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_var.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_vm.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh_file.c - - - $PROJ_DIR$\..\..\..\components\finsh\shell.c - - - - Kernel - - $PROJ_DIR$\..\..\..\src\clock.c - - - $PROJ_DIR$\..\..\..\src\components.c - - - $PROJ_DIR$\..\..\..\src\device.c - - - $PROJ_DIR$\..\..\..\src\idle.c - - - $PROJ_DIR$\..\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\..\src\irq.c - - - $PROJ_DIR$\..\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\..\src\mem.c - - - $PROJ_DIR$\..\..\..\src\memheap.c - - - $PROJ_DIR$\..\..\..\src\mempool.c - - - $PROJ_DIR$\..\..\..\src\object.c - - - $PROJ_DIR$\..\..\..\src\scheduler.c - - - $PROJ_DIR$\..\..\..\src\signal.c - - - $PROJ_DIR$\..\..\..\src\thread.c - - - $PROJ_DIR$\..\..\..\src\timer.c - - - - libc - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c - - - - STM32_HAL - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c - - - $PROJ_DIR$\..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\spi\spi_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + + + dlib + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\libc.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\rmtx.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\stdio.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + $PROJ_DIR$\board\ports\ili9341.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\iar\startup_stm32f429xx.s + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_spi.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_sdram.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_lcd.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c + + + + Filesystem + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\poll.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\select.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs\devfs.c + + + + finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_file.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\signal.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + libc + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\unistd.c + + + $PROJ_DIR$\..\..\..\components\libc\signal\posix_signal.c + + + + pthreads + + $PROJ_DIR$\..\..\..\components\libc\pthreads\mqueue.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_attr.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_barrier.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_cond.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_mutex.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_rwlock.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_spin.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\pthread_tls.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\sched.c + + + $PROJ_DIR$\..\..\..\components\libc\pthreads\semaphore.c + + + $PROJ_DIR$\..\..\..\components\libc\time\clock_time.c + + + $PROJ_DIR$\..\..\..\components\libc\time\posix_sleep.c + + + + STM32_HAL + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cec.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cryp_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rng.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_dma2d.c + + + $PROJ_DIR$\..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c + + diff --git a/bsp/stm32/stm32f429-st-disco/project.uvprojx b/bsp/stm32/stm32f429-st-disco/project.uvprojx index 1eabc6fa01..b6adb12dd1 100644 --- a/bsp/stm32/stm32f429-st-disco/project.uvprojx +++ b/bsp/stm32/stm32f429-st-disco/project.uvprojx @@ -13,8 +13,8 @@ STM32F429ZITx STMicroelectronics - Keil.STM32F4xx_DFP.2.14.0 - http://www.keil.com/pack/ + Keil.STM32F4xx_DFP.2.13.0 + http://www.keil.com/pack IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x200000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -51,7 +51,7 @@ 0 0 1 - 1 + 0 .\Listings\ 1 0 @@ -335,7 +335,7 @@ USE_HAL_DRIVER, RT_USING_ARM_LIBC, STM32F429xx - .;..\..\..\include;applications;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include + applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\..\..\components\libc\signal;..\..\..\components\libc\pthreads;..\..\..\components\libc\time;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include @@ -376,114 +376,6 @@ - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - - - components.c - 1 - ..\..\..\src\components.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - - - idle.c - 1 - ..\..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\..\src\mem.c - - - - - memheap.c - 1 - ..\..\..\src\memheap.c - - - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - - - object.c - 1 - ..\..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - - - signal.c - 1 - ..\..\..\src\signal.c - - - - - thread.c - 1 - ..\..\..\src\thread.c - - - - - timer.c - 1 - ..\..\..\src\timer.c - - - Applications @@ -501,51 +393,6 @@ - - Drivers - - - board.c - 1 - board\board.c - - - - - stm32f4xx_hal_msp.c - 1 - board\CubeMX_Config\Src\stm32f4xx_hal_msp.c - - - - - startup_stm32f429xx.s - 2 - ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f429xx.s - - - - - drv_gpio.c - 1 - ..\libraries\HAL_Drivers\drv_gpio.c - - - - - drv_usart.c - 1 - ..\libraries\HAL_Drivers\drv_usart.c - - - - - drv_common.c - 1 - ..\libraries\HAL_Drivers\drv_common.c - - - cpu @@ -584,6 +431,192 @@ + + DeviceDrivers + + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + + + i2c-bit-ops.c + 1 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + + + + + + + + + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32f4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32f4xx_hal_msp.c + + + + + ili9341.c + 1 + board\ports\ili9341.c + + + + + startup_stm32f429xx.s + 2 + ..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f429xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_spi.c + 1 + ..\libraries\HAL_Drivers\drv_spi.c + + + + + drv_sdram.c + 1 + ..\libraries\HAL_Drivers\drv_sdram.c + + + + + drv_lcd.c + 1 + ..\libraries\HAL_Drivers\drv_lcd.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + Filesystem @@ -636,93 +669,6 @@ - - DeviceDrivers - - - i2c_core.c - 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - - - i2c-bit-ops.c - 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - - - - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c - - - - - pipe.c - 1 - ..\..\..\components\drivers\src\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\src\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\..\components\drivers\src\ringbuffer.c - - - - - waitqueue.c - 1 - ..\..\..\components\drivers\src\waitqueue.c - - - - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - - - finsh @@ -753,74 +699,105 @@ ..\..\..\components\finsh\msh_file.c + + + Kernel - finsh_compiler.c + clock.c 1 - ..\..\..\components\finsh\finsh_compiler.c + ..\..\..\src\clock.c - finsh_error.c + components.c 1 - ..\..\..\components\finsh\finsh_error.c + ..\..\..\src\components.c - finsh_heap.c + device.c 1 - ..\..\..\components\finsh\finsh_heap.c + ..\..\..\src\device.c - finsh_init.c + idle.c 1 - ..\..\..\components\finsh\finsh_init.c + ..\..\..\src\idle.c - finsh_node.c + ipc.c 1 - ..\..\..\components\finsh\finsh_node.c + ..\..\..\src\ipc.c - finsh_ops.c + irq.c 1 - ..\..\..\components\finsh\finsh_ops.c + ..\..\..\src\irq.c - finsh_parser.c + kservice.c 1 - ..\..\..\components\finsh\finsh_parser.c + ..\..\..\src\kservice.c - finsh_var.c + memheap.c 1 - ..\..\..\components\finsh\finsh_var.c + ..\..\..\src\memheap.c - finsh_vm.c + mempool.c 1 - ..\..\..\components\finsh\finsh_vm.c + ..\..\..\src\mempool.c - finsh_token.c + object.c 1 - ..\..\..\components\finsh\finsh_token.c + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c @@ -861,6 +838,114 @@ ..\..\..\components\libc\compilers\common\time.c + + + unistd.c + 1 + ..\..\..\components\libc\compilers\common\unistd.c + + + + + posix_signal.c + 1 + ..\..\..\components\libc\signal\posix_signal.c + + + + + pthreads + + + mqueue.c + 1 + ..\..\..\components\libc\pthreads\mqueue.c + + + + + pthread.c + 1 + ..\..\..\components\libc\pthreads\pthread.c + + + + + pthread_attr.c + 1 + ..\..\..\components\libc\pthreads\pthread_attr.c + + + + + pthread_barrier.c + 1 + ..\..\..\components\libc\pthreads\pthread_barrier.c + + + + + pthread_cond.c + 1 + ..\..\..\components\libc\pthreads\pthread_cond.c + + + + + pthread_mutex.c + 1 + ..\..\..\components\libc\pthreads\pthread_mutex.c + + + + + pthread_rwlock.c + 1 + ..\..\..\components\libc\pthreads\pthread_rwlock.c + + + + + pthread_spin.c + 1 + ..\..\..\components\libc\pthreads\pthread_spin.c + + + + + pthread_tls.c + 1 + ..\..\..\components\libc\pthreads\pthread_tls.c + + + + + sched.c + 1 + ..\..\..\components\libc\pthreads\sched.c + + + + + semaphore.c + 1 + ..\..\..\components\libc\pthreads\semaphore.c + + + + + clock_time.c + 1 + ..\..\..\components\libc\time\clock_time.c + + + + + posix_sleep.c + 1 + ..\..\..\components\libc\time\posix_sleep.c + + STM32_HAL @@ -997,6 +1082,76 @@ ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + + + stm32f4xx_hal_spi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c + + + + + stm32f4xx_hal_qspi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_qspi.c + + + + + stm32f4xx_ll_fmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c + + + + + stm32f4xx_ll_fsmc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c + + + + + stm32f4xx_hal_sdram.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sdram.c + + + + + stm32f4xx_hal_ltdc.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc.c + + + + + stm32f4xx_hal_ltdc_ex.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_ltdc_ex.c + + + + + stm32f4xx_hal_dma2d.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma2d.c + + + + + stm32f4xx_ll_dma2d.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_dma2d.c + + + + + stm32f4xx_hal_dsi.c + 1 + ..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dsi.c + + diff --git a/bsp/stm32/stm32f429-st-disco/template.ewp b/bsp/stm32/stm32f429-st-disco/template.ewp index 697f6d71f3..aa9a55e898 100644 --- a/bsp/stm32/stm32f429-st-disco/template.ewp +++ b/bsp/stm32/stm32f429-st-disco/template.ewp @@ -1,1819 +1,2032 @@ - - + - 2 - - Debug - - ARM - - 1 - - General - 3 - - 21 - 1 + 3 + + rt-thread + + ARM + 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 14 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 21 - 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 28 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 14 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + - - diff --git a/bsp/stm32/stm32f429-st-disco/template.eww b/bsp/stm32/stm32f429-st-disco/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/stm32/stm32f429-st-disco/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32f429-st-disco/template.uvprojx b/bsp/stm32/stm32f429-st-disco/template.uvprojx index 2c8869914b..afcb484788 100644 --- a/bsp/stm32/stm32f429-st-disco/template.uvprojx +++ b/bsp/stm32/stm32f429-st-disco/template.uvprojx @@ -16,8 +16,8 @@ STM32F429ZITx STMicroelectronics - Keil.STM32F4xx_DFP.2.14.0 - http://www.keil.com/pack/ + Keil.STM32F4xx_DFP.2.13.0 + http://www.keil.com/pack IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x200000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -54,7 +54,7 @@ 0 0 1 - 1 + 0 .\Listings\ 1 0 diff --git a/bsp/stm32/stm32f469-st-disco/project.ewp b/bsp/stm32/stm32f469-st-disco/project.ewp index 71a6331118..1a249d6915 100644 --- a/bsp/stm32/stm32f469-st-disco/project.ewp +++ b/bsp/stm32/stm32f469-st-disco/project.ewp @@ -215,10 +215,9 @@ + @@ -1720,7 +1771,7 @@ ILINK 0 - 20 + 23 1 0 + + + + + + @@ -2061,78 +2136,12 @@ - - Kernel - - $PROJ_DIR$\..\..\..\src\clock.c - - - $PROJ_DIR$\..\..\..\src\components.c - - - $PROJ_DIR$\..\..\..\src\device.c - - - $PROJ_DIR$\..\..\..\src\idle.c - - - $PROJ_DIR$\..\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\..\src\irq.c - - - $PROJ_DIR$\..\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\..\src\mem.c - - - $PROJ_DIR$\..\..\..\src\mempool.c - - - $PROJ_DIR$\..\..\..\src\object.c - - - $PROJ_DIR$\..\..\..\src\scheduler.c - - - $PROJ_DIR$\..\..\..\src\signal.c - - - $PROJ_DIR$\..\..\..\src\thread.c - - - $PROJ_DIR$\..\..\..\src\timer.c - - Applications $PROJ_DIR$\applications\main.c - - Drivers - - $PROJ_DIR$\board\board.c - - - $PROJ_DIR$\board\CubeMX_Config\Src\stm32l0xx_hal_msp.c - - - $PROJ_DIR$\..\libraries\STM32L0xx_HAL\CMSIS\Device\ST\STM32L0xx\Source\Templates\iar\startup_stm32l053xx.s - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c - - cpu @@ -2181,6 +2190,27 @@ $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\CubeMX_Config\Src\stm32l0xx_hal_msp.c + + + $PROJ_DIR$\..\libraries\STM32L0xx_HAL\CMSIS\Device\ST\STM32L0xx\Source\Templates\iar\startup_stm32l053xx.s + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c + + finsh @@ -2193,6 +2223,51 @@ $PROJ_DIR$\..\..\..\components\finsh\msh.c + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\signal.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + libc diff --git a/bsp/stm32/stm32l010-st-nucleo/template.ewp b/bsp/stm32/stm32l010-st-nucleo/template.ewp index f390ad7bc1..8f39159a1e 100644 --- a/bsp/stm32/stm32l010-st-nucleo/template.ewp +++ b/bsp/stm32/stm32l010-st-nucleo/template.ewp @@ -11,7 +11,7 @@ General 3 - 29 + 31 1 1 + + @@ -206,7 +215,7 @@ ICCARM 2 - 34 + 35 1 1 + @@ -674,7 +687,7 @@ ILINK 0 - 20 + 23 1 1 + + + + + + @@ -1025,7 +1062,7 @@ General 3 - 29 + 31 1 0 + + ICCARM 2 - 34 + 35 1 0 + @@ -1687,7 +1738,7 @@ ILINK 0 - 20 + 23 1 0 + + + + + + diff --git a/bsp/stm32/stm32l053-st-nucleo/project.ewd b/bsp/stm32/stm32l053-st-nucleo/project.ewd deleted file mode 100644 index 4b27053590..0000000000 --- a/bsp/stm32/stm32l053-st-nucleo/project.ewd +++ /dev/null @@ -1,2834 +0,0 @@ - - - 3 - - rt-thread - - ARM - - 1 - - C-SPY - 2 - - 29 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 1 - - - - - - - - CADI_ID - 2 - - 0 - 1 - 1 - - - - - - - - - CMSISDAP_ID - 2 - - 4 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - IJET_ID - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - JLINK_ID - 2 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - PEMICRO_ID - 2 - - 3 - 1 - 1 - - - - - - - - STLINK_ID - 2 - - 4 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - TIFET_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - - - XDS100_ID - 2 - - 6 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - 0 - - - - - Release - - ARM - - 0 - - C-SPY - 2 - - 29 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 0 - - - - - - - - CADI_ID - 2 - - 0 - 1 - 0 - - - - - - - - - CMSISDAP_ID - 2 - - 4 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - IJET_ID - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - JLINK_ID - 2 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 2 - 1 - 0 - - - - - - - - - - PEMICRO_ID - 2 - - 3 - 1 - 0 - - - - - - - - STLINK_ID - 2 - - 4 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 0 - - - - - - - - TIFET_ID - 2 - - 1 - 1 - 0 - - - - - - - - - - - - - - - - - - - XDS100_ID - 2 - - 6 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - 0 - - - - diff --git a/bsp/stm32/stm32l053-st-nucleo/project.ewp b/bsp/stm32/stm32l053-st-nucleo/project.ewp index b551e2de5f..1ab1f50306 100644 --- a/bsp/stm32/stm32l053-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l053-st-nucleo/project.ewp @@ -10,7 +10,7 @@ General 3 - 29 + 31 1 1 + + @@ -205,7 +214,7 @@ ICCARM 2 - 34 + 35 1 1 + @@ -690,7 +702,7 @@ ILINK 0 - 20 + 23 1 1 + + + + + + @@ -1041,7 +1077,7 @@ General 3 - 29 + 31 1 0 + + ICCARM 2 - 34 + 35 1 0 @@ -1381,7 +1427,6 @@ $PROJ_DIR$\..\libraries\HAL_Drivers\config $PROJ_DIR$\board $PROJ_DIR$\..\libraries\STM32L0xx_HAL\CMSIS\Include - $PROJ_DIR$\..\..\..\components\libc\compilers\common $PROJ_DIR$\board\CubeMX_Config\Inc $PROJ_DIR$\..\libraries\STM32L0xx_HAL\CMSIS\Device\ST\STM32L0xx\Include $PROJ_DIR$\..\..\..\include @@ -1500,6 +1545,10 @@ IccRTTI2 0 + @@ -1720,7 +1769,7 @@ ILINK 0 - 20 + 23 1 0 + + + + + + @@ -2061,81 +2134,12 @@ - - Kernel - - $PROJ_DIR$\..\..\..\src\clock.c - - - $PROJ_DIR$\..\..\..\src\components.c - - - $PROJ_DIR$\..\..\..\src\cpu.c - - - $PROJ_DIR$\..\..\..\src\device.c - - - $PROJ_DIR$\..\..\..\src\idle.c - - - $PROJ_DIR$\..\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\..\src\irq.c - - - $PROJ_DIR$\..\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\..\src\mem.c - - - $PROJ_DIR$\..\..\..\src\mempool.c - - - $PROJ_DIR$\..\..\..\src\object.c - - - $PROJ_DIR$\..\..\..\src\scheduler.c - - - $PROJ_DIR$\..\..\..\src\signal.c - - - $PROJ_DIR$\..\..\..\src\thread.c - - - $PROJ_DIR$\..\..\..\src\timer.c - - Applications $PROJ_DIR$\applications\main.c - - Drivers - - $PROJ_DIR$\board\board.c - - - $PROJ_DIR$\board\CubeMX_Config\Src\stm32l0xx_hal_msp.c - - - $PROJ_DIR$\..\libraries\STM32L0xx_HAL\CMSIS\Device\ST\STM32L0xx\Source\Templates\iar\startup_stm32l053xx.s - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c - - cpu @@ -2184,6 +2188,27 @@ $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\CubeMX_Config\Src\stm32l0xx_hal_msp.c + + + $PROJ_DIR$\..\libraries\STM32L0xx_HAL\CMSIS\Device\ST\STM32L0xx\Source\Templates\iar\startup_stm32l053xx.s + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c + + finsh @@ -2197,7 +2222,49 @@ - libc + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\signal.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + STM32_HAL diff --git a/bsp/stm32/stm32l053-st-nucleo/template.ewp b/bsp/stm32/stm32l053-st-nucleo/template.ewp index f390ad7bc1..8b8aed0348 100644 --- a/bsp/stm32/stm32l053-st-nucleo/template.ewp +++ b/bsp/stm32/stm32l053-st-nucleo/template.ewp @@ -11,7 +11,7 @@ General 3 - 29 + 31 1 1 + + @@ -206,7 +215,7 @@ ICCARM 2 - 34 + 35 1 1 + @@ -674,7 +687,7 @@ ILINK 0 - 20 + 23 1 1 + + + + + + @@ -1025,7 +1062,7 @@ General 3 - 29 + 31 1 0 + + ICCARM 2 - 34 + 35 1 0 + @@ -1687,7 +1738,7 @@ ILINK 0 - 20 + 23 1 0 + + + + + + diff --git a/bsp/stm32/stm32l412-st-nucleo/project.uvoptx b/bsp/stm32/stm32l412-st-nucleo/project.uvoptx index 54b8659855..7ce742a348 100644 --- a/bsp/stm32/stm32l412-st-nucleo/project.uvoptx +++ b/bsp/stm32/stm32l412-st-nucleo/project.uvoptx @@ -103,7 +103,7 @@ 1 0 0 - 6 + 0 @@ -114,18 +114,13 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\UL2CM3.DLL 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_128 -FL020000 -FS08000000 -FP0($$Device:STM32L412CBTx$CMSIS\Flash\STM32L4xx_128.FLM) - - - 0 - ST-LINKIII-KEIL_SWO - -U0672FF495649657867191218 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32L412CBTx$CMSIS\Flash\STM32L4xx_128.FLM) + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_128 -FL020000 -FS08000000 -FP0($$Device:STM32L412RBIx$CMSIS\Flash\STM32L4xx_128.FLM) @@ -182,895 +177,11 @@ - Kernel + Source Group 1 0 0 0 0 - - 1 - 1 - 1 - 0 - 0 - 0 - ..\..\..\src\clock.c - clock.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - ..\..\..\src\components.c - components.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - ..\..\..\src\device.c - device.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - ..\..\..\src\idle.c - idle.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - ..\..\..\src\mem.c - mem.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - ..\..\..\src\signal.c - signal.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c - 0 - 0 - - - - - Applications - 0 - 0 - 0 - 0 - - 2 - 15 - 1 - 0 - 0 - 0 - applications\main.c - main.c - 0 - 0 - - - - - Drivers - 0 - 0 - 0 - 0 - - 3 - 16 - 1 - 0 - 0 - 0 - board\board.c - board.c - 0 - 0 - - - 3 - 17 - 1 - 0 - 0 - 0 - board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - stm32l4xx_hal_msp.c - 0 - 0 - - - 3 - 18 - 2 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l412xx.s - startup_stm32l412xx.s - 0 - 0 - - - 3 - 19 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_gpio.c - drv_gpio.c - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_usart.c - drv_usart.c - 0 - 0 - - - 3 - 21 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_common.c - drv_common.c - 0 - 0 - - - - - cpu - 0 - 0 - 0 - 0 - - 4 - 22 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c - 0 - 0 - - - 4 - 23 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\div0.c - div0.c - 0 - 0 - - - 4 - 24 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\showmem.c - showmem.c - 0 - 0 - - - 4 - 25 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c - cpuport.c - 0 - 0 - - - 4 - 26 - 2 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - context_rvds.S - 0 - 0 - - - - - DeviceDrivers - 0 - 0 - 0 - 0 - - 5 - 27 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\misc\pin.c - pin.c - 0 - 0 - - - 5 - 28 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\rtc\rtc.c - rtc.c - 0 - 0 - - - 5 - 29 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\serial\serial.c - serial.c - 0 - 0 - - - 5 - 30 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\completion.c - completion.c - 0 - 0 - - - 5 - 31 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c - 0 - 0 - - - 5 - 32 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c - 0 - 0 - - - 5 - 33 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringblk_buf.c - ringblk_buf.c - 0 - 0 - - - 5 - 34 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringbuffer.c - ringbuffer.c - 0 - 0 - - - 5 - 35 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\waitqueue.c - waitqueue.c - 0 - 0 - - - 5 - 36 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c - 0 - 0 - - - 5 - 37 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\watchdog\watchdog.c - watchdog.c - 0 - 0 - - - - - finsh - 0 - 0 - 0 - 0 - - 6 - 38 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\shell.c - shell.c - 0 - 0 - - - 6 - 39 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\cmd.c - cmd.c - 0 - 0 - - - 6 - 40 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\msh.c - msh.c - 0 - 0 - - - - - libc - 0 - 0 - 0 - 0 - - 7 - 41 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\armlibc\libc.c - libc.c - 0 - 0 - - - 7 - 42 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\armlibc\mem_std.c - mem_std.c - 0 - 0 - - - 7 - 43 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\armlibc\stubs.c - stubs.c - 0 - 0 - - - 7 - 44 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\common\time.c - time.c - 0 - 0 - - - - - STM32_HAL - 0 - 0 - 0 - 0 - - 8 - 45 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c - system_stm32l4xx.c - 0 - 0 - - - 8 - 46 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c - stm32l4xx_hal.c - 0 - 0 - - - 8 - 47 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c - stm32l4xx_hal_comp.c - 0 - 0 - - - 8 - 48 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - stm32l4xx_hal_cortex.c - 0 - 0 - - - 8 - 49 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c - stm32l4xx_hal_crc.c - 0 - 0 - - - 8 - 50 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - stm32l4xx_hal_crc_ex.c - 0 - 0 - - - 8 - 51 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c - stm32l4xx_hal_cryp.c - 0 - 0 - - - 8 - 52 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c - stm32l4xx_hal_cryp_ex.c - 0 - 0 - - - 8 - 53 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - stm32l4xx_hal_dma.c - 0 - 0 - - - 8 - 54 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c - stm32l4xx_hal_dma_ex.c - 0 - 0 - - - 8 - 55 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c - stm32l4xx_hal_exti.c - 0 - 0 - - - 8 - 56 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - stm32l4xx_hal_pwr.c - 0 - 0 - - - 8 - 57 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - stm32l4xx_hal_pwr_ex.c - 0 - 0 - - - 8 - 58 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - stm32l4xx_hal_rcc.c - 0 - 0 - - - 8 - 59 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - stm32l4xx_hal_rcc_ex.c - 0 - 0 - - - 8 - 60 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - stm32l4xx_hal_rng.c - 0 - 0 - - - 8 - 61 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - stm32l4xx_hal_gpio.c - 0 - 0 - - - 8 - 62 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - stm32l4xx_hal_uart.c - 0 - 0 - - - 8 - 63 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - stm32l4xx_hal_uart_ex.c - 0 - 0 - - - 8 - 64 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c - stm32l4xx_hal_usart.c - 0 - 0 - - - 8 - 65 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c - stm32l4xx_hal_usart_ex.c - 0 - 0 - - - 8 - 66 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc.c - stm32l4xx_hal_rtc.c - 0 - 0 - - - 8 - 67 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c - stm32l4xx_hal_rtc_ex.c - 0 - 0 - - - 8 - 68 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c - stm32l4xx_hal_iwdg.c - 0 - 0 - - - 8 - 69 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_wwdg.c - stm32l4xx_hal_wwdg.c - 0 - 0 - diff --git a/bsp/stm32/stm32l412-st-nucleo/project.uvprojx b/bsp/stm32/stm32l412-st-nucleo/project.uvprojx index acb15e8337..1d632e7ce2 100644 --- a/bsp/stm32/stm32l412-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l412-st-nucleo/project.uvprojx @@ -1,46 +1,43 @@ - 2.1 -
### uVision Project, (C) Keil Software
- rt-thread 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060300::V5.06 update 3 (build 300)::ARMCC 0 - STM32L412CBTx + STM32L412RBIx STMicroelectronics - Keil.STM32L4xx_DFP.2.3.0 + Keil.STM32L4xx_DFP.2.5.0 https://www.keil.com/pack/ IRAM(0x20000000,0x00008000) IRAM2(0x10000000,0x00002000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_128 -FS08000000 -FL020000 -FP0($$Device:STM32L412CBTx$CMSIS\Flash\STM32L4xx_128.FLM)) + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_128 -FS08000000 -FL020000 -FP0($$Device:STM32L412RBIx$CMSIS\Flash\STM32L4xx_128.FLM)) 0 - $$Device:STM32L412CBTx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h - - - - - - - - - - $$Device:STM32L412CBTx$CMSIS\SVD\STM32L412.svd + $$Device:STM32L412RBIx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + + + + + + + + + + $$Device:STM32L412RBIx$CMSIS\SVD\STM32L412.svd 0 0 - - - - - + + + + + 0 0 @@ -52,9 +49,9 @@ rt-thread 1 0 - 1 + 0 1 - 1 + 0 .\build\keil\List\ 1 0 @@ -62,8 +59,8 @@ 0 0 - - + + 0 0 0 @@ -72,8 +69,8 @@ 0 0 - - + + 0 0 0 @@ -83,14 +80,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -104,8 +101,8 @@ 0 0 3 - - + + 1 @@ -138,11 +135,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -175,7 +172,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -308,7 +305,7 @@ 0x2000 - + 1 @@ -335,10 +332,10 @@ 0 0 - + USE_HAL_DRIVER, STM32L412xx, RT_USING_ARM_LIBC - - .;..\..\..\include;.;applications;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + + .;applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include @@ -353,10 +350,10 @@ 0 0 - - - - + + + + @@ -368,92 +365,17 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c - 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - irq.c - 1 - ..\..\..\src\irq.c - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - mem.c - 1 - ..\..\..\src\mem.c - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - object.c - 1 - ..\..\..\src\object.c - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - signal.c - 1 - ..\..\..\src\signal.c - - - thread.c - 1 - ..\..\..\src\thread.c - - - timer.c - 1 - ..\..\..\src\timer.c - - - Applications @@ -464,41 +386,6 @@ - - Drivers - - - board.c - 1 - board\board.c - - - stm32l4xx_hal_msp.c - 1 - board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - - - startup_stm32l412xx.s - 2 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l412xx.s - - - drv_gpio.c - 1 - ..\libraries\HAL_Drivers\drv_gpio.c - - - drv_usart.c - 1 - ..\libraries\HAL_Drivers\drv_usart.c - - - drv_common.c - 1 - ..\libraries\HAL_Drivers\drv_common.c - - - cpu @@ -507,21 +394,29 @@ 1 ..\..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\..\libcpu\arm\common\div0.c + + showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c + + cpuport.c 1 ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + context_rvds.S 2 @@ -537,51 +432,71 @@ 1 ..\..\..\components\drivers\misc\pin.c + + rtc.c 1 ..\..\..\components\drivers\rtc\rtc.c + + serial.c 1 ..\..\..\components\drivers\serial\serial.c + + completion.c 1 ..\..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\..\components\drivers\src\pipe.c + + ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 ..\..\..\components\drivers\src\workqueue.c + + watchdog.c 1 @@ -589,6 +504,51 @@ + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32l4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + + + + + startup_stm32l412xx.s + 2 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l412xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + finsh @@ -597,11 +557,15 @@ 1 ..\..\..\components\finsh\shell.c + + cmd.c 1 ..\..\..\components\finsh\cmd.c + + msh.c 1 @@ -609,6 +573,107 @@ + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + libc @@ -617,16 +682,22 @@ 1 ..\..\..\components\libc\compilers\armlibc\libc.c + + mem_std.c 1 ..\..\..\components\libc\compilers\armlibc\mem_std.c + + stubs.c 1 ..\..\..\components\libc\compilers\armlibc\stubs.c + + time.c 1 @@ -642,121 +713,169 @@ 1 ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c + + stm32l4xx_hal.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + stm32l4xx_hal_comp.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + + stm32l4xx_hal_cortex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + + stm32l4xx_hal_crc.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c + + stm32l4xx_hal_crc_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c + + stm32l4xx_hal_cryp.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c + + stm32l4xx_hal_cryp_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c + + stm32l4xx_hal_dma.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + stm32l4xx_hal_dma_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + stm32l4xx_hal_exti.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + + stm32l4xx_hal_pwr.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + stm32l4xx_hal_pwr_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + stm32l4xx_hal_rcc.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + + stm32l4xx_hal_rcc_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + stm32l4xx_hal_rng.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c + + stm32l4xx_hal_gpio.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + stm32l4xx_hal_uart.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + + stm32l4xx_hal_uart_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + + stm32l4xx_hal_usart.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c + + stm32l4xx_hal_usart_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c + + stm32l4xx_hal_rtc.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc.c + + stm32l4xx_hal_rtc_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c + + stm32l4xx_hal_iwdg.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c + + stm32l4xx_hal_wwdg.c 1 @@ -767,11 +886,9 @@ - - - - + + + - diff --git a/bsp/stm32/stm32l412-st-nucleo/template.uvoptx b/bsp/stm32/stm32l412-st-nucleo/template.uvoptx index d18ee55260..7ce742a348 100644 --- a/bsp/stm32/stm32l412-st-nucleo/template.uvoptx +++ b/bsp/stm32/stm32l412-st-nucleo/template.uvoptx @@ -100,7 +100,10 @@ 1 0 0 - 5 + 1 + 0 + 0 + 0 @@ -111,23 +114,13 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\UL2CM3.DLL - - 0 - ST-LINKIII-KEIL_SWO - -U066AFF534854845187093307 -O206 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32L432KCUx$CMSIS\Flash\STM32L4xx_256.FLM) - 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_256 -FL040000 -FS08000000 -FP0($$Device:STM32L432KCUx$CMSIS\Flash\STM32L4xx_256.FLM) - - - 0 - JL2CM3 - -U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_128 -FL020000 -FS08000000 -FP0($$Device:STM32L412RBIx$CMSIS\Flash\STM32L4xx_128.FLM) @@ -163,11 +156,19 @@ 0 - - - 0 + 0 + 0 + + + + + + + + 1 + 0 0 2 10000000 diff --git a/bsp/stm32/stm32l412-st-nucleo/template.uvprojx b/bsp/stm32/stm32l412-st-nucleo/template.uvprojx index 01e792faf7..fa4b7bae15 100644 --- a/bsp/stm32/stm32l412-st-nucleo/template.uvprojx +++ b/bsp/stm32/stm32l412-st-nucleo/template.uvprojx @@ -11,18 +11,19 @@ 0x4 ARM-ADS 5060300::V5.06 update 3 (build 300)::ARMCC + 0 - STM32L432KCUx + STM32L412RBIx STMicroelectronics - Keil.STM32L4xx_DFP.2.0.0 - http://www.keil.com/pack - IRAM(0x20000000,0x0000C000) IRAM2(0x10000000,0x00004000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x00008000) IRAM2(0x10000000,0x00002000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32L432KCUx$CMSIS\Flash\STM32L4xx_256.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_128 -FS08000000 -FL020000 -FP0($$Device:STM32L412RBIx$CMSIS\Flash\STM32L4xx_128.FLM)) 0 - $$Device:STM32L432KCUx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + $$Device:STM32L412RBIx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h @@ -32,7 +33,7 @@ - $$Device:STM32L432KCUx$CMSIS\SVD\STM32L4x2.svd + $$Device:STM32L412RBIx$CMSIS\SVD\STM32L412.svd 0 0 @@ -51,9 +52,9 @@ rt-thread 1 0 - 1 + 0 1 - 1 + 0 .\build\keil\List\ 1 0 @@ -137,7 +138,7 @@ 1 BIN\UL2CM3.DLL - "" () + @@ -183,6 +184,7 @@ 0 0 2 + 0 1 0 8 @@ -191,7 +193,7 @@ 0 0 3 - 3 + 4 0 0 0 @@ -243,12 +245,12 @@ 0 0x20000000 - 0xc000 + 0x8000 1 0x8000000 - 0x40000 + 0x20000 0 @@ -273,7 +275,7 @@ 1 0x8000000 - 0x40000 + 0x20000 1 @@ -298,12 +300,12 @@ 0 0x20000000 - 0x10000 + 0x8000 0 - 0x0 - 0x0 + 0x10000000 + 0x2000 @@ -323,6 +325,7 @@ 0 0 1 + 0 0 1 1 @@ -383,4 +386,10 @@ + + + + + + diff --git a/bsp/stm32/stm32l432-st-nucleo/project.uvoptx b/bsp/stm32/stm32l432-st-nucleo/project.uvoptx index d18ee55260..f1edd5910d 100644 --- a/bsp/stm32/stm32l432-st-nucleo/project.uvoptx +++ b/bsp/stm32/stm32l432-st-nucleo/project.uvoptx @@ -73,7 +73,7 @@ 0 - 0 + 1 0 1 @@ -100,7 +100,10 @@ 1 0 0 - 5 + 1 + 0 + 0 + 6 @@ -163,11 +166,19 @@ 0 - - - 0 + 0 + 0 + + + + + + + + 1 + 0 0 2 10000000 diff --git a/bsp/stm32/stm32l432-st-nucleo/project.uvprojx b/bsp/stm32/stm32l432-st-nucleo/project.uvprojx index 85d9948d49..a48bfd2ab6 100644 --- a/bsp/stm32/stm32l432-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l432-st-nucleo/project.uvprojx @@ -7,13 +7,14 @@ rt-thread 0x4 ARM-ADS - 5060300::V5.06 update 3 (build 300)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 STM32L432KCUx STMicroelectronics - Keil.STM32L4xx_DFP.2.0.0 - http://www.keil.com/pack + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ IRAM(0x20000000,0x0000C000) IRAM2(0x10000000,0x00004000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -48,9 +49,9 @@ rt-thread 1 0 - 1 + 0 1 - 1 + 0 .\build\keil\List\ 1 0 @@ -180,6 +181,7 @@ 0 0 2 + 0 1 0 8 @@ -299,8 +301,8 @@ 0 - 0x0 - 0x0 + 0x10000000 + 0x4000 @@ -320,6 +322,7 @@ 0 0 1 + 0 0 1 1 @@ -332,7 +335,7 @@ USE_HAL_DRIVER, STM32L432xx, RT_USING_ARM_LIBC - .;..\..\..\include;.;applications;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + .;applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include @@ -373,114 +376,6 @@ - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - - - components.c - 1 - ..\..\..\src\components.c - - - - - cpu.c - 1 - ..\..\..\src\cpu.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - - - idle.c - 1 - ..\..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - - - object.c - 1 - ..\..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - - - signal.c - 1 - ..\..\..\src\signal.c - - - - - thread.c - 1 - ..\..\..\src\thread.c - - - - - timer.c - 1 - ..\..\..\src\timer.c - - - Applications @@ -491,51 +386,6 @@ - - Drivers - - - board.c - 1 - board\board.c - - - - - stm32l4xx_hal_msp.c - 1 - board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - - - - - startup_stm32l432xx.s - 2 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l432xx.s - - - - - drv_gpio.c - 1 - ..\libraries\HAL_Drivers\drv_gpio.c - - - - - drv_usart.c - 1 - ..\libraries\HAL_Drivers\drv_usart.c - - - - - drv_common.c - 1 - ..\libraries\HAL_Drivers\drv_common.c - - - cpu @@ -654,6 +504,51 @@ + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32l4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + + + + + startup_stm32l432xx.s + 2 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l432xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + finsh @@ -678,6 +573,107 @@ + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + libc @@ -890,4 +886,9 @@ + + + + + diff --git a/bsp/stm32/stm32l432-st-nucleo/template.uvoptx b/bsp/stm32/stm32l432-st-nucleo/template.uvoptx index d18ee55260..f1edd5910d 100644 --- a/bsp/stm32/stm32l432-st-nucleo/template.uvoptx +++ b/bsp/stm32/stm32l432-st-nucleo/template.uvoptx @@ -73,7 +73,7 @@ 0 - 0 + 1 0 1 @@ -100,7 +100,10 @@ 1 0 0 - 5 + 1 + 0 + 0 + 6 @@ -163,11 +166,19 @@ 0 - - - 0 + 0 + 0 + + + + + + + + 1 + 0 0 2 10000000 diff --git a/bsp/stm32/stm32l432-st-nucleo/template.uvprojx b/bsp/stm32/stm32l432-st-nucleo/template.uvprojx index 01e792faf7..71768c87f6 100644 --- a/bsp/stm32/stm32l432-st-nucleo/template.uvprojx +++ b/bsp/stm32/stm32l432-st-nucleo/template.uvprojx @@ -10,13 +10,14 @@ rt-thread 0x4 ARM-ADS - 5060300::V5.06 update 3 (build 300)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 STM32L432KCUx STMicroelectronics - Keil.STM32L4xx_DFP.2.0.0 - http://www.keil.com/pack + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ IRAM(0x20000000,0x0000C000) IRAM2(0x10000000,0x00004000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -51,9 +52,9 @@ rt-thread 1 0 - 1 + 0 1 - 1 + 0 .\build\keil\List\ 1 0 @@ -183,6 +184,7 @@ 0 0 2 + 0 1 0 8 @@ -302,8 +304,8 @@ 0 - 0x0 - 0x0 + 0x10000000 + 0x4000 @@ -323,6 +325,7 @@ 0 0 1 + 0 0 1 1 @@ -383,4 +386,10 @@ + + + + + + diff --git a/bsp/stm32/stm32l433-st-nucleo/project.uvoptx b/bsp/stm32/stm32l433-st-nucleo/project.uvoptx index fe048932d8..6122affd8f 100644 --- a/bsp/stm32/stm32l433-st-nucleo/project.uvoptx +++ b/bsp/stm32/stm32l433-st-nucleo/project.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -182,823 +182,11 @@ - Kernel + Source Group 1 0 0 0 0 - - 1 - 1 - 1 - 0 - 0 - 0 - ..\..\..\src\clock.c - clock.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - ..\..\..\src\components.c - components.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - ..\..\..\src\device.c - device.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - ..\..\..\src\idle.c - idle.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - ..\..\..\src\mem.c - mem.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - ..\..\..\src\signal.c - signal.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c - 0 - 0 - - - - - Applications - 1 - 0 - 0 - 0 - - 2 - 15 - 1 - 0 - 0 - 0 - applications\main.c - main.c - 0 - 0 - - - - - Drivers - 1 - 0 - 0 - 0 - - 3 - 16 - 1 - 0 - 0 - 0 - board\board.c - board.c - 0 - 0 - - - 3 - 17 - 1 - 0 - 0 - 0 - board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - stm32l4xx_hal_msp.c - 0 - 0 - - - 3 - 18 - 2 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l433xx.s - startup_stm32l433xx.s - 0 - 0 - - - 3 - 19 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_gpio.c - drv_gpio.c - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_usart.c - drv_usart.c - 0 - 0 - - - 3 - 21 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_common.c - drv_common.c - 0 - 0 - - - - - cpu - 0 - 0 - 0 - 0 - - 4 - 22 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c - 0 - 0 - - - 4 - 23 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\div0.c - div0.c - 0 - 0 - - - 4 - 24 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\showmem.c - showmem.c - 0 - 0 - - - 4 - 25 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c - cpuport.c - 0 - 0 - - - 4 - 26 - 2 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - context_rvds.S - 0 - 0 - - - - - DeviceDrivers - 0 - 0 - 0 - 0 - - 5 - 27 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\misc\pin.c - pin.c - 0 - 0 - - - 5 - 28 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\serial\serial.c - serial.c - 0 - 0 - - - 5 - 29 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\completion.c - completion.c - 0 - 0 - - - 5 - 30 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c - 0 - 0 - - - 5 - 31 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c - 0 - 0 - - - 5 - 32 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringblk_buf.c - ringblk_buf.c - 0 - 0 - - - 5 - 33 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringbuffer.c - ringbuffer.c - 0 - 0 - - - 5 - 34 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\waitqueue.c - waitqueue.c - 0 - 0 - - - 5 - 35 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c - 0 - 0 - - - - - finsh - 0 - 0 - 0 - 0 - - 6 - 36 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\shell.c - shell.c - 0 - 0 - - - 6 - 37 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\cmd.c - cmd.c - 0 - 0 - - - 6 - 38 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\msh.c - msh.c - 0 - 0 - - - - - libc - 0 - 0 - 0 - 0 - - 7 - 39 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\armlibc\libc.c - libc.c - 0 - 0 - - - 7 - 40 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\armlibc\mem_std.c - mem_std.c - 0 - 0 - - - 7 - 41 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\armlibc\stubs.c - stubs.c - 0 - 0 - - - 7 - 42 - 1 - 0 - 0 - 0 - ..\..\..\components\libc\compilers\common\time.c - time.c - 0 - 0 - - - - - STM32_HAL - 0 - 0 - 0 - 0 - - 8 - 43 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c - system_stm32l4xx.c - 0 - 0 - - - 8 - 44 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c - stm32l4xx_hal.c - 0 - 0 - - - 8 - 45 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c - stm32l4xx_hal_comp.c - 0 - 0 - - - 8 - 46 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - stm32l4xx_hal_cortex.c - 0 - 0 - - - 8 - 47 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c - stm32l4xx_hal_crc.c - 0 - 0 - - - 8 - 48 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - stm32l4xx_hal_crc_ex.c - 0 - 0 - - - 8 - 49 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c - stm32l4xx_hal_cryp.c - 0 - 0 - - - 8 - 50 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c - stm32l4xx_hal_cryp_ex.c - 0 - 0 - - - 8 - 51 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - stm32l4xx_hal_dma.c - 0 - 0 - - - 8 - 52 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c - stm32l4xx_hal_dma_ex.c - 0 - 0 - - - 8 - 53 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c - stm32l4xx_hal_exti.c - 0 - 0 - - - 8 - 54 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - stm32l4xx_hal_pwr.c - 0 - 0 - - - 8 - 55 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - stm32l4xx_hal_pwr_ex.c - 0 - 0 - - - 8 - 56 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - stm32l4xx_hal_rcc.c - 0 - 0 - - - 8 - 57 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - stm32l4xx_hal_rcc_ex.c - 0 - 0 - - - 8 - 58 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - stm32l4xx_hal_rng.c - 0 - 0 - - - 8 - 59 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - stm32l4xx_hal_gpio.c - 0 - 0 - - - 8 - 60 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - stm32l4xx_hal_uart.c - 0 - 0 - - - 8 - 61 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - stm32l4xx_hal_uart_ex.c - 0 - 0 - - - 8 - 62 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c - stm32l4xx_hal_usart.c - 0 - 0 - - - 8 - 63 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c - stm32l4xx_hal_usart_ex.c - 0 - 0 - diff --git a/bsp/stm32/stm32l433-st-nucleo/project.uvprojx b/bsp/stm32/stm32l433-st-nucleo/project.uvprojx index 7a7fdfe915..dc49c9882e 100644 --- a/bsp/stm32/stm32l433-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l433-st-nucleo/project.uvprojx @@ -1,46 +1,43 @@ - 2.1 -
### uVision Project, (C) Keil Software
- rt-thread 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC + 5060300::V5.06 update 3 (build 300)::ARMCC 0 STM32L433RCTx STMicroelectronics - Keil.STM32L4xx_DFP.2.3.0 + Keil.STM32L4xx_DFP.2.5.0 https://www.keil.com/pack/ IRAM(0x20000000,0x0000C000) IRAM2(0x10000000,0x00004000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32L433RCTx$CMSIS\Flash\STM32L4xx_256.FLM)) 0 $$Device:STM32L433RCTx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h - - - - - - - - - + + + + + + + + + $$Device:STM32L433RCTx$CMSIS\SVD\STM32L4x3.svd 0 0 - - - - - + + + + + 0 0 @@ -52,9 +49,9 @@ rt-thread 1 0 - 1 + 0 1 - 1 + 0 .\build\keil\List\ 1 0 @@ -62,8 +59,8 @@ 0 0 - - + + 0 0 0 @@ -72,8 +69,8 @@ 0 0 - - + + 0 0 0 @@ -83,14 +80,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -104,8 +101,8 @@ 0 0 3 - - + + 1 @@ -138,11 +135,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -175,7 +172,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -308,7 +305,7 @@ 0x4000 - + 1 @@ -335,10 +332,10 @@ 0 0 - + USE_HAL_DRIVER, STM32L433xx, RT_USING_ARM_LIBC - - .;..\..\..\include;.;applications;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + + .;applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include @@ -353,10 +350,10 @@ 0 0 - - - - + + + + @@ -368,92 +365,17 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c - 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - irq.c - 1 - ..\..\..\src\irq.c - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - mem.c - 1 - ..\..\..\src\mem.c - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - object.c - 1 - ..\..\..\src\object.c - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - signal.c - 1 - ..\..\..\src\signal.c - - - thread.c - 1 - ..\..\..\src\thread.c - - - timer.c - 1 - ..\..\..\src\timer.c - - - Applications @@ -464,41 +386,6 @@ - - Drivers - - - board.c - 1 - board\board.c - - - stm32l4xx_hal_msp.c - 1 - board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - - - startup_stm32l433xx.s - 2 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l433xx.s - - - drv_gpio.c - 1 - ..\libraries\HAL_Drivers\drv_gpio.c - - - drv_usart.c - 1 - ..\libraries\HAL_Drivers\drv_usart.c - - - drv_common.c - 1 - ..\libraries\HAL_Drivers\drv_common.c - - - cpu @@ -507,21 +394,29 @@ 1 ..\..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\..\libcpu\arm\common\div0.c + + showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c + + cpuport.c 1 ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + context_rvds.S 2 @@ -537,41 +432,57 @@ 1 ..\..\..\components\drivers\misc\pin.c + + serial.c 1 ..\..\..\components\drivers\serial\serial.c + + completion.c 1 ..\..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\..\components\drivers\src\pipe.c + + ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 @@ -579,6 +490,51 @@ + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32l4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + + + + + startup_stm32l433xx.s + 2 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l433xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + finsh @@ -587,11 +543,15 @@ 1 ..\..\..\components\finsh\shell.c + + cmd.c 1 ..\..\..\components\finsh\cmd.c + + msh.c 1 @@ -599,6 +559,107 @@ + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + libc @@ -607,16 +668,22 @@ 1 ..\..\..\components\libc\compilers\armlibc\libc.c + + mem_std.c 1 ..\..\..\components\libc\compilers\armlibc\mem_std.c + + stubs.c 1 ..\..\..\components\libc\compilers\armlibc\stubs.c + + time.c 1 @@ -632,101 +699,141 @@ 1 ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c + + stm32l4xx_hal.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + stm32l4xx_hal_comp.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + + stm32l4xx_hal_cortex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + + stm32l4xx_hal_crc.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c + + stm32l4xx_hal_crc_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c + + stm32l4xx_hal_cryp.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c + + stm32l4xx_hal_cryp_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c + + stm32l4xx_hal_dma.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + stm32l4xx_hal_dma_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + stm32l4xx_hal_exti.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + + stm32l4xx_hal_pwr.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + stm32l4xx_hal_pwr_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + stm32l4xx_hal_rcc.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + + stm32l4xx_hal_rcc_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + stm32l4xx_hal_rng.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c + + stm32l4xx_hal_gpio.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + stm32l4xx_hal_uart.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + + stm32l4xx_hal_uart_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + + stm32l4xx_hal_usart.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c + + stm32l4xx_hal_usart_ex.c 1 @@ -737,11 +844,9 @@ - - - - + + + - diff --git a/bsp/stm32/stm32l433-st-nucleo/template.uvprojx b/bsp/stm32/stm32l433-st-nucleo/template.uvprojx index f4e671bde3..55247ceb63 100644 --- a/bsp/stm32/stm32l433-st-nucleo/template.uvprojx +++ b/bsp/stm32/stm32l433-st-nucleo/template.uvprojx @@ -16,7 +16,7 @@ STM32L433RCTx STMicroelectronics - Keil.STM32L4xx_DFP.2.3.0 + Keil.STM32L4xx_DFP.2.5.0 https://www.keil.com/pack/ IRAM(0x20000000,0x0000C000) IRAM2(0x10000000,0x00004000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE @@ -52,9 +52,9 @@ rt-thread 1 0 - 1 + 0 1 - 1 + 0 .\build\keil\List\ 1 0 diff --git a/bsp/stm32/stm32l475-st-discovery/project.uvprojx b/bsp/stm32/stm32l475-st-discovery/project.uvprojx index d086ed139e..71798fd0e5 100644 --- a/bsp/stm32/stm32l475-st-discovery/project.uvprojx +++ b/bsp/stm32/stm32l475-st-discovery/project.uvprojx @@ -13,8 +13,8 @@ STM32L475VGTx STMicroelectronics - Keil.STM32L4xx_DFP.2.2.0 - http://www.keil.com/pack + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ IRAM(0x20000000,0x00018000) IRAM2(0x10000000,0x00008000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -51,7 +51,7 @@ 0 0 1 - 1 + 0 .\build\keil\List\ 1 0 @@ -335,7 +335,7 @@ USE_HAL_DRIVER, STM32L475xx - .;..\..\..\include;applications;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include @@ -376,114 +376,6 @@ - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - - - components.c - 1 - ..\..\..\src\components.c - - - - - cpu.c - 1 - ..\..\..\src\cpu.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - - - idle.c - 1 - ..\..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - - - object.c - 1 - ..\..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - - - signal.c - 1 - ..\..\..\src\signal.c - - - - - thread.c - 1 - ..\..\..\src\thread.c - - - - - timer.c - 1 - ..\..\..\src\timer.c - - - Applications @@ -494,51 +386,6 @@ - - Drivers - - - board.c - 1 - board\board.c - - - - - stm32l4xx_hal_msp.c - 1 - board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - - - - - startup_stm32l475xx.s - 2 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l475xx.s - - - - - drv_gpio.c - 1 - ..\libraries\HAL_Drivers\drv_gpio.c - - - - - drv_usart.c - 1 - ..\libraries\HAL_Drivers\drv_usart.c - - - - - drv_common.c - 1 - ..\libraries\HAL_Drivers\drv_common.c - - - cpu @@ -643,6 +490,51 @@ + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32l4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + + + + + startup_stm32l475xx.s + 2 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l475xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + finsh @@ -667,6 +559,107 @@ + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + STM32_HAL diff --git a/bsp/stm32/stm32l475-st-discovery/template.uvprojx b/bsp/stm32/stm32l475-st-discovery/template.uvprojx index 9ceefbf708..2090e98f77 100644 --- a/bsp/stm32/stm32l475-st-discovery/template.uvprojx +++ b/bsp/stm32/stm32l475-st-discovery/template.uvprojx @@ -16,8 +16,8 @@ STM32L475VGTx STMicroelectronics - Keil.STM32L4xx_DFP.2.2.0 - http://www.keil.com/pack + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ IRAM(0x20000000,0x00018000) IRAM2(0x10000000,0x00008000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE @@ -54,7 +54,7 @@ 0 0 1 - 1 + 0 .\build\keil\List\ 1 0 diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/.mxproject index d3df7c29f8..0be25bee00 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/.mxproject @@ -1,14 +1,14 @@ [PreviousGenFiles] -HeaderPath=E:/Work/GitLib/rt-thread/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc +HeaderPath=/home/rudy/workspace_hd/Projects/rt-thread/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h;gpio.h;adc.h;iwdg.h;lptim.h;usart.h;rtc.h;spi.h;tim.h;usb_otg.h; -SourcePath=E:/Work/GitLib/rt-thread/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src +SourcePath=/home/rudy/workspace_hd/Projects/rt-thread/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c;gpio.c;adc.c;iwdg.c;lptim.c;usart.c;rtc.c;spi.c;tim.c;usb_otg.c; [PreviousLibFiles] -LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; +LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/mpu_armv8.h; [PreviousUsedIarFiles] -SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;../\Src/system_stm32l4xx.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;../\Src/system_stm32l4xx.c;../Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;null; -HeaderPath=..\Drivers\STM32L4xx_HAL_Driver\Inc;..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32L4xx\Include;..\Drivers\CMSIS\Include;..\Inc; -CDefines=USE_HAL_DRIVER;STM32L4R5xx;USE_HAL_DRIVER;STM32L4R5xx; +SourceFiles=../Src/main.c;../Src/stm32l4xx_it.c;../Src/stm32l4xx_hal_msp.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..//Src/system_stm32l4xx.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..//Src/system_stm32l4xx.c;../Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;; +HeaderPath=../Drivers/STM32L4xx_HAL_Driver/Inc;../Drivers/STM32L4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32L4xx/Include;../Drivers/CMSIS/Include;../Inc; +CDefines=USE_HAL_DRIVER;STM32L4R5xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h index ad2b2456c6..03ebfd6ed9 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h @@ -5,7 +5,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2020 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/STM32L4R5ZITx.ioc b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/STM32L4R5ZITx.ioc index d09331ae4c..8e60a86eb0 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/STM32L4R5ZITx.ioc +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/STM32L4R5ZITx.ioc @@ -6,15 +6,18 @@ Mcu.IP0=LPUART1 Mcu.IP1=NVIC Mcu.IP2=RCC Mcu.IP3=SYS -Mcu.IPNb=4 +Mcu.IP4=USART3 +Mcu.IPNb=5 Mcu.Name=STM32L4R5Z(G-I)Tx Mcu.Package=LQFP144 Mcu.Pin0=PC14-OSC32_IN (PC14) Mcu.Pin1=PC15-OSC32_OUT (PC15) -Mcu.Pin2=PG7 -Mcu.Pin3=PG8 -Mcu.Pin4=VP_SYS_VS_Systick -Mcu.PinsNb=5 +Mcu.Pin2=PD8 +Mcu.Pin3=PD9 +Mcu.Pin4=PG7 +Mcu.Pin5=PG8 +Mcu.Pin6=VP_SYS_VS_Systick +Mcu.PinsNb=7 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32L4R5ZITx @@ -22,6 +25,7 @@ MxCube.Version=5.3.0 MxDb.Version=DB.5.0.30 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false @@ -42,6 +46,12 @@ PCC.Seq0=0 PCC.Series=STM32L4 PCC.Temperature=25 PCC.Vdd=3.0 +PD8.Locked=true +PD8.Mode=Asynchronous +PD8.Signal=USART3_TX +PD9.Locked=true +PD9.Mode=Asynchronous +PD9.Signal=USART3_RX PG7.GPIOParameters=GPIO_Speed,GPIO_PuPd PG7.GPIO_PuPd=GPIO_PULLUP PG7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH @@ -159,6 +169,9 @@ RCC.VCOInputFreq_Value=8000000 RCC.VCOOutputFreq_Value=200000000 RCC.VCOSAI1OutputFreq_Value=96000000 RCC.VCOSAI2OutputFreq_Value=64000000 +USART3.BaudRate=9600 +USART3.IPParameters=VirtualMode-Asynchronous,BaudRate +USART3.VirtualMode-Asynchronous=VM_ASYNC VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick board=custom diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/main.c index 62ca06d018..eb41654222 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/main.c @@ -43,6 +43,7 @@ /* Private variables ---------------------------------------------------------*/ UART_HandleTypeDef hlpuart1; +UART_HandleTypeDef huart3; /* USER CODE BEGIN PV */ @@ -52,6 +53,7 @@ UART_HandleTypeDef hlpuart1; void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_LPUART1_UART_Init(void); +static void MX_USART3_UART_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -91,6 +93,7 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_LPUART1_UART_Init(); + MX_USART3_UART_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -151,7 +154,8 @@ void SystemClock_Config(void) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_LPUART1; + PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_HSI; PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { @@ -203,6 +207,54 @@ static void MX_LPUART1_UART_Init(void) } +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 9600; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + /** * @brief GPIO Initialization Function * @param None @@ -213,6 +265,7 @@ static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); HAL_PWREx_EnableVddIO2(); diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c index cd642f7a7f..7446f38eb7 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c @@ -111,6 +111,30 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspInit 1 */ } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } } @@ -140,6 +164,24 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USER CODE END LPUART1_MspDeInit 1 */ } + else if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } } diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig b/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig index bc51589157..90fb8181a4 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig @@ -215,7 +215,7 @@ menu "Hardware Drivers Config" select RT_USING_PWM if BSP_USING_PWM config BSP_USING_PWM1 - bool "Using PWM1 + bool "Using PWM1" default n if BSP_USING_PWM1 config BSP_USING_PWM1_CH1 diff --git a/bsp/stm32/stm32l4r5-st-nucleo/project.ewd b/bsp/stm32/stm32l4r5-st-nucleo/project.ewd deleted file mode 100644 index b5ac2594b8..0000000000 --- a/bsp/stm32/stm32l4r5-st-nucleo/project.ewd +++ /dev/null @@ -1,2974 +0,0 @@ - - - 3 - - rt-thread - - ARM - - 1 - - C-SPY - 2 - - 32 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 1 - - - - - - - - CADI_ID - 2 - - 0 - 1 - 1 - - - - - - - - - CMSISDAP_ID - 2 - - 4 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 1 - - - - - - - - - - - IJET_ID - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - JLINK_ID - 2 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 2 - 1 - 1 - - - - - - - - - - NULINK_ID - 2 - - 0 - 1 - 1 - - - - - - - PEMICRO_ID - 2 - - 3 - 1 - 1 - - - - - - - - STLINK_ID - 2 - - 6 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 1 - - - - - - - - TIFET_ID - 2 - - 1 - 1 - 1 - - - - - - - - - - - - - - - - - - - XDS100_ID - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - 0 - - - - - Release - - ARM - - 0 - - C-SPY - 2 - - 32 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 0 - - - - - - - - CADI_ID - 2 - - 0 - 1 - 0 - - - - - - - - - CMSISDAP_ID - 2 - - 4 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - GDBSERVER_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - IJET_ID - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - JLINK_ID - 2 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 2 - 1 - 0 - - - - - - - - - - NULINK_ID - 2 - - 0 - 1 - 0 - - - - - - - PEMICRO_ID - 2 - - 3 - 1 - 0 - - - - - - - - STLINK_ID - 2 - - 6 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 0 - - - - - - - - TIFET_ID - 2 - - 1 - 1 - 0 - - - - - - - - - - - - - - - - - - - XDS100_ID - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin - 0 - - - - diff --git a/bsp/stm32/stm32l4r5-st-nucleo/project.ewp b/bsp/stm32/stm32l4r5-st-nucleo/project.ewp index dc0a210499..0343c802b1 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/project.ewp +++ b/bsp/stm32/stm32l4r5-st-nucleo/project.ewp @@ -362,7 +362,6 @@ $PROJ_DIR$\applications $PROJ_DIR$\..\libraries\HAL_Drivers\config $PROJ_DIR$\board - $PROJ_DIR$\..\..\..\components\libc\compilers\common $PROJ_DIR$\board\CubeMX_Config\Inc $PROJ_DIR$\..\..\..\include $PROJ_DIR$\..\libraries\HAL_Drivers @@ -1430,7 +1429,6 @@ $PROJ_DIR$\applications $PROJ_DIR$\..\libraries\HAL_Drivers\config $PROJ_DIR$\board - $PROJ_DIR$\..\..\..\components\libc\compilers\common $PROJ_DIR$\board\CubeMX_Config\Inc $PROJ_DIR$\..\..\..\include $PROJ_DIR$\..\libraries\HAL_Drivers @@ -2136,78 +2134,12 @@ - - Kernel - - $PROJ_DIR$\..\..\..\src\clock.c - - - $PROJ_DIR$\..\..\..\src\components.c - - - $PROJ_DIR$\..\..\..\src\device.c - - - $PROJ_DIR$\..\..\..\src\idle.c - - - $PROJ_DIR$\..\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\..\src\irq.c - - - $PROJ_DIR$\..\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\..\src\mem.c - - - $PROJ_DIR$\..\..\..\src\memheap.c - - - $PROJ_DIR$\..\..\..\src\object.c - - - $PROJ_DIR$\..\..\..\src\scheduler.c - - - $PROJ_DIR$\..\..\..\src\signal.c - - - $PROJ_DIR$\..\..\..\src\thread.c - - - $PROJ_DIR$\..\..\..\src\timer.c - - Applications $PROJ_DIR$\applications\main.c - - Drivers - - $PROJ_DIR$\board\board.c - - - $PROJ_DIR$\board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\iar\startup_stm32l4r5xx.s - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c - - cpu @@ -2256,6 +2188,27 @@ $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + + + $PROJ_DIR$\..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\iar\startup_stm32l4r5xx.s + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c + + + $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c + + finsh @@ -2269,7 +2222,49 @@ - libc + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\device.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\..\src\signal.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + STM32_HAL diff --git a/bsp/stm32/stm32l4r5-st-nucleo/project.ewt b/bsp/stm32/stm32l4r5-st-nucleo/project.ewt deleted file mode 100644 index b04fd11b3e..0000000000 --- a/bsp/stm32/stm32l4r5-st-nucleo/project.ewt +++ /dev/null @@ -1,2629 +0,0 @@ - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - Release - - ARM - - 0 - - C-STAT - 262 - - 262 - - 0 - - 1 - 600 - 1 - 2 - 0 - 1 - 100 - - - 1.6.2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - Applications - - $PROJ_DIR$\applications\main.c - - - - cpu - - $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c - - - - DeviceDrivers - - $PROJ_DIR$\..\..\..\components\drivers\src\completion.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c - - - $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c - - - - dlib - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\libc.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\rmtx.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\stdio.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\time.c - - - - Drivers - - $PROJ_DIR$\board\board.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c - - - $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\iar\startup_stm32l4r5xx.s - - - $PROJ_DIR$\board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - - - - finsh - - $PROJ_DIR$\..\..\..\components\finsh\cmd.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh_cmd.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh_file.c - - - $PROJ_DIR$\..\..\..\components\finsh\shell.c - - - $PROJ_DIR$\..\..\..\components\finsh\symbol.c - - - - Kernel - - $PROJ_DIR$\..\..\..\src\clock.c - - - $PROJ_DIR$\..\..\..\src\components.c - - - $PROJ_DIR$\..\..\..\src\cpu.c - - - $PROJ_DIR$\..\..\..\src\device.c - - - $PROJ_DIR$\..\..\..\src\idle.c - - - $PROJ_DIR$\..\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\..\src\irq.c - - - $PROJ_DIR$\..\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\..\src\mem.c - - - $PROJ_DIR$\..\..\..\src\memheap.c - - - $PROJ_DIR$\..\..\..\src\object.c - - - $PROJ_DIR$\..\..\..\src\scheduler.c - - - $PROJ_DIR$\..\..\..\src\signal.c - - - $PROJ_DIR$\..\..\..\src\thread.c - - - $PROJ_DIR$\..\..\..\src\timer.c - - - - libc - - $PROJ_DIR$\..\..\..\components\libc\compilers\common\gmtime_r.c - - - - STM32_HAL - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c - - - diff --git a/bsp/stm32/stm32l4r5-st-nucleo/project.uvoptx b/bsp/stm32/stm32l4r5-st-nucleo/project.uvoptx index 4c989e2d13..e3575cbfe8 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/project.uvoptx +++ b/bsp/stm32/stm32l4r5-st-nucleo/project.uvoptx @@ -103,7 +103,7 @@ 1 0 0 - 6 + 0 @@ -114,23 +114,18 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\UL2CM3.DLL - - 0 - ST-LINKIII-KEIL_SWO - -U066EFF495056867767053013 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) - 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4Rx_2048_Dual -FL0200000 -FS08000000 -FP0($$Device:STM32L4R5ZITx$CMSIS\Flash\STM32L4Rx_2048_Dual.FLM) 0 - JL2CM3 - -U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + ST-LINKIII-KEIL_SWO + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4Rx_2048_Dual -FL0200000 -FS08000000 -FP0($$Device:STM32L4R5ZITx$CMSIS\Flash\STM32L4Rx_2048_Dual.FLM) @@ -178,6 +173,7 @@ 1 + 0 0 2 10000000 diff --git a/bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx b/bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx index fba8b6cb9d..a21983548d 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx +++ b/bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx @@ -11,16 +11,16 @@ 0 - STM32L475VETx + STM32L4R5ZITx STMicroelectronics - Keil.STM32L4xx_DFP.2.0.0 - http://www.keil.com/pack - IRAM(0x20000000,0x00018000) IRAM2(0x10000000,0x00008000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x000A0000) IROM(0x08000000,0x00200000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4Rx_2048_Dual -FS08000000 -FL0200000 -FP0($$Device:STM32L4R5ZITx$CMSIS\Flash\STM32L4Rx_2048_Dual.FLM)) 0 - $$Device:STM32L475VETx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + $$Device:STM32L4R5ZITx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h @@ -30,7 +30,7 @@ - $$Device:STM32L475VETx$CMSIS\SVD\STM32L4x5.svd + $$Device:STM32L4R5ZITx$CMSIS\SVD\STM32L4R5.svd 0 0 @@ -135,7 +135,7 @@ 1 BIN\UL2CM3.DLL - "" () + @@ -181,7 +181,8 @@ 0 0 2 - 1 + 0 + 0 0 8 0 @@ -189,7 +190,7 @@ 0 0 3 - 4 + 3 0 0 0 @@ -241,12 +242,12 @@ 0 0x20000000 - 0x18000 + 0xa0000 1 0x8000000 - 0x80000 + 0x200000 0 @@ -271,7 +272,7 @@ 1 0x8000000 - 0x80000 + 0x200000 1 @@ -296,12 +297,12 @@ 0 0x20000000 - 0x18000 + 0xa0000 0 - 0x10000000 - 0x8000 + 0x0 + 0x0 @@ -332,9 +333,9 @@ 0 - STM32L4R5xx, USE_HAL_DRIVER, RT_USING_ARM_LIBC + STM32L4R5xx, USE_HAL_DRIVER - .;..\..\..\include;.;applications;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include @@ -375,114 +376,6 @@ - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - - - components.c - 1 - ..\..\..\src\components.c - - - - - cpu.c - 1 - ..\..\..\src\cpu.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - - - idle.c - 1 - ..\..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\..\src\mem.c - - - - - memheap.c - 1 - ..\..\..\src\memheap.c - - - - - object.c - 1 - ..\..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - - - signal.c - 1 - ..\..\..\src\signal.c - - - - - thread.c - 1 - ..\..\..\src\thread.c - - - - - timer.c - 1 - ..\..\..\src\timer.c - - - Applications @@ -493,51 +386,6 @@ - - Drivers - - - board.c - 1 - board\board.c - - - - - stm32l4xx_hal_msp.c - 1 - board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - - - - - startup_stm32l4r5xx.s - 2 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l4r5xx.s - - - - - drv_gpio.c - 1 - ..\libraries\HAL_Drivers\drv_gpio.c - - - - - drv_usart.c - 1 - ..\libraries\HAL_Drivers\drv_usart.c - - - - - drv_common.c - 1 - ..\libraries\HAL_Drivers\drv_common.c - - - cpu @@ -642,6 +490,51 @@ + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32l4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + + + + + startup_stm32l4r5xx.s + 2 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l4r5xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + finsh @@ -651,13 +544,6 @@ ..\..\..\components\finsh\shell.c - - - symbol.c - 1 - ..\..\..\components\finsh\symbol.c - - cmd.c @@ -672,56 +558,105 @@ ..\..\..\components\finsh\msh.c - - - msh_cmd.c - 1 - ..\..\..\components\finsh\msh_cmd.c - - - - - msh_file.c - 1 - ..\..\..\components\finsh\msh_file.c - - - libc + Kernel - libc.c + clock.c 1 - ..\..\..\components\libc\compilers\armlibc\libc.c + ..\..\..\src\clock.c - mem_std.c + components.c 1 - ..\..\..\components\libc\compilers\armlibc\mem_std.c + ..\..\..\src\components.c - stubs.c + device.c 1 - ..\..\..\components\libc\compilers\armlibc\stubs.c + ..\..\..\src\device.c - time.c + idle.c 1 - ..\..\..\components\libc\compilers\armlibc\time.c + ..\..\..\src\idle.c - gmtime_r.c + ipc.c 1 - ..\..\..\components\libc\compilers\common\gmtime_r.c + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c diff --git a/bsp/stm32/stm32l4r5-st-nucleo/template.uvoptx b/bsp/stm32/stm32l4r5-st-nucleo/template.uvoptx index 4c989e2d13..e3575cbfe8 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/template.uvoptx +++ b/bsp/stm32/stm32l4r5-st-nucleo/template.uvoptx @@ -103,7 +103,7 @@ 1 0 0 - 6 + 0 @@ -114,23 +114,18 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\UL2CM3.DLL - - 0 - ST-LINKIII-KEIL_SWO - -U066EFF495056867767053013 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) - 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4Rx_2048_Dual -FL0200000 -FS08000000 -FP0($$Device:STM32L4R5ZITx$CMSIS\Flash\STM32L4Rx_2048_Dual.FLM) 0 - JL2CM3 - -U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM) + ST-LINKIII-KEIL_SWO + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4Rx_2048_Dual -FL0200000 -FS08000000 -FP0($$Device:STM32L4R5ZITx$CMSIS\Flash\STM32L4Rx_2048_Dual.FLM) @@ -178,6 +173,7 @@ 1 + 0 0 2 10000000 diff --git a/bsp/stm32/stm32l4r5-st-nucleo/template.uvprojx b/bsp/stm32/stm32l4r5-st-nucleo/template.uvprojx index 246542fb09..f86483f1f1 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/template.uvprojx +++ b/bsp/stm32/stm32l4r5-st-nucleo/template.uvprojx @@ -14,16 +14,16 @@ 0 - STM32L475VETx + STM32L4R5ZITx STMicroelectronics - Keil.STM32L4xx_DFP.2.0.0 - http://www.keil.com/pack - IRAM(0x20000000,0x00018000) IRAM2(0x10000000,0x00008000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ + IRAM(0x20000000,0x000A0000) IROM(0x08000000,0x00200000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4Rx_2048_Dual -FS08000000 -FL0200000 -FP0($$Device:STM32L4R5ZITx$CMSIS\Flash\STM32L4Rx_2048_Dual.FLM)) 0 - $$Device:STM32L475VETx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h + $$Device:STM32L4R5ZITx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h @@ -33,7 +33,7 @@ - $$Device:STM32L475VETx$CMSIS\SVD\STM32L4x5.svd + $$Device:STM32L4R5ZITx$CMSIS\SVD\STM32L4R5.svd 0 0 @@ -138,7 +138,7 @@ 1 BIN\UL2CM3.DLL - "" () + @@ -184,7 +184,8 @@ 0 0 2 - 1 + 0 + 0 0 8 0 @@ -192,7 +193,7 @@ 0 0 3 - 4 + 3 0 0 0 @@ -244,12 +245,12 @@ 0 0x20000000 - 0x18000 + 0xa0000 1 0x8000000 - 0x80000 + 0x200000 0 @@ -274,7 +275,7 @@ 1 0x8000000 - 0x80000 + 0x200000 1 @@ -299,12 +300,12 @@ 0 0x20000000 - 0x18000 + 0xa0000 0 - 0x10000000 - 0x8000 + 0x0 + 0x0 diff --git a/bsp/stm32/stm32l4r9-st-eval/project.uvoptx b/bsp/stm32/stm32l4r9-st-eval/project.uvoptx index a792b963fc..ca63bbdf5f 100644 --- a/bsp/stm32/stm32l4r9-st-eval/project.uvoptx +++ b/bsp/stm32/stm32l4r9-st-eval/project.uvoptx @@ -73,7 +73,7 @@ 0 - 1 + 0 0 1 @@ -173,6 +173,7 @@ 1 + 0 0 2 10000000 @@ -181,875 +182,11 @@ - Kernel + Source Group 1 0 0 0 0 - - 1 - 1 - 1 - 0 - 0 - 0 - ..\..\..\src\clock.c - clock.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - ..\..\..\src\components.c - components.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - ..\..\..\src\cpu.c - cpu.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - ..\..\..\src\device.c - device.c - 0 - 0 - - - 1 - 5 - 1 - 0 - 0 - 0 - ..\..\..\src\idle.c - idle.c - 0 - 0 - - - 1 - 6 - 1 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - 0 - 0 - - - 1 - 7 - 1 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - 0 - 0 - - - 1 - 8 - 1 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - 0 - 0 - - - 1 - 9 - 1 - 0 - 0 - 0 - ..\..\..\src\memheap.c - memheap.c - 0 - 0 - - - 1 - 10 - 1 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - 0 - 0 - - - 1 - 11 - 1 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - 0 - 0 - - - 1 - 12 - 1 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 1 - 13 - 1 - 0 - 0 - 0 - ..\..\..\src\signal.c - signal.c - 0 - 0 - - - 1 - 14 - 1 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - 0 - 0 - - - 1 - 15 - 1 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c - 0 - 0 - - - - - Applications - 0 - 0 - 0 - 0 - - 2 - 16 - 1 - 0 - 0 - 0 - applications\main.c - main.c - 0 - 0 - - - - - Drivers - 0 - 0 - 0 - 0 - - 3 - 17 - 1 - 0 - 0 - 0 - board\board.c - board.c - 0 - 0 - - - 3 - 18 - 1 - 0 - 0 - 0 - board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - stm32l4xx_hal_msp.c - 0 - 0 - - - 3 - 19 - 2 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l4r9xx.s - startup_stm32l4r9xx.s - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_gpio.c - drv_gpio.c - 0 - 0 - - - 3 - 21 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_usart.c - drv_usart.c - 0 - 0 - - - 3 - 22 - 1 - 0 - 0 - 0 - ..\libraries\HAL_Drivers\drv_common.c - drv_common.c - 0 - 0 - - - - - cpu - 0 - 0 - 0 - 0 - - 4 - 23 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c - 0 - 0 - - - 4 - 24 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\div0.c - div0.c - 0 - 0 - - - 4 - 25 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\common\showmem.c - showmem.c - 0 - 0 - - - 4 - 26 - 1 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c - cpuport.c - 0 - 0 - - - 4 - 27 - 2 - 0 - 0 - 0 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - context_rvds.S - 0 - 0 - - - - - DeviceDrivers - 0 - 0 - 0 - 0 - - 5 - 28 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c_core.c - i2c_core.c - 0 - 0 - - - 5 - 29 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c_dev.c - i2c_dev.c - 0 - 0 - - - 5 - 30 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - i2c-bit-ops.c - 0 - 0 - - - 5 - 31 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\misc\pin.c - pin.c - 0 - 0 - - - 5 - 32 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\serial\serial.c - serial.c - 0 - 0 - - - 5 - 33 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\completion.c - completion.c - 0 - 0 - - - 5 - 34 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\dataqueue.c - dataqueue.c - 0 - 0 - - - 5 - 35 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\pipe.c - pipe.c - 0 - 0 - - - 5 - 36 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringblk_buf.c - ringblk_buf.c - 0 - 0 - - - 5 - 37 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\ringbuffer.c - ringbuffer.c - 0 - 0 - - - 5 - 38 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\waitqueue.c - waitqueue.c - 0 - 0 - - - 5 - 39 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\src\workqueue.c - workqueue.c - 0 - 0 - - - - - finsh - 0 - 0 - 0 - 0 - - 6 - 40 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\shell.c - shell.c - 0 - 0 - - - 6 - 41 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\symbol.c - symbol.c - 0 - 0 - - - 6 - 42 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\cmd.c - cmd.c - 0 - 0 - - - 6 - 43 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\msh.c - msh.c - 0 - 0 - - - 6 - 44 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\msh_cmd.c - msh_cmd.c - 0 - 0 - - - 6 - 45 - 1 - 0 - 0 - 0 - ..\..\..\components\finsh\msh_file.c - msh_file.c - 0 - 0 - - - - - STM32_HAL - 0 - 0 - 0 - 0 - - 7 - 46 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c - system_stm32l4xx.c - 0 - 0 - - - 7 - 47 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c - stm32l4xx_hal.c - 0 - 0 - - - 7 - 48 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c - stm32l4xx_hal_comp.c - 0 - 0 - - - 7 - 49 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - stm32l4xx_hal_cortex.c - 0 - 0 - - - 7 - 50 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c - stm32l4xx_hal_crc.c - 0 - 0 - - - 7 - 51 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - stm32l4xx_hal_crc_ex.c - 0 - 0 - - - 7 - 52 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c - stm32l4xx_hal_cryp.c - 0 - 0 - - - 7 - 53 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c - stm32l4xx_hal_cryp_ex.c - 0 - 0 - - - 7 - 54 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - stm32l4xx_hal_dma.c - 0 - 0 - - - 7 - 55 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c - stm32l4xx_hal_dma_ex.c - 0 - 0 - - - 7 - 56 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c - stm32l4xx_hal_exti.c - 0 - 0 - - - 7 - 57 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - stm32l4xx_hal_pwr.c - 0 - 0 - - - 7 - 58 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - stm32l4xx_hal_pwr_ex.c - 0 - 0 - - - 7 - 59 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - stm32l4xx_hal_rcc.c - 0 - 0 - - - 7 - 60 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - stm32l4xx_hal_rcc_ex.c - 0 - 0 - - - 7 - 61 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - stm32l4xx_hal_rng.c - 0 - 0 - - - 7 - 62 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - stm32l4xx_hal_gpio.c - 0 - 0 - - - 7 - 63 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - stm32l4xx_hal_uart.c - 0 - 0 - - - 7 - 64 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - stm32l4xx_hal_uart_ex.c - 0 - 0 - - - 7 - 65 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c - stm32l4xx_hal_usart.c - 0 - 0 - - - 7 - 66 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c - stm32l4xx_hal_usart_ex.c - 0 - 0 - - - 7 - 67 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c - stm32l4xx_hal_i2c.c - 0 - 0 - - - 7 - 68 - 1 - 0 - 0 - 0 - ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c - stm32l4xx_hal_i2c_ex.c - 0 - 0 - diff --git a/bsp/stm32/stm32l4r9-st-eval/project.uvprojx b/bsp/stm32/stm32l4r9-st-eval/project.uvprojx index 7cc8eb590c..6476709703 100644 --- a/bsp/stm32/stm32l4r9-st-eval/project.uvprojx +++ b/bsp/stm32/stm32l4r9-st-eval/project.uvprojx @@ -1,10 +1,7 @@ - 2.1 -
### uVision Project, (C) Keil Software
- rt-thread @@ -19,28 +16,28 @@ Keil.STM32L4xx_DFP.2.0.0 http://www.keil.com/pack IRAM(0x20000000,0x000A0000) IROM(0x08000000,0x00200000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4Rx_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32L4R9AIIx$CMSIS\Flash\STM32L4Rx_2048.FLM)) 0 $$Device:STM32L4R9AIIx$Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h - - - - - - - - - + + + + + + + + + $$Device:STM32L4R9AIIx$CMSIS\SVD\STM32L4R9.svd 0 0 - - - - - + + + + + 0 0 @@ -62,8 +59,8 @@ 0 0 - - + + 0 0 0 @@ -72,8 +69,8 @@ 0 0 - - + + 0 0 0 @@ -83,14 +80,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -104,8 +101,8 @@ 0 0 3 - - + + 1 @@ -138,11 +135,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -175,7 +172,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -184,6 +181,7 @@ 0 0 2 + 0 0 0 8 @@ -307,7 +305,7 @@ 0x0 - + 1 @@ -334,10 +332,10 @@ 0 0 - + USE_HAL_DRIVER, STM32L4R9xx - - .;..\..\..\include;applications;board;board\CubeMX_Config\Inc;board\ports\include;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include + + applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports\include;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include @@ -352,10 +350,10 @@ 0 0 - - - - + + + + @@ -367,97 +365,17 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - components.c - 1 - ..\..\..\src\components.c - - - cpu.c - 1 - ..\..\..\src\cpu.c - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c - 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - irq.c - 1 - ..\..\..\src\irq.c - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - memheap.c - 1 - ..\..\..\src\memheap.c - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - object.c - 1 - ..\..\..\src\object.c - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - signal.c - 1 - ..\..\..\src\signal.c - - - thread.c - 1 - ..\..\..\src\thread.c - - - timer.c - 1 - ..\..\..\src\timer.c - - - Applications @@ -468,41 +386,6 @@ - - Drivers - - - board.c - 1 - board\board.c - - - stm32l4xx_hal_msp.c - 1 - board\CubeMX_Config\Src\stm32l4xx_hal_msp.c - - - startup_stm32l4r9xx.s - 2 - ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l4r9xx.s - - - drv_gpio.c - 1 - ..\libraries\HAL_Drivers\drv_gpio.c - - - drv_usart.c - 1 - ..\libraries\HAL_Drivers\drv_usart.c - - - drv_common.c - 1 - ..\libraries\HAL_Drivers\drv_common.c - - - cpu @@ -511,21 +394,29 @@ 1 ..\..\..\libcpu\arm\common\backtrace.c + + div0.c 1 ..\..\..\libcpu\arm\common\div0.c + + showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c + + cpuport.c 1 ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + context_rvds.S 2 @@ -541,56 +432,78 @@ 1 ..\..\..\components\drivers\i2c\i2c_core.c + + i2c_dev.c 1 ..\..\..\components\drivers\i2c\i2c_dev.c + + i2c-bit-ops.c 1 ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + pin.c 1 ..\..\..\components\drivers\misc\pin.c + + serial.c 1 ..\..\..\components\drivers\serial\serial.c + + completion.c 1 ..\..\..\components\drivers\src\completion.c + + dataqueue.c 1 ..\..\..\components\drivers\src\dataqueue.c + + pipe.c 1 ..\..\..\components\drivers\src\pipe.c + + ringblk_buf.c 1 ..\..\..\components\drivers\src\ringblk_buf.c + + ringbuffer.c 1 ..\..\..\components\drivers\src\ringbuffer.c + + waitqueue.c 1 ..\..\..\components\drivers\src\waitqueue.c + + workqueue.c 1 @@ -598,6 +511,51 @@ + + Drivers + + + board.c + 1 + board\board.c + + + + + stm32l4xx_hal_msp.c + 1 + board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + + + + + startup_stm32l4r9xx.s + 2 + ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l4r9xx.s + + + + + drv_gpio.c + 1 + ..\libraries\HAL_Drivers\drv_gpio.c + + + + + drv_usart.c + 1 + ..\libraries\HAL_Drivers\drv_usart.c + + + + + drv_common.c + 1 + ..\libraries\HAL_Drivers\drv_common.c + + + finsh @@ -606,30 +564,120 @@ 1 ..\..\..\components\finsh\shell.c - - symbol.c - 1 - ..\..\..\components\finsh\symbol.c - + + cmd.c 1 ..\..\..\components\finsh\cmd.c + + msh.c 1 ..\..\..\components\finsh\msh.c + + + + Kernel + - msh_cmd.c + clock.c 1 - ..\..\..\components\finsh\msh_cmd.c + ..\..\..\src\clock.c + + - msh_file.c + components.c 1 - ..\..\..\components\finsh\msh_file.c + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c @@ -641,111 +689,155 @@ 1 ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c + + stm32l4xx_hal.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + stm32l4xx_hal_comp.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + + stm32l4xx_hal_cortex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + + stm32l4xx_hal_crc.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c + + stm32l4xx_hal_crc_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c + + stm32l4xx_hal_cryp.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c + + stm32l4xx_hal_cryp_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c + + stm32l4xx_hal_dma.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + stm32l4xx_hal_dma_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + stm32l4xx_hal_exti.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + + stm32l4xx_hal_pwr.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + stm32l4xx_hal_pwr_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + stm32l4xx_hal_rcc.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + + stm32l4xx_hal_rcc_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + stm32l4xx_hal_rng.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c + + stm32l4xx_hal_gpio.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + stm32l4xx_hal_uart.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + + stm32l4xx_hal_uart_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + + stm32l4xx_hal_usart.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c + + stm32l4xx_hal_usart_ex.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c + + stm32l4xx_hal_i2c.c 1 ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c + + stm32l4xx_hal_i2c_ex.c 1 @@ -756,11 +848,9 @@ - - - - + + + - diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig index 6f8ee6d865..2ea8df97ab 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig +++ b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig @@ -35,9 +35,24 @@ menu "Onboard Peripheral Drivers" config BSP_USING_OPENAMP bool "Enable OpenAMP" - select RT_USING_OPENAMP default n + menuconfig BSP_USING_RS485 + bool "Enable RS485 " + default n + if BSP_USING_RS485 + comment "set rts pin number " + config BSP_RS485_RTS_PIN + int "RS485 rts pin number" + range 1 176 + default 5 + + config RS485_UART_DEVICE_NAME + string "the uart name for rs485" + default "uart3" + + endif + endmenu menu "On-chip Peripheral Drivers" @@ -59,12 +74,10 @@ menu "On-chip Peripheral Drivers" config BSP_USING_UART3 bool "Enable UART3" default y - config BSP_UART3_RX_USING_DMA bool "Enable UART3 RX DMA" - depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA default n - config BSP_UART3_TX_USING_DMA bool "Enable UART3 TX DMA" depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA @@ -73,12 +86,10 @@ menu "On-chip Peripheral Drivers" config BSP_USING_UART4 bool "Enable UART4" default y - config BSP_UART4_RX_USING_DMA bool "Enable UART4 RX DMA" depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA default n - config BSP_UART4_TX_USING_DMA bool "Enable UART4 TX DMA" depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/SConscript b/bsp/stm32/stm32mp157a-st-discovery/board/SConscript index 305b3e60d4..a99f95d786 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/SConscript +++ b/bsp/stm32/stm32mp157a-st-discovery/board/SConscript @@ -37,6 +37,9 @@ if GetDepend(['BSP_USING_TIM14']): if GetDepend(['BSP_USING_PMIC']): src += Glob('ports/drv_pmic.c') +if GetDepend(['BSP_USING_RS485']): + src += Glob('ports/drv_rs485.c') + if GetDepend(['BSP_USING_OPENAMP']): src += Glob('CubeMX_Config/CM4/Src/ipcc.c') src += Glob('CubeMX_Config/CM4/Src/openamp.c') diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.c index 58e1c95f39..12651efa1a 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/drv_openamp.c @@ -12,6 +12,7 @@ #ifdef BSP_USING_OPENAMP +#include #include #include #include @@ -234,6 +235,11 @@ int rt_hw_openamp_init(void) openamp_init(); rt_hw_openamp_register(&dev_openamp, "openamp", 0, NULL); + + if (RT_CONSOLE_DEVICE_NAME == "openamp") + { + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + } return RT_EOK; } diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c index a4924fced1..8c6f45ad91 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c @@ -9,6 +9,7 @@ */ #include "board.h" + //#define DRV_DEBUG #define LOG_TAG "drv.rcc" #include @@ -17,12 +18,12 @@ static void enable_clock(void) { - __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); } static void disable_clock(void) { - __HAL_RCC_GPIOD_CLK_DISABLE(); + __HAL_RCC_GPIOH_CLK_DISABLE(); } static int rcc_sample(int argc, char *argv[]) @@ -47,8 +48,8 @@ static int rcc_sample(int argc, char *argv[]) _exit: { rt_kprintf("Usage:\n"); - rt_kprintf("rcc_sample enable - enable GPIOD clock, the LD8 will blink '\n"); - rt_kprintf("rcc_sample disable - disable GPIOD clock, the LD8 will stop blink'\n"); + rt_kprintf("rcc_sample enable - enable GPIOH clock, the LD7 will blink '\n"); + rt_kprintf("rcc_sample disable - disable GPIOH clock, the LD7 will stop blink'\n"); } return -RT_ERROR; diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c new file mode 100644 index 0000000000..44eba3be91 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-24 thread-liu first version + */ + +#include +#include "drv_rs485.h" + +#ifdef BSP_USING_RS485 + +#define RS485_OUT rt_pin_write(BSP_RS485_RTS_PIN, PIN_HIGH) +#define RS485_IN rt_pin_write(BSP_RS485_RTS_PIN, PIN_LOW) + +static rt_device_t serial = {0}; +static struct rt_semaphore rx_sem = {0}; + +/* uart send data callback function */ +static rt_err_t rs485_output(rt_device_t dev, void * buffer) +{ + return RT_EOK; +} + +/* uart receive data callback function */ +static rt_err_t rs485_input(rt_device_t dev, rt_size_t size) +{ + rt_sem_release(&rx_sem); + + return RT_EOK; +} + +/* send string */ +int rs485_send_data(char *tbuf, rt_uint16_t t_len) +{ + /* change rs485 mode */ + RS485_OUT; + + /* send data */ + rt_device_write(serial, 0, tbuf, t_len); + + /* change rs485 mode */ + RS485_IN; + + return RT_EOK; +} + +static void rs485_thread_entry(void *parameter) +{ + char ch; + + while (1) + { + /* A byte of data is read from a serial port, and if it is not read, it waits for the received semaphore */ + while (rt_device_read(serial, -1, &ch, 1) != 1) + { + rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + } + + /* The data read through the serial port output dislocation */ + ch = ch + 1; + + /* send char */ + rs485_send_data(&ch, 1); + } +} + +/* rs485 rts pin init */ +static int rs485_init(void) +{ + /* find uart device */ + serial = rt_device_find(RS485_UART_DEVICE_NAME); + if (!serial) + { + rt_kprintf("find %s failed!\n", RS485_UART_DEVICE_NAME); + return RT_ERROR; + } + + rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); + + /* set receive data callback function */ + rt_device_set_rx_indicate(serial, rs485_input); + + /* set the send completion callback function */ + rt_device_set_tx_complete(serial, rs485_output); + + rt_pin_mode(BSP_RS485_RTS_PIN, PIN_MODE_OUTPUT); + + RS485_IN; + + rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + /* create rs485 thread */ + rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL, 1024, 25, 10); + + if (thread != RT_NULL) + { + rt_thread_startup(thread); + } + else + { + return RT_ERROR; + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rs485_init); + +#endif /* bsp_using_RS485 */ diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h new file mode 100644 index 0000000000..01edf84ae8 --- /dev/null +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-24 thread-liu first version + */ + +#ifndef __DRV_RS485_H__ +#define __DRV_RS485_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define RS485_SEND_MODE 0 +#define RS485_RECV_MODE 1 + +#ifdef __cplusplus +} +#endif + +#endif /* drv_rs485.h */ diff --git a/bsp/stm32/stm32wb55-st-nucleo/.config b/bsp/stm32/stm32wb55-st-nucleo/.config index 6f880b4b87..fefa10fef8 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/.config +++ b/bsp/stm32/stm32wb55-st-nucleo/.config @@ -65,7 +65,7 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x40003 CONFIG_ARCH_ARM=y CONFIG_RT_USING_CPU_FFS=y @@ -108,18 +108,7 @@ CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system # -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -# CONFIG_RT_USING_DFS_ELMFAT is not set -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS is not set # # Device Drivers @@ -164,11 +153,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_USING_POSIX=y -# CONFIG_RT_USING_POSIX_MMAP is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_GETLINE is not set -# CONFIG_RT_USING_POSIX_AIO is not set + # CONFIG_RT_USING_MODULE is not set # diff --git a/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds index b4936af7aa..fb39eb5783 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32wb55-st-nucleo/board/linker_scripts/link.lds @@ -5,7 +5,7 @@ /* Program Entry, set to mark it as "used" and avoid gc */ MEMORY { - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024 /* 1024KB flash */ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ RAM (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */ } ENTRY(Reset_Handler) @@ -153,4 +153,10 @@ SECTIONS .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } + + .ARM.attributes 0 : { *(.ARM.attributes) } + MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED + MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED + MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED + } diff --git a/bsp/stm32/stm32wb55-st-nucleo/project.ewp b/bsp/stm32/stm32wb55-st-nucleo/project.ewp index 268f4f0e33..c1935c48f5 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/project.ewp +++ b/bsp/stm32/stm32wb55-st-nucleo/project.ewp @@ -215,7 +215,9 @@ + + cpu + + $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S + + + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c + + + + dlib + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\libc.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\rmtx.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\stdio.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + Drivers $PROJ_DIR$\board\board.c - $PROJ_DIR$\board\CubeMX_Config\Src\stm32l4xx_hal_msp.c + $PROJ_DIR$\board\CubeMX_Config\Src\stm32wbxx_hal_msp.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\iar\startup_stm32l475xx.s + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\CMSIS\Device\ST\STM32WBxx\Source\Templates\iar\startup_stm32wb55xx_cm4.s $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c @@ -2086,6 +2184,75 @@ $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c + + Filesystem + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\poll.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\select.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs\devfs.c + + + + finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_file.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\..\components\finsh\finsh_token.c + + Kernel @@ -2132,366 +2299,78 @@ - CORTEX-M4 + libc - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\cpuport.c + $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4\context_iar.S - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c - - - $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c - - - - DeviceDrivers - - $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c - - - $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\completion.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c - - - $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c - - - - finsh - - $PROJ_DIR$\..\..\..\components\finsh\shell.c - - - $PROJ_DIR$\..\..\..\components\finsh\symbol.c - - - $PROJ_DIR$\..\..\..\components\finsh\cmd.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh_cmd.c - - - $PROJ_DIR$\..\..\..\components\finsh\msh_file.c + $PROJ_DIR$\..\..\..\components\libc\compilers\common\unistd.c STM32_HAL - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\CMSIS\Device\ST\STM32WBxx\Source\Templates\system_stm32wbxx.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_comp.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_cortex.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_can.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_crc.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_crc_ex.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_cryp.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_cryp_ex.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_dma.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_dma_ex.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_exti.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_pwr.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_pwr_ex.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dcmi.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_rcc.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dfsdm.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_rcc_ex.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dfsdm_ex.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_rng.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_gpio.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma2d.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_uart.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_uart_ex.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dsi.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_usart.c - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_firewall.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gfxmmu.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_hash.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_hash_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_hcd.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_irda.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_lcd.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_lptim.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_ltdc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_ltdc_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_nand.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_nor.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_opamp.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_opamp_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_ospi.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_qspi.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sai.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sai_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_smartcard.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_smartcard_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_smbus.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sram.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_swpmi.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tsc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_wwdg.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_adc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_comp.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_crc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_crs.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dac.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma2d.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_exti.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_fmc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_gpio.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_i2c.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_lptim.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_lpuart.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_opamp.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_pwr.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rcc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rng.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rtc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_spi.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_swpmi.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_tim.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usart.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usb.c - - - $PROJ_DIR$\..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_utils.c + $PROJ_DIR$\..\libraries\STM32WBxx_HAL\STM32WBxx_HAL_Driver\Src\STM32wbxx_hal_usart_ex.c diff --git a/bsp/stm32/stm32wb55-st-nucleo/rtconfig.h b/bsp/stm32/stm32wb55-st-nucleo/rtconfig.h index 7ba6a2581b..c21b1c4357 100644 --- a/bsp/stm32/stm32wb55-st-nucleo/rtconfig.h +++ b/bsp/stm32/stm32wb55-st-nucleo/rtconfig.h @@ -40,7 +40,7 @@ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x40003 #define ARCH_ARM #define RT_USING_CPU_FFS @@ -74,12 +74,6 @@ /* Device virtual file system */ -#define RT_USING_DFS -#define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 -#define DFS_FD_MAX 16 -#define RT_USING_DFS_DEVFS /* Device Drivers */ @@ -96,7 +90,7 @@ /* POSIX layer and C standard library */ #define RT_USING_LIBC -#define RT_USING_POSIX + /* Network */ diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 457b8751fe..db4455160e 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -103,6 +103,10 @@ if RT_USING_I2C endif endif +config RT_USING_PHY + bool "Using ethernet phy device drivers" + default n + config RT_USING_PIN bool "Using generic GPIO device drivers" default y diff --git a/components/drivers/include/drivers/alarm.h b/components/drivers/include/drivers/alarm.h index b5ebbc86d9..dd59f4c1e8 100644 --- a/components/drivers/include/drivers/alarm.h +++ b/components/drivers/include/drivers/alarm.h @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2012-10-27 heyuanjie87 first version. + * 2013-05-17 aozima initial alarm event & mutex in system init. + * 2020-10-15 zhangsz add alarm flags hour minute second. */ #ifndef __ALARM_H__ @@ -22,6 +24,9 @@ #define RT_ALARM_WEEKLY 0x200 /* alarm weekly at Monday or Friday etc. */ #define RT_ALARM_MONTHLY 0x400 /* alarm monthly at someday */ #define RT_ALARM_YAERLY 0x800 /* alarm yearly at a certain date */ +#define RT_ALARM_HOUR 0x1000 /* alarm each hour at a certain min:second */ +#define RT_ALARM_MINUTE 0x2000 /* alarm each minute at a certain second */ +#define RT_ALARM_SECOND 0x4000 /* alarm each second */ /* alarm control cmd */ #define RT_ALARM_CTRL_MODIFY 1 /* modify alarm time or alarm flag */ @@ -67,6 +72,6 @@ void rt_alarm_update(rt_device_t dev, rt_uint32_t event); rt_err_t rt_alarm_delete(rt_alarm_t alarm); rt_err_t rt_alarm_start(rt_alarm_t alarm); rt_err_t rt_alarm_stop(rt_alarm_t alarm); -void rt_alarm_system_init(void); +int rt_alarm_system_init(void); #endif /* __ALARM_H__ */ diff --git a/components/drivers/include/drivers/phy.h b/components/drivers/include/drivers/phy.h new file mode 100644 index 0000000000..2d1ad9f91f --- /dev/null +++ b/components/drivers/include/drivers/phy.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-14 wangqiang the first version + */ + +#ifndef __PHY_H__ +#define __PHY_H__ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Defines the PHY link speed. This is align with the speed for MAC. */ +enum phy_speed +{ + PHY_SPEED_10M = 0U, /* PHY 10M speed. */ + PHY_SPEED_100M /* PHY 100M speed. */ +}; + +/* Defines the PHY link duplex. */ +enum phy_duplex +{ + PHY_HALF_DUPLEX = 0U, /* PHY half duplex. */ + PHY_FULL_DUPLEX /* PHY full duplex. */ +}; + +/*! @brief Defines the PHY loopback mode. */ +enum phy_loop +{ + PHY_LOCAL_LOOP = 0U, /* PHY local loopback. */ + PHY_REMOTE_LOOP /* PHY remote loopback. */ +}; + + +struct rt_phy_msg +{ + rt_uint32_t reg; + rt_uint32_t value; +}; + +typedef struct rt_phy_msg rt_phy_msg_t; + + +struct rt_phy_device +{ + struct rt_device parent; + struct rt_mdio_bus *bus; + rt_uint32_t addr; + struct rt_phy_ops *ops; +}; + +typedef struct rt_phy_device rt_phy_t; + + +enum { + PHY_STATUS_OK = 0, + PHY_STATUS_FAIL, + PHY_STATUS_TIMEOUT, +}; + +typedef rt_int32_t rt_phy_status; + +struct rt_phy_ops +{ + rt_phy_status (*init)(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz); + rt_phy_status (*read)(rt_uint32_t reg, rt_uint32_t *data); + rt_phy_status (*write)(rt_uint32_t reg, rt_uint32_t data); + rt_phy_status (*loopback)(rt_uint32_t mode, rt_uint32_t speed, rt_bool_t enable); + rt_phy_status (*get_link_status)(rt_bool_t *status); + rt_phy_status (*get_link_speed_duplex)(rt_uint32_t *speed, rt_uint32_t *duplex); +}; + +rt_err_t rt_hw_phy_register(struct rt_phy_device *phy, const char *name); + +#ifdef __cplusplus +} +#endif + +#endif /* __PHY_H__*/ diff --git a/components/drivers/include/drivers/phy_mdio.h b/components/drivers/include/drivers/phy_mdio.h new file mode 100644 index 0000000000..d978ec2984 --- /dev/null +++ b/components/drivers/include/drivers/phy_mdio.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-14 wangqiang the first version + */ + +#ifndef __MDIO_H__ +#define __MDIO_H__ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +struct rt_mdio_bus_ops +{ + rt_bool_t (*init)(void *bus, rt_uint32_t src_clock_hz); + rt_size_t (*read)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size); + rt_size_t (*write)(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size); + rt_bool_t (*uninit)(void *bus); +}; + +struct rt_mdio_bus +{ + void *hw_obj; + char *name; + struct rt_mdio_bus_ops *ops; +}; + +typedef struct rt_mdio_bus rt_mdio_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index f54290097c..f0fa2f5b4a 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -69,6 +69,11 @@ extern "C" { #endif /* RT_USING_I2C_BITOPS */ #endif /* RT_USING_I2C */ +#ifdef RT_USING_PHY +#include "drivers/phy.h" +#include "drivers/phy_mdio.h" +#endif /* RT_USING_PHY */ + #ifdef RT_USING_SDIO #include "drivers/mmcsd_core.h" #include "drivers/sd.h" diff --git a/components/drivers/phy/SConscript b/components/drivers/phy/SConscript new file mode 100644 index 0000000000..ec12ed24c2 --- /dev/null +++ b/components/drivers/phy/SConscript @@ -0,0 +1,8 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd + '/../include'] +group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_PHY'], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/drivers/phy/phy.c b/components/drivers/phy/phy.c new file mode 100644 index 0000000000..3ed4a1a265 --- /dev/null +++ b/components/drivers/phy/phy.c @@ -0,0 +1,78 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-09-27 wangqiang first version + */ + +#include +#include +#include + +#define DBG_TAG "PHY" +#define DBG_LVL DBG_INFO +#include + + +static rt_size_t phy_device_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t count) +{ + struct rt_phy_device *phy = (struct rt_phy_device *)dev->user_data; + struct rt_phy_msg *msg = (struct rt_phy_msg *)buffer; + return phy->bus->ops->read(phy->bus, phy->addr, msg->reg, &(msg->value), 4); +} +static rt_size_t phy_device_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t count) +{ + struct rt_phy_device *phy = (struct rt_phy_device *)dev->user_data; + struct rt_phy_msg *msg = (struct rt_phy_msg *)buffer; + return phy->bus->ops->write(phy->bus, phy->addr, msg->reg, &(msg->value), 4); +} + + + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops phy_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + phy_device_read, + phy_device_write, + RT_NULL, +}; +#endif + +/* +* phy device register +*/ +rt_err_t rt_hw_phy_register(struct rt_phy_device *phy, const char *name) +{ + rt_err_t ret; + struct rt_device *device; + + device = &(phy->parent); + + device->type = RT_Device_Class_PHY; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + device->ops = phy_ops; +#else + device->init = NULL; + device->open = NULL; + device->close = NULL; + device->read = phy_device_read; + device->write = phy_device_write; + device->control = NULL; +#endif + device->user_data = phy; + + /* register a character device */ + ret = rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); + + return ret; +} diff --git a/components/drivers/rtc/alarm.c b/components/drivers/rtc/alarm.c index c497ebf727..71b6e7236a 100644 --- a/components/drivers/rtc/alarm.c +++ b/components/drivers/rtc/alarm.c @@ -7,6 +7,7 @@ * Date Author Notes * 2012-10-27 heyuanjie87 first version. * 2013-05-17 aozima initial alarm event & mutex in system init. + * 2020-10-15 zhangsz add alarm flags hour minute second. */ #include @@ -97,6 +98,61 @@ static void alarm_wakeup(struct rt_alarm *alarm, struct tm *now) } } break; + case RT_ALARM_SECOND: + { + alarm->wktime.tm_hour = now->tm_hour; + alarm->wktime.tm_min = now->tm_min; + alarm->wktime.tm_sec = alarm->wktime.tm_sec + 1; + if (alarm->wktime.tm_sec > 59) + { + alarm->wktime.tm_sec = 0; + alarm->wktime.tm_min = alarm->wktime.tm_min + 1; + if (alarm->wktime.tm_min > 59) + { + alarm->wktime.tm_min = 0; + alarm->wktime.tm_hour = alarm->wktime.tm_hour + 1; + if (alarm->wktime.tm_hour > 23) + { + alarm->wktime.tm_hour = 0; + } + } + } + wakeup = RT_TRUE; + } + break; + case RT_ALARM_MINUTE: + { + alarm->wktime.tm_hour = now->tm_hour; + if (alarm->wktime.tm_sec == now->tm_sec) + { + alarm->wktime.tm_min = alarm->wktime.tm_min + 1; + if (alarm->wktime.tm_min > 59) + { + alarm->wktime.tm_min = 0; + alarm->wktime.tm_hour = alarm->wktime.tm_hour + 1; + if (alarm->wktime.tm_hour > 23) + { + alarm->wktime.tm_hour = 0; + } + } + wakeup = RT_TRUE; + } + } + break; + case RT_ALARM_HOUR: + { + if ((alarm->wktime.tm_min == now->tm_min) && + (alarm->wktime.tm_sec == now->tm_sec)) + { + alarm->wktime.tm_hour = alarm->wktime.tm_hour + 1; + if (alarm->wktime.tm_hour > 23) + { + alarm->wktime.tm_hour = 0; + } + wakeup = RT_TRUE; + } + } + break; case RT_ALARM_DAILY: { if (((sec_now - sec_alarm) <= RT_ALARM_DELAY) && (sec_now >= sec_alarm)) @@ -177,7 +233,7 @@ static void alarm_update(rt_uint32_t event) /* calculate seconds from 00:00:00 */ sec_alarm = alarm_mkdaysec(&alarm->wktime); - if ((alarm->flag & RT_ALARM_STATE_START) && (alarm != _container.current)) + if (alarm->flag & RT_ALARM_STATE_START) { sec_tmp = sec_alarm - sec_now; if (sec_tmp > 0) @@ -212,6 +268,11 @@ static void alarm_update(rt_uint32_t event) if (alarm_set(alm_prev) == RT_EOK) _container.current = alm_prev; } + else + { + if (_container.current != RT_NULL) + alarm_set(_container.current); + } } rt_mutex_release(&_container.mutex); } @@ -279,6 +340,51 @@ static rt_err_t alarm_setup(rt_alarm_t alarm, struct tm *wktime) switch (alarm->flag & 0xFF00) { + case RT_ALARM_SECOND: + { + alarm->wktime.tm_hour = now.tm_hour; + alarm->wktime.tm_min = now.tm_min; + alarm->wktime.tm_sec = now.tm_sec + 1; + if (alarm->wktime.tm_sec > 59) + { + alarm->wktime.tm_sec = 0; + alarm->wktime.tm_min = alarm->wktime.tm_min + 1; + if (alarm->wktime.tm_min > 59) + { + alarm->wktime.tm_min = 0; + alarm->wktime.tm_hour = alarm->wktime.tm_hour + 1; + if (alarm->wktime.tm_hour > 23) + { + alarm->wktime.tm_hour = 0; + } + } + } + } + break; + case RT_ALARM_MINUTE: + { + alarm->wktime.tm_hour = now.tm_hour; + alarm->wktime.tm_min = now.tm_min + 1; + if (alarm->wktime.tm_min > 59) + { + alarm->wktime.tm_min = 0; + alarm->wktime.tm_hour = alarm->wktime.tm_hour + 1; + if (alarm->wktime.tm_hour > 23) + { + alarm->wktime.tm_hour = 0; + } + } + } + break; + case RT_ALARM_HOUR: + { + alarm->wktime.tm_hour = now.tm_hour + 1; + if (alarm->wktime.tm_hour > 23) + { + alarm->wktime.tm_hour = 0; + } + } + break; case RT_ALARM_DAILY: { /* do nothing but needed */ @@ -426,17 +532,17 @@ rt_err_t rt_alarm_start(rt_alarm_t alarm) if (alarm == RT_NULL) return (ret); rt_mutex_take(&_container.mutex, RT_WAITING_FOREVER); - if (!(alarm->flag & RT_ALARM_STATE_INITED)) + + if (!(alarm->flag & RT_ALARM_STATE_START)) { if (alarm_setup(alarm, &alarm->wktime) != RT_EOK) goto _exit; - } - if ((alarm->flag & 0x01) == RT_ALARM_STATE_STOP) - { + timestamp = time(RT_NULL); localtime_r(×tamp, &now); alarm->flag |= RT_ALARM_STATE_START; + /* set alarm */ if (_container.current == RT_NULL) { @@ -518,10 +624,10 @@ _exit: */ rt_err_t rt_alarm_delete(rt_alarm_t alarm) { - rt_err_t ret = RT_ERROR; + rt_err_t ret = RT_EOK; if (alarm == RT_NULL) - return (ret); + return RT_ERROR; rt_mutex_take(&_container.mutex, RT_WAITING_FOREVER); /* stop the alarm */ alarm->flag &= ~RT_ALARM_STATE_START; @@ -551,9 +657,11 @@ rt_alarm_t rt_alarm_create(rt_alarm_callback_t callback, struct rt_alarm_setup * if (setup == RT_NULL) return (RT_NULL); + alarm = rt_malloc(sizeof(struct rt_alarm)); if (alarm == RT_NULL) return (RT_NULL); + rt_list_init(&alarm->list); alarm->wktime = setup->wktime; @@ -586,13 +694,33 @@ static void rt_alarmsvc_thread_init(void *param) } } +void rt_alarm_dump(void) +{ + rt_list_t *next; + rt_alarm_t alarm; + rt_uint8_t index = 0; + + rt_kprintf("| alarm_id | YYYY-MM-DD hh:mm:ss | weekday | flags |\n"); + rt_kprintf("+----------+---------------------+---------+---------+\n"); + for (next = _container.head.next; next != &_container.head; next = next->next) + { + alarm = rt_list_entry(next, struct rt_alarm, list); + rt_kprintf("| No %5d | %04d-%02d-%02d %02d:%02d:%02d | %7d | 0x%04x |\n", + index++, alarm->wktime.tm_year + 1900, alarm->wktime.tm_mon + 1, alarm->wktime.tm_mday, + alarm->wktime.tm_hour, alarm->wktime.tm_min, alarm->wktime.tm_sec, + alarm->wktime.tm_wday, alarm->flag); + } + rt_kprintf("+----------+---------------------+---------+---------+\n"); +} + +FINSH_FUNCTION_EXPORT_ALIAS(rt_alarm_dump, __cmd_alarm_dump, dump alarm info); /** \brief initialize alarm service system * * \param none * \return none */ -void rt_alarm_system_init(void) +int rt_alarm_system_init(void) { rt_thread_t tid; @@ -602,8 +730,12 @@ void rt_alarm_system_init(void) tid = rt_thread_create("alarmsvc", rt_alarmsvc_thread_init, RT_NULL, - 512, 8, 1); + 2048, 10, 5); if (tid != RT_NULL) rt_thread_startup(tid); + + return 0; } + +INIT_PREV_EXPORT(rt_alarm_system_init); #endif diff --git a/components/drivers/usb/usbhost/class/udisk.c b/components/drivers/usb/usbhost/class/udisk.c index 1509a26105..6c8030b29a 100644 --- a/components/drivers/usb/usbhost/class/udisk.c +++ b/components/drivers/usb/usbhost/class/udisk.c @@ -186,7 +186,7 @@ rt_err_t rt_udisk_run(struct uhintf* intf) { int i = 0; rt_err_t ret; - char dname[4]; + char dname[8]; char sname[8]; rt_uint8_t max_lun, *sector, sense[18], inquiry[36]; struct dfs_partition part[MAX_PARTITION_COUNT]; diff --git a/components/drivers/usb/usbhost/core/hub.c b/components/drivers/usb/usbhost/core/hub.c index fb6cd9c406..eefa571472 100644 --- a/components/drivers/usb/usbhost/core/hub.c +++ b/components/drivers/usb/usbhost/core/hub.c @@ -417,8 +417,13 @@ static rt_err_t rt_usbh_hub_port_change(uhub_t hub) if(reconnect) { - if(hub->child[i] != RT_NULL && hub->child[i]->status != DEV_STATUS_IDLE) + if(hub->child[i] != RT_NULL && hub->child[i]->status != DEV_STATUS_IDLE) + { rt_usbh_detach_instance(hub->child[i]); + + /* Child device have been detach. Set hub->child[i] to NULL. */ + hub->child[i] = RT_NULL; + } ret = rt_usbh_hub_port_debounce(hub, i + 1); if(ret != RT_EOK) continue; @@ -532,7 +537,12 @@ static rt_err_t rt_usbh_hub_enable(void *arg) } /* get hub ports number */ - hub->num_ports = hub->hub_desc.num_ports; + /* If hub device supported ports over USB_HUB_PORT_NUM(Ex: 8 port hub). Set hub->num_ports to USB_HUB_PORT_NUM */ + if(hub->hub_desc.num_ports > USB_HUB_PORT_NUM) + hub->num_ports = USB_HUB_PORT_NUM; + else + hub->num_ports = hub->hub_desc.num_ports; + hub->hcd = device->hcd; hub->self = device; @@ -607,7 +617,6 @@ static rt_err_t rt_usbh_hub_disable(void* arg) } if(hub != RT_NULL) rt_free(hub); - if(intf != RT_NULL) rt_free(intf); return RT_EOK; } diff --git a/components/finsh/cmd.c b/components/finsh/cmd.c index d764ea4231..afbda59e90 100644 --- a/components/finsh/cmd.c +++ b/components/finsh/cmd.c @@ -821,6 +821,7 @@ static char *const device_type_str[] = "Miscellaneous Device", "Sensor Device", "Touch Device", + "Phy Device", "Unknown" }; diff --git a/components/libc/compilers/armlibc/README.md b/components/libc/compilers/armlibc/README.md new file mode 100644 index 0000000000..4d2a73b6be --- /dev/null +++ b/components/libc/compilers/armlibc/README.md @@ -0,0 +1,9 @@ +# ARMLIB (Keil-MDK) porting for RT-Thread + +Please define RT_USING_LIBC and compile RT-Thread with Keil-MDK compiler. + + + +## More Information + +https://www.keil.com/support/man/docs/armlib/ \ No newline at end of file diff --git a/components/libc/compilers/common/readme.md b/components/libc/compilers/common/readme.md index 0cd56272ff..99797d933c 100644 --- a/components/libc/compilers/common/readme.md +++ b/components/libc/compilers/common/readme.md @@ -1,4 +1,4 @@ -# Attention : +## Attentions 1. This folder is "common" for armlibc newlibc and dlib. It's not "common" for minilibc. diff --git a/components/libc/compilers/dlib/README.md b/components/libc/compilers/dlib/README.md index 846eb3f5c0..acd08f9074 100644 --- a/components/libc/compilers/dlib/README.md +++ b/components/libc/compilers/dlib/README.md @@ -1,4 +1,9 @@ -Dlib(IAR) porting for RT-Thread. +# DLIB (IAR) porting for RT-Thread Please define RT_USING_LIBC and compile RT-Thread with IAR compiler. + + +## More Information + +http://www.iarsys.co.jp/download/LMS2/arm/7502/ewarm7502doc/arm/doc/EWARM_DevelopmentGuide.ENU.pdf P.130 \ No newline at end of file diff --git a/components/libc/compilers/newlib/README.md b/components/libc/compilers/newlib/README.md new file mode 100644 index 0000000000..385f329a4f --- /dev/null +++ b/components/libc/compilers/newlib/README.md @@ -0,0 +1,9 @@ +# NEWLIB (GCC) porting for RT-Thread + +Please define RT_USING_LIBC and compile RT-Thread with GCC compiler. + + + +## More Information + +https://sourceware.org/newlib/libc.html#Reentrancy \ No newline at end of file diff --git a/components/net/at/src/at_client.c b/components/net/at/src/at_client.c index ba4009738d..788549392d 100644 --- a/components/net/at/src/at_client.c +++ b/components/net/at/src/at_client.c @@ -917,6 +917,11 @@ int at_client_init(const char *dev_name, rt_size_t recv_bufsz) RT_ASSERT(dev_name); RT_ASSERT(recv_bufsz > 0); + if (at_client_get(dev_name) != RT_NULL) + { + return result; + } + for (idx = 0; idx < AT_CLIENT_NUM_MAX && at_client_table[idx].device; idx++); if (idx >= AT_CLIENT_NUM_MAX) diff --git a/include/rtdef.h b/include/rtdef.h index 0690371c6d..e4ddbd37d3 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -871,6 +871,7 @@ enum rt_device_class_type RT_Device_Class_Miscellaneous, /**< Miscellaneous device */ RT_Device_Class_Sensor, /**< Sensor device */ RT_Device_Class_Touch, /**< Touch device */ + RT_Device_Class_PHY, /**< PHY device */ RT_Device_Class_Unknown /**< unknown device */ }; diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index 5055b533e6..dece8b0423 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -10,7 +10,7 @@ group = [] list = os.listdir(cwd) # add common code files -if rtconfig.VENDOR == "t-head" : +if rtconfig.CPU == "e906" : group = group elif rtconfig.CPU == "nuclei" : group = group @@ -18,7 +18,7 @@ else : group = group + SConscript(os.path.join(cwd, 'common', 'SConscript')) # cpu porting code files -if rtconfig.VENDOR == "t-head" : +if rtconfig.CPU == "e906" : group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript')) else : group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript')) diff --git a/src/kservice.c b/src/kservice.c index 7caf43ce28..0a74f05268 100644 --- a/src/kservice.c +++ b/src/kservice.c @@ -1116,7 +1116,7 @@ RTM_EXPORT(rt_console_get_device); * * @param name the name of new console device * - * @return the old console device handler + * @return the old console device handler on successful, or RT_NULL on failure. */ rt_device_t rt_console_set_device(const char *name) { @@ -1127,6 +1127,10 @@ rt_device_t rt_console_set_device(const char *name) /* find new console device */ new_device = rt_device_find(name); + + /* check whether it's a same device */ + if (new_device == old_device) return RT_NULL; + if (new_device != RT_NULL) { if (_console_device != RT_NULL) diff --git a/src/memheap.c b/src/memheap.c index aef56e1a74..0ff6925696 100644 --- a/src/memheap.c +++ b/src/memheap.c @@ -126,8 +126,8 @@ rt_err_t rt_memheap_detach(struct rt_memheap *heap) RT_ASSERT(heap); RT_ASSERT(rt_object_get_type(&heap->parent) == RT_Object_Class_MemHeap); RT_ASSERT(rt_object_is_systemobject(&heap->parent)); - - rt_object_detach(&(heap->lock.parent.parent)); + + rt_sem_detach(&heap->lock); rt_object_detach(&(heap->parent)); /* Return a successful completion. */